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-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 6;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_ok_4_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_ok_4_e-c.vhd,v 1.1 2006/11/22 10:40:10 wig Exp $
-- $Date: 2006/11/22 10:40:10 $
-- $Log: inst_shadow_ok_4_e-c.vhd,v $
-- Revision 1.1 2006/11/22 10:40:10 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_ok_4_rtl_conf / inst_shadow_ok_4_e
--
configuration inst_shadow_ok_4_rtl_conf of inst_shadow_ok_4_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_ok_4_rtl_conf;
--
-- End of Generated Configuration inst_shadow_ok_4_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY InterfaceWithVHDLUnconstrainedArrayImportedType2 IS
GENERIC(
SIZE_X : INTEGER := 3
);
PORT(
din_0 : IN UNSIGNED(7 DOWNTO 0);
din_1 : IN UNSIGNED(7 DOWNTO 0);
din_2 : IN UNSIGNED(7 DOWNTO 0);
dout : OUT mem(0 TO 3)(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF InterfaceWithVHDLUnconstrainedArrayImportedType2 IS
BEGIN
dout(0) <= din_0;
dout(1) <= din_1;
dout(2) <= din_2;
ASSERT SIZE_X = 3 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity U232C_RECV is
generic (
WTIME : std_logic_vector(15 downto 0) := x"1B17");
port (
CLK : in std_logic;
OK : in std_logic;
RX : in std_logic;
DATA : out std_logic_vector (7 downto 0);
RECVED : out std_logic);
end U232C_RECV;
architecture blackbox of U232C_RECV is
signal countdown : std_logic_vector(15 downto 0);
signal recvbuf : std_logic_vector(8 downto 0) := (others => '0');
signal state : integer range 0 to 11 := 11;
signal sig_recved : std_logic := '0';
begin
RECVED <= sig_recved;
recvbuf(8) <= RX;
statemachine : process(CLK)
begin
if rising_edge(CLK) then
case state is
when 11 =>
if recvbuf(8) = '1' then
-- read start bit at half of wtime
countdown <= "0"&WTIME(15 downto 1);
state <= 10;
end if;
when 10 =>
if recvbuf(8) = '0' then
if countdown = 0 then
countdown <= WTIME;
state <= state-1;
else
countdown <= countdown-1;
end if;
else
countdown <= "0"&WTIME(15 downto 1);
end if;
when 1 =>
if countdown = 0 then
if recvbuf(8) = '1' then
sig_recved <= '1';
state <= 0;
else
state <= 11;
end if;
else
countdown <= countdown-1;
end if;
when 0 =>
if OK = '1' then
DATA <= recvbuf(7 downto 0);
sig_recved <= '0';
state <= 11;
end if;
when others =>
if countdown = 0 then
recvbuf(7 downto 0) <= recvbuf(8 downto 1);
countdown <= WTIME;
state <= state-1;
else
countdown <= countdown-1;
end if;
end case;
end if;
end process;
end blackbox;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2439.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02439ent IS
END c07s03b02x02p01n01i02439ent;
ARCHITECTURE c07s03b02x02p01n01i02439arch OF c07s03b02x02p01n01i02439ent IS
BEGIN
TESTING: PROCESS
-- Range types are all predefined enumerated types.
type CHAR_ARR is ARRAY( CHARACTER ) of BIT;
type BIT_ARR is ARRAY( BIT ) of BIT;
type BOOL_ARR is ARRAY( BOOLEAN ) of BIT;
type SEV_ARR is ARRAY( SEVERITY_LEVEL ) of BIT;
-- Declare variables of these types.
variable CHARV : CHAR_ARR;
variable BITV : BIT_ARR;
variable BOOLV : BOOL_ARR;
variable SEVV : SEV_ARR;
variable OKtest: integer := 0;
BEGIN
-- Assign each of these arrays using aggregates.
-- 1. Individual aggregates.
CHARV := CHAR_ARR'( 'a' => '1', 'b' => '0', NUL to '`' => '1',
'c' to character'high => '1' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( '0' => '0', '1' => '1' );
assert( BITV( '0' ) = '0' );
if NOT( BITV( '0' ) = '0' ) then
OKtest := 1;
end if;
assert( BITV( '1' ) = '1' );
if NOT( BITV( '1' ) = '1' ) then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE => '0', TRUE => '1' );
assert( BOOLV( FALSE ) = '0' );
if NOT( BOOLV( FALSE ) = '0' ) then
OKtest := 1;
end if;
assert( BOOLV( TRUE ) = '1' );
if NOT( BOOLV( TRUE ) = '1' ) then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE => '0', WARNING => '1', ERROR => '0',
FAILURE => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
-- 2. Groups of aggregates.
CHARV := CHAR_ARR'( 'a' | 'b' => '1', NUL to '`' => '0',
'c' to character'high => '0' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( '0' | '1' => '0' );
assert( BITV( '0' ) = '0' );
assert( BITV( '1' ) = '0' );
if NOT((BITV('0')='0') and (BITV('1')='0')) then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE | TRUE => '1' );
assert( BOOLV( FALSE ) = '1' );
assert( BOOLV( TRUE ) = '1' );
if NOT((BOOLV(FALSE)='1') and (BOOLV(TRUE)='1')) then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE | ERROR => '0', WARNING | FAILURE => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
-- 3. Use of 'others' in these aggregates.
CHARV := CHAR_ARR'( 'a' | 'b' => '0', others => '1' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( others => '1' );
assert( BITV( '0' ) = '1' );
assert( BITV( '1' ) = '1' );
if NOT(( BITV( '0' ) = '1' )and( BITV( '1' ) = '1' ))then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE => '1', others => '0' );
assert( BOOLV( FALSE ) = '1' );
assert( BOOLV( TRUE ) = '0' );
if NOT(( BOOLV( FALSE ) = '1' )and( BOOLV( TRUE ) = '0' ))then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE | ERROR => '0', others => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
wait for 5 ns;
assert NOT(OKtest = 0)
report "***PASSED TEST: c07s03b02x02p01n01i02439"
severity NOTE;
assert (OKtest = 0)
report "***FAILED TEST: c07s03b02x02p01n01i02439 - Aggregates with different range types test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02439arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2439.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02439ent IS
END c07s03b02x02p01n01i02439ent;
ARCHITECTURE c07s03b02x02p01n01i02439arch OF c07s03b02x02p01n01i02439ent IS
BEGIN
TESTING: PROCESS
-- Range types are all predefined enumerated types.
type CHAR_ARR is ARRAY( CHARACTER ) of BIT;
type BIT_ARR is ARRAY( BIT ) of BIT;
type BOOL_ARR is ARRAY( BOOLEAN ) of BIT;
type SEV_ARR is ARRAY( SEVERITY_LEVEL ) of BIT;
-- Declare variables of these types.
variable CHARV : CHAR_ARR;
variable BITV : BIT_ARR;
variable BOOLV : BOOL_ARR;
variable SEVV : SEV_ARR;
variable OKtest: integer := 0;
BEGIN
-- Assign each of these arrays using aggregates.
-- 1. Individual aggregates.
CHARV := CHAR_ARR'( 'a' => '1', 'b' => '0', NUL to '`' => '1',
'c' to character'high => '1' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( '0' => '0', '1' => '1' );
assert( BITV( '0' ) = '0' );
if NOT( BITV( '0' ) = '0' ) then
OKtest := 1;
end if;
assert( BITV( '1' ) = '1' );
if NOT( BITV( '1' ) = '1' ) then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE => '0', TRUE => '1' );
assert( BOOLV( FALSE ) = '0' );
if NOT( BOOLV( FALSE ) = '0' ) then
OKtest := 1;
end if;
assert( BOOLV( TRUE ) = '1' );
if NOT( BOOLV( TRUE ) = '1' ) then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE => '0', WARNING => '1', ERROR => '0',
FAILURE => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
-- 2. Groups of aggregates.
CHARV := CHAR_ARR'( 'a' | 'b' => '1', NUL to '`' => '0',
'c' to character'high => '0' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( '0' | '1' => '0' );
assert( BITV( '0' ) = '0' );
assert( BITV( '1' ) = '0' );
if NOT((BITV('0')='0') and (BITV('1')='0')) then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE | TRUE => '1' );
assert( BOOLV( FALSE ) = '1' );
assert( BOOLV( TRUE ) = '1' );
if NOT((BOOLV(FALSE)='1') and (BOOLV(TRUE)='1')) then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE | ERROR => '0', WARNING | FAILURE => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
-- 3. Use of 'others' in these aggregates.
CHARV := CHAR_ARR'( 'a' | 'b' => '0', others => '1' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( others => '1' );
assert( BITV( '0' ) = '1' );
assert( BITV( '1' ) = '1' );
if NOT(( BITV( '0' ) = '1' )and( BITV( '1' ) = '1' ))then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE => '1', others => '0' );
assert( BOOLV( FALSE ) = '1' );
assert( BOOLV( TRUE ) = '0' );
if NOT(( BOOLV( FALSE ) = '1' )and( BOOLV( TRUE ) = '0' ))then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE | ERROR => '0', others => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
wait for 5 ns;
assert NOT(OKtest = 0)
report "***PASSED TEST: c07s03b02x02p01n01i02439"
severity NOTE;
assert (OKtest = 0)
report "***FAILED TEST: c07s03b02x02p01n01i02439 - Aggregates with different range types test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02439arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2439.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02439ent IS
END c07s03b02x02p01n01i02439ent;
ARCHITECTURE c07s03b02x02p01n01i02439arch OF c07s03b02x02p01n01i02439ent IS
BEGIN
TESTING: PROCESS
-- Range types are all predefined enumerated types.
type CHAR_ARR is ARRAY( CHARACTER ) of BIT;
type BIT_ARR is ARRAY( BIT ) of BIT;
type BOOL_ARR is ARRAY( BOOLEAN ) of BIT;
type SEV_ARR is ARRAY( SEVERITY_LEVEL ) of BIT;
-- Declare variables of these types.
variable CHARV : CHAR_ARR;
variable BITV : BIT_ARR;
variable BOOLV : BOOL_ARR;
variable SEVV : SEV_ARR;
variable OKtest: integer := 0;
BEGIN
-- Assign each of these arrays using aggregates.
-- 1. Individual aggregates.
CHARV := CHAR_ARR'( 'a' => '1', 'b' => '0', NUL to '`' => '1',
'c' to character'high => '1' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( '0' => '0', '1' => '1' );
assert( BITV( '0' ) = '0' );
if NOT( BITV( '0' ) = '0' ) then
OKtest := 1;
end if;
assert( BITV( '1' ) = '1' );
if NOT( BITV( '1' ) = '1' ) then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE => '0', TRUE => '1' );
assert( BOOLV( FALSE ) = '0' );
if NOT( BOOLV( FALSE ) = '0' ) then
OKtest := 1;
end if;
assert( BOOLV( TRUE ) = '1' );
if NOT( BOOLV( TRUE ) = '1' ) then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE => '0', WARNING => '1', ERROR => '0',
FAILURE => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
-- 2. Groups of aggregates.
CHARV := CHAR_ARR'( 'a' | 'b' => '1', NUL to '`' => '0',
'c' to character'high => '0' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( '0' | '1' => '0' );
assert( BITV( '0' ) = '0' );
assert( BITV( '1' ) = '0' );
if NOT((BITV('0')='0') and (BITV('1')='0')) then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE | TRUE => '1' );
assert( BOOLV( FALSE ) = '1' );
assert( BOOLV( TRUE ) = '1' );
if NOT((BOOLV(FALSE)='1') and (BOOLV(TRUE)='1')) then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE | ERROR => '0', WARNING | FAILURE => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
-- 3. Use of 'others' in these aggregates.
CHARV := CHAR_ARR'( 'a' | 'b' => '0', others => '1' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( others => '1' );
assert( BITV( '0' ) = '1' );
assert( BITV( '1' ) = '1' );
if NOT(( BITV( '0' ) = '1' )and( BITV( '1' ) = '1' ))then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE => '1', others => '0' );
assert( BOOLV( FALSE ) = '1' );
assert( BOOLV( TRUE ) = '0' );
if NOT(( BOOLV( FALSE ) = '1' )and( BOOLV( TRUE ) = '0' ))then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE | ERROR => '0', others => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
wait for 5 ns;
assert NOT(OKtest = 0)
report "***PASSED TEST: c07s03b02x02p01n01i02439"
severity NOTE;
assert (OKtest = 0)
report "***FAILED TEST: c07s03b02x02p01n01i02439 - Aggregates with different range types test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02439arch;
|
-- Copyright (c) 2017 Stephan Nolting / IMS, Leibniz Univ. Hannover
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-- Title : Generic shift and round unit; simulation model without
-- UNISIM components
-------------------------------------------------------------------------------
-- File : generic_sru.vhd
-- Author : Stephan Nolting
-- Company : Leibniz Univ. Hannover
-- Created : 2018-02-06
-- Last update: 2018-06-18
-------------------------------------------------------------------------------
-- Description: Generic shift unit providing logical left shift, logical right
-- shift & arithmetical right shift. Up to 4 pipeline registers can be inserted
-- into the data path. See the according generic's comments for further
-- information. The more pipeline registers are activated, the more the unit's
-- latency is increased.
--
-- If you use this design in your work, please cite the following publication:
-- Payá-Vayá, Guillermo, Roman Burg, and Holger Blume.
-- "Dynamic data-path self-reconfiguration of a VLIW-SIMD soft-processor
-- architecture."
-- Workshop on Self-Awareness in Reconfigurable Computing Systems, SRCS. 2012.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-02-06 1.0 nolting Created
-- 2018-06-11 1.1 tervoa Added MIT License, reformatted header
-- 2018-06-18 1.2 tervoa Reformat due to FUGen limitations
-- 2018-06-18 1.2 tervoa Simulation model without UNISIM components
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library UNISIM;
-- use UNISIM.vcomponents.all;
entity generic_sru is
generic (
DATA_WIDTH : natural := 32; -- data width (power of 2)
EN_ROUNDING : boolean := false; -- enable hw for rounding to zero/infinity
-- pipeline stages --
EN_INPUT_REG : boolean := false; -- enable input registers
EN_SHIFT_REG : boolean := false; -- enable shifter output register
EN_ROUND_REG : boolean := false; -- enable rounding unit shift register
EN_OUT_REG : boolean := false -- enable output register
);
port (
-- global control --
clk : in std_logic;
-- operand data --
opa_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
opb_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- operation control --
shift_dir_i : in std_logic; -- 0: right, 1: left (shift dreiction)
arith_shift_i : in std_logic; -- 0: logical, 1: arithmetical (only for right shifts)
rnd_en_i : in std_logic; -- 0: rounding disabled, 1: rounding enabled
rnd_mode_i : in std_logic; -- 0: floor, 1: infinity (type of rounding)
-- operation result --
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end generic_sru;
architecture generic_sru_xv6_rtl of generic_sru is
-- muxcy xilinx primitive component (carry chain multiplexer) --
component muxcy
port (
o : out std_logic;
ci : in std_logic;
di : in std_logic;
s : in std_logic
);
end component;
-- xorcy xilinx primitive component (carry chain 'adder') --
component xorcy
port (
o : out std_logic;
ci : in std_logic;
li : in std_logic
);
end component;
-- local types --
type smask_array_t is array(0 to DATA_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- Function: Minimum required bit width --
function index_size(input : natural) return natural is
begin
for i in 0 to natural'high loop
if (2**i >= input) then
return i;
end if;
end loop; -- i
return 0;
end function index_size;
-- Function: init mask for shifter's sign bit cancellation mask --
function init_smask(n: natural) return smask_array_t is
variable smask_array_v : smask_array_t;
begin
smask_array_v := (others => (others => '0'));
smask_array_v(0) := (others => '1');
for i in 0 to n-2 loop
smask_array_v(i+1) := '0' & (smask_array_v(i)(n-1 downto 1));
end loop; -- i
return smask_array_v;
end function init_smask;
-- Function: Bit reversal --
function bit_reversal(input : std_logic_vector) return std_logic_vector is
variable output_v : std_logic_vector(input'range);
begin
for i in 0 to input'length-1 loop
output_v(input'length-i-1) := input(i);
end loop; -- i
return output_v;
end function bit_reversal;
-- internal configuration --
constant log2_data_width_c : natural := index_size(DATA_WIDTH);
constant subword_c : natural := 0;
-- pipeline stage 0 (input register) --
signal opa_s0, opa_ff0 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal opb_s0, opb_ff0 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal shift_dir_s0, shift_dir_ff0 : std_logic;
signal shift_arith_s0, shift_arith_ff0 : std_logic;
signal rnd_en_s0, rnd_en_ff0 : std_logic;
signal rnd_mode_s0, rnd_mode_ff0 : std_logic;
-- shifter core --
constant smask_array : smask_array_t := init_smask(DATA_WIDTH);
signal sra_data : std_logic_vector(DATA_WIDTH-1 downto 0);
signal sra_mask : std_logic_vector(DATA_WIDTH-1 downto 0);
signal shift_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal shift_res : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_sel : std_logic;
-- pipeline stage 1 --
signal sra_data_s1, sra_data_ff1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal sra_mask_s1, sra_mask_ff1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_s1, carry_ff1 : std_logic;
signal shift_dir_s1, shift_dir_ff1 : std_logic;
signal shift_arith_s1, shift_arith_ff1 : std_logic;
signal rnd_en_s1, rnd_en_ff1 : std_logic;
signal rnd_mode_s1, rnd_mode_ff1 : std_logic;
-- rounding unit --
signal inc_chain : std_logic_vector(DATA_WIDTH downto 0);
signal inc_data : std_logic_vector(DATA_WIDTH-1 downto 0);
signal inc_result : std_logic_vector(DATA_WIDTH-1 downto 0);
-- pipeline stage 2 --
signal inc_res_s2, inc_res_ff2 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_s2, carry_ff2 : std_logic;
-- zero detector --
signal nibble_is_zero : std_logic_vector((DATA_WIDTH/4)-1 downto 0);
signal zero_chain : std_logic_vector((DATA_WIDTH/4) downto 0);
-- pipeline stage 3: output register --
signal inc_res_s3, inc_res_ff3 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_s3, carry_ff3 : std_logic;
signal zero_s3, zero_ff3 : std_logic;
-- zero overflow carry negative
signal z_flag_o, o_flag_o, c_flag_o, n_flag_o : std_logic;
begin
-- Pipeline Stage 0: Input Register -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s0: process(clk)
begin
if rising_edge(clk) then
opa_ff0 <= opa_i;
opb_ff0 <= opb_i;
shift_dir_ff0 <= shift_dir_i;
shift_arith_ff0 <= arith_shift_i;
rnd_en_ff0 <= rnd_en_i;
rnd_mode_ff0 <= rnd_mode_i;
end if;
end process pipe_s0;
-- use input registers? --
opa_s0 <= opa_ff0 when (EN_INPUT_REG = true) else opa_i;
opb_s0 <= opb_ff0 when (EN_INPUT_REG = true) else opb_i;
shift_dir_s0 <= shift_dir_ff0 when (EN_INPUT_REG = true) else shift_dir_i;
shift_arith_s0 <= shift_arith_ff0 when (EN_INPUT_REG = true) else arith_shift_i;
rnd_en_s0 <= rnd_en_ff0 when (EN_INPUT_REG = true) else rnd_en_i;
rnd_mode_s0 <= rnd_mode_ff0 when (EN_INPUT_REG = true) else rnd_mode_i;
-- Shifter Core ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
shift_in <= bit_reversal(opa_s0) when (shift_dir_s0 = '1') else opa_s0; -- reverse bits if left shift
shifter_core: process(opb_s0, shift_in)
variable carry_sel_v : std_logic_vector(DATA_WIDTH-1 downto 0);
variable positions_v : integer;
begin
-- all shift types are based on a single arithmetical right shifter
positions_v := to_integer(unsigned(opb_s0(log2_data_width_c-1 downto 0)));
sra_data <= std_logic_vector(shift_right(signed(shift_in), positions_v));
sra_mask <= smask_array(positions_v);
-- select carry --
carry_sel_v := shift_in(DATA_WIDTH-2 downto 0) & '0';
carry_sel <= carry_sel_v(positions_v);
end process shifter_core;
-- Pipeline Stage 1: Shifter output register ----------------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s1: process(clk)
begin
if rising_edge(clk) then
sra_data_ff1 <= sra_data;
sra_mask_ff1 <= sra_mask;
carry_ff1 <= carry_sel;
shift_dir_ff1 <= shift_dir_s0;
shift_arith_ff1 <= shift_arith_s0;
rnd_en_ff1 <= rnd_en_s0;
rnd_mode_ff1 <= rnd_mode_s0;
end if;
end process pipe_s1;
-- use pipeline 1 registers? --
sra_data_s1 <= sra_data_ff1 when (EN_SHIFT_REG = true) else sra_data;
sra_mask_s1 <= sra_mask_ff1 when (EN_SHIFT_REG = true) else sra_mask;
carry_s1 <= carry_ff1 when (EN_SHIFT_REG = true) else carry_sel;
shift_dir_s1 <= shift_dir_ff1 when (EN_SHIFT_REG = true) else shift_dir_s0;
shift_arith_s1 <= shift_arith_ff1 when (EN_SHIFT_REG = true) else shift_arith_s0;
rnd_en_s1 <= rnd_en_ff1 when (EN_SHIFT_REG = true) else rnd_en_s0;
rnd_mode_s1 <= rnd_mode_ff1 when (EN_SHIFT_REG = true) else rnd_mode_s0;
-- Shifter result masking ------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------
shifter_sel: process(shift_dir_s1, shift_arith_s1, sra_data_s1, sra_mask_s1)
variable lrs_v : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
lrs_v := sra_data_s1 and sra_mask_s1;
if (shift_dir_s1 = '1') then -- logical left shift
shift_res <= bit_reversal(lrs_v);
else -- right shift
if (shift_arith_s1 = '1') then -- arithmetical right shift
shift_res <= sra_data_s1;
else -- logical right shift
shift_res <= lrs_v;
end if;
end if;
end process shifter_sel;
-- Rounding --------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------
-- start of incrementer carry line with internal carry input
inc_chain(0) <= carry_s1 and (rnd_en_s1 and rnd_mode_s1);
-- simple incrementer, using dedicated hardware (muxcy, xorcy)
increment_unit:
for i in 0 to DATA_WIDTH-1 generate
-- inc_muxcy_inst: muxcy
-- port map (
-- o => inc_chain(i+1),
-- ci => inc_chain(i),
-- di => '0',
-- s => shift_res(i)
-- );
inc_chain(i+1) <= '0' when shift_res(i) = '0' else inc_chain(i);
-- inc_xorcy_inst: xorcy
-- port map (
-- o => inc_data(i),
-- ci => inc_chain(i),
-- li => shift_res(i)
-- );
inc_data(i) <= inc_chain(i) xor shift_res(i);
end generate; -- i
-- operation result output --
inc_result <= inc_data when (EN_ROUNDING = true) else shift_res;
-- Pipeline Stage 2: Rounding unit output register ----------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s2: process(clk)
begin
if rising_edge(clk) then
inc_res_ff2 <= inc_result;
carry_ff2 <= carry_s1;
end if;
end process pipe_s2;
-- use pipeline 2 registers? --
inc_res_s2 <= inc_res_ff2 when (EN_ROUND_REG = true) else inc_result;
carry_s2 <= carry_ff2 when (EN_ROUND_REG = true) else carry_s1;
-- Zero Detector --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
zero_chain(0) <= '1'; -- start a new subword chain
zero_detector:
for i in 0 to (DATA_WIDTH/4)-1 generate -- number of nibbles
-- zero detection for 4 bit -> 1 LUT + 1 MUXCY, propagate previous zero signal, when nibble is zero
nibble_is_zero(i) <= '1' when (inc_res_s2(i*4+3 downto i*4) = "0000") else '0'; -- is zero?
-- zero_detector_muxcy: muxcy
-- port map (
-- o => zero_chain(i+1), -- chain output signal
-- ci => zero_chain(i), -- s=1: chain input signal
-- di => '0', -- s=0: 0 input, nibble is not zero
-- s => nibble_is_zero(i) -- mux select input
-- );
zero_chain(i+1) <= '0' when nibble_is_zero(i) = '0' else zero_chain(i);
end generate; -- i
-- Pipeline Stage 3: Output register ------------------------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s3: process(clk)
begin
if rising_edge(clk) then
inc_res_ff3 <= inc_res_s2;
carry_ff3 <= carry_s2;
zero_ff3 <= zero_chain(DATA_WIDTH/4);
end if;
end process pipe_s3;
-- use pipeline 2 registers? --
inc_res_s3 <= inc_res_ff3 when (EN_OUT_REG = true) else inc_res_s2;
carry_s3 <= carry_ff3 when (EN_OUT_REG = true) else carry_s2;
zero_s3 <= zero_ff3 when (EN_OUT_REG = true) else zero_chain(DATA_WIDTH/4);
-- data output --
data_o <= inc_res_s3;
-- negative flag output --
n_flag_o <= inc_res_s3(DATA_WIDTH-1);
-- zero flag output --
z_flag_o <= zero_s3;
-- carry flag output --
c_flag_o <= carry_s3;
-- TODO: overflow:
-- all out-shifted bits should be equal to the sign, else overflow
-- for signed operations, also the result sign should be equal to the original sign
o_flag_o <= '0'; -- implement me!
end generic_sru_xv6_rtl;
|
-- Copyright (c) 2017 Stephan Nolting / IMS, Leibniz Univ. Hannover
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-- Title : Generic shift and round unit; simulation model without
-- UNISIM components
-------------------------------------------------------------------------------
-- File : generic_sru.vhd
-- Author : Stephan Nolting
-- Company : Leibniz Univ. Hannover
-- Created : 2018-02-06
-- Last update: 2018-06-18
-------------------------------------------------------------------------------
-- Description: Generic shift unit providing logical left shift, logical right
-- shift & arithmetical right shift. Up to 4 pipeline registers can be inserted
-- into the data path. See the according generic's comments for further
-- information. The more pipeline registers are activated, the more the unit's
-- latency is increased.
--
-- If you use this design in your work, please cite the following publication:
-- Payá-Vayá, Guillermo, Roman Burg, and Holger Blume.
-- "Dynamic data-path self-reconfiguration of a VLIW-SIMD soft-processor
-- architecture."
-- Workshop on Self-Awareness in Reconfigurable Computing Systems, SRCS. 2012.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-02-06 1.0 nolting Created
-- 2018-06-11 1.1 tervoa Added MIT License, reformatted header
-- 2018-06-18 1.2 tervoa Reformat due to FUGen limitations
-- 2018-06-18 1.2 tervoa Simulation model without UNISIM components
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library UNISIM;
-- use UNISIM.vcomponents.all;
entity generic_sru is
generic (
DATA_WIDTH : natural := 32; -- data width (power of 2)
EN_ROUNDING : boolean := false; -- enable hw for rounding to zero/infinity
-- pipeline stages --
EN_INPUT_REG : boolean := false; -- enable input registers
EN_SHIFT_REG : boolean := false; -- enable shifter output register
EN_ROUND_REG : boolean := false; -- enable rounding unit shift register
EN_OUT_REG : boolean := false -- enable output register
);
port (
-- global control --
clk : in std_logic;
-- operand data --
opa_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
opb_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- operation control --
shift_dir_i : in std_logic; -- 0: right, 1: left (shift dreiction)
arith_shift_i : in std_logic; -- 0: logical, 1: arithmetical (only for right shifts)
rnd_en_i : in std_logic; -- 0: rounding disabled, 1: rounding enabled
rnd_mode_i : in std_logic; -- 0: floor, 1: infinity (type of rounding)
-- operation result --
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end generic_sru;
architecture generic_sru_xv6_rtl of generic_sru is
-- muxcy xilinx primitive component (carry chain multiplexer) --
component muxcy
port (
o : out std_logic;
ci : in std_logic;
di : in std_logic;
s : in std_logic
);
end component;
-- xorcy xilinx primitive component (carry chain 'adder') --
component xorcy
port (
o : out std_logic;
ci : in std_logic;
li : in std_logic
);
end component;
-- local types --
type smask_array_t is array(0 to DATA_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- Function: Minimum required bit width --
function index_size(input : natural) return natural is
begin
for i in 0 to natural'high loop
if (2**i >= input) then
return i;
end if;
end loop; -- i
return 0;
end function index_size;
-- Function: init mask for shifter's sign bit cancellation mask --
function init_smask(n: natural) return smask_array_t is
variable smask_array_v : smask_array_t;
begin
smask_array_v := (others => (others => '0'));
smask_array_v(0) := (others => '1');
for i in 0 to n-2 loop
smask_array_v(i+1) := '0' & (smask_array_v(i)(n-1 downto 1));
end loop; -- i
return smask_array_v;
end function init_smask;
-- Function: Bit reversal --
function bit_reversal(input : std_logic_vector) return std_logic_vector is
variable output_v : std_logic_vector(input'range);
begin
for i in 0 to input'length-1 loop
output_v(input'length-i-1) := input(i);
end loop; -- i
return output_v;
end function bit_reversal;
-- internal configuration --
constant log2_data_width_c : natural := index_size(DATA_WIDTH);
constant subword_c : natural := 0;
-- pipeline stage 0 (input register) --
signal opa_s0, opa_ff0 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal opb_s0, opb_ff0 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal shift_dir_s0, shift_dir_ff0 : std_logic;
signal shift_arith_s0, shift_arith_ff0 : std_logic;
signal rnd_en_s0, rnd_en_ff0 : std_logic;
signal rnd_mode_s0, rnd_mode_ff0 : std_logic;
-- shifter core --
constant smask_array : smask_array_t := init_smask(DATA_WIDTH);
signal sra_data : std_logic_vector(DATA_WIDTH-1 downto 0);
signal sra_mask : std_logic_vector(DATA_WIDTH-1 downto 0);
signal shift_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal shift_res : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_sel : std_logic;
-- pipeline stage 1 --
signal sra_data_s1, sra_data_ff1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal sra_mask_s1, sra_mask_ff1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_s1, carry_ff1 : std_logic;
signal shift_dir_s1, shift_dir_ff1 : std_logic;
signal shift_arith_s1, shift_arith_ff1 : std_logic;
signal rnd_en_s1, rnd_en_ff1 : std_logic;
signal rnd_mode_s1, rnd_mode_ff1 : std_logic;
-- rounding unit --
signal inc_chain : std_logic_vector(DATA_WIDTH downto 0);
signal inc_data : std_logic_vector(DATA_WIDTH-1 downto 0);
signal inc_result : std_logic_vector(DATA_WIDTH-1 downto 0);
-- pipeline stage 2 --
signal inc_res_s2, inc_res_ff2 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_s2, carry_ff2 : std_logic;
-- zero detector --
signal nibble_is_zero : std_logic_vector((DATA_WIDTH/4)-1 downto 0);
signal zero_chain : std_logic_vector((DATA_WIDTH/4) downto 0);
-- pipeline stage 3: output register --
signal inc_res_s3, inc_res_ff3 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_s3, carry_ff3 : std_logic;
signal zero_s3, zero_ff3 : std_logic;
-- zero overflow carry negative
signal z_flag_o, o_flag_o, c_flag_o, n_flag_o : std_logic;
begin
-- Pipeline Stage 0: Input Register -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s0: process(clk)
begin
if rising_edge(clk) then
opa_ff0 <= opa_i;
opb_ff0 <= opb_i;
shift_dir_ff0 <= shift_dir_i;
shift_arith_ff0 <= arith_shift_i;
rnd_en_ff0 <= rnd_en_i;
rnd_mode_ff0 <= rnd_mode_i;
end if;
end process pipe_s0;
-- use input registers? --
opa_s0 <= opa_ff0 when (EN_INPUT_REG = true) else opa_i;
opb_s0 <= opb_ff0 when (EN_INPUT_REG = true) else opb_i;
shift_dir_s0 <= shift_dir_ff0 when (EN_INPUT_REG = true) else shift_dir_i;
shift_arith_s0 <= shift_arith_ff0 when (EN_INPUT_REG = true) else arith_shift_i;
rnd_en_s0 <= rnd_en_ff0 when (EN_INPUT_REG = true) else rnd_en_i;
rnd_mode_s0 <= rnd_mode_ff0 when (EN_INPUT_REG = true) else rnd_mode_i;
-- Shifter Core ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
shift_in <= bit_reversal(opa_s0) when (shift_dir_s0 = '1') else opa_s0; -- reverse bits if left shift
shifter_core: process(opb_s0, shift_in)
variable carry_sel_v : std_logic_vector(DATA_WIDTH-1 downto 0);
variable positions_v : integer;
begin
-- all shift types are based on a single arithmetical right shifter
positions_v := to_integer(unsigned(opb_s0(log2_data_width_c-1 downto 0)));
sra_data <= std_logic_vector(shift_right(signed(shift_in), positions_v));
sra_mask <= smask_array(positions_v);
-- select carry --
carry_sel_v := shift_in(DATA_WIDTH-2 downto 0) & '0';
carry_sel <= carry_sel_v(positions_v);
end process shifter_core;
-- Pipeline Stage 1: Shifter output register ----------------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s1: process(clk)
begin
if rising_edge(clk) then
sra_data_ff1 <= sra_data;
sra_mask_ff1 <= sra_mask;
carry_ff1 <= carry_sel;
shift_dir_ff1 <= shift_dir_s0;
shift_arith_ff1 <= shift_arith_s0;
rnd_en_ff1 <= rnd_en_s0;
rnd_mode_ff1 <= rnd_mode_s0;
end if;
end process pipe_s1;
-- use pipeline 1 registers? --
sra_data_s1 <= sra_data_ff1 when (EN_SHIFT_REG = true) else sra_data;
sra_mask_s1 <= sra_mask_ff1 when (EN_SHIFT_REG = true) else sra_mask;
carry_s1 <= carry_ff1 when (EN_SHIFT_REG = true) else carry_sel;
shift_dir_s1 <= shift_dir_ff1 when (EN_SHIFT_REG = true) else shift_dir_s0;
shift_arith_s1 <= shift_arith_ff1 when (EN_SHIFT_REG = true) else shift_arith_s0;
rnd_en_s1 <= rnd_en_ff1 when (EN_SHIFT_REG = true) else rnd_en_s0;
rnd_mode_s1 <= rnd_mode_ff1 when (EN_SHIFT_REG = true) else rnd_mode_s0;
-- Shifter result masking ------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------
shifter_sel: process(shift_dir_s1, shift_arith_s1, sra_data_s1, sra_mask_s1)
variable lrs_v : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
lrs_v := sra_data_s1 and sra_mask_s1;
if (shift_dir_s1 = '1') then -- logical left shift
shift_res <= bit_reversal(lrs_v);
else -- right shift
if (shift_arith_s1 = '1') then -- arithmetical right shift
shift_res <= sra_data_s1;
else -- logical right shift
shift_res <= lrs_v;
end if;
end if;
end process shifter_sel;
-- Rounding --------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------
-- start of incrementer carry line with internal carry input
inc_chain(0) <= carry_s1 and (rnd_en_s1 and rnd_mode_s1);
-- simple incrementer, using dedicated hardware (muxcy, xorcy)
increment_unit:
for i in 0 to DATA_WIDTH-1 generate
-- inc_muxcy_inst: muxcy
-- port map (
-- o => inc_chain(i+1),
-- ci => inc_chain(i),
-- di => '0',
-- s => shift_res(i)
-- );
inc_chain(i+1) <= '0' when shift_res(i) = '0' else inc_chain(i);
-- inc_xorcy_inst: xorcy
-- port map (
-- o => inc_data(i),
-- ci => inc_chain(i),
-- li => shift_res(i)
-- );
inc_data(i) <= inc_chain(i) xor shift_res(i);
end generate; -- i
-- operation result output --
inc_result <= inc_data when (EN_ROUNDING = true) else shift_res;
-- Pipeline Stage 2: Rounding unit output register ----------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s2: process(clk)
begin
if rising_edge(clk) then
inc_res_ff2 <= inc_result;
carry_ff2 <= carry_s1;
end if;
end process pipe_s2;
-- use pipeline 2 registers? --
inc_res_s2 <= inc_res_ff2 when (EN_ROUND_REG = true) else inc_result;
carry_s2 <= carry_ff2 when (EN_ROUND_REG = true) else carry_s1;
-- Zero Detector --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
zero_chain(0) <= '1'; -- start a new subword chain
zero_detector:
for i in 0 to (DATA_WIDTH/4)-1 generate -- number of nibbles
-- zero detection for 4 bit -> 1 LUT + 1 MUXCY, propagate previous zero signal, when nibble is zero
nibble_is_zero(i) <= '1' when (inc_res_s2(i*4+3 downto i*4) = "0000") else '0'; -- is zero?
-- zero_detector_muxcy: muxcy
-- port map (
-- o => zero_chain(i+1), -- chain output signal
-- ci => zero_chain(i), -- s=1: chain input signal
-- di => '0', -- s=0: 0 input, nibble is not zero
-- s => nibble_is_zero(i) -- mux select input
-- );
zero_chain(i+1) <= '0' when nibble_is_zero(i) = '0' else zero_chain(i);
end generate; -- i
-- Pipeline Stage 3: Output register ------------------------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s3: process(clk)
begin
if rising_edge(clk) then
inc_res_ff3 <= inc_res_s2;
carry_ff3 <= carry_s2;
zero_ff3 <= zero_chain(DATA_WIDTH/4);
end if;
end process pipe_s3;
-- use pipeline 2 registers? --
inc_res_s3 <= inc_res_ff3 when (EN_OUT_REG = true) else inc_res_s2;
carry_s3 <= carry_ff3 when (EN_OUT_REG = true) else carry_s2;
zero_s3 <= zero_ff3 when (EN_OUT_REG = true) else zero_chain(DATA_WIDTH/4);
-- data output --
data_o <= inc_res_s3;
-- negative flag output --
n_flag_o <= inc_res_s3(DATA_WIDTH-1);
-- zero flag output --
z_flag_o <= zero_s3;
-- carry flag output --
c_flag_o <= carry_s3;
-- TODO: overflow:
-- all out-shifted bits should be equal to the sign, else overflow
-- for signed operations, also the result sign should be equal to the original sign
o_flag_o <= '0'; -- implement me!
end generic_sru_xv6_rtl;
|
-- wasca_reset_controller_0.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_reset_controller_0 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "both";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
reset_in1 : in std_logic := '0'; -- reset_in1.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_reset_controller_0;
architecture rtl of wasca_reset_controller_0 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
reset_controller_0 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
reset_in1 => reset_in1, -- reset_in1.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_reset_controller_0
|
-- wasca_reset_controller_0.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_reset_controller_0 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "both";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
reset_in1 : in std_logic := '0'; -- reset_in1.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_reset_controller_0;
architecture rtl of wasca_reset_controller_0 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
reset_controller_0 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
reset_in1 => reset_in1, -- reset_in1.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_reset_controller_0
|
-- wasca_reset_controller_0.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_reset_controller_0 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "both";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
reset_in1 : in std_logic := '0'; -- reset_in1.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_reset_controller_0;
architecture rtl of wasca_reset_controller_0 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
reset_controller_0 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
reset_in1 => reset_in1, -- reset_in1.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_reset_controller_0
|
-- wasca_reset_controller_0.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_reset_controller_0 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "both";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
reset_in1 : in std_logic := '0'; -- reset_in1.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_reset_controller_0;
architecture rtl of wasca_reset_controller_0 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
reset_controller_0 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
reset_in1 => reset_in1, -- reset_in1.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_reset_controller_0
|
-- wasca_reset_controller_0.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_reset_controller_0 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "both";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
reset_in1 : in std_logic := '0'; -- reset_in1.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_reset_controller_0;
architecture rtl of wasca_reset_controller_0 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
reset_controller_0 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
reset_in1 => reset_in1, -- reset_in1.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_reset_controller_0
|
-- wasca_reset_controller_0.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_reset_controller_0 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "both";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
reset_in1 : in std_logic := '0'; -- reset_in1.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_reset_controller_0;
architecture rtl of wasca_reset_controller_0 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
reset_controller_0 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
reset_in1 => reset_in1, -- reset_in1.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_reset_controller_0
|
-- NEED RESULT: ARCH00555: Signal declarations - composite globally static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00555
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.2 (10)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00555)
-- ENT00555_Test_Bench(ARCH00555_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00555 of GENERIC_STANDARD_TYPES is
signal si_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
signal si_st_string_1 : st_string
:= c_st_string_1 ;
signal si_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
signal si_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
signal si_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
signal si_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
signal si_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
signal si_st_arr3_1 : st_arr3
:= c_st_arr3_1 ;
signal synch : boolean := false ;
signal s_correct : boolean := true ;
begin
process
variable correct : boolean := true ;
begin
correct := correct and si_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and si_st_string_1 = c_st_string_1 ;
correct := correct and si_st_rec1_1 = c_st_rec1_1 ;
correct := correct and si_st_rec2_1 = c_st_rec2_1 ;
correct := correct and si_st_rec3_1 = c_st_rec3_1 ;
correct := correct and si_st_arr1_1 = c_st_arr1_1 ;
correct := correct and si_st_arr2_1 = c_st_arr2_1 ;
correct := correct and si_st_arr3_1 = c_st_arr3_1 ;
si_st_bit_vector_1 <= c_st_bit_vector_2 ;
si_st_string_1 <= c_st_string_2 ;
si_st_rec1_1 <= c_st_rec1_2 ;
si_st_rec2_1 <= c_st_rec2_2 ;
si_st_rec3_1 <= c_st_rec3_2 ;
si_st_arr1_1 <= c_st_arr1_2 ;
si_st_arr2_1 <= c_st_arr2_2 ;
si_st_arr3_1 <= c_st_arr3_2 ;
synch <= true ;
s_correct <= s_correct and correct ;
wait ;
end process ;
process (synch)
variable correct : boolean ;
begin
correct := s_correct ;
if synch = true then
correct := correct and si_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and si_st_string_1 = c_st_string_2 ;
correct := correct and si_st_rec1_1 = c_st_rec1_2 ;
correct := correct and si_st_rec2_1 = c_st_rec2_2 ;
correct := correct and si_st_rec3_1 = c_st_rec3_2 ;
correct := correct and si_st_arr1_1 = c_st_arr1_2 ;
correct := correct and si_st_arr2_1 = c_st_arr2_2 ;
correct := correct and si_st_arr3_1 = c_st_arr3_2 ;
test_report ( "ARCH00555" ,
"Signal declarations - composite globally static subtypes" ,
correct) ;
end if ;
end process ;
end ARCH00555 ;
--
entity ENT00555_Test_Bench is
end ENT00555_Test_Bench ;
--
architecture ARCH00555_Test_Bench of ENT00555_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00555 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00555_Test_Bench ;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:08:15 11/19/2013
-- Design Name:
-- Module Name: HalfAdder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.MyTypes.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity HalfAdder is
port( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
end HalfAdder;
architecture Behavioral of HalfAdder is
begin
s <= a xor b;
c <= a and b;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:04:25 05/29/2014
-- Design Name:
-- Module Name: FSM1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FSM1 is
Port (
reset : in std_logic;
clk : in std_logic;
start: in std_logic;
data_in : in std_logic_vector(3 downto 0);
AVAIL : out std_logic;
DONE : out std_logic;
flag : out std_logic_vector(1 downto 0));
end FSM1;
architecture Behavioral of FSM1 is
type tipoestado is (s0, s1, s2, s3, s4, s5, s6);
signal estado : tipoestado;
begin
process(reset, clk)
variable regd : std_logic_vector(3 downto 0);
variable cont : std_logic_vector(6 downto 0);
begin
if reset = '1' then
estado <= s0;
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := "0000"; cont := "0000000";
elsif (clk'event and clk='1') then
CASE estado IS
WHEN s0 =>
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := "0000"; cont := "0000000"; if start='0'then estado
<= s0; else estado <= s1; end if;
WHEN s1 =>
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := data_in; cont := cont+1;
if (regd = "1011" and cont <= "1100100") then estado <= s2;
elsif cont="1100100" then estado <= s4;
else estado <= s1;
end if;
WHEN s2 => -- achou um valor em <=100
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s3;
WHEN s3 =>
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s0;
WHEN s4 => -- nao achou valor ate 100 dados
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s5;
WHEN s5 =>
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s0;
WHEN others =>
AVAIL <= '1'; done <= '0'; flag <= "00"; estado <= s0;
end CASE;
end if;
end process;
end Behavioral;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: cond_broadcast_1.c
-- NUM_THREADS = 3
-- reg1 = i
-- reg2 = * mutex
-- reg3 = * cond
-- reg4 = * start_num
-- reg5 = * waken_num
-- reg6 = * function
-- reg7 = thread[i]
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of mutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of cond
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg3_next <= intrfc2thrd_value;
-- Read the address of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg4_next <= intrfc2thrd_value;
-- Read the address of waken_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 12;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg5_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 16;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
-- for( i=0; i<NUM_THREADS; i++ )
when STATE_6 =>
reg6_next <= intrfc2thrd_value;
-- set i=0
reg1_next <= Z32;
next_state <= STATE_7;
when STATE_7 =>
case reg1 is
when x"00000000" => next_state <= STATE_8;
when x"00000001" => next_state <= STATE_8;
when x"00000002" => next_state <= STATE_8;
when others => next_state <= STATE_13;
end case;
-- hthread_create( &data->thread[i], NULL, data->function, (void *) data );
when STATE_8 =>
-- push (void *) data
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- push &data->thread[i]
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000014" + (reg1(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
reg1_next <= reg1 + x"00000001";
-- while( *(data->start_num) != THREAD_NUM ) hthread_yield();
when STATE_13 =>
-- Read the value of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_14;
when STATE_14 =>
case intrfc2thrd_value is
when x"00000003" => next_state <= STATE_16;
when others => next_state <= STATE_15;
end case;
when STATE_15 =>
-- call hthread_yield
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_YIELD;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_13;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( data->mutex );
when STATE_16 =>
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
when STATE_17 =>
-- call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_18;
next_state <= WAIT_STATE;
-- hthread_cond_broadcast( data->cond );
when STATE_18 =>
-- push data->cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_19;
when STATE_19 =>
-- call hthread_cond_broadcast
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_BROADCAST;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_20;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( data->mutex );
when STATE_20 =>
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_21;
when STATE_21 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_22;
next_state <= WAIT_STATE;
-- for( i=0; i<NUM_THREADS; i++ )
when STATE_22 =>
reg1_next <= Z32;
next_state <= STATE_23;
when STATE_23 =>
case reg1 is
when x"00000000" => next_state <= STATE_24;
when x"00000001" => next_state <= STATE_24;
when x"00000002" => next_state <= STATE_24;
when others => next_state <= STATE_28;
end case;
-- retVal = hthread_join( data->thread[i], NULL );
when STATE_24 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000014" + (reg1(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= STATE_25;
when STATE_25 =>
reg4_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_26;
when STATE_26 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_27;
when STATE_27 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_23;
next_state <= WAIT_STATE;
reg1_next <= reg1 + 1;
-- retVal = *( data->waken_num )
when STATE_28 =>
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg5;
next_state <= WAIT_STATE;
return_state_next <= STATE_29;
when STATE_29 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity test_cmds is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8;
BASE : std_logic_vector := x"75000000"
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
addr : out std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
datain : in std_logic_vector(0 to C_DWIDTH-1);
kind : out std_logic_vector(0 to 1);
owner : out std_logic_vector(0 to C_TWIDTH-1);
count : out std_logic_vector(0 to C_CWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end test_cmds;
architecture behavioral of test_cmds is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
SETID,
SETMID,
DOLOCK,
DOUNLOCK,
DOTRYLOCK,
DOSETKIND,
DOGETKIND,
DOGETCOUNT,
DOGETOWNER,
DONE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
-- Signals for stuff
signal tid : std_logic_vector(0 to C_TWIDTH-1);
signal mid : std_logic_vector(0 to C_MWIDTH-1);
signal tidn : std_logic_vector(0 to C_TWIDTH-1);
signal midn : std_logic_vector(0 to C_MWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
tid <= (others => '0');
mid <= (others => '0');
else
lock_cs <= lock_ns;
tid <= tidn;
mid <= midn;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
tidn <= tid;
midn <= mid;
case lock_cs is
when IDLE =>
if( start = '1' ) then
if( mikind = "00" ) then
lock_ns <= DOLOCK;
elsif( mikind = "01" ) then
lock_ns <= SETID;
else
lock_ns <= SETMID;
end if;
end if;
when SETID =>
tidn <= miowner;
lock_ns <= IDLE;
when SETMID =>
midn <= mutex;
lock_ns <= IDLE;
-- LOCK Command:
-- To perform a lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_lockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use when locking the mutex
-- and the 7th parameter is the mutex identifier to lock.
--
-- Thus a to generate the address to use when performing a lock operation:
-- synch_lockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_locksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the lock operation:
-- synch_locksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_LOCKSTA_CONTINUE then the lock was
-- successfully locked and the thread can continue to run. If the
-- returned status is SYNCH_LOCKSTA_BLOCK then the thread did not get
-- the lock and should not continue to run.
when DOLOCK =>
addr <= synch_lockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_locksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_LOCKSTA_CONTINUE ) then
null; -- Continue the operation of the core
else
null; -- Halt the operation of the core
end if;
lock_ns <= DOUNLOCK;
-- UNLOCK Command:
-- To perform an unlock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_unlockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use the 7th parameter is the
-- mutex identifier.
--
-- Thus a to generate the address to use when performing an unlock operation:
-- synch_unlockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_unlocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the unlock operation:
-- synch_unlocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_UNLOCKSTA_SUCCESS then the unlock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_UNLOCKSTA_ERROR then the thread did not unlock
-- the lock because some error occurred.
when DOUNLOCK =>
addr <= synch_unlockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if (synch_unlocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_UNLOCKSTA_SUCCESS ) then
null; -- Unlock operation was successful
else
null; -- Unlock operation failed because of some reason
end if;
lock_ns <= DOTRYLOCK;
-- TRYLOCK Command:
-- To perform a try lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_trylockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing a try lock:
-- synch_trylockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_trylocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the trylock operation:
-- synch_trylocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_TRYLOCKSTA_SUCCESS then the lock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_TRYLOCKSTA_ERROR then the thread did not get the lock
-- because the lock was already owned by another thread.
when DOTRYLOCK =>
addr<=synch_trylockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_trylocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_TRYLOCKSTA_SUCCESS ) then
null; -- Lock was acquired
else
null; -- Lock was already owned by another thread
end if;
lock_ns <= DOSETKIND;
-- SET KIND Command:
-- To perform a kind set operation with the synchronization manager you
-- perform a write to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to set the kind of an mutex:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- Since this is a write operation no status information is returned.
when DOSETKIND =>
-- As write operation
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
lock_ns <= DOGETKIND;
-- GET KIND Command:
-- To perform a get kind operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_kindsta which will gets the kind. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to get the kind of a mutex:
-- synch_kindsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned from this function is one of SYNCH_FAST, SYNCH_RECURS,
-- or SYNCH_ERROR depending on the type of mutex that was returned.
when DOGETKIND =>
-- As read operations
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
kind <= synch_kindsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETCOUNT;
-- GET COUNT Command:
-- To perform a get count operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_countcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_countcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_countsta which will gets the count. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the recursive lock count of a mutex::
-- synch_countsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the recursive lock count.
when DOGETCOUNT =>
addr <= synch_countcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
count <= synch_countsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETOWNER;
-- GET OWNER Command:
-- To perform a get owner operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_ownercmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_ownercmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_ownersta which will gets the owner. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the owner of a mutex::
-- synch_ownersta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the owner of the mutex.
when DOGETOWNER =>
addr <= synch_ownercmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
owner <= synch_ownersta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DONE;
when DONE =>
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity test_cmds is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8;
BASE : std_logic_vector := x"75000000"
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
addr : out std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
datain : in std_logic_vector(0 to C_DWIDTH-1);
kind : out std_logic_vector(0 to 1);
owner : out std_logic_vector(0 to C_TWIDTH-1);
count : out std_logic_vector(0 to C_CWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end test_cmds;
architecture behavioral of test_cmds is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
SETID,
SETMID,
DOLOCK,
DOUNLOCK,
DOTRYLOCK,
DOSETKIND,
DOGETKIND,
DOGETCOUNT,
DOGETOWNER,
DONE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
-- Signals for stuff
signal tid : std_logic_vector(0 to C_TWIDTH-1);
signal mid : std_logic_vector(0 to C_MWIDTH-1);
signal tidn : std_logic_vector(0 to C_TWIDTH-1);
signal midn : std_logic_vector(0 to C_MWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
tid <= (others => '0');
mid <= (others => '0');
else
lock_cs <= lock_ns;
tid <= tidn;
mid <= midn;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
tidn <= tid;
midn <= mid;
case lock_cs is
when IDLE =>
if( start = '1' ) then
if( mikind = "00" ) then
lock_ns <= DOLOCK;
elsif( mikind = "01" ) then
lock_ns <= SETID;
else
lock_ns <= SETMID;
end if;
end if;
when SETID =>
tidn <= miowner;
lock_ns <= IDLE;
when SETMID =>
midn <= mutex;
lock_ns <= IDLE;
-- LOCK Command:
-- To perform a lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_lockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use when locking the mutex
-- and the 7th parameter is the mutex identifier to lock.
--
-- Thus a to generate the address to use when performing a lock operation:
-- synch_lockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_locksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the lock operation:
-- synch_locksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_LOCKSTA_CONTINUE then the lock was
-- successfully locked and the thread can continue to run. If the
-- returned status is SYNCH_LOCKSTA_BLOCK then the thread did not get
-- the lock and should not continue to run.
when DOLOCK =>
addr <= synch_lockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_locksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_LOCKSTA_CONTINUE ) then
null; -- Continue the operation of the core
else
null; -- Halt the operation of the core
end if;
lock_ns <= DOUNLOCK;
-- UNLOCK Command:
-- To perform an unlock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_unlockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use the 7th parameter is the
-- mutex identifier.
--
-- Thus a to generate the address to use when performing an unlock operation:
-- synch_unlockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_unlocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the unlock operation:
-- synch_unlocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_UNLOCKSTA_SUCCESS then the unlock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_UNLOCKSTA_ERROR then the thread did not unlock
-- the lock because some error occurred.
when DOUNLOCK =>
addr <= synch_unlockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if (synch_unlocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_UNLOCKSTA_SUCCESS ) then
null; -- Unlock operation was successful
else
null; -- Unlock operation failed because of some reason
end if;
lock_ns <= DOTRYLOCK;
-- TRYLOCK Command:
-- To perform a try lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_trylockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing a try lock:
-- synch_trylockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_trylocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the trylock operation:
-- synch_trylocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_TRYLOCKSTA_SUCCESS then the lock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_TRYLOCKSTA_ERROR then the thread did not get the lock
-- because the lock was already owned by another thread.
when DOTRYLOCK =>
addr<=synch_trylockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_trylocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_TRYLOCKSTA_SUCCESS ) then
null; -- Lock was acquired
else
null; -- Lock was already owned by another thread
end if;
lock_ns <= DOSETKIND;
-- SET KIND Command:
-- To perform a kind set operation with the synchronization manager you
-- perform a write to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to set the kind of an mutex:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- Since this is a write operation no status information is returned.
when DOSETKIND =>
-- As write operation
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
lock_ns <= DOGETKIND;
-- GET KIND Command:
-- To perform a get kind operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_kindsta which will gets the kind. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to get the kind of a mutex:
-- synch_kindsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned from this function is one of SYNCH_FAST, SYNCH_RECURS,
-- or SYNCH_ERROR depending on the type of mutex that was returned.
when DOGETKIND =>
-- As read operations
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
kind <= synch_kindsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETCOUNT;
-- GET COUNT Command:
-- To perform a get count operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_countcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_countcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_countsta which will gets the count. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the recursive lock count of a mutex::
-- synch_countsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the recursive lock count.
when DOGETCOUNT =>
addr <= synch_countcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
count <= synch_countsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETOWNER;
-- GET OWNER Command:
-- To perform a get owner operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_ownercmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_ownercmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_ownersta which will gets the owner. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the owner of a mutex::
-- synch_ownersta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the owner of the mutex.
when DOGETOWNER =>
addr <= synch_ownercmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
owner <= synch_ownersta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DONE;
when DONE =>
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity test_cmds is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8;
BASE : std_logic_vector := x"75000000"
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
addr : out std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
datain : in std_logic_vector(0 to C_DWIDTH-1);
kind : out std_logic_vector(0 to 1);
owner : out std_logic_vector(0 to C_TWIDTH-1);
count : out std_logic_vector(0 to C_CWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end test_cmds;
architecture behavioral of test_cmds is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
SETID,
SETMID,
DOLOCK,
DOUNLOCK,
DOTRYLOCK,
DOSETKIND,
DOGETKIND,
DOGETCOUNT,
DOGETOWNER,
DONE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
-- Signals for stuff
signal tid : std_logic_vector(0 to C_TWIDTH-1);
signal mid : std_logic_vector(0 to C_MWIDTH-1);
signal tidn : std_logic_vector(0 to C_TWIDTH-1);
signal midn : std_logic_vector(0 to C_MWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
tid <= (others => '0');
mid <= (others => '0');
else
lock_cs <= lock_ns;
tid <= tidn;
mid <= midn;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
tidn <= tid;
midn <= mid;
case lock_cs is
when IDLE =>
if( start = '1' ) then
if( mikind = "00" ) then
lock_ns <= DOLOCK;
elsif( mikind = "01" ) then
lock_ns <= SETID;
else
lock_ns <= SETMID;
end if;
end if;
when SETID =>
tidn <= miowner;
lock_ns <= IDLE;
when SETMID =>
midn <= mutex;
lock_ns <= IDLE;
-- LOCK Command:
-- To perform a lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_lockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use when locking the mutex
-- and the 7th parameter is the mutex identifier to lock.
--
-- Thus a to generate the address to use when performing a lock operation:
-- synch_lockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_locksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the lock operation:
-- synch_locksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_LOCKSTA_CONTINUE then the lock was
-- successfully locked and the thread can continue to run. If the
-- returned status is SYNCH_LOCKSTA_BLOCK then the thread did not get
-- the lock and should not continue to run.
when DOLOCK =>
addr <= synch_lockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_locksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_LOCKSTA_CONTINUE ) then
null; -- Continue the operation of the core
else
null; -- Halt the operation of the core
end if;
lock_ns <= DOUNLOCK;
-- UNLOCK Command:
-- To perform an unlock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_unlockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use the 7th parameter is the
-- mutex identifier.
--
-- Thus a to generate the address to use when performing an unlock operation:
-- synch_unlockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_unlocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the unlock operation:
-- synch_unlocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_UNLOCKSTA_SUCCESS then the unlock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_UNLOCKSTA_ERROR then the thread did not unlock
-- the lock because some error occurred.
when DOUNLOCK =>
addr <= synch_unlockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if (synch_unlocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_UNLOCKSTA_SUCCESS ) then
null; -- Unlock operation was successful
else
null; -- Unlock operation failed because of some reason
end if;
lock_ns <= DOTRYLOCK;
-- TRYLOCK Command:
-- To perform a try lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_trylockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing a try lock:
-- synch_trylockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_trylocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the trylock operation:
-- synch_trylocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_TRYLOCKSTA_SUCCESS then the lock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_TRYLOCKSTA_ERROR then the thread did not get the lock
-- because the lock was already owned by another thread.
when DOTRYLOCK =>
addr<=synch_trylockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_trylocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_TRYLOCKSTA_SUCCESS ) then
null; -- Lock was acquired
else
null; -- Lock was already owned by another thread
end if;
lock_ns <= DOSETKIND;
-- SET KIND Command:
-- To perform a kind set operation with the synchronization manager you
-- perform a write to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to set the kind of an mutex:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- Since this is a write operation no status information is returned.
when DOSETKIND =>
-- As write operation
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
lock_ns <= DOGETKIND;
-- GET KIND Command:
-- To perform a get kind operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_kindsta which will gets the kind. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to get the kind of a mutex:
-- synch_kindsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned from this function is one of SYNCH_FAST, SYNCH_RECURS,
-- or SYNCH_ERROR depending on the type of mutex that was returned.
when DOGETKIND =>
-- As read operations
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
kind <= synch_kindsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETCOUNT;
-- GET COUNT Command:
-- To perform a get count operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_countcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_countcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_countsta which will gets the count. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the recursive lock count of a mutex::
-- synch_countsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the recursive lock count.
when DOGETCOUNT =>
addr <= synch_countcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
count <= synch_countsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETOWNER;
-- GET OWNER Command:
-- To perform a get owner operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_ownercmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_ownercmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_ownersta which will gets the owner. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the owner of a mutex::
-- synch_ownersta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the owner of the mutex.
when DOGETOWNER =>
addr <= synch_ownercmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
owner <= synch_ownersta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DONE;
when DONE =>
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity test_cmds is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8;
BASE : std_logic_vector := x"75000000"
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
addr : out std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
datain : in std_logic_vector(0 to C_DWIDTH-1);
kind : out std_logic_vector(0 to 1);
owner : out std_logic_vector(0 to C_TWIDTH-1);
count : out std_logic_vector(0 to C_CWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end test_cmds;
architecture behavioral of test_cmds is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
SETID,
SETMID,
DOLOCK,
DOUNLOCK,
DOTRYLOCK,
DOSETKIND,
DOGETKIND,
DOGETCOUNT,
DOGETOWNER,
DONE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
-- Signals for stuff
signal tid : std_logic_vector(0 to C_TWIDTH-1);
signal mid : std_logic_vector(0 to C_MWIDTH-1);
signal tidn : std_logic_vector(0 to C_TWIDTH-1);
signal midn : std_logic_vector(0 to C_MWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
tid <= (others => '0');
mid <= (others => '0');
else
lock_cs <= lock_ns;
tid <= tidn;
mid <= midn;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
tidn <= tid;
midn <= mid;
case lock_cs is
when IDLE =>
if( start = '1' ) then
if( mikind = "00" ) then
lock_ns <= DOLOCK;
elsif( mikind = "01" ) then
lock_ns <= SETID;
else
lock_ns <= SETMID;
end if;
end if;
when SETID =>
tidn <= miowner;
lock_ns <= IDLE;
when SETMID =>
midn <= mutex;
lock_ns <= IDLE;
-- LOCK Command:
-- To perform a lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_lockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use when locking the mutex
-- and the 7th parameter is the mutex identifier to lock.
--
-- Thus a to generate the address to use when performing a lock operation:
-- synch_lockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_locksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the lock operation:
-- synch_locksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_LOCKSTA_CONTINUE then the lock was
-- successfully locked and the thread can continue to run. If the
-- returned status is SYNCH_LOCKSTA_BLOCK then the thread did not get
-- the lock and should not continue to run.
when DOLOCK =>
addr <= synch_lockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_locksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_LOCKSTA_CONTINUE ) then
null; -- Continue the operation of the core
else
null; -- Halt the operation of the core
end if;
lock_ns <= DOUNLOCK;
-- UNLOCK Command:
-- To perform an unlock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_unlockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use the 7th parameter is the
-- mutex identifier.
--
-- Thus a to generate the address to use when performing an unlock operation:
-- synch_unlockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_unlocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the unlock operation:
-- synch_unlocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_UNLOCKSTA_SUCCESS then the unlock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_UNLOCKSTA_ERROR then the thread did not unlock
-- the lock because some error occurred.
when DOUNLOCK =>
addr <= synch_unlockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if (synch_unlocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_UNLOCKSTA_SUCCESS ) then
null; -- Unlock operation was successful
else
null; -- Unlock operation failed because of some reason
end if;
lock_ns <= DOTRYLOCK;
-- TRYLOCK Command:
-- To perform a try lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_trylockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing a try lock:
-- synch_trylockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_trylocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the trylock operation:
-- synch_trylocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_TRYLOCKSTA_SUCCESS then the lock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_TRYLOCKSTA_ERROR then the thread did not get the lock
-- because the lock was already owned by another thread.
when DOTRYLOCK =>
addr<=synch_trylockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_trylocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_TRYLOCKSTA_SUCCESS ) then
null; -- Lock was acquired
else
null; -- Lock was already owned by another thread
end if;
lock_ns <= DOSETKIND;
-- SET KIND Command:
-- To perform a kind set operation with the synchronization manager you
-- perform a write to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to set the kind of an mutex:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- Since this is a write operation no status information is returned.
when DOSETKIND =>
-- As write operation
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
lock_ns <= DOGETKIND;
-- GET KIND Command:
-- To perform a get kind operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_kindsta which will gets the kind. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to get the kind of a mutex:
-- synch_kindsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned from this function is one of SYNCH_FAST, SYNCH_RECURS,
-- or SYNCH_ERROR depending on the type of mutex that was returned.
when DOGETKIND =>
-- As read operations
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
kind <= synch_kindsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETCOUNT;
-- GET COUNT Command:
-- To perform a get count operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_countcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_countcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_countsta which will gets the count. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the recursive lock count of a mutex::
-- synch_countsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the recursive lock count.
when DOGETCOUNT =>
addr <= synch_countcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
count <= synch_countsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETOWNER;
-- GET OWNER Command:
-- To perform a get owner operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_ownercmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_ownercmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_ownersta which will gets the owner. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the owner of a mutex::
-- synch_ownersta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the owner of the mutex.
when DOGETOWNER =>
addr <= synch_ownercmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
owner <= synch_ownersta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DONE;
when DONE =>
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity test_cmds is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8;
BASE : std_logic_vector := x"75000000"
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
addr : out std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
datain : in std_logic_vector(0 to C_DWIDTH-1);
kind : out std_logic_vector(0 to 1);
owner : out std_logic_vector(0 to C_TWIDTH-1);
count : out std_logic_vector(0 to C_CWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end test_cmds;
architecture behavioral of test_cmds is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
SETID,
SETMID,
DOLOCK,
DOUNLOCK,
DOTRYLOCK,
DOSETKIND,
DOGETKIND,
DOGETCOUNT,
DOGETOWNER,
DONE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
-- Signals for stuff
signal tid : std_logic_vector(0 to C_TWIDTH-1);
signal mid : std_logic_vector(0 to C_MWIDTH-1);
signal tidn : std_logic_vector(0 to C_TWIDTH-1);
signal midn : std_logic_vector(0 to C_MWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
tid <= (others => '0');
mid <= (others => '0');
else
lock_cs <= lock_ns;
tid <= tidn;
mid <= midn;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
tidn <= tid;
midn <= mid;
case lock_cs is
when IDLE =>
if( start = '1' ) then
if( mikind = "00" ) then
lock_ns <= DOLOCK;
elsif( mikind = "01" ) then
lock_ns <= SETID;
else
lock_ns <= SETMID;
end if;
end if;
when SETID =>
tidn <= miowner;
lock_ns <= IDLE;
when SETMID =>
midn <= mutex;
lock_ns <= IDLE;
-- LOCK Command:
-- To perform a lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_lockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use when locking the mutex
-- and the 7th parameter is the mutex identifier to lock.
--
-- Thus a to generate the address to use when performing a lock operation:
-- synch_lockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_locksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the lock operation:
-- synch_locksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_LOCKSTA_CONTINUE then the lock was
-- successfully locked and the thread can continue to run. If the
-- returned status is SYNCH_LOCKSTA_BLOCK then the thread did not get
-- the lock and should not continue to run.
when DOLOCK =>
addr <= synch_lockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_locksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_LOCKSTA_CONTINUE ) then
null; -- Continue the operation of the core
else
null; -- Halt the operation of the core
end if;
lock_ns <= DOUNLOCK;
-- UNLOCK Command:
-- To perform an unlock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_unlockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use the 7th parameter is the
-- mutex identifier.
--
-- Thus a to generate the address to use when performing an unlock operation:
-- synch_unlockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_unlocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the unlock operation:
-- synch_unlocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_UNLOCKSTA_SUCCESS then the unlock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_UNLOCKSTA_ERROR then the thread did not unlock
-- the lock because some error occurred.
when DOUNLOCK =>
addr <= synch_unlockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if (synch_unlocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_UNLOCKSTA_SUCCESS ) then
null; -- Unlock operation was successful
else
null; -- Unlock operation failed because of some reason
end if;
lock_ns <= DOTRYLOCK;
-- TRYLOCK Command:
-- To perform a try lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_trylockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing a try lock:
-- synch_trylockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_trylocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the trylock operation:
-- synch_trylocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_TRYLOCKSTA_SUCCESS then the lock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_TRYLOCKSTA_ERROR then the thread did not get the lock
-- because the lock was already owned by another thread.
when DOTRYLOCK =>
addr<=synch_trylockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_trylocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_TRYLOCKSTA_SUCCESS ) then
null; -- Lock was acquired
else
null; -- Lock was already owned by another thread
end if;
lock_ns <= DOSETKIND;
-- SET KIND Command:
-- To perform a kind set operation with the synchronization manager you
-- perform a write to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to set the kind of an mutex:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- Since this is a write operation no status information is returned.
when DOSETKIND =>
-- As write operation
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
lock_ns <= DOGETKIND;
-- GET KIND Command:
-- To perform a get kind operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_kindsta which will gets the kind. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to get the kind of a mutex:
-- synch_kindsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned from this function is one of SYNCH_FAST, SYNCH_RECURS,
-- or SYNCH_ERROR depending on the type of mutex that was returned.
when DOGETKIND =>
-- As read operations
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
kind <= synch_kindsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETCOUNT;
-- GET COUNT Command:
-- To perform a get count operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_countcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_countcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_countsta which will gets the count. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the recursive lock count of a mutex::
-- synch_countsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the recursive lock count.
when DOGETCOUNT =>
addr <= synch_countcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
count <= synch_countsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETOWNER;
-- GET OWNER Command:
-- To perform a get owner operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_ownercmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_ownercmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_ownersta which will gets the owner. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the owner of a mutex::
-- synch_ownersta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the owner of the mutex.
when DOGETOWNER =>
addr <= synch_ownercmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
owner <= synch_ownersta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DONE;
when DONE =>
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity test_cmds is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8;
BASE : std_logic_vector := x"75000000"
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
addr : out std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
datain : in std_logic_vector(0 to C_DWIDTH-1);
kind : out std_logic_vector(0 to 1);
owner : out std_logic_vector(0 to C_TWIDTH-1);
count : out std_logic_vector(0 to C_CWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end test_cmds;
architecture behavioral of test_cmds is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
SETID,
SETMID,
DOLOCK,
DOUNLOCK,
DOTRYLOCK,
DOSETKIND,
DOGETKIND,
DOGETCOUNT,
DOGETOWNER,
DONE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
-- Signals for stuff
signal tid : std_logic_vector(0 to C_TWIDTH-1);
signal mid : std_logic_vector(0 to C_MWIDTH-1);
signal tidn : std_logic_vector(0 to C_TWIDTH-1);
signal midn : std_logic_vector(0 to C_MWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
tid <= (others => '0');
mid <= (others => '0');
else
lock_cs <= lock_ns;
tid <= tidn;
mid <= midn;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
tidn <= tid;
midn <= mid;
case lock_cs is
when IDLE =>
if( start = '1' ) then
if( mikind = "00" ) then
lock_ns <= DOLOCK;
elsif( mikind = "01" ) then
lock_ns <= SETID;
else
lock_ns <= SETMID;
end if;
end if;
when SETID =>
tidn <= miowner;
lock_ns <= IDLE;
when SETMID =>
midn <= mutex;
lock_ns <= IDLE;
-- LOCK Command:
-- To perform a lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_lockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use when locking the mutex
-- and the 7th parameter is the mutex identifier to lock.
--
-- Thus a to generate the address to use when performing a lock operation:
-- synch_lockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_locksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the lock operation:
-- synch_locksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_LOCKSTA_CONTINUE then the lock was
-- successfully locked and the thread can continue to run. If the
-- returned status is SYNCH_LOCKSTA_BLOCK then the thread did not get
-- the lock and should not continue to run.
when DOLOCK =>
addr <= synch_lockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_locksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_LOCKSTA_CONTINUE ) then
null; -- Continue the operation of the core
else
null; -- Halt the operation of the core
end if;
lock_ns <= DOUNLOCK;
-- UNLOCK Command:
-- To perform an unlock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_unlockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use the 7th parameter is the
-- mutex identifier.
--
-- Thus a to generate the address to use when performing an unlock operation:
-- synch_unlockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_unlocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the unlock operation:
-- synch_unlocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_UNLOCKSTA_SUCCESS then the unlock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_UNLOCKSTA_ERROR then the thread did not unlock
-- the lock because some error occurred.
when DOUNLOCK =>
addr <= synch_unlockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if (synch_unlocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_UNLOCKSTA_SUCCESS ) then
null; -- Unlock operation was successful
else
null; -- Unlock operation failed because of some reason
end if;
lock_ns <= DOTRYLOCK;
-- TRYLOCK Command:
-- To perform a try lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_trylockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing a try lock:
-- synch_trylockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_trylocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the trylock operation:
-- synch_trylocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_TRYLOCKSTA_SUCCESS then the lock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_TRYLOCKSTA_ERROR then the thread did not get the lock
-- because the lock was already owned by another thread.
when DOTRYLOCK =>
addr<=synch_trylockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_trylocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_TRYLOCKSTA_SUCCESS ) then
null; -- Lock was acquired
else
null; -- Lock was already owned by another thread
end if;
lock_ns <= DOSETKIND;
-- SET KIND Command:
-- To perform a kind set operation with the synchronization manager you
-- perform a write to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to set the kind of an mutex:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- Since this is a write operation no status information is returned.
when DOSETKIND =>
-- As write operation
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
lock_ns <= DOGETKIND;
-- GET KIND Command:
-- To perform a get kind operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_kindsta which will gets the kind. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to get the kind of a mutex:
-- synch_kindsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned from this function is one of SYNCH_FAST, SYNCH_RECURS,
-- or SYNCH_ERROR depending on the type of mutex that was returned.
when DOGETKIND =>
-- As read operations
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
kind <= synch_kindsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETCOUNT;
-- GET COUNT Command:
-- To perform a get count operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_countcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_countcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_countsta which will gets the count. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the recursive lock count of a mutex::
-- synch_countsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the recursive lock count.
when DOGETCOUNT =>
addr <= synch_countcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
count <= synch_countsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETOWNER;
-- GET OWNER Command:
-- To perform a get owner operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_ownercmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_ownercmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_ownersta which will gets the owner. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the owner of a mutex::
-- synch_ownersta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the owner of the mutex.
when DOGETOWNER =>
addr <= synch_ownercmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
owner <= synch_ownersta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DONE;
when DONE =>
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity test_cmds is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8;
BASE : std_logic_vector := x"75000000"
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
addr : out std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
datain : in std_logic_vector(0 to C_DWIDTH-1);
kind : out std_logic_vector(0 to 1);
owner : out std_logic_vector(0 to C_TWIDTH-1);
count : out std_logic_vector(0 to C_CWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end test_cmds;
architecture behavioral of test_cmds is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
SETID,
SETMID,
DOLOCK,
DOUNLOCK,
DOTRYLOCK,
DOSETKIND,
DOGETKIND,
DOGETCOUNT,
DOGETOWNER,
DONE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
-- Signals for stuff
signal tid : std_logic_vector(0 to C_TWIDTH-1);
signal mid : std_logic_vector(0 to C_MWIDTH-1);
signal tidn : std_logic_vector(0 to C_TWIDTH-1);
signal midn : std_logic_vector(0 to C_MWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
tid <= (others => '0');
mid <= (others => '0');
else
lock_cs <= lock_ns;
tid <= tidn;
mid <= midn;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
tidn <= tid;
midn <= mid;
case lock_cs is
when IDLE =>
if( start = '1' ) then
if( mikind = "00" ) then
lock_ns <= DOLOCK;
elsif( mikind = "01" ) then
lock_ns <= SETID;
else
lock_ns <= SETMID;
end if;
end if;
when SETID =>
tidn <= miowner;
lock_ns <= IDLE;
when SETMID =>
midn <= mutex;
lock_ns <= IDLE;
-- LOCK Command:
-- To perform a lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_lockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use when locking the mutex
-- and the 7th parameter is the mutex identifier to lock.
--
-- Thus a to generate the address to use when performing a lock operation:
-- synch_lockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_locksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the lock operation:
-- synch_locksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_LOCKSTA_CONTINUE then the lock was
-- successfully locked and the thread can continue to run. If the
-- returned status is SYNCH_LOCKSTA_BLOCK then the thread did not get
-- the lock and should not continue to run.
when DOLOCK =>
addr <= synch_lockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_locksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_LOCKSTA_CONTINUE ) then
null; -- Continue the operation of the core
else
null; -- Halt the operation of the core
end if;
lock_ns <= DOUNLOCK;
-- UNLOCK Command:
-- To perform an unlock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_unlockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use the 7th parameter is the
-- mutex identifier.
--
-- Thus a to generate the address to use when performing an unlock operation:
-- synch_unlockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_unlocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the unlock operation:
-- synch_unlocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_UNLOCKSTA_SUCCESS then the unlock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_UNLOCKSTA_ERROR then the thread did not unlock
-- the lock because some error occurred.
when DOUNLOCK =>
addr <= synch_unlockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if (synch_unlocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_UNLOCKSTA_SUCCESS ) then
null; -- Unlock operation was successful
else
null; -- Unlock operation failed because of some reason
end if;
lock_ns <= DOTRYLOCK;
-- TRYLOCK Command:
-- To perform a try lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_trylockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing a try lock:
-- synch_trylockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_trylocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the trylock operation:
-- synch_trylocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_TRYLOCKSTA_SUCCESS then the lock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_TRYLOCKSTA_ERROR then the thread did not get the lock
-- because the lock was already owned by another thread.
when DOTRYLOCK =>
addr<=synch_trylockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_trylocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_TRYLOCKSTA_SUCCESS ) then
null; -- Lock was acquired
else
null; -- Lock was already owned by another thread
end if;
lock_ns <= DOSETKIND;
-- SET KIND Command:
-- To perform a kind set operation with the synchronization manager you
-- perform a write to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to set the kind of an mutex:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- Since this is a write operation no status information is returned.
when DOSETKIND =>
-- As write operation
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
lock_ns <= DOGETKIND;
-- GET KIND Command:
-- To perform a get kind operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_kindsta which will gets the kind. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to get the kind of a mutex:
-- synch_kindsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned from this function is one of SYNCH_FAST, SYNCH_RECURS,
-- or SYNCH_ERROR depending on the type of mutex that was returned.
when DOGETKIND =>
-- As read operations
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
kind <= synch_kindsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETCOUNT;
-- GET COUNT Command:
-- To perform a get count operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_countcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_countcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_countsta which will gets the count. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the recursive lock count of a mutex::
-- synch_countsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the recursive lock count.
when DOGETCOUNT =>
addr <= synch_countcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
count <= synch_countsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETOWNER;
-- GET OWNER Command:
-- To perform a get owner operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_ownercmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_ownercmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_ownersta which will gets the owner. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the owner of a mutex::
-- synch_ownersta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the owner of the mutex.
when DOGETOWNER =>
addr <= synch_ownercmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
owner <= synch_ownersta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DONE;
when DONE =>
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity test_cmds is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8;
BASE : std_logic_vector := x"75000000"
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
addr : out std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
datain : in std_logic_vector(0 to C_DWIDTH-1);
kind : out std_logic_vector(0 to 1);
owner : out std_logic_vector(0 to C_TWIDTH-1);
count : out std_logic_vector(0 to C_CWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end test_cmds;
architecture behavioral of test_cmds is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
SETID,
SETMID,
DOLOCK,
DOUNLOCK,
DOTRYLOCK,
DOSETKIND,
DOGETKIND,
DOGETCOUNT,
DOGETOWNER,
DONE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
-- Signals for stuff
signal tid : std_logic_vector(0 to C_TWIDTH-1);
signal mid : std_logic_vector(0 to C_MWIDTH-1);
signal tidn : std_logic_vector(0 to C_TWIDTH-1);
signal midn : std_logic_vector(0 to C_MWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
tid <= (others => '0');
mid <= (others => '0');
else
lock_cs <= lock_ns;
tid <= tidn;
mid <= midn;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
tidn <= tid;
midn <= mid;
case lock_cs is
when IDLE =>
if( start = '1' ) then
if( mikind = "00" ) then
lock_ns <= DOLOCK;
elsif( mikind = "01" ) then
lock_ns <= SETID;
else
lock_ns <= SETMID;
end if;
end if;
when SETID =>
tidn <= miowner;
lock_ns <= IDLE;
when SETMID =>
midn <= mutex;
lock_ns <= IDLE;
-- LOCK Command:
-- To perform a lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_lockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use when locking the mutex
-- and the 7th parameter is the mutex identifier to lock.
--
-- Thus a to generate the address to use when performing a lock operation:
-- synch_lockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_locksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the lock operation:
-- synch_locksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_LOCKSTA_CONTINUE then the lock was
-- successfully locked and the thread can continue to run. If the
-- returned status is SYNCH_LOCKSTA_BLOCK then the thread did not get
-- the lock and should not continue to run.
when DOLOCK =>
addr <= synch_lockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_locksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_LOCKSTA_CONTINUE ) then
null; -- Continue the operation of the core
else
null; -- Halt the operation of the core
end if;
lock_ns <= DOUNLOCK;
-- UNLOCK Command:
-- To perform an unlock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_unlockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use the 7th parameter is the
-- mutex identifier.
--
-- Thus a to generate the address to use when performing an unlock operation:
-- synch_unlockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_unlocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the unlock operation:
-- synch_unlocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_UNLOCKSTA_SUCCESS then the unlock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_UNLOCKSTA_ERROR then the thread did not unlock
-- the lock because some error occurred.
when DOUNLOCK =>
addr <= synch_unlockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if (synch_unlocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_UNLOCKSTA_SUCCESS ) then
null; -- Unlock operation was successful
else
null; -- Unlock operation failed because of some reason
end if;
lock_ns <= DOTRYLOCK;
-- TRYLOCK Command:
-- To perform a try lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_trylockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing a try lock:
-- synch_trylockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_trylocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the trylock operation:
-- synch_trylocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_TRYLOCKSTA_SUCCESS then the lock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_TRYLOCKSTA_ERROR then the thread did not get the lock
-- because the lock was already owned by another thread.
when DOTRYLOCK =>
addr<=synch_trylockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_trylocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_TRYLOCKSTA_SUCCESS ) then
null; -- Lock was acquired
else
null; -- Lock was already owned by another thread
end if;
lock_ns <= DOSETKIND;
-- SET KIND Command:
-- To perform a kind set operation with the synchronization manager you
-- perform a write to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to set the kind of an mutex:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- Since this is a write operation no status information is returned.
when DOSETKIND =>
-- As write operation
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
lock_ns <= DOGETKIND;
-- GET KIND Command:
-- To perform a get kind operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_kindsta which will gets the kind. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to get the kind of a mutex:
-- synch_kindsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned from this function is one of SYNCH_FAST, SYNCH_RECURS,
-- or SYNCH_ERROR depending on the type of mutex that was returned.
when DOGETKIND =>
-- As read operations
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
kind <= synch_kindsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETCOUNT;
-- GET COUNT Command:
-- To perform a get count operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_countcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_countcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_countsta which will gets the count. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the recursive lock count of a mutex::
-- synch_countsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the recursive lock count.
when DOGETCOUNT =>
addr <= synch_countcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
count <= synch_countsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETOWNER;
-- GET OWNER Command:
-- To perform a get owner operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_ownercmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_ownercmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_ownersta which will gets the owner. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the owner of a mutex::
-- synch_ownersta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the owner of the mutex.
when DOGETOWNER =>
addr <= synch_ownercmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
owner <= synch_ownersta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DONE;
when DONE =>
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity test_cmds is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8;
BASE : std_logic_vector := x"75000000"
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
addr : out std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
datain : in std_logic_vector(0 to C_DWIDTH-1);
kind : out std_logic_vector(0 to 1);
owner : out std_logic_vector(0 to C_TWIDTH-1);
count : out std_logic_vector(0 to C_CWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end test_cmds;
architecture behavioral of test_cmds is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
SETID,
SETMID,
DOLOCK,
DOUNLOCK,
DOTRYLOCK,
DOSETKIND,
DOGETKIND,
DOGETCOUNT,
DOGETOWNER,
DONE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
-- Signals for stuff
signal tid : std_logic_vector(0 to C_TWIDTH-1);
signal mid : std_logic_vector(0 to C_MWIDTH-1);
signal tidn : std_logic_vector(0 to C_TWIDTH-1);
signal midn : std_logic_vector(0 to C_MWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
tid <= (others => '0');
mid <= (others => '0');
else
lock_cs <= lock_ns;
tid <= tidn;
mid <= midn;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
tidn <= tid;
midn <= mid;
case lock_cs is
when IDLE =>
if( start = '1' ) then
if( mikind = "00" ) then
lock_ns <= DOLOCK;
elsif( mikind = "01" ) then
lock_ns <= SETID;
else
lock_ns <= SETMID;
end if;
end if;
when SETID =>
tidn <= miowner;
lock_ns <= IDLE;
when SETMID =>
midn <= mutex;
lock_ns <= IDLE;
-- LOCK Command:
-- To perform a lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_lockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use when locking the mutex
-- and the 7th parameter is the mutex identifier to lock.
--
-- Thus a to generate the address to use when performing a lock operation:
-- synch_lockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_locksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the lock operation:
-- synch_locksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_LOCKSTA_CONTINUE then the lock was
-- successfully locked and the thread can continue to run. If the
-- returned status is SYNCH_LOCKSTA_BLOCK then the thread did not get
-- the lock and should not continue to run.
when DOLOCK =>
addr <= synch_lockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_locksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_LOCKSTA_CONTINUE ) then
null; -- Continue the operation of the core
else
null; -- Halt the operation of the core
end if;
lock_ns <= DOUNLOCK;
-- UNLOCK Command:
-- To perform an unlock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_unlockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use the 7th parameter is the
-- mutex identifier.
--
-- Thus a to generate the address to use when performing an unlock operation:
-- synch_unlockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_unlocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the unlock operation:
-- synch_unlocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_UNLOCKSTA_SUCCESS then the unlock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_UNLOCKSTA_ERROR then the thread did not unlock
-- the lock because some error occurred.
when DOUNLOCK =>
addr <= synch_unlockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if (synch_unlocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_UNLOCKSTA_SUCCESS ) then
null; -- Unlock operation was successful
else
null; -- Unlock operation failed because of some reason
end if;
lock_ns <= DOTRYLOCK;
-- TRYLOCK Command:
-- To perform a try lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_trylockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing a try lock:
-- synch_trylockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_trylocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the trylock operation:
-- synch_trylocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_TRYLOCKSTA_SUCCESS then the lock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_TRYLOCKSTA_ERROR then the thread did not get the lock
-- because the lock was already owned by another thread.
when DOTRYLOCK =>
addr<=synch_trylockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_trylocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_TRYLOCKSTA_SUCCESS ) then
null; -- Lock was acquired
else
null; -- Lock was already owned by another thread
end if;
lock_ns <= DOSETKIND;
-- SET KIND Command:
-- To perform a kind set operation with the synchronization manager you
-- perform a write to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to set the kind of an mutex:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- Since this is a write operation no status information is returned.
when DOSETKIND =>
-- As write operation
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
lock_ns <= DOGETKIND;
-- GET KIND Command:
-- To perform a get kind operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_kindsta which will gets the kind. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to get the kind of a mutex:
-- synch_kindsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned from this function is one of SYNCH_FAST, SYNCH_RECURS,
-- or SYNCH_ERROR depending on the type of mutex that was returned.
when DOGETKIND =>
-- As read operations
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
kind <= synch_kindsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETCOUNT;
-- GET COUNT Command:
-- To perform a get count operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_countcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_countcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_countsta which will gets the count. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the recursive lock count of a mutex::
-- synch_countsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the recursive lock count.
when DOGETCOUNT =>
addr <= synch_countcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
count <= synch_countsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETOWNER;
-- GET OWNER Command:
-- To perform a get owner operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_ownercmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_ownercmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_ownersta which will gets the owner. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the owner of a mutex::
-- synch_ownersta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the owner of the mutex.
when DOGETOWNER =>
addr <= synch_ownercmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
owner <= synch_ownersta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DONE;
when DONE =>
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity test_cmds is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8;
BASE : std_logic_vector := x"75000000"
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
addr : out std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
datain : in std_logic_vector(0 to C_DWIDTH-1);
kind : out std_logic_vector(0 to 1);
owner : out std_logic_vector(0 to C_TWIDTH-1);
count : out std_logic_vector(0 to C_CWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end test_cmds;
architecture behavioral of test_cmds is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
SETID,
SETMID,
DOLOCK,
DOUNLOCK,
DOTRYLOCK,
DOSETKIND,
DOGETKIND,
DOGETCOUNT,
DOGETOWNER,
DONE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
-- Signals for stuff
signal tid : std_logic_vector(0 to C_TWIDTH-1);
signal mid : std_logic_vector(0 to C_MWIDTH-1);
signal tidn : std_logic_vector(0 to C_TWIDTH-1);
signal midn : std_logic_vector(0 to C_MWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
tid <= (others => '0');
mid <= (others => '0');
else
lock_cs <= lock_ns;
tid <= tidn;
mid <= midn;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
tidn <= tid;
midn <= mid;
case lock_cs is
when IDLE =>
if( start = '1' ) then
if( mikind = "00" ) then
lock_ns <= DOLOCK;
elsif( mikind = "01" ) then
lock_ns <= SETID;
else
lock_ns <= SETMID;
end if;
end if;
when SETID =>
tidn <= miowner;
lock_ns <= IDLE;
when SETMID =>
midn <= mutex;
lock_ns <= IDLE;
-- LOCK Command:
-- To perform a lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_lockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use when locking the mutex
-- and the 7th parameter is the mutex identifier to lock.
--
-- Thus a to generate the address to use when performing a lock operation:
-- synch_lockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_locksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the lock operation:
-- synch_locksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_LOCKSTA_CONTINUE then the lock was
-- successfully locked and the thread can continue to run. If the
-- returned status is SYNCH_LOCKSTA_BLOCK then the thread did not get
-- the lock and should not continue to run.
when DOLOCK =>
addr <= synch_lockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_locksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_LOCKSTA_CONTINUE ) then
null; -- Continue the operation of the core
else
null; -- Halt the operation of the core
end if;
lock_ns <= DOUNLOCK;
-- UNLOCK Command:
-- To perform an unlock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_unlockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use the 7th parameter is the
-- mutex identifier.
--
-- Thus a to generate the address to use when performing an unlock operation:
-- synch_unlockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_unlocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the unlock operation:
-- synch_unlocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_UNLOCKSTA_SUCCESS then the unlock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_UNLOCKSTA_ERROR then the thread did not unlock
-- the lock because some error occurred.
when DOUNLOCK =>
addr <= synch_unlockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if (synch_unlocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_UNLOCKSTA_SUCCESS ) then
null; -- Unlock operation was successful
else
null; -- Unlock operation failed because of some reason
end if;
lock_ns <= DOTRYLOCK;
-- TRYLOCK Command:
-- To perform a try lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_trylockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing a try lock:
-- synch_trylockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_trylocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the trylock operation:
-- synch_trylocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_TRYLOCKSTA_SUCCESS then the lock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_TRYLOCKSTA_ERROR then the thread did not get the lock
-- because the lock was already owned by another thread.
when DOTRYLOCK =>
addr<=synch_trylockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_trylocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_TRYLOCKSTA_SUCCESS ) then
null; -- Lock was acquired
else
null; -- Lock was already owned by another thread
end if;
lock_ns <= DOSETKIND;
-- SET KIND Command:
-- To perform a kind set operation with the synchronization manager you
-- perform a write to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to set the kind of an mutex:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- Since this is a write operation no status information is returned.
when DOSETKIND =>
-- As write operation
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
lock_ns <= DOGETKIND;
-- GET KIND Command:
-- To perform a get kind operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_kindsta which will gets the kind. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to get the kind of a mutex:
-- synch_kindsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned from this function is one of SYNCH_FAST, SYNCH_RECURS,
-- or SYNCH_ERROR depending on the type of mutex that was returned.
when DOGETKIND =>
-- As read operations
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
kind <= synch_kindsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETCOUNT;
-- GET COUNT Command:
-- To perform a get count operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_countcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_countcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_countsta which will gets the count. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the recursive lock count of a mutex::
-- synch_countsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the recursive lock count.
when DOGETCOUNT =>
addr <= synch_countcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
count <= synch_countsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETOWNER;
-- GET OWNER Command:
-- To perform a get owner operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_ownercmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_ownercmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_ownersta which will gets the owner. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the owner of a mutex::
-- synch_ownersta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the owner of the mutex.
when DOGETOWNER =>
addr <= synch_ownercmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
owner <= synch_ownersta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DONE;
when DONE =>
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
|
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9nlS3BloLZCcOD52QKA=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4864)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4864)
`protect data_block
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`protect begin_protected
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rYZ/9U/is9XqAQni7cjqNC+g45FXaXGvlEJ9FmkSozCnZxh1db4uuI96Ykxwbo8FF+c5XnqJUxJN
2V2u4eyFD31UArpVC/EO/ayVLLFyWjCbKc3vZejwVvHomM1FqOPFSTCg0VFfxNa4hj8nKFYnLtfS
WuwR9f9zFYCvY4/tSzEaK5b1ETYyMoRkqJSyk5KoxzHAunZY7JEdaAI5Tlphie8jLAf6ZC61fPCX
y9zg3MkjAn23ibFvU0X/2aD9Cuq+htaOFbnodoyZxKr5JwLnxYbcaCEpLyjqYOorbb3gOz11/Biu
15wpZbstVqt+6xzjtDnTtxFu1aVXfYLYgUgc8uYhPwCl9BMKY2bPlZK3wmlAocmoGF5EbCpBcgJc
7oQjlDdvi1yxF3bR7Jmn6T4zDellh8llnIELRfTZ9l0O5D0n2DFlIO2KQHAD+6YhFFsNrdPsv31+
nCipYp9R83K3N5irYk1dv2G1ZA==
`protect end_protected
|
-------------------------------------------------------------------------------
-- Design : Register array acting as data cache
-- Project : Tomasulo Processor
-- Author : Rohit Goel
-- Company : University of Southern California
-- Following is the VHDL code for a dual-port RAM with a write clock.
-- There is no read clock. The read port is not a clocked port.
-- This is actually a register array. with no input or output registers.
-- ===================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ls_buffer_ram_reg_array is
generic (ADDR_WIDTH: integer := 6; DATA_WIDTH: integer := 32);
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector (ADDR_WIDTH-1 downto 0);
dia : in std_logic_vector (DATA_WIDTH-1 downto 0);
addrb : in std_logic_vector (ADDR_WIDTH-1 downto 0);
dob : out std_logic_vector (DATA_WIDTH-1 downto 0);
rea : in std_logic ;
mem_wri : out std_logic ;
mem_exc : out std_logic ;
mem_read : out std_logic
-- modified by kapil
--addrc : in std_logic_vector(ADDR_WIDTH-1 downto 0);
--doc : out std_logic_vector(DATA_WIDTH-1 downto 0)
-- end modified by kapil
);
end entity ls_buffer_ram_reg_array;
architecture syn of ls_buffer_ram_reg_array is
type ram_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal RAM : ram_type :=
( X"0000_FFFF", X"0000_0010", X"0000_0020", X"0000_0030", -- 00 04 08 0c
X"0000_0040", X"0000_0050", X"0000_0060", X"0000_0070",
X"0000_0080", X"0000_0001", X"0000_0002", X"0000_00B0",
X"0000_00C0", X"0000_00D0", X"0000_00E0", X"0000_00F0",
X"0000_0100", X"0000_0110", X"0000_0120", X"0000_0130",
X"0000_0140", X"0000_0150", X"0000_0160", X"0000_0170",
X"0000_0180", X"0000_0190", X"0000_01A0", X"0000_01B0",
X"0000_01C0", X"0000_01D0", X"0000_01E0", X"0000_01F0",
X"0000_0200", X"0000_0210", X"0000_0220", X"0000_0230",
X"0000_0240", X"0000_0250", X"0000_0260", X"0000_0270",
X"0000_0280", X"0000_0290", X"0000_02A0", X"0000_02B0",
X"0000_02C0", X"0000_02D0", X"0000_02E0", X"0000_02F0",
X"0000_0300", X"0000_0310", X"0000_0320", X"0000_0330",
X"0000_0340", X"0000_0350", X"0000_0360", X"0000_0370",
X"0000_0380", X"0000_0390", X"0000_03A0", X"0000_03B0",
X"0000_03C0", X"0000_03D0", X"0000_03E0", X"0000_03F0"
);
-- signal read_addrb : std_logic_vector(1 downto 0) := "00";
--signal doc_async : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
process (clka)
begin
if (clka'event and clka = '1') then
mem_read <= rea ;
dob <= RAM(conv_integer(addrb));
mem_wri <= '0' ;
mem_exc <= '0';
if (wea = '1') then
RAM(conv_integer(addra)) <= dia;
mem_wri <= '1' ;
mem_exc <= '0';
else
end if;
end if;
end process;
--doc <= RAM(conv_integer(addrc)); -- not a clocked-port
end architecture syn;
-----------------------------------------------------------------------------
|
---- Memory ------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.processor_functions.all;
------------------------------------------------------------------------------------------------------------------
ENTITY memory IS
PORT (clk, nrst: IN STD_LOGIC; -- reset ativo em zero
MDR_load: IN STD_LOGIC; -- sinal de carregamento do BUS para MDR
MAR_load: IN STD_LOGIC; -- sinal de carregamento do BUS para MAR
MEM_valid: IN STD_LOGIC; -- sinal que indica que o resultado da MDR deve ser colocado em MEM_bus (ou Z se 0)
MEM_en: IN STD_LOGIC; -- ativacao da memorica para operacoes de leitura e escrita
MEM_rw: IN STD_LOGIC; -- flag que indica se a operacao a ser realizada eh de leitura ou escrita
MEM_bus: INOUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)); -- barramento de entrada/saida
END ENTITY memory;
------------------------------------------------------------------------------------------------------------------
ARCHITECTURE rtl OF memory IS
SIGNAL mdr: STD_LOGIC_VECTOR(wordlen-1 DOWNTO 0); -- registrador de dados
SIGNAL mar: UNSIGNED(wordlen-oplen-1 DOWNTO 0); -- registrador de enderecos
BEGIN
-- Se o MEM_valid = '1', manda o valor do resultado do MDR pro barramento. Caso contrario, manda Z.
MEM_bus <= mdr
WHEN MEM_valid = '1'
ELSE (others => 'Z');
PROCESS (clk, nrst) IS
VARIABLE contents: memory_array; -- conteudo da memoria
-- Definicao do valor padrao da memoria (para simular ROM com programa)
CONSTANT program: memory_array := (0 => "000000000011",
1 => "001000000100",
2 => "000100000101",
3 => "000000001100",
4 => "000000000011",
5 => "000000000000" ,
OTHERS => (OTHERS => '0'));
BEGIN
-- De forma assincrona, se o reset ficar em nivel 0, reseta os registradores e conteudo da memoria
IF nrst = '0' THEN
mdr <= (OTHERS => '0');
mar <= (OTHERS => '0');
contents := program;
-- Se teve uma borda de subida no clock, faz as outras coisas
ELSIF (clk'EVENT AND clk='1') THEN
-- A ordem de prioridade eh: Carregamento do MAR, Carregamento do MDR e leitura/escrita
IF MAR_load = '1' THEN
mar <= UNSIGNED(MEM_bus(n-oplen-1 DOWNTO 0)); -- Para carregar MAR, basta ler o endereco do que tem no BUS (desconsidera o OPCODE)
ELSIF MDR_load = '1' THEN
mdr <= MEM_bus; -- Para carregar MDR, basta ler direto do BUS
ELSIF MEM_en = '1' THEN
IF MEM_rw = '0' THEN
mdr <= contents(to_integer(mar)); -- Se for leitura, pega o conteudo do endereco salvo em MAR e manda para MDR
ELSE
contents(to_integer(mar)) := mdr; -- Se for escrita, escreve MDR no endereco salvo em MAR
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
------------------------------------------------------------------------------------------------------------------ |
-------------------------------------------------------------------------------
-- Title : tb_wave_gen
-- Project : Exercise 06
-------------------------------------------------------------------------------
-- File : tb_wave_gen.vhd
-- Author : Erno Salminen <ege@tiibetinhanhi.cs.tut.fi>
-- Company :
-- Last update: 2008/12/19
-- Platform :
-------------------------------------------------------------------------------
-- Description: Stimulus generation for wave generator. NOTE! This does not
-- check the validity of DUV's output signal!
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2008/12/19 1.0 ege Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_wave_gen IS
END tb_wave_gen;
ARCHITECTURE testbench OF tb_wave_gen IS
-- CONSTANT width_c : INTEGER := 6;
-- CONSTANT width_c : INTEGER := 16;
CONSTANT width_c : INTEGER := 8;
-- Set the clk period and total simulation length
CONSTANT period_c : TIME := 10 NS; -- 10 ns = 100 MHz
CONSTANT sim_duration_c : TIME := 1 MS;
-- Set the time when generator is cleared synchronously
CONSTANT clear_delay_c : INTEGER := 74000;
CONSTANT clear_duration_c : INTEGER := 6000;
-- Signals for the DUV
SIGNAL clk : STD_LOGIC := '0';
SIGNAL rst_n : STD_LOGIC := '0';
TYPE output_array IS ARRAY (1 TO 4) OF STD_LOGIC_VECTOR(width_c-1 DOWNTO 0);
SIGNAL output : output_array;
SIGNAL sync_clear : STD_LOGIC;
-- These are for assistants. These store the largest and smallest
-- values from each generator.
SIGNAL maxim : output_array;
SIGNAL minim : output_array;
COMPONENT wave_gen
GENERIC (
width_g : INTEGER;
step_g : INTEGER);
PORT (
rst_n : IN STD_LOGIC;
clk : IN STD_LOGIC;
sync_clear_in : IN STD_LOGIC;
value_out : OUT STD_LOGIC_VECTOR(width_g-1 DOWNTO 0));
END COMPONENT;
SIGNAL sync_clear_old_r : STD_LOGIC;
CONSTANT zero_c : STD_LOGIC_VECTOR( width_c-1 DOWNTO 0 ) := (OTHERS => '0');
SIGNAL endsim : STD_LOGIC := '0';
BEGIN -- testbench
clk <= NOT clk AFTER period_c/2;
rst_n <= '1' AFTER period_c*4;
-- Create synchronous clear signal
sync_clear <= '0',
'1' AFTER period_c*clear_delay_c,
'0' AFTER period_c*(clear_delay_c+clear_duration_c);
g_wave_gen : FOR step IN 1 TO 4 GENERATE
i_wave_gen : wave_gen
GENERIC MAP (
width_g => width_c,
step_g => step
)
PORT MAP (
rst_n => rst_n,
clk => clk,
sync_clear_in => sync_clear,
value_out => output(step)
);
END GENERATE g_wave_gen;
-- CUSTOM process for assistant
sync_test : PROCESS (clk, rst_n)
BEGIN -- PROCESS sync_test
IF rst_n = '0' THEN -- asynchronous reset (active low)
maxim <= (OTHERS => (OTHERS => '0') );
minim <= (OTHERS => (OTHERS => '0') );
sync_clear_old_r <= '0';
ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
sync_clear_old_r <= sync_clear;
FOR i IN 1 TO 4 LOOP
IF SIGNED(output(i)) > SIGNED(maxim(i)) THEN
maxim(i) <= output(i);
END IF;
IF SIGNED(output(i)) < SIGNED(minim(i)) THEN
minim(i) <= output(i);
END IF;
ASSERT sync_clear_old_r = '0' OR output(i) = zero_c
REPORT "Sync clear failed" SEVERITY ERROR;
END LOOP; -- i
END IF;
END PROCESS sync_test;
-- Stop the simulation
endsim <= '1' AFTER sim_duration_c;
ASSERT endsim = '0' REPORT "Simulation done" SEVERITY FAILURE;
END testbench;
|
-------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric buffered packet sink
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : xwb_fabric_sink.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-16
-- Last update: 2012-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple WB packet streaming sink with builtin FIFO buffer.
-- Outputs a trivial interface (start-of-packet, end-of-packet, data-valid)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-16 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
entity xwb_fabric_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end xwb_fabric_sink;
architecture rtl of xwb_fabric_sink is
constant c_fifo_width : integer := 16 + 2 + 4;
signal q_valid, full, we, rd : std_logic;
signal fin, fout, fout_reg : std_logic_vector(c_fifo_width-1 downto 0);
signal cyc_d0, rd_d0 : std_logic;
signal pre_sof, pre_eof, pre_bytesel, pre_dvalid : std_logic;
signal post_sof, post_dvalid : std_logic;
signal post_addr : std_logic_vector(1 downto 0);
signal post_data : std_logic_vector(15 downto 0);
signal snk_out : t_wrf_sink_out;
begin -- rtl
p_delay_cyc_and_rd : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cyc_d0 <= '0';
rd_d0 <= '0';
else
if(full = '0') then
cyc_d0 <= snk_i.cyc;
end if;
rd_d0 <= rd;
end if;
end if;
end process;
pre_sof <= snk_i.cyc and not cyc_d0; -- sof
pre_eof <= not snk_i.cyc and cyc_d0; -- eof
pre_bytesel <= not snk_i.sel(0); -- bytesel
pre_dvalid <= snk_i.stb and snk_i.we and snk_i.cyc and not snk_out.stall; -- data valid
fin(15 downto 0) <= snk_i.dat;
fin(17 downto 16) <= snk_i.adr;
fin(21 downto 18) <= pre_sof & pre_eof & pre_bytesel & pre_dvalid;
snk_out.stall <= full or (snk_i.cyc and not cyc_d0);
snk_out.err <= '0';
snk_out.rty <= '0';
p_gen_ack : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
snk_out.ack <= '0';
else
snk_out.ack <= snk_i.cyc and snk_i.stb and snk_i.we and not snk_out.stall;
end if;
end if;
end process;
snk_o <= snk_out;
we <= '1' when fin(21 downto 18) /= "0000" and full = '0' else '0';
rd <= q_valid and dreq_i and not post_sof;
U_FIFO : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => 16)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fin,
we_i => we,
q_o => fout,
rd_i => rd,
almost_full_o => full,
q_valid_o => q_valid);
p_fout_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fout_reg <= (others => '0');
elsif(rd = '1') then
fout_reg <= fout;
end if;
end if;
end process;
post_data <= fout_reg(15 downto 0);
post_addr <= fout_reg(17 downto 16);
post_sof <= fout_reg(21) and rd_d0; --and q_valid;
post_dvalid <= fout_reg(18);
sof_o <= post_sof and rd_d0;
dvalid_o <= post_dvalid and rd_d0;
error_o <= '1' when rd_d0 = '1' and (post_addr = c_WRF_STATUS) and (f_unmarshall_wrf_status(post_data).error = '1') else '0';
eof_o <= fout_reg(20) and rd_d0;
bytesel_o <= fout_reg(19);
data_o <= post_data;
addr_o <= post_addr;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
entity wb_fabric_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_dat_i : in std_logic_vector(15 downto 0);
snk_adr_i : in std_logic_vector(1 downto 0);
snk_sel_i : in std_logic_vector(1 downto 0);
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_ack_o : out std_logic;
snk_err_o : out std_logic;
snk_rty_o : out std_logic;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end wb_fabric_sink;
architecture wrapper of wb_fabric_sink is
component xwb_fabric_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic);
end component;
signal snk_in : t_wrf_sink_in;
signal snk_out : t_wrf_sink_out;
begin -- wrapper
U_Wrapped_Sink : xwb_fabric_sink
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
snk_i => snk_in,
snk_o => snk_out,
addr_o => addr_o,
data_o => data_o,
dvalid_o => dvalid_o,
sof_o => sof_o,
eof_o => eof_o,
error_o => error_o,
bytesel_o => bytesel_o,
dreq_i => dreq_i);
snk_in.adr <= snk_adr_i;
snk_in.dat <= snk_dat_i;
snk_in.stb <= snk_stb_i;
snk_in.we <= snk_we_i;
snk_in.cyc <= snk_cyc_i;
snk_in.sel <= snk_sel_i;
snk_stall_o <= snk_out.stall;
snk_ack_o <= snk_out.ack;
snk_err_o <= snk_out.err;
snk_rty_o <= snk_out.rty;
end wrapper;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\Shifter_8_bit.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Shifter_8_bit
-- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit/Shifter (8-bit)
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Shifter_8_bit IS
PORT( select_rsvd : IN std_logic_vector(1 DOWNTO 0); -- ufix2
input : IN std_logic_vector(7 DOWNTO 0); -- int8
in_flags : IN std_logic_vector(3 DOWNTO 0); -- ufix4
out_flags : OUT std_logic_vector(3 DOWNTO 0); -- ufix4
shift_out : OUT std_logic_vector(7 DOWNTO 0) -- int8
);
END Shifter_8_bit;
ARCHITECTURE rtl OF Shifter_8_bit IS
-- Functions
-- HDLCODER_TO_STDLOGIC
FUNCTION hdlcoder_to_stdlogic(arg: boolean) RETURN std_logic IS
BEGIN
IF arg THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END FUNCTION;
-- Signals
SIGNAL select_unsigned : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL input_signed : signed(7 DOWNTO 0); -- int8
SIGNAL in_flags_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL out_flags_tmp : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL shift_out_tmp : signed(7 DOWNTO 0); -- int8
BEGIN
select_unsigned <= unsigned(select_rsvd);
input_signed <= signed(input);
in_flags_unsigned <= unsigned(in_flags);
Shifter_8_bit_1_output : PROCESS (select_unsigned, input_signed, in_flags_unsigned)
VARIABLE c_out : std_logic;
VARIABLE sign_bit : std_logic;
VARIABLE is_zero : unsigned(7 DOWNTO 0);
VARIABLE zero_ufix1 : std_logic;
VARIABLE c_uint : std_logic;
VARIABLE c : signed(7 DOWNTO 0);
VARIABLE c_0 : BOOLEAN;
BEGIN
--MATLAB Function 'CPU_Subsystem_8_bit/Shifter (8-bit)': '<S11>:1'
-- An 8-bit shifter:
-- select = 1 => shift left by 1 bit
-- select = 2 => shift right by 1 bit
-- otherwise, pass the input
-- HDL specific fimath
-- Overflow (V)
--'<S11>:1:16'
c_uint := in_flags_unsigned(1);
-- Carry (C)
--'<S11>:1:19'
c_out := in_flags_unsigned(3);
CASE select_unsigned IS
WHEN "01" =>
-- shift left
-- affects C and V as well
--'<S11>:1:25'
c := input_signed sll 1;
-- Carry (C)
--'<S11>:1:27'
c_out := input_signed(7);
-- Overflow (V)
--'<S11>:1:29'
c_uint := input_signed(7) XOR input_signed(6);
WHEN "10" =>
-- shift right
--'<S11>:1:32'
c := SHIFT_RIGHT(input_signed , 1);
WHEN OTHERS =>
-- pass the input
--'<S11>:1:35'
c := input_signed;
END CASE;
-- Negativity (N)
--'<S11>:1:39'
sign_bit := c(7);
-- Is Zero? (Z)
--'<S11>:1:42'
c_0 := NOT (c /= 0);
is_zero := '0' & '0' & '0' & '0' & '0' & '0' & '0' & hdlcoder_to_stdlogic(c_0);
--'<S11>:1:43'
zero_ufix1 := is_zero(0);
-- Set [C, N, V, Z] in the flag register
--'<S11>:1:46'
out_flags_tmp <= unsigned'(c_out & sign_bit & c_uint & zero_ufix1);
shift_out_tmp <= c;
END PROCESS Shifter_8_bit_1_output;
out_flags <= std_logic_vector(out_flags_tmp);
shift_out <= std_logic_vector(shift_out_tmp);
END rtl;
|
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- ADS1281 filter package.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ads1281_filter_pkg is
-- Number of ADS1281 filter channels
constant ads1281_filter_num_channels_c : positive := 3;
-- Type for filter results
type ads1281_filter_result_t is array (0 to ads1281_filter_num_channels_c - 1) of std_ulogic_vector(23 downto 0);
end package ads1281_filter_pkg;
package body ads1281_filter_pkg is
end package body ads1281_filter_pkg;
|
------------------------------------------------------------------------------
-- @file adder_full.vhd
-- @brief Implementes a simple 1 bit half adder that can be used to make full
-- adders and vector adders.
-- @see adder_full_tb
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- Computes the sum and carry bit for two input bits and a carry in bit.
--
entity adder_full is
port(
in_0 : in std_logic;
in_1 : in std_logic;
carry_in : in std_logic;
sum : out std_logic;
carry_out : out std_logic
);
end entity adder_full;
architecture rtl of adder_full is
signal i0_xor_i1 : std_logic;
signal i0_and_i1 : std_logic;
signal ci_and_xor: std_logic;
begin
i0_xor_i1 <= in_0 xor in_1;
i0_and_i1 <= in_0 and in_1;
ci_and_xor <= i0_xor_i1 and carry_in;
sum <= i0_xor_i1 xor carry_in;
carry_out <= ci_and_xor or i0_and_i1;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- implements n-th order prbs with common polynomials y = x^n + x^(n-1) + 1
entity prbs is
generic (
n : positive;
width : positive
);
port (
clk : in std_logic;
clk_en : in std_logic;
rst : in std_logic;
q : out std_logic_vector(width-1 downto 0);
def_val : in std_logic_vector(n-1 downto 0)
);
end entity prbs;
architecture rtl of prbs is
signal sr : std_logic_vector(n-1 downto 0) := def_val;
begin
process
begin
wait until rising_edge(clk);
if rst = '1' then
sr <= def_val;
elsif clk_en = '1' then
for i in 0 to width-1 loop
sr(width-1-i) <= sr(n-1-i) xor sr(n-2-i);
end loop;
for i in 0 to n-width-1 loop
sr(width+i) <= sr(i);
end loop;
end if;
end process;
bla : for i in 0 to width-1 generate
q(width-1-i) <= sr(n-1-i) xor sr(n-2-i);
end generate bla;
assert (n>width) report "mode not supported: n should be greater than width" severity failure;
end architecture rtl;
|
entity tb_if02 is
end tb_if02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_if02 is
signal i, o: std_logic_vector(7 downto 0);
signal s : std_logic;
begin
dut: entity work.if02
port map (i, s, o);
process
begin
i <= b"01011010";
s <= '0';
wait for 1 ns;
assert o = x"2d" severity failure;
i <= b"01011010";
s <= '1';
wait for 1 ns;
assert o = x"b4" severity failure;
wait;
end process;
end behav;
|
-- $Id$
--
------------------------------------------------------------------------------
-- Package Name: avmblib
-- Description: Avnet MicroBoard components
--
-- Dependencies: -
-- Tool versions: xst 13.4; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-24 ??? 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package avmblib is
component avmb_aif is -- Avnet MicroBoard, abstract iface, base
port (
I_CLK40 : in slbit; -- 40 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- avmb switches
I_BTN : in slv1; -- avmb button
O_LED : out slv4 -- avmb leds
);
end component;
component avmb_fusp_aif is -- Avnet MicroBoard, abstract iface, base+fusp
port (
I_CLK40 : in slbit; -- 40 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- avmb switches
I_BTN : in slv1; -- avmb button
O_LED : out slv4; -- avmb leds
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end component;
end package avmblib;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
entity ram is
generic(
depth : integer;
width : integer
);
port(
ctrl : in ctrl_t;
read_addr : in unsigned(integer(ceil(log2(real(depth)))) -1 downto 0);
next_write_addr : in unsigned(integer(ceil(log2(real(depth)))) -1 downto 0);
write_enable : in std_logic;
write_in : in std_logic_vector(width - 1 downto 0);
read_out : out std_logic_vector(width - 1 downto 0)
);
end;
--synthesize a dual port block ram
architecture rtl of ram is
type ram_type is array (0 to depth - 1) of std_logic_vector (width - 1 downto 0);
-- This signal is preinitialized as zeroes to remove simulation warnings..
-- we don't actually need to zero this.
--
-- also when simulating under xst, if a warning 3035 is generated relating to
-- size mismatch which may cause simulation errors, this is because depth is
-- not a power of 2.
signal ram : ram_type := (others => (others => '0'));
begin
ram_proc : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if write_enable = '1' then
ram(to_integer(next_write_addr)) <= write_in;
end if;
read_out <= ram(to_integer(read_addr));
end if;
end process;
end;
|
entity top2 is
generic (
ok : boolean := false
);
port (
clk : in bit;
inp : in bit;
outp : out bit);
end;
architecture beh of top2 is
begin
assert ok report "my assert message";
outp <= inp;
end beh;
|
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_execution_unit.vhd
--!
--! @brief fpgaMSP430 Execution unit
--
--! @author Olivier Girard, olgirard@gmail.com
--! @author Emmanuel Amadio, emmanuel.amadio@gmail.com (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fmsp_core_package.all;
use work.fmsp_functions.all;
entity fmsp_execution_unit is
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
dbg_halt_st : in std_logic; --! Halt/Run status from CPU
dbg_mem_dout : in std_logic_vector(15 downto 0); --! Debug unit data output
dbg_reg_wr : in std_logic; --! Debug unit CPU register write
e_state : in std_logic_vector(3 downto 0); --! Execution state
exec_done : in std_logic; --! Execution completed
inst_ad : in std_logic_vector(7 downto 0); --! Decoded Inst: destination addressing mode
inst_as : in std_logic_vector(7 downto 0); --! Decoded Inst: source addressing mode
inst_alu : in std_logic_vector(11 downto 0); --! ALU control signals
inst_bw : in std_logic; --! Decoded Inst: byte width
inst_dest : in std_logic_vector(15 downto 0); --! Decoded Inst: destination (one hot)
inst_dext : in std_logic_vector(15 downto 0); --! Decoded Inst: destination extended instruction word
inst_irq_rst : in std_logic; --! Decoded Inst: reset interrupt
inst_jmp : in std_logic_vector(7 downto 0); --! Decoded Inst: Conditional jump
inst_mov : in std_logic; --! Decoded Inst: mov instruction
inst_sext : in std_logic_vector(15 downto 0); --! Decoded Inst: source extended instruction word
inst_so : in std_logic_vector(7 downto 0); --! Decoded Inst: Single-operand arithmetic
inst_src : in std_logic_vector(15 downto 0); --! Decoded Inst: source (one hot)
inst_type : in std_logic_vector(2 downto 0); --! Decoded Instruction type
mdb_in : in std_logic_vector(15 downto 0); --! Memory data bus input
pc : in std_logic_vector(15 downto 0); --! Program counter
pc_nxt : in std_logic_vector(15 downto 0); --! Next d.pc value (for CALL & IRQ)
--! OUTPUTs
cpuoff : out std_logic; --! Turns off the CPU
dbg_reg_din : out std_logic_vector(15 downto 0); --! Debug unit CPU register data input
gie : out std_logic; --! General interrupt enable
mab : out std_logic_vector(15 downto 0); --! Memory address bus
mb_en : out std_logic; --! Memory bus enable
mb_wr : out std_logic_vector(1 downto 0); --! Memory bus write transfer
mdb_out : out std_logic_vector(15 downto 0); --! Memory data bus output
oscoff : out std_logic; --! Turns off LFXT1 clock input
pc_sw : out std_logic_vector(15 downto 0); --! Program counter software value
pc_sw_wr : out std_logic; --! Program counter software write
scg0 : out std_logic; --! System clock generator 1. Turns off te DCO
scg1 : out std_logic --! System clock generator 1. Turns off the SMCLK
);
end entity fmsp_execution_unit;
architecture RTL of fmsp_execution_unit is
type fmsp_execution_unit_in_type is record
dbg_halt_st : std_logic; --! Halt/Run status from CPU
dbg_mem_dout : std_logic_vector(15 downto 0); --! Debug unit data output
dbg_reg_wr : std_logic; --! Debug unit CPU register write
e_state : std_logic_vector(3 downto 0); --! Execution state
exec_done : std_logic; --! Execution completed
inst_ad : std_logic_vector(7 downto 0); --! Decoded Inst: destination addressing mode
inst_as : std_logic_vector(7 downto 0); --! Decoded Inst: source addressing mode
inst_alu : std_logic_vector(11 downto 0); --! ALU control signals
inst_bw : std_logic; --! Decoded Inst: byte width
inst_dest : std_logic_vector(15 downto 0); --! Decoded Inst: destination (one hot)
inst_dext : std_logic_vector(15 downto 0); --! Decoded Inst: destination extended instruction word
inst_irq_rst : std_logic; --! Decoded Inst: reset interrupt
inst_jmp : std_logic_vector(7 downto 0); --! Decoded Inst: Conditional jump
inst_mov : std_logic; --! Decoded Inst: mov instruction
inst_sext : std_logic_vector(15 downto 0); --! Decoded Inst: source extended instruction word
inst_so : std_logic_vector(7 downto 0); --! Decoded Inst: Single-operand arithmetic
inst_src : std_logic_vector(15 downto 0); --! Decoded Inst: source (one hot)
inst_type : std_logic_vector(2 downto 0); --! Decoded Instruction type
mdb_in : std_logic_vector(15 downto 0); --! Memory data bus input
pc : std_logic_vector(15 downto 0); --! Program counter
pc_nxt : std_logic_vector(15 downto 0); --! Next pc value (for CALL & IRQ)
reg_dest : std_logic_vector(15 downto 0);
reg_src : std_logic_vector(15 downto 0);
alu_stat : std_logic_vector(3 downto 0);
alu_stat_wr : std_logic_vector(3 downto 0);
alu_out : std_logic_vector(15 downto 0);
alu_out_add : std_logic_vector(15 downto 0);
end record;
type reg_type is record
mdb_out_nxt : std_logic_vector(15 downto 0); --! Memory data bus output
mab_lsb : std_logic; --! Format memory data bus input depending on BW
mdb_in_buf_en : std_logic; --! Memory data bus input buffer (buffer after a source read)
mdb_in_buf_valid : std_logic;
mdb_in_buf : std_logic_vector(15 downto 0);
end record;
signal d : fmsp_execution_unit_in_type;
signal r : reg_type := ( mdb_out_nxt => x"0000", --! Memory data bus output
mab_lsb => '0',--! Format memory data bus input depending on BW
mdb_in_buf_en => '0',--! Memory data bus input buffer (buffer after a source read)
mdb_in_buf_valid => '0',
mdb_in_buf => x"0000"
);
signal rin : reg_type;
signal reg_dest_wr : std_logic;
signal reg_sp_wr : std_logic;
signal reg_sr_wr : std_logic;
signal reg_sr_clr : std_logic;
signal reg_pc_call : std_logic;
signal reg_incr : std_logic;
signal exec_cycle : std_logic;
signal status : std_logic_vector(3 downto 0);
signal op_dst : std_logic_vector(15 downto 0);
signal op_src : std_logic_vector(15 downto 0);
begin
d.dbg_halt_st <= dbg_halt_st;
d.dbg_mem_dout <= dbg_mem_dout;
d.dbg_reg_wr <= dbg_reg_wr;
d.e_state <= e_state;
d.exec_done <= exec_done;
d.inst_ad <= inst_ad;
d.inst_as <= inst_as;
d.inst_alu <= inst_alu;
d.inst_bw <= inst_bw;
d.inst_dest <= inst_dest;
d.inst_dext <= inst_dext;
d.inst_irq_rst <= inst_irq_rst;
d.inst_jmp <= inst_jmp;
d.inst_mov <= inst_mov;
d.inst_sext <= inst_sext;
d.inst_so <= inst_so;
d.inst_src <= inst_src;
d.inst_type <= inst_type;
d.mdb_in <= mdb_in;
d.pc <= pc;
d.pc_nxt <= pc_nxt;
COMB : process (all)
variable v : reg_type;
variable v_alu_stat : std_logic_vector(3 downto 0);
variable v_alu_stat_wr : std_logic_vector(3 downto 0);
variable v_op_dst : std_logic_vector(15 downto 0);
variable v_op_src : std_logic_vector(15 downto 0);
variable v_status : std_logic_vector(3 downto 0);
variable v_reg_dest_wr : std_logic;
variable v_reg_sp_wr : std_logic;
variable v_reg_sr_wr : std_logic;
variable v_reg_sr_clr : std_logic;
variable v_reg_pc_call : std_logic;
variable v_reg_incr : std_logic;
variable v_dbg_reg_din : std_logic_vector(15 downto 0);
variable v_src_reg_src_sel : std_logic;
variable v_src_reg_dest_sel : std_logic;
variable v_src_mdb_in_val_sel : std_logic;
variable v_src_inst_dext_sel : std_logic;
variable v_src_inst_sext_sel : std_logic;
variable v_dst_inst_sext_sel : std_logic;
variable v_dst_mdb_in_bw_sel : std_logic;
variable v_dst_fffe_sel : std_logic;
variable v_dst_reg_dest_sel : std_logic;
variable v_exec_cycle : std_logic;
--! Detect memory read/write access
variable v_mb_wr_det : std_logic;
variable v_mb_rd_det : std_logic;
variable v_mb_en : std_logic;
variable v_mb_wr_msk : std_logic_vector(1 downto 0);
variable v_mb_wr : std_logic_vector(1 downto 0);
--! Memory address bus
variable v_mab : std_logic_vector(15 downto 0);
variable v_mdb_out : std_logic_vector(15 downto 0);
variable v_mdb_in_bw : std_logic_vector(15 downto 0);
variable v_mdb_in_val : std_logic_vector(15 downto 0);
begin
--! default assignment
v := r;
--! overriding assignments
--=============================================================================
--! 2) REGISTER FILE
--=============================================================================
if ( ((d.e_state = E_EXEC) and (
((d.inst_type(C_INST_TO) = '1') and (d.inst_ad(C_DIR) = '1') and not (d.inst_alu(C_EXEC_NO_WR) = '1')) or
((d.inst_type(C_INST_SO) = '1') and (d.inst_as(C_DIR) = '1') and not ((d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') or (d.inst_so(C_RETI) = '1') )) or
(d.inst_type(C_INST_JMP) = '1'))) or (d.dbg_reg_wr = '1') ) then
v_reg_dest_wr := '1';
else
v_reg_dest_wr:= '0';
end if;
if ( ( ( (d.e_state = E_IRQ_1)
or (d.e_state = E_IRQ_3) )
and (not(d.inst_irq_rst) = '1') )
or ( (d.e_state = E_DST_RD)
and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') )
and (not(d.inst_as(C_IDX)) = '1')
and not( ( (d.inst_as(C_INDIR) = '1') or (d.inst_as(C_INDIR_I) = '1') ) and (d.inst_src(1) = '1') ) )
or ( (d.e_state = E_SRC_AD)
and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') )
and (d.inst_as(C_IDX) = '1') )
or ( (d.e_state = E_SRC_RD)
and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') )
and ( ((d.inst_as(C_INDIR) = '1') or (d.inst_as(C_INDIR_I) = '1')) and (d.inst_src(1) = '1') ) ) ) then
v_reg_sp_wr := '1';
else
v_reg_sp_wr := '0';
end if;
if ( (d.e_state = E_DST_RD) and (d.inst_so(C_RETI) = '1') ) then
v_reg_sr_wr := '1';
else
v_reg_sr_wr := '0';
end if;
if ( (d.e_state = E_IRQ_2) ) then
v_reg_sr_clr := '1';
else
v_reg_sr_clr := '0';
end if;
if ( ((d.e_state = E_EXEC) and (d.inst_so(C_CALL) = '1')) or
((d.e_state = E_DST_WR) and (d.inst_so(C_RETI) = '1')) ) then
v_reg_pc_call := '1';
else
v_reg_pc_call := '0';
end if;
if ( ((d.exec_done = '1') and (d.inst_as(C_INDIR_I) = '1')) or
((d.e_state = E_SRC_RD) and (d.inst_so(C_RETI) = '1')) or
((d.e_state = E_EXEC) and (d.inst_so(C_RETI) = '1')) ) then
v_reg_incr := '1';
else
v_reg_incr := '0';
end if;
v_dbg_reg_din := d.reg_dest;
--=============================================================================
--! 3) SOURCE OPERAND MUXING
--=============================================================================
--! d.inst_as(C_DIR) = '1') : Register direct. -> Source is in register
--! d.inst_as(C_IDX) = '1') : Register indexed. -> Source is in memory, address is register+offset
--! d.inst_as(C_INDIR) = '1') : Register indirect.
--! d.inst_as(C_INDIR_I) = '1'): Register indirect autoincrement.
--! d.inst_as(C_SYMB) = '1') : Symbolic (operand is in memory at address d.pc+x).
--! d.inst_as(C_IMM) = '1') : Immediate (operand is next word in the instruction stream).
--! d.inst_as(C_ABS) = '1') : Absolute (operand is in memory at address x).
--! d.inst_as(C_CONST) = '1') : Constant.
if ( ( (d.e_state = E_IRQ_0) or (d.e_state = E_IRQ_2) )
or ( (d.e_state = E_SRC_RD) and not(d.inst_as(C_ABS) = '1') )
or ( (d.e_state = E_SRC_WR) and not(d.inst_as(C_ABS) = '1') )
or ( (d.e_state = E_EXEC) and (d.inst_as(C_DIR) = '1') and not(d.inst_type(C_INST_JMP) = '1') ) ) then
v_src_reg_src_sel := '1';
else
v_src_reg_src_sel := '0';
end if;
if ( ( (d.e_state = E_IRQ_1) or (d.e_state = E_IRQ_3) )
or ( (d.e_state = E_DST_RD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) )
or ( (d.e_state = E_SRC_AD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) and (d.inst_as(C_IDX) = '1') ) ) then
v_src_reg_dest_sel := '1';
else
v_src_reg_dest_sel := '0';
end if;
if ( ( (d.e_state = E_DST_RD) and (d.inst_so(C_RETI) = '1') )
or ( (d.e_state = E_EXEC) and ( (d.inst_as(C_INDIR) = '1') or (d.inst_as(C_INDIR_I) = '1')
or (d.inst_as(C_IDX) = '1') or (d.inst_as(C_SYMB) = '1')
or (d.inst_as(C_ABS) = '1') ) ) ) then
v_src_mdb_in_val_sel := '1';
else
v_src_mdb_in_val_sel := '0';
end if;
if ( ( (d.e_state = E_DST_RD) and not( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) )
or ( (d.e_state = E_DST_WR) and not( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1')
or (d.inst_as(C_IDX) = '1') or (d.inst_as(C_SYMB) = '1')
or (d.inst_so(C_RETI) = '1') ) ) ) then
v_src_inst_dext_sel := '1';
else
v_src_inst_dext_sel := '0';
end if;
if ( (d.e_state = E_EXEC) and ( (d.inst_type(C_INST_JMP) = '1') or (d.inst_as(C_IMM) = '1') or (d.inst_as(C_CONST) = '1')
or (d.inst_so(C_RETI) = '1') ) ) then
v_src_inst_sext_sel := '1';
else
v_src_inst_sext_sel := '0';
end if;
if (v_src_reg_src_sel = '1') then
v_op_src := d.reg_src;
elsif (v_src_reg_dest_sel = '1') then
v_op_src := d.reg_dest;
elsif (v_src_mdb_in_val_sel = '1') then
v_op_src := v_mdb_in_val;
elsif (v_src_inst_dext_sel = '1') then
v_op_src := d.inst_dext;
elsif (v_src_inst_sext_sel = '1') then
v_op_src := d.inst_sext;
else
v_op_src := x"0000";
end if;
--=============================================================================
--! 4) DESTINATION OPERAND MUXING
--=============================================================================
--! d.inst_ad(C_DIR) = '1') : Register direct.
--! d.inst_ad(C_IDX) = '1') : Register indexed.
--! d.inst_ad(C_SYMB) = '1') : Symbolic (operand is in memory at address d.pc+x).
--! d.inst_ad(C_ABS) = '1') : Absolute (operand is in memory at address x).
if ( ( (d.e_state = E_SRC_RD) and ( (d.inst_as(C_IDX) = '1') or (d.inst_as(C_SYMB) = '1')
or (d.inst_as(C_ABS) = '1') ) )
or ( (d.e_state = E_SRC_RD) and ( (d.inst_as(C_IDX) = '1') or (d.inst_as(C_SYMB) = '1')
or (d.inst_as(C_ABS) = '1') ) ) ) then
v_dst_inst_sext_sel := '1';
else
v_dst_inst_sext_sel := '0';
end if;
if ( ( (d.e_state = E_DST_WR) and (d.inst_so(C_RETI) = '1') )
or ( (d.e_state = E_EXEC) and not( (d.inst_ad(C_IDX) = '1') or (d.inst_type(C_INST_JMP) = '1')
or (d.inst_type(C_INST_SO) = '1') ) and not(d.inst_so(C_RETI) = '1') ) ) then
v_dst_mdb_in_bw_sel := '1';
else
v_dst_mdb_in_bw_sel := '0';
end if;
if ( ( (d.e_state = E_IRQ_0) or (d.e_state = E_IRQ_0) or (d.e_state = E_IRQ_3) )
or ( (d.e_state = E_DST_RD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) and not(d.inst_so(C_RETI) = '1') )
or ( (d.e_state = E_SRC_AD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) and (d.inst_as(C_IDX) = '1') )
or ( (d.e_state = E_SRC_RD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) and ( (d.inst_as(C_INDIR) = '1') or (d.inst_as(C_INDIR_I) = '1') ) and (d.inst_src(1) = '1') ) ) then
v_dst_fffe_sel := '1';
else
v_dst_fffe_sel := '0';
end if;
if ( ( (d.e_state = E_DST_RD) and not( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') or (d.inst_ad(C_ABS) = '1') or (d.inst_so(C_RETI) = '1') ) )
or ( (d.e_state = E_DST_WR) and not(d.inst_ad(C_ABS) = '1') )
or ( (d.e_state = E_EXEC) and ( (d.inst_ad(C_DIR) = '1') or (d.inst_type(C_INST_JMP) = '1') or (d.inst_type(C_INST_SO) = '1') ) and not(d.inst_so(C_RETI) = '1') ) ) then
v_dst_reg_dest_sel := '1';
else
v_dst_reg_dest_sel := '0';
end if;
if (d.dbg_halt_st = '1') then
v_op_dst := d.dbg_mem_dout;
elsif (v_dst_inst_sext_sel = '1') then
v_op_dst := d.inst_sext;
elsif (v_dst_mdb_in_bw_sel = '1') then
v_op_dst := v_mdb_in_bw;
elsif (v_dst_reg_dest_sel = '1') then
v_op_dst := d.reg_dest;
elsif (v_dst_fffe_sel = '1') then
v_op_dst := x"FFFE";
else
v_op_dst := x"0000";
end if;
--=============================================================================
--! 5) ALU
--=============================================================================
if (d.e_state = E_EXEC) then
v_exec_cycle := '1';
else
v_exec_cycle := '0';
end if;
--=============================================================================
--! 6) MEMORY INTERFACE
--=============================================================================
--! Detect memory read/write access
if ( ( (d.e_state = E_SRC_RD) and (d.inst_as(C_IMM) = '0') )
or ( (d.e_state = E_EXEC) and (d.inst_so(C_RETI) = '0') )
or ( (d.e_state = E_SRC_RD) and (d.inst_type(C_INST_SO) = '0') and (d.inst_mov = '0') )
) then
v_mb_rd_det := '1';
else
v_mb_rd_det := '0';
end if;
--! Detect memory read/write access
if ( ( (d.e_state = E_IRQ_1) and (not(d.inst_irq_rst) = '0') )
or ( (d.e_state = E_IRQ_3) and (not(d.inst_irq_rst) = '0') )
or ( (d.e_state = E_DST_WR) and (not(d.inst_so(C_RETI)) = '0') )
or (d.e_state = E_SRC_WR) ) then
v_mb_wr_det := '1';
else
v_mb_wr_det := '0';
end if;
if (d.inst_alu(C_EXEC_NO_WR) = '1') then
v_mb_wr_msk := "00";
elsif (d.inst_bw = '0') then
v_mb_wr_msk := "11";
elsif (d.alu_out_add(0) = '1') then
v_mb_wr_msk := "10";
else
v_mb_wr_msk := "01";
end if;
if ( ( (not(d.inst_alu(C_EXEC_NO_WR)) = '1') and (v_mb_wr_det= '1') )
or (v_mb_rd_det= '1')
) then
v_mb_en := '1';
else
v_mb_en := '0';
end if;
if (v_mb_wr_det = '1') then
v_mb_wr := v_mb_wr_msk;
else
v_mb_wr := "00";
end if;
--! Memory address bus
v_mab := d.alu_out_add;
--! Memory data bus output
if (d.e_state = E_DST_RD) then
v.mdb_out_nxt := d.pc_nxt;
elsif ( ( (d.e_state = E_EXEC) and (not(d.inst_so(C_CALL)) = '1') )
or (d.e_state = E_IRQ_0) or (d.e_state = E_IRQ_2) ) then
v.mdb_out_nxt := d.alu_out;
end if;
if (d.inst_bw = '1') then
v_mdb_out := r.mdb_out_nxt(7 downto 0) & r.mdb_out_nxt(7 downto 0);
else
v_mdb_out := r.mdb_out_nxt;
end if;
--! Format memory data bus input depending on BW
if (v_mb_en = '1') then
v.mab_lsb := d.alu_out_add(0);
end if;
if (not(d.inst_bw) = '1') then
v_mdb_in_bw := d.mdb_in;
elsif (r.mab_lsb = '1') then
v_mdb_in_bw := d.mdb_in(15 downto 8) & d.mdb_in(15 downto 8);
else
v_mdb_in_bw := d.mdb_in;
end if;
--! Memory data bus input buffer (buffer after a source read)
if (d.e_state = E_SRC_RD) then
v.mdb_in_buf_en := '1';
else
v.mdb_in_buf_en := '0';
end if;
if (d.e_state = E_EXEC) then
v.mdb_in_buf_valid := '0';
elsif (r.mdb_in_buf_en) then
v.mdb_in_buf_valid := '1';
end if;
if (r.mdb_in_buf_en = '1') then
v.mdb_in_buf := v_mdb_in_bw;
end if;
if (r.mdb_in_buf_valid = '1') then
v_mdb_in_val := r.mdb_in_buf;
else
v_mdb_in_val := v_mdb_in_bw;
end if;
--! drive register inputs
rin <= v;
--! drive module outputs
reg_dest_wr <= v_reg_dest_wr;
reg_sp_wr <= v_reg_sp_wr;
reg_sr_wr <= v_reg_sr_wr;
reg_sr_clr <= v_reg_sr_clr;
reg_pc_call <= v_reg_pc_call;
reg_incr <= v_reg_incr;
exec_cycle <= v_exec_cycle;
-- signal status : std_logic_vector(3 downto 0);
op_dst <= v_op_dst;
op_src <= v_op_src;
--! OUTPUTs
-- cpuoff : out std_logic; --! Turns off the CPU
dbg_reg_din <= v_dbg_reg_din; --! Debug unit CPU register data input
-- gie : out std_logic; --! General interrupt enable
mab <= v_mab; --! Memory address bus
mb_en <= v_mb_en; --! Memory bus enable
mb_wr <= v_mb_wr; --! Memory bus write transfer
mdb_out <= v_mdb_out; --! Memory data bus output
-- oscoff : out std_logic; --! Turns off LFXT1 clock input
-- pc_sw <= v_dbg_reg_di; --! Program counter software value
-- pc_sw_wr <= v_dbg_reg_di; --! Program counter software write
-- scg0 : out std_logic; --! System clock generator 1. Turns off hte DCO
-- scg1 : out std_logic; --! System clock generator 1. Turns off the SMCLK
end process COMB;
REGS : process (mclk,mrst)
begin
if (mrst = '1') then
r <= ( mdb_out_nxt => x"0000", --! Memory data bus output
mab_lsb => '0',--! Format memory data bus input depending on BW
mdb_in_buf_en => '0',--! Memory data bus input buffer (buffer after a source read)
mdb_in_buf_valid => '0',
mdb_in_buf => x"0000"
);
elsif rising_edge(mclk) then
r <= rin;
end if;
end process REGS;
register_file : fmsp_register_file
port map(
mclk => mclk, --! Main system clock
mrst => mrst, --! Main system reset
--! INPUTs
alu_stat => d.alu_stat, --! ALU Status {V,N,Z,C}
alu_stat_wr => d.alu_stat_wr, --! ALU Status write {V,N,Z,C}
inst_bw => d.inst_bw, --! Decoded Inst: byte width
inst_dest => d.inst_dest, --! Register destination selection
inst_src => d.inst_src, --! Register source selection
pc => d.pc, --! Program counter
reg_dest_val => d.alu_out, --! Selected register destination value
reg_dest_wr => reg_dest_wr, --! Write selected register destination
reg_pc_call => reg_pc_call, --! Trigger pc update for a CALL instruction
reg_sp_val => d.alu_out_add, --! Stack Pointer next value
reg_sp_wr => reg_sp_wr, --! Stack Pointer write
reg_sr_clr => reg_sr_clr, --! Status register clear for interrupts
reg_sr_wr => reg_sr_wr, --! Status Register update for RETI instruction
reg_incr => reg_incr, --! Increment source register
--! OUTPUTs
cpuoff => cpuoff, --! Turns off the CPU
gie => gie, --! General interrupt enable
oscoff => oscoff, --! Turns off LFXT1 clock input
pc_sw => pc_sw, --! Program counter software value
pc_sw_wr => pc_sw_wr, --! Program counter software write
reg_dest => d.reg_dest, --! Selected register destination content
reg_src => d.reg_src, --! Selected register source content
scg0 => scg0, --! System clock generator 1. Turns off the DCOK
scg1 => scg1, --! System clock generator 1. Turns off the SMCLK
status => status --! R2 Status {V,N,Z,C}
);
alu : fmsp_alu
port map(
--! INPUTs
dbg_halt_st => d.dbg_halt_st, --! Halt/Run status from CPU
exec_cycle => exec_cycle, --! Instruction execution cycle
inst_alu => d.inst_alu, --! ALU control signals
inst_bw => d.inst_bw, --! Decoded Inst: byte width
inst_jmp => d.inst_jmp, --! Decoded Inst: Conditional jump
inst_so => d.inst_so, --! Single-operand arithmetic
op_dst => op_dst, --! Destination operand
op_src => op_src, --! Source operand
status => status, --! R2 Status {V,N,Z,C}
--! OUTPUTs
alu_out => d.alu_out, --! ALU output value
alu_out_add => d.alu_out_add, --! ALU adder output value
alu_stat => d.alu_stat, --! ALU Status {V,N,Z,C}
alu_stat_wr => d.alu_stat_wr --! ALU Status write {V,N,Z,C}
);
end RTL;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_eba_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eba_e-e.vhd,v 1.1 2004/04/06 10:50:46 wig Exp $
-- $Date: 2004/04/06 10:50:46 $
-- $Log: inst_eba_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:46 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_eba_e
--
entity inst_eba_e is
-- Generics:
-- No Generated Generics for Entity inst_eba_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_eba_e
end inst_eba_e;
--
-- End of Generated Entity inst_eba_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ----
---- File name: rom_s.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SinglePortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
we_i : in std_logic;
re_i : in std_logic;
addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
write_i : in unsigned(WORD_SIZE-1 downto 0);
read_o : out unsigned(WORD_SIZE-1 downto 0);
busy_o : out std_logic);
end entity SinglePortRAM;
architecture Xilinx of SinglePortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram : ram_type :=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80f8ec0c",
3 => x"3a0b0b80",
4 => x"e7ea0400",
5 => x"00000000",
6 => x"00000000",
7 => x"00000000",
8 => x"80088408",
9 => x"88080b0b",
10 => x"80e8b72d",
11 => x"880c840c",
12 => x"800c0400",
13 => x"00000000",
14 => x"00000000",
15 => x"00000000",
16 => x"71fd0608",
17 => x"72830609",
18 => x"81058205",
19 => x"832b2a83",
20 => x"ffff0652",
21 => x"04000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"83ffff73",
26 => x"83060981",
27 => x"05820583",
28 => x"2b2b0906",
29 => x"7383ffff",
30 => x"0b0b0b0b",
31 => x"83a70400",
32 => x"72098105",
33 => x"72057373",
34 => x"09060906",
35 => x"73097306",
36 => x"070a8106",
37 => x"53510400",
38 => x"00000000",
39 => x"00000000",
40 => x"72722473",
41 => x"732e0753",
42 => x"51040000",
43 => x"00000000",
44 => x"00000000",
45 => x"00000000",
46 => x"00000000",
47 => x"00000000",
48 => x"71737109",
49 => x"71068106",
50 => x"30720a10",
51 => x"0a720a10",
52 => x"0a31050a",
53 => x"81065151",
54 => x"53510400",
55 => x"00000000",
56 => x"72722673",
57 => x"732e0753",
58 => x"51040000",
59 => x"00000000",
60 => x"00000000",
61 => x"00000000",
62 => x"00000000",
63 => x"00000000",
64 => x"00000000",
65 => x"00000000",
66 => x"00000000",
67 => x"00000000",
68 => x"00000000",
69 => x"00000000",
70 => x"00000000",
71 => x"00000000",
72 => x"0b0b0b88",
73 => x"c4040000",
74 => x"00000000",
75 => x"00000000",
76 => x"00000000",
77 => x"00000000",
78 => x"00000000",
79 => x"00000000",
80 => x"720a722b",
81 => x"0a535104",
82 => x"00000000",
83 => x"00000000",
84 => x"00000000",
85 => x"00000000",
86 => x"00000000",
87 => x"00000000",
88 => x"72729f06",
89 => x"0981050b",
90 => x"0b0b88a7",
91 => x"05040000",
92 => x"00000000",
93 => x"00000000",
94 => x"00000000",
95 => x"00000000",
96 => x"72722aff",
97 => x"739f062a",
98 => x"0974090a",
99 => x"8106ff05",
100 => x"06075351",
101 => x"04000000",
102 => x"00000000",
103 => x"00000000",
104 => x"71715351",
105 => x"020d0406",
106 => x"73830609",
107 => x"81058205",
108 => x"832b0b2b",
109 => x"0772fc06",
110 => x"0c515104",
111 => x"00000000",
112 => x"72098105",
113 => x"72050970",
114 => x"81050906",
115 => x"0a810653",
116 => x"51040000",
117 => x"00000000",
118 => x"00000000",
119 => x"00000000",
120 => x"72098105",
121 => x"72050970",
122 => x"81050906",
123 => x"0a098106",
124 => x"53510400",
125 => x"00000000",
126 => x"00000000",
127 => x"00000000",
128 => x"71098105",
129 => x"52040000",
130 => x"00000000",
131 => x"00000000",
132 => x"00000000",
133 => x"00000000",
134 => x"00000000",
135 => x"00000000",
136 => x"72720981",
137 => x"05055351",
138 => x"04000000",
139 => x"00000000",
140 => x"00000000",
141 => x"00000000",
142 => x"00000000",
143 => x"00000000",
144 => x"72097206",
145 => x"73730906",
146 => x"07535104",
147 => x"00000000",
148 => x"00000000",
149 => x"00000000",
150 => x"00000000",
151 => x"00000000",
152 => x"71fc0608",
153 => x"72830609",
154 => x"81058305",
155 => x"1010102a",
156 => x"81ff0652",
157 => x"04000000",
158 => x"00000000",
159 => x"00000000",
160 => x"71fc0608",
161 => x"0b0b80f8",
162 => x"d8738306",
163 => x"10100508",
164 => x"060b0b0b",
165 => x"88aa0400",
166 => x"00000000",
167 => x"00000000",
168 => x"80088408",
169 => x"88087575",
170 => x"0b0b80ce",
171 => x"b62d5050",
172 => x"80085688",
173 => x"0c840c80",
174 => x"0c510400",
175 => x"00000000",
176 => x"80088408",
177 => x"88087575",
178 => x"0b0b80cf",
179 => x"e82d5050",
180 => x"80085688",
181 => x"0c840c80",
182 => x"0c510400",
183 => x"00000000",
184 => x"72097081",
185 => x"0509060a",
186 => x"8106ff05",
187 => x"70547106",
188 => x"73097274",
189 => x"05ff0506",
190 => x"07515151",
191 => x"04000000",
192 => x"72097081",
193 => x"0509060a",
194 => x"098106ff",
195 => x"05705471",
196 => x"06730972",
197 => x"7405ff05",
198 => x"06075151",
199 => x"51040000",
200 => x"05ff0504",
201 => x"00000000",
202 => x"00000000",
203 => x"00000000",
204 => x"00000000",
205 => x"00000000",
206 => x"00000000",
207 => x"00000000",
208 => x"810b0b0b",
209 => x"80f8e80c",
210 => x"51040000",
211 => x"00000000",
212 => x"00000000",
213 => x"00000000",
214 => x"00000000",
215 => x"00000000",
216 => x"71810552",
217 => x"04000000",
218 => x"00000000",
219 => x"00000000",
220 => x"00000000",
221 => x"00000000",
222 => x"00000000",
223 => x"00000000",
224 => x"00000000",
225 => x"00000000",
226 => x"00000000",
227 => x"00000000",
228 => x"00000000",
229 => x"00000000",
230 => x"00000000",
231 => x"00000000",
232 => x"02840572",
233 => x"10100552",
234 => x"04000000",
235 => x"00000000",
236 => x"00000000",
237 => x"00000000",
238 => x"00000000",
239 => x"00000000",
240 => x"00000000",
241 => x"00000000",
242 => x"00000000",
243 => x"00000000",
244 => x"00000000",
245 => x"00000000",
246 => x"00000000",
247 => x"00000000",
248 => x"717105ff",
249 => x"05715351",
250 => x"020d0400",
251 => x"00000000",
252 => x"00000000",
253 => x"00000000",
254 => x"00000000",
255 => x"00000000",
256 => x"83803f80",
257 => x"e2953f04",
258 => x"10101010",
259 => x"10101010",
260 => x"10101010",
261 => x"10101010",
262 => x"10101010",
263 => x"10101010",
264 => x"10101010",
265 => x"10101053",
266 => x"51047381",
267 => x"ff067383",
268 => x"06098105",
269 => x"83051010",
270 => x"102b0772",
271 => x"fc060c51",
272 => x"51043c04",
273 => x"72728072",
274 => x"8106ff05",
275 => x"09720605",
276 => x"71105272",
277 => x"0a100a53",
278 => x"72ed3851",
279 => x"51535104",
280 => x"ff3d0d0b",
281 => x"0b8188e0",
282 => x"08527108",
283 => x"70882a81",
284 => x"32708106",
285 => x"51515170",
286 => x"f1387372",
287 => x"0c833d0d",
288 => x"0480f8e8",
289 => x"08802ea4",
290 => x"3880f8ec",
291 => x"08822ebd",
292 => x"38838080",
293 => x"0b0b0b81",
294 => x"88e00c82",
295 => x"a0800b81",
296 => x"88e40c82",
297 => x"90800b81",
298 => x"88e80c04",
299 => x"f8808080",
300 => x"a40b0b0b",
301 => x"8188e00c",
302 => x"f8808082",
303 => x"800b8188",
304 => x"e40cf880",
305 => x"8084800b",
306 => x"8188e80c",
307 => x"0480c0a8",
308 => x"808c0b0b",
309 => x"0b8188e0",
310 => x"0c80c0a8",
311 => x"80940b81",
312 => x"88e40c0b",
313 => x"0b80eac8",
314 => x"0b8188e8",
315 => x"0c04f23d",
316 => x"0d608188",
317 => x"e408565d",
318 => x"82750c80",
319 => x"59805a80",
320 => x"0b8f3d5d",
321 => x"5b7a1010",
322 => x"15700871",
323 => x"08719f2c",
324 => x"7e852b58",
325 => x"55557d53",
326 => x"59579d94",
327 => x"3f7d7f7a",
328 => x"72077c72",
329 => x"07717160",
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3666 => x"5f4c6f63",
3667 => x"3a202020",
3668 => x"20202020",
3669 => x"20202020",
3670 => x"2025640a",
3671 => x"00000000",
3672 => x"5374725f",
3673 => x"315f4c6f",
3674 => x"633a2020",
3675 => x"20202020",
3676 => x"20202020",
3677 => x"2025730a",
3678 => x"00000000",
3679 => x"20202020",
3680 => x"20202020",
3681 => x"73686f75",
3682 => x"6c642062",
3683 => x"653a2020",
3684 => x"20444852",
3685 => x"5953544f",
3686 => x"4e452050",
3687 => x"524f4752",
3688 => x"414d2c20",
3689 => x"31275354",
3690 => x"20535452",
3691 => x"494e470a",
3692 => x"00000000",
3693 => x"5374725f",
3694 => x"325f4c6f",
3695 => x"633a2020",
3696 => x"20202020",
3697 => x"20202020",
3698 => x"2025730a",
3699 => x"00000000",
3700 => x"20202020",
3701 => x"20202020",
3702 => x"73686f75",
3703 => x"6c642062",
3704 => x"653a2020",
3705 => x"20444852",
3706 => x"5953544f",
3707 => x"4e452050",
3708 => x"524f4752",
3709 => x"414d2c20",
3710 => x"32274e44",
3711 => x"20535452",
3712 => x"494e470a",
3713 => x"00000000",
3714 => x"55736572",
3715 => x"2074696d",
3716 => x"653a2025",
3717 => x"640a0000",
3718 => x"4d696372",
3719 => x"6f736563",
3720 => x"6f6e6473",
3721 => x"20666f72",
3722 => x"206f6e65",
3723 => x"2072756e",
3724 => x"20746872",
3725 => x"6f756768",
3726 => x"20446872",
3727 => x"7973746f",
3728 => x"6e653a20",
3729 => x"00000000",
3730 => x"2564200a",
3731 => x"00000000",
3732 => x"44687279",
3733 => x"73746f6e",
3734 => x"65732070",
3735 => x"65722053",
3736 => x"65636f6e",
3737 => x"643a2020",
3738 => x"20202020",
3739 => x"20202020",
3740 => x"20202020",
3741 => x"20202020",
3742 => x"20202020",
3743 => x"00000000",
3744 => x"56415820",
3745 => x"4d495053",
3746 => x"20726174",
3747 => x"696e6720",
3748 => x"2a203130",
3749 => x"3030203d",
3750 => x"20256420",
3751 => x"0a000000",
3752 => x"50726f67",
3753 => x"72616d20",
3754 => x"636f6d70",
3755 => x"696c6564",
3756 => x"20776974",
3757 => x"686f7574",
3758 => x"20277265",
3759 => x"67697374",
3760 => x"65722720",
3761 => x"61747472",
3762 => x"69627574",
3763 => x"650a0000",
3764 => x"4d656173",
3765 => x"75726564",
3766 => x"2074696d",
3767 => x"6520746f",
3768 => x"6f20736d",
3769 => x"616c6c20",
3770 => x"746f206f",
3771 => x"62746169",
3772 => x"6e206d65",
3773 => x"616e696e",
3774 => x"6766756c",
3775 => x"20726573",
3776 => x"756c7473",
3777 => x"0a000000",
3778 => x"506c6561",
3779 => x"73652069",
3780 => x"6e637265",
3781 => x"61736520",
3782 => x"6e756d62",
3783 => x"6572206f",
3784 => x"66207275",
3785 => x"6e730a00",
3786 => x"44485259",
3787 => x"53544f4e",
3788 => x"45205052",
3789 => x"4f475241",
3790 => x"4d2c2033",
3791 => x"27524420",
3792 => x"53545249",
3793 => x"4e470000",
3794 => x"00010202",
3795 => x"03030303",
3796 => x"04040404",
3797 => x"04040404",
3798 => x"05050505",
3799 => x"05050505",
3800 => x"05050505",
3801 => x"05050505",
3802 => x"06060606",
3803 => x"06060606",
3804 => x"06060606",
3805 => x"06060606",
3806 => x"06060606",
3807 => x"06060606",
3808 => x"06060606",
3809 => x"06060606",
3810 => x"07070707",
3811 => x"07070707",
3812 => x"07070707",
3813 => x"07070707",
3814 => x"07070707",
3815 => x"07070707",
3816 => x"07070707",
3817 => x"07070707",
3818 => x"07070707",
3819 => x"07070707",
3820 => x"07070707",
3821 => x"07070707",
3822 => x"07070707",
3823 => x"07070707",
3824 => x"07070707",
3825 => x"07070707",
3826 => x"08080808",
3827 => x"08080808",
3828 => x"08080808",
3829 => x"08080808",
3830 => x"08080808",
3831 => x"08080808",
3832 => x"08080808",
3833 => x"08080808",
3834 => x"08080808",
3835 => x"08080808",
3836 => x"08080808",
3837 => x"08080808",
3838 => x"08080808",
3839 => x"08080808",
3840 => x"08080808",
3841 => x"08080808",
3842 => x"08080808",
3843 => x"08080808",
3844 => x"08080808",
3845 => x"08080808",
3846 => x"08080808",
3847 => x"08080808",
3848 => x"08080808",
3849 => x"08080808",
3850 => x"08080808",
3851 => x"08080808",
3852 => x"08080808",
3853 => x"08080808",
3854 => x"08080808",
3855 => x"08080808",
3856 => x"08080808",
3857 => x"08080808",
3858 => x"43000000",
3859 => x"64756d6d",
3860 => x"792e6578",
3861 => x"65000000",
3862 => x"00ffffff",
3863 => x"ff00ffff",
3864 => x"ffff00ff",
3865 => x"ffffff00",
3866 => x"00000000",
3867 => x"00000000",
3868 => x"00000000",
3869 => x"00004458",
3870 => x"0000000a",
3871 => x"00000000",
3872 => x"00000032",
3873 => x"00000000",
3874 => x"00000000",
3875 => x"00000000",
3876 => x"00000000",
3877 => x"00000000",
3878 => x"00000000",
3879 => x"00000000",
3880 => x"00000000",
3881 => x"00000000",
3882 => x"00000000",
3883 => x"00000000",
3884 => x"00000000",
3885 => x"ffffffff",
3886 => x"00000000",
3887 => x"00020000",
3888 => x"00000000",
3889 => x"00000000",
3890 => x"00003cc0",
3891 => x"00003cc0",
3892 => x"00003cc8",
3893 => x"00003cc8",
3894 => x"00003cd0",
3895 => x"00003cd0",
3896 => x"00003cd8",
3897 => x"00003cd8",
3898 => x"00003ce0",
3899 => x"00003ce0",
3900 => x"00003ce8",
3901 => x"00003ce8",
3902 => x"00003cf0",
3903 => x"00003cf0",
3904 => x"00003cf8",
3905 => x"00003cf8",
3906 => x"00003d00",
3907 => x"00003d00",
3908 => x"00003d08",
3909 => x"00003d08",
3910 => x"00003d10",
3911 => x"00003d10",
3912 => x"00003d18",
3913 => x"00003d18",
3914 => x"00003d20",
3915 => x"00003d20",
3916 => x"00003d28",
3917 => x"00003d28",
3918 => x"00003d30",
3919 => x"00003d30",
3920 => x"00003d38",
3921 => x"00003d38",
3922 => x"00003d40",
3923 => x"00003d40",
3924 => x"00003d48",
3925 => x"00003d48",
3926 => x"00003d50",
3927 => x"00003d50",
3928 => x"00003d58",
3929 => x"00003d58",
3930 => x"00003d60",
3931 => x"00003d60",
3932 => x"00003d68",
3933 => x"00003d68",
3934 => x"00003d70",
3935 => x"00003d70",
3936 => x"00003d78",
3937 => x"00003d78",
3938 => x"00003d80",
3939 => x"00003d80",
3940 => x"00003d88",
3941 => x"00003d88",
3942 => x"00003d90",
3943 => x"00003d90",
3944 => x"00003d98",
3945 => x"00003d98",
3946 => x"00003da0",
3947 => x"00003da0",
3948 => x"00003da8",
3949 => x"00003da8",
3950 => x"00003db0",
3951 => x"00003db0",
3952 => x"00003db8",
3953 => x"00003db8",
3954 => x"00003dc0",
3955 => x"00003dc0",
3956 => x"00003dc8",
3957 => x"00003dc8",
3958 => x"00003dd0",
3959 => x"00003dd0",
3960 => x"00003dd8",
3961 => x"00003dd8",
3962 => x"00003de0",
3963 => x"00003de0",
3964 => x"00003de8",
3965 => x"00003de8",
3966 => x"00003df0",
3967 => x"00003df0",
3968 => x"00003df8",
3969 => x"00003df8",
3970 => x"00003e00",
3971 => x"00003e00",
3972 => x"00003e08",
3973 => x"00003e08",
3974 => x"00003e10",
3975 => x"00003e10",
3976 => x"00003e18",
3977 => x"00003e18",
3978 => x"00003e20",
3979 => x"00003e20",
3980 => x"00003e28",
3981 => x"00003e28",
3982 => x"00003e30",
3983 => x"00003e30",
3984 => x"00003e38",
3985 => x"00003e38",
3986 => x"00003e40",
3987 => x"00003e40",
3988 => x"00003e48",
3989 => x"00003e48",
3990 => x"00003e50",
3991 => x"00003e50",
3992 => x"00003e58",
3993 => x"00003e58",
3994 => x"00003e60",
3995 => x"00003e60",
3996 => x"00003e68",
3997 => x"00003e68",
3998 => x"00003e70",
3999 => x"00003e70",
4000 => x"00003e78",
4001 => x"00003e78",
4002 => x"00003e80",
4003 => x"00003e80",
4004 => x"00003e88",
4005 => x"00003e88",
4006 => x"00003e90",
4007 => x"00003e90",
4008 => x"00003e98",
4009 => x"00003e98",
4010 => x"00003ea0",
4011 => x"00003ea0",
4012 => x"00003ea8",
4013 => x"00003ea8",
4014 => x"00003eb0",
4015 => x"00003eb0",
4016 => x"00003eb8",
4017 => x"00003eb8",
4018 => x"00003ec0",
4019 => x"00003ec0",
4020 => x"00003ec8",
4021 => x"00003ec8",
4022 => x"00003ed0",
4023 => x"00003ed0",
4024 => x"00003ed8",
4025 => x"00003ed8",
4026 => x"00003ee0",
4027 => x"00003ee0",
4028 => x"00003ee8",
4029 => x"00003ee8",
4030 => x"00003ef0",
4031 => x"00003ef0",
4032 => x"00003ef8",
4033 => x"00003ef8",
4034 => x"00003f00",
4035 => x"00003f00",
4036 => x"00003f08",
4037 => x"00003f08",
4038 => x"00003f10",
4039 => x"00003f10",
4040 => x"00003f18",
4041 => x"00003f18",
4042 => x"00003f20",
4043 => x"00003f20",
4044 => x"00003f28",
4045 => x"00003f28",
4046 => x"00003f30",
4047 => x"00003f30",
4048 => x"00003f38",
4049 => x"00003f38",
4050 => x"00003f40",
4051 => x"00003f40",
4052 => x"00003f48",
4053 => x"00003f48",
4054 => x"00003f50",
4055 => x"00003f50",
4056 => x"00003f58",
4057 => x"00003f58",
4058 => x"00003f60",
4059 => x"00003f60",
4060 => x"00003f68",
4061 => x"00003f68",
4062 => x"00003f70",
4063 => x"00003f70",
4064 => x"00003f78",
4065 => x"00003f78",
4066 => x"00003f80",
4067 => x"00003f80",
4068 => x"00003f88",
4069 => x"00003f88",
4070 => x"00003f90",
4071 => x"00003f90",
4072 => x"00003f98",
4073 => x"00003f98",
4074 => x"00003fa0",
4075 => x"00003fa0",
4076 => x"00003fa8",
4077 => x"00003fa8",
4078 => x"00003fb0",
4079 => x"00003fb0",
4080 => x"00003fb8",
4081 => x"00003fb8",
4082 => x"00003fc0",
4083 => x"00003fc0",
4084 => x"00003fc8",
4085 => x"00003fc8",
4086 => x"00003fd0",
4087 => x"00003fd0",
4088 => x"00003fd8",
4089 => x"00003fd8",
4090 => x"00003fe0",
4091 => x"00003fe0",
4092 => x"00003fe8",
4093 => x"00003fe8",
4094 => x"00003ff0",
4095 => x"00003ff0",
4096 => x"00003ff8",
4097 => x"00003ff8",
4098 => x"00004000",
4099 => x"00004000",
4100 => x"00004008",
4101 => x"00004008",
4102 => x"00004010",
4103 => x"00004010",
4104 => x"00004018",
4105 => x"00004018",
4106 => x"00004020",
4107 => x"00004020",
4108 => x"00004028",
4109 => x"00004028",
4110 => x"00004030",
4111 => x"00004030",
4112 => x"00004038",
4113 => x"00004038",
4114 => x"00004040",
4115 => x"00004040",
4116 => x"00004048",
4117 => x"00004048",
4118 => x"00004050",
4119 => x"00004050",
4120 => x"00004058",
4121 => x"00004058",
4122 => x"00004060",
4123 => x"00004060",
4124 => x"00004068",
4125 => x"00004068",
4126 => x"00004070",
4127 => x"00004070",
4128 => x"00004078",
4129 => x"00004078",
4130 => x"00004080",
4131 => x"00004080",
4132 => x"00004088",
4133 => x"00004088",
4134 => x"00004090",
4135 => x"00004090",
4136 => x"00004098",
4137 => x"00004098",
4138 => x"000040a0",
4139 => x"000040a0",
4140 => x"000040a8",
4141 => x"000040a8",
4142 => x"000040b0",
4143 => x"000040b0",
4144 => x"000040b8",
4145 => x"000040b8",
4146 => x"000040cc",
4147 => x"00000000",
4148 => x"00004334",
4149 => x"00004390",
4150 => x"000043ec",
4151 => x"00000000",
4152 => x"00000000",
4153 => x"00000000",
4154 => x"00000000",
4155 => x"00000000",
4156 => x"00000000",
4157 => x"00000000",
4158 => x"00000000",
4159 => x"00000000",
4160 => x"00003c48",
4161 => x"00000000",
4162 => x"00000000",
4163 => x"00000000",
4164 => x"00000000",
4165 => x"00000000",
4166 => x"00000000",
4167 => x"00000000",
4168 => x"00000000",
4169 => x"00000000",
4170 => x"00000000",
4171 => x"00000000",
4172 => x"00000000",
4173 => x"00000000",
4174 => x"00000000",
4175 => x"00000000",
4176 => x"00000000",
4177 => x"00000000",
4178 => x"00000000",
4179 => x"00000000",
4180 => x"00000000",
4181 => x"00000000",
4182 => x"00000000",
4183 => x"00000000",
4184 => x"00000000",
4185 => x"00000000",
4186 => x"00000000",
4187 => x"00000000",
4188 => x"00000000",
4189 => x"00000001",
4190 => x"330eabcd",
4191 => x"1234e66d",
4192 => x"deec0005",
4193 => x"000b0000",
4194 => x"00000000",
4195 => x"00000000",
4196 => x"00000000",
4197 => x"00000000",
4198 => x"00000000",
4199 => x"00000000",
4200 => x"00000000",
4201 => x"00000000",
4202 => x"00000000",
4203 => x"00000000",
4204 => x"00000000",
4205 => x"00000000",
4206 => x"00000000",
4207 => x"00000000",
4208 => x"00000000",
4209 => x"00000000",
4210 => x"00000000",
4211 => x"00000000",
4212 => x"00000000",
4213 => x"00000000",
4214 => x"00000000",
4215 => x"00000000",
4216 => x"00000000",
4217 => x"00000000",
4218 => x"00000000",
4219 => x"00000000",
4220 => x"00000000",
4221 => x"00000000",
4222 => x"00000000",
4223 => x"00000000",
4224 => x"00000000",
4225 => x"00000000",
4226 => x"00000000",
4227 => x"00000000",
4228 => x"00000000",
4229 => x"00000000",
4230 => x"00000000",
4231 => x"00000000",
4232 => x"00000000",
4233 => x"00000000",
4234 => x"00000000",
4235 => x"00000000",
4236 => x"00000000",
4237 => x"00000000",
4238 => x"00000000",
4239 => x"00000000",
4240 => x"00000000",
4241 => x"00000000",
4242 => x"00000000",
4243 => x"00000000",
4244 => x"00000000",
4245 => x"00000000",
4246 => x"00000000",
4247 => x"00000000",
4248 => x"00000000",
4249 => x"00000000",
4250 => x"00000000",
4251 => x"00000000",
4252 => x"00000000",
4253 => x"00000000",
4254 => x"00000000",
4255 => x"00000000",
4256 => x"00000000",
4257 => x"00000000",
4258 => x"00000000",
4259 => x"00000000",
4260 => x"00000000",
4261 => x"00000000",
4262 => x"00000000",
4263 => x"00000000",
4264 => x"00000000",
4265 => x"00000000",
4266 => x"00000000",
4267 => x"00000000",
4268 => x"00000000",
4269 => x"00000000",
4270 => x"00000000",
4271 => x"00000000",
4272 => x"00000000",
4273 => x"00000000",
4274 => x"00000000",
4275 => x"00000000",
4276 => x"00000000",
4277 => x"00000000",
4278 => x"00000000",
4279 => x"00000000",
4280 => x"00000000",
4281 => x"00000000",
4282 => x"00000000",
4283 => x"00000000",
4284 => x"00000000",
4285 => x"00000000",
4286 => x"00000000",
4287 => x"00000000",
4288 => x"00000000",
4289 => x"00000000",
4290 => x"00000000",
4291 => x"00000000",
4292 => x"00000000",
4293 => x"00000000",
4294 => x"00000000",
4295 => x"00000000",
4296 => x"00000000",
4297 => x"00000000",
4298 => x"00000000",
4299 => x"00000000",
4300 => x"00000000",
4301 => x"00000000",
4302 => x"00000000",
4303 => x"00000000",
4304 => x"00000000",
4305 => x"00000000",
4306 => x"00000000",
4307 => x"00000000",
4308 => x"00000000",
4309 => x"00000000",
4310 => x"00000000",
4311 => x"00000000",
4312 => x"00000000",
4313 => x"00000000",
4314 => x"00000000",
4315 => x"00000000",
4316 => x"00000000",
4317 => x"00000000",
4318 => x"00000000",
4319 => x"00000000",
4320 => x"00000000",
4321 => x"00000000",
4322 => x"00000000",
4323 => x"00000000",
4324 => x"00000000",
4325 => x"00000000",
4326 => x"00000000",
4327 => x"00000000",
4328 => x"00000000",
4329 => x"00000000",
4330 => x"00000000",
4331 => x"00000000",
4332 => x"00000000",
4333 => x"00000000",
4334 => x"00000000",
4335 => x"00000000",
4336 => x"00000000",
4337 => x"00000000",
4338 => x"00000000",
4339 => x"00000000",
4340 => x"00000000",
4341 => x"00000000",
4342 => x"00000000",
4343 => x"00000000",
4344 => x"00000000",
4345 => x"00000000",
4346 => x"00000000",
4347 => x"00000000",
4348 => x"00000000",
4349 => x"00000000",
4350 => x"00000000",
4351 => x"00000000",
4352 => x"00000000",
4353 => x"00000000",
4354 => x"00000000",
4355 => x"00000000",
4356 => x"00000000",
4357 => x"00000000",
4358 => x"00000000",
4359 => x"00000000",
4360 => x"00000000",
4361 => x"00000000",
4362 => x"00000000",
4363 => x"00000000",
4364 => x"00000000",
4365 => x"00000000",
4366 => x"00000000",
4367 => x"00000000",
4368 => x"00000000",
4369 => x"00000000",
4370 => x"00003c4c",
4371 => x"ffffffff",
4372 => x"00000000",
4373 => x"ffffffff",
4374 => x"00000000",
4375 => x"00000000",
others => x"00000000"
);
begin
busy_o <= re_i; -- we're done on the cycle after we serve the read request
do_ram:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(addr_i)) <= write_i;
end if;
addr_r <= addr_i;
end if;
end process do_ram;
read_o <= ram(to_integer(addr_r));
end architecture Xilinx; -- Entity: SinglePortRAM
|
----------------------------------------------------------------------------------
-- Create Date: 15:31:16 04/11/2017
-- Module Name: incrementador - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity incrementador is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
O : out STD_LOGIC_VECTOR (3 downto 0));
end incrementador;
architecture Behavioral of incrementador is
component Somador4bits
Port ( X : in STD_LOGIC_VECTOR (3 downto 0);
Y : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
Ov : out STD_LOGIC;
Z : out STD_LOGIC_VECTOR (3 downto 0));
end component;
begin
O: Somador4bits port map( A, "0000", '1');
end Behavioral;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net7
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net7,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net8,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
|
library ieee;
use ieee.std_logic_1164.all;
entity sign is
port(a: in std_logic_vector(15 downto 0);
y: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of sign is
begin
process (a)
variable v : std_logic_vector(15 downto 0);
begin
if (a(0)='1') then
v := (others => '1');
y <= (a & v);
elsif (a(0)='0') then
v := (others => '0');
y <= (a & v);
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity sign is
port(a: in std_logic_vector(15 downto 0);
y: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of sign is
begin
process (a)
variable v : std_logic_vector(15 downto 0);
begin
if (a(0)='1') then
v := (others => '1');
y <= (a & v);
elsif (a(0)='0') then
v := (others => '0');
y <= (a & v);
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity sign is
port(a: in std_logic_vector(15 downto 0);
y: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of sign is
begin
process (a)
variable v : std_logic_vector(15 downto 0);
begin
if (a(0)='1') then
v := (others => '1');
y <= (a & v);
elsif (a(0)='0') then
v := (others => '0');
y <= (a & v);
end if;
end process;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18);
port(
a : in std_logic_vector((WIDTH)-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
direction : in std_logic;
distance : in std_logic_vector((DISTANCE_WIDTH)-1 downto 0);
ena : in std_logic;
r : out std_logic_vector((WIDTH)-1 downto 0);
user_aclr : in std_logic);
end entity;
--- The DSPBuilder BarrelShifter
architecture rtl of alt_dspbuilder_barrelshifter_GNV5DVAGHT is
signal clear : std_logic;
signal a_ext : std_logic_vector(18 downto 0);
signal d_ext : std_logic_vector(5 - 1 downto 0);
signal r_ext : std_logic_vector(18 downto 0);
Begin
clear <= aclr or user_aclr;
a_ext(18 - 1 downto 0) <= a;
a_ext(18) <= '0';
d_ext(4 - 1 downto 0) <= distance;
d_ext(5 - 1 downto 4) <= (others => '0');
BarrelShifteri : alt_dspbuilder_BarrelShiftAltr Generic map (
widthin => WIDTH + 1 ,
pipeline => PIPELINE,
use_dedicated_circuitry => 0 ,
widthd => 5 ,
ndirection => NDIRECTION )
port map (
clock => clock,
aclr => clear,
sclr => '0',
ena => ena,
direction => '0',
xin => a_ext ,
distance => d_ext ,
yout => r_ext );
r <= r_ext(18 - 1 downto 0);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18);
port(
a : in std_logic_vector((WIDTH)-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
direction : in std_logic;
distance : in std_logic_vector((DISTANCE_WIDTH)-1 downto 0);
ena : in std_logic;
r : out std_logic_vector((WIDTH)-1 downto 0);
user_aclr : in std_logic);
end entity;
--- The DSPBuilder BarrelShifter
architecture rtl of alt_dspbuilder_barrelshifter_GNV5DVAGHT is
signal clear : std_logic;
signal a_ext : std_logic_vector(18 downto 0);
signal d_ext : std_logic_vector(5 - 1 downto 0);
signal r_ext : std_logic_vector(18 downto 0);
Begin
clear <= aclr or user_aclr;
a_ext(18 - 1 downto 0) <= a;
a_ext(18) <= '0';
d_ext(4 - 1 downto 0) <= distance;
d_ext(5 - 1 downto 4) <= (others => '0');
BarrelShifteri : alt_dspbuilder_BarrelShiftAltr Generic map (
widthin => WIDTH + 1 ,
pipeline => PIPELINE,
use_dedicated_circuitry => 0 ,
widthd => 5 ,
ndirection => NDIRECTION )
port map (
clock => clock,
aclr => clear,
sclr => '0',
ena => ena,
direction => '0',
xin => a_ext ,
distance => d_ext ,
yout => r_ext );
r <= r_ext(18 - 1 downto 0);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18);
port(
a : in std_logic_vector((WIDTH)-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
direction : in std_logic;
distance : in std_logic_vector((DISTANCE_WIDTH)-1 downto 0);
ena : in std_logic;
r : out std_logic_vector((WIDTH)-1 downto 0);
user_aclr : in std_logic);
end entity;
--- The DSPBuilder BarrelShifter
architecture rtl of alt_dspbuilder_barrelshifter_GNV5DVAGHT is
signal clear : std_logic;
signal a_ext : std_logic_vector(18 downto 0);
signal d_ext : std_logic_vector(5 - 1 downto 0);
signal r_ext : std_logic_vector(18 downto 0);
Begin
clear <= aclr or user_aclr;
a_ext(18 - 1 downto 0) <= a;
a_ext(18) <= '0';
d_ext(4 - 1 downto 0) <= distance;
d_ext(5 - 1 downto 4) <= (others => '0');
BarrelShifteri : alt_dspbuilder_BarrelShiftAltr Generic map (
widthin => WIDTH + 1 ,
pipeline => PIPELINE,
use_dedicated_circuitry => 0 ,
widthd => 5 ,
ndirection => NDIRECTION )
port map (
clock => clock,
aclr => clear,
sclr => '0',
ena => ena,
direction => '0',
xin => a_ext ,
distance => d_ext ,
yout => r_ext );
r <= r_ext(18 - 1 downto 0);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18);
port(
a : in std_logic_vector((WIDTH)-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
direction : in std_logic;
distance : in std_logic_vector((DISTANCE_WIDTH)-1 downto 0);
ena : in std_logic;
r : out std_logic_vector((WIDTH)-1 downto 0);
user_aclr : in std_logic);
end entity;
--- The DSPBuilder BarrelShifter
architecture rtl of alt_dspbuilder_barrelshifter_GNV5DVAGHT is
signal clear : std_logic;
signal a_ext : std_logic_vector(18 downto 0);
signal d_ext : std_logic_vector(5 - 1 downto 0);
signal r_ext : std_logic_vector(18 downto 0);
Begin
clear <= aclr or user_aclr;
a_ext(18 - 1 downto 0) <= a;
a_ext(18) <= '0';
d_ext(4 - 1 downto 0) <= distance;
d_ext(5 - 1 downto 4) <= (others => '0');
BarrelShifteri : alt_dspbuilder_BarrelShiftAltr Generic map (
widthin => WIDTH + 1 ,
pipeline => PIPELINE,
use_dedicated_circuitry => 0 ,
widthd => 5 ,
ndirection => NDIRECTION )
port map (
clock => clock,
aclr => clear,
sclr => '0',
ena => ena,
direction => '0',
xin => a_ext ,
distance => d_ext ,
yout => r_ext );
r <= r_ext(18 - 1 downto 0);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18);
port(
a : in std_logic_vector((WIDTH)-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
direction : in std_logic;
distance : in std_logic_vector((DISTANCE_WIDTH)-1 downto 0);
ena : in std_logic;
r : out std_logic_vector((WIDTH)-1 downto 0);
user_aclr : in std_logic);
end entity;
--- The DSPBuilder BarrelShifter
architecture rtl of alt_dspbuilder_barrelshifter_GNV5DVAGHT is
signal clear : std_logic;
signal a_ext : std_logic_vector(18 downto 0);
signal d_ext : std_logic_vector(5 - 1 downto 0);
signal r_ext : std_logic_vector(18 downto 0);
Begin
clear <= aclr or user_aclr;
a_ext(18 - 1 downto 0) <= a;
a_ext(18) <= '0';
d_ext(4 - 1 downto 0) <= distance;
d_ext(5 - 1 downto 4) <= (others => '0');
BarrelShifteri : alt_dspbuilder_BarrelShiftAltr Generic map (
widthin => WIDTH + 1 ,
pipeline => PIPELINE,
use_dedicated_circuitry => 0 ,
widthd => 5 ,
ndirection => NDIRECTION )
port map (
clock => clock,
aclr => clear,
sclr => '0',
ena => ena,
direction => '0',
xin => a_ext ,
distance => d_ext ,
yout => r_ext );
r <= r_ext(18 - 1 downto 0);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18);
port(
a : in std_logic_vector((WIDTH)-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
direction : in std_logic;
distance : in std_logic_vector((DISTANCE_WIDTH)-1 downto 0);
ena : in std_logic;
r : out std_logic_vector((WIDTH)-1 downto 0);
user_aclr : in std_logic);
end entity;
--- The DSPBuilder BarrelShifter
architecture rtl of alt_dspbuilder_barrelshifter_GNV5DVAGHT is
signal clear : std_logic;
signal a_ext : std_logic_vector(18 downto 0);
signal d_ext : std_logic_vector(5 - 1 downto 0);
signal r_ext : std_logic_vector(18 downto 0);
Begin
clear <= aclr or user_aclr;
a_ext(18 - 1 downto 0) <= a;
a_ext(18) <= '0';
d_ext(4 - 1 downto 0) <= distance;
d_ext(5 - 1 downto 4) <= (others => '0');
BarrelShifteri : alt_dspbuilder_BarrelShiftAltr Generic map (
widthin => WIDTH + 1 ,
pipeline => PIPELINE,
use_dedicated_circuitry => 0 ,
widthd => 5 ,
ndirection => NDIRECTION )
port map (
clock => clock,
aclr => clear,
sclr => '0',
ena => ena,
direction => '0',
xin => a_ext ,
distance => d_ext ,
yout => r_ext );
r <= r_ext(18 - 1 downto 0);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18);
port(
a : in std_logic_vector((WIDTH)-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
direction : in std_logic;
distance : in std_logic_vector((DISTANCE_WIDTH)-1 downto 0);
ena : in std_logic;
r : out std_logic_vector((WIDTH)-1 downto 0);
user_aclr : in std_logic);
end entity;
--- The DSPBuilder BarrelShifter
architecture rtl of alt_dspbuilder_barrelshifter_GNV5DVAGHT is
signal clear : std_logic;
signal a_ext : std_logic_vector(18 downto 0);
signal d_ext : std_logic_vector(5 - 1 downto 0);
signal r_ext : std_logic_vector(18 downto 0);
Begin
clear <= aclr or user_aclr;
a_ext(18 - 1 downto 0) <= a;
a_ext(18) <= '0';
d_ext(4 - 1 downto 0) <= distance;
d_ext(5 - 1 downto 4) <= (others => '0');
BarrelShifteri : alt_dspbuilder_BarrelShiftAltr Generic map (
widthin => WIDTH + 1 ,
pipeline => PIPELINE,
use_dedicated_circuitry => 0 ,
widthd => 5 ,
ndirection => NDIRECTION )
port map (
clock => clock,
aclr => clear,
sclr => '0',
ena => ena,
direction => '0',
xin => a_ext ,
distance => d_ext ,
yout => r_ext );
r <= r_ext(18 - 1 downto 0);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18);
port(
a : in std_logic_vector((WIDTH)-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
direction : in std_logic;
distance : in std_logic_vector((DISTANCE_WIDTH)-1 downto 0);
ena : in std_logic;
r : out std_logic_vector((WIDTH)-1 downto 0);
user_aclr : in std_logic);
end entity;
--- The DSPBuilder BarrelShifter
architecture rtl of alt_dspbuilder_barrelshifter_GNV5DVAGHT is
signal clear : std_logic;
signal a_ext : std_logic_vector(18 downto 0);
signal d_ext : std_logic_vector(5 - 1 downto 0);
signal r_ext : std_logic_vector(18 downto 0);
Begin
clear <= aclr or user_aclr;
a_ext(18 - 1 downto 0) <= a;
a_ext(18) <= '0';
d_ext(4 - 1 downto 0) <= distance;
d_ext(5 - 1 downto 4) <= (others => '0');
BarrelShifteri : alt_dspbuilder_BarrelShiftAltr Generic map (
widthin => WIDTH + 1 ,
pipeline => PIPELINE,
use_dedicated_circuitry => 0 ,
widthd => 5 ,
ndirection => NDIRECTION )
port map (
clock => clock,
aclr => clear,
sclr => '0',
ena => ena,
direction => '0',
xin => a_ext ,
distance => d_ext ,
yout => r_ext );
r <= r_ext(18 - 1 downto 0);
end architecture; |
-- NEED RESULT: ARCH00249: All tests for Section 2.2 passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00249
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.2 (1)
-- 2.2 (2)
-- 2.2 (3)
-- 2.2 (4)
-- 2.2 (5)
-- 2.2 (6)
-- 2.2 (7)
-- 2.2 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00249)
-- ENT00249_Test_Bench(ARCH00249_Test_Bench)
--
-- REVISION HISTORY:
--
-- 15-JUL-1987 - initial revision
-- 11-DEC-1989 - GDT: removed signal asg from function
--
-- NOTES:
--
-- self-checking
--
-- Only objectives 2.2 (6) and 2.2 (7) are checked dynamically; the others
-- are static compile-time checks.
--
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00249 of E00000 is
constant c : integer := 25 ;
signal s : integer ;
-- the following proc shows that all admissable declarations may appear
-- in a subprogram declaration part 2.2 (1)
procedure proc_with_big_declarative_part is
variable x : integer ; -- variable declaration
procedure subprogram ( a,b,c : integer ) ; -- subprogram declaration
procedure subprogram ( a,b,c : integer ) is -- subprogram body
begin
end ;
type enum_type is (enum_0, enum_1, enum_2) ; -- type declaration
subtype sub_enum_type is -- subtype declaration
enum_type range enum_0 to enum_1 ;
constant k : integer := 2 ; -- constant declaration
type enum_file_type is file of enum_type ;
file enum_file : enum_file_type is in "HOSTFILENAME";
-- file declaration
alias alias_x : integer is x ; -- alias declaration
attribute enum_attribute : enum_type ; -- attribute declaration
attribute enum_attribute of all : signal is enum_0 ; -- attribute spec
use WORK.all ; -- use clause
use STANDARD_TYPES.all ; -- use clause
begin
end proc_with_big_declarative_part ;
-- the following proc shows that the ending designator is optional 2.2 (2)
-- and that a subprogram statement part need contain no statements 2.2 (4)
-- and that the declaration of a subprogram is optional 2.2 (5)
procedure proc_without_ending_designator is
begin
end ;
-- the following proc & function shows that all sequential sttements can
-- appear in a subprogram (except wait statements in a function) 2.2 (3)
-- JW: signal parameter added so that the signal assign stm would be legal
procedure proc_with_all_sequential_statements(signal s: inout integer) is
variable b : boolean ;
variable x : integer ;
begin
s <= 1 ; -- signal assign statement
assert false report "false" ; -- assertion statement
wait for 1 ns ; -- wait statement
case b is -- case statement
when false => null; -- null statement
when true => proc_without_ending_designator;-- procedure call statement
end case ;
for i in 1 to 5 loop -- loop statement via "for"
if i < 5 then -- if statement
next ; -- next statement
else
exit; -- exit statement
end if ;
end loop ;
while x < 5 loop -- loop statement via "while"
x := x + 1 ; -- variable assign statement
end loop ;
return ; -- return statement
end ;
-- the following shows that subprograms can access constants outside
-- their declarative regions 2.2 (6) and 2.2 (7)
procedure proc_called_by_func ( n: inout integer ) is
begin
n := n + c ;
end proc_called_by_func ;
function func_calling_proc ( n: integer) return integer is
variable v : integer;
begin
v := n;
proc_called_by_func(v);
return v + c ;
end func_calling_proc ;
-- the following shows that dynamically sized structures may be declared
-- within a subroutine that contains a wait statement 2.2 (8)
procedure proc_with_wait_statement ( n: integer ) is
type dyn_array is array ( integer range <> ) of integer ;
variable arr : dyn_array (1 to n) ;
begin
wait for 1 ns ;
end proc_with_wait_statement ;
begin
JW:
process
-- JW: This function was moved into a process so that the signal assign
-- statement would be legal.
function func_with_all_sequential_statements return integer is
variable b : boolean ;
variable x : integer ;
begin
-- GDT 12-7-89: s <= 1 ; -- signal assign statement
assert false report "false" ; -- assertion statement
case b is -- case statement
when false => null; -- null statement
when true => proc_without_ending_designator;-- procedure call statement
end case ;
for i in 1 to 5 loop -- loop statement via "for"
if i < 5 then -- if statement
next ; -- next statement
else
exit; -- exit statement
end if ;
end loop ;
while x < 5 loop -- loop statement via "while"
x := x + 1 ; -- variable assign statement
end loop ;
return 0 ; -- return statement
end ;
begin
wait ;
end process;
P :
process
begin
test_report ( "ARCH00249" ,
"All tests for Section 2.2 " ,
func_calling_proc (20) = 20 + 2*25 ) ;
wait ;
end process P ;
end ARCH00249 ;
entity ENT00249_Test_Bench is
end ENT00249_Test_Bench ;
architecture ARCH00249_Test_Bench of ENT00249_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00249 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00249_Test_Bench ;
|
--
-- 6502 compatible microprocessor core
--
-- Version : 0245
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
-- 0245 : First version
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end T65_ALU;
architecture rtl of T65_ALU is
-- AddSub variables (temporary signals)
signal ADC_Z : std_logic;
signal ADC_C : std_logic;
signal ADC_V : std_logic;
signal ADC_N : std_logic;
signal ADC_Q : std_logic_vector(7 downto 0);
signal SBC_Z : std_logic;
signal SBC_C : std_logic;
signal SBC_V : std_logic;
signal SBC_N : std_logic;
signal SBC_Q : std_logic_vector(7 downto 0);
begin
process (P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
begin
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
ADC_Z <= '1';
else
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
C := AL(6) or AL(5);
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
ADC_N <= AH(4);
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-- pragma translate_off
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
ADC_C <= AH(6) or AH(5);
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
begin
C := P_In(Flag_C) or not Op(0);
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
SBC_Z <= '1';
else
SBC_Z <= '0';
end if;
SBC_C <= not AH(5);
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
SBC_N <= AH(4);
if P_In(Flag_D) = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
if AH(5) = '1' then
AH(5 downto 1) := AH(5 downto 1) - 6;
end if;
end if;
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
variable Q_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
case Op(3 downto 0) is
when "0000" =>
-- ORA
Q_t := BusA or BusB;
when "0001" =>
-- AND
Q_t := BusA and BusB;
when "0010" =>
-- EOR
Q_t := BusA xor BusB;
when "0011" =>
-- ADC
P_Out(Flag_V) <= ADC_V;
P_Out(Flag_C) <= ADC_C;
Q_t := ADC_Q;
when "0101" | "1101" =>
-- LDA
when "0110" =>
-- CMP
P_Out(Flag_C) <= SBC_C;
when "0111" =>
-- SBC
P_Out(Flag_V) <= SBC_V;
P_Out(Flag_C) <= SBC_C;
Q_t := SBC_Q;
when "1000" =>
-- ASL
Q_t := BusA(6 downto 0) & "0";
P_Out(Flag_C) <= BusA(7);
when "1001" =>
-- ROL
Q_t := BusA(6 downto 0) & P_In(Flag_C);
P_Out(Flag_C) <= BusA(7);
when "1010" =>
-- LSR
Q_t := "0" & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1011" =>
-- ROR
Q_t := P_In(Flag_C) & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1100" =>
-- BIT
P_Out(Flag_V) <= BusB(6);
when "1110" =>
-- DEC
Q_t := std_logic_vector(unsigned(BusA) - 1);
when "1111" =>
-- INC
Q_t := std_logic_vector(unsigned(BusA) + 1);
when others =>
end case;
case Op(3 downto 0) is
when "0011" =>
P_Out(Flag_N) <= ADC_N;
P_Out(Flag_Z) <= ADC_Z;
when "0110" | "0111" =>
P_Out(Flag_N) <= SBC_N;
P_Out(Flag_Z) <= SBC_Z;
when "0100" =>
when "1100" =>
P_Out(Flag_N) <= BusB(7);
if (BusA and BusB) = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when others =>
P_Out(Flag_N) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
end case;
Q <= Q_t;
end process;
end;
|
-- Inertial assignment
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture arch of ENT00001_Test_Bench is
signal i : integer := 0;
signal o1 : integer := 0;
signal o2 : integer := 0;
begin
terminator : process
begin
i <= 1 after 5 us, 0 after 10 us, 1 after 20 us, 0 after 30 us;
wait for 100 us;
assert false report "end of simulation" severity failure;
end process;
o1 <= i after 8 us;
o2 <= i after 2 us;
end;
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: memory_test.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 21:10:02 $
--
--------------------------------------------------------------------------
--
-- Entity declaration for test bench for memory
--
entity memory_test is
end memory_test;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romdepth : integer := 20; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal sma_clkout : std_ulogic;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 24);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic;
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(35 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col : std_logic := '0';
signal eth_gtxclk, erx_crs, etx_en, etx_er : std_logic :='0';
signal eth_macclk : std_logic := '0';
signal erxd, etxd : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emdintn : std_logic := '1';
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
signal can_txd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_rxd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_stb : std_logic_vector(0 to CFG_CAN_NUM-1);
signal clk_1553 : std_logic;
signal busainen : std_logic;
signal busainp : std_logic;
signal busainn : std_logic;
signal busaoutin : std_logic;
signal busaoutp : std_logic;
signal busaoutn : std_logic;
signal busbinen : std_logic;
signal busbinp : std_logic;
signal busbinn : std_logic;
signal busboutin : std_logic;
signal busboutp : std_logic;
signal busboutn : std_logic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1';
dsubre <= '1'; -- inverted on the board
rxd1 <= '1';
can_rxd <= (others => 'H'); bexcn <= '1';
gpio(2 downto 0) <= "LHL";
gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
eth_macclk <= not eth_macclk after 4 ns;
ereset <= 'H';
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, sma_clkout, error, address(22 downto 0), data,
sa(12 downto 0), sa(14 downto 13), sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsubre, dsuact,
oen, writen, open, open, romsn, gpio,
emdio, eth_macclk, etx_clk, erx_clk, erxd(3 downto 0), erx_dv, erx_er,
erx_col, erx_crs, emdintn, ereset, etxd(3 downto 0), etx_en, etx_er, emdc,
can_txd, can_rxd, can_stb,
clk_1553, busainen, busainp, busainn, busaoutin, busaoutp, busaoutn,
busbinen, busbinp, busbinn, busboutin, busboutp, busboutn
);
sd1 : if ((CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1)) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
-- sram0 : for i in 0 to (sramwidth/8)-1 generate
-- sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
-- port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
-- rwen(0), ramoen(0));
-- end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(address => 16)
port map(ereset, emdio, etx_clk, erx_clk, erxd, erx_dv,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, eth_macclk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
-- test0 : grtestmod
-- port map ( rst, clk, error, address(21 downto 2), data,
-- iosn, oen, writen, brdyn);
-- data <= buskeep(data), (others => 'H') after 250 ns;
data <= buskeep(data) after 5 ns;
-- sd <= buskeep(sd), (others => 'H') after 250 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
architecture RTL of FIFO is
attribute coordinate of comp_1:component is (0.0, 17.5);
ATTRIBUTE coordinate OF comp_1:component IS (0.0, 17.5);
begin
end architecture RTL;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo.vhd when simulating
-- the core, fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo;
ARCHITECTURE fifo_a OF fifo IS
-- synthesis translate_off
COMPONENT wrapped_fifo
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fifo USE ENTITY XilinxCoreLib.fifo_generator_v8_4(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "1kx36",
c_prog_empty_thresh_assert_val => 2,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 1022,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1021,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo
PORT MAP (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END fifo_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo.vhd when simulating
-- the core, fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo;
ARCHITECTURE fifo_a OF fifo IS
-- synthesis translate_off
COMPONENT wrapped_fifo
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fifo USE ENTITY XilinxCoreLib.fifo_generator_v8_4(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "1kx36",
c_prog_empty_thresh_assert_val => 2,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 1022,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1021,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo
PORT MAP (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END fifo_a;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 22:04:02 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bid_gets_fifo_load : out STD_LOGIC;
bvalid_cnt_inc : out STD_LOGIC;
bid_gets_fifo_load_d1_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
axi_wdata_full_cmb114_out : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\bvalid_cnt_reg[2]\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
\bvalid_cnt_reg[2]_0\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
bram_addr_ld_en : in STD_LOGIC;
bid_gets_fifo_load_d1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
axi_bvalid_int_reg : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\bvalid_cnt_reg[1]\ : in STD_LOGIC;
aw_active : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
axi_wr_burst : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC;
signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal \axi_bid_int[11]_i_3_n_0\ : STD_LOGIC;
signal axi_bvalid_int_i_4_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_5_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_6_n_0 : STD_LOGIC;
signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC;
signal bid_fifo_ld : STD_LOGIC_VECTOR ( 11 downto 0 );
signal bid_fifo_not_empty : STD_LOGIC;
signal bid_fifo_rd : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^bid_gets_fifo_load\ : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC;
signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC;
signal \^bvalid_cnt_inc\ : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FIFO_RAM[0].SRL16E_I_i_1\ : label is "soft_lutpair42";
attribute BOX_TYPE of \FIFO_RAM[10].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[10].SRL16E_I_i_1\ : label is "soft_lutpair52";
attribute BOX_TYPE of \FIFO_RAM[11].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[11].SRL16E_I_i_1\ : label is "soft_lutpair53";
attribute BOX_TYPE of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[1].SRL16E_I_i_1\ : label is "soft_lutpair43";
attribute BOX_TYPE of \FIFO_RAM[2].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[2].SRL16E_I_i_1\ : label is "soft_lutpair44";
attribute BOX_TYPE of \FIFO_RAM[3].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[3].SRL16E_I_i_1\ : label is "soft_lutpair45";
attribute BOX_TYPE of \FIFO_RAM[4].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[4].SRL16E_I_i_1\ : label is "soft_lutpair46";
attribute BOX_TYPE of \FIFO_RAM[5].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[5].SRL16E_I_i_1\ : label is "soft_lutpair47";
attribute BOX_TYPE of \FIFO_RAM[6].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[6].SRL16E_I_i_1\ : label is "soft_lutpair48";
attribute BOX_TYPE of \FIFO_RAM[7].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[7].SRL16E_I_i_1\ : label is "soft_lutpair49";
attribute BOX_TYPE of \FIFO_RAM[8].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[8].SRL16E_I_i_1\ : label is "soft_lutpair50";
attribute BOX_TYPE of \FIFO_RAM[9].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[9].SRL16E_I_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \axi_bid_int[0]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[10]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \axi_bid_int[11]_i_2\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \axi_bid_int[1]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \axi_bid_int[2]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \axi_bid_int[3]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \axi_bid_int[4]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \axi_bid_int[5]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axi_bid_int[6]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \axi_bid_int[7]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \axi_bid_int[8]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \axi_bid_int[9]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair54";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair54";
begin
axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\;
bid_gets_fifo_load <= \^bid_gets_fifo_load\;
bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\;
bvalid_cnt_inc <= \^bvalid_cnt_inc\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAAAAAAAAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => \axi_bid_int[11]_i_3_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => CI
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_0,
Q => bid_fifo_not_empty,
R => SR(0)
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE0A"
)
port map (
I0 => bram_addr_ld_en,
I1 => Data_Exists_DFF_i_2_n_0,
I2 => Data_Exists_DFF_i_3_n_0,
I3 => bid_fifo_not_empty,
O => D_0
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFD"
)
port map (
I0 => \^bvalid_cnt_inc\,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
I3 => bvalid_cnt(1),
I4 => \^bid_gets_fifo_load_d1_reg\,
I5 => bid_gets_fifo_load_d1,
O => Data_Exists_DFF_i_2_n_0
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_i_3_n_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(11),
Q => bid_fifo_rd(11)
);
\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
O => bid_fifo_ld(11)
);
\FIFO_RAM[10].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(1),
Q => bid_fifo_rd(1)
);
\FIFO_RAM[10].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
O => bid_fifo_ld(1)
);
\FIFO_RAM[11].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(0),
Q => bid_fifo_rd(0)
);
\FIFO_RAM[11].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
O => bid_fifo_ld(0)
);
\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(10),
Q => bid_fifo_rd(10)
);
\FIFO_RAM[1].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
O => bid_fifo_ld(10)
);
\FIFO_RAM[2].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(9),
Q => bid_fifo_rd(9)
);
\FIFO_RAM[2].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
O => bid_fifo_ld(9)
);
\FIFO_RAM[3].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(8),
Q => bid_fifo_rd(8)
);
\FIFO_RAM[3].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
O => bid_fifo_ld(8)
);
\FIFO_RAM[4].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(7),
Q => bid_fifo_rd(7)
);
\FIFO_RAM[4].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
O => bid_fifo_ld(7)
);
\FIFO_RAM[5].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(6),
Q => bid_fifo_rd(6)
);
\FIFO_RAM[5].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
O => bid_fifo_ld(6)
);
\FIFO_RAM[6].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(5),
Q => bid_fifo_rd(5)
);
\FIFO_RAM[6].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
O => bid_fifo_ld(5)
);
\FIFO_RAM[7].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(4),
Q => bid_fifo_rd(4)
);
\FIFO_RAM[7].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
O => bid_fifo_ld(4)
);
\FIFO_RAM[8].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(3),
Q => bid_fifo_rd(3)
);
\FIFO_RAM[8].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
O => bid_fifo_ld(3)
);
\FIFO_RAM[9].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(2),
Q => bid_fifo_rd(2)
);
\FIFO_RAM[9].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
O => bid_fifo_ld(2)
);
\axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(0),
O => D(0)
);
\axi_bid_int[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(10),
O => D(10)
);
\axi_bid_int[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^bid_gets_fifo_load\,
I1 => \axi_bid_int[11]_i_3_n_0\,
O => E(0)
);
\axi_bid_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(11),
O => D(11)
);
\axi_bid_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888AAAAA8888888"
)
port map (
I0 => bid_fifo_not_empty,
I1 => bid_gets_fifo_load_d1,
I2 => s_axi_bready,
I3 => axi_bvalid_int_reg,
I4 => bid_gets_fifo_load_d1_i_3_n_0,
I5 => \^bvalid_cnt_inc\,
O => \axi_bid_int[11]_i_3_n_0\
);
\axi_bid_int[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(1),
O => D(1)
);
\axi_bid_int[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(2),
O => D(2)
);
\axi_bid_int[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(3),
O => D(3)
);
\axi_bid_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(4),
O => D(4)
);
\axi_bid_int[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(5),
O => D(5)
);
\axi_bid_int[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(6),
O => D(6)
);
\axi_bid_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(7),
O => D(7)
);
\axi_bid_int[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(8),
O => D(8)
);
\axi_bid_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(9),
O => D(9)
);
axi_bvalid_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000055FD00000000"
)
port map (
I0 => \out\(2),
I1 => \^axi_wdata_full_cmb114_out\,
I2 => axi_bvalid_int_i_4_n_0,
I3 => axi_wr_burst,
I4 => \out\(1),
I5 => axi_bvalid_int_i_5_n_0,
O => \^bvalid_cnt_inc\
);
axi_bvalid_int_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FE000000"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => axi_bvalid_int_reg,
I4 => s_axi_bready,
O => \^bid_gets_fifo_load_d1_reg\
);
axi_bvalid_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"1F11000000000000"
)
port map (
I0 => axi_bvalid_int_i_6_n_0,
I1 => \bvalid_cnt_reg[2]\,
I2 => wr_addr_sm_cs,
I3 => \bvalid_cnt_reg[2]_0\,
I4 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I5 => axi_awaddr_full,
O => axi_bvalid_int_i_4_n_0
);
axi_bvalid_int_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"74446444"
)
port map (
I0 => \out\(0),
I1 => \out\(2),
I2 => s_axi_wvalid,
I3 => s_axi_wlast,
I4 => \^axi_wdata_full_cmb114_out\,
O => axi_bvalid_int_i_5_n_0
);
axi_bvalid_int_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => curr_awlen_reg_1_or_2,
I1 => axi_awlen_pipe_1_or_2,
I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I3 => axi_awaddr_full,
I4 => last_data_ack_mod,
O => axi_bvalid_int_i_6_n_0
);
axi_wready_int_mod_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F007F007F00"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => aw_active,
I4 => s_axi_awready,
I5 => s_axi_awvalid,
O => \^axi_wdata_full_cmb114_out\
);
bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800AA00AA00"
)
port map (
I0 => bram_addr_ld_en,
I1 => \^bid_gets_fifo_load_d1_reg\,
I2 => bid_fifo_not_empty,
I3 => \^bvalid_cnt_inc\,
I4 => \bvalid_cnt_reg[1]\,
I5 => bid_gets_fifo_load_d1_i_3_n_0,
O => \^bid_gets_fifo_load\
);
bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => bid_gets_fifo_load_d1_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
port (
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
bram_addr_ld_en_mod : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
\save_init_bram_addr_ld_reg[12]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC;
bram_addr_ld_en : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_1\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_2\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_3\ : out STD_LOGIC;
curr_fixed_burst_reg_reg : out STD_LOGIC;
curr_wrap_burst_reg_reg : out STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
bram_addr_inc : in STD_LOGIC;
bram_addr_rst_cmb : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
aw_active : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
curr_fixed_burst : in STD_LOGIC;
curr_wrap_burst : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^bram_addr_ld_en_mod\ : STD_LOGIC;
signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 12 downto 3 );
signal \save_init_bram_addr_ld[12]_i_6_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[12]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^save_init_bram_addr_ld_reg[12]_1\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[12]_2\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[12]_3\ : STD_LOGIC;
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \curr_fixed_burst_reg_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[12]_i_5\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[12]_i_6\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_2__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_3__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair55";
begin
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\;
bram_addr_ld_en <= \^bram_addr_ld_en\;
bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\;
\save_init_bram_addr_ld_reg[12]_0\(0) <= \^save_init_bram_addr_ld_reg[12]_0\(0);
\save_init_bram_addr_ld_reg[12]_1\ <= \^save_init_bram_addr_ld_reg[12]_1\;
\save_init_bram_addr_ld_reg[12]_2\ <= \^save_init_bram_addr_ld_reg[12]_2\;
\save_init_bram_addr_ld_reg[12]_3\ <= \^save_init_bram_addr_ld_reg[12]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB8BBBBB88B88888"
)
port map (
I0 => bram_addr_ld(8),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(7),
I5 => bram_addr_a(8),
O => D(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"4500FFFF"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => bram_addr_inc,
I3 => bram_addr_rst_cmb,
I4 => s_axi_aresetn,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(9),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(9),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\,
I4 => bram_addr_a(8),
O => D(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0\,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => \^bram_addr_ld_en_mod\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFFDF"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => wrap_burst_total(1),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(0),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00C000"
)
port map (
I0 => bram_addr_a(2),
I1 => bram_addr_a(1),
I2 => wrap_burst_total(1),
I3 => bram_addr_a(0),
I4 => wrap_burst_total(0),
I5 => wrap_burst_total(2),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B800FFFF"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
I1 => axi_awaddr_full,
I2 => s_axi_awaddr(0),
I3 => \^bram_addr_ld_en\,
I4 => \^bram_addr_ld_en_mod\,
I5 => bram_addr_a(0),
O => D(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => bram_addr_ld(1),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(1),
I3 => bram_addr_a(0),
O => D(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BB8B8B8"
)
port map (
I0 => bram_addr_ld(2),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(2),
I3 => bram_addr_a(0),
I4 => bram_addr_a(1),
O => D(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BB8B8B8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(3),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(3),
I3 => bram_addr_a(2),
I4 => bram_addr_a(0),
I5 => bram_addr_a(1),
O => D(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => bram_addr_ld(4),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
O => D(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(5),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(5),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I4 => bram_addr_a(4),
O => D(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B88BB8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(6),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => bram_addr_a(4),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => bram_addr_a(5),
O => D(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => bram_addr_a(1),
I1 => bram_addr_a(0),
I2 => bram_addr_a(2),
I3 => bram_addr_a(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(7),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(6),
O => D(7)
);
\curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_fixed_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_fixed_burst,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
O => curr_fixed_burst_reg_reg
);
\curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_wrap_burst,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
O => curr_wrap_burst_reg_reg
);
\save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(10),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(8),
O => bram_addr_ld(8)
);
\save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(11),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(9),
O => bram_addr_ld(9)
);
\save_init_bram_addr_ld[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808080808AA0808"
)
port map (
I0 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I1 => \^save_init_bram_addr_ld_reg[12]_1\,
I2 => wr_addr_sm_cs,
I3 => \^save_init_bram_addr_ld_reg[12]_2\,
I4 => last_data_ack_mod,
I5 => \^save_init_bram_addr_ld_reg[12]_3\,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(12),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(10),
O => \^save_init_bram_addr_ld_reg[12]_0\(0)
);
\save_init_bram_addr_ld[12]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"007F007F007F0000"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
I3 => aw_active,
I4 => axi_awaddr_full,
I5 => s_axi_awvalid,
O => \^save_init_bram_addr_ld_reg[12]_1\
);
\save_init_bram_addr_ld[12]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => \^save_init_bram_addr_ld_reg[12]_2\
);
\save_init_bram_addr_ld[12]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I2 => axi_awlen_pipe_1_or_2,
I3 => curr_awlen_reg_1_or_2,
O => \^save_init_bram_addr_ld_reg[12]_3\
);
\save_init_bram_addr_ld[12]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0\,
O => \save_init_bram_addr_ld[12]_i_6_n_0\
);
\save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\,
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(1),
O => bram_addr_ld(1)
);
\save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"C80C"
)
port map (
I0 => wrap_burst_total(0),
I1 => save_init_bram_addr_ld(3),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[3]_i_2__0_n_0\
);
\save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\,
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(2),
O => bram_addr_ld(2)
);
\save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => save_init_bram_addr_ld(4),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[4]_i_2__0_n_0\
);
\save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F808F8F8F808080"
)
port map (
I0 => save_init_bram_addr_ld(5),
I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\,
I2 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
I4 => axi_awaddr_full,
I5 => s_axi_awaddr(3),
O => bram_addr_ld(3)
);
\save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => wrap_burst_total(0),
I1 => wrap_burst_total(2),
I2 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[5]_i_2__0_n_0\
);
\save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(6),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(4),
O => bram_addr_ld(4)
);
\save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(7),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(5),
O => bram_addr_ld(5)
);
\save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(8),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(6),
O => bram_addr_ld(6)
);
\save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(9),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(7),
O => bram_addr_ld(7)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(8),
Q => save_init_bram_addr_ld(10),
R => SR(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(9),
Q => save_init_bram_addr_ld(11),
R => SR(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^save_init_bram_addr_ld_reg[12]_0\(0),
Q => save_init_bram_addr_ld(12),
R => SR(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(1),
Q => save_init_bram_addr_ld(3),
R => SR(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(2),
Q => save_init_bram_addr_ld(4),
R => SR(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(3),
Q => save_init_bram_addr_ld(5),
R => SR(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(4),
Q => save_init_bram_addr_ld(6),
R => SR(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(5),
Q => save_init_bram_addr_ld(7),
R => SR(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(6),
Q => save_init_bram_addr_ld(8),
R => SR(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(7),
Q => save_init_bram_addr_ld(9),
R => SR(0)
);
\wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A22200000000"
)
port map (
I0 => \wrap_burst_total[0]_i_2__0_n_0\,
I1 => \wrap_burst_total[0]_i_3_n_0\,
I2 => Q(1),
I3 => Q(2),
I4 => \wrap_burst_total[2]_i_2__0_n_0\,
I5 => \wrap_burst_total[1]_i_2__0_n_0\,
O => \wrap_burst_total[0]_i_1__0_n_0\
);
\wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCA533A5FFA5FFA5"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
I5 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_2__0_n_0\
);
\wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_awaddr_full,
I1 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_3_n_0\
);
\wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08000800F3000000"
)
port map (
I0 => \wrap_burst_total[2]_i_3_n_0\,
I1 => axi_awaddr_full,
I2 => axi_awsize_pipe(0),
I3 => \wrap_burst_total[1]_i_2__0_n_0\,
I4 => \wrap_burst_total[1]_i_3__0_n_0\,
I5 => \wrap_burst_total[2]_i_2__0_n_0\,
O => \wrap_burst_total[1]_i_1__0_n_0\
);
\wrap_burst_total[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(0),
O => \wrap_burst_total[1]_i_2__0_n_0\
);
\wrap_burst_total[1]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(1),
O => \wrap_burst_total[1]_i_3__0_n_0\
);
\wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000000088008800"
)
port map (
I0 => \wrap_burst_total[2]_i_2__0_n_0\,
I1 => s_axi_awlen(0),
I2 => Q(0),
I3 => \wrap_burst_total[2]_i_3_n_0\,
I4 => axi_awsize_pipe(0),
I5 => axi_awaddr_full,
O => \wrap_burst_total[2]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(3),
O => \wrap_burst_total[2]_i_2__0_n_0\
);
\wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
O => \wrap_burst_total[2]_i_3_n_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1__0_n_0\,
Q => wrap_burst_total(0),
R => SR(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1__0_n_0\,
Q => wrap_burst_total(1),
R => SR(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1__0_n_0\,
Q => wrap_burst_total(2),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
port (
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_1\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_3\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
bram_addr_ld_en : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_data_sm_cs_reg[1]\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_1\ : out STD_LOGIC;
axi_b2b_brst_reg : out STD_LOGIC;
\rd_data_sm_cs_reg[3]\ : out STD_LOGIC;
rd_adv_buf67_out : out STD_LOGIC;
end_brst_rd : in STD_LOGIC;
brst_zero : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_rvalid_int_reg : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
axi_araddr_full : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
curr_fixed_burst_reg : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
axi_rd_burst_two_reg : in STD_LOGIC;
axi_rd_burst : in STD_LOGIC;
axi_aresetn_d2 : in STD_LOGIC;
rd_addr_sm_cs : in STD_LOGIC;
last_bram_addr : in STD_LOGIC;
ar_active : in STD_LOGIC;
pend_rd_op : in STD_LOGIC;
no_ar_ack : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_b2b_brst : in STD_LOGIC;
axi_arsize_pipe_max : in STD_LOGIC;
disable_b2b_brst : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_arlen_pipe_1_or_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 : entity is "wrap_brst";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axi_b2b_brst_reg\ : STD_LOGIC;
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^rd_adv_buf67_out\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[12]_i_3__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[12]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^save_init_bram_addr_ld_reg[12]_1\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_3\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_1\ : label is "soft_lutpair0";
begin
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\;
SR(0) <= \^sr\(0);
axi_b2b_brst_reg <= \^axi_b2b_brst_reg\;
bram_addr_ld_en <= \^bram_addr_ld_en\;
rd_adv_buf67_out <= \^rd_adv_buf67_out\;
\rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\;
\rd_data_sm_cs_reg[3]\ <= \^rd_data_sm_cs_reg[3]\;
\save_init_bram_addr_ld_reg[12]_0\(0) <= \^save_init_bram_addr_ld_reg[12]_0\(0);
\save_init_bram_addr_ld_reg[12]_1\ <= \^save_init_bram_addr_ld_reg[12]_1\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\;
\wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\;
\wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF20FFFFDF200000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(8),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
O => D(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\,
I2 => curr_fixed_burst_reg,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(8),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
O => D(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0F0F0E0E0FFF0"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\,
I2 => \^rd_data_sm_cs_reg[1]\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I4 => Q(1),
I5 => Q(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => Q(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080800080"
)
port map (
I0 => Q(0),
I1 => axi_rvalid_int_reg,
I2 => s_axi_rready,
I3 => end_brst_rd,
I4 => axi_b2b_brst,
I5 => brst_zero,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A808FD5D"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => s_axi_araddr(0),
I2 => axi_araddr_full,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
O => D(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A80000"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0\,
I2 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I4 => curr_wrap_burst_reg,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00A000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(2),
I2 => \wrap_burst_total_reg_n_0_[1]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I4 => \wrap_burst_total_reg_n_0_[0]\,
I5 => \wrap_burst_total_reg_n_0_[2]\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
O => D(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFF6A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(2),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
O => D(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(3),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(2),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
O => D(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(4),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
O => D(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(5),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
O => D(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAFFFFA6AA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(4),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(5),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
O => D(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(2),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(6),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
O => D(7)
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rvalid_int_reg,
I1 => s_axi_rready,
O => \^rd_adv_buf67_out\
);
axi_b2b_brst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => axi_arsize_pipe_max,
I1 => disable_b2b_brst,
I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\,
I3 => axi_arlen_pipe_1_or_2,
I4 => axi_araddr_full,
O => \^axi_b2b_brst_reg\
);
bram_en_int_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => Q(3),
I1 => Q(2),
O => \^rd_data_sm_cs_reg[3]\
);
bram_en_int_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => end_brst_rd,
I1 => brst_zero,
I2 => Q(2),
I3 => Q(0),
I4 => axi_rvalid_int_reg,
I5 => s_axi_rready,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
bram_rst_b_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000E000F0000"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => axi_rd_burst,
I2 => Q(3),
I3 => Q(2),
I4 => Q(1),
I5 => Q(0),
O => \^rd_data_sm_cs_reg[1]\
);
\save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[10]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(8),
O => \save_init_bram_addr_ld[10]_i_1__0_n_0\
);
\save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(9),
O => \save_init_bram_addr_ld[11]_i_1__0_n_0\
);
\save_init_bram_addr_ld[12]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"02AA0202"
)
port map (
I0 => axi_aresetn_d2,
I1 => rd_addr_sm_cs,
I2 => \save_init_bram_addr_ld[12]_i_3__0_n_0\,
I3 => \^save_init_bram_addr_ld_reg[12]_1\,
I4 => last_bram_addr,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[12]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[12]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(10),
O => \^save_init_bram_addr_ld_reg[12]_0\(0)
);
\save_init_bram_addr_ld[12]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFEFEFF"
)
port map (
I0 => ar_active,
I1 => pend_rd_op,
I2 => no_ar_ack,
I3 => s_axi_arvalid,
I4 => axi_araddr_full,
O => \save_init_bram_addr_ld[12]_i_3__0_n_0\
);
\save_init_bram_addr_ld[12]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \^axi_b2b_brst_reg\,
I1 => Q(0),
I2 => Q(1),
I3 => \^rd_data_sm_cs_reg[3]\,
I4 => brst_zero,
I5 => \^rd_adv_buf67_out\,
O => \^save_init_bram_addr_ld_reg[12]_1\
);
\save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(1),
O => \save_init_bram_addr_ld[3]_i_1__0_n_0\
);
\save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A282"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[3]\,
I1 => \wrap_burst_total_reg_n_0_[1]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[0]\,
O => \save_init_bram_addr_ld[3]_i_2_n_0\
);
\save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(2),
O => \save_init_bram_addr_ld[4]_i_1__0_n_0\
);
\save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[4]\,
I1 => \wrap_burst_total_reg_n_0_[0]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[4]_i_2_n_0\
);
\save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[5]\,
I1 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
I4 => axi_araddr_full,
I5 => s_axi_araddr(3),
O => \save_init_bram_addr_ld[5]_i_1__0_n_0\
);
\save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \wrap_burst_total_reg_n_0_[0]\,
I1 => \wrap_burst_total_reg_n_0_[2]\,
I2 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[5]_i_2_n_0\
);
\save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[6]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(4),
O => \save_init_bram_addr_ld[6]_i_1__0_n_0\
);
\save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[7]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(5),
O => \save_init_bram_addr_ld[7]_i_1__0_n_0\
);
\save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[8]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(6),
O => \save_init_bram_addr_ld[8]_i_1__0_n_0\
);
\save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[9]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(7),
O => \save_init_bram_addr_ld[9]_i_1__0_n_0\
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[10]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[11]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^save_init_bram_addr_ld_reg[12]_0\(0),
Q => \save_init_bram_addr_ld_reg_n_0_[12]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[3]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[4]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[5]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[6]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[7]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[8]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[9]\,
R => \^sr\(0)
);
\wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3202010100000000"
)
port map (
I0 => \^wrap_burst_total_reg[0]_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => \wrap_burst_total[0]_i_3__0_n_0\,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I4 => \^wrap_burst_total_reg[0]_2\,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[0]_i_1_n_0\
);
\wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I1 => axi_araddr_full,
I2 => s_axi_arlen(2),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
O => \wrap_burst_total[0]_i_3__0_n_0\
);
\wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"20CF000000000000"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I1 => axi_arsize_pipe(0),
I2 => axi_araddr_full,
I3 => \^wrap_burst_total_reg[0]_1\,
I4 => \^wrap_burst_total_reg[0]_3\,
I5 => \^wrap_burst_total_reg[0]_2\,
O => \wrap_burst_total[1]_i_1_n_0\
);
\wrap_burst_total[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3),
I1 => axi_araddr_full,
I2 => s_axi_arlen(3),
O => \^wrap_burst_total_reg[0]_1\
);
\wrap_burst_total[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(0),
I1 => axi_araddr_full,
I2 => s_axi_arlen(0),
O => \^wrap_burst_total_reg[0]_3\
);
\wrap_burst_total[1]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
O => \^wrap_burst_total_reg[0]_2\
);
\wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000D580"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
I2 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I3 => s_axi_arlen(2),
I4 => \wrap_burst_total[2]_i_2_n_0\,
O => \wrap_burst_total[2]_i_1_n_0\
);
\wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FFF5F5F3FFFFFFF"
)
port map (
I0 => s_axi_arlen(3),
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3),
I2 => \^wrap_burst_total_reg[0]_3\,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1),
I4 => axi_araddr_full,
I5 => s_axi_arlen(1),
O => \wrap_burst_total[2]_i_2_n_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[0]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[1]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[2]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
port (
bram_rst_a : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_arready : out STD_LOGIC;
bram_addr_b : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aclk : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
axi_aresetn_d2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_aresetn_re_reg : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_4_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_5_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_5 : STD_LOGIC;
signal I_WRAP_BRST_n_6 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal act_rd_burst : STD_LOGIC;
signal act_rd_burst_i_1_n_0 : STD_LOGIC;
signal act_rd_burst_i_3_n_0 : STD_LOGIC;
signal act_rd_burst_i_4_n_0 : STD_LOGIC;
signal act_rd_burst_set : STD_LOGIC;
signal act_rd_burst_two : STD_LOGIC;
signal act_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal ar_active : STD_LOGIC;
signal araddr_pipe_ld43_out : STD_LOGIC;
signal axi_araddr_full : STD_LOGIC;
signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_arid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_arlen_pipe_1_or_2 : STD_LOGIC;
signal axi_arready_int : STD_LOGIC;
signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_arsize_pipe_max : STD_LOGIC;
signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst : STD_LOGIC;
signal axi_b2b_brst_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst_i_3_n_0 : STD_LOGIC;
signal axi_early_arready_int : STD_LOGIC;
signal axi_rd_burst : STD_LOGIC;
signal axi_rd_burst_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_i_2_n_0 : STD_LOGIC;
signal axi_rd_burst_i_3_n_0 : STD_LOGIC;
signal axi_rd_burst_two : STD_LOGIC;
signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_two_reg_n_0 : STD_LOGIC;
signal axi_rid_temp : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp20_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2_full : STD_LOGIC;
signal axi_rid_temp_full : STD_LOGIC;
signal axi_rid_temp_full_d1 : STD_LOGIC;
signal axi_rlast_int_i_1_n_0 : STD_LOGIC;
signal axi_rlast_set : STD_LOGIC;
signal axi_rvalid_clr_ok : STD_LOGIC;
signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC;
signal axi_rvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_set : STD_LOGIC;
signal axi_rvalid_set_cmb : STD_LOGIC;
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bram_addr_ld_en : STD_LOGIC;
signal \^bram_en_b\ : STD_LOGIC;
signal bram_en_int_i_10_n_0 : STD_LOGIC;
signal bram_en_int_i_11_n_0 : STD_LOGIC;
signal bram_en_int_i_1_n_0 : STD_LOGIC;
signal bram_en_int_i_2_n_0 : STD_LOGIC;
signal bram_en_int_i_3_n_0 : STD_LOGIC;
signal bram_en_int_i_4_n_0 : STD_LOGIC;
signal bram_en_int_i_6_n_0 : STD_LOGIC;
signal bram_en_int_i_7_n_0 : STD_LOGIC;
signal bram_en_int_i_9_n_0 : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal brst_cnt_max : STD_LOGIC;
signal brst_cnt_max_d1 : STD_LOGIC;
signal brst_one : STD_LOGIC;
signal brst_one0 : STD_LOGIC;
signal brst_one_i_1_n_0 : STD_LOGIC;
signal brst_zero : STD_LOGIC;
signal brst_zero_i_1_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal disable_b2b_brst : STD_LOGIC;
signal disable_b2b_brst_cmb : STD_LOGIC;
signal disable_b2b_brst_i_2_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_3_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_4_n_0 : STD_LOGIC;
signal end_brst_rd : STD_LOGIC;
signal end_brst_rd_clr : STD_LOGIC;
signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC;
signal end_brst_rd_i_1_n_0 : STD_LOGIC;
signal last_bram_addr : STD_LOGIC;
signal last_bram_addr0 : STD_LOGIC;
signal last_bram_addr_i_10_n_0 : STD_LOGIC;
signal last_bram_addr_i_2_n_0 : STD_LOGIC;
signal last_bram_addr_i_3_n_0 : STD_LOGIC;
signal last_bram_addr_i_4_n_0 : STD_LOGIC;
signal last_bram_addr_i_5_n_0 : STD_LOGIC;
signal last_bram_addr_i_6_n_0 : STD_LOGIC;
signal last_bram_addr_i_7_n_0 : STD_LOGIC;
signal last_bram_addr_i_8_n_0 : STD_LOGIC;
signal last_bram_addr_i_9_n_0 : STD_LOGIC;
signal no_ar_ack : STD_LOGIC;
signal no_ar_ack_i_1_n_0 : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_26_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pend_rd_op : STD_LOGIC;
signal pend_rd_op_i_1_n_0 : STD_LOGIC;
signal pend_rd_op_i_2_n_0 : STD_LOGIC;
signal pend_rd_op_i_3_n_0 : STD_LOGIC;
signal pend_rd_op_i_4_n_0 : STD_LOGIC;
signal pend_rd_op_i_5_n_0 : STD_LOGIC;
signal pend_rd_op_i_6_n_0 : STD_LOGIC;
signal pend_rd_op_i_7_n_0 : STD_LOGIC;
signal rd_addr_sm_cs : STD_LOGIC;
signal rd_adv_buf67_out : STD_LOGIC;
signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC;
signal rd_data_sm_ns : STD_LOGIC;
signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_skid_buf_ld : STD_LOGIC;
signal rd_skid_buf_ld_cmb : STD_LOGIC;
signal rd_skid_buf_ld_reg : STD_LOGIC;
signal rddata_mux_sel : STD_LOGIC;
signal rddata_mux_sel_cmb : STD_LOGIC;
signal rddata_mux_sel_i_1_n_0 : STD_LOGIC;
signal rddata_mux_sel_i_3_n_0 : STD_LOGIC;
signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of rlast_sm_cs : signal is "yes";
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_AR_DUAL.ar_active_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[0]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[10]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[11]_i_2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[1]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[4]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[5]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[6]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[7]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[8]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[9]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_3 : label is "soft_lutpair30";
attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of last_bram_addr_i_10 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of last_bram_addr_i_3 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of last_bram_addr_i_6 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of last_bram_addr_i_8 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of pend_rd_op_i_5 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_4\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_5\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_5\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair11";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
bram_addr_b(0) <= \^bram_addr_b\(0);
bram_en_b <= \^bram_en_b\;
bram_rst_a <= \^bram_rst_a\;
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rvalid <= \^s_axi_rvalid\;
\/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0011001300130013"
)
port map (
I0 => axi_rd_burst,
I1 => rlast_sm_cs(1),
I2 => act_rd_burst_two,
I3 => axi_rd_burst_two_reg_n_0,
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\
);
\/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"003F007F003F0055"
)
port map (
I0 => axi_rd_burst,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rlast_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_two,
O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\
);
\/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F111F000E000"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rlast_sm_cs(0),
I5 => last_bram_addr,
O => \/i__n_0\
);
\/i___0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080000F8080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(1),
I4 => rlast_sm_cs(2),
I5 => \^s_axi_rlast\,
O => axi_rlast_set
);
\FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(0),
O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(1),
O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A4FFFF00A40000"
)
port map (
I0 => rlast_sm_cs(1),
I1 => p_0_in13_in,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(2),
I4 => \/i__n_0\,
I5 => rlast_sm_cs(2),
O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst,
O => p_0_in13_in
);
\FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\,
Q => rlast_sm_cs(0),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\,
Q => rlast_sm_cs(1),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\,
Q => rlast_sm_cs(2),
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEEE"
)
port map (
I0 => p_9_out,
I1 => axi_arready_int,
I2 => s_axi_arvalid,
I3 => axi_araddr_full,
I4 => araddr_pipe_ld43_out,
O => \GEN_ARREADY.axi_arready_int_i_1_n_0\
);
\GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BAAA"
)
port map (
I0 => axi_aresetn_re_reg,
I1 => axi_early_arready_int,
I2 => axi_araddr_full,
I3 => bram_addr_ld_en,
O => p_9_out
);
\GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_ARREADY.axi_arready_int_i_1_n_0\,
Q => axi_arready_int,
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\,
I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\,
I2 => rd_data_sm_cs(3),
I3 => brst_one,
I4 => axi_arready_int,
I5 => I_WRAP_BRST_n_23,
O => p_48_out
);
\GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CC304400000044"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => axi_araddr_full,
I1 => s_axi_arvalid,
O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\
);
\GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_48_out,
Q => axi_early_arready_int,
R => \^bram_rst_a\
);
\GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDCDCDDDCCCCCCCC"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => \GEN_AR_DUAL.ar_active_i_3_n_0\,
I3 => end_brst_rd,
I4 => brst_zero,
I5 => ar_active,
O => \GEN_AR_DUAL.ar_active_i_1_n_0\
);
\GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"808880808088A280"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I1 => rd_data_sm_cs(1),
I2 => \GEN_AR_DUAL.ar_active_i_5_n_0\,
I3 => rd_data_sm_cs(0),
I4 => axi_rd_burst_two_reg_n_0,
I5 => axi_rd_burst,
O => \GEN_AR_DUAL.ar_active_i_2_n_0\
);
\GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \GEN_AR_DUAL.ar_active_i_3_n_0\
);
\GEN_AR_DUAL.ar_active_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
O => \GEN_AR_DUAL.ar_active_i_4_n_0\
);
\GEN_AR_DUAL.ar_active_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A88000000000000"
)
port map (
I0 => I_WRAP_BRST_n_24,
I1 => brst_zero,
I2 => axi_b2b_brst,
I3 => end_brst_rd,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => \GEN_AR_DUAL.ar_active_i_5_n_0\
);
\GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.ar_active_i_1_n_0\,
Q => ar_active,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10001000F0F01000"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I4 => last_bram_addr,
I5 => I_WRAP_BRST_n_23,
O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\
);
\GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\,
Q => rd_addr_sm_cs,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(8),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(9),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(10),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(0),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(1),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(2),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(3),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(4),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(5),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(6),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(7),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C08888CCCC8888"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => s_axi_aresetn,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I4 => axi_araddr_full,
I5 => bram_addr_ld_en,
O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\,
Q => axi_araddr_full,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"03AA"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
I1 => s_axi_arburst(0),
I2 => s_axi_arburst(1),
I3 => araddr_pipe_ld43_out,
O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(0),
Q => axi_arburst_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(1),
Q => axi_arburst_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(0),
Q => axi_arid_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(10),
Q => axi_arid_pipe(10),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(11),
Q => axi_arid_pipe(11),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(1),
Q => axi_arid_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(2),
Q => axi_arid_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(3),
Q => axi_arid_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(4),
Q => axi_arid_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(5),
Q => axi_arid_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(6),
Q => axi_arid_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(7),
Q => axi_arid_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(8),
Q => axi_arid_pipe(8),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(9),
Q => axi_arid_pipe(9),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220022002A002200"
)
port map (
I0 => axi_aresetn_d2,
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I2 => rd_addr_sm_cs,
I3 => s_axi_arvalid,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I5 => axi_araddr_full,
O => araddr_pipe_ld43_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => I_WRAP_BRST_n_23,
I1 => last_bram_addr,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => no_ar_ack,
I1 => pend_rd_op,
I2 => ar_active,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arlen(7),
I1 => s_axi_arlen(1),
I2 => s_axi_arlen(3),
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\,
O => p_13_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_axi_arlen(5),
I1 => s_axi_arlen(4),
I2 => s_axi_arlen(2),
I3 => s_axi_arlen(6),
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => p_13_out,
Q => axi_arlen_pipe_1_or_2,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(0),
Q => axi_arlen_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(1),
Q => axi_arlen_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(2),
Q => axi_arlen_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(3),
Q => axi_arlen_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(4),
Q => axi_arlen_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(5),
Q => axi_arlen_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(6),
Q => axi_arlen_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(7),
Q => axi_arlen_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => '1',
Q => axi_arsize_pipe(1),
R => '0'
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => brst_cnt_max,
I1 => pend_rd_op,
I2 => ar_active,
I3 => brst_zero,
I4 => s_axi_aresetn,
I5 => bram_addr_ld_en,
O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\,
Q => brst_cnt_max,
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \^q\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => I_WRAP_BRST_n_20,
I3 => \^q\(5),
I4 => \^q\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => I_WRAP_BRST_n_21,
I1 => I_WRAP_BRST_n_7,
I2 => \^bram_addr_b\(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_10,
Q => \^q\(8),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_9,
Q => \^q\(9),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\,
Q => \^bram_addr_b\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_18,
Q => \^q\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_17,
Q => \^q\(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_16,
Q => \^q\(2),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_15,
Q => \^q\(3),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_14,
Q => \^q\(4),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_13,
Q => \^q\(5),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_12,
Q => \^q\(6),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_11,
Q => \^q\(7),
R => '0'
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(0),
I1 => bram_rddata_b(0),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\,
Q => s_axi_rdata(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(10),
I1 => bram_rddata_b(10),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\,
Q => s_axi_rdata(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(11),
I1 => bram_rddata_b(11),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\,
Q => s_axi_rdata(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(12),
I1 => bram_rddata_b(12),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\,
Q => s_axi_rdata(12),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(13),
I1 => bram_rddata_b(13),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\,
Q => s_axi_rdata(13),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(14),
I1 => bram_rddata_b(14),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\,
Q => s_axi_rdata(14),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(15),
I1 => bram_rddata_b(15),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\,
Q => s_axi_rdata(15),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(16),
I1 => bram_rddata_b(16),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\,
Q => s_axi_rdata(16),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(17),
I1 => bram_rddata_b(17),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\,
Q => s_axi_rdata(17),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(18),
I1 => bram_rddata_b(18),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\,
Q => s_axi_rdata(18),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(19),
I1 => bram_rddata_b(19),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\,
Q => s_axi_rdata(19),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(1),
I1 => bram_rddata_b(1),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\,
Q => s_axi_rdata(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(20),
I1 => bram_rddata_b(20),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\,
Q => s_axi_rdata(20),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(21),
I1 => bram_rddata_b(21),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\,
Q => s_axi_rdata(21),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(22),
I1 => bram_rddata_b(22),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\,
Q => s_axi_rdata(22),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(23),
I1 => bram_rddata_b(23),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\,
Q => s_axi_rdata(23),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(24),
I1 => bram_rddata_b(24),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\,
Q => s_axi_rdata(24),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(25),
I1 => bram_rddata_b(25),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\,
Q => s_axi_rdata(25),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(26),
I1 => bram_rddata_b(26),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\,
Q => s_axi_rdata(26),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(27),
I1 => bram_rddata_b(27),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\,
Q => s_axi_rdata(27),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(28),
I1 => bram_rddata_b(28),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\,
Q => s_axi_rdata(28),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(29),
I1 => bram_rddata_b(29),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\,
Q => s_axi_rdata(29),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(2),
I1 => bram_rddata_b(2),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\,
Q => s_axi_rdata(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(30),
I1 => bram_rddata_b(30),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\,
Q => s_axi_rdata(30),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414545410000404"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\,
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(31),
I1 => bram_rddata_b(31),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
Q => s_axi_rdata(31),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(3),
I1 => bram_rddata_b(3),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\,
Q => s_axi_rdata(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(4),
I1 => bram_rddata_b(4),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\,
Q => s_axi_rdata(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(5),
I1 => bram_rddata_b(5),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\,
Q => s_axi_rdata(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(6),
I1 => bram_rddata_b(6),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\,
Q => s_axi_rdata(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(7),
I1 => bram_rddata_b(7),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\,
Q => s_axi_rdata(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(8),
I1 => bram_rddata_b(8),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\,
Q => s_axi_rdata(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(9),
I1 => bram_rddata_b(9),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\,
Q => s_axi_rdata(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAEAA"
)
port map (
I0 => rd_skid_buf_ld_reg,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(3),
O => rd_skid_buf_ld
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(0),
Q => rd_skid_buf(0),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(10),
Q => rd_skid_buf(10),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(11),
Q => rd_skid_buf(11),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(12),
Q => rd_skid_buf(12),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(13),
Q => rd_skid_buf(13),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(14),
Q => rd_skid_buf(14),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(15),
Q => rd_skid_buf(15),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(16),
Q => rd_skid_buf(16),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(17),
Q => rd_skid_buf(17),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(18),
Q => rd_skid_buf(18),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(19),
Q => rd_skid_buf(19),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(1),
Q => rd_skid_buf(1),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(20),
Q => rd_skid_buf(20),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(21),
Q => rd_skid_buf(21),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(22),
Q => rd_skid_buf(22),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(23),
Q => rd_skid_buf(23),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(24),
Q => rd_skid_buf(24),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(25),
Q => rd_skid_buf(25),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(26),
Q => rd_skid_buf(26),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(27),
Q => rd_skid_buf(27),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(28),
Q => rd_skid_buf(28),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(29),
Q => rd_skid_buf(29),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(2),
Q => rd_skid_buf(2),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(30),
Q => rd_skid_buf(30),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(31),
Q => rd_skid_buf(31),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(3),
Q => rd_skid_buf(3),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(4),
Q => rd_skid_buf(4),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(5),
Q => rd_skid_buf(5),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(6),
Q => rd_skid_buf(6),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(7),
Q => rd_skid_buf(7),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(8),
Q => rd_skid_buf(8),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(9),
Q => rd_skid_buf(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_int[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
I2 => axi_b2b_brst,
I3 => s_axi_aresetn,
O => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_rvalid_set,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => axi_b2b_brst,
O => p_4_out
);
\GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(0),
Q => s_axi_rid(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(10),
Q => s_axi_rid(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(11),
Q => s_axi_rid(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(1),
Q => s_axi_rid(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(2),
Q => s_axi_rid(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(3),
Q => s_axi_rid(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(4),
Q => s_axi_rid(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(5),
Q => s_axi_rid(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(6),
Q => s_axi_rid(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(7),
Q => s_axi_rid(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(8),
Q => s_axi_rid(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(9),
Q => s_axi_rid(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
O => axi_rid_temp20_in(0)
);
\GEN_RID.axi_rid_temp2[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
O => axi_rid_temp20_in(10)
);
\GEN_RID.axi_rid_temp2[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rid_temp_full,
I1 => bram_addr_ld_en,
O => p_26_out
);
\GEN_RID.axi_rid_temp2[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
O => axi_rid_temp20_in(11)
);
\GEN_RID.axi_rid_temp2[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
O => axi_rid_temp20_in(1)
);
\GEN_RID.axi_rid_temp2[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
O => axi_rid_temp20_in(2)
);
\GEN_RID.axi_rid_temp2[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
O => axi_rid_temp20_in(3)
);
\GEN_RID.axi_rid_temp2[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
O => axi_rid_temp20_in(4)
);
\GEN_RID.axi_rid_temp2[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
O => axi_rid_temp20_in(5)
);
\GEN_RID.axi_rid_temp2[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
O => axi_rid_temp20_in(6)
);
\GEN_RID.axi_rid_temp2[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
O => axi_rid_temp20_in(7)
);
\GEN_RID.axi_rid_temp2[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
O => axi_rid_temp20_in(8)
);
\GEN_RID.axi_rid_temp2[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
O => axi_rid_temp20_in(9)
);
\GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080000C8C800C0"
)
port map (
I0 => bram_addr_ld_en,
I1 => s_axi_aresetn,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full_d1,
I4 => axi_rid_temp_full,
I5 => p_4_out,
O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\,
Q => axi_rid_temp2_full,
R => '0'
);
\GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(0),
Q => axi_rid_temp2(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(10),
Q => axi_rid_temp2(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(11),
Q => axi_rid_temp2(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(1),
Q => axi_rid_temp2(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(2),
Q => axi_rid_temp2(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(3),
Q => axi_rid_temp2(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(4),
Q => axi_rid_temp2(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(5),
Q => axi_rid_temp2(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(6),
Q => axi_rid_temp2(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(7),
Q => axi_rid_temp2(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(8),
Q => axi_rid_temp2(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(9),
Q => axi_rid_temp2(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(0),
O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(10),
O => \GEN_RID.axi_rid_temp[10]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A0FFA0E0"
)
port map (
I0 => p_4_out,
I1 => axi_rid_temp_full_d1,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
O => \GEN_RID.axi_rid_temp[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(11),
O => \GEN_RID.axi_rid_temp[11]_i_2_n_0\
);
\GEN_RID.axi_rid_temp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(1),
O => \GEN_RID.axi_rid_temp[1]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(2),
O => \GEN_RID.axi_rid_temp[2]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(3),
O => \GEN_RID.axi_rid_temp[3]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(4),
O => \GEN_RID.axi_rid_temp[4]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(5),
O => \GEN_RID.axi_rid_temp[5]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(6),
O => \GEN_RID.axi_rid_temp[6]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(7),
O => \GEN_RID.axi_rid_temp[7]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(8),
O => \GEN_RID.axi_rid_temp[8]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(9),
O => \GEN_RID.axi_rid_temp[9]_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rid_temp_full,
Q => axi_rid_temp_full_d1,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E000F0A0A0"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_rid_temp_full_d1,
I2 => s_axi_aresetn,
I3 => p_4_out,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2_full,
O => \GEN_RID.axi_rid_temp_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp_full_i_1_n_0\,
Q => axi_rid_temp_full,
R => '0'
);
\GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\,
Q => axi_rid_temp(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[10]_i_1_n_0\,
Q => axi_rid_temp(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[11]_i_2_n_0\,
Q => axi_rid_temp(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[1]_i_1_n_0\,
Q => axi_rid_temp(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[2]_i_1_n_0\,
Q => axi_rid_temp(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[3]_i_1_n_0\,
Q => axi_rid_temp(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[4]_i_1_n_0\,
Q => axi_rid_temp(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[5]_i_1_n_0\,
Q => axi_rid_temp(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[6]_i_1_n_0\,
Q => axi_rid_temp(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[7]_i_1_n_0\,
Q => axi_rid_temp(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[8]_i_1_n_0\,
Q => axi_rid_temp(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[9]_i_1_n_0\,
Q => axi_rid_temp(9),
R => \^bram_rst_a\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0
port map (
D(9) => I_WRAP_BRST_n_9,
D(8) => I_WRAP_BRST_n_10,
D(7) => I_WRAP_BRST_n_11,
D(6) => I_WRAP_BRST_n_12,
D(5) => I_WRAP_BRST_n_13,
D(4) => I_WRAP_BRST_n_14,
D(3) => I_WRAP_BRST_n_15,
D(2) => I_WRAP_BRST_n_16,
D(1) => I_WRAP_BRST_n_17,
D(0) => I_WRAP_BRST_n_18,
E(0) => I_WRAP_BRST_n_6,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3 downto 0) => axi_arlen_pipe(3 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_0,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_7,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ => I_WRAP_BRST_n_8,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(9 downto 0) => \^q\(9 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_20,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0\,
Q(3 downto 0) => rd_data_sm_cs(3 downto 0),
SR(0) => \^bram_rst_a\,
ar_active => ar_active,
axi_araddr_full => axi_araddr_full,
axi_aresetn_d2 => axi_aresetn_d2,
axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2,
axi_arsize_pipe(0) => axi_arsize_pipe(1),
axi_arsize_pipe_max => axi_arsize_pipe_max,
axi_b2b_brst => axi_b2b_brst,
axi_b2b_brst_reg => I_WRAP_BRST_n_24,
axi_rd_burst => axi_rd_burst,
axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0,
axi_rvalid_int_reg => \^s_axi_rvalid\,
bram_addr_ld_en => bram_addr_ld_en,
brst_zero => brst_zero,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_wrap_burst_reg => curr_wrap_burst_reg,
disable_b2b_brst => disable_b2b_brst,
end_brst_rd => end_brst_rd,
last_bram_addr => last_bram_addr,
no_ar_ack => no_ar_ack,
pend_rd_op => pend_rd_op,
rd_addr_sm_cs => rd_addr_sm_cs,
rd_adv_buf67_out => rd_adv_buf67_out,
\rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_22,
\rd_data_sm_cs_reg[3]\ => I_WRAP_BRST_n_25,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(10 downto 0) => s_axi_araddr(10 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
\save_init_bram_addr_ld_reg[12]_0\(0) => I_WRAP_BRST_n_21,
\save_init_bram_addr_ld_reg[12]_1\ => I_WRAP_BRST_n_23,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_2,
\wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_3,
\wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_4,
\wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_5
);
act_rd_burst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002EEE22E2"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_set,
I2 => bram_addr_ld_en,
I3 => axi_rd_burst_two,
I4 => axi_rd_burst,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_i_1_n_0
);
act_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8A8A8"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I1 => act_rd_burst_i_4_n_0,
I2 => axi_b2b_brst_i_3_n_0,
I3 => \rd_data_sm_cs[2]_i_4_n_0\,
I4 => last_bram_addr_i_8_n_0,
I5 => bram_addr_ld_en,
O => act_rd_burst_set
);
act_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"02000004FFFFFFFF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => \rd_data_sm_cs[3]_i_6_n_0\,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => s_axi_aresetn,
O => act_rd_burst_i_3_n_0
);
act_rd_burst_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"4440"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
O => act_rd_burst_i_4_n_0
);
act_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_i_1_n_0,
Q => act_rd_burst,
R => '0'
);
act_rd_burst_two_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst_set,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_two_i_1_n_0
);
act_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_two_i_1_n_0,
Q => act_rd_burst_two,
R => '0'
);
axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => axi_arsize_pipe_max,
O => axi_arsize_pipe_max_i_1_n_0
);
axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_arsize_pipe_max_i_1_n_0,
Q => axi_arsize_pipe_max,
R => \^bram_rst_a\
);
axi_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC0CCC55CC0CCCCC"
)
port map (
I0 => I_WRAP_BRST_n_24,
I1 => axi_b2b_brst,
I2 => disable_b2b_brst_i_2_n_0,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => axi_b2b_brst_i_3_n_0,
O => axi_b2b_brst_i_1_n_0
);
axi_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088880080"
)
port map (
I0 => \rd_data_sm_cs[0]_i_3_n_0\,
I1 => rd_adv_buf67_out,
I2 => end_brst_rd,
I3 => axi_b2b_brst,
I4 => brst_zero,
I5 => I_WRAP_BRST_n_24,
O => axi_b2b_brst_i_3_n_0
);
axi_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_b2b_brst_i_1_n_0,
Q => axi_b2b_brst,
R => \^bram_rst_a\
);
axi_rd_burst_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"303000A0"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_i_1_n_0
);
axi_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => axi_rd_burst_i_3_n_0,
I2 => I_WRAP_BRST_n_4,
I3 => \brst_cnt[7]_i_3_n_0\,
I4 => I_WRAP_BRST_n_3,
I5 => I_WRAP_BRST_n_2,
O => axi_rd_burst_i_2_n_0
);
axi_rd_burst_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arlen(5),
I1 => axi_arlen_pipe(5),
I2 => s_axi_arlen(4),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(4),
O => axi_rd_burst_i_3_n_0
);
axi_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_i_1_n_0,
Q => axi_rd_burst,
R => '0'
);
axi_rd_burst_two_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"C0C000A0"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst_two,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_two_i_1_n_0
);
axi_rd_burst_two_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => axi_rd_burst_two
);
axi_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_two_i_1_n_0,
Q => axi_rd_burst_two_reg_n_0,
R => '0'
);
axi_rlast_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88A8"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_rlast_set,
I2 => \^s_axi_rlast\,
I3 => s_axi_rready,
O => axi_rlast_int_i_1_n_0
);
axi_rlast_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rlast_int_i_1_n_0,
Q => \^s_axi_rlast\,
R => '0'
);
axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFEEEA"
)
port map (
I0 => axi_rvalid_clr_ok,
I1 => last_bram_addr,
I2 => disable_b2b_brst,
I3 => disable_b2b_brst_cmb,
I4 => axi_rvalid_clr_ok_i_2_n_0,
I5 => axi_rvalid_clr_ok_i_3_n_0,
O => axi_rvalid_clr_ok_i_1_n_0
);
axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => axi_rvalid_clr_ok_i_2_n_0
);
axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => I_WRAP_BRST_n_23,
I1 => bram_addr_ld_en,
I2 => s_axi_aresetn,
O => axi_rvalid_clr_ok_i_3_n_0
);
axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_clr_ok_i_1_n_0,
Q => axi_rvalid_clr_ok,
R => '0'
);
axi_rvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00E0E0E0E0E0E0E0"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => axi_rvalid_set,
I2 => s_axi_aresetn,
I3 => axi_rvalid_clr_ok,
I4 => \^s_axi_rlast\,
I5 => s_axi_rready,
O => axi_rvalid_int_i_1_n_0
);
axi_rvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_int_i_1_n_0,
Q => \^s_axi_rvalid\,
R => '0'
);
axi_rvalid_set_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
O => axi_rvalid_set_cmb
);
axi_rvalid_set_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_set_cmb,
Q => axi_rvalid_set,
R => \^bram_rst_a\
);
bram_en_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEFFFEEEEE000E"
)
port map (
I0 => bram_en_int_i_2_n_0,
I1 => bram_en_int_i_3_n_0,
I2 => bram_en_int_i_4_n_0,
I3 => I_WRAP_BRST_n_25,
I4 => bram_en_int_i_6_n_0,
I5 => \^bram_en_b\,
O => bram_en_int_i_1_n_0
);
bram_en_int_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF777FFFFFFFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => act_rd_burst,
I3 => act_rd_burst_two,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_10_n_0
);
bram_en_int_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"D0D000F0D0D0F0F0"
)
port map (
I0 => \rd_data_sm_cs[3]_i_7_n_0\,
I1 => I_WRAP_BRST_n_24,
I2 => rd_data_sm_cs(1),
I3 => brst_one,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => bram_en_int_i_11_n_0
);
bram_en_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FDF50000"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(1),
I5 => bram_en_int_i_7_n_0,
O => bram_en_int_i_2_n_0
);
bram_en_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEEAFAAAAAAEE"
)
port map (
I0 => I_WRAP_BRST_n_0,
I1 => bram_addr_ld_en,
I2 => p_0_in13_in,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_3_n_0
);
bram_en_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"000F007F0000007F"
)
port map (
I0 => pend_rd_op,
I1 => rd_adv_buf67_out,
I2 => \rd_data_sm_cs[0]_i_3_n_0\,
I3 => bram_en_int_i_9_n_0,
I4 => bram_addr_ld_en,
I5 => bram_en_int_i_10_n_0,
O => bram_en_int_i_4_n_0
);
bram_en_int_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"1010111111111110"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => bram_en_int_i_11_n_0,
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_6_n_0
);
bram_en_int_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"3330131003001310"
)
port map (
I0 => \rd_data_sm_cs[2]_i_5_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => axi_rd_burst_two_reg_n_0,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_7_n_0\,
O => bram_en_int_i_7_n_0
);
bram_en_int_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111111000"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => brst_zero,
I5 => end_brst_rd,
O => bram_en_int_i_9_n_0
);
bram_en_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_int_i_1_n_0,
Q => \^bram_en_b\,
R => \^bram_rst_a\
);
\brst_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1DDD111"
)
port map (
I0 => brst_cnt(0),
I1 => bram_addr_ld_en,
I2 => axi_arlen_pipe(0),
I3 => axi_araddr_full,
I4 => s_axi_arlen(0),
O => \brst_cnt[0]_i_1_n_0\
);
\brst_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
I3 => bram_addr_ld_en,
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[1]_i_1_n_0\
);
\brst_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => bram_addr_ld_en,
I2 => brst_cnt(2),
I3 => brst_cnt(1),
I4 => brst_cnt(0),
O => \brst_cnt[2]_i_1_n_0\
);
\brst_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_3,
I1 => bram_addr_ld_en,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[3]_i_1_n_0\
);
\brst_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arlen(4),
I3 => bram_addr_ld_en,
I4 => brst_cnt(4),
I5 => \brst_cnt[4]_i_2_n_0\,
O => \brst_cnt[4]_i_1_n_0\
);
\brst_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => brst_cnt(2),
I1 => brst_cnt(0),
I2 => brst_cnt(1),
I3 => brst_cnt(3),
O => \brst_cnt[4]_i_2_n_0\
);
\brst_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => bram_addr_ld_en,
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[5]_i_1_n_0\
);
\brst_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(6),
I3 => brst_cnt(5),
I4 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[6]_i_1_n_0\
);
\brst_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arlen(6),
O => \brst_cnt[6]_i_2_n_0\
);
\brst_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_8,
O => \brst_cnt[7]_i_1_n_0\
);
\brst_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB8B8B8B8"
)
port map (
I0 => \brst_cnt[7]_i_3_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(7),
I3 => brst_cnt(6),
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[7]_i_2_n_0\
);
\brst_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arlen(7),
O => \brst_cnt[7]_i_3_n_0\
);
\brst_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => brst_cnt(3),
I1 => brst_cnt(1),
I2 => brst_cnt(0),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
O => \brst_cnt[7]_i_4_n_0\
);
brst_cnt_max_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_cnt_max,
Q => brst_cnt_max_d1,
R => \^bram_rst_a\
);
\brst_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[0]_i_1_n_0\,
Q => brst_cnt(0),
R => \^bram_rst_a\
);
\brst_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[1]_i_1_n_0\,
Q => brst_cnt(1),
R => \^bram_rst_a\
);
\brst_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[2]_i_1_n_0\,
Q => brst_cnt(2),
R => \^bram_rst_a\
);
\brst_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[3]_i_1_n_0\,
Q => brst_cnt(3),
R => \^bram_rst_a\
);
\brst_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[4]_i_1_n_0\,
Q => brst_cnt(4),
R => \^bram_rst_a\
);
\brst_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[5]_i_1_n_0\,
Q => brst_cnt(5),
R => \^bram_rst_a\
);
\brst_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[6]_i_1_n_0\,
Q => brst_cnt(6),
R => \^bram_rst_a\
);
\brst_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[7]_i_2_n_0\,
Q => brst_cnt(7),
R => \^bram_rst_a\
);
brst_one_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E0EE0000"
)
port map (
I0 => brst_one,
I1 => brst_one0,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => s_axi_aresetn,
I5 => last_bram_addr_i_7_n_0,
O => brst_one_i_1_n_0
);
brst_one_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_5,
I2 => axi_rd_burst_i_2_n_0,
I3 => brst_cnt(0),
I4 => brst_cnt(1),
I5 => last_bram_addr_i_9_n_0,
O => brst_one0
);
brst_one_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_one_i_1_n_0,
Q => brst_one,
R => '0'
);
brst_zero_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => brst_zero,
I1 => last_bram_addr_i_7_n_0,
I2 => s_axi_aresetn,
I3 => last_bram_addr_i_3_n_0,
O => brst_zero_i_1_n_0
);
brst_zero_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_zero_i_1_n_0,
Q => brst_zero,
R => '0'
);
curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arburst(0),
I1 => axi_arburst_pipe(0),
I2 => s_axi_arburst(1),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(1),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^bram_rst_a\
);
curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_arburst(1),
I1 => axi_arburst_pipe(1),
I2 => s_axi_arburst(0),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^bram_rst_a\
);
disable_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000D0000"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst_i_2_n_0,
I5 => disable_b2b_brst_i_3_n_0,
O => disable_b2b_brst_cmb
);
disable_b2b_brst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
O => disable_b2b_brst_i_2_n_0
);
disable_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FE7D0000FE7DFE7D"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst,
I5 => disable_b2b_brst_i_4_n_0,
O => disable_b2b_brst_i_3_n_0
);
disable_b2b_brst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFDFDFDFDFFF"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => brst_zero,
I4 => end_brst_rd,
I5 => brst_one,
O => disable_b2b_brst_i_4_n_0
);
disable_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => disable_b2b_brst_cmb,
Q => disable_b2b_brst,
R => \^bram_rst_a\
);
end_brst_rd_clr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFF10100000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(0),
I5 => end_brst_rd_clr,
O => end_brst_rd_clr_i_1_n_0
);
end_brst_rd_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_clr_i_1_n_0,
Q => end_brst_rd_clr,
R => \^bram_rst_a\
);
end_brst_rd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0020F020"
)
port map (
I0 => brst_cnt_max,
I1 => brst_cnt_max_d1,
I2 => s_axi_aresetn,
I3 => end_brst_rd,
I4 => end_brst_rd_clr,
O => end_brst_rd_i_1_n_0
);
end_brst_rd_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_i_1_n_0,
Q => end_brst_rd,
R => '0'
);
last_bram_addr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF57550000"
)
port map (
I0 => last_bram_addr_i_2_n_0,
I1 => last_bram_addr_i_3_n_0,
I2 => last_bram_addr_i_4_n_0,
I3 => last_bram_addr_i_5_n_0,
I4 => last_bram_addr_i_6_n_0,
I5 => last_bram_addr_i_7_n_0,
O => last_bram_addr0
);
last_bram_addr_i_10: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => brst_cnt(6),
I1 => brst_cnt(5),
O => last_bram_addr_i_10_n_0
);
last_bram_addr_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"AABFFFBFFFBFFFBF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => last_bram_addr_i_8_n_0,
I2 => bram_addr_ld_en,
I3 => rd_data_sm_cs(3),
I4 => rd_adv_buf67_out,
I5 => p_0_in13_in,
O => last_bram_addr_i_2_n_0
);
last_bram_addr_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_arlen_pipe(0),
I2 => axi_araddr_full,
I3 => s_axi_arlen(0),
I4 => axi_rd_burst_i_2_n_0,
O => last_bram_addr_i_3_n_0
);
last_bram_addr_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDFFFDFFFF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => last_bram_addr_i_4_n_0
);
last_bram_addr_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => bram_addr_ld_en,
I3 => pend_rd_op,
O => last_bram_addr_i_5_n_0
);
last_bram_addr_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"81"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
O => last_bram_addr_i_6_n_0
);
last_bram_addr_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_9_n_0,
I1 => brst_cnt(0),
I2 => brst_cnt(1),
O => last_bram_addr_i_7_n_0
);
last_bram_addr_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"02A2"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => last_bram_addr_i_8_n_0
);
last_bram_addr_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => I_WRAP_BRST_n_8,
I1 => last_bram_addr_i_10_n_0,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
I5 => brst_cnt(7),
O => last_bram_addr_i_9_n_0
);
last_bram_addr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_bram_addr0,
Q => last_bram_addr,
R => \^bram_rst_a\
);
no_ar_ack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA88C8AAAA"
)
port map (
I0 => no_ar_ack,
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_25,
O => no_ar_ack_i_1_n_0
);
no_ar_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => no_ar_ack_i_1_n_0,
Q => no_ar_ack,
R => \^bram_rst_a\
);
pend_rd_op_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFFFEAAAA0002"
)
port map (
I0 => pend_rd_op_i_2_n_0,
I1 => pend_rd_op_i_3_n_0,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
I4 => pend_rd_op_i_4_n_0,
I5 => pend_rd_op,
O => pend_rd_op_i_1_n_0
);
pend_rd_op_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFCC8C80CCCC8C8"
)
port map (
I0 => p_0_in13_in,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => pend_rd_op_i_5_n_0,
O => pend_rd_op_i_2_n_0
);
pend_rd_op_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0303070733F3FFFF"
)
port map (
I0 => p_0_in13_in,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => \^s_axi_rlast\,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => pend_rd_op_i_3_n_0
);
pend_rd_op_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBBABB00"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_data_sm_cs(0),
I2 => pend_rd_op_i_5_n_0,
I3 => bram_addr_ld_en,
I4 => pend_rd_op_i_7_n_0,
I5 => I_WRAP_BRST_n_25,
O => pend_rd_op_i_4_n_0
);
pend_rd_op_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ar_active,
I1 => end_brst_rd,
O => pend_rd_op_i_5_n_0
);
pend_rd_op_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"8000FFFF"
)
port map (
I0 => pend_rd_op,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => pend_rd_op_i_6_n_0
);
pend_rd_op_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF0008888"
)
port map (
I0 => pend_rd_op,
I1 => \^s_axi_rlast\,
I2 => ar_active,
I3 => end_brst_rd,
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(1),
O => pend_rd_op_i_7_n_0
);
pend_rd_op_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => pend_rd_op_i_1_n_0,
Q => pend_rd_op,
R => \^bram_rst_a\
);
\rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF54005555"
)
port map (
I0 => \rd_data_sm_cs[0]_i_2_n_0\,
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[0]_i_3_n_0\,
I5 => \rd_data_sm_cs[0]_i_4_n_0\,
O => \rd_data_sm_cs[0]_i_1_n_0\
);
\rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAAAAAFEAAFEAA"
)
port map (
I0 => I_WRAP_BRST_n_25,
I1 => act_rd_burst_two,
I2 => act_rd_burst,
I3 => disable_b2b_brst_i_2_n_0,
I4 => bram_addr_ld_en,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[0]_i_2_n_0\
);
\rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[0]_i_3_n_0\
);
\rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"000300BF0003008F"
)
port map (
I0 => rd_adv_buf67_out,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => p_0_in13_in,
O => \rd_data_sm_cs[0]_i_4_n_0\
);
\rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => I_WRAP_BRST_n_25,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(0),
I4 => I_WRAP_BRST_n_22,
I5 => \rd_data_sm_cs[1]_i_3_n_0\,
O => \rd_data_sm_cs[1]_i_1_n_0\
);
\rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0CCCCCC88888888"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => I_WRAP_BRST_n_24,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[1]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAABAEAFAAAB"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => \rd_data_sm_cs[2]_i_3_n_0\,
I4 => \rd_data_sm_cs[2]_i_4_n_0\,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => \rd_data_sm_cs[2]_i_1_n_0\
);
\rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000DF00000"
)
port map (
I0 => bram_addr_ld_en,
I1 => \rd_data_sm_cs[3]_i_6_n_0\,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(3),
O => \rd_data_sm_cs[2]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C0FFFF33F3BBBB"
)
port map (
I0 => axi_rd_burst,
I1 => rd_data_sm_cs(0),
I2 => rd_adv_buf67_out,
I3 => I_WRAP_BRST_n_24,
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => \rd_data_sm_cs[2]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[2]_i_4_n_0\
);
\rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
O => \rd_data_sm_cs[2]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCCCBBBB3000B888"
)
port map (
I0 => \rd_data_sm_cs[3]_i_3_n_0\,
I1 => \rd_data_sm_cs[3]_i_4_n_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => \rd_data_sm_cs[3]_i_5_n_0\,
I5 => bram_addr_ld_en,
O => rd_data_sm_ns
);
\rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004050005040"
)
port map (
I0 => I_WRAP_BRST_n_25,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => \rd_data_sm_cs[3]_i_6_n_0\,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[3]_i_2_n_0\
);
\rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF5EFFFF"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_7_n_0\,
O => \rd_data_sm_cs[3]_i_3_n_0\
);
\rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"BFAD"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_4_n_0\
);
\rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0035"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FFF"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \rd_data_sm_cs[3]_i_6_n_0\
);
\rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => brst_zero,
I1 => axi_b2b_brst,
I2 => end_brst_rd,
O => \rd_data_sm_cs[3]_i_7_n_0\
);
\rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[0]_i_1_n_0\,
Q => rd_data_sm_cs(0),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[1]_i_1_n_0\,
Q => rd_data_sm_cs(1),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[2]_i_1_n_0\,
Q => rd_data_sm_cs(2),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[3]_i_2_n_0\,
Q => rd_data_sm_cs(3),
R => \^bram_rst_a\
);
rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1110011001100110"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => s_axi_rready,
I5 => \^s_axi_rvalid\,
O => rd_skid_buf_ld_cmb
);
rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_skid_buf_ld_cmb,
Q => rd_skid_buf_ld_reg,
R => \^bram_rst_a\
);
rddata_mux_sel_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => rddata_mux_sel_cmb,
I1 => rd_data_sm_cs(3),
I2 => rddata_mux_sel_i_3_n_0,
I3 => rddata_mux_sel,
O => rddata_mux_sel_i_1_n_0
);
rddata_mux_sel_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F010F00F00F000"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
I5 => rd_adv_buf67_out,
O => rddata_mux_sel_cmb
);
rddata_mux_sel_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F700070FF70F070F"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => rddata_mux_sel_i_3_n_0
);
rddata_mux_sel_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rddata_mux_sel_i_1_n_0,
Q => rddata_mux_sel,
R => \^bram_rst_a\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_arready_int,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => axi_early_arready_int,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
port (
axi_aresetn_d2 : out STD_LOGIC;
axi_aresetn_re_reg : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
signal BID_FIFO_n_0 : STD_LOGIC;
signal BID_FIFO_n_10 : STD_LOGIC;
signal BID_FIFO_n_11 : STD_LOGIC;
signal BID_FIFO_n_12 : STD_LOGIC;
signal BID_FIFO_n_13 : STD_LOGIC;
signal BID_FIFO_n_14 : STD_LOGIC;
signal BID_FIFO_n_15 : STD_LOGIC;
signal BID_FIFO_n_3 : STD_LOGIC;
signal BID_FIFO_n_4 : STD_LOGIC;
signal BID_FIFO_n_5 : STD_LOGIC;
signal BID_FIFO_n_6 : STD_LOGIC;
signal BID_FIFO_n_7 : STD_LOGIC;
signal BID_FIFO_n_8 : STD_LOGIC;
signal BID_FIFO_n_9 : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC;
signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC;
signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_5 : STD_LOGIC;
signal I_WRAP_BRST_n_6 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal aw_active : STD_LOGIC;
signal \^axi_aresetn_d2\ : STD_LOGIC;
signal axi_aresetn_re : STD_LOGIC;
signal \^axi_aresetn_re_reg\ : STD_LOGIC;
signal axi_awaddr_full : STD_LOGIC;
signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_awid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_awlen_pipe_1_or_2 : STD_LOGIC;
signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_bvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_wdata_full_cmb : STD_LOGIC;
signal axi_wdata_full_cmb114_out : STD_LOGIC;
signal axi_wdata_full_reg : STD_LOGIC;
signal axi_wr_burst : STD_LOGIC;
signal axi_wr_burst_cmb : STD_LOGIC;
signal axi_wr_burst_cmb0 : STD_LOGIC;
signal axi_wr_burst_i_1_n_0 : STD_LOGIC;
signal axi_wr_burst_i_3_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC;
signal bid_gets_fifo_load : STD_LOGIC;
signal bid_gets_fifo_load_d1 : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal bram_addr_inc : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 10 to 10 );
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal bram_addr_rst_cmb : STD_LOGIC;
signal bram_en_cmb : STD_LOGIC;
signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal bvalid_cnt_inc : STD_LOGIC;
signal bvalid_cnt_inc11_out : STD_LOGIC;
signal clr_bram_we : STD_LOGIC;
signal clr_bram_we_cmb : STD_LOGIC;
signal curr_awlen_reg_1_or_2 : STD_LOGIC;
signal curr_awlen_reg_1_or_20 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_3_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal delay_aw_active_clr : STD_LOGIC;
signal last_data_ack_mod : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_addr_sm_cs : STD_LOGIC;
signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of wr_data_sm_cs : signal is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair63";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair61";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair60";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair60";
begin
\GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\;
axi_aresetn_d2 <= \^axi_aresetn_d2\;
axi_aresetn_re_reg <= \^axi_aresetn_re_reg\;
bram_addr_a(10 downto 0) <= \^bram_addr_a\(10 downto 0);
s_axi_awready <= \^s_axi_awready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_wready <= \^s_axi_wready\;
BID_FIFO: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO
port map (
D(11) => BID_FIFO_n_4,
D(10) => BID_FIFO_n_5,
D(9) => BID_FIFO_n_6,
D(8) => BID_FIFO_n_7,
D(7) => BID_FIFO_n_8,
D(6) => BID_FIFO_n_9,
D(5) => BID_FIFO_n_10,
D(4) => BID_FIFO_n_11,
D(3) => BID_FIFO_n_12,
D(2) => BID_FIFO_n_13,
D(1) => BID_FIFO_n_14,
D(0) => BID_FIFO_n_15,
E(0) => BID_FIFO_n_0,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
Q(11 downto 0) => axi_awid_pipe(11 downto 0),
SR(0) => SR(0),
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_bvalid_int_reg => \^s_axi_bvalid\,
axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out,
axi_wr_burst => axi_wr_burst,
bid_gets_fifo_load => bid_gets_fifo_load,
bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1,
bid_gets_fifo_load_d1_reg => BID_FIFO_n_3,
bram_addr_ld_en => bram_addr_ld_en,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
bvalid_cnt_inc => bvalid_cnt_inc,
\bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0,
\bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_17,
\bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_16,
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_addr_sm_cs => wr_addr_sm_cs
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(0),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05051F1A"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => axi_wr_burst_cmb0,
I2 => wr_data_sm_cs(0),
I3 => axi_wdata_full_cmb114_out,
I4 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => I_WRAP_BRST_n_18,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
O => axi_wr_burst_cmb0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(1),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000554000555540"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => s_axi_wlast,
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(2),
I5 => axi_wr_burst,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44010001"
)
port map (
I0 => wr_data_sm_cs(2),
I1 => wr_data_sm_cs(1),
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7774777774744444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(0),
I5 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\,
Q => wr_data_sm_cs(0),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\,
Q => wr_data_sm_cs(1),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\,
Q => wr_data_sm_cs(2),
R => SR(0)
);
\GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_aresetn,
Q => \I_RD_CHNL/axi_aresetn_d1\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \I_RD_CHNL/axi_aresetn_d1\,
Q => \^axi_aresetn_d2\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_aresetn,
I1 => \I_RD_CHNL/axi_aresetn_d1\,
O => axi_aresetn_re
);
\GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_aresetn_re,
Q => \^axi_aresetn_re_reg\,
R => '0'
);
\GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBFFFFFAA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => bram_addr_ld_en,
I4 => \^axi_aresetn_re_reg\,
I5 => \^s_axi_awready\,
O => \GEN_AWREADY.axi_awready_int_i_1_n_0\
);
\GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5444444400000000"
)
port map (
I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\,
I1 => aw_active,
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => s_axi_awvalid,
O => \GEN_AWREADY.axi_awready_int_i_2_n_0\
);
\GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABABABABABABA"
)
port map (
I0 => wr_addr_sm_cs,
I1 => I_WRAP_BRST_n_18,
I2 => last_data_ack_mod,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \GEN_AWREADY.axi_awready_int_i_3_n_0\
);
\GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AWREADY.axi_awready_int_i_1_n_0\,
Q => \^s_axi_awready\,
R => SR(0)
);
\GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi_aresetn_d2\,
O => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFF0000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => wr_data_sm_cs(2),
I3 => delay_aw_active_clr,
I4 => bram_addr_ld_en,
I5 => aw_active,
O => \GEN_AW_DUAL.aw_active_i_2_n_0\
);
\GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.aw_active_i_2_n_0\,
Q => aw_active,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => p_18_out
);
\GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_18_out,
Q => last_data_ack_mod,
R => SR(0)
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000100000"
)
port map (
I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\,
I1 => wr_addr_sm_cs,
I2 => s_axi_awvalid,
I3 => axi_awaddr_full,
I4 => I_WRAP_BRST_n_17,
I5 => aw_active,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => I_WRAP_BRST_n_17,
I1 => last_data_ack_mod,
I2 => axi_awaddr_full,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => axi_awlen_pipe_1_or_2,
I5 => curr_awlen_reg_1_or_2,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\,
Q => wr_addr_sm_cs,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(8),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(9),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(10),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(0),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(1),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(2),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(3),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(4),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(5),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(6),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(7),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000EA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => s_axi_aresetn,
I4 => bram_addr_ld_en,
O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\,
Q => axi_awaddr_full,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00BF00BF00FF40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(0),
Q => axi_awburst_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(1),
Q => axi_awburst_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(0),
Q => axi_awid_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(10),
Q => axi_awid_pipe(10),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(11),
Q => axi_awid_pipe(11),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(1),
Q => axi_awid_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(2),
Q => axi_awid_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(3),
Q => axi_awid_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(4),
Q => axi_awid_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(5),
Q => axi_awid_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(6),
Q => axi_awid_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(7),
Q => axi_awid_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(8),
Q => axi_awid_pipe(8),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(9),
Q => axi_awid_pipe(9),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(1),
O => p_9_out
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awlen(4),
I1 => s_axi_awlen(6),
I2 => s_axi_awlen(7),
I3 => s_axi_awlen(5),
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => p_9_out,
Q => axi_awlen_pipe_1_or_2,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(0),
Q => axi_awlen_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(1),
Q => axi_awlen_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(2),
Q => axi_awlen_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(3),
Q => axi_awlen_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(4),
Q => axi_awlen_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(5),
Q => axi_awlen_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(6),
Q => axi_awlen_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(7),
Q => axi_awlen_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => '1',
Q => axi_awsize_pipe(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
I5 => \^bram_addr_a\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => s_axi_wvalid,
O => bram_addr_inc
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => wr_data_sm_cs(1),
O => bram_addr_rst_cmb
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WRAP_BRST_n_14,
I3 => \^bram_addr_a\(5),
I4 => \^bram_addr_a\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => \^bram_addr_a\(10),
I1 => bram_addr_ld_en_mod,
I2 => bram_addr_ld(10),
I3 => I_WRAP_BRST_n_0,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_4,
Q => \^bram_addr_a\(8),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_3,
Q => \^bram_addr_a\(9),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\,
Q => \^bram_addr_a\(10),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_12,
Q => \^bram_addr_a\(0),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_11,
Q => \^bram_addr_a\(1),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_10,
Q => \^bram_addr_a\(2),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_9,
Q => \^bram_addr_a\(3),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_8,
Q => \^bram_addr_a\(4),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_7,
Q => \^bram_addr_a\(5),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_6,
Q => \^bram_addr_a\(6),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_5,
Q => \^bram_addr_a\(7),
R => I_WRAP_BRST_n_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"15FF1500"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
O => axi_wdata_full_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wdata_full_cmb,
Q => axi_wdata_full_reg,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4777477444444444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => s_axi_wvalid,
O => bram_en_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_cmb,
Q => bram_en_a,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000101110"
)
port map (
I0 => wr_data_sm_cs(0),
I1 => wr_data_sm_cs(1),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I5 => axi_wr_burst,
O => clr_bram_we_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => clr_bram_we_cmb,
Q => clr_bram_we,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAFEFF02AA0200"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\,
I1 => axi_wr_burst,
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\,
I5 => delay_aw_active_clr,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222E"
)
port map (
I0 => s_axi_wlast,
I1 => wr_data_sm_cs(2),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(1),
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B338B0088008800"
)
port map (
I0 => delay_aw_active_clr,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => bvalid_cnt_inc11_out,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_wlast,
O => bvalid_cnt_inc11_out
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\,
Q => delay_aw_active_clr,
R => SR(0)
);
\GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(0),
Q => bram_wrdata_a(0),
R => '0'
);
\GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(10),
Q => bram_wrdata_a(10),
R => '0'
);
\GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(11),
Q => bram_wrdata_a(11),
R => '0'
);
\GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(12),
Q => bram_wrdata_a(12),
R => '0'
);
\GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(13),
Q => bram_wrdata_a(13),
R => '0'
);
\GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(14),
Q => bram_wrdata_a(14),
R => '0'
);
\GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(15),
Q => bram_wrdata_a(15),
R => '0'
);
\GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(16),
Q => bram_wrdata_a(16),
R => '0'
);
\GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(17),
Q => bram_wrdata_a(17),
R => '0'
);
\GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(18),
Q => bram_wrdata_a(18),
R => '0'
);
\GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(19),
Q => bram_wrdata_a(19),
R => '0'
);
\GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(1),
Q => bram_wrdata_a(1),
R => '0'
);
\GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(20),
Q => bram_wrdata_a(20),
R => '0'
);
\GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(21),
Q => bram_wrdata_a(21),
R => '0'
);
\GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(22),
Q => bram_wrdata_a(22),
R => '0'
);
\GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(23),
Q => bram_wrdata_a(23),
R => '0'
);
\GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(24),
Q => bram_wrdata_a(24),
R => '0'
);
\GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(25),
Q => bram_wrdata_a(25),
R => '0'
);
\GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(26),
Q => bram_wrdata_a(26),
R => '0'
);
\GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(27),
Q => bram_wrdata_a(27),
R => '0'
);
\GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(28),
Q => bram_wrdata_a(28),
R => '0'
);
\GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(29),
Q => bram_wrdata_a(29),
R => '0'
);
\GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(2),
Q => bram_wrdata_a(2),
R => '0'
);
\GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(30),
Q => bram_wrdata_a(30),
R => '0'
);
\GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(31),
Q => bram_wrdata_a(31),
R => '0'
);
\GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(3),
Q => bram_wrdata_a(3),
R => '0'
);
\GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(4),
Q => bram_wrdata_a(4),
R => '0'
);
\GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(5),
Q => bram_wrdata_a(5),
R => '0'
);
\GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(6),
Q => bram_wrdata_a(6),
R => '0'
);
\GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(7),
Q => bram_wrdata_a(7),
R => '0'
);
\GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(8),
Q => bram_wrdata_a(8),
R => '0'
);
\GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(9),
Q => bram_wrdata_a(9),
R => '0'
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D0FF"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => clr_bram_we,
I3 => s_axi_aresetn,
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(0),
Q => bram_we_a(0),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(1),
Q => bram_we_a(1),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(2),
Q => bram_we_a(2),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(3),
Q => bram_we_a(3),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst
port map (
D(9) => I_WRAP_BRST_n_3,
D(8) => I_WRAP_BRST_n_4,
D(7) => I_WRAP_BRST_n_5,
D(6) => I_WRAP_BRST_n_6,
D(5) => I_WRAP_BRST_n_7,
D(4) => I_WRAP_BRST_n_8,
D(3) => I_WRAP_BRST_n_9,
D(2) => I_WRAP_BRST_n_10,
D(1) => I_WRAP_BRST_n_11,
D(0) => I_WRAP_BRST_n_12,
E(0) => I_WRAP_BRST_n_2,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_0,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_14,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0\,
Q(3 downto 0) => axi_awlen_pipe(3 downto 0),
SR(0) => SR(0),
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_awsize_pipe(0) => axi_awsize_pipe(1),
bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0),
bram_addr_inc => bram_addr_inc,
bram_addr_ld_en => bram_addr_ld_en,
bram_addr_ld_en_mod => bram_addr_ld_en_mod,
bram_addr_rst_cmb => bram_addr_rst_cmb,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
curr_fixed_burst => curr_fixed_burst,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_fixed_burst_reg_reg => I_WRAP_BRST_n_19,
curr_wrap_burst => curr_wrap_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
curr_wrap_burst_reg_reg => I_WRAP_BRST_n_20,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(10 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld_reg[12]_0\(0) => bram_addr_ld(10),
\save_init_bram_addr_ld_reg[12]_1\ => I_WRAP_BRST_n_16,
\save_init_bram_addr_ld_reg[12]_2\ => I_WRAP_BRST_n_17,
\save_init_bram_addr_ld_reg[12]_3\ => I_WRAP_BRST_n_18,
wr_addr_sm_cs => wr_addr_sm_cs
);
\axi_bid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_15,
Q => s_axi_bid(0),
R => SR(0)
);
\axi_bid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_5,
Q => s_axi_bid(10),
R => SR(0)
);
\axi_bid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_4,
Q => s_axi_bid(11),
R => SR(0)
);
\axi_bid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_14,
Q => s_axi_bid(1),
R => SR(0)
);
\axi_bid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_13,
Q => s_axi_bid(2),
R => SR(0)
);
\axi_bid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_12,
Q => s_axi_bid(3),
R => SR(0)
);
\axi_bid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_11,
Q => s_axi_bid(4),
R => SR(0)
);
\axi_bid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_10,
Q => s_axi_bid(5),
R => SR(0)
);
\axi_bid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_9,
Q => s_axi_bid(6),
R => SR(0)
);
\axi_bid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_8,
Q => s_axi_bid(7),
R => SR(0)
);
\axi_bid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_7,
Q => s_axi_bid(8),
R => SR(0)
);
\axi_bid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_6,
Q => s_axi_bid(9),
R => SR(0)
);
axi_bvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAA8A88"
)
port map (
I0 => s_axi_aresetn,
I1 => bvalid_cnt_inc,
I2 => BID_FIFO_n_3,
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => bvalid_cnt(1),
O => axi_bvalid_int_i_1_n_0
);
axi_bvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_bvalid_int_i_1_n_0,
Q => \^s_axi_bvalid\,
R => '0'
);
axi_wr_burst_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_wr_burst_cmb,
I1 => axi_wr_burst_i_3_n_0,
I2 => axi_wr_burst,
O => axi_wr_burst_i_1_n_0
);
axi_wr_burst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"3088FCBB"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wlast,
O => axi_wr_burst_cmb
);
axi_wr_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAA222"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(0),
I2 => axi_wr_burst_cmb0,
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(1),
I5 => wr_data_sm_cs(2),
O => axi_wr_burst_i_3_n_0
);
axi_wr_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wr_burst_i_1_n_0,
Q => axi_wr_burst,
R => SR(0)
);
axi_wready_int_mod_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EA00EAFF00000000"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
I5 => s_axi_aresetn,
O => axi_wready_int_mod_i_1_n_0
);
axi_wready_int_mod_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"F8F9F0F0"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => axi_wdata_full_reg,
I3 => axi_wdata_full_cmb114_out,
I4 => s_axi_wvalid,
O => axi_wready_int_mod_i_3_n_0
);
axi_wready_int_mod_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wready_int_mod_i_1_n_0,
Q => \^s_axi_wready\,
R => '0'
);
bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
O => bid_gets_fifo_load_d1_i_2_n_0
);
bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bid_gets_fifo_load,
Q => bid_gets_fifo_load_d1,
R => SR(0)
);
\bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"95956A6A95956AAA"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[0]_i_1_n_0\
);
\bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5BFBF2A2A4000"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[1]_i_1_n_0\
);
\bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D52AFF00FF00BF00"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[2]_i_1_n_0\
);
\bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[0]_i_1_n_0\,
Q => bvalid_cnt(0),
R => SR(0)
);
\bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[1]_i_1_n_0\,
Q => bvalid_cnt(1),
R => SR(0)
);
\bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[2]_i_1_n_0\,
Q => bvalid_cnt(2),
R => SR(0)
);
curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"5000303050003000"
)
port map (
I0 => axi_awlen_pipe(3),
I1 => s_axi_awlen(3),
I2 => curr_awlen_reg_1_or_2_i_2_n_0,
I3 => curr_awlen_reg_1_or_2_i_3_n_0,
I4 => axi_awaddr_full,
I5 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
O => curr_awlen_reg_1_or_20
);
curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awlen(2),
I1 => axi_awlen_pipe(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => axi_awlen_pipe(1),
O => curr_awlen_reg_1_or_2_i_2_n_0
);
curr_awlen_reg_1_or_2_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => axi_awlen_pipe(4),
I1 => axi_awlen_pipe(7),
I2 => axi_awlen_pipe(6),
I3 => axi_awaddr_full,
I4 => axi_awlen_pipe(5),
O => curr_awlen_reg_1_or_2_i_3_n_0
);
curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_awlen_reg_1_or_20,
Q => curr_awlen_reg_1_or_2,
R => SR(0)
);
curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_19,
Q => curr_fixed_burst_reg,
R => '0'
);
curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_20,
Q => curr_wrap_burst_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
signal I_WR_CHNL_n_36 : STD_LOGIC;
signal axi_aresetn_d2 : STD_LOGIC;
signal axi_aresetn_re_reg : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
begin
bram_rst_a <= \^bram_rst_a\;
I_RD_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36,
Q(9 downto 0) => bram_addr_b(9 downto 0),
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_b(0) => bram_addr_b(10),
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(10 downto 0) => s_axi_araddr(10 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
I_WR_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl
port map (
\GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36,
SR(0) => \^bram_rst_a\,
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_a(10 downto 0) => bram_addr_a(10 downto 0),
bram_en_a => bram_en_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(10 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
begin
\GEN_AXI4.I_FULL_AXI\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi
port map (
bram_addr_a(10 downto 0) => bram_addr_a(10 downto 0),
bram_addr_b(10 downto 0) => bram_addr_b(10 downto 0),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(10 downto 0) => s_axi_araddr(10 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(10 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ecc_interrupt : out STD_LOGIC;
ecc_ue : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_ctrl_awvalid : in STD_LOGIC;
s_axi_ctrl_awready : out STD_LOGIC;
s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wvalid : in STD_LOGIC;
s_axi_ctrl_wready : out STD_LOGIC;
s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_bvalid : out STD_LOGIC;
s_axi_ctrl_bready : in STD_LOGIC;
s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_arvalid : in STD_LOGIC;
s_axi_ctrl_arready : out STD_LOGIC;
s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_rvalid : out STD_LOGIC;
s_axi_ctrl_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 11;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 2048;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 13;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
signal \<const0>\ : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 12 downto 2 );
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 12 downto 2 );
signal \^bram_rst_a\ : STD_LOGIC;
signal \^s_axi_aclk\ : STD_LOGIC;
begin
\^s_axi_aclk\ <= s_axi_aclk;
bram_addr_a(12 downto 2) <= \^bram_addr_a\(12 downto 2);
bram_addr_a(1) <= \<const0>\;
bram_addr_a(0) <= \<const0>\;
bram_addr_b(12 downto 2) <= \^bram_addr_b\(12 downto 2);
bram_addr_b(1) <= \<const0>\;
bram_addr_b(0) <= \<const0>\;
bram_clk_a <= \^s_axi_aclk\;
bram_clk_b <= \^s_axi_aclk\;
bram_rst_a <= \^bram_rst_a\;
bram_rst_b <= \^bram_rst_a\;
bram_we_b(3) <= \<const0>\;
bram_we_b(2) <= \<const0>\;
bram_we_b(1) <= \<const0>\;
bram_we_b(0) <= \<const0>\;
bram_wrdata_b(31) <= \<const0>\;
bram_wrdata_b(30) <= \<const0>\;
bram_wrdata_b(29) <= \<const0>\;
bram_wrdata_b(28) <= \<const0>\;
bram_wrdata_b(27) <= \<const0>\;
bram_wrdata_b(26) <= \<const0>\;
bram_wrdata_b(25) <= \<const0>\;
bram_wrdata_b(24) <= \<const0>\;
bram_wrdata_b(23) <= \<const0>\;
bram_wrdata_b(22) <= \<const0>\;
bram_wrdata_b(21) <= \<const0>\;
bram_wrdata_b(20) <= \<const0>\;
bram_wrdata_b(19) <= \<const0>\;
bram_wrdata_b(18) <= \<const0>\;
bram_wrdata_b(17) <= \<const0>\;
bram_wrdata_b(16) <= \<const0>\;
bram_wrdata_b(15) <= \<const0>\;
bram_wrdata_b(14) <= \<const0>\;
bram_wrdata_b(13) <= \<const0>\;
bram_wrdata_b(12) <= \<const0>\;
bram_wrdata_b(11) <= \<const0>\;
bram_wrdata_b(10) <= \<const0>\;
bram_wrdata_b(9) <= \<const0>\;
bram_wrdata_b(8) <= \<const0>\;
bram_wrdata_b(7) <= \<const0>\;
bram_wrdata_b(6) <= \<const0>\;
bram_wrdata_b(5) <= \<const0>\;
bram_wrdata_b(4) <= \<const0>\;
bram_wrdata_b(3) <= \<const0>\;
bram_wrdata_b(2) <= \<const0>\;
bram_wrdata_b(1) <= \<const0>\;
bram_wrdata_b(0) <= \<const0>\;
ecc_interrupt <= \<const0>\;
ecc_ue <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_ctrl_arready <= \<const0>\;
s_axi_ctrl_awready <= \<const0>\;
s_axi_ctrl_bresp(1) <= \<const0>\;
s_axi_ctrl_bresp(0) <= \<const0>\;
s_axi_ctrl_bvalid <= \<const0>\;
s_axi_ctrl_rdata(31) <= \<const0>\;
s_axi_ctrl_rdata(30) <= \<const0>\;
s_axi_ctrl_rdata(29) <= \<const0>\;
s_axi_ctrl_rdata(28) <= \<const0>\;
s_axi_ctrl_rdata(27) <= \<const0>\;
s_axi_ctrl_rdata(26) <= \<const0>\;
s_axi_ctrl_rdata(25) <= \<const0>\;
s_axi_ctrl_rdata(24) <= \<const0>\;
s_axi_ctrl_rdata(23) <= \<const0>\;
s_axi_ctrl_rdata(22) <= \<const0>\;
s_axi_ctrl_rdata(21) <= \<const0>\;
s_axi_ctrl_rdata(20) <= \<const0>\;
s_axi_ctrl_rdata(19) <= \<const0>\;
s_axi_ctrl_rdata(18) <= \<const0>\;
s_axi_ctrl_rdata(17) <= \<const0>\;
s_axi_ctrl_rdata(16) <= \<const0>\;
s_axi_ctrl_rdata(15) <= \<const0>\;
s_axi_ctrl_rdata(14) <= \<const0>\;
s_axi_ctrl_rdata(13) <= \<const0>\;
s_axi_ctrl_rdata(12) <= \<const0>\;
s_axi_ctrl_rdata(11) <= \<const0>\;
s_axi_ctrl_rdata(10) <= \<const0>\;
s_axi_ctrl_rdata(9) <= \<const0>\;
s_axi_ctrl_rdata(8) <= \<const0>\;
s_axi_ctrl_rdata(7) <= \<const0>\;
s_axi_ctrl_rdata(6) <= \<const0>\;
s_axi_ctrl_rdata(5) <= \<const0>\;
s_axi_ctrl_rdata(4) <= \<const0>\;
s_axi_ctrl_rdata(3) <= \<const0>\;
s_axi_ctrl_rdata(2) <= \<const0>\;
s_axi_ctrl_rdata(1) <= \<const0>\;
s_axi_ctrl_rdata(0) <= \<const0>\;
s_axi_ctrl_rresp(1) <= \<const0>\;
s_axi_ctrl_rresp(0) <= \<const0>\;
s_axi_ctrl_rvalid <= \<const0>\;
s_axi_ctrl_wready <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gext_inst.abcv4_0_ext_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top
port map (
bram_addr_a(10 downto 0) => \^bram_addr_a\(12 downto 2),
bram_addr_b(10 downto 0) => \^bram_addr_b\(12 downto 2),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => \^s_axi_aclk\,
s_axi_araddr(10 downto 0) => s_axi_araddr(12 downto 2),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(12 downto 2),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_bram_ctrl,Vivado 2017.2.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of U0 : label is 11;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of U0 : label is 2048;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 13;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl
port map (
bram_addr_a(12 downto 0) => bram_addr_a(12 downto 0),
bram_addr_b(12 downto 0) => bram_addr_b(12 downto 0),
bram_clk_a => bram_clk_a,
bram_clk_b => bram_clk_b,
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_rst_b => bram_rst_b,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_we_b(3 downto 0) => bram_we_b(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0),
ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED,
ecc_ue => NLW_U0_ecc_ue_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(12 downto 0) => s_axi_araddr(12 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock => s_axi_arlock,
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(12 downto 0) => s_axi_awaddr(12 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock => s_axi_awlock,
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED,
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED,
s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0),
s_axi_ctrl_rready => '0',
s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED,
s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED,
s_axi_ctrl_wvalid => '0',
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
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-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 24 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 96,
C_DOUT_WIDTH => 96,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 96,
C_DIN_WIDTH => 96,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 96,
C_DIN_WIDTH => 96,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_fwft_96x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: toplevel_synthesis.vhd
-- /___/ /\ Timestamp: Sun Mar 27 23:04:04 2016
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -tm toplevel -w -dir netgen/synthesis -ofmt vhdl -sim toplevel.ngc toplevel_synthesis.vhd
-- Device : xc6slx9-2-tqg144
-- Input file : toplevel.ngc
-- Output file : /home/chris/Documents/tek7854mpu/debugger/debug_hdl/netgen/synthesis/toplevel_synthesis.vhd
-- # of Entities : 1
-- Design Name : toplevel
-- Xilinx : /opt/Xilinx/14.7/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity toplevel is
port (
clk : in STD_LOGIC := 'X';
mojo_tx : out STD_LOGIC;
idpromnut_tx : out STD_LOGIC;
led0 : out STD_LOGIC;
led1 : out STD_LOGIC;
led2 : out STD_LOGIC;
led3 : out STD_LOGIC;
led4 : out STD_LOGIC;
led5 : out STD_LOGIC;
led6 : out STD_LOGIC;
led7 : out STD_LOGIC
);
end toplevel;
architecture Structure of toplevel is
signal clk_BUFGP_0 : STD_LOGIC;
signal transmitter_tx_out_1 : STD_LOGIC;
signal transmitter_ready_2 : STD_LOGIC;
signal ser_ready_last_3 : STD_LOGIC;
signal ser_ready_ser_ready_last_AND_7_o : STD_LOGIC;
signal Q_n0018 : STD_LOGIC;
signal N0 : STD_LOGIC;
signal Mram_n0015_7_0_Q : STD_LOGIC;
signal Mram_n0015_7_0_1 : STD_LOGIC;
signal Mram_n0015_7_0_2 : STD_LOGIC;
signal Mram_n0015_7_0_3 : STD_LOGIC;
signal Mram_n0015_7_0_4 : STD_LOGIC;
signal Mram_n0015_7_0_5 : STD_LOGIC;
signal Mram_n0015_7_0_6 : STD_LOGIC;
signal Mram_n0015_7_0_7 : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o_30_1_108 : STD_LOGIC;
signal transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_1 : STD_LOGIC;
signal transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_Q_142 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_Q_143 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_Q_144 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_Q_145 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_Q_146 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_Q_147 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_Q_148 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_Q_149 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_Q_150 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_Q_151 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_Q_152 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_Q_153 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_Q_154 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_Q_155 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_Q_156 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_Q_157 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_Q_158 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_Q_159 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_Q_160 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_Q_161 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_Q_162 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_Q_163 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_Q_164 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_Q_165 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_Q_166 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_Q_167 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_Q_168 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_Q_169 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_Q_170 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_0_Q_171 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_lut_0_Q : STD_LOGIC;
signal transmitter_state_FSM_FFd2_204 : STD_LOGIC;
signal transmitter_state_FSM_FFd1_In : STD_LOGIC;
signal transmitter_state_FSM_FFd2_In : STD_LOGIC;
signal transmitter_n0071_inv : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_4_o : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o : STD_LOGIC;
signal transmitter_state_1_PWR_5_o_Mux_20_o : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_0_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_1_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_2_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_3_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_4_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_5_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_6_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_7_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_8_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_9_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_10_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_11_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_12_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_13_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_14_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_15_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_16_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_17_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_18_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_19_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_20_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_21_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_22_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_23_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_24_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_25_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_26_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_27_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_28_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_29_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_30_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_0_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_1_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_2_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_3_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_4_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_5_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_6_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_7_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_8_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_9_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_10_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_11_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_12_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_13_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_14_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_15_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_16_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_17_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_18_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_19_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_20_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_21_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_22_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_23_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_24_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_25_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_26_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_27_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_28_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_29_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_30_Q : STD_LOGIC;
signal transmitter_baud_clk_edge_342 : STD_LOGIC;
signal transmitter_state_1_GND_5_o_Mux_21_o : STD_LOGIC;
signal transmitter_state_FSM_FFd1_344 : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_0_Q : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_1_Q : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_2_Q : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_3_Q : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_4_Q : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_5_Q : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_6_Q : STD_LOGIC;
signal Q_n00181_352 : STD_LOGIC;
signal Q_n00182_353 : STD_LOGIC;
signal Q_n00183_354 : STD_LOGIC;
signal Q_n00184_355 : STD_LOGIC;
signal Q_n00185_356 : STD_LOGIC;
signal Q_n00186_357 : STD_LOGIC;
signal N3 : STD_LOGIC;
signal N5 : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o_30_11_360 : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o_30_12_361 : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o_30_13_362 : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o_30_14_363 : STD_LOGIC;
signal transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_11_364 : STD_LOGIC;
signal transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_12_365 : STD_LOGIC;
signal transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_13_366 : STD_LOGIC;
signal transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_14_367 : STD_LOGIC;
signal transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_15_368 : STD_LOGIC;
signal Mcount_rom_addr_cy_1_rt_380 : STD_LOGIC;
signal Mcount_rom_addr_cy_2_rt_381 : STD_LOGIC;
signal Mcount_rom_addr_cy_3_rt_382 : STD_LOGIC;
signal Mcount_rom_addr_cy_4_rt_383 : STD_LOGIC;
signal Mcount_rom_addr_cy_5_rt_384 : STD_LOGIC;
signal Mcount_rom_addr_cy_6_rt_385 : STD_LOGIC;
signal Mcount_rom_addr_cy_7_rt_386 : STD_LOGIC;
signal Mcount_rom_addr_cy_8_rt_387 : STD_LOGIC;
signal Mcount_rom_addr_cy_9_rt_388 : STD_LOGIC;
signal Mcount_rom_addr_cy_10_rt_389 : STD_LOGIC;
signal Mcount_rom_addr_cy_11_rt_390 : STD_LOGIC;
signal Mcount_rom_addr_cy_12_rt_391 : STD_LOGIC;
signal Mcount_rom_addr_cy_13_rt_392 : STD_LOGIC;
signal Mcount_rom_addr_cy_14_rt_393 : STD_LOGIC;
signal Mcount_rom_addr_cy_15_rt_394 : STD_LOGIC;
signal Mcount_rom_addr_cy_16_rt_395 : STD_LOGIC;
signal Mcount_rom_addr_cy_17_rt_396 : STD_LOGIC;
signal Mcount_rom_addr_cy_18_rt_397 : STD_LOGIC;
signal Mcount_rom_addr_cy_19_rt_398 : STD_LOGIC;
signal Mcount_rom_addr_cy_20_rt_399 : STD_LOGIC;
signal Mcount_rom_addr_cy_21_rt_400 : STD_LOGIC;
signal Mcount_rom_addr_cy_22_rt_401 : STD_LOGIC;
signal Mcount_rom_addr_cy_23_rt_402 : STD_LOGIC;
signal Mcount_rom_addr_cy_24_rt_403 : STD_LOGIC;
signal Mcount_rom_addr_cy_25_rt_404 : STD_LOGIC;
signal Mcount_rom_addr_cy_26_rt_405 : STD_LOGIC;
signal Mcount_rom_addr_cy_27_rt_406 : STD_LOGIC;
signal Mcount_rom_addr_cy_28_rt_407 : STD_LOGIC;
signal Mcount_rom_addr_cy_29_rt_408 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_29_rt_409 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_28_rt_410 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_27_rt_411 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_26_rt_412 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_25_rt_413 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_24_rt_414 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_23_rt_415 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_22_rt_416 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_21_rt_417 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_20_rt_418 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_19_rt_419 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_18_rt_420 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_17_rt_421 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_16_rt_422 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_15_rt_423 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_14_rt_424 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_13_rt_425 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_12_rt_426 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_11_rt_427 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_10_rt_428 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_9_rt_429 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_8_rt_430 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_7_rt_431 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_6_rt_432 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_5_rt_433 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_4_rt_434 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_3_rt_435 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_2_rt_436 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_1_rt_437 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_rt_438 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_rt_439 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_rt_440 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_rt_441 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_rt_442 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_rt_443 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_rt_444 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_rt_445 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_rt_446 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_rt_447 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_rt_448 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_rt_449 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_rt_450 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_rt_451 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_rt_452 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_rt_453 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_rt_454 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_rt_455 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_rt_456 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_rt_457 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_rt_458 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_rt_459 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_rt_460 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_rt_461 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_rt_462 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_rt_463 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_rt_464 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_rt_465 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_rt_466 : STD_LOGIC;
signal Mcount_rom_addr_xor_30_rt_467 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_xor_30_rt_468 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_30_rt_469 : STD_LOGIC;
signal N7 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal transmitter_baud_divider_30_rstpot_473 : STD_LOGIC;
signal transmitter_baud_divider_29_rstpot_474 : STD_LOGIC;
signal transmitter_baud_divider_28_rstpot_475 : STD_LOGIC;
signal transmitter_baud_divider_27_rstpot_476 : STD_LOGIC;
signal transmitter_baud_divider_26_rstpot_477 : STD_LOGIC;
signal transmitter_baud_divider_25_rstpot_478 : STD_LOGIC;
signal transmitter_baud_divider_24_rstpot_479 : STD_LOGIC;
signal transmitter_baud_divider_23_rstpot_480 : STD_LOGIC;
signal transmitter_baud_divider_22_rstpot_481 : STD_LOGIC;
signal transmitter_baud_divider_21_rstpot_482 : STD_LOGIC;
signal transmitter_baud_divider_20_rstpot_483 : STD_LOGIC;
signal transmitter_baud_divider_19_rstpot_484 : STD_LOGIC;
signal transmitter_baud_divider_18_rstpot_485 : STD_LOGIC;
signal transmitter_baud_divider_17_rstpot_486 : STD_LOGIC;
signal transmitter_baud_divider_16_rstpot_487 : STD_LOGIC;
signal transmitter_baud_divider_15_rstpot_488 : STD_LOGIC;
signal transmitter_baud_divider_14_rstpot_489 : STD_LOGIC;
signal transmitter_baud_divider_13_rstpot_490 : STD_LOGIC;
signal transmitter_baud_divider_12_rstpot_491 : STD_LOGIC;
signal transmitter_baud_divider_11_rstpot_492 : STD_LOGIC;
signal transmitter_baud_divider_10_rstpot_493 : STD_LOGIC;
signal transmitter_baud_divider_9_rstpot_494 : STD_LOGIC;
signal transmitter_baud_divider_8_rstpot_495 : STD_LOGIC;
signal transmitter_baud_divider_7_rstpot_496 : STD_LOGIC;
signal transmitter_baud_divider_6_rstpot_497 : STD_LOGIC;
signal transmitter_baud_divider_5_rstpot_498 : STD_LOGIC;
signal transmitter_baud_divider_4_rstpot_499 : STD_LOGIC;
signal transmitter_baud_divider_3_rstpot_500 : STD_LOGIC;
signal transmitter_baud_divider_2_rstpot_501 : STD_LOGIC;
signal transmitter_baud_divider_1_rstpot_502 : STD_LOGIC;
signal transmitter_baud_divider_0_rstpot_503 : STD_LOGIC;
signal transmitter_baud_clk_edge_1_504 : STD_LOGIC;
signal transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505 : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506 : STD_LOGIC;
signal rom_addr : STD_LOGIC_VECTOR ( 30 downto 0 );
signal Result : STD_LOGIC_VECTOR ( 30 downto 0 );
signal Mcount_rom_addr_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal Mcount_rom_addr_cy : STD_LOGIC_VECTOR ( 29 downto 0 );
signal transmitter_Mcount_baud_divider_cy : STD_LOGIC_VECTOR ( 29 downto 0 );
signal transmitter_Mcount_baud_divider_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal transmitter_Result : STD_LOGIC_VECTOR ( 30 downto 0 );
signal transmitter_data_shift_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
signal transmitter_baud_divider : STD_LOGIC_VECTOR ( 30 downto 0 );
signal transmitter_bits_transmitted : STD_LOGIC_VECTOR ( 30 downto 0 );
begin
XST_VCC : VCC
port map (
P => N0
);
XST_GND : GND
port map (
G => Mram_n0015_7_0_7
);
ser_ready_last : FD
port map (
C => clk_BUFGP_0,
D => transmitter_ready_2,
Q => ser_ready_last_3
);
rom_addr_0 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(0),
R => Q_n0018,
Q => rom_addr(0)
);
rom_addr_1 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(1),
R => Q_n0018,
Q => rom_addr(1)
);
rom_addr_2 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(2),
R => Q_n0018,
Q => rom_addr(2)
);
rom_addr_3 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(3),
R => Q_n0018,
Q => rom_addr(3)
);
rom_addr_4 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(4),
R => Q_n0018,
Q => rom_addr(4)
);
rom_addr_5 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(5),
R => Q_n0018,
Q => rom_addr(5)
);
rom_addr_6 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(6),
R => Q_n0018,
Q => rom_addr(6)
);
rom_addr_7 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(7),
R => Q_n0018,
Q => rom_addr(7)
);
rom_addr_8 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(8),
R => Q_n0018,
Q => rom_addr(8)
);
rom_addr_9 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(9),
R => Q_n0018,
Q => rom_addr(9)
);
rom_addr_10 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(10),
R => Q_n0018,
Q => rom_addr(10)
);
rom_addr_11 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(11),
R => Q_n0018,
Q => rom_addr(11)
);
rom_addr_12 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(12),
R => Q_n0018,
Q => rom_addr(12)
);
rom_addr_13 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(13),
R => Q_n0018,
Q => rom_addr(13)
);
rom_addr_14 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(14),
R => Q_n0018,
Q => rom_addr(14)
);
rom_addr_15 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(15),
R => Q_n0018,
Q => rom_addr(15)
);
rom_addr_16 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(16),
R => Q_n0018,
Q => rom_addr(16)
);
rom_addr_17 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(17),
R => Q_n0018,
Q => rom_addr(17)
);
rom_addr_18 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(18),
R => Q_n0018,
Q => rom_addr(18)
);
rom_addr_19 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(19),
R => Q_n0018,
Q => rom_addr(19)
);
rom_addr_20 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(20),
R => Q_n0018,
Q => rom_addr(20)
);
rom_addr_21 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(21),
R => Q_n0018,
Q => rom_addr(21)
);
rom_addr_22 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(22),
R => Q_n0018,
Q => rom_addr(22)
);
rom_addr_23 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(23),
R => Q_n0018,
Q => rom_addr(23)
);
rom_addr_24 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(24),
R => Q_n0018,
Q => rom_addr(24)
);
rom_addr_25 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(25),
R => Q_n0018,
Q => rom_addr(25)
);
rom_addr_26 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(26),
R => Q_n0018,
Q => rom_addr(26)
);
rom_addr_27 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(27),
R => Q_n0018,
Q => rom_addr(27)
);
rom_addr_28 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(28),
R => Q_n0018,
Q => rom_addr(28)
);
rom_addr_29 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(29),
R => Q_n0018,
Q => rom_addr(29)
);
rom_addr_30 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(30),
R => Q_n0018,
Q => rom_addr(30)
);
Mcount_rom_addr_cy_0_Q : MUXCY
port map (
CI => Mram_n0015_7_0_7,
DI => N0,
S => Mcount_rom_addr_lut(0),
O => Mcount_rom_addr_cy(0)
);
Mcount_rom_addr_xor_0_Q : XORCY
port map (
CI => Mram_n0015_7_0_7,
LI => Mcount_rom_addr_lut(0),
O => Result(0)
);
Mcount_rom_addr_cy_1_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(0),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_1_rt_380,
O => Mcount_rom_addr_cy(1)
);
Mcount_rom_addr_xor_1_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(0),
LI => Mcount_rom_addr_cy_1_rt_380,
O => Result(1)
);
Mcount_rom_addr_cy_2_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(1),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_2_rt_381,
O => Mcount_rom_addr_cy(2)
);
Mcount_rom_addr_xor_2_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(1),
LI => Mcount_rom_addr_cy_2_rt_381,
O => Result(2)
);
Mcount_rom_addr_cy_3_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(2),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_3_rt_382,
O => Mcount_rom_addr_cy(3)
);
Mcount_rom_addr_xor_3_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(2),
LI => Mcount_rom_addr_cy_3_rt_382,
O => Result(3)
);
Mcount_rom_addr_cy_4_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(3),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_4_rt_383,
O => Mcount_rom_addr_cy(4)
);
Mcount_rom_addr_xor_4_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(3),
LI => Mcount_rom_addr_cy_4_rt_383,
O => Result(4)
);
Mcount_rom_addr_cy_5_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(4),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_5_rt_384,
O => Mcount_rom_addr_cy(5)
);
Mcount_rom_addr_xor_5_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(4),
LI => Mcount_rom_addr_cy_5_rt_384,
O => Result(5)
);
Mcount_rom_addr_cy_6_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(5),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_6_rt_385,
O => Mcount_rom_addr_cy(6)
);
Mcount_rom_addr_xor_6_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(5),
LI => Mcount_rom_addr_cy_6_rt_385,
O => Result(6)
);
Mcount_rom_addr_cy_7_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(6),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_7_rt_386,
O => Mcount_rom_addr_cy(7)
);
Mcount_rom_addr_xor_7_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(6),
LI => Mcount_rom_addr_cy_7_rt_386,
O => Result(7)
);
Mcount_rom_addr_cy_8_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(7),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_8_rt_387,
O => Mcount_rom_addr_cy(8)
);
Mcount_rom_addr_xor_8_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(7),
LI => Mcount_rom_addr_cy_8_rt_387,
O => Result(8)
);
Mcount_rom_addr_cy_9_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(8),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_9_rt_388,
O => Mcount_rom_addr_cy(9)
);
Mcount_rom_addr_xor_9_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(8),
LI => Mcount_rom_addr_cy_9_rt_388,
O => Result(9)
);
Mcount_rom_addr_cy_10_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(9),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_10_rt_389,
O => Mcount_rom_addr_cy(10)
);
Mcount_rom_addr_xor_10_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(9),
LI => Mcount_rom_addr_cy_10_rt_389,
O => Result(10)
);
Mcount_rom_addr_cy_11_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(10),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_11_rt_390,
O => Mcount_rom_addr_cy(11)
);
Mcount_rom_addr_xor_11_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(10),
LI => Mcount_rom_addr_cy_11_rt_390,
O => Result(11)
);
Mcount_rom_addr_cy_12_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(11),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_12_rt_391,
O => Mcount_rom_addr_cy(12)
);
Mcount_rom_addr_xor_12_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(11),
LI => Mcount_rom_addr_cy_12_rt_391,
O => Result(12)
);
Mcount_rom_addr_cy_13_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(12),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_13_rt_392,
O => Mcount_rom_addr_cy(13)
);
Mcount_rom_addr_xor_13_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(12),
LI => Mcount_rom_addr_cy_13_rt_392,
O => Result(13)
);
Mcount_rom_addr_cy_14_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(13),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_14_rt_393,
O => Mcount_rom_addr_cy(14)
);
Mcount_rom_addr_xor_14_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(13),
LI => Mcount_rom_addr_cy_14_rt_393,
O => Result(14)
);
Mcount_rom_addr_cy_15_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(14),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_15_rt_394,
O => Mcount_rom_addr_cy(15)
);
Mcount_rom_addr_xor_15_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(14),
LI => Mcount_rom_addr_cy_15_rt_394,
O => Result(15)
);
Mcount_rom_addr_cy_16_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(15),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_16_rt_395,
O => Mcount_rom_addr_cy(16)
);
Mcount_rom_addr_xor_16_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(15),
LI => Mcount_rom_addr_cy_16_rt_395,
O => Result(16)
);
Mcount_rom_addr_cy_17_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(16),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_17_rt_396,
O => Mcount_rom_addr_cy(17)
);
Mcount_rom_addr_xor_17_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(16),
LI => Mcount_rom_addr_cy_17_rt_396,
O => Result(17)
);
Mcount_rom_addr_cy_18_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(17),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_18_rt_397,
O => Mcount_rom_addr_cy(18)
);
Mcount_rom_addr_xor_18_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(17),
LI => Mcount_rom_addr_cy_18_rt_397,
O => Result(18)
);
Mcount_rom_addr_cy_19_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(18),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_19_rt_398,
O => Mcount_rom_addr_cy(19)
);
Mcount_rom_addr_xor_19_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(18),
LI => Mcount_rom_addr_cy_19_rt_398,
O => Result(19)
);
Mcount_rom_addr_cy_20_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(19),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_20_rt_399,
O => Mcount_rom_addr_cy(20)
);
Mcount_rom_addr_xor_20_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(19),
LI => Mcount_rom_addr_cy_20_rt_399,
O => Result(20)
);
Mcount_rom_addr_cy_21_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(20),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_21_rt_400,
O => Mcount_rom_addr_cy(21)
);
Mcount_rom_addr_xor_21_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(20),
LI => Mcount_rom_addr_cy_21_rt_400,
O => Result(21)
);
Mcount_rom_addr_cy_22_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(21),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_22_rt_401,
O => Mcount_rom_addr_cy(22)
);
Mcount_rom_addr_xor_22_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(21),
LI => Mcount_rom_addr_cy_22_rt_401,
O => Result(22)
);
Mcount_rom_addr_cy_23_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(22),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_23_rt_402,
O => Mcount_rom_addr_cy(23)
);
Mcount_rom_addr_xor_23_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(22),
LI => Mcount_rom_addr_cy_23_rt_402,
O => Result(23)
);
Mcount_rom_addr_cy_24_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(23),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_24_rt_403,
O => Mcount_rom_addr_cy(24)
);
Mcount_rom_addr_xor_24_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(23),
LI => Mcount_rom_addr_cy_24_rt_403,
O => Result(24)
);
Mcount_rom_addr_cy_25_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(24),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_25_rt_404,
O => Mcount_rom_addr_cy(25)
);
Mcount_rom_addr_xor_25_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(24),
LI => Mcount_rom_addr_cy_25_rt_404,
O => Result(25)
);
Mcount_rom_addr_cy_26_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(25),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_26_rt_405,
O => Mcount_rom_addr_cy(26)
);
Mcount_rom_addr_xor_26_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(25),
LI => Mcount_rom_addr_cy_26_rt_405,
O => Result(26)
);
Mcount_rom_addr_cy_27_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(26),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_27_rt_406,
O => Mcount_rom_addr_cy(27)
);
Mcount_rom_addr_xor_27_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(26),
LI => Mcount_rom_addr_cy_27_rt_406,
O => Result(27)
);
Mcount_rom_addr_cy_28_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(27),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_28_rt_407,
O => Mcount_rom_addr_cy(28)
);
Mcount_rom_addr_xor_28_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(27),
LI => Mcount_rom_addr_cy_28_rt_407,
O => Result(28)
);
Mcount_rom_addr_cy_29_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(28),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_29_rt_408,
O => Mcount_rom_addr_cy(29)
);
Mcount_rom_addr_xor_29_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(28),
LI => Mcount_rom_addr_cy_29_rt_408,
O => Result(29)
);
Mcount_rom_addr_xor_30_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(29),
LI => Mcount_rom_addr_xor_30_rt_467,
O => Result(30)
);
transmitter_Mcount_baud_divider_xor_30_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(29),
LI => transmitter_Mcount_baud_divider_xor_30_rt_468,
O => transmitter_Result(30)
);
transmitter_Mcount_baud_divider_xor_29_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(28),
LI => transmitter_Mcount_baud_divider_cy_29_rt_409,
O => transmitter_Result(29)
);
transmitter_Mcount_baud_divider_cy_29_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(28),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_29_rt_409,
O => transmitter_Mcount_baud_divider_cy(29)
);
transmitter_Mcount_baud_divider_xor_28_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(27),
LI => transmitter_Mcount_baud_divider_cy_28_rt_410,
O => transmitter_Result(28)
);
transmitter_Mcount_baud_divider_cy_28_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(27),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_28_rt_410,
O => transmitter_Mcount_baud_divider_cy(28)
);
transmitter_Mcount_baud_divider_xor_27_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(26),
LI => transmitter_Mcount_baud_divider_cy_27_rt_411,
O => transmitter_Result(27)
);
transmitter_Mcount_baud_divider_cy_27_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(26),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_27_rt_411,
O => transmitter_Mcount_baud_divider_cy(27)
);
transmitter_Mcount_baud_divider_xor_26_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(25),
LI => transmitter_Mcount_baud_divider_cy_26_rt_412,
O => transmitter_Result(26)
);
transmitter_Mcount_baud_divider_cy_26_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(25),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_26_rt_412,
O => transmitter_Mcount_baud_divider_cy(26)
);
transmitter_Mcount_baud_divider_xor_25_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(24),
LI => transmitter_Mcount_baud_divider_cy_25_rt_413,
O => transmitter_Result(25)
);
transmitter_Mcount_baud_divider_cy_25_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(24),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_25_rt_413,
O => transmitter_Mcount_baud_divider_cy(25)
);
transmitter_Mcount_baud_divider_xor_24_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(23),
LI => transmitter_Mcount_baud_divider_cy_24_rt_414,
O => transmitter_Result(24)
);
transmitter_Mcount_baud_divider_cy_24_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(23),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_24_rt_414,
O => transmitter_Mcount_baud_divider_cy(24)
);
transmitter_Mcount_baud_divider_xor_23_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(22),
LI => transmitter_Mcount_baud_divider_cy_23_rt_415,
O => transmitter_Result(23)
);
transmitter_Mcount_baud_divider_cy_23_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(22),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_23_rt_415,
O => transmitter_Mcount_baud_divider_cy(23)
);
transmitter_Mcount_baud_divider_xor_22_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(21),
LI => transmitter_Mcount_baud_divider_cy_22_rt_416,
O => transmitter_Result(22)
);
transmitter_Mcount_baud_divider_cy_22_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(21),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_22_rt_416,
O => transmitter_Mcount_baud_divider_cy(22)
);
transmitter_Mcount_baud_divider_xor_21_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(20),
LI => transmitter_Mcount_baud_divider_cy_21_rt_417,
O => transmitter_Result(21)
);
transmitter_Mcount_baud_divider_cy_21_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(20),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_21_rt_417,
O => transmitter_Mcount_baud_divider_cy(21)
);
transmitter_Mcount_baud_divider_xor_20_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(19),
LI => transmitter_Mcount_baud_divider_cy_20_rt_418,
O => transmitter_Result(20)
);
transmitter_Mcount_baud_divider_cy_20_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(19),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_20_rt_418,
O => transmitter_Mcount_baud_divider_cy(20)
);
transmitter_Mcount_baud_divider_xor_19_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(18),
LI => transmitter_Mcount_baud_divider_cy_19_rt_419,
O => transmitter_Result(19)
);
transmitter_Mcount_baud_divider_cy_19_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(18),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_19_rt_419,
O => transmitter_Mcount_baud_divider_cy(19)
);
transmitter_Mcount_baud_divider_xor_18_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(17),
LI => transmitter_Mcount_baud_divider_cy_18_rt_420,
O => transmitter_Result(18)
);
transmitter_Mcount_baud_divider_cy_18_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(17),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_18_rt_420,
O => transmitter_Mcount_baud_divider_cy(18)
);
transmitter_Mcount_baud_divider_xor_17_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(16),
LI => transmitter_Mcount_baud_divider_cy_17_rt_421,
O => transmitter_Result(17)
);
transmitter_Mcount_baud_divider_cy_17_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(16),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_17_rt_421,
O => transmitter_Mcount_baud_divider_cy(17)
);
transmitter_Mcount_baud_divider_xor_16_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(15),
LI => transmitter_Mcount_baud_divider_cy_16_rt_422,
O => transmitter_Result(16)
);
transmitter_Mcount_baud_divider_cy_16_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(15),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_16_rt_422,
O => transmitter_Mcount_baud_divider_cy(16)
);
transmitter_Mcount_baud_divider_xor_15_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(14),
LI => transmitter_Mcount_baud_divider_cy_15_rt_423,
O => transmitter_Result(15)
);
transmitter_Mcount_baud_divider_cy_15_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(14),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_15_rt_423,
O => transmitter_Mcount_baud_divider_cy(15)
);
transmitter_Mcount_baud_divider_xor_14_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(13),
LI => transmitter_Mcount_baud_divider_cy_14_rt_424,
O => transmitter_Result(14)
);
transmitter_Mcount_baud_divider_cy_14_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(13),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_14_rt_424,
O => transmitter_Mcount_baud_divider_cy(14)
);
transmitter_Mcount_baud_divider_xor_13_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(12),
LI => transmitter_Mcount_baud_divider_cy_13_rt_425,
O => transmitter_Result(13)
);
transmitter_Mcount_baud_divider_cy_13_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(12),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_13_rt_425,
O => transmitter_Mcount_baud_divider_cy(13)
);
transmitter_Mcount_baud_divider_xor_12_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(11),
LI => transmitter_Mcount_baud_divider_cy_12_rt_426,
O => transmitter_Result(12)
);
transmitter_Mcount_baud_divider_cy_12_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(11),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_12_rt_426,
O => transmitter_Mcount_baud_divider_cy(12)
);
transmitter_Mcount_baud_divider_xor_11_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(10),
LI => transmitter_Mcount_baud_divider_cy_11_rt_427,
O => transmitter_Result(11)
);
transmitter_Mcount_baud_divider_cy_11_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(10),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_11_rt_427,
O => transmitter_Mcount_baud_divider_cy(11)
);
transmitter_Mcount_baud_divider_xor_10_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(9),
LI => transmitter_Mcount_baud_divider_cy_10_rt_428,
O => transmitter_Result(10)
);
transmitter_Mcount_baud_divider_cy_10_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(9),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_10_rt_428,
O => transmitter_Mcount_baud_divider_cy(10)
);
transmitter_Mcount_baud_divider_xor_9_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(8),
LI => transmitter_Mcount_baud_divider_cy_9_rt_429,
O => transmitter_Result(9)
);
transmitter_Mcount_baud_divider_cy_9_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(8),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_9_rt_429,
O => transmitter_Mcount_baud_divider_cy(9)
);
transmitter_Mcount_baud_divider_xor_8_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(7),
LI => transmitter_Mcount_baud_divider_cy_8_rt_430,
O => transmitter_Result(8)
);
transmitter_Mcount_baud_divider_cy_8_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(7),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_8_rt_430,
O => transmitter_Mcount_baud_divider_cy(8)
);
transmitter_Mcount_baud_divider_xor_7_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(6),
LI => transmitter_Mcount_baud_divider_cy_7_rt_431,
O => transmitter_Result(7)
);
transmitter_Mcount_baud_divider_cy_7_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(6),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_7_rt_431,
O => transmitter_Mcount_baud_divider_cy(7)
);
transmitter_Mcount_baud_divider_xor_6_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(5),
LI => transmitter_Mcount_baud_divider_cy_6_rt_432,
O => transmitter_Result(6)
);
transmitter_Mcount_baud_divider_cy_6_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(5),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_6_rt_432,
O => transmitter_Mcount_baud_divider_cy(6)
);
transmitter_Mcount_baud_divider_xor_5_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(4),
LI => transmitter_Mcount_baud_divider_cy_5_rt_433,
O => transmitter_Result(5)
);
transmitter_Mcount_baud_divider_cy_5_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(4),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_5_rt_433,
O => transmitter_Mcount_baud_divider_cy(5)
);
transmitter_Mcount_baud_divider_xor_4_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(3),
LI => transmitter_Mcount_baud_divider_cy_4_rt_434,
O => transmitter_Result(4)
);
transmitter_Mcount_baud_divider_cy_4_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(3),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_4_rt_434,
O => transmitter_Mcount_baud_divider_cy(4)
);
transmitter_Mcount_baud_divider_xor_3_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(2),
LI => transmitter_Mcount_baud_divider_cy_3_rt_435,
O => transmitter_Result(3)
);
transmitter_Mcount_baud_divider_cy_3_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(2),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_3_rt_435,
O => transmitter_Mcount_baud_divider_cy(3)
);
transmitter_Mcount_baud_divider_xor_2_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(1),
LI => transmitter_Mcount_baud_divider_cy_2_rt_436,
O => transmitter_Result(2)
);
transmitter_Mcount_baud_divider_cy_2_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(1),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_2_rt_436,
O => transmitter_Mcount_baud_divider_cy(2)
);
transmitter_Mcount_baud_divider_xor_1_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(0),
LI => transmitter_Mcount_baud_divider_cy_1_rt_437,
O => transmitter_Result(1)
);
transmitter_Mcount_baud_divider_cy_1_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(0),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_1_rt_437,
O => transmitter_Mcount_baud_divider_cy(1)
);
transmitter_Mcount_baud_divider_xor_0_Q : XORCY
port map (
CI => Mram_n0015_7_0_7,
LI => transmitter_Mcount_baud_divider_lut(0),
O => transmitter_Result(0)
);
transmitter_Mcount_baud_divider_cy_0_Q : MUXCY
port map (
CI => Mram_n0015_7_0_7,
DI => N0,
S => transmitter_Mcount_baud_divider_lut(0),
O => transmitter_Mcount_baud_divider_cy(0)
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_30_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_Q_142,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_30_rt_469,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_30_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_29_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_Q_143,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_rt_438,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_29_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_Q_143,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_rt_438,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_Q_142
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_28_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_Q_144,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_rt_439,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_28_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_Q_144,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_rt_439,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_Q_143
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_27_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_Q_145,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_rt_440,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_27_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_Q_145,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_rt_440,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_Q_144
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_26_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_Q_146,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_rt_441,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_26_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_Q_146,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_rt_441,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_Q_145
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_25_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_Q_147,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_rt_442,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_25_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_Q_147,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_rt_442,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_Q_146
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_24_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_Q_148,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_rt_443,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_24_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_Q_148,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_rt_443,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_Q_147
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_23_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_Q_149,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_rt_444,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_23_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_Q_149,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_rt_444,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_Q_148
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_22_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_Q_150,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_rt_445,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_22_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_Q_150,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_rt_445,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_Q_149
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_21_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_Q_151,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_rt_446,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_21_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_Q_151,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_rt_446,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_Q_150
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_20_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_Q_152,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_rt_447,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_20_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_Q_152,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_rt_447,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_Q_151
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_19_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_Q_153,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_rt_448,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_19_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_Q_153,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_rt_448,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_Q_152
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_18_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_Q_154,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_rt_449,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_18_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_Q_154,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_rt_449,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_Q_153
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_17_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_Q_155,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_rt_450,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_17_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_Q_155,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_rt_450,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_Q_154
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_16_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_Q_156,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_rt_451,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_16_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_Q_156,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_rt_451,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_Q_155
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_15_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_Q_157,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_rt_452,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_15_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_Q_157,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_rt_452,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_Q_156
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_14_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_Q_158,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_rt_453,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_14_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_Q_158,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_rt_453,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_Q_157
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_13_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_Q_159,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_rt_454,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_13_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_Q_159,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_rt_454,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_Q_158
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_12_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_Q_160,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_rt_455,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_12_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_Q_160,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_rt_455,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_Q_159
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_11_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_Q_161,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_rt_456,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_11_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_Q_161,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_rt_456,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_Q_160
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_10_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_Q_162,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_rt_457,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_10_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_Q_162,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_rt_457,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_Q_161
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_9_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_Q_163,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_rt_458,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_9_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_Q_163,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_rt_458,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_Q_162
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_8_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_Q_164,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_rt_459,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_8_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_Q_164,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_rt_459,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_Q_163
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_7_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_Q_165,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_rt_460,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_7_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_Q_165,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_rt_460,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_Q_164
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_6_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_Q_166,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_rt_461,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_6_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_Q_166,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_rt_461,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_Q_165
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_5_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_Q_167,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_rt_462,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_5_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_Q_167,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_rt_462,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_Q_166
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_4_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_Q_168,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_rt_463,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_4_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_Q_168,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_rt_463,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_Q_167
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_3_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_Q_169,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_rt_464,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_3_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_Q_169,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_rt_464,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_Q_168
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_2_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_Q_170,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_rt_465,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_2_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_Q_170,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_rt_465,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_Q_169
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_1_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_0_Q_171,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_rt_466,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_1_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_0_Q_171,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_rt_466,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_Q_170
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_0_Q : XORCY
port map (
CI => Mram_n0015_7_0_7,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_lut_0_Q,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_0_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_0_Q : MUXCY
port map (
CI => Mram_n0015_7_0_7,
DI => N0,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_lut_0_Q,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_0_Q_171
);
transmitter_state_FSM_FFd1 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_FSM_FFd1_In,
Q => transmitter_state_FSM_FFd1_344
);
transmitter_state_FSM_FFd2 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_FSM_FFd2_In,
Q => transmitter_state_FSM_FFd2_204
);
transmitter_bits_transmitted_30 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_30_Q,
Q => transmitter_bits_transmitted(30)
);
transmitter_bits_transmitted_29 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_29_Q,
Q => transmitter_bits_transmitted(29)
);
transmitter_bits_transmitted_28 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_28_Q,
Q => transmitter_bits_transmitted(28)
);
transmitter_bits_transmitted_27 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_27_Q,
Q => transmitter_bits_transmitted(27)
);
transmitter_bits_transmitted_26 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_26_Q,
Q => transmitter_bits_transmitted(26)
);
transmitter_bits_transmitted_25 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_25_Q,
Q => transmitter_bits_transmitted(25)
);
transmitter_bits_transmitted_24 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_24_Q,
Q => transmitter_bits_transmitted(24)
);
transmitter_bits_transmitted_23 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_23_Q,
Q => transmitter_bits_transmitted(23)
);
transmitter_bits_transmitted_22 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_22_Q,
Q => transmitter_bits_transmitted(22)
);
transmitter_bits_transmitted_21 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_21_Q,
Q => transmitter_bits_transmitted(21)
);
transmitter_bits_transmitted_20 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_20_Q,
Q => transmitter_bits_transmitted(20)
);
transmitter_bits_transmitted_19 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_19_Q,
Q => transmitter_bits_transmitted(19)
);
transmitter_bits_transmitted_18 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_18_Q,
Q => transmitter_bits_transmitted(18)
);
transmitter_bits_transmitted_17 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_17_Q,
Q => transmitter_bits_transmitted(17)
);
transmitter_bits_transmitted_16 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_16_Q,
Q => transmitter_bits_transmitted(16)
);
transmitter_bits_transmitted_15 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_15_Q,
Q => transmitter_bits_transmitted(15)
);
transmitter_bits_transmitted_14 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_14_Q,
Q => transmitter_bits_transmitted(14)
);
transmitter_bits_transmitted_13 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_13_Q,
Q => transmitter_bits_transmitted(13)
);
transmitter_bits_transmitted_12 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_12_Q,
Q => transmitter_bits_transmitted(12)
);
transmitter_bits_transmitted_11 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_11_Q,
Q => transmitter_bits_transmitted(11)
);
transmitter_bits_transmitted_10 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_10_Q,
Q => transmitter_bits_transmitted(10)
);
transmitter_bits_transmitted_9 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_9_Q,
Q => transmitter_bits_transmitted(9)
);
transmitter_bits_transmitted_8 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_8_Q,
Q => transmitter_bits_transmitted(8)
);
transmitter_bits_transmitted_7 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_7_Q,
Q => transmitter_bits_transmitted(7)
);
transmitter_bits_transmitted_6 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_6_Q,
Q => transmitter_bits_transmitted(6)
);
transmitter_bits_transmitted_5 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_5_Q,
Q => transmitter_bits_transmitted(5)
);
transmitter_bits_transmitted_4 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_4_Q,
Q => transmitter_bits_transmitted(4)
);
transmitter_bits_transmitted_3 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_3_Q,
Q => transmitter_bits_transmitted(3)
);
transmitter_bits_transmitted_2 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_2_Q,
Q => transmitter_bits_transmitted(2)
);
transmitter_bits_transmitted_1 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_1_Q,
Q => transmitter_bits_transmitted(1)
);
transmitter_bits_transmitted_0 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_0_Q,
Q => transmitter_bits_transmitted(0)
);
transmitter_ready : FD
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_GND_5_o_Mux_21_o,
Q => transmitter_ready_2
);
transmitter_data_shift_reg_6 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_6_Q,
Q => transmitter_data_shift_reg(6)
);
transmitter_data_shift_reg_5 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_5_Q,
Q => transmitter_data_shift_reg(5)
);
transmitter_data_shift_reg_4 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_4_Q,
Q => transmitter_data_shift_reg(4)
);
transmitter_data_shift_reg_3 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_3_Q,
Q => transmitter_data_shift_reg(3)
);
transmitter_data_shift_reg_2 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_2_Q,
Q => transmitter_data_shift_reg(2)
);
transmitter_data_shift_reg_1 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_1_Q,
Q => transmitter_data_shift_reg(1)
);
transmitter_data_shift_reg_0 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_0_Q,
Q => transmitter_data_shift_reg(0)
);
transmitter_tx_out : FD
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_PWR_5_o_Mux_20_o,
Q => transmitter_tx_out_1
);
transmitter_baud_clk_edge : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_GND_5_o_baud_divider_30_equal_4_o,
Q => transmitter_baud_clk_edge_342
);
ser_ready_ser_ready_last_AND_7_o1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_ready_2,
I1 => ser_ready_last_3,
O => ser_ready_ser_ready_last_AND_7_o
);
Mram_n0015_7_0_111 : LUT5
generic map(
INIT => X"CC72B557"
)
port map (
I0 => rom_addr(0),
I1 => rom_addr(1),
I2 => rom_addr(2),
I3 => rom_addr(4),
I4 => rom_addr(3),
O => Mram_n0015_7_0_1
);
Mram_n0015_7_0_31 : LUT5
generic map(
INIT => X"A9A089D5"
)
port map (
I0 => rom_addr(4),
I1 => rom_addr(3),
I2 => rom_addr(0),
I3 => rom_addr(1),
I4 => rom_addr(2),
O => Mram_n0015_7_0_3
);
Mram_n0015_7_0_21 : LUT5
generic map(
INIT => X"6236FF3F"
)
port map (
I0 => rom_addr(4),
I1 => rom_addr(1),
I2 => rom_addr(0),
I3 => rom_addr(2),
I4 => rom_addr(3),
O => Mram_n0015_7_0_2
);
Mram_n0015_7_0_51 : LUT5
generic map(
INIT => X"1D101018"
)
port map (
I0 => rom_addr(2),
I1 => rom_addr(3),
I2 => rom_addr(4),
I3 => rom_addr(0),
I4 => rom_addr(1),
O => Mram_n0015_7_0_5
);
Mram_n0015_7_0_41 : LUT5
generic map(
INIT => X"222402C4"
)
port map (
I0 => rom_addr(2),
I1 => rom_addr(4),
I2 => rom_addr(1),
I3 => rom_addr(3),
I4 => rom_addr(0),
O => Mram_n0015_7_0_4
);
Mram_n0015_7_0_11 : LUT5
generic map(
INIT => X"3435791A"
)
port map (
I0 => rom_addr(3),
I1 => rom_addr(1),
I2 => rom_addr(0),
I3 => rom_addr(2),
I4 => rom_addr(4),
O => Mram_n0015_7_0_Q
);
Mram_n0015_7_0_61 : LUT5
generic map(
INIT => X"1617FF13"
)
port map (
I0 => rom_addr(1),
I1 => rom_addr(4),
I2 => rom_addr(0),
I3 => rom_addr(2),
I4 => rom_addr(3),
O => Mram_n0015_7_0_6
);
transmitter_mux12 : LUT5
generic map(
INIT => X"F7D5A280"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(1),
I3 => transmitter_data_shift_reg(0),
I4 => Mram_n0015_7_0_Q,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_0_Q
);
transmitter_mux111 : LUT5
generic map(
INIT => X"F7D5A280"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(2),
I3 => transmitter_data_shift_reg(1),
I4 => Mram_n0015_7_0_1,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_1_Q
);
transmitter_mux311 : LUT5
generic map(
INIT => X"F7D5A280"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(4),
I3 => transmitter_data_shift_reg(3),
I4 => Mram_n0015_7_0_3,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_3_Q
);
transmitter_mux411 : LUT5
generic map(
INIT => X"F7D5A280"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(5),
I3 => transmitter_data_shift_reg(4),
I4 => Mram_n0015_7_0_4,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_4_Q
);
transmitter_mux211 : LUT5
generic map(
INIT => X"F7D5A280"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(3),
I3 => transmitter_data_shift_reg(2),
I4 => Mram_n0015_7_0_2,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_2_Q
);
transmitter_mux611 : LUT4
generic map(
INIT => X"7520"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(6),
I3 => Mram_n0015_7_0_6,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_6_Q
);
transmitter_mux511 : LUT5
generic map(
INIT => X"F7D5A280"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(6),
I3 => transmitter_data_shift_reg(5),
I4 => Mram_n0015_7_0_5,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_5_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT110 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(0),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_0_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_0_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT210 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(10),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_10_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_10_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT32 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(11),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_11_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_11_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT41 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(12),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_12_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_12_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT51 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(13),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_13_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_13_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT61 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(14),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_14_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_14_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT71 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(15),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_15_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_15_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT81 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(16),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_16_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_16_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT91 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(17),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_17_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_17_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT101 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(18),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_18_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_18_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(19),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_19_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_19_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT121 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(1),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_1_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_1_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT131 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(20),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_20_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_20_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT141 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(21),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_21_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_21_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT151 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(22),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_22_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_22_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT161 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(23),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_23_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_23_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT171 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(24),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_24_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_24_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT181 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(25),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_25_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_25_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT191 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(26),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_26_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_26_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT201 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(27),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_27_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_27_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT211 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(28),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_28_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_28_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT221 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(29),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_29_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_29_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT231 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(2),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_2_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_2_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT241 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(30),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_30_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_30_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT251 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(3),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_3_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_3_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT261 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(4),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_4_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_4_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT271 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(5),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_5_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_5_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT281 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(6),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_6_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_6_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT291 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(7),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_7_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_7_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT301 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(8),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_8_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_8_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT311 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(9),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_9_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_9_Q
);
transmitter_state_1_PWR_5_o_Mux_20_o1 : LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => transmitter_state_FSM_FFd2_204,
I1 => transmitter_data_shift_reg(0),
I2 => transmitter_state_FSM_FFd1_344,
O => transmitter_state_1_PWR_5_o_Mux_20_o
);
transmitter_state_state_1_GND_5_o_Mux_21_o1 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => transmitter_state_FSM_FFd2_204,
I1 => transmitter_state_FSM_FFd1_344,
O => transmitter_state_1_GND_5_o_Mux_21_o
);
transmitter_n0071_inv1 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => transmitter_state_FSM_FFd2_204,
I1 => transmitter_state_FSM_FFd1_344,
O => transmitter_n0071_inv
);
Q_n00181 : LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => ser_ready_last_3,
I1 => transmitter_ready_2,
I2 => rom_addr(3),
I3 => rom_addr(4),
I4 => rom_addr(1),
I5 => rom_addr(0),
O => Q_n00181_352
);
Q_n00182 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => rom_addr(8),
I1 => rom_addr(9),
I2 => rom_addr(7),
I3 => rom_addr(6),
I4 => rom_addr(5),
I5 => rom_addr(30),
O => Q_n00182_353
);
Q_n00183 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => rom_addr(25),
I1 => rom_addr(26),
I2 => rom_addr(27),
I3 => rom_addr(28),
I4 => rom_addr(29),
I5 => rom_addr(2),
O => Q_n00183_354
);
Q_n00184 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => rom_addr(23),
I1 => rom_addr(24),
I2 => rom_addr(22),
I3 => rom_addr(21),
I4 => rom_addr(20),
I5 => rom_addr(19),
O => Q_n00184_355
);
Q_n00185 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => rom_addr(17),
I1 => rom_addr(18),
I2 => rom_addr(16),
I3 => rom_addr(15),
I4 => rom_addr(14),
I5 => rom_addr(13),
O => Q_n00185_356
);
Q_n00186 : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => rom_addr(11),
I1 => rom_addr(12),
I2 => rom_addr(10),
O => Q_n00186_357
);
Q_n00187 : LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => Q_n00186_357,
I1 => Q_n00185_356,
I2 => Q_n00184_355,
I3 => Q_n00182_353,
I4 => Q_n00183_354,
I5 => Q_n00181_352,
O => Q_n0018
);
transmitter_GND_5_o_baud_divider_30_equal_4_o_30_SW0 : LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => transmitter_baud_divider(9),
I1 => transmitter_baud_divider(5),
I2 => transmitter_baud_divider(2),
I3 => transmitter_baud_divider(11),
O => N3
);
transmitter_GND_5_o_baud_divider_30_equal_4_o_30_Q : LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => transmitter_baud_divider(10),
I1 => transmitter_baud_divider(12),
I2 => transmitter_baud_divider(4),
I3 => transmitter_baud_divider(6),
I4 => N3,
I5 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_1_108,
O => transmitter_GND_5_o_baud_divider_30_equal_4_o
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_SW0 : LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => transmitter_baud_divider(9),
I1 => transmitter_baud_divider(5),
I2 => transmitter_baud_divider(2),
I3 => transmitter_baud_divider(11),
O => N5
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q : LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => transmitter_baud_divider(10),
I1 => transmitter_baud_divider(12),
I2 => transmitter_baud_divider(4),
I3 => transmitter_baud_divider(6),
I4 => N5,
I5 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_1_108,
O => transmitter_GND_5_o_baud_divider_30_equal_1_o
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_11 : LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => transmitter_baud_divider(3),
I1 => transmitter_baud_divider(0),
I2 => transmitter_baud_divider(30),
I3 => transmitter_baud_divider(1),
I4 => transmitter_baud_divider(7),
I5 => transmitter_baud_divider(8),
O => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_11_360
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_12 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => transmitter_baud_divider(14),
I1 => transmitter_baud_divider(13),
I2 => transmitter_baud_divider(15),
I3 => transmitter_baud_divider(17),
I4 => transmitter_baud_divider(16),
I5 => transmitter_baud_divider(18),
O => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_12_361
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_13 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => transmitter_baud_divider(20),
I1 => transmitter_baud_divider(19),
I2 => transmitter_baud_divider(21),
I3 => transmitter_baud_divider(22),
I4 => transmitter_baud_divider(24),
I5 => transmitter_baud_divider(23),
O => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_13_362
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_14 : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => transmitter_baud_divider(26),
I1 => transmitter_baud_divider(25),
I2 => transmitter_baud_divider(27),
I3 => transmitter_baud_divider(28),
I4 => transmitter_baud_divider(29),
O => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_14_363
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_15 : LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_14_363,
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_13_362,
I2 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_12_361,
I3 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_11_360,
O => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_1_108
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_11 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => transmitter_bits_transmitted(3),
I1 => transmitter_bits_transmitted(30),
I2 => transmitter_bits_transmitted(4),
I3 => transmitter_bits_transmitted(5),
I4 => transmitter_bits_transmitted(6),
I5 => transmitter_bits_transmitted(7),
O => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_11_364
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_12 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => transmitter_bits_transmitted(9),
I1 => transmitter_bits_transmitted(8),
I2 => transmitter_bits_transmitted(10),
I3 => transmitter_bits_transmitted(11),
I4 => transmitter_bits_transmitted(12),
I5 => transmitter_bits_transmitted(13),
O => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_12_365
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_13 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => transmitter_bits_transmitted(14),
I1 => transmitter_bits_transmitted(15),
I2 => transmitter_bits_transmitted(16),
I3 => transmitter_bits_transmitted(17),
I4 => transmitter_bits_transmitted(18),
I5 => transmitter_bits_transmitted(19),
O => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_13_366
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_14 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => transmitter_bits_transmitted(21),
I1 => transmitter_bits_transmitted(20),
I2 => transmitter_bits_transmitted(22),
I3 => transmitter_bits_transmitted(23),
I4 => transmitter_bits_transmitted(24),
I5 => transmitter_bits_transmitted(25),
O => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_14_367
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_15 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => transmitter_bits_transmitted(27),
I1 => transmitter_bits_transmitted(26),
I2 => transmitter_bits_transmitted(28),
I3 => transmitter_bits_transmitted(29),
O => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_15_368
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_16 : LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_15_368,
I1 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_14_367,
I2 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_11_364,
I3 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_13_366,
I4 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_12_365,
O => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_1
);
mojo_tx_OBUF : OBUF
port map (
I => transmitter_tx_out_1,
O => mojo_tx
);
idpromnut_tx_OBUF : OBUF
port map (
I => transmitter_tx_out_1,
O => idpromnut_tx
);
led0_OBUF : OBUF
port map (
I => Mram_n0015_7_0_Q,
O => led0
);
led1_OBUF : OBUF
port map (
I => Mram_n0015_7_0_1,
O => led1
);
led2_OBUF : OBUF
port map (
I => Mram_n0015_7_0_2,
O => led2
);
led3_OBUF : OBUF
port map (
I => Mram_n0015_7_0_3,
O => led3
);
led4_OBUF : OBUF
port map (
I => Mram_n0015_7_0_4,
O => led4
);
led5_OBUF : OBUF
port map (
I => Mram_n0015_7_0_5,
O => led5
);
led6_OBUF : OBUF
port map (
I => Mram_n0015_7_0_6,
O => led6
);
led7_OBUF : OBUF
port map (
I => Mram_n0015_7_0_7,
O => led7
);
Mcount_rom_addr_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(1),
O => Mcount_rom_addr_cy_1_rt_380
);
Mcount_rom_addr_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(2),
O => Mcount_rom_addr_cy_2_rt_381
);
Mcount_rom_addr_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(3),
O => Mcount_rom_addr_cy_3_rt_382
);
Mcount_rom_addr_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(4),
O => Mcount_rom_addr_cy_4_rt_383
);
Mcount_rom_addr_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(5),
O => Mcount_rom_addr_cy_5_rt_384
);
Mcount_rom_addr_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(6),
O => Mcount_rom_addr_cy_6_rt_385
);
Mcount_rom_addr_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(7),
O => Mcount_rom_addr_cy_7_rt_386
);
Mcount_rom_addr_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(8),
O => Mcount_rom_addr_cy_8_rt_387
);
Mcount_rom_addr_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(9),
O => Mcount_rom_addr_cy_9_rt_388
);
Mcount_rom_addr_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(10),
O => Mcount_rom_addr_cy_10_rt_389
);
Mcount_rom_addr_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(11),
O => Mcount_rom_addr_cy_11_rt_390
);
Mcount_rom_addr_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(12),
O => Mcount_rom_addr_cy_12_rt_391
);
Mcount_rom_addr_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(13),
O => Mcount_rom_addr_cy_13_rt_392
);
Mcount_rom_addr_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(14),
O => Mcount_rom_addr_cy_14_rt_393
);
Mcount_rom_addr_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(15),
O => Mcount_rom_addr_cy_15_rt_394
);
Mcount_rom_addr_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(16),
O => Mcount_rom_addr_cy_16_rt_395
);
Mcount_rom_addr_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(17),
O => Mcount_rom_addr_cy_17_rt_396
);
Mcount_rom_addr_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(18),
O => Mcount_rom_addr_cy_18_rt_397
);
Mcount_rom_addr_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(19),
O => Mcount_rom_addr_cy_19_rt_398
);
Mcount_rom_addr_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(20),
O => Mcount_rom_addr_cy_20_rt_399
);
Mcount_rom_addr_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(21),
O => Mcount_rom_addr_cy_21_rt_400
);
Mcount_rom_addr_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(22),
O => Mcount_rom_addr_cy_22_rt_401
);
Mcount_rom_addr_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(23),
O => Mcount_rom_addr_cy_23_rt_402
);
Mcount_rom_addr_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(24),
O => Mcount_rom_addr_cy_24_rt_403
);
Mcount_rom_addr_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(25),
O => Mcount_rom_addr_cy_25_rt_404
);
Mcount_rom_addr_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(26),
O => Mcount_rom_addr_cy_26_rt_405
);
Mcount_rom_addr_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(27),
O => Mcount_rom_addr_cy_27_rt_406
);
Mcount_rom_addr_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(28),
O => Mcount_rom_addr_cy_28_rt_407
);
Mcount_rom_addr_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(29),
O => Mcount_rom_addr_cy_29_rt_408
);
transmitter_Mcount_baud_divider_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(29),
O => transmitter_Mcount_baud_divider_cy_29_rt_409
);
transmitter_Mcount_baud_divider_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(28),
O => transmitter_Mcount_baud_divider_cy_28_rt_410
);
transmitter_Mcount_baud_divider_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(27),
O => transmitter_Mcount_baud_divider_cy_27_rt_411
);
transmitter_Mcount_baud_divider_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(26),
O => transmitter_Mcount_baud_divider_cy_26_rt_412
);
transmitter_Mcount_baud_divider_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(25),
O => transmitter_Mcount_baud_divider_cy_25_rt_413
);
transmitter_Mcount_baud_divider_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(24),
O => transmitter_Mcount_baud_divider_cy_24_rt_414
);
transmitter_Mcount_baud_divider_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(23),
O => transmitter_Mcount_baud_divider_cy_23_rt_415
);
transmitter_Mcount_baud_divider_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(22),
O => transmitter_Mcount_baud_divider_cy_22_rt_416
);
transmitter_Mcount_baud_divider_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(21),
O => transmitter_Mcount_baud_divider_cy_21_rt_417
);
transmitter_Mcount_baud_divider_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(20),
O => transmitter_Mcount_baud_divider_cy_20_rt_418
);
transmitter_Mcount_baud_divider_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(19),
O => transmitter_Mcount_baud_divider_cy_19_rt_419
);
transmitter_Mcount_baud_divider_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(18),
O => transmitter_Mcount_baud_divider_cy_18_rt_420
);
transmitter_Mcount_baud_divider_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(17),
O => transmitter_Mcount_baud_divider_cy_17_rt_421
);
transmitter_Mcount_baud_divider_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(16),
O => transmitter_Mcount_baud_divider_cy_16_rt_422
);
transmitter_Mcount_baud_divider_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(15),
O => transmitter_Mcount_baud_divider_cy_15_rt_423
);
transmitter_Mcount_baud_divider_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(14),
O => transmitter_Mcount_baud_divider_cy_14_rt_424
);
transmitter_Mcount_baud_divider_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(13),
O => transmitter_Mcount_baud_divider_cy_13_rt_425
);
transmitter_Mcount_baud_divider_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(12),
O => transmitter_Mcount_baud_divider_cy_12_rt_426
);
transmitter_Mcount_baud_divider_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(11),
O => transmitter_Mcount_baud_divider_cy_11_rt_427
);
transmitter_Mcount_baud_divider_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(10),
O => transmitter_Mcount_baud_divider_cy_10_rt_428
);
transmitter_Mcount_baud_divider_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(9),
O => transmitter_Mcount_baud_divider_cy_9_rt_429
);
transmitter_Mcount_baud_divider_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(8),
O => transmitter_Mcount_baud_divider_cy_8_rt_430
);
transmitter_Mcount_baud_divider_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(7),
O => transmitter_Mcount_baud_divider_cy_7_rt_431
);
transmitter_Mcount_baud_divider_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(6),
O => transmitter_Mcount_baud_divider_cy_6_rt_432
);
transmitter_Mcount_baud_divider_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(5),
O => transmitter_Mcount_baud_divider_cy_5_rt_433
);
transmitter_Mcount_baud_divider_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(4),
O => transmitter_Mcount_baud_divider_cy_4_rt_434
);
transmitter_Mcount_baud_divider_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(3),
O => transmitter_Mcount_baud_divider_cy_3_rt_435
);
transmitter_Mcount_baud_divider_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(2),
O => transmitter_Mcount_baud_divider_cy_2_rt_436
);
transmitter_Mcount_baud_divider_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(1),
O => transmitter_Mcount_baud_divider_cy_1_rt_437
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(29),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_rt_438
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(28),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_rt_439
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(27),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_rt_440
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(26),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_rt_441
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(25),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_rt_442
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(24),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_rt_443
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(23),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_rt_444
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(22),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_rt_445
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(21),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_rt_446
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(20),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_rt_447
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(19),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_rt_448
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(18),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_rt_449
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(17),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_rt_450
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(16),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_rt_451
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(15),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_rt_452
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(14),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_rt_453
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(13),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_rt_454
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(12),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_rt_455
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(11),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_rt_456
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(10),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_rt_457
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(9),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_rt_458
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(8),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_rt_459
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(7),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_rt_460
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(6),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_rt_461
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(5),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_rt_462
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(4),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_rt_463
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(3),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_rt_464
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(2),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_rt_465
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(1),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_rt_466
);
Mcount_rom_addr_xor_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(30),
O => Mcount_rom_addr_xor_30_rt_467
);
transmitter_Mcount_baud_divider_xor_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(30),
O => transmitter_Mcount_baud_divider_xor_30_rt_468
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(30),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_30_rt_469
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_SW0 : LUT2
generic map(
INIT => X"7"
)
port map (
I0 => transmitter_baud_clk_edge_1_504,
I1 => transmitter_state_FSM_FFd1_344,
O => N7
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111 : LUT6
generic map(
INIT => X"1555555455555555"
)
port map (
I0 => N7,
I1 => transmitter_bits_transmitted(0),
I2 => transmitter_bits_transmitted(2),
I3 => transmitter_bits_transmitted(1),
I4 => transmitter_state_FSM_FFd2_204,
I5 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_1,
O => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_2_SW0 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => transmitter_bits_transmitted(1),
I1 => transmitter_bits_transmitted(2),
O => N9
);
transmitter_state_FSM_FFd1_In1 : LUT6
generic map(
INIT => X"EEEEEEEEAAAAAA2A"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_1,
I3 => transmitter_bits_transmitted(0),
I4 => N9,
I5 => transmitter_state_FSM_FFd2_204,
O => transmitter_state_FSM_FFd1_In
);
transmitter_GND_5_o_bits_transmitted_30_equal_8_o_30_1_SW0 : LUT3
generic map(
INIT => X"80"
)
port map (
I0 => transmitter_bits_transmitted(0),
I1 => transmitter_bits_transmitted(1),
I2 => transmitter_bits_transmitted(2),
O => N11
);
transmitter_state_FSM_FFd2_In1 : LUT6
generic map(
INIT => X"2EAEAEAE2AAAAAAA"
)
port map (
I0 => transmitter_state_FSM_FFd2_204,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_1,
I4 => N11,
I5 => transmitter_ready_2,
O => transmitter_state_FSM_FFd2_In
);
transmitter_baud_divider_30_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(30),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_30_rstpot_473
);
transmitter_baud_divider_30 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_30_rstpot_473,
Q => transmitter_baud_divider(30)
);
transmitter_baud_divider_29_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(29),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_29_rstpot_474
);
transmitter_baud_divider_29 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_29_rstpot_474,
Q => transmitter_baud_divider(29)
);
transmitter_baud_divider_28_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(28),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_28_rstpot_475
);
transmitter_baud_divider_28 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_28_rstpot_475,
Q => transmitter_baud_divider(28)
);
transmitter_baud_divider_27_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(27),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_27_rstpot_476
);
transmitter_baud_divider_27 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_27_rstpot_476,
Q => transmitter_baud_divider(27)
);
transmitter_baud_divider_26_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(26),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_26_rstpot_477
);
transmitter_baud_divider_26 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_26_rstpot_477,
Q => transmitter_baud_divider(26)
);
transmitter_baud_divider_25_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(25),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_25_rstpot_478
);
transmitter_baud_divider_25 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_25_rstpot_478,
Q => transmitter_baud_divider(25)
);
transmitter_baud_divider_24_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(24),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_24_rstpot_479
);
transmitter_baud_divider_24 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_24_rstpot_479,
Q => transmitter_baud_divider(24)
);
transmitter_baud_divider_23_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(23),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_23_rstpot_480
);
transmitter_baud_divider_23 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_23_rstpot_480,
Q => transmitter_baud_divider(23)
);
transmitter_baud_divider_22_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(22),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_22_rstpot_481
);
transmitter_baud_divider_22 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_22_rstpot_481,
Q => transmitter_baud_divider(22)
);
transmitter_baud_divider_21_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(21),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_21_rstpot_482
);
transmitter_baud_divider_21 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_21_rstpot_482,
Q => transmitter_baud_divider(21)
);
transmitter_baud_divider_20_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(20),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_20_rstpot_483
);
transmitter_baud_divider_20 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_20_rstpot_483,
Q => transmitter_baud_divider(20)
);
transmitter_baud_divider_19_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(19),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_19_rstpot_484
);
transmitter_baud_divider_19 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_19_rstpot_484,
Q => transmitter_baud_divider(19)
);
transmitter_baud_divider_18_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(18),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_18_rstpot_485
);
transmitter_baud_divider_18 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_18_rstpot_485,
Q => transmitter_baud_divider(18)
);
transmitter_baud_divider_17_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(17),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_17_rstpot_486
);
transmitter_baud_divider_17 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_17_rstpot_486,
Q => transmitter_baud_divider(17)
);
transmitter_baud_divider_16_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(16),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_16_rstpot_487
);
transmitter_baud_divider_16 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_16_rstpot_487,
Q => transmitter_baud_divider(16)
);
transmitter_baud_divider_15_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(15),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_15_rstpot_488
);
transmitter_baud_divider_15 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_15_rstpot_488,
Q => transmitter_baud_divider(15)
);
transmitter_baud_divider_14_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(14),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_14_rstpot_489
);
transmitter_baud_divider_14 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_14_rstpot_489,
Q => transmitter_baud_divider(14)
);
transmitter_baud_divider_13_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(13),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_13_rstpot_490
);
transmitter_baud_divider_13 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_13_rstpot_490,
Q => transmitter_baud_divider(13)
);
transmitter_baud_divider_12_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(12),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_12_rstpot_491
);
transmitter_baud_divider_12 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_12_rstpot_491,
Q => transmitter_baud_divider(12)
);
transmitter_baud_divider_11_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(11),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_11_rstpot_492
);
transmitter_baud_divider_11 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_11_rstpot_492,
Q => transmitter_baud_divider(11)
);
transmitter_baud_divider_10_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(10),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_10_rstpot_493
);
transmitter_baud_divider_10 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_10_rstpot_493,
Q => transmitter_baud_divider(10)
);
transmitter_baud_divider_9_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(9),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_9_rstpot_494
);
transmitter_baud_divider_9 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_9_rstpot_494,
Q => transmitter_baud_divider(9)
);
transmitter_baud_divider_8_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(8),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_8_rstpot_495
);
transmitter_baud_divider_8 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_8_rstpot_495,
Q => transmitter_baud_divider(8)
);
transmitter_baud_divider_7_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(7),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_7_rstpot_496
);
transmitter_baud_divider_7 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_7_rstpot_496,
Q => transmitter_baud_divider(7)
);
transmitter_baud_divider_6_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(6),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_6_rstpot_497
);
transmitter_baud_divider_6 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_6_rstpot_497,
Q => transmitter_baud_divider(6)
);
transmitter_baud_divider_5_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(5),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_5_rstpot_498
);
transmitter_baud_divider_5 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_5_rstpot_498,
Q => transmitter_baud_divider(5)
);
transmitter_baud_divider_4_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(4),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_4_rstpot_499
);
transmitter_baud_divider_4 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_4_rstpot_499,
Q => transmitter_baud_divider(4)
);
transmitter_baud_divider_3_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(3),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_3_rstpot_500
);
transmitter_baud_divider_3 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_3_rstpot_500,
Q => transmitter_baud_divider(3)
);
transmitter_baud_divider_2_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(2),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_2_rstpot_501
);
transmitter_baud_divider_2 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_2_rstpot_501,
Q => transmitter_baud_divider(2)
);
transmitter_baud_divider_1_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(1),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_1_rstpot_502
);
transmitter_baud_divider_1 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_1_rstpot_502,
Q => transmitter_baud_divider(1)
);
transmitter_baud_divider_0_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(0),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_0_rstpot_503
);
transmitter_baud_divider_0 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_0_rstpot_503,
Q => transmitter_baud_divider(0)
);
transmitter_baud_clk_edge_1 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_GND_5_o_baud_divider_30_equal_4_o,
Q => transmitter_baud_clk_edge_1_504
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_1 : LUT6
generic map(
INIT => X"1555555455555555"
)
port map (
I0 => N7,
I1 => transmitter_bits_transmitted(0),
I2 => transmitter_bits_transmitted(2),
I3 => transmitter_bits_transmitted(1),
I4 => transmitter_state_FSM_FFd2_204,
I5 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_1,
O => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_1 : LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => transmitter_baud_divider(10),
I1 => transmitter_baud_divider(12),
I2 => transmitter_baud_divider(4),
I3 => transmitter_baud_divider(6),
I4 => N5,
I5 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_1_108,
O => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506
);
clk_BUFGP : BUFGP
port map (
I => clk,
O => clk_BUFGP_0
);
Mcount_rom_addr_lut_0_INV_0 : INV
port map (
I => rom_addr(0),
O => Mcount_rom_addr_lut(0)
);
transmitter_Mcount_baud_divider_lut_0_INV_0 : INV
port map (
I => transmitter_baud_divider(0),
O => transmitter_Mcount_baud_divider_lut(0)
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_lut_0_INV_0 : INV
port map (
I => transmitter_bits_transmitted(0),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_lut_0_Q
);
end Structure;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1745.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p05n03i01745ent IS
END c09s05b00x00p05n03i01745ent;
ARCHITECTURE c09s05b00x00p05n03i01745arch OF c09s05b00x00p05n03i01745ent IS
signal A : bit := '0';
BEGIN
A <= transport '1' after 10 ns;
TESTING: PROCESS(A)
variable NEWTIME : TIME;
BEGIN
NEWTIME := now;
if ( now > 1 ns ) then
assert NOT( A= '1' and NEWTIME = 10 ns )
report "***PASSED TEST: c09s05b00x00p05n03i01745"
severity NOTE;
assert ( A= '1' and NEWTIME = 10 ns )
report "***FAILED TEST: c09s05b00x00p05n03i01745 - Transport specifies the transport delay."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s05b00x00p05n03i01745arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1745.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p05n03i01745ent IS
END c09s05b00x00p05n03i01745ent;
ARCHITECTURE c09s05b00x00p05n03i01745arch OF c09s05b00x00p05n03i01745ent IS
signal A : bit := '0';
BEGIN
A <= transport '1' after 10 ns;
TESTING: PROCESS(A)
variable NEWTIME : TIME;
BEGIN
NEWTIME := now;
if ( now > 1 ns ) then
assert NOT( A= '1' and NEWTIME = 10 ns )
report "***PASSED TEST: c09s05b00x00p05n03i01745"
severity NOTE;
assert ( A= '1' and NEWTIME = 10 ns )
report "***FAILED TEST: c09s05b00x00p05n03i01745 - Transport specifies the transport delay."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s05b00x00p05n03i01745arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1745.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p05n03i01745ent IS
END c09s05b00x00p05n03i01745ent;
ARCHITECTURE c09s05b00x00p05n03i01745arch OF c09s05b00x00p05n03i01745ent IS
signal A : bit := '0';
BEGIN
A <= transport '1' after 10 ns;
TESTING: PROCESS(A)
variable NEWTIME : TIME;
BEGIN
NEWTIME := now;
if ( now > 1 ns ) then
assert NOT( A= '1' and NEWTIME = 10 ns )
report "***PASSED TEST: c09s05b00x00p05n03i01745"
severity NOTE;
assert ( A= '1' and NEWTIME = 10 ns )
report "***FAILED TEST: c09s05b00x00p05n03i01745 - Transport specifies the transport delay."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s05b00x00p05n03i01745arch;
|
library verilog;
use verilog.vl_types.all;
entity maquina is
port(
SW : in vl_logic_vector(4 downto 0);
LEDG : out vl_logic_vector(0 downto 0);
LEDR : out vl_logic_vector(0 downto 0);
HEX0 : out vl_logic_vector(6 downto 0);
CLK : in vl_logic
);
end maquina;
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Creates a signal that toggles at every rising edge of an input signal. This
-- can be used before passing a signal (e.g. of short pulses) to a different
-- clock domain. A dual edge detector can be used in the destination clock domain
-- to reconstruct the signal.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Toggler is
port
(
-- The system clock.
clk: in std_logic;
-- The signal to create a toggled signal from.
sigin: in std_logic;
-- The created toggled signal.
toggled_sigout: out std_logic
);
end entity;
architecture stdarch of Toggler is
type reg_type is record
sigout: std_logic;
end record;
signal state, next_state: reg_type := (sigout => '0');
signal sigin_edge: std_logic := '0';
begin
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
detect_edges_of_sigin: entity work.EdgeDetector
port map
(
clk => clk,
sigin => sigin,
edge => sigin_edge
);
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, sigin_edge) is
begin
-- Defaults.
next_state <= state;
if (sigin_edge = '1') then
next_state.sigout <= not state.sigout;
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
toggled_sigout <= state.sigout;
end architecture;
|
-- This is the top-level of the fp68030 design, instantiating
-- all top IP blocks, connecting things to external FPGA pins
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <ccl@xunit.de>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file udp_decoder.vhd
--! @brief decodes the received udp packets
--! @author Benjamin Bässler
--! @email ccl@xunit.de
--! @date 2013-11-25
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity udp_decoder is
generic(
G_MAX_DATA_SIZE : natural := 128
);
port (
-- System signals
------------------
rst_in : in std_logic; -- asynchronous reset
rx_clk_in : in std_logic;
-- UDP RX signals
-----------------
udp_rx_start_in : in std_logic;
udp_rx_in : in udp_rx_type;
ip_rx_hdr_in : in ipv4_rx_header_type;
-- Decoder outputs
-- read/write command
dec_valid_out : out std_logic;
write_out : out std_logic;
type_out : out unsigned(15 downto 0);
id_out : out unsigned(15 downto 0);
length_out : out unsigned(15 downto 0);
data_out : out unsigned(G_MAX_DATA_SIZE - 1 downto 0);
header_error_out : out std_logic
);
end udp_decoder;
architecture udp_decoder_arc of udp_decoder is
CONSTANT C_UDP_PORT : unsigned(15 downto 0) := x"D820"; --55328
type T_STATE is (IDLE, DECODING, VALID, INVALID, IDLE_WAIT);
signal rx_state_s : T_STATE;
-- counts the data bytes of udp packet
signal udp_cnt_s : unsigned(15 downto 0);
signal udp_data_s : unsigned(G_MAX_DATA_SIZE - 1 downto 0);
signal write_s : std_logic;
signal type_s : unsigned(15 downto 0);
signal id_s : unsigned(15 downto 0);
signal length_s : unsigned(15 downto 0);
begin
--! @brief RX state process
--! STATES:
--! IDLE wait for new UDP Data (rising udp_rx.hdr.is_valid = 1)
--! DECODING decode receiving data
--! VALID received data valid and write to output
--! IDLE_WAIT wait for udp_rx.hdr.is_valid = 0
--! INVALID data_length of UDP to short/big wrong port or broadcast
--!
p_rx_state : process (rx_clk_in, rst_in) is
begin
if rst_in = '1' then
--reset
rx_state_s <= IDLE;
elsif rising_edge(rx_clk_in) then
case rx_state_s is
when IDLE =>
if udp_rx_in.hdr.is_valid = '1' then
-- UDP DATA length needs to be at least 6 bytes
-- only listen on the C_UDP_PORT
-- Broadcasts should not be interpreted
if unsigned(udp_rx_in.hdr.data_length) < 6 or
unsigned(udp_rx_in.hdr.data_length) > G_MAX_DATA_SIZE or
ip_rx_hdr_in.is_broadcast = '1' or
unsigned(udp_rx_in.hdr.dst_port) /= C_UDP_PORT
then
rx_state_s <= INVALID;
else
rx_state_s <= DECODING;
end if;
end if;
when DECODING =>
if udp_rx_in.data.data_in_last = '1' then
rx_state_s <= VALID;
end if;
when VALID =>
rx_state_s <= IDLE_WAIT;
when IDLE_WAIT =>
if udp_rx_in.hdr.is_valid = '0' then
rx_state_s <= IDLE;
end if;
when INVALID =>
rx_state_s <= IDLE_WAIT;
end case;
end if; --clk
end process p_rx_state;
--! @brief store UDP Packet
p_rx_udp : process (rx_clk_in, rst_in) is
begin
if rst_in = '1' then
udp_cnt_s <= (others => '0');
dec_valid_out <= '0';
header_error_out <= '0';
write_out <= '0';
elsif rising_edge(rx_clk_in) then
-- default output
dec_valid_out <= '0';
if rx_state_s = IDLE then
udp_cnt_s <= (others => '0');
elsif rx_state_s = DECODING then
--only read data if valid
-- and prevent storing invalid data
if udp_rx_in.data.data_in_valid = '1' and
udp_cnt_s <= unsigned(udp_rx_in.hdr.data_length) then
-- Packet format:
-- 0 7 15 16 23 31 32 39 47 48
-- +--------------+--------------+--------------+------...-------
-- | type | id | length | data |
-- +--------------+--------------+--------------+------...-------
case udp_cnt_s is
when x"0000" =>
write_s <= udp_rx_in.data.data_in(7);
type_s(15 downto 8) <= "0" & unsigned(udp_rx_in.data.data_in(6 downto 0));
when x"0001" =>
type_s(7 downto 0) <= unsigned(udp_rx_in.data.data_in);
when x"0002" =>
id_s(15 downto 8) <= unsigned(udp_rx_in.data.data_in);
when x"0003" =>
id_s(7 downto 0) <= unsigned(udp_rx_in.data.data_in);
when x"0004" =>
length_s(15 downto 8) <= unsigned(udp_rx_in.data.data_in);
when x"0005" =>
length_s(7 downto 0) <= unsigned(udp_rx_in.data.data_in);
when others =>
--store data part
udp_data_s(G_MAX_DATA_SIZE-1 - to_integer(udp_cnt_s-6)*8 downto
G_MAX_DATA_SIZE-1 - to_integer(udp_cnt_s-6)*8 - 7)
<= unsigned(udp_rx_in.data.data_in);
end case;
--increment data counter
udp_cnt_s <= udp_cnt_s + 1;
end if; -- udp valid
elsif rx_state_s = VALID then
write_out <= write_s;
type_out <= type_s;
id_out <= id_s;
length_out <= length_s;
data_out <= udp_data_s;
dec_valid_out <= '1';
if udp_cnt_s < 6 then
header_error_out <= '1';
else
header_error_out <= '0';
end if;
end if; -- state
end if; --clk
end process p_rx_udp;
end architecture udp_decoder_arc;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:50:17 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/system_vga_hessian_0_0_stub.vhdl
-- Design : system_vga_hessian_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_hessian_0_0 is
Port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end system_vga_hessian_0_0;
architecture stub of system_vga_hessian_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_x16,active,rst,x_addr[9:0],y_addr[9:0],g_in[7:0],hessian_out[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_hessian,Vivado 2016.4";
begin
end;
|
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
architecture behavioral of dynshreg_i_f is
constant USE_INFERRED : boolean := true;
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
begin
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
-------------------------------------------------------------------------------
-- uartlite_tx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_tx.vhd
-- Version: v2.0
-- Description: UART Lite Transmit Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.UNSIGNED;
use IEEE.numeric_std.to_unsigned;
use IEEE.numeric_std."-";
library lib_srl_fifo_v1_0_2;
-- dynshreg_i_f refered from proc_common_v4_0_20_a
library axi_uartlite_v2_0_15;
-- uartlite_core refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.all;
-- srl_fifo_f refered from proc_common_v4_0_20_a
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- TX -- Transmit Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Write_TX_FIFO -- Write transmit FIFO
-- Reset_TX_FIFO -- Reset transmit FIFO
-- TX_Data -- Transmit data input
-- TX_Buffer_Full -- Transmit buffer full
-- TX_Buffer_Empty -- Transmit buffer empty
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_tx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
TX : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_DATA_BITS-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic
);
end entity uartlite_tx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_tx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
-------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------
constant MUX_SEL_INIT : std_logic_vector(0 to 2) :=
std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
-------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------
signal parity : std_logic;
signal tx_Run1 : std_logic;
signal select_Parity : std_logic;
signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
signal div16 : std_logic;
signal tx_Data_Enable : std_logic;
signal tx_Start : std_logic;
signal tx_DataBits : std_logic;
signal tx_Run : std_logic;
signal mux_sel : std_logic_vector(0 to 2);
signal mux_sel_is_zero : std_logic;
signal mux_01 : std_logic;
signal mux_23 : std_logic;
signal mux_45 : std_logic;
signal mux_67 : std_logic;
signal mux_0123 : std_logic;
signal mux_4567 : std_logic;
signal mux_Out : std_logic;
signal serial_Data : std_logic;
signal fifo_Read : std_logic;
signal fifo_Data_Present : std_logic := '0';
signal fifo_Data_Empty : std_logic;
signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1);
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal tx_buffer_full_i : std_logic;
signal TX_FIFO_Reset : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
--MID_START_BIT_SRL16_I : Shift register is used to generate div16 that
-- gets shifted for 16 times(as Addr = 15) when
-- EN_16x_Baud is high.
---------------------------------------------------------------------------
MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0_15.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_INIT_VALUE => X"8000",
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => div16,
Dout(0) => div16
);
------------------------------------------------------------------------
-- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and
-- EN_16x_Baud is 1. It will deasserted in the
-- next clock cycle.
------------------------------------------------------------------------
TX_DATA_ENABLE_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Data_Enable <= '0';
else
if (tx_Data_Enable = '1') then
tx_Data_Enable <= '0';
elsif (EN_16x_Baud = '1') then
tx_Data_Enable <= div16;
end if;
end if;
end if;
end process TX_DATA_ENABLE_DFF;
------------------------------------------------------------------------
-- TX_START_DFF : tx_start is '1' for the start bit in a transmission
------------------------------------------------------------------------
TX_START_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Start <= '0';
else
tx_Start <= (not(tx_Run) and (tx_Start or
(fifo_Data_Present and tx_Data_Enable)));
end if;
end if;
end process TX_START_DFF;
--------------------------------------------------------------------------
-- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission
--------------------------------------------------------------------------
TX_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_DataBits <= '0';
else
tx_DataBits <= (not(fifo_Read) and (tx_DataBits or
(tx_Start and tx_Data_Enable)));
end if;
end if;
end process TX_DATA_DFF;
-------------------------------------------------------------------------
-- COUNTER : If mux_sel is zero then reload with the init value else if
-- tx_DataBits = '1', decrement
-------------------------------------------------------------------------
COUNTER : process (Clk) is
begin -- process Mux_Addr_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1,
mux_sel'length));
elsif (tx_Data_Enable = '1') then
if (mux_sel_is_zero = '1') then
mux_sel <= MUX_SEL_INIT;
elsif (tx_DataBits = '1') then
mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1);
end if;
end if;
end if;
end process COUNTER;
------------------------------------------------------------------------
-- Detecting when mux_sel is zero, i.e. all data bits are transfered
------------------------------------------------------------------------
mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
--------------------------------------------------------------------------
-- FIFO_READ_DFF : Read out the next data from the transmit fifo when the
-- data has been transmitted
--------------------------------------------------------------------------
FIFO_READ_DFF : process (Clk) is
begin -- process FIFO_Read_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Read <= '0';
else
fifo_Read <= tx_Data_Enable and mux_sel_is_zero;
end if;
end if;
end process FIFO_READ_DFF;
--------------------------------------------------------------------------
-- Select which bit within the data word to transmit
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- PARITY_BIT_INSERTION : Need special treatment for inserting the parity
-- bit because of parity generation
--------------------------------------------------------------------------
data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2);
data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else
fifo_DOut(C_DATA_BITS-1);
mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else
data_to_transfer(0);
mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else
data_to_transfer(2);
--------------------------------------------------------------------------
-- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5
--------------------------------------------------------------------------
DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate
mux_45 <= data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_5;
--------------------------------------------------------------------------
-- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6
--------------------------------------------------------------------------
DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_6;
--------------------------------------------------------------------------
-- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7
--------------------------------------------------------------------------
DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(6);
end generate DATA_BITS_IS_7;
--------------------------------------------------------------------------
-- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8
--------------------------------------------------------------------------
DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else
data_to_transfer(6);
end generate DATA_BITS_IS_8;
mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01;
mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45;
mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123;
--------------------------------------------------------------------------
-- SERIAL_DATA_DFF : Register the mux_Out
--------------------------------------------------------------------------
SERIAL_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
serial_Data <= '0';
else
serial_Data <= mux_Out;
end if;
end if;
end process SERIAL_DATA_DFF;
--------------------------------------------------------------------------
-- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit
-- Force a '1' when tx_run is '0', Idle
-- otherwise put out the serial_data
--------------------------------------------------------------------------
SERIAL_OUT_DFF : process (Clk) is
begin -- process Serial_Out_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
TX <= '1';
else
TX <= (not(tx_Run) or serial_Data) and (not(tx_Start));
end if;
end if;
end process SERIAL_OUT_DFF;
--------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
--------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (tx_Start = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (tx_Data_Enable = '1') then
parity <= parity xor serial_Data;
end if;
end if;
end process PARITY_DFF;
TX_RUN1_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Run1 <= '0';
elsif (tx_Data_Enable = '1') then
tx_Run1 <= tx_DataBits;
end if;
end if;
end process TX_RUN1_DFF;
tx_Run <= tx_Run1 or tx_DataBits;
SELECT_PARITY_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
select_Parity <= '0';
elsif (tx_Data_Enable = '1') then
select_Parity <= mux_sel_is_zero;
end if;
end if;
end process SELECT_PARITY_DFF;
end generate USING_PARITY;
--------------------------------------------------------------------------
-- NO_PARITY : When C_USE_PARITY = 0 select parity as '0'
--------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
tx_Run <= tx_DataBits;
select_Parity <= '0';
end generate NO_PARITY;
--------------------------------------------------------------------------
-- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO
--------------------------------------------------------------------------
fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i);
--------------------------------------------------------------------------
-- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO
--------------------------------------------------------------------------
fifo_rd <= fifo_Read and (not fifo_Data_Empty);
--------------------------------------------------------------------------
-- Reset TX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
TX_FIFO_Reset <= Reset_TX_FIFO or Reset;
--------------------------------------------------------------------------
-- SRL_FIFO_I : Transmit FIFO Interface
--------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => TX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => TX_Data,
FIFO_Read => fifo_rd,
Data_Out => fifo_DOut,
FIFO_Full => tx_buffer_full_i,
FIFO_Empty => fifo_Data_Empty
);
TX_Buffer_Full <= tx_buffer_full_i;
TX_Buffer_Empty <= fifo_Data_Empty;
fifo_Data_Present <= not fifo_Data_Empty;
end architecture RTL;
-------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_rx.vhd
-- Version: v2.0
-- Description: UART Lite Receive Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
-- dynshreg_i_f refered from proc_common_v4_0_2
-- srl_fifo_f refered from proc_common_v4_0_2
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_uartlite_v2_0_15;
-- uartlite_core refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
--
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- RX -- Receive Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Read_RX_FIFO -- Read receive FIFO
-- Reset_RX_FIFO -- Reset receive FIFO
-- RX_Data -- Receive data output
-- RX_Data_Present -- Receive data present
-- RX_Buffer_Full -- Receive buffer full
-- RX_Frame_Error -- Receive frame error
-- RX_Overrun_Error -- Receive overrun error
-- RX_Parity_Error -- Receive parity error
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_rx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
RX : in std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_DATA_BITS-1);
RX_Data_Present : out std_logic;
RX_Buffer_Full : out std_logic;
RX_Frame_Error : out std_logic;
RX_Overrun_Error : out std_logic;
RX_Parity_Error : out std_logic
);
end entity uartlite_rx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_rx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant SERIAL_TO_PAR_LENGTH : integer :=
C_DATA_BITS + C_USE_PARITY;
constant STOP_BIT_POS : integer := SERIAL_TO_PAR_LENGTH;
constant DATA_LSB_POS : integer := SERIAL_TO_PAR_LENGTH;
constant CALC_PAR_POS : integer := SERIAL_TO_PAR_LENGTH;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
signal start_Edge_Detected : boolean;
signal start_Edge_Detected_Bit : std_logic;
signal running : boolean;
signal recycle : std_logic;
signal sample_Point : std_logic;
signal stop_Bit_Position : std_logic;
signal fifo_Write : std_logic;
signal fifo_din : std_logic_vector(0 to SERIAL_TO_PAR_LENGTH);
signal serial_to_Par : std_logic_vector(1 to SERIAL_TO_PAR_LENGTH);
signal calc_parity : std_logic;
signal parity : std_logic;
signal RX_Buffer_Full_I : std_logic;
signal RX_D1 : std_logic;
signal RX_D2 : std_logic;
signal rx_1 : std_logic;
signal rx_2 : std_logic;
signal rx_3 : std_logic;
signal rx_4 : std_logic;
signal rx_5 : std_logic;
signal rx_6 : std_logic;
signal rx_7 : std_logic;
signal rx_8 : std_logic;
signal rx_9 : std_logic;
signal rx_Data_Empty : std_logic := '0';
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal RX_FIFO_Reset : std_logic;
signal valid_rx : std_logic;
signal valid_start : std_logic;
signal frame_err_ocrd : std_logic;
signal frame_err : std_logic;
begin -- architecture RTL
---------------------------------------------------------------------------
-- RX_SAMPLING : Double sample RX to avoid meta-stability
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => RX,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => RX_D2,
scndry_vect_out => open
);
-- RX_SAMPLING: process (Clk) is
-- begin -- process RX_Sampling
-- if Clk'event and Clk = '1' then -- rising clock edge
-- if Reset = '1' then -- synchronous reset (active high)
-- RX_D1 <= '1';
-- RX_D2 <= '1';
-- else
-- RX_D1 <= RX;
-- RX_D2 <= RX_D1;
-- end if;
-- end if;
-- end process RX_SAMPLING;
-------------------------------------------------------------------------------
-- Detect a falling edge on RX and start a new reception if idle
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- detect the start of the frame
---------------------------------------------------------------------------
RX_DFFS : process (Clk) is
begin -- process Prev_RX_DFFS
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
rx_1 <= '0';
rx_2 <= '0';
rx_3 <= '0';
rx_4 <= '0';
rx_5 <= '0';
rx_6 <= '0';
rx_7 <= '0';
rx_8 <= '0';
rx_9 <= '0';
elsif (EN_16x_Baud = '1') then
rx_1 <= RX_D2;
rx_2 <= rx_1;
rx_3 <= rx_2;
rx_4 <= rx_3;
rx_5 <= rx_4;
rx_6 <= rx_5;
rx_7 <= rx_6;
rx_8 <= rx_7;
rx_9 <= rx_8;
end if;
end if;
end process RX_DFFS;
---------------------------------------------------------------------------
-- Start bit valid when RX is continuously low for atleast 8 samples
---------------------------------------------------------------------------
valid_start <= rx_8 or rx_7 or rx_6 or rx_5 or
rx_4 or rx_3 or rx_2 or rx_1;
---------------------------------------------------------------------------
-- START_EDGE_DFF : Start a new reception if idle
---------------------------------------------------------------------------
START_EDGE_DFF : process (Clk) is
begin -- process Start_Edge_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
start_Edge_Detected <= false;
elsif (EN_16x_Baud = '1') then
start_Edge_Detected <= ((not running) and
(frame_err_ocrd = '0') and
(rx_9 = '1') and
(valid_start = '0'));
end if;
end if;
end process START_EDGE_DFF;
---------------------------------------------------------------------------
-- FRAME_ERR_CAPTURE : frame_err_ocrd is '1' when a frame error is occured
-- and deasserted when the next low to high on RX
---------------------------------------------------------------------------
FRAME_ERR_CAPTURE : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
frame_err_ocrd <= '0';
elsif (frame_err = '1') then
frame_err_ocrd <= '1';
elsif (RX_D2 = '1') then
frame_err_ocrd <= '0';
end if;
end if;
end process FRAME_ERR_CAPTURE;
---------------------------------------------------------------------------
-- VALID_XFER : valid_rx is '1' when a valid start edge detected
---------------------------------------------------------------------------
VALID_XFER : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
valid_rx <= '0';
elsif (start_Edge_Detected = true) then
valid_rx <= '1';
elsif (fifo_Write = '1') then
valid_rx <= '0';
end if;
end if;
end process VALID_XFER;
---------------------------------------------------------------------------
-- RUNNING_DFF : Running is '1' during a reception
---------------------------------------------------------------------------
RUNNING_DFF : process (Clk) is
begin -- process Running_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
running <= false;
elsif (EN_16x_Baud = '1') then
if (start_Edge_Detected) then
running <= true;
elsif ((sample_Point = '1') and (stop_Bit_Position = '1')) then
running <= false;
end if;
end if;
end if;
end process RUNNING_DFF;
---------------------------------------------------------------------------
-- Boolean to std logic conversion of start edge
---------------------------------------------------------------------------
start_Edge_Detected_Bit <= '1' when start_Edge_Detected else '0';
---------------------------------------------------------------------------
-- After the start edge is detected, generate recycle to generate sample
-- point
---------------------------------------------------------------------------
recycle <= (valid_rx and (not stop_Bit_Position) and
(start_Edge_Detected_Bit or sample_Point));
-------------------------------------------------------------------------
-- DELAY_16_I : Keep regenerating new values into the 16 clock delay,
-- Starting with the first start_Edge_Detected_Bit and for every new
-- sample_points until stop_Bit_Position is reached
-------------------------------------------------------------------------
DELAY_16_I : entity axi_uartlite_v2_0_15.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => recycle,
Dout(0) => sample_Point
);
---------------------------------------------------------------------------
-- STOP_BIT_HANDLER : Detect when the stop bit is received
---------------------------------------------------------------------------
STOP_BIT_HANDLER : process (Clk) is
begin -- process Stop_Bit_Handler
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
stop_Bit_Position <= '0';
elsif (EN_16x_Baud = '1') then
if (stop_Bit_Position = '0') then
-- Start bit has reached the end of the shift register
-- (Stop bit position)
stop_Bit_Position <= sample_Point and
fifo_din(STOP_BIT_POS);
elsif (sample_Point = '1') then
-- if stop_Bit_Position is 1 clear it at next sample_Point
stop_Bit_Position <= '0';
end if;
end if;
end if;
end process STOP_BIT_HANDLER;
USING_PARITY_NO : if (C_USE_PARITY = 0) generate
RX_Parity_Error <= '0' ;
end generate USING_PARITY_NO;
---------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
---------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1' or start_Edge_Detected_Bit = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (EN_16x_Baud = '1') then
parity <= calc_parity;
end if;
end if;
end process PARITY_DFF;
calc_parity <= parity when (stop_Bit_Position or
(not sample_Point)) = '1'
else parity xor RX_D2;
RX_Parity_Error <= (EN_16x_Baud and sample_Point) and
(fifo_din(CALC_PAR_POS)) and not stop_Bit_Position
when running and (RX_D2 /= parity) else '0';
end generate USING_PARITY;
fifo_din(0) <= RX_D2 and not Reset;
---------------------------------------------------------------------------
-- SERIAL_TO_PARALLEL : Serial to parrallel conversion data part
---------------------------------------------------------------------------
SERIAL_TO_PARALLEL : for i in 1 to serial_to_Par'length generate
serial_to_Par(i) <= fifo_din(i) when (stop_Bit_Position or
not sample_Point) = '1'
else fifo_din(i-1);
BIT_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
fifo_din(i) <= '0'; -- Bit STOP_BIT_POS resets to '0';
else -- others to '1'
if (start_Edge_Detected_Bit = '1') then
fifo_din(i) <= bo2sl(i=1); -- Bit 1 resets to '1';
-- others to '0'
elsif (EN_16x_Baud = '1') then
fifo_din(i) <= serial_to_Par(i);
end if;
end if;
end if;
end process BIT_I;
end generate SERIAL_TO_PARALLEL;
--------------------------------------------------------------------------
-- FIFO_WRITE_DFF : Write in the received word when the stop_bit has been
-- received and it is a '1'
--------------------------------------------------------------------------
FIFO_WRITE_DFF : process (Clk) is
begin -- process FIFO_Write_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Write <= '0';
else
fifo_Write <= stop_Bit_Position and RX_D2 and sample_Point
and EN_16x_Baud;
end if;
end if;
end process FIFO_WRITE_DFF;
frame_err <= stop_Bit_Position and sample_Point and EN_16x_Baud
and not RX_D2;
RX_Frame_Error <= frame_err;
--------------------------------------------------------------------------
-- Write RX FIFO when FIFO is not full when valid data is reveived
--------------------------------------------------------------------------
fifo_wr <= fifo_Write and (not RX_Buffer_Full_I) and valid_rx;
--------------------------------------------------------------------------
-- Read RX FIFO when FIFO is not empty when AXI reads data from RX FIFO
--------------------------------------------------------------------------
fifo_rd <= Read_RX_FIFO and (not rx_Data_Empty);
--------------------------------------------------------------------------
-- Reset RX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
RX_FIFO_Reset <= Reset_RX_FIFO or Reset;
---------------------------------------------------------------------------
-- SRL_FIFO_I : Receive FIFO Interface
---------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => RX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => fifo_din((DATA_LSB_POS-C_DATA_BITS + 1) to DATA_LSB_POS),
FIFO_Read => fifo_rd,
Data_Out => RX_Data,
FIFO_Full => RX_Buffer_Full_I,
FIFO_Empty => rx_Data_Empty,
Addr => open
);
RX_Data_Present <= not rx_Data_Empty;
RX_Overrun_Error <= RX_Buffer_Full_I and fifo_Write; -- Note that if
-- the RX FIFO is read on the same cycle as it is written while full,
-- there is no loss of data. However this case is not optimized and
-- is also reported as an overrun.
RX_Buffer_Full <= RX_Buffer_Full_I;
end architecture RTL;
-------------------------------------------------------------------------------
-- baudrate - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: baudrate.vhd
-- Version: v2.0
-- Description: Baud rate enable logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_RATIO -- The ratio between clk and the asked baudrate
-- multiplied with 16
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Reset -- Reset signal
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity baudrate is
generic
(
C_RATIO : integer := 48 -- The ratio between clk and the asked
-- baudrate multiplied with 16
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : out std_logic
);
end entity baudrate;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of baudrate is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
signal count : natural range 0 to C_RATIO-1;
begin -- architecture VHDL_RTL
---------------------------------------------------------------------------
-- COUNTER_PROCESS : Down counter for generating EN_16x_Baud signal
---------------------------------------------------------------------------
COUNTER_PROCESS : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
count <= 0;
EN_16x_Baud <= '0';
else
if (count = 0) then
count <= C_RATIO-1;
EN_16x_Baud <= '1';
else
count <= count - 1;
EN_16x_Baud <= '0';
end if;
end if;
end if;
end process COUNTER_PROCESS;
end architecture RTL;
-------------------------------------------------------------------------------
-- uartlite_core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_core.vhd
-- Version: v2.0
-- Description: UART Lite core for implementing UART logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_uartlite_v2_0_15;
-- baudrate refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.baudrate;
-- uartlite_rx refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.uartlite_rx;
-- uartlite_tx refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.uartlite_tx;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- Slave attachment interface
-- bus2ip_data -- bus2ip data signal
-- bus2ip_rdce -- bus2ip read CE
-- bus2ip_wrce -- bus2ip write CE
-- ip2bus_rdack -- ip2bus read acknowledgement
-- ip2bus_wrack -- ip2bus write acknowledgement
-- ip2bus_error -- ip2bus error
-- SIn_DBus -- ip2bus data
-- UART Lite interface
-- RX -- Receive Data
-- TX -- Transmit Data
-- Interrupt -- UART Interrupt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_core is
generic
(
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
-- IPIF signals
bus2ip_data : in std_logic_vector(0 to 7);
bus2ip_rdce : in std_logic_vector(0 to 3);
bus2ip_wrce : in std_logic_vector(0 to 3);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
SIn_DBus : out std_logic_vector(0 to 7);
-- UART signals
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end entity uartlite_core;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- function declarations
---------------------------------------------------------------------------
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
C_BAUDRATE : integer ) return Integer is
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
constant REMAINDER : integer :=
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
constant RATIO : integer :=
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
begin
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
return (RATIO + 1);
else
return RATIO;
end if;
end function CALC_RATIO;
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Read Only
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- bit 2 Overrun Error
-- bit 1 Frame Error
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
-- Write Only
-- Below mentioned bits belong to Control Register and are declared as
-- signals below
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4-5 Dont'Care
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal en_16x_Baud : std_logic;
signal enable_interrupts : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal rx_Frame_Error : std_logic;
signal rx_Overrun_Error : std_logic;
signal rx_Parity_Error : std_logic;
signal clr_Status : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal rx_Data_Present_Pre : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
-- Generating the acknowledgement and error signals
---------------------------------------------------------------------------
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
-------------------------------------------------------------------------
-- BAUD_RATE_I : Instansiating the baudrate module
-------------------------------------------------------------------------
BAUD_RATE_I : entity axi_uartlite_v2_0_15.baudrate
generic map
(
C_RATIO => RATIO
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud
);
-------------------------------------------------------------------------
-- Status register handling
-------------------------------------------------------------------------
status_reg(7) <= rx_Data_Present;
status_reg(6) <= rx_Buffer_Full;
status_reg(5) <= tx_Buffer_Empty;
status_reg(4) <= tx_Buffer_Full;
status_reg(3) <= enable_interrupts;
-------------------------------------------------------------------------
-- CLEAR_STATUS_REG : Process to clear status register
-------------------------------------------------------------------------
CLEAR_STATUS_REG : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then
if Reset = '1' then
clr_Status <= '0';
else
clr_Status <= bus2ip_rdce(2);
end if;
end if;
end process CLEAR_STATUS_REG;
-------------------------------------------------------------------------
-- Process to register rx_Overrun_Error
-------------------------------------------------------------------------
RX_OVERRUN_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Reset = '1') or (clr_Status = '1')) then
status_reg(2) <= '0';
elsif (rx_Overrun_Error = '1') then
status_reg(2) <= '1';
end if;
end if;
end process RX_OVERRUN_ERROR_DFF;
-------------------------------------------------------------------------
-- Process to register rx_Frame_Error
-------------------------------------------------------------------------
RX_FRAME_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(1) <= '0';
else
if (clr_Status = '1') then
status_reg(1) <= '0';
elsif (rx_Frame_Error = '1') then
status_reg(1) <= '1';
end if;
end if;
end if;
end process RX_FRAME_ERROR_DFF;
-------------------------------------------------------------------------
-- If C_USE_PARITY = 1, register rx_Parity_Error
-------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
RX_PARITY_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(0) <= '0';
else
if (clr_Status = '1') then
status_reg(0) <= '0';
elsif (rx_Parity_Error = '1') then
status_reg(0) <= '1';
end if;
end if;
end if;
end process RX_PARITY_ERROR_DFF;
end generate USING_PARITY;
-------------------------------------------------------------------------
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
-------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
status_reg(0) <= '0';
end generate NO_PARITY;
-------------------------------------------------------------------------
-- CTRL_REG_DFF : Control Register Handling
-------------------------------------------------------------------------
CTRL_REG_DFF : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
elsif (bus2ip_wrce(3) = '1') then
reset_RX_FIFO <= bus2ip_data(6);
reset_TX_FIFO <= bus2ip_data(7);
enable_interrupts <= bus2ip_data(3);
else
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
-------------------------------------------------------------------------
-- Tx Fifo Interrupt handling
-------------------------------------------------------------------------
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Buffer_Empty_Pre <= '0';
else
if (bus2ip_wrce(1) = '1') then
tx_Buffer_Empty_Pre <= '0';
else
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
end if;
end if;
end if;
end process TX_BUFFER_EMPTY_DFF_I;
-------------------------------------------------------------------------
-- Rx Fifo Interrupt handling
-------------------------------------------------------------------------
RX_BUFFER_DATA_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
rx_Data_Present_Pre <= '0';
else
if (bus2ip_rdce(0) = '1') then
rx_Data_Present_Pre <= '0';
else
rx_Data_Present_Pre <= rx_Data_Present;
end if;
end if;
end if;
end process RX_BUFFER_DATA_DFF_I;
-------------------------------------------------------------------------
-- Interrupt register handling
-------------------------------------------------------------------------
INTERRUPT_DFF: process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then -- synchronous reset (active high)
Interrupt <= '0';
else
Interrupt <= enable_interrupts and
((rx_Data_Present and not rx_Data_Present_Pre) or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
end if;
end if;
end process INTERRUPT_DFF;
-------------------------------------------------------------------------
-- READ_MUX : Read bus interface handling
-------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin -- process Read_Mux
if (bus2ip_rdce(2) = '1') then
SIn_DBus <= status_reg;
elsif (bus2ip_rdce(0) = '1') then
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
else
SIn_DBus <= (others => '0');
end if;
end process READ_MUX;
-------------------------------------------------------------------------
-- UARTLITE_RX_I : Instansiating the receive module
-------------------------------------------------------------------------
UARTLITE_RX_I : entity axi_uartlite_v2_0_15.uartlite_rx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
RX => RX,
Read_RX_FIFO => bus2ip_rdce(0),
Reset_RX_FIFO => reset_RX_FIFO,
RX_Data => rx_Data,
RX_Data_Present => rx_Data_Present,
RX_Buffer_Full => rx_Buffer_Full,
RX_Frame_Error => rx_Frame_Error,
RX_Overrun_Error => rx_Overrun_Error,
RX_Parity_Error => rx_Parity_Error
);
-------------------------------------------------------------------------
-- UARTLITE_TX_I : Instansiating the transmit module
-------------------------------------------------------------------------
UARTLITE_TX_I : entity axi_uartlite_v2_0_15.uartlite_tx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
TX => TX,
Write_TX_FIFO => bus2ip_wrce(1),
Reset_TX_FIFO => reset_TX_FIFO,
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
TX_Buffer_Full => tx_Buffer_Full,
TX_Buffer_Empty => tx_Buffer_Empty
);
end architecture RTL;
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_uartlite.vhd
-- Version: v1.02.a
-- Description: AXI UART Lite Interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_lite_ipif_v3_0_4;
-- SLV64_ARRAY_TYPE refered from ipif_pkg
use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE;
-- INTEGER_ARRAY_TYPE refered from ipif_pkg
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
-- calc_num_ce comoponent refered from ipif_pkg
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
-- axi_lite_ipif refered from axi_lite_ipif_v2_0
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
library axi_uartlite_v2_0_15;
-- uartlite_core refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.uartlite_core;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- AXI generics
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
--
-- UART Lite generics
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
--System signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- Interrupt -- UART Interrupt
--AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
--UARTLite Interface Signals
-- rx -- Receive Data
-- tx -- Transmit Data
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity axi_uartlite is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ : integer := 100_000_000;
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 4;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- UARTLite Parameters
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
-- System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
interrupt : out std_logic;
-- AXI signals
s_axi_awaddr : in std_logic_vector
(3 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector
(31 downto 0);
s_axi_wstrb : in std_logic_vector
(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector
(3 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector
(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- UARTLite Interface Signals
rx : in std_logic;
tx : out std_logic
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
-------------------------------------------------------------------------------
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of s_axi_aclk : signal is "10000";
ATTRIBUTE MAX_FANOUT of s_axi_aresetn : signal is "10000";
end entity axi_uartlite;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of axi_uartlite is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0)
:= X"00000000";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
-- UARTLite registers Base Address
ZEROES & X"00000000",
ZEROES & (X"00000000" or X"0000000F")
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 4
);
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0)
:= X"0000000F";
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0)
:= (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector
(C_S_AXI_DATA_WIDTH - 1 downto 0);
signal bus2ip_cs : std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
begin -- architecture IMP
--------------------------------------------------------------------------
-- RESET signal assignment - IPIC RESET is active low
--------------------------------------------------------------------------
bus2ip_reset <= not bus2ip_resetn;
--------------------------------------------------------------------------
-- ip2bus_data assignment - as core is using maximum upto 8 bits
--------------------------------------------------------------------------
ip2bus_data((C_S_AXI_DATA_WIDTH-1) downto 8) <= (others => '0');
--------------------------------------------------------------------------
-- Instansiating the UART core
--------------------------------------------------------------------------
UARTLITE_CORE_I : entity axi_uartlite_v2_0_15.uartlite_core
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_BAUDRATE => C_BAUDRATE,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => bus2ip_clk,
Reset => bus2ip_reset,
bus2ip_data => bus2ip_data(7 downto 0),
bus2ip_rdce => bus2ip_rdce(3 downto 0),
bus2ip_wrce => bus2ip_wrce(3 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
SIn_DBus => ip2bus_data(7 downto 0),
RX => rx,
TX => tx,
Interrupt => Interrupt
);
--------------------------------------------------------------------------
-- Instantiate AXI lite IPIF
--------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end architecture RTL;
|
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
architecture behavioral of dynshreg_i_f is
constant USE_INFERRED : boolean := true;
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
begin
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
-------------------------------------------------------------------------------
-- uartlite_tx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_tx.vhd
-- Version: v2.0
-- Description: UART Lite Transmit Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.UNSIGNED;
use IEEE.numeric_std.to_unsigned;
use IEEE.numeric_std."-";
library lib_srl_fifo_v1_0_2;
-- dynshreg_i_f refered from proc_common_v4_0_20_a
library axi_uartlite_v2_0_15;
-- uartlite_core refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.all;
-- srl_fifo_f refered from proc_common_v4_0_20_a
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- TX -- Transmit Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Write_TX_FIFO -- Write transmit FIFO
-- Reset_TX_FIFO -- Reset transmit FIFO
-- TX_Data -- Transmit data input
-- TX_Buffer_Full -- Transmit buffer full
-- TX_Buffer_Empty -- Transmit buffer empty
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_tx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
TX : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_DATA_BITS-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic
);
end entity uartlite_tx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_tx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
-------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------
constant MUX_SEL_INIT : std_logic_vector(0 to 2) :=
std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
-------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------
signal parity : std_logic;
signal tx_Run1 : std_logic;
signal select_Parity : std_logic;
signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
signal div16 : std_logic;
signal tx_Data_Enable : std_logic;
signal tx_Start : std_logic;
signal tx_DataBits : std_logic;
signal tx_Run : std_logic;
signal mux_sel : std_logic_vector(0 to 2);
signal mux_sel_is_zero : std_logic;
signal mux_01 : std_logic;
signal mux_23 : std_logic;
signal mux_45 : std_logic;
signal mux_67 : std_logic;
signal mux_0123 : std_logic;
signal mux_4567 : std_logic;
signal mux_Out : std_logic;
signal serial_Data : std_logic;
signal fifo_Read : std_logic;
signal fifo_Data_Present : std_logic := '0';
signal fifo_Data_Empty : std_logic;
signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1);
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal tx_buffer_full_i : std_logic;
signal TX_FIFO_Reset : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
--MID_START_BIT_SRL16_I : Shift register is used to generate div16 that
-- gets shifted for 16 times(as Addr = 15) when
-- EN_16x_Baud is high.
---------------------------------------------------------------------------
MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0_15.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_INIT_VALUE => X"8000",
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => div16,
Dout(0) => div16
);
------------------------------------------------------------------------
-- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and
-- EN_16x_Baud is 1. It will deasserted in the
-- next clock cycle.
------------------------------------------------------------------------
TX_DATA_ENABLE_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Data_Enable <= '0';
else
if (tx_Data_Enable = '1') then
tx_Data_Enable <= '0';
elsif (EN_16x_Baud = '1') then
tx_Data_Enable <= div16;
end if;
end if;
end if;
end process TX_DATA_ENABLE_DFF;
------------------------------------------------------------------------
-- TX_START_DFF : tx_start is '1' for the start bit in a transmission
------------------------------------------------------------------------
TX_START_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Start <= '0';
else
tx_Start <= (not(tx_Run) and (tx_Start or
(fifo_Data_Present and tx_Data_Enable)));
end if;
end if;
end process TX_START_DFF;
--------------------------------------------------------------------------
-- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission
--------------------------------------------------------------------------
TX_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_DataBits <= '0';
else
tx_DataBits <= (not(fifo_Read) and (tx_DataBits or
(tx_Start and tx_Data_Enable)));
end if;
end if;
end process TX_DATA_DFF;
-------------------------------------------------------------------------
-- COUNTER : If mux_sel is zero then reload with the init value else if
-- tx_DataBits = '1', decrement
-------------------------------------------------------------------------
COUNTER : process (Clk) is
begin -- process Mux_Addr_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1,
mux_sel'length));
elsif (tx_Data_Enable = '1') then
if (mux_sel_is_zero = '1') then
mux_sel <= MUX_SEL_INIT;
elsif (tx_DataBits = '1') then
mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1);
end if;
end if;
end if;
end process COUNTER;
------------------------------------------------------------------------
-- Detecting when mux_sel is zero, i.e. all data bits are transfered
------------------------------------------------------------------------
mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
--------------------------------------------------------------------------
-- FIFO_READ_DFF : Read out the next data from the transmit fifo when the
-- data has been transmitted
--------------------------------------------------------------------------
FIFO_READ_DFF : process (Clk) is
begin -- process FIFO_Read_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Read <= '0';
else
fifo_Read <= tx_Data_Enable and mux_sel_is_zero;
end if;
end if;
end process FIFO_READ_DFF;
--------------------------------------------------------------------------
-- Select which bit within the data word to transmit
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- PARITY_BIT_INSERTION : Need special treatment for inserting the parity
-- bit because of parity generation
--------------------------------------------------------------------------
data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2);
data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else
fifo_DOut(C_DATA_BITS-1);
mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else
data_to_transfer(0);
mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else
data_to_transfer(2);
--------------------------------------------------------------------------
-- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5
--------------------------------------------------------------------------
DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate
mux_45 <= data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_5;
--------------------------------------------------------------------------
-- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6
--------------------------------------------------------------------------
DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_6;
--------------------------------------------------------------------------
-- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7
--------------------------------------------------------------------------
DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(6);
end generate DATA_BITS_IS_7;
--------------------------------------------------------------------------
-- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8
--------------------------------------------------------------------------
DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else
data_to_transfer(6);
end generate DATA_BITS_IS_8;
mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01;
mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45;
mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123;
--------------------------------------------------------------------------
-- SERIAL_DATA_DFF : Register the mux_Out
--------------------------------------------------------------------------
SERIAL_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
serial_Data <= '0';
else
serial_Data <= mux_Out;
end if;
end if;
end process SERIAL_DATA_DFF;
--------------------------------------------------------------------------
-- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit
-- Force a '1' when tx_run is '0', Idle
-- otherwise put out the serial_data
--------------------------------------------------------------------------
SERIAL_OUT_DFF : process (Clk) is
begin -- process Serial_Out_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
TX <= '1';
else
TX <= (not(tx_Run) or serial_Data) and (not(tx_Start));
end if;
end if;
end process SERIAL_OUT_DFF;
--------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
--------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (tx_Start = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (tx_Data_Enable = '1') then
parity <= parity xor serial_Data;
end if;
end if;
end process PARITY_DFF;
TX_RUN1_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Run1 <= '0';
elsif (tx_Data_Enable = '1') then
tx_Run1 <= tx_DataBits;
end if;
end if;
end process TX_RUN1_DFF;
tx_Run <= tx_Run1 or tx_DataBits;
SELECT_PARITY_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
select_Parity <= '0';
elsif (tx_Data_Enable = '1') then
select_Parity <= mux_sel_is_zero;
end if;
end if;
end process SELECT_PARITY_DFF;
end generate USING_PARITY;
--------------------------------------------------------------------------
-- NO_PARITY : When C_USE_PARITY = 0 select parity as '0'
--------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
tx_Run <= tx_DataBits;
select_Parity <= '0';
end generate NO_PARITY;
--------------------------------------------------------------------------
-- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO
--------------------------------------------------------------------------
fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i);
--------------------------------------------------------------------------
-- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO
--------------------------------------------------------------------------
fifo_rd <= fifo_Read and (not fifo_Data_Empty);
--------------------------------------------------------------------------
-- Reset TX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
TX_FIFO_Reset <= Reset_TX_FIFO or Reset;
--------------------------------------------------------------------------
-- SRL_FIFO_I : Transmit FIFO Interface
--------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => TX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => TX_Data,
FIFO_Read => fifo_rd,
Data_Out => fifo_DOut,
FIFO_Full => tx_buffer_full_i,
FIFO_Empty => fifo_Data_Empty
);
TX_Buffer_Full <= tx_buffer_full_i;
TX_Buffer_Empty <= fifo_Data_Empty;
fifo_Data_Present <= not fifo_Data_Empty;
end architecture RTL;
-------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_rx.vhd
-- Version: v2.0
-- Description: UART Lite Receive Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
-- dynshreg_i_f refered from proc_common_v4_0_2
-- srl_fifo_f refered from proc_common_v4_0_2
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_uartlite_v2_0_15;
-- uartlite_core refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
--
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- RX -- Receive Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Read_RX_FIFO -- Read receive FIFO
-- Reset_RX_FIFO -- Reset receive FIFO
-- RX_Data -- Receive data output
-- RX_Data_Present -- Receive data present
-- RX_Buffer_Full -- Receive buffer full
-- RX_Frame_Error -- Receive frame error
-- RX_Overrun_Error -- Receive overrun error
-- RX_Parity_Error -- Receive parity error
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_rx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
RX : in std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_DATA_BITS-1);
RX_Data_Present : out std_logic;
RX_Buffer_Full : out std_logic;
RX_Frame_Error : out std_logic;
RX_Overrun_Error : out std_logic;
RX_Parity_Error : out std_logic
);
end entity uartlite_rx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_rx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant SERIAL_TO_PAR_LENGTH : integer :=
C_DATA_BITS + C_USE_PARITY;
constant STOP_BIT_POS : integer := SERIAL_TO_PAR_LENGTH;
constant DATA_LSB_POS : integer := SERIAL_TO_PAR_LENGTH;
constant CALC_PAR_POS : integer := SERIAL_TO_PAR_LENGTH;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
signal start_Edge_Detected : boolean;
signal start_Edge_Detected_Bit : std_logic;
signal running : boolean;
signal recycle : std_logic;
signal sample_Point : std_logic;
signal stop_Bit_Position : std_logic;
signal fifo_Write : std_logic;
signal fifo_din : std_logic_vector(0 to SERIAL_TO_PAR_LENGTH);
signal serial_to_Par : std_logic_vector(1 to SERIAL_TO_PAR_LENGTH);
signal calc_parity : std_logic;
signal parity : std_logic;
signal RX_Buffer_Full_I : std_logic;
signal RX_D1 : std_logic;
signal RX_D2 : std_logic;
signal rx_1 : std_logic;
signal rx_2 : std_logic;
signal rx_3 : std_logic;
signal rx_4 : std_logic;
signal rx_5 : std_logic;
signal rx_6 : std_logic;
signal rx_7 : std_logic;
signal rx_8 : std_logic;
signal rx_9 : std_logic;
signal rx_Data_Empty : std_logic := '0';
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal RX_FIFO_Reset : std_logic;
signal valid_rx : std_logic;
signal valid_start : std_logic;
signal frame_err_ocrd : std_logic;
signal frame_err : std_logic;
begin -- architecture RTL
---------------------------------------------------------------------------
-- RX_SAMPLING : Double sample RX to avoid meta-stability
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => RX,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => RX_D2,
scndry_vect_out => open
);
-- RX_SAMPLING: process (Clk) is
-- begin -- process RX_Sampling
-- if Clk'event and Clk = '1' then -- rising clock edge
-- if Reset = '1' then -- synchronous reset (active high)
-- RX_D1 <= '1';
-- RX_D2 <= '1';
-- else
-- RX_D1 <= RX;
-- RX_D2 <= RX_D1;
-- end if;
-- end if;
-- end process RX_SAMPLING;
-------------------------------------------------------------------------------
-- Detect a falling edge on RX and start a new reception if idle
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- detect the start of the frame
---------------------------------------------------------------------------
RX_DFFS : process (Clk) is
begin -- process Prev_RX_DFFS
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
rx_1 <= '0';
rx_2 <= '0';
rx_3 <= '0';
rx_4 <= '0';
rx_5 <= '0';
rx_6 <= '0';
rx_7 <= '0';
rx_8 <= '0';
rx_9 <= '0';
elsif (EN_16x_Baud = '1') then
rx_1 <= RX_D2;
rx_2 <= rx_1;
rx_3 <= rx_2;
rx_4 <= rx_3;
rx_5 <= rx_4;
rx_6 <= rx_5;
rx_7 <= rx_6;
rx_8 <= rx_7;
rx_9 <= rx_8;
end if;
end if;
end process RX_DFFS;
---------------------------------------------------------------------------
-- Start bit valid when RX is continuously low for atleast 8 samples
---------------------------------------------------------------------------
valid_start <= rx_8 or rx_7 or rx_6 or rx_5 or
rx_4 or rx_3 or rx_2 or rx_1;
---------------------------------------------------------------------------
-- START_EDGE_DFF : Start a new reception if idle
---------------------------------------------------------------------------
START_EDGE_DFF : process (Clk) is
begin -- process Start_Edge_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
start_Edge_Detected <= false;
elsif (EN_16x_Baud = '1') then
start_Edge_Detected <= ((not running) and
(frame_err_ocrd = '0') and
(rx_9 = '1') and
(valid_start = '0'));
end if;
end if;
end process START_EDGE_DFF;
---------------------------------------------------------------------------
-- FRAME_ERR_CAPTURE : frame_err_ocrd is '1' when a frame error is occured
-- and deasserted when the next low to high on RX
---------------------------------------------------------------------------
FRAME_ERR_CAPTURE : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
frame_err_ocrd <= '0';
elsif (frame_err = '1') then
frame_err_ocrd <= '1';
elsif (RX_D2 = '1') then
frame_err_ocrd <= '0';
end if;
end if;
end process FRAME_ERR_CAPTURE;
---------------------------------------------------------------------------
-- VALID_XFER : valid_rx is '1' when a valid start edge detected
---------------------------------------------------------------------------
VALID_XFER : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
valid_rx <= '0';
elsif (start_Edge_Detected = true) then
valid_rx <= '1';
elsif (fifo_Write = '1') then
valid_rx <= '0';
end if;
end if;
end process VALID_XFER;
---------------------------------------------------------------------------
-- RUNNING_DFF : Running is '1' during a reception
---------------------------------------------------------------------------
RUNNING_DFF : process (Clk) is
begin -- process Running_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
running <= false;
elsif (EN_16x_Baud = '1') then
if (start_Edge_Detected) then
running <= true;
elsif ((sample_Point = '1') and (stop_Bit_Position = '1')) then
running <= false;
end if;
end if;
end if;
end process RUNNING_DFF;
---------------------------------------------------------------------------
-- Boolean to std logic conversion of start edge
---------------------------------------------------------------------------
start_Edge_Detected_Bit <= '1' when start_Edge_Detected else '0';
---------------------------------------------------------------------------
-- After the start edge is detected, generate recycle to generate sample
-- point
---------------------------------------------------------------------------
recycle <= (valid_rx and (not stop_Bit_Position) and
(start_Edge_Detected_Bit or sample_Point));
-------------------------------------------------------------------------
-- DELAY_16_I : Keep regenerating new values into the 16 clock delay,
-- Starting with the first start_Edge_Detected_Bit and for every new
-- sample_points until stop_Bit_Position is reached
-------------------------------------------------------------------------
DELAY_16_I : entity axi_uartlite_v2_0_15.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => recycle,
Dout(0) => sample_Point
);
---------------------------------------------------------------------------
-- STOP_BIT_HANDLER : Detect when the stop bit is received
---------------------------------------------------------------------------
STOP_BIT_HANDLER : process (Clk) is
begin -- process Stop_Bit_Handler
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
stop_Bit_Position <= '0';
elsif (EN_16x_Baud = '1') then
if (stop_Bit_Position = '0') then
-- Start bit has reached the end of the shift register
-- (Stop bit position)
stop_Bit_Position <= sample_Point and
fifo_din(STOP_BIT_POS);
elsif (sample_Point = '1') then
-- if stop_Bit_Position is 1 clear it at next sample_Point
stop_Bit_Position <= '0';
end if;
end if;
end if;
end process STOP_BIT_HANDLER;
USING_PARITY_NO : if (C_USE_PARITY = 0) generate
RX_Parity_Error <= '0' ;
end generate USING_PARITY_NO;
---------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
---------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1' or start_Edge_Detected_Bit = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (EN_16x_Baud = '1') then
parity <= calc_parity;
end if;
end if;
end process PARITY_DFF;
calc_parity <= parity when (stop_Bit_Position or
(not sample_Point)) = '1'
else parity xor RX_D2;
RX_Parity_Error <= (EN_16x_Baud and sample_Point) and
(fifo_din(CALC_PAR_POS)) and not stop_Bit_Position
when running and (RX_D2 /= parity) else '0';
end generate USING_PARITY;
fifo_din(0) <= RX_D2 and not Reset;
---------------------------------------------------------------------------
-- SERIAL_TO_PARALLEL : Serial to parrallel conversion data part
---------------------------------------------------------------------------
SERIAL_TO_PARALLEL : for i in 1 to serial_to_Par'length generate
serial_to_Par(i) <= fifo_din(i) when (stop_Bit_Position or
not sample_Point) = '1'
else fifo_din(i-1);
BIT_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
fifo_din(i) <= '0'; -- Bit STOP_BIT_POS resets to '0';
else -- others to '1'
if (start_Edge_Detected_Bit = '1') then
fifo_din(i) <= bo2sl(i=1); -- Bit 1 resets to '1';
-- others to '0'
elsif (EN_16x_Baud = '1') then
fifo_din(i) <= serial_to_Par(i);
end if;
end if;
end if;
end process BIT_I;
end generate SERIAL_TO_PARALLEL;
--------------------------------------------------------------------------
-- FIFO_WRITE_DFF : Write in the received word when the stop_bit has been
-- received and it is a '1'
--------------------------------------------------------------------------
FIFO_WRITE_DFF : process (Clk) is
begin -- process FIFO_Write_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Write <= '0';
else
fifo_Write <= stop_Bit_Position and RX_D2 and sample_Point
and EN_16x_Baud;
end if;
end if;
end process FIFO_WRITE_DFF;
frame_err <= stop_Bit_Position and sample_Point and EN_16x_Baud
and not RX_D2;
RX_Frame_Error <= frame_err;
--------------------------------------------------------------------------
-- Write RX FIFO when FIFO is not full when valid data is reveived
--------------------------------------------------------------------------
fifo_wr <= fifo_Write and (not RX_Buffer_Full_I) and valid_rx;
--------------------------------------------------------------------------
-- Read RX FIFO when FIFO is not empty when AXI reads data from RX FIFO
--------------------------------------------------------------------------
fifo_rd <= Read_RX_FIFO and (not rx_Data_Empty);
--------------------------------------------------------------------------
-- Reset RX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
RX_FIFO_Reset <= Reset_RX_FIFO or Reset;
---------------------------------------------------------------------------
-- SRL_FIFO_I : Receive FIFO Interface
---------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => RX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => fifo_din((DATA_LSB_POS-C_DATA_BITS + 1) to DATA_LSB_POS),
FIFO_Read => fifo_rd,
Data_Out => RX_Data,
FIFO_Full => RX_Buffer_Full_I,
FIFO_Empty => rx_Data_Empty,
Addr => open
);
RX_Data_Present <= not rx_Data_Empty;
RX_Overrun_Error <= RX_Buffer_Full_I and fifo_Write; -- Note that if
-- the RX FIFO is read on the same cycle as it is written while full,
-- there is no loss of data. However this case is not optimized and
-- is also reported as an overrun.
RX_Buffer_Full <= RX_Buffer_Full_I;
end architecture RTL;
-------------------------------------------------------------------------------
-- baudrate - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: baudrate.vhd
-- Version: v2.0
-- Description: Baud rate enable logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_RATIO -- The ratio between clk and the asked baudrate
-- multiplied with 16
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Reset -- Reset signal
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity baudrate is
generic
(
C_RATIO : integer := 48 -- The ratio between clk and the asked
-- baudrate multiplied with 16
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : out std_logic
);
end entity baudrate;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of baudrate is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
signal count : natural range 0 to C_RATIO-1;
begin -- architecture VHDL_RTL
---------------------------------------------------------------------------
-- COUNTER_PROCESS : Down counter for generating EN_16x_Baud signal
---------------------------------------------------------------------------
COUNTER_PROCESS : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
count <= 0;
EN_16x_Baud <= '0';
else
if (count = 0) then
count <= C_RATIO-1;
EN_16x_Baud <= '1';
else
count <= count - 1;
EN_16x_Baud <= '0';
end if;
end if;
end if;
end process COUNTER_PROCESS;
end architecture RTL;
-------------------------------------------------------------------------------
-- uartlite_core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_core.vhd
-- Version: v2.0
-- Description: UART Lite core for implementing UART logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_uartlite_v2_0_15;
-- baudrate refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.baudrate;
-- uartlite_rx refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.uartlite_rx;
-- uartlite_tx refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.uartlite_tx;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- Slave attachment interface
-- bus2ip_data -- bus2ip data signal
-- bus2ip_rdce -- bus2ip read CE
-- bus2ip_wrce -- bus2ip write CE
-- ip2bus_rdack -- ip2bus read acknowledgement
-- ip2bus_wrack -- ip2bus write acknowledgement
-- ip2bus_error -- ip2bus error
-- SIn_DBus -- ip2bus data
-- UART Lite interface
-- RX -- Receive Data
-- TX -- Transmit Data
-- Interrupt -- UART Interrupt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_core is
generic
(
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
-- IPIF signals
bus2ip_data : in std_logic_vector(0 to 7);
bus2ip_rdce : in std_logic_vector(0 to 3);
bus2ip_wrce : in std_logic_vector(0 to 3);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
SIn_DBus : out std_logic_vector(0 to 7);
-- UART signals
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end entity uartlite_core;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- function declarations
---------------------------------------------------------------------------
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
C_BAUDRATE : integer ) return Integer is
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
constant REMAINDER : integer :=
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
constant RATIO : integer :=
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
begin
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
return (RATIO + 1);
else
return RATIO;
end if;
end function CALC_RATIO;
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Read Only
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- bit 2 Overrun Error
-- bit 1 Frame Error
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
-- Write Only
-- Below mentioned bits belong to Control Register and are declared as
-- signals below
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4-5 Dont'Care
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal en_16x_Baud : std_logic;
signal enable_interrupts : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal rx_Frame_Error : std_logic;
signal rx_Overrun_Error : std_logic;
signal rx_Parity_Error : std_logic;
signal clr_Status : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal rx_Data_Present_Pre : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
-- Generating the acknowledgement and error signals
---------------------------------------------------------------------------
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
-------------------------------------------------------------------------
-- BAUD_RATE_I : Instansiating the baudrate module
-------------------------------------------------------------------------
BAUD_RATE_I : entity axi_uartlite_v2_0_15.baudrate
generic map
(
C_RATIO => RATIO
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud
);
-------------------------------------------------------------------------
-- Status register handling
-------------------------------------------------------------------------
status_reg(7) <= rx_Data_Present;
status_reg(6) <= rx_Buffer_Full;
status_reg(5) <= tx_Buffer_Empty;
status_reg(4) <= tx_Buffer_Full;
status_reg(3) <= enable_interrupts;
-------------------------------------------------------------------------
-- CLEAR_STATUS_REG : Process to clear status register
-------------------------------------------------------------------------
CLEAR_STATUS_REG : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then
if Reset = '1' then
clr_Status <= '0';
else
clr_Status <= bus2ip_rdce(2);
end if;
end if;
end process CLEAR_STATUS_REG;
-------------------------------------------------------------------------
-- Process to register rx_Overrun_Error
-------------------------------------------------------------------------
RX_OVERRUN_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Reset = '1') or (clr_Status = '1')) then
status_reg(2) <= '0';
elsif (rx_Overrun_Error = '1') then
status_reg(2) <= '1';
end if;
end if;
end process RX_OVERRUN_ERROR_DFF;
-------------------------------------------------------------------------
-- Process to register rx_Frame_Error
-------------------------------------------------------------------------
RX_FRAME_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(1) <= '0';
else
if (clr_Status = '1') then
status_reg(1) <= '0';
elsif (rx_Frame_Error = '1') then
status_reg(1) <= '1';
end if;
end if;
end if;
end process RX_FRAME_ERROR_DFF;
-------------------------------------------------------------------------
-- If C_USE_PARITY = 1, register rx_Parity_Error
-------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
RX_PARITY_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(0) <= '0';
else
if (clr_Status = '1') then
status_reg(0) <= '0';
elsif (rx_Parity_Error = '1') then
status_reg(0) <= '1';
end if;
end if;
end if;
end process RX_PARITY_ERROR_DFF;
end generate USING_PARITY;
-------------------------------------------------------------------------
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
-------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
status_reg(0) <= '0';
end generate NO_PARITY;
-------------------------------------------------------------------------
-- CTRL_REG_DFF : Control Register Handling
-------------------------------------------------------------------------
CTRL_REG_DFF : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
elsif (bus2ip_wrce(3) = '1') then
reset_RX_FIFO <= bus2ip_data(6);
reset_TX_FIFO <= bus2ip_data(7);
enable_interrupts <= bus2ip_data(3);
else
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
-------------------------------------------------------------------------
-- Tx Fifo Interrupt handling
-------------------------------------------------------------------------
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Buffer_Empty_Pre <= '0';
else
if (bus2ip_wrce(1) = '1') then
tx_Buffer_Empty_Pre <= '0';
else
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
end if;
end if;
end if;
end process TX_BUFFER_EMPTY_DFF_I;
-------------------------------------------------------------------------
-- Rx Fifo Interrupt handling
-------------------------------------------------------------------------
RX_BUFFER_DATA_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
rx_Data_Present_Pre <= '0';
else
if (bus2ip_rdce(0) = '1') then
rx_Data_Present_Pre <= '0';
else
rx_Data_Present_Pre <= rx_Data_Present;
end if;
end if;
end if;
end process RX_BUFFER_DATA_DFF_I;
-------------------------------------------------------------------------
-- Interrupt register handling
-------------------------------------------------------------------------
INTERRUPT_DFF: process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then -- synchronous reset (active high)
Interrupt <= '0';
else
Interrupt <= enable_interrupts and
((rx_Data_Present and not rx_Data_Present_Pre) or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
end if;
end if;
end process INTERRUPT_DFF;
-------------------------------------------------------------------------
-- READ_MUX : Read bus interface handling
-------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin -- process Read_Mux
if (bus2ip_rdce(2) = '1') then
SIn_DBus <= status_reg;
elsif (bus2ip_rdce(0) = '1') then
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
else
SIn_DBus <= (others => '0');
end if;
end process READ_MUX;
-------------------------------------------------------------------------
-- UARTLITE_RX_I : Instansiating the receive module
-------------------------------------------------------------------------
UARTLITE_RX_I : entity axi_uartlite_v2_0_15.uartlite_rx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
RX => RX,
Read_RX_FIFO => bus2ip_rdce(0),
Reset_RX_FIFO => reset_RX_FIFO,
RX_Data => rx_Data,
RX_Data_Present => rx_Data_Present,
RX_Buffer_Full => rx_Buffer_Full,
RX_Frame_Error => rx_Frame_Error,
RX_Overrun_Error => rx_Overrun_Error,
RX_Parity_Error => rx_Parity_Error
);
-------------------------------------------------------------------------
-- UARTLITE_TX_I : Instansiating the transmit module
-------------------------------------------------------------------------
UARTLITE_TX_I : entity axi_uartlite_v2_0_15.uartlite_tx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
TX => TX,
Write_TX_FIFO => bus2ip_wrce(1),
Reset_TX_FIFO => reset_TX_FIFO,
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
TX_Buffer_Full => tx_Buffer_Full,
TX_Buffer_Empty => tx_Buffer_Empty
);
end architecture RTL;
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_uartlite.vhd
-- Version: v1.02.a
-- Description: AXI UART Lite Interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_lite_ipif_v3_0_4;
-- SLV64_ARRAY_TYPE refered from ipif_pkg
use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE;
-- INTEGER_ARRAY_TYPE refered from ipif_pkg
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
-- calc_num_ce comoponent refered from ipif_pkg
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
-- axi_lite_ipif refered from axi_lite_ipif_v2_0
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
library axi_uartlite_v2_0_15;
-- uartlite_core refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.uartlite_core;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- AXI generics
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
--
-- UART Lite generics
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
--System signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- Interrupt -- UART Interrupt
--AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
--UARTLite Interface Signals
-- rx -- Receive Data
-- tx -- Transmit Data
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity axi_uartlite is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ : integer := 100_000_000;
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 4;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- UARTLite Parameters
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
-- System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
interrupt : out std_logic;
-- AXI signals
s_axi_awaddr : in std_logic_vector
(3 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector
(31 downto 0);
s_axi_wstrb : in std_logic_vector
(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector
(3 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector
(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- UARTLite Interface Signals
rx : in std_logic;
tx : out std_logic
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
-------------------------------------------------------------------------------
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of s_axi_aclk : signal is "10000";
ATTRIBUTE MAX_FANOUT of s_axi_aresetn : signal is "10000";
end entity axi_uartlite;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of axi_uartlite is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0)
:= X"00000000";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
-- UARTLite registers Base Address
ZEROES & X"00000000",
ZEROES & (X"00000000" or X"0000000F")
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 4
);
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0)
:= X"0000000F";
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0)
:= (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector
(C_S_AXI_DATA_WIDTH - 1 downto 0);
signal bus2ip_cs : std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
begin -- architecture IMP
--------------------------------------------------------------------------
-- RESET signal assignment - IPIC RESET is active low
--------------------------------------------------------------------------
bus2ip_reset <= not bus2ip_resetn;
--------------------------------------------------------------------------
-- ip2bus_data assignment - as core is using maximum upto 8 bits
--------------------------------------------------------------------------
ip2bus_data((C_S_AXI_DATA_WIDTH-1) downto 8) <= (others => '0');
--------------------------------------------------------------------------
-- Instansiating the UART core
--------------------------------------------------------------------------
UARTLITE_CORE_I : entity axi_uartlite_v2_0_15.uartlite_core
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_BAUDRATE => C_BAUDRATE,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => bus2ip_clk,
Reset => bus2ip_reset,
bus2ip_data => bus2ip_data(7 downto 0),
bus2ip_rdce => bus2ip_rdce(3 downto 0),
bus2ip_wrce => bus2ip_wrce(3 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
SIn_DBus => ip2bus_data(7 downto 0),
RX => rx,
TX => tx,
Interrupt => Interrupt
);
--------------------------------------------------------------------------
-- Instantiate AXI lite IPIF
--------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end architecture RTL;
|
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 14;
constant AMPL_WIDTH : integer := 12;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(512,AMPL_WIDTH),
conv_std_logic_vector(513,AMPL_WIDTH),
conv_std_logic_vector(513,AMPL_WIDTH),
conv_std_logic_vector(514,AMPL_WIDTH),
conv_std_logic_vector(515,AMPL_WIDTH),
conv_std_logic_vector(516,AMPL_WIDTH),
conv_std_logic_vector(516,AMPL_WIDTH),
conv_std_logic_vector(517,AMPL_WIDTH),
conv_std_logic_vector(518,AMPL_WIDTH),
conv_std_logic_vector(519,AMPL_WIDTH),
conv_std_logic_vector(519,AMPL_WIDTH),
conv_std_logic_vector(520,AMPL_WIDTH),
conv_std_logic_vector(521,AMPL_WIDTH),
conv_std_logic_vector(522,AMPL_WIDTH),
conv_std_logic_vector(522,AMPL_WIDTH),
conv_std_logic_vector(523,AMPL_WIDTH),
conv_std_logic_vector(524,AMPL_WIDTH),
conv_std_logic_vector(525,AMPL_WIDTH),
conv_std_logic_vector(526,AMPL_WIDTH),
conv_std_logic_vector(526,AMPL_WIDTH),
conv_std_logic_vector(527,AMPL_WIDTH),
conv_std_logic_vector(528,AMPL_WIDTH),
conv_std_logic_vector(529,AMPL_WIDTH),
conv_std_logic_vector(529,AMPL_WIDTH),
conv_std_logic_vector(530,AMPL_WIDTH),
conv_std_logic_vector(531,AMPL_WIDTH),
conv_std_logic_vector(532,AMPL_WIDTH),
conv_std_logic_vector(532,AMPL_WIDTH),
conv_std_logic_vector(533,AMPL_WIDTH),
conv_std_logic_vector(534,AMPL_WIDTH),
conv_std_logic_vector(535,AMPL_WIDTH),
conv_std_logic_vector(535,AMPL_WIDTH),
conv_std_logic_vector(536,AMPL_WIDTH),
conv_std_logic_vector(537,AMPL_WIDTH),
conv_std_logic_vector(538,AMPL_WIDTH),
conv_std_logic_vector(538,AMPL_WIDTH),
conv_std_logic_vector(539,AMPL_WIDTH),
conv_std_logic_vector(540,AMPL_WIDTH),
conv_std_logic_vector(541,AMPL_WIDTH),
conv_std_logic_vector(541,AMPL_WIDTH),
conv_std_logic_vector(542,AMPL_WIDTH),
conv_std_logic_vector(543,AMPL_WIDTH),
conv_std_logic_vector(544,AMPL_WIDTH),
conv_std_logic_vector(544,AMPL_WIDTH),
conv_std_logic_vector(545,AMPL_WIDTH),
conv_std_logic_vector(546,AMPL_WIDTH),
conv_std_logic_vector(547,AMPL_WIDTH),
conv_std_logic_vector(547,AMPL_WIDTH),
conv_std_logic_vector(548,AMPL_WIDTH),
conv_std_logic_vector(549,AMPL_WIDTH),
conv_std_logic_vector(550,AMPL_WIDTH),
conv_std_logic_vector(550,AMPL_WIDTH),
conv_std_logic_vector(551,AMPL_WIDTH),
conv_std_logic_vector(552,AMPL_WIDTH),
conv_std_logic_vector(553,AMPL_WIDTH),
conv_std_logic_vector(554,AMPL_WIDTH),
conv_std_logic_vector(554,AMPL_WIDTH),
conv_std_logic_vector(555,AMPL_WIDTH),
conv_std_logic_vector(556,AMPL_WIDTH),
conv_std_logic_vector(557,AMPL_WIDTH),
conv_std_logic_vector(557,AMPL_WIDTH),
conv_std_logic_vector(558,AMPL_WIDTH),
conv_std_logic_vector(559,AMPL_WIDTH),
conv_std_logic_vector(560,AMPL_WIDTH),
conv_std_logic_vector(560,AMPL_WIDTH),
conv_std_logic_vector(561,AMPL_WIDTH),
conv_std_logic_vector(562,AMPL_WIDTH),
conv_std_logic_vector(563,AMPL_WIDTH),
conv_std_logic_vector(563,AMPL_WIDTH),
conv_std_logic_vector(564,AMPL_WIDTH),
conv_std_logic_vector(565,AMPL_WIDTH),
conv_std_logic_vector(566,AMPL_WIDTH),
conv_std_logic_vector(566,AMPL_WIDTH),
conv_std_logic_vector(567,AMPL_WIDTH),
conv_std_logic_vector(568,AMPL_WIDTH),
conv_std_logic_vector(569,AMPL_WIDTH),
conv_std_logic_vector(569,AMPL_WIDTH),
conv_std_logic_vector(570,AMPL_WIDTH),
conv_std_logic_vector(571,AMPL_WIDTH),
conv_std_logic_vector(572,AMPL_WIDTH),
conv_std_logic_vector(572,AMPL_WIDTH),
conv_std_logic_vector(573,AMPL_WIDTH),
conv_std_logic_vector(574,AMPL_WIDTH),
conv_std_logic_vector(575,AMPL_WIDTH),
conv_std_logic_vector(575,AMPL_WIDTH),
conv_std_logic_vector(576,AMPL_WIDTH),
conv_std_logic_vector(577,AMPL_WIDTH),
conv_std_logic_vector(578,AMPL_WIDTH),
conv_std_logic_vector(578,AMPL_WIDTH),
conv_std_logic_vector(579,AMPL_WIDTH),
conv_std_logic_vector(580,AMPL_WIDTH),
conv_std_logic_vector(581,AMPL_WIDTH),
conv_std_logic_vector(581,AMPL_WIDTH),
conv_std_logic_vector(582,AMPL_WIDTH),
conv_std_logic_vector(583,AMPL_WIDTH),
conv_std_logic_vector(584,AMPL_WIDTH),
conv_std_logic_vector(584,AMPL_WIDTH),
conv_std_logic_vector(585,AMPL_WIDTH),
conv_std_logic_vector(586,AMPL_WIDTH),
conv_std_logic_vector(587,AMPL_WIDTH),
conv_std_logic_vector(587,AMPL_WIDTH),
conv_std_logic_vector(588,AMPL_WIDTH),
conv_std_logic_vector(589,AMPL_WIDTH),
conv_std_logic_vector(590,AMPL_WIDTH),
conv_std_logic_vector(590,AMPL_WIDTH),
conv_std_logic_vector(591,AMPL_WIDTH),
conv_std_logic_vector(592,AMPL_WIDTH),
conv_std_logic_vector(593,AMPL_WIDTH),
conv_std_logic_vector(593,AMPL_WIDTH),
conv_std_logic_vector(594,AMPL_WIDTH),
conv_std_logic_vector(595,AMPL_WIDTH),
conv_std_logic_vector(596,AMPL_WIDTH),
conv_std_logic_vector(596,AMPL_WIDTH),
conv_std_logic_vector(597,AMPL_WIDTH),
conv_std_logic_vector(598,AMPL_WIDTH),
conv_std_logic_vector(599,AMPL_WIDTH),
conv_std_logic_vector(599,AMPL_WIDTH),
conv_std_logic_vector(600,AMPL_WIDTH),
conv_std_logic_vector(601,AMPL_WIDTH),
conv_std_logic_vector(602,AMPL_WIDTH),
conv_std_logic_vector(602,AMPL_WIDTH),
conv_std_logic_vector(603,AMPL_WIDTH),
conv_std_logic_vector(604,AMPL_WIDTH),
conv_std_logic_vector(605,AMPL_WIDTH),
conv_std_logic_vector(605,AMPL_WIDTH),
conv_std_logic_vector(606,AMPL_WIDTH),
conv_std_logic_vector(607,AMPL_WIDTH),
conv_std_logic_vector(608,AMPL_WIDTH),
conv_std_logic_vector(608,AMPL_WIDTH),
conv_std_logic_vector(609,AMPL_WIDTH),
conv_std_logic_vector(610,AMPL_WIDTH),
conv_std_logic_vector(611,AMPL_WIDTH),
conv_std_logic_vector(611,AMPL_WIDTH),
conv_std_logic_vector(612,AMPL_WIDTH),
conv_std_logic_vector(613,AMPL_WIDTH),
conv_std_logic_vector(614,AMPL_WIDTH),
conv_std_logic_vector(614,AMPL_WIDTH),
conv_std_logic_vector(615,AMPL_WIDTH),
conv_std_logic_vector(616,AMPL_WIDTH),
conv_std_logic_vector(617,AMPL_WIDTH),
conv_std_logic_vector(617,AMPL_WIDTH),
conv_std_logic_vector(618,AMPL_WIDTH),
conv_std_logic_vector(619,AMPL_WIDTH),
conv_std_logic_vector(620,AMPL_WIDTH),
conv_std_logic_vector(620,AMPL_WIDTH),
conv_std_logic_vector(621,AMPL_WIDTH),
conv_std_logic_vector(622,AMPL_WIDTH),
conv_std_logic_vector(623,AMPL_WIDTH),
conv_std_logic_vector(623,AMPL_WIDTH),
conv_std_logic_vector(624,AMPL_WIDTH),
conv_std_logic_vector(625,AMPL_WIDTH),
conv_std_logic_vector(626,AMPL_WIDTH),
conv_std_logic_vector(626,AMPL_WIDTH),
conv_std_logic_vector(627,AMPL_WIDTH),
conv_std_logic_vector(628,AMPL_WIDTH),
conv_std_logic_vector(629,AMPL_WIDTH),
conv_std_logic_vector(629,AMPL_WIDTH),
conv_std_logic_vector(630,AMPL_WIDTH),
conv_std_logic_vector(631,AMPL_WIDTH),
conv_std_logic_vector(632,AMPL_WIDTH),
conv_std_logic_vector(632,AMPL_WIDTH),
conv_std_logic_vector(633,AMPL_WIDTH),
conv_std_logic_vector(634,AMPL_WIDTH),
conv_std_logic_vector(635,AMPL_WIDTH),
conv_std_logic_vector(635,AMPL_WIDTH),
conv_std_logic_vector(636,AMPL_WIDTH),
conv_std_logic_vector(637,AMPL_WIDTH),
conv_std_logic_vector(638,AMPL_WIDTH),
conv_std_logic_vector(638,AMPL_WIDTH),
conv_std_logic_vector(639,AMPL_WIDTH),
conv_std_logic_vector(640,AMPL_WIDTH),
conv_std_logic_vector(641,AMPL_WIDTH),
conv_std_logic_vector(641,AMPL_WIDTH),
conv_std_logic_vector(642,AMPL_WIDTH),
conv_std_logic_vector(643,AMPL_WIDTH),
conv_std_logic_vector(644,AMPL_WIDTH),
conv_std_logic_vector(644,AMPL_WIDTH),
conv_std_logic_vector(645,AMPL_WIDTH),
conv_std_logic_vector(646,AMPL_WIDTH),
conv_std_logic_vector(647,AMPL_WIDTH),
conv_std_logic_vector(647,AMPL_WIDTH),
conv_std_logic_vector(648,AMPL_WIDTH),
conv_std_logic_vector(649,AMPL_WIDTH),
conv_std_logic_vector(650,AMPL_WIDTH),
conv_std_logic_vector(650,AMPL_WIDTH),
conv_std_logic_vector(651,AMPL_WIDTH),
conv_std_logic_vector(652,AMPL_WIDTH),
conv_std_logic_vector(653,AMPL_WIDTH),
conv_std_logic_vector(653,AMPL_WIDTH),
conv_std_logic_vector(654,AMPL_WIDTH),
conv_std_logic_vector(655,AMPL_WIDTH),
conv_std_logic_vector(656,AMPL_WIDTH),
conv_std_logic_vector(656,AMPL_WIDTH),
conv_std_logic_vector(657,AMPL_WIDTH),
conv_std_logic_vector(658,AMPL_WIDTH),
conv_std_logic_vector(658,AMPL_WIDTH),
conv_std_logic_vector(659,AMPL_WIDTH),
conv_std_logic_vector(660,AMPL_WIDTH),
conv_std_logic_vector(661,AMPL_WIDTH),
conv_std_logic_vector(661,AMPL_WIDTH),
conv_std_logic_vector(662,AMPL_WIDTH),
conv_std_logic_vector(663,AMPL_WIDTH),
conv_std_logic_vector(664,AMPL_WIDTH),
conv_std_logic_vector(664,AMPL_WIDTH),
conv_std_logic_vector(665,AMPL_WIDTH),
conv_std_logic_vector(666,AMPL_WIDTH),
conv_std_logic_vector(667,AMPL_WIDTH),
conv_std_logic_vector(667,AMPL_WIDTH),
conv_std_logic_vector(668,AMPL_WIDTH),
conv_std_logic_vector(669,AMPL_WIDTH),
conv_std_logic_vector(670,AMPL_WIDTH),
conv_std_logic_vector(670,AMPL_WIDTH),
conv_std_logic_vector(671,AMPL_WIDTH),
conv_std_logic_vector(672,AMPL_WIDTH),
conv_std_logic_vector(673,AMPL_WIDTH),
conv_std_logic_vector(673,AMPL_WIDTH),
conv_std_logic_vector(674,AMPL_WIDTH),
conv_std_logic_vector(675,AMPL_WIDTH),
conv_std_logic_vector(676,AMPL_WIDTH),
conv_std_logic_vector(676,AMPL_WIDTH),
conv_std_logic_vector(677,AMPL_WIDTH),
conv_std_logic_vector(678,AMPL_WIDTH),
conv_std_logic_vector(679,AMPL_WIDTH),
conv_std_logic_vector(679,AMPL_WIDTH),
conv_std_logic_vector(680,AMPL_WIDTH),
conv_std_logic_vector(681,AMPL_WIDTH),
conv_std_logic_vector(681,AMPL_WIDTH),
conv_std_logic_vector(682,AMPL_WIDTH),
conv_std_logic_vector(683,AMPL_WIDTH),
conv_std_logic_vector(684,AMPL_WIDTH),
conv_std_logic_vector(684,AMPL_WIDTH),
conv_std_logic_vector(685,AMPL_WIDTH),
conv_std_logic_vector(686,AMPL_WIDTH),
conv_std_logic_vector(687,AMPL_WIDTH),
conv_std_logic_vector(687,AMPL_WIDTH),
conv_std_logic_vector(688,AMPL_WIDTH),
conv_std_logic_vector(689,AMPL_WIDTH),
conv_std_logic_vector(690,AMPL_WIDTH),
conv_std_logic_vector(690,AMPL_WIDTH),
conv_std_logic_vector(691,AMPL_WIDTH),
conv_std_logic_vector(692,AMPL_WIDTH),
conv_std_logic_vector(693,AMPL_WIDTH),
conv_std_logic_vector(693,AMPL_WIDTH),
conv_std_logic_vector(694,AMPL_WIDTH),
conv_std_logic_vector(695,AMPL_WIDTH),
conv_std_logic_vector(696,AMPL_WIDTH),
conv_std_logic_vector(696,AMPL_WIDTH),
conv_std_logic_vector(697,AMPL_WIDTH),
conv_std_logic_vector(698,AMPL_WIDTH),
conv_std_logic_vector(698,AMPL_WIDTH),
conv_std_logic_vector(699,AMPL_WIDTH),
conv_std_logic_vector(700,AMPL_WIDTH),
conv_std_logic_vector(701,AMPL_WIDTH),
conv_std_logic_vector(701,AMPL_WIDTH),
conv_std_logic_vector(702,AMPL_WIDTH),
conv_std_logic_vector(703,AMPL_WIDTH),
conv_std_logic_vector(704,AMPL_WIDTH),
conv_std_logic_vector(704,AMPL_WIDTH),
conv_std_logic_vector(705,AMPL_WIDTH),
conv_std_logic_vector(706,AMPL_WIDTH),
conv_std_logic_vector(707,AMPL_WIDTH),
conv_std_logic_vector(707,AMPL_WIDTH),
conv_std_logic_vector(708,AMPL_WIDTH),
conv_std_logic_vector(709,AMPL_WIDTH),
conv_std_logic_vector(710,AMPL_WIDTH),
conv_std_logic_vector(710,AMPL_WIDTH),
conv_std_logic_vector(711,AMPL_WIDTH),
conv_std_logic_vector(712,AMPL_WIDTH),
conv_std_logic_vector(712,AMPL_WIDTH),
conv_std_logic_vector(713,AMPL_WIDTH),
conv_std_logic_vector(714,AMPL_WIDTH),
conv_std_logic_vector(715,AMPL_WIDTH),
conv_std_logic_vector(715,AMPL_WIDTH),
conv_std_logic_vector(716,AMPL_WIDTH),
conv_std_logic_vector(717,AMPL_WIDTH),
conv_std_logic_vector(718,AMPL_WIDTH),
conv_std_logic_vector(718,AMPL_WIDTH),
conv_std_logic_vector(719,AMPL_WIDTH),
conv_std_logic_vector(720,AMPL_WIDTH),
conv_std_logic_vector(721,AMPL_WIDTH),
conv_std_logic_vector(721,AMPL_WIDTH),
conv_std_logic_vector(722,AMPL_WIDTH),
conv_std_logic_vector(723,AMPL_WIDTH),
conv_std_logic_vector(724,AMPL_WIDTH),
conv_std_logic_vector(724,AMPL_WIDTH),
conv_std_logic_vector(725,AMPL_WIDTH),
conv_std_logic_vector(726,AMPL_WIDTH),
conv_std_logic_vector(726,AMPL_WIDTH),
conv_std_logic_vector(727,AMPL_WIDTH),
conv_std_logic_vector(728,AMPL_WIDTH),
conv_std_logic_vector(729,AMPL_WIDTH),
conv_std_logic_vector(729,AMPL_WIDTH),
conv_std_logic_vector(730,AMPL_WIDTH),
conv_std_logic_vector(731,AMPL_WIDTH),
conv_std_logic_vector(732,AMPL_WIDTH),
conv_std_logic_vector(732,AMPL_WIDTH),
conv_std_logic_vector(733,AMPL_WIDTH),
conv_std_logic_vector(734,AMPL_WIDTH),
conv_std_logic_vector(735,AMPL_WIDTH),
conv_std_logic_vector(735,AMPL_WIDTH),
conv_std_logic_vector(736,AMPL_WIDTH),
conv_std_logic_vector(737,AMPL_WIDTH),
conv_std_logic_vector(737,AMPL_WIDTH),
conv_std_logic_vector(738,AMPL_WIDTH),
conv_std_logic_vector(739,AMPL_WIDTH),
conv_std_logic_vector(740,AMPL_WIDTH),
conv_std_logic_vector(740,AMPL_WIDTH),
conv_std_logic_vector(741,AMPL_WIDTH),
conv_std_logic_vector(742,AMPL_WIDTH),
conv_std_logic_vector(743,AMPL_WIDTH),
conv_std_logic_vector(743,AMPL_WIDTH),
conv_std_logic_vector(744,AMPL_WIDTH),
conv_std_logic_vector(745,AMPL_WIDTH),
conv_std_logic_vector(745,AMPL_WIDTH),
conv_std_logic_vector(746,AMPL_WIDTH),
conv_std_logic_vector(747,AMPL_WIDTH),
conv_std_logic_vector(748,AMPL_WIDTH),
conv_std_logic_vector(748,AMPL_WIDTH),
conv_std_logic_vector(749,AMPL_WIDTH),
conv_std_logic_vector(750,AMPL_WIDTH),
conv_std_logic_vector(751,AMPL_WIDTH),
conv_std_logic_vector(751,AMPL_WIDTH),
conv_std_logic_vector(752,AMPL_WIDTH),
conv_std_logic_vector(753,AMPL_WIDTH),
conv_std_logic_vector(754,AMPL_WIDTH),
conv_std_logic_vector(754,AMPL_WIDTH),
conv_std_logic_vector(755,AMPL_WIDTH),
conv_std_logic_vector(756,AMPL_WIDTH),
conv_std_logic_vector(756,AMPL_WIDTH),
conv_std_logic_vector(757,AMPL_WIDTH),
conv_std_logic_vector(758,AMPL_WIDTH),
conv_std_logic_vector(759,AMPL_WIDTH),
conv_std_logic_vector(759,AMPL_WIDTH),
conv_std_logic_vector(760,AMPL_WIDTH),
conv_std_logic_vector(761,AMPL_WIDTH),
conv_std_logic_vector(762,AMPL_WIDTH),
conv_std_logic_vector(762,AMPL_WIDTH),
conv_std_logic_vector(763,AMPL_WIDTH),
conv_std_logic_vector(764,AMPL_WIDTH),
conv_std_logic_vector(764,AMPL_WIDTH),
conv_std_logic_vector(765,AMPL_WIDTH),
conv_std_logic_vector(766,AMPL_WIDTH),
conv_std_logic_vector(767,AMPL_WIDTH),
conv_std_logic_vector(767,AMPL_WIDTH),
conv_std_logic_vector(768,AMPL_WIDTH),
conv_std_logic_vector(769,AMPL_WIDTH),
conv_std_logic_vector(770,AMPL_WIDTH),
conv_std_logic_vector(770,AMPL_WIDTH),
conv_std_logic_vector(771,AMPL_WIDTH),
conv_std_logic_vector(772,AMPL_WIDTH),
conv_std_logic_vector(772,AMPL_WIDTH),
conv_std_logic_vector(773,AMPL_WIDTH),
conv_std_logic_vector(774,AMPL_WIDTH),
conv_std_logic_vector(775,AMPL_WIDTH),
conv_std_logic_vector(775,AMPL_WIDTH),
conv_std_logic_vector(776,AMPL_WIDTH),
conv_std_logic_vector(777,AMPL_WIDTH),
conv_std_logic_vector(778,AMPL_WIDTH),
conv_std_logic_vector(778,AMPL_WIDTH),
conv_std_logic_vector(779,AMPL_WIDTH),
conv_std_logic_vector(780,AMPL_WIDTH),
conv_std_logic_vector(780,AMPL_WIDTH),
conv_std_logic_vector(781,AMPL_WIDTH),
conv_std_logic_vector(782,AMPL_WIDTH),
conv_std_logic_vector(783,AMPL_WIDTH),
conv_std_logic_vector(783,AMPL_WIDTH),
conv_std_logic_vector(784,AMPL_WIDTH),
conv_std_logic_vector(785,AMPL_WIDTH),
conv_std_logic_vector(786,AMPL_WIDTH),
conv_std_logic_vector(786,AMPL_WIDTH),
conv_std_logic_vector(787,AMPL_WIDTH),
conv_std_logic_vector(788,AMPL_WIDTH),
conv_std_logic_vector(788,AMPL_WIDTH),
conv_std_logic_vector(789,AMPL_WIDTH),
conv_std_logic_vector(790,AMPL_WIDTH),
conv_std_logic_vector(791,AMPL_WIDTH),
conv_std_logic_vector(791,AMPL_WIDTH),
conv_std_logic_vector(792,AMPL_WIDTH),
conv_std_logic_vector(793,AMPL_WIDTH),
conv_std_logic_vector(793,AMPL_WIDTH),
conv_std_logic_vector(794,AMPL_WIDTH),
conv_std_logic_vector(795,AMPL_WIDTH),
conv_std_logic_vector(796,AMPL_WIDTH),
conv_std_logic_vector(796,AMPL_WIDTH),
conv_std_logic_vector(797,AMPL_WIDTH),
conv_std_logic_vector(798,AMPL_WIDTH),
conv_std_logic_vector(799,AMPL_WIDTH),
conv_std_logic_vector(799,AMPL_WIDTH),
conv_std_logic_vector(800,AMPL_WIDTH),
conv_std_logic_vector(801,AMPL_WIDTH),
conv_std_logic_vector(801,AMPL_WIDTH),
conv_std_logic_vector(802,AMPL_WIDTH),
conv_std_logic_vector(803,AMPL_WIDTH),
conv_std_logic_vector(804,AMPL_WIDTH),
conv_std_logic_vector(804,AMPL_WIDTH),
conv_std_logic_vector(805,AMPL_WIDTH),
conv_std_logic_vector(806,AMPL_WIDTH),
conv_std_logic_vector(807,AMPL_WIDTH),
conv_std_logic_vector(807,AMPL_WIDTH),
conv_std_logic_vector(808,AMPL_WIDTH),
conv_std_logic_vector(809,AMPL_WIDTH),
conv_std_logic_vector(809,AMPL_WIDTH),
conv_std_logic_vector(810,AMPL_WIDTH),
conv_std_logic_vector(811,AMPL_WIDTH),
conv_std_logic_vector(812,AMPL_WIDTH),
conv_std_logic_vector(812,AMPL_WIDTH),
conv_std_logic_vector(813,AMPL_WIDTH),
conv_std_logic_vector(814,AMPL_WIDTH),
conv_std_logic_vector(814,AMPL_WIDTH),
conv_std_logic_vector(815,AMPL_WIDTH),
conv_std_logic_vector(816,AMPL_WIDTH),
conv_std_logic_vector(817,AMPL_WIDTH),
conv_std_logic_vector(817,AMPL_WIDTH),
conv_std_logic_vector(818,AMPL_WIDTH),
conv_std_logic_vector(819,AMPL_WIDTH),
conv_std_logic_vector(819,AMPL_WIDTH),
conv_std_logic_vector(820,AMPL_WIDTH),
conv_std_logic_vector(821,AMPL_WIDTH),
conv_std_logic_vector(822,AMPL_WIDTH),
conv_std_logic_vector(822,AMPL_WIDTH),
conv_std_logic_vector(823,AMPL_WIDTH),
conv_std_logic_vector(824,AMPL_WIDTH),
conv_std_logic_vector(825,AMPL_WIDTH),
conv_std_logic_vector(825,AMPL_WIDTH),
conv_std_logic_vector(826,AMPL_WIDTH),
conv_std_logic_vector(827,AMPL_WIDTH),
conv_std_logic_vector(827,AMPL_WIDTH),
conv_std_logic_vector(828,AMPL_WIDTH),
conv_std_logic_vector(829,AMPL_WIDTH),
conv_std_logic_vector(830,AMPL_WIDTH),
conv_std_logic_vector(830,AMPL_WIDTH),
conv_std_logic_vector(831,AMPL_WIDTH),
conv_std_logic_vector(832,AMPL_WIDTH),
conv_std_logic_vector(832,AMPL_WIDTH),
conv_std_logic_vector(833,AMPL_WIDTH),
conv_std_logic_vector(834,AMPL_WIDTH),
conv_std_logic_vector(835,AMPL_WIDTH),
conv_std_logic_vector(835,AMPL_WIDTH),
conv_std_logic_vector(836,AMPL_WIDTH),
conv_std_logic_vector(837,AMPL_WIDTH),
conv_std_logic_vector(837,AMPL_WIDTH),
conv_std_logic_vector(838,AMPL_WIDTH),
conv_std_logic_vector(839,AMPL_WIDTH),
conv_std_logic_vector(840,AMPL_WIDTH),
conv_std_logic_vector(840,AMPL_WIDTH),
conv_std_logic_vector(841,AMPL_WIDTH),
conv_std_logic_vector(842,AMPL_WIDTH),
conv_std_logic_vector(842,AMPL_WIDTH),
conv_std_logic_vector(843,AMPL_WIDTH),
conv_std_logic_vector(844,AMPL_WIDTH),
conv_std_logic_vector(845,AMPL_WIDTH),
conv_std_logic_vector(845,AMPL_WIDTH),
conv_std_logic_vector(846,AMPL_WIDTH),
conv_std_logic_vector(847,AMPL_WIDTH),
conv_std_logic_vector(847,AMPL_WIDTH),
conv_std_logic_vector(848,AMPL_WIDTH),
conv_std_logic_vector(849,AMPL_WIDTH),
conv_std_logic_vector(850,AMPL_WIDTH),
conv_std_logic_vector(850,AMPL_WIDTH),
conv_std_logic_vector(851,AMPL_WIDTH),
conv_std_logic_vector(852,AMPL_WIDTH),
conv_std_logic_vector(852,AMPL_WIDTH),
conv_std_logic_vector(853,AMPL_WIDTH),
conv_std_logic_vector(854,AMPL_WIDTH),
conv_std_logic_vector(855,AMPL_WIDTH),
conv_std_logic_vector(855,AMPL_WIDTH),
conv_std_logic_vector(856,AMPL_WIDTH),
conv_std_logic_vector(857,AMPL_WIDTH),
conv_std_logic_vector(857,AMPL_WIDTH),
conv_std_logic_vector(858,AMPL_WIDTH),
conv_std_logic_vector(859,AMPL_WIDTH),
conv_std_logic_vector(860,AMPL_WIDTH),
conv_std_logic_vector(860,AMPL_WIDTH),
conv_std_logic_vector(861,AMPL_WIDTH),
conv_std_logic_vector(862,AMPL_WIDTH),
conv_std_logic_vector(862,AMPL_WIDTH),
conv_std_logic_vector(863,AMPL_WIDTH),
conv_std_logic_vector(864,AMPL_WIDTH),
conv_std_logic_vector(865,AMPL_WIDTH),
conv_std_logic_vector(865,AMPL_WIDTH),
conv_std_logic_vector(866,AMPL_WIDTH),
conv_std_logic_vector(867,AMPL_WIDTH),
conv_std_logic_vector(867,AMPL_WIDTH),
conv_std_logic_vector(868,AMPL_WIDTH),
conv_std_logic_vector(869,AMPL_WIDTH),
conv_std_logic_vector(870,AMPL_WIDTH),
conv_std_logic_vector(870,AMPL_WIDTH),
conv_std_logic_vector(871,AMPL_WIDTH),
conv_std_logic_vector(872,AMPL_WIDTH),
conv_std_logic_vector(872,AMPL_WIDTH),
conv_std_logic_vector(873,AMPL_WIDTH),
conv_std_logic_vector(874,AMPL_WIDTH),
conv_std_logic_vector(874,AMPL_WIDTH),
conv_std_logic_vector(875,AMPL_WIDTH),
conv_std_logic_vector(876,AMPL_WIDTH),
conv_std_logic_vector(877,AMPL_WIDTH),
conv_std_logic_vector(877,AMPL_WIDTH),
conv_std_logic_vector(878,AMPL_WIDTH),
conv_std_logic_vector(879,AMPL_WIDTH),
conv_std_logic_vector(879,AMPL_WIDTH),
conv_std_logic_vector(880,AMPL_WIDTH),
conv_std_logic_vector(881,AMPL_WIDTH),
conv_std_logic_vector(882,AMPL_WIDTH),
conv_std_logic_vector(882,AMPL_WIDTH),
conv_std_logic_vector(883,AMPL_WIDTH),
conv_std_logic_vector(884,AMPL_WIDTH),
conv_std_logic_vector(884,AMPL_WIDTH),
conv_std_logic_vector(885,AMPL_WIDTH),
conv_std_logic_vector(886,AMPL_WIDTH),
conv_std_logic_vector(887,AMPL_WIDTH),
conv_std_logic_vector(887,AMPL_WIDTH),
conv_std_logic_vector(888,AMPL_WIDTH),
conv_std_logic_vector(889,AMPL_WIDTH),
conv_std_logic_vector(889,AMPL_WIDTH),
conv_std_logic_vector(890,AMPL_WIDTH),
conv_std_logic_vector(891,AMPL_WIDTH),
conv_std_logic_vector(891,AMPL_WIDTH),
conv_std_logic_vector(892,AMPL_WIDTH),
conv_std_logic_vector(893,AMPL_WIDTH),
conv_std_logic_vector(894,AMPL_WIDTH),
conv_std_logic_vector(894,AMPL_WIDTH),
conv_std_logic_vector(895,AMPL_WIDTH),
conv_std_logic_vector(896,AMPL_WIDTH),
conv_std_logic_vector(896,AMPL_WIDTH),
conv_std_logic_vector(897,AMPL_WIDTH),
conv_std_logic_vector(898,AMPL_WIDTH),
conv_std_logic_vector(899,AMPL_WIDTH),
conv_std_logic_vector(899,AMPL_WIDTH),
conv_std_logic_vector(900,AMPL_WIDTH),
conv_std_logic_vector(901,AMPL_WIDTH),
conv_std_logic_vector(901,AMPL_WIDTH),
conv_std_logic_vector(902,AMPL_WIDTH),
conv_std_logic_vector(903,AMPL_WIDTH),
conv_std_logic_vector(903,AMPL_WIDTH),
conv_std_logic_vector(904,AMPL_WIDTH),
conv_std_logic_vector(905,AMPL_WIDTH),
conv_std_logic_vector(906,AMPL_WIDTH),
conv_std_logic_vector(906,AMPL_WIDTH),
conv_std_logic_vector(907,AMPL_WIDTH),
conv_std_logic_vector(908,AMPL_WIDTH),
conv_std_logic_vector(908,AMPL_WIDTH),
conv_std_logic_vector(909,AMPL_WIDTH),
conv_std_logic_vector(910,AMPL_WIDTH),
conv_std_logic_vector(911,AMPL_WIDTH),
conv_std_logic_vector(911,AMPL_WIDTH),
conv_std_logic_vector(912,AMPL_WIDTH),
conv_std_logic_vector(913,AMPL_WIDTH),
conv_std_logic_vector(913,AMPL_WIDTH),
conv_std_logic_vector(914,AMPL_WIDTH),
conv_std_logic_vector(915,AMPL_WIDTH),
conv_std_logic_vector(915,AMPL_WIDTH),
conv_std_logic_vector(916,AMPL_WIDTH),
conv_std_logic_vector(917,AMPL_WIDTH),
conv_std_logic_vector(918,AMPL_WIDTH),
conv_std_logic_vector(918,AMPL_WIDTH),
conv_std_logic_vector(919,AMPL_WIDTH),
conv_std_logic_vector(920,AMPL_WIDTH),
conv_std_logic_vector(920,AMPL_WIDTH),
conv_std_logic_vector(921,AMPL_WIDTH),
conv_std_logic_vector(922,AMPL_WIDTH),
conv_std_logic_vector(922,AMPL_WIDTH),
conv_std_logic_vector(923,AMPL_WIDTH),
conv_std_logic_vector(924,AMPL_WIDTH),
conv_std_logic_vector(925,AMPL_WIDTH),
conv_std_logic_vector(925,AMPL_WIDTH),
conv_std_logic_vector(926,AMPL_WIDTH),
conv_std_logic_vector(927,AMPL_WIDTH),
conv_std_logic_vector(927,AMPL_WIDTH),
conv_std_logic_vector(928,AMPL_WIDTH),
conv_std_logic_vector(929,AMPL_WIDTH),
conv_std_logic_vector(929,AMPL_WIDTH),
conv_std_logic_vector(930,AMPL_WIDTH),
conv_std_logic_vector(931,AMPL_WIDTH),
conv_std_logic_vector(932,AMPL_WIDTH),
conv_std_logic_vector(932,AMPL_WIDTH),
conv_std_logic_vector(933,AMPL_WIDTH),
conv_std_logic_vector(934,AMPL_WIDTH),
conv_std_logic_vector(934,AMPL_WIDTH),
conv_std_logic_vector(935,AMPL_WIDTH),
conv_std_logic_vector(936,AMPL_WIDTH),
conv_std_logic_vector(936,AMPL_WIDTH),
conv_std_logic_vector(937,AMPL_WIDTH),
conv_std_logic_vector(938,AMPL_WIDTH),
conv_std_logic_vector(939,AMPL_WIDTH),
conv_std_logic_vector(939,AMPL_WIDTH),
conv_std_logic_vector(940,AMPL_WIDTH),
conv_std_logic_vector(941,AMPL_WIDTH),
conv_std_logic_vector(941,AMPL_WIDTH),
conv_std_logic_vector(942,AMPL_WIDTH),
conv_std_logic_vector(943,AMPL_WIDTH),
conv_std_logic_vector(943,AMPL_WIDTH),
conv_std_logic_vector(944,AMPL_WIDTH),
conv_std_logic_vector(945,AMPL_WIDTH),
conv_std_logic_vector(946,AMPL_WIDTH),
conv_std_logic_vector(946,AMPL_WIDTH),
conv_std_logic_vector(947,AMPL_WIDTH),
conv_std_logic_vector(948,AMPL_WIDTH),
conv_std_logic_vector(948,AMPL_WIDTH),
conv_std_logic_vector(949,AMPL_WIDTH),
conv_std_logic_vector(950,AMPL_WIDTH),
conv_std_logic_vector(950,AMPL_WIDTH),
conv_std_logic_vector(951,AMPL_WIDTH),
conv_std_logic_vector(952,AMPL_WIDTH),
conv_std_logic_vector(952,AMPL_WIDTH),
conv_std_logic_vector(953,AMPL_WIDTH),
conv_std_logic_vector(954,AMPL_WIDTH),
conv_std_logic_vector(955,AMPL_WIDTH),
conv_std_logic_vector(955,AMPL_WIDTH),
conv_std_logic_vector(956,AMPL_WIDTH),
conv_std_logic_vector(957,AMPL_WIDTH),
conv_std_logic_vector(957,AMPL_WIDTH),
conv_std_logic_vector(958,AMPL_WIDTH),
conv_std_logic_vector(959,AMPL_WIDTH),
conv_std_logic_vector(959,AMPL_WIDTH),
conv_std_logic_vector(960,AMPL_WIDTH),
conv_std_logic_vector(961,AMPL_WIDTH),
conv_std_logic_vector(961,AMPL_WIDTH),
conv_std_logic_vector(962,AMPL_WIDTH),
conv_std_logic_vector(963,AMPL_WIDTH),
conv_std_logic_vector(964,AMPL_WIDTH),
conv_std_logic_vector(964,AMPL_WIDTH),
conv_std_logic_vector(965,AMPL_WIDTH),
conv_std_logic_vector(966,AMPL_WIDTH),
conv_std_logic_vector(966,AMPL_WIDTH),
conv_std_logic_vector(967,AMPL_WIDTH),
conv_std_logic_vector(968,AMPL_WIDTH),
conv_std_logic_vector(968,AMPL_WIDTH),
conv_std_logic_vector(969,AMPL_WIDTH),
conv_std_logic_vector(970,AMPL_WIDTH),
conv_std_logic_vector(970,AMPL_WIDTH),
conv_std_logic_vector(971,AMPL_WIDTH),
conv_std_logic_vector(972,AMPL_WIDTH),
conv_std_logic_vector(973,AMPL_WIDTH),
conv_std_logic_vector(973,AMPL_WIDTH),
conv_std_logic_vector(974,AMPL_WIDTH),
conv_std_logic_vector(975,AMPL_WIDTH),
conv_std_logic_vector(975,AMPL_WIDTH),
conv_std_logic_vector(976,AMPL_WIDTH),
conv_std_logic_vector(977,AMPL_WIDTH),
conv_std_logic_vector(977,AMPL_WIDTH),
conv_std_logic_vector(978,AMPL_WIDTH),
conv_std_logic_vector(979,AMPL_WIDTH),
conv_std_logic_vector(979,AMPL_WIDTH),
conv_std_logic_vector(980,AMPL_WIDTH),
conv_std_logic_vector(981,AMPL_WIDTH),
conv_std_logic_vector(982,AMPL_WIDTH),
conv_std_logic_vector(982,AMPL_WIDTH),
conv_std_logic_vector(983,AMPL_WIDTH),
conv_std_logic_vector(984,AMPL_WIDTH),
conv_std_logic_vector(984,AMPL_WIDTH),
conv_std_logic_vector(985,AMPL_WIDTH),
conv_std_logic_vector(986,AMPL_WIDTH),
conv_std_logic_vector(986,AMPL_WIDTH),
conv_std_logic_vector(987,AMPL_WIDTH),
conv_std_logic_vector(988,AMPL_WIDTH),
conv_std_logic_vector(988,AMPL_WIDTH),
conv_std_logic_vector(989,AMPL_WIDTH),
conv_std_logic_vector(990,AMPL_WIDTH),
conv_std_logic_vector(990,AMPL_WIDTH),
conv_std_logic_vector(991,AMPL_WIDTH),
conv_std_logic_vector(992,AMPL_WIDTH),
conv_std_logic_vector(993,AMPL_WIDTH),
conv_std_logic_vector(993,AMPL_WIDTH),
conv_std_logic_vector(994,AMPL_WIDTH),
conv_std_logic_vector(995,AMPL_WIDTH),
conv_std_logic_vector(995,AMPL_WIDTH),
conv_std_logic_vector(996,AMPL_WIDTH),
conv_std_logic_vector(997,AMPL_WIDTH),
conv_std_logic_vector(997,AMPL_WIDTH),
conv_std_logic_vector(998,AMPL_WIDTH),
conv_std_logic_vector(999,AMPL_WIDTH),
conv_std_logic_vector(999,AMPL_WIDTH),
conv_std_logic_vector(1000,AMPL_WIDTH),
conv_std_logic_vector(1001,AMPL_WIDTH),
conv_std_logic_vector(1001,AMPL_WIDTH),
conv_std_logic_vector(1002,AMPL_WIDTH),
conv_std_logic_vector(1003,AMPL_WIDTH),
conv_std_logic_vector(1003,AMPL_WIDTH),
conv_std_logic_vector(1004,AMPL_WIDTH),
conv_std_logic_vector(1005,AMPL_WIDTH),
conv_std_logic_vector(1006,AMPL_WIDTH),
conv_std_logic_vector(1006,AMPL_WIDTH),
conv_std_logic_vector(1007,AMPL_WIDTH),
conv_std_logic_vector(1008,AMPL_WIDTH),
conv_std_logic_vector(1008,AMPL_WIDTH),
conv_std_logic_vector(1009,AMPL_WIDTH),
conv_std_logic_vector(1010,AMPL_WIDTH),
conv_std_logic_vector(1010,AMPL_WIDTH),
conv_std_logic_vector(1011,AMPL_WIDTH),
conv_std_logic_vector(1012,AMPL_WIDTH),
conv_std_logic_vector(1012,AMPL_WIDTH),
conv_std_logic_vector(1013,AMPL_WIDTH),
conv_std_logic_vector(1014,AMPL_WIDTH),
conv_std_logic_vector(1014,AMPL_WIDTH),
conv_std_logic_vector(1015,AMPL_WIDTH),
conv_std_logic_vector(1016,AMPL_WIDTH),
conv_std_logic_vector(1016,AMPL_WIDTH),
conv_std_logic_vector(1017,AMPL_WIDTH),
conv_std_logic_vector(1018,AMPL_WIDTH),
conv_std_logic_vector(1019,AMPL_WIDTH),
conv_std_logic_vector(1019,AMPL_WIDTH),
conv_std_logic_vector(1020,AMPL_WIDTH),
conv_std_logic_vector(1021,AMPL_WIDTH),
conv_std_logic_vector(1021,AMPL_WIDTH),
conv_std_logic_vector(1022,AMPL_WIDTH),
conv_std_logic_vector(1023,AMPL_WIDTH),
conv_std_logic_vector(1023,AMPL_WIDTH),
conv_std_logic_vector(1024,AMPL_WIDTH),
conv_std_logic_vector(1025,AMPL_WIDTH),
conv_std_logic_vector(1025,AMPL_WIDTH),
conv_std_logic_vector(1026,AMPL_WIDTH),
conv_std_logic_vector(1027,AMPL_WIDTH),
conv_std_logic_vector(1027,AMPL_WIDTH),
conv_std_logic_vector(1028,AMPL_WIDTH),
conv_std_logic_vector(1029,AMPL_WIDTH),
conv_std_logic_vector(1029,AMPL_WIDTH),
conv_std_logic_vector(1030,AMPL_WIDTH),
conv_std_logic_vector(1031,AMPL_WIDTH),
conv_std_logic_vector(1031,AMPL_WIDTH),
conv_std_logic_vector(1032,AMPL_WIDTH),
conv_std_logic_vector(1033,AMPL_WIDTH),
conv_std_logic_vector(1033,AMPL_WIDTH),
conv_std_logic_vector(1034,AMPL_WIDTH),
conv_std_logic_vector(1035,AMPL_WIDTH),
conv_std_logic_vector(1035,AMPL_WIDTH),
conv_std_logic_vector(1036,AMPL_WIDTH),
conv_std_logic_vector(1037,AMPL_WIDTH),
conv_std_logic_vector(1038,AMPL_WIDTH),
conv_std_logic_vector(1038,AMPL_WIDTH),
conv_std_logic_vector(1039,AMPL_WIDTH),
conv_std_logic_vector(1040,AMPL_WIDTH),
conv_std_logic_vector(1040,AMPL_WIDTH),
conv_std_logic_vector(1041,AMPL_WIDTH),
conv_std_logic_vector(1042,AMPL_WIDTH),
conv_std_logic_vector(1042,AMPL_WIDTH),
conv_std_logic_vector(1043,AMPL_WIDTH),
conv_std_logic_vector(1044,AMPL_WIDTH),
conv_std_logic_vector(1044,AMPL_WIDTH),
conv_std_logic_vector(1045,AMPL_WIDTH),
conv_std_logic_vector(1046,AMPL_WIDTH),
conv_std_logic_vector(1046,AMPL_WIDTH),
conv_std_logic_vector(1047,AMPL_WIDTH),
conv_std_logic_vector(1048,AMPL_WIDTH),
conv_std_logic_vector(1048,AMPL_WIDTH),
conv_std_logic_vector(1049,AMPL_WIDTH),
conv_std_logic_vector(1050,AMPL_WIDTH),
conv_std_logic_vector(1050,AMPL_WIDTH),
conv_std_logic_vector(1051,AMPL_WIDTH),
conv_std_logic_vector(1052,AMPL_WIDTH),
conv_std_logic_vector(1052,AMPL_WIDTH),
conv_std_logic_vector(1053,AMPL_WIDTH),
conv_std_logic_vector(1054,AMPL_WIDTH),
conv_std_logic_vector(1054,AMPL_WIDTH),
conv_std_logic_vector(1055,AMPL_WIDTH),
conv_std_logic_vector(1056,AMPL_WIDTH),
conv_std_logic_vector(1056,AMPL_WIDTH),
conv_std_logic_vector(1057,AMPL_WIDTH),
conv_std_logic_vector(1058,AMPL_WIDTH),
conv_std_logic_vector(1058,AMPL_WIDTH),
conv_std_logic_vector(1059,AMPL_WIDTH),
conv_std_logic_vector(1060,AMPL_WIDTH),
conv_std_logic_vector(1060,AMPL_WIDTH),
conv_std_logic_vector(1061,AMPL_WIDTH),
conv_std_logic_vector(1062,AMPL_WIDTH),
conv_std_logic_vector(1062,AMPL_WIDTH),
conv_std_logic_vector(1063,AMPL_WIDTH),
conv_std_logic_vector(1064,AMPL_WIDTH),
conv_std_logic_vector(1064,AMPL_WIDTH),
conv_std_logic_vector(1065,AMPL_WIDTH),
conv_std_logic_vector(1066,AMPL_WIDTH),
conv_std_logic_vector(1066,AMPL_WIDTH),
conv_std_logic_vector(1067,AMPL_WIDTH),
conv_std_logic_vector(1068,AMPL_WIDTH),
conv_std_logic_vector(1068,AMPL_WIDTH),
conv_std_logic_vector(1069,AMPL_WIDTH),
conv_std_logic_vector(1070,AMPL_WIDTH),
conv_std_logic_vector(1070,AMPL_WIDTH),
conv_std_logic_vector(1071,AMPL_WIDTH),
conv_std_logic_vector(1072,AMPL_WIDTH),
conv_std_logic_vector(1072,AMPL_WIDTH),
conv_std_logic_vector(1073,AMPL_WIDTH),
conv_std_logic_vector(1074,AMPL_WIDTH),
conv_std_logic_vector(1075,AMPL_WIDTH),
conv_std_logic_vector(1075,AMPL_WIDTH),
conv_std_logic_vector(1076,AMPL_WIDTH),
conv_std_logic_vector(1077,AMPL_WIDTH),
conv_std_logic_vector(1077,AMPL_WIDTH),
conv_std_logic_vector(1078,AMPL_WIDTH),
conv_std_logic_vector(1079,AMPL_WIDTH),
conv_std_logic_vector(1079,AMPL_WIDTH),
conv_std_logic_vector(1080,AMPL_WIDTH),
conv_std_logic_vector(1081,AMPL_WIDTH),
conv_std_logic_vector(1081,AMPL_WIDTH),
conv_std_logic_vector(1082,AMPL_WIDTH),
conv_std_logic_vector(1083,AMPL_WIDTH),
conv_std_logic_vector(1083,AMPL_WIDTH),
conv_std_logic_vector(1084,AMPL_WIDTH),
conv_std_logic_vector(1085,AMPL_WIDTH),
conv_std_logic_vector(1085,AMPL_WIDTH),
conv_std_logic_vector(1086,AMPL_WIDTH),
conv_std_logic_vector(1087,AMPL_WIDTH),
conv_std_logic_vector(1087,AMPL_WIDTH),
conv_std_logic_vector(1088,AMPL_WIDTH),
conv_std_logic_vector(1088,AMPL_WIDTH),
conv_std_logic_vector(1089,AMPL_WIDTH),
conv_std_logic_vector(1090,AMPL_WIDTH),
conv_std_logic_vector(1090,AMPL_WIDTH),
conv_std_logic_vector(1091,AMPL_WIDTH),
conv_std_logic_vector(1092,AMPL_WIDTH),
conv_std_logic_vector(1092,AMPL_WIDTH),
conv_std_logic_vector(1093,AMPL_WIDTH),
conv_std_logic_vector(1094,AMPL_WIDTH),
conv_std_logic_vector(1094,AMPL_WIDTH),
conv_std_logic_vector(1095,AMPL_WIDTH),
conv_std_logic_vector(1096,AMPL_WIDTH),
conv_std_logic_vector(1096,AMPL_WIDTH),
conv_std_logic_vector(1097,AMPL_WIDTH),
conv_std_logic_vector(1098,AMPL_WIDTH),
conv_std_logic_vector(1098,AMPL_WIDTH),
conv_std_logic_vector(1099,AMPL_WIDTH),
conv_std_logic_vector(1100,AMPL_WIDTH),
conv_std_logic_vector(1100,AMPL_WIDTH),
conv_std_logic_vector(1101,AMPL_WIDTH),
conv_std_logic_vector(1102,AMPL_WIDTH),
conv_std_logic_vector(1102,AMPL_WIDTH),
conv_std_logic_vector(1103,AMPL_WIDTH),
conv_std_logic_vector(1104,AMPL_WIDTH),
conv_std_logic_vector(1104,AMPL_WIDTH),
conv_std_logic_vector(1105,AMPL_WIDTH),
conv_std_logic_vector(1106,AMPL_WIDTH),
conv_std_logic_vector(1106,AMPL_WIDTH),
conv_std_logic_vector(1107,AMPL_WIDTH),
conv_std_logic_vector(1108,AMPL_WIDTH),
conv_std_logic_vector(1108,AMPL_WIDTH),
conv_std_logic_vector(1109,AMPL_WIDTH),
conv_std_logic_vector(1110,AMPL_WIDTH),
conv_std_logic_vector(1110,AMPL_WIDTH),
conv_std_logic_vector(1111,AMPL_WIDTH),
conv_std_logic_vector(1112,AMPL_WIDTH),
conv_std_logic_vector(1112,AMPL_WIDTH),
conv_std_logic_vector(1113,AMPL_WIDTH),
conv_std_logic_vector(1114,AMPL_WIDTH),
conv_std_logic_vector(1114,AMPL_WIDTH),
conv_std_logic_vector(1115,AMPL_WIDTH),
conv_std_logic_vector(1116,AMPL_WIDTH),
conv_std_logic_vector(1116,AMPL_WIDTH),
conv_std_logic_vector(1117,AMPL_WIDTH),
conv_std_logic_vector(1118,AMPL_WIDTH),
conv_std_logic_vector(1118,AMPL_WIDTH),
conv_std_logic_vector(1119,AMPL_WIDTH),
conv_std_logic_vector(1120,AMPL_WIDTH),
conv_std_logic_vector(1120,AMPL_WIDTH),
conv_std_logic_vector(1121,AMPL_WIDTH),
conv_std_logic_vector(1122,AMPL_WIDTH),
conv_std_logic_vector(1122,AMPL_WIDTH),
conv_std_logic_vector(1123,AMPL_WIDTH),
conv_std_logic_vector(1124,AMPL_WIDTH),
conv_std_logic_vector(1124,AMPL_WIDTH),
conv_std_logic_vector(1125,AMPL_WIDTH),
conv_std_logic_vector(1125,AMPL_WIDTH),
conv_std_logic_vector(1126,AMPL_WIDTH),
conv_std_logic_vector(1127,AMPL_WIDTH),
conv_std_logic_vector(1127,AMPL_WIDTH),
conv_std_logic_vector(1128,AMPL_WIDTH),
conv_std_logic_vector(1129,AMPL_WIDTH),
conv_std_logic_vector(1129,AMPL_WIDTH),
conv_std_logic_vector(1130,AMPL_WIDTH),
conv_std_logic_vector(1131,AMPL_WIDTH),
conv_std_logic_vector(1131,AMPL_WIDTH),
conv_std_logic_vector(1132,AMPL_WIDTH),
conv_std_logic_vector(1133,AMPL_WIDTH),
conv_std_logic_vector(1133,AMPL_WIDTH),
conv_std_logic_vector(1134,AMPL_WIDTH),
conv_std_logic_vector(1135,AMPL_WIDTH),
conv_std_logic_vector(1135,AMPL_WIDTH),
conv_std_logic_vector(1136,AMPL_WIDTH),
conv_std_logic_vector(1137,AMPL_WIDTH),
conv_std_logic_vector(1137,AMPL_WIDTH),
conv_std_logic_vector(1138,AMPL_WIDTH),
conv_std_logic_vector(1139,AMPL_WIDTH),
conv_std_logic_vector(1139,AMPL_WIDTH),
conv_std_logic_vector(1140,AMPL_WIDTH),
conv_std_logic_vector(1141,AMPL_WIDTH),
conv_std_logic_vector(1141,AMPL_WIDTH),
conv_std_logic_vector(1142,AMPL_WIDTH),
conv_std_logic_vector(1142,AMPL_WIDTH),
conv_std_logic_vector(1143,AMPL_WIDTH),
conv_std_logic_vector(1144,AMPL_WIDTH),
conv_std_logic_vector(1144,AMPL_WIDTH),
conv_std_logic_vector(1145,AMPL_WIDTH),
conv_std_logic_vector(1146,AMPL_WIDTH),
conv_std_logic_vector(1146,AMPL_WIDTH),
conv_std_logic_vector(1147,AMPL_WIDTH),
conv_std_logic_vector(1148,AMPL_WIDTH),
conv_std_logic_vector(1148,AMPL_WIDTH),
conv_std_logic_vector(1149,AMPL_WIDTH),
conv_std_logic_vector(1150,AMPL_WIDTH),
conv_std_logic_vector(1150,AMPL_WIDTH),
conv_std_logic_vector(1151,AMPL_WIDTH),
conv_std_logic_vector(1152,AMPL_WIDTH),
conv_std_logic_vector(1152,AMPL_WIDTH),
conv_std_logic_vector(1153,AMPL_WIDTH),
conv_std_logic_vector(1154,AMPL_WIDTH),
conv_std_logic_vector(1154,AMPL_WIDTH),
conv_std_logic_vector(1155,AMPL_WIDTH),
conv_std_logic_vector(1155,AMPL_WIDTH),
conv_std_logic_vector(1156,AMPL_WIDTH),
conv_std_logic_vector(1157,AMPL_WIDTH),
conv_std_logic_vector(1157,AMPL_WIDTH),
conv_std_logic_vector(1158,AMPL_WIDTH),
conv_std_logic_vector(1159,AMPL_WIDTH),
conv_std_logic_vector(1159,AMPL_WIDTH),
conv_std_logic_vector(1160,AMPL_WIDTH),
conv_std_logic_vector(1161,AMPL_WIDTH),
conv_std_logic_vector(1161,AMPL_WIDTH),
conv_std_logic_vector(1162,AMPL_WIDTH),
conv_std_logic_vector(1163,AMPL_WIDTH),
conv_std_logic_vector(1163,AMPL_WIDTH),
conv_std_logic_vector(1164,AMPL_WIDTH),
conv_std_logic_vector(1165,AMPL_WIDTH),
conv_std_logic_vector(1165,AMPL_WIDTH),
conv_std_logic_vector(1166,AMPL_WIDTH),
conv_std_logic_vector(1166,AMPL_WIDTH),
conv_std_logic_vector(1167,AMPL_WIDTH),
conv_std_logic_vector(1168,AMPL_WIDTH),
conv_std_logic_vector(1168,AMPL_WIDTH),
conv_std_logic_vector(1169,AMPL_WIDTH),
conv_std_logic_vector(1170,AMPL_WIDTH),
conv_std_logic_vector(1170,AMPL_WIDTH),
conv_std_logic_vector(1171,AMPL_WIDTH),
conv_std_logic_vector(1172,AMPL_WIDTH),
conv_std_logic_vector(1172,AMPL_WIDTH),
conv_std_logic_vector(1173,AMPL_WIDTH),
conv_std_logic_vector(1174,AMPL_WIDTH),
conv_std_logic_vector(1174,AMPL_WIDTH),
conv_std_logic_vector(1175,AMPL_WIDTH),
conv_std_logic_vector(1175,AMPL_WIDTH),
conv_std_logic_vector(1176,AMPL_WIDTH),
conv_std_logic_vector(1177,AMPL_WIDTH),
conv_std_logic_vector(1177,AMPL_WIDTH),
conv_std_logic_vector(1178,AMPL_WIDTH),
conv_std_logic_vector(1179,AMPL_WIDTH),
conv_std_logic_vector(1179,AMPL_WIDTH),
conv_std_logic_vector(1180,AMPL_WIDTH),
conv_std_logic_vector(1181,AMPL_WIDTH),
conv_std_logic_vector(1181,AMPL_WIDTH),
conv_std_logic_vector(1182,AMPL_WIDTH),
conv_std_logic_vector(1183,AMPL_WIDTH),
conv_std_logic_vector(1183,AMPL_WIDTH),
conv_std_logic_vector(1184,AMPL_WIDTH),
conv_std_logic_vector(1184,AMPL_WIDTH),
conv_std_logic_vector(1185,AMPL_WIDTH),
conv_std_logic_vector(1186,AMPL_WIDTH),
conv_std_logic_vector(1186,AMPL_WIDTH),
conv_std_logic_vector(1187,AMPL_WIDTH),
conv_std_logic_vector(1188,AMPL_WIDTH),
conv_std_logic_vector(1188,AMPL_WIDTH),
conv_std_logic_vector(1189,AMPL_WIDTH),
conv_std_logic_vector(1190,AMPL_WIDTH),
conv_std_logic_vector(1190,AMPL_WIDTH),
conv_std_logic_vector(1191,AMPL_WIDTH),
conv_std_logic_vector(1191,AMPL_WIDTH),
conv_std_logic_vector(1192,AMPL_WIDTH),
conv_std_logic_vector(1193,AMPL_WIDTH),
conv_std_logic_vector(1193,AMPL_WIDTH),
conv_std_logic_vector(1194,AMPL_WIDTH),
conv_std_logic_vector(1195,AMPL_WIDTH),
conv_std_logic_vector(1195,AMPL_WIDTH),
conv_std_logic_vector(1196,AMPL_WIDTH),
conv_std_logic_vector(1197,AMPL_WIDTH),
conv_std_logic_vector(1197,AMPL_WIDTH),
conv_std_logic_vector(1198,AMPL_WIDTH),
conv_std_logic_vector(1198,AMPL_WIDTH),
conv_std_logic_vector(1199,AMPL_WIDTH),
conv_std_logic_vector(1200,AMPL_WIDTH),
conv_std_logic_vector(1200,AMPL_WIDTH),
conv_std_logic_vector(1201,AMPL_WIDTH),
conv_std_logic_vector(1202,AMPL_WIDTH),
conv_std_logic_vector(1202,AMPL_WIDTH),
conv_std_logic_vector(1203,AMPL_WIDTH),
conv_std_logic_vector(1204,AMPL_WIDTH),
conv_std_logic_vector(1204,AMPL_WIDTH),
conv_std_logic_vector(1205,AMPL_WIDTH),
conv_std_logic_vector(1205,AMPL_WIDTH),
conv_std_logic_vector(1206,AMPL_WIDTH),
conv_std_logic_vector(1207,AMPL_WIDTH),
conv_std_logic_vector(1207,AMPL_WIDTH),
conv_std_logic_vector(1208,AMPL_WIDTH),
conv_std_logic_vector(1209,AMPL_WIDTH),
conv_std_logic_vector(1209,AMPL_WIDTH),
conv_std_logic_vector(1210,AMPL_WIDTH),
conv_std_logic_vector(1211,AMPL_WIDTH),
conv_std_logic_vector(1211,AMPL_WIDTH),
conv_std_logic_vector(1212,AMPL_WIDTH),
conv_std_logic_vector(1212,AMPL_WIDTH),
conv_std_logic_vector(1213,AMPL_WIDTH),
conv_std_logic_vector(1214,AMPL_WIDTH),
conv_std_logic_vector(1214,AMPL_WIDTH),
conv_std_logic_vector(1215,AMPL_WIDTH),
conv_std_logic_vector(1216,AMPL_WIDTH),
conv_std_logic_vector(1216,AMPL_WIDTH),
conv_std_logic_vector(1217,AMPL_WIDTH),
conv_std_logic_vector(1218,AMPL_WIDTH),
conv_std_logic_vector(1218,AMPL_WIDTH),
conv_std_logic_vector(1219,AMPL_WIDTH),
conv_std_logic_vector(1219,AMPL_WIDTH),
conv_std_logic_vector(1220,AMPL_WIDTH),
conv_std_logic_vector(1221,AMPL_WIDTH),
conv_std_logic_vector(1221,AMPL_WIDTH),
conv_std_logic_vector(1222,AMPL_WIDTH),
conv_std_logic_vector(1223,AMPL_WIDTH),
conv_std_logic_vector(1223,AMPL_WIDTH),
conv_std_logic_vector(1224,AMPL_WIDTH),
conv_std_logic_vector(1224,AMPL_WIDTH),
conv_std_logic_vector(1225,AMPL_WIDTH),
conv_std_logic_vector(1226,AMPL_WIDTH),
conv_std_logic_vector(1226,AMPL_WIDTH),
conv_std_logic_vector(1227,AMPL_WIDTH),
conv_std_logic_vector(1228,AMPL_WIDTH),
conv_std_logic_vector(1228,AMPL_WIDTH),
conv_std_logic_vector(1229,AMPL_WIDTH),
conv_std_logic_vector(1229,AMPL_WIDTH),
conv_std_logic_vector(1230,AMPL_WIDTH),
conv_std_logic_vector(1231,AMPL_WIDTH),
conv_std_logic_vector(1231,AMPL_WIDTH),
conv_std_logic_vector(1232,AMPL_WIDTH),
conv_std_logic_vector(1233,AMPL_WIDTH),
conv_std_logic_vector(1233,AMPL_WIDTH),
conv_std_logic_vector(1234,AMPL_WIDTH),
conv_std_logic_vector(1234,AMPL_WIDTH),
conv_std_logic_vector(1235,AMPL_WIDTH),
conv_std_logic_vector(1236,AMPL_WIDTH),
conv_std_logic_vector(1236,AMPL_WIDTH),
conv_std_logic_vector(1237,AMPL_WIDTH),
conv_std_logic_vector(1238,AMPL_WIDTH),
conv_std_logic_vector(1238,AMPL_WIDTH),
conv_std_logic_vector(1239,AMPL_WIDTH),
conv_std_logic_vector(1239,AMPL_WIDTH),
conv_std_logic_vector(1240,AMPL_WIDTH),
conv_std_logic_vector(1241,AMPL_WIDTH),
conv_std_logic_vector(1241,AMPL_WIDTH),
conv_std_logic_vector(1242,AMPL_WIDTH),
conv_std_logic_vector(1243,AMPL_WIDTH),
conv_std_logic_vector(1243,AMPL_WIDTH),
conv_std_logic_vector(1244,AMPL_WIDTH),
conv_std_logic_vector(1244,AMPL_WIDTH),
conv_std_logic_vector(1245,AMPL_WIDTH),
conv_std_logic_vector(1246,AMPL_WIDTH),
conv_std_logic_vector(1246,AMPL_WIDTH),
conv_std_logic_vector(1247,AMPL_WIDTH),
conv_std_logic_vector(1248,AMPL_WIDTH),
conv_std_logic_vector(1248,AMPL_WIDTH),
conv_std_logic_vector(1249,AMPL_WIDTH),
conv_std_logic_vector(1249,AMPL_WIDTH),
conv_std_logic_vector(1250,AMPL_WIDTH),
conv_std_logic_vector(1251,AMPL_WIDTH),
conv_std_logic_vector(1251,AMPL_WIDTH),
conv_std_logic_vector(1252,AMPL_WIDTH),
conv_std_logic_vector(1253,AMPL_WIDTH),
conv_std_logic_vector(1253,AMPL_WIDTH),
conv_std_logic_vector(1254,AMPL_WIDTH),
conv_std_logic_vector(1254,AMPL_WIDTH),
conv_std_logic_vector(1255,AMPL_WIDTH),
conv_std_logic_vector(1256,AMPL_WIDTH),
conv_std_logic_vector(1256,AMPL_WIDTH),
conv_std_logic_vector(1257,AMPL_WIDTH),
conv_std_logic_vector(1258,AMPL_WIDTH),
conv_std_logic_vector(1258,AMPL_WIDTH),
conv_std_logic_vector(1259,AMPL_WIDTH),
conv_std_logic_vector(1259,AMPL_WIDTH),
conv_std_logic_vector(1260,AMPL_WIDTH),
conv_std_logic_vector(1261,AMPL_WIDTH),
conv_std_logic_vector(1261,AMPL_WIDTH),
conv_std_logic_vector(1262,AMPL_WIDTH),
conv_std_logic_vector(1262,AMPL_WIDTH),
conv_std_logic_vector(1263,AMPL_WIDTH),
conv_std_logic_vector(1264,AMPL_WIDTH),
conv_std_logic_vector(1264,AMPL_WIDTH),
conv_std_logic_vector(1265,AMPL_WIDTH),
conv_std_logic_vector(1266,AMPL_WIDTH),
conv_std_logic_vector(1266,AMPL_WIDTH),
conv_std_logic_vector(1267,AMPL_WIDTH),
conv_std_logic_vector(1267,AMPL_WIDTH),
conv_std_logic_vector(1268,AMPL_WIDTH),
conv_std_logic_vector(1269,AMPL_WIDTH),
conv_std_logic_vector(1269,AMPL_WIDTH),
conv_std_logic_vector(1270,AMPL_WIDTH),
conv_std_logic_vector(1270,AMPL_WIDTH),
conv_std_logic_vector(1271,AMPL_WIDTH),
conv_std_logic_vector(1272,AMPL_WIDTH),
conv_std_logic_vector(1272,AMPL_WIDTH),
conv_std_logic_vector(1273,AMPL_WIDTH),
conv_std_logic_vector(1274,AMPL_WIDTH),
conv_std_logic_vector(1274,AMPL_WIDTH),
conv_std_logic_vector(1275,AMPL_WIDTH),
conv_std_logic_vector(1275,AMPL_WIDTH),
conv_std_logic_vector(1276,AMPL_WIDTH),
conv_std_logic_vector(1277,AMPL_WIDTH),
conv_std_logic_vector(1277,AMPL_WIDTH),
conv_std_logic_vector(1278,AMPL_WIDTH),
conv_std_logic_vector(1278,AMPL_WIDTH),
conv_std_logic_vector(1279,AMPL_WIDTH),
conv_std_logic_vector(1280,AMPL_WIDTH),
conv_std_logic_vector(1280,AMPL_WIDTH),
conv_std_logic_vector(1281,AMPL_WIDTH),
conv_std_logic_vector(1282,AMPL_WIDTH),
conv_std_logic_vector(1282,AMPL_WIDTH),
conv_std_logic_vector(1283,AMPL_WIDTH),
conv_std_logic_vector(1283,AMPL_WIDTH),
conv_std_logic_vector(1284,AMPL_WIDTH),
conv_std_logic_vector(1285,AMPL_WIDTH),
conv_std_logic_vector(1285,AMPL_WIDTH),
conv_std_logic_vector(1286,AMPL_WIDTH),
conv_std_logic_vector(1286,AMPL_WIDTH),
conv_std_logic_vector(1287,AMPL_WIDTH),
conv_std_logic_vector(1288,AMPL_WIDTH),
conv_std_logic_vector(1288,AMPL_WIDTH),
conv_std_logic_vector(1289,AMPL_WIDTH),
conv_std_logic_vector(1289,AMPL_WIDTH),
conv_std_logic_vector(1290,AMPL_WIDTH),
conv_std_logic_vector(1291,AMPL_WIDTH),
conv_std_logic_vector(1291,AMPL_WIDTH),
conv_std_logic_vector(1292,AMPL_WIDTH),
conv_std_logic_vector(1293,AMPL_WIDTH),
conv_std_logic_vector(1293,AMPL_WIDTH),
conv_std_logic_vector(1294,AMPL_WIDTH),
conv_std_logic_vector(1294,AMPL_WIDTH),
conv_std_logic_vector(1295,AMPL_WIDTH),
conv_std_logic_vector(1296,AMPL_WIDTH),
conv_std_logic_vector(1296,AMPL_WIDTH),
conv_std_logic_vector(1297,AMPL_WIDTH),
conv_std_logic_vector(1297,AMPL_WIDTH),
conv_std_logic_vector(1298,AMPL_WIDTH),
conv_std_logic_vector(1299,AMPL_WIDTH),
conv_std_logic_vector(1299,AMPL_WIDTH),
conv_std_logic_vector(1300,AMPL_WIDTH),
conv_std_logic_vector(1300,AMPL_WIDTH),
conv_std_logic_vector(1301,AMPL_WIDTH),
conv_std_logic_vector(1302,AMPL_WIDTH),
conv_std_logic_vector(1302,AMPL_WIDTH),
conv_std_logic_vector(1303,AMPL_WIDTH),
conv_std_logic_vector(1303,AMPL_WIDTH),
conv_std_logic_vector(1304,AMPL_WIDTH),
conv_std_logic_vector(1305,AMPL_WIDTH),
conv_std_logic_vector(1305,AMPL_WIDTH),
conv_std_logic_vector(1306,AMPL_WIDTH),
conv_std_logic_vector(1306,AMPL_WIDTH),
conv_std_logic_vector(1307,AMPL_WIDTH),
conv_std_logic_vector(1308,AMPL_WIDTH),
conv_std_logic_vector(1308,AMPL_WIDTH),
conv_std_logic_vector(1309,AMPL_WIDTH),
conv_std_logic_vector(1309,AMPL_WIDTH),
conv_std_logic_vector(1310,AMPL_WIDTH),
conv_std_logic_vector(1311,AMPL_WIDTH),
conv_std_logic_vector(1311,AMPL_WIDTH),
conv_std_logic_vector(1312,AMPL_WIDTH),
conv_std_logic_vector(1313,AMPL_WIDTH),
conv_std_logic_vector(1313,AMPL_WIDTH),
conv_std_logic_vector(1314,AMPL_WIDTH),
conv_std_logic_vector(1314,AMPL_WIDTH),
conv_std_logic_vector(1315,AMPL_WIDTH),
conv_std_logic_vector(1316,AMPL_WIDTH),
conv_std_logic_vector(1316,AMPL_WIDTH),
conv_std_logic_vector(1317,AMPL_WIDTH),
conv_std_logic_vector(1317,AMPL_WIDTH),
conv_std_logic_vector(1318,AMPL_WIDTH),
conv_std_logic_vector(1319,AMPL_WIDTH),
conv_std_logic_vector(1319,AMPL_WIDTH),
conv_std_logic_vector(1320,AMPL_WIDTH),
conv_std_logic_vector(1320,AMPL_WIDTH),
conv_std_logic_vector(1321,AMPL_WIDTH),
conv_std_logic_vector(1322,AMPL_WIDTH),
conv_std_logic_vector(1322,AMPL_WIDTH),
conv_std_logic_vector(1323,AMPL_WIDTH),
conv_std_logic_vector(1323,AMPL_WIDTH),
conv_std_logic_vector(1324,AMPL_WIDTH),
conv_std_logic_vector(1325,AMPL_WIDTH),
conv_std_logic_vector(1325,AMPL_WIDTH),
conv_std_logic_vector(1326,AMPL_WIDTH),
conv_std_logic_vector(1326,AMPL_WIDTH),
conv_std_logic_vector(1327,AMPL_WIDTH),
conv_std_logic_vector(1328,AMPL_WIDTH),
conv_std_logic_vector(1328,AMPL_WIDTH),
conv_std_logic_vector(1329,AMPL_WIDTH),
conv_std_logic_vector(1329,AMPL_WIDTH),
conv_std_logic_vector(1330,AMPL_WIDTH),
conv_std_logic_vector(1330,AMPL_WIDTH),
conv_std_logic_vector(1331,AMPL_WIDTH),
conv_std_logic_vector(1332,AMPL_WIDTH),
conv_std_logic_vector(1332,AMPL_WIDTH),
conv_std_logic_vector(1333,AMPL_WIDTH),
conv_std_logic_vector(1333,AMPL_WIDTH),
conv_std_logic_vector(1334,AMPL_WIDTH),
conv_std_logic_vector(1335,AMPL_WIDTH),
conv_std_logic_vector(1335,AMPL_WIDTH),
conv_std_logic_vector(1336,AMPL_WIDTH),
conv_std_logic_vector(1336,AMPL_WIDTH),
conv_std_logic_vector(1337,AMPL_WIDTH),
conv_std_logic_vector(1338,AMPL_WIDTH),
conv_std_logic_vector(1338,AMPL_WIDTH),
conv_std_logic_vector(1339,AMPL_WIDTH),
conv_std_logic_vector(1339,AMPL_WIDTH),
conv_std_logic_vector(1340,AMPL_WIDTH),
conv_std_logic_vector(1341,AMPL_WIDTH),
conv_std_logic_vector(1341,AMPL_WIDTH),
conv_std_logic_vector(1342,AMPL_WIDTH),
conv_std_logic_vector(1342,AMPL_WIDTH),
conv_std_logic_vector(1343,AMPL_WIDTH),
conv_std_logic_vector(1344,AMPL_WIDTH),
conv_std_logic_vector(1344,AMPL_WIDTH),
conv_std_logic_vector(1345,AMPL_WIDTH),
conv_std_logic_vector(1345,AMPL_WIDTH),
conv_std_logic_vector(1346,AMPL_WIDTH),
conv_std_logic_vector(1347,AMPL_WIDTH),
conv_std_logic_vector(1347,AMPL_WIDTH),
conv_std_logic_vector(1348,AMPL_WIDTH),
conv_std_logic_vector(1348,AMPL_WIDTH),
conv_std_logic_vector(1349,AMPL_WIDTH),
conv_std_logic_vector(1349,AMPL_WIDTH),
conv_std_logic_vector(1350,AMPL_WIDTH),
conv_std_logic_vector(1351,AMPL_WIDTH),
conv_std_logic_vector(1351,AMPL_WIDTH),
conv_std_logic_vector(1352,AMPL_WIDTH),
conv_std_logic_vector(1352,AMPL_WIDTH),
conv_std_logic_vector(1353,AMPL_WIDTH),
conv_std_logic_vector(1354,AMPL_WIDTH),
conv_std_logic_vector(1354,AMPL_WIDTH),
conv_std_logic_vector(1355,AMPL_WIDTH),
conv_std_logic_vector(1355,AMPL_WIDTH),
conv_std_logic_vector(1356,AMPL_WIDTH),
conv_std_logic_vector(1357,AMPL_WIDTH),
conv_std_logic_vector(1357,AMPL_WIDTH),
conv_std_logic_vector(1358,AMPL_WIDTH),
conv_std_logic_vector(1358,AMPL_WIDTH),
conv_std_logic_vector(1359,AMPL_WIDTH),
conv_std_logic_vector(1359,AMPL_WIDTH),
conv_std_logic_vector(1360,AMPL_WIDTH),
conv_std_logic_vector(1361,AMPL_WIDTH),
conv_std_logic_vector(1361,AMPL_WIDTH),
conv_std_logic_vector(1362,AMPL_WIDTH),
conv_std_logic_vector(1362,AMPL_WIDTH),
conv_std_logic_vector(1363,AMPL_WIDTH),
conv_std_logic_vector(1364,AMPL_WIDTH),
conv_std_logic_vector(1364,AMPL_WIDTH),
conv_std_logic_vector(1365,AMPL_WIDTH),
conv_std_logic_vector(1365,AMPL_WIDTH),
conv_std_logic_vector(1366,AMPL_WIDTH),
conv_std_logic_vector(1367,AMPL_WIDTH),
conv_std_logic_vector(1367,AMPL_WIDTH),
conv_std_logic_vector(1368,AMPL_WIDTH),
conv_std_logic_vector(1368,AMPL_WIDTH),
conv_std_logic_vector(1369,AMPL_WIDTH),
conv_std_logic_vector(1369,AMPL_WIDTH),
conv_std_logic_vector(1370,AMPL_WIDTH),
conv_std_logic_vector(1371,AMPL_WIDTH),
conv_std_logic_vector(1371,AMPL_WIDTH),
conv_std_logic_vector(1372,AMPL_WIDTH),
conv_std_logic_vector(1372,AMPL_WIDTH),
conv_std_logic_vector(1373,AMPL_WIDTH),
conv_std_logic_vector(1374,AMPL_WIDTH),
conv_std_logic_vector(1374,AMPL_WIDTH),
conv_std_logic_vector(1375,AMPL_WIDTH),
conv_std_logic_vector(1375,AMPL_WIDTH),
conv_std_logic_vector(1376,AMPL_WIDTH),
conv_std_logic_vector(1376,AMPL_WIDTH),
conv_std_logic_vector(1377,AMPL_WIDTH),
conv_std_logic_vector(1378,AMPL_WIDTH),
conv_std_logic_vector(1378,AMPL_WIDTH),
conv_std_logic_vector(1379,AMPL_WIDTH),
conv_std_logic_vector(1379,AMPL_WIDTH),
conv_std_logic_vector(1380,AMPL_WIDTH),
conv_std_logic_vector(1380,AMPL_WIDTH),
conv_std_logic_vector(1381,AMPL_WIDTH),
conv_std_logic_vector(1382,AMPL_WIDTH),
conv_std_logic_vector(1382,AMPL_WIDTH),
conv_std_logic_vector(1383,AMPL_WIDTH),
conv_std_logic_vector(1383,AMPL_WIDTH),
conv_std_logic_vector(1384,AMPL_WIDTH),
conv_std_logic_vector(1385,AMPL_WIDTH),
conv_std_logic_vector(1385,AMPL_WIDTH),
conv_std_logic_vector(1386,AMPL_WIDTH),
conv_std_logic_vector(1386,AMPL_WIDTH),
conv_std_logic_vector(1387,AMPL_WIDTH),
conv_std_logic_vector(1387,AMPL_WIDTH),
conv_std_logic_vector(1388,AMPL_WIDTH),
conv_std_logic_vector(1389,AMPL_WIDTH),
conv_std_logic_vector(1389,AMPL_WIDTH),
conv_std_logic_vector(1390,AMPL_WIDTH),
conv_std_logic_vector(1390,AMPL_WIDTH),
conv_std_logic_vector(1391,AMPL_WIDTH),
conv_std_logic_vector(1391,AMPL_WIDTH),
conv_std_logic_vector(1392,AMPL_WIDTH),
conv_std_logic_vector(1393,AMPL_WIDTH),
conv_std_logic_vector(1393,AMPL_WIDTH),
conv_std_logic_vector(1394,AMPL_WIDTH),
conv_std_logic_vector(1394,AMPL_WIDTH),
conv_std_logic_vector(1395,AMPL_WIDTH),
conv_std_logic_vector(1395,AMPL_WIDTH),
conv_std_logic_vector(1396,AMPL_WIDTH),
conv_std_logic_vector(1397,AMPL_WIDTH),
conv_std_logic_vector(1397,AMPL_WIDTH),
conv_std_logic_vector(1398,AMPL_WIDTH),
conv_std_logic_vector(1398,AMPL_WIDTH),
conv_std_logic_vector(1399,AMPL_WIDTH),
conv_std_logic_vector(1400,AMPL_WIDTH),
conv_std_logic_vector(1400,AMPL_WIDTH),
conv_std_logic_vector(1401,AMPL_WIDTH),
conv_std_logic_vector(1401,AMPL_WIDTH),
conv_std_logic_vector(1402,AMPL_WIDTH),
conv_std_logic_vector(1402,AMPL_WIDTH),
conv_std_logic_vector(1403,AMPL_WIDTH),
conv_std_logic_vector(1404,AMPL_WIDTH),
conv_std_logic_vector(1404,AMPL_WIDTH),
conv_std_logic_vector(1405,AMPL_WIDTH),
conv_std_logic_vector(1405,AMPL_WIDTH),
conv_std_logic_vector(1406,AMPL_WIDTH),
conv_std_logic_vector(1406,AMPL_WIDTH),
conv_std_logic_vector(1407,AMPL_WIDTH),
conv_std_logic_vector(1408,AMPL_WIDTH),
conv_std_logic_vector(1408,AMPL_WIDTH),
conv_std_logic_vector(1409,AMPL_WIDTH),
conv_std_logic_vector(1409,AMPL_WIDTH),
conv_std_logic_vector(1410,AMPL_WIDTH),
conv_std_logic_vector(1410,AMPL_WIDTH),
conv_std_logic_vector(1411,AMPL_WIDTH),
conv_std_logic_vector(1411,AMPL_WIDTH),
conv_std_logic_vector(1412,AMPL_WIDTH),
conv_std_logic_vector(1413,AMPL_WIDTH),
conv_std_logic_vector(1413,AMPL_WIDTH),
conv_std_logic_vector(1414,AMPL_WIDTH),
conv_std_logic_vector(1414,AMPL_WIDTH),
conv_std_logic_vector(1415,AMPL_WIDTH),
conv_std_logic_vector(1415,AMPL_WIDTH),
conv_std_logic_vector(1416,AMPL_WIDTH),
conv_std_logic_vector(1417,AMPL_WIDTH),
conv_std_logic_vector(1417,AMPL_WIDTH),
conv_std_logic_vector(1418,AMPL_WIDTH),
conv_std_logic_vector(1418,AMPL_WIDTH),
conv_std_logic_vector(1419,AMPL_WIDTH),
conv_std_logic_vector(1419,AMPL_WIDTH),
conv_std_logic_vector(1420,AMPL_WIDTH),
conv_std_logic_vector(1421,AMPL_WIDTH),
conv_std_logic_vector(1421,AMPL_WIDTH),
conv_std_logic_vector(1422,AMPL_WIDTH),
conv_std_logic_vector(1422,AMPL_WIDTH),
conv_std_logic_vector(1423,AMPL_WIDTH),
conv_std_logic_vector(1423,AMPL_WIDTH),
conv_std_logic_vector(1424,AMPL_WIDTH),
conv_std_logic_vector(1425,AMPL_WIDTH),
conv_std_logic_vector(1425,AMPL_WIDTH),
conv_std_logic_vector(1426,AMPL_WIDTH),
conv_std_logic_vector(1426,AMPL_WIDTH),
conv_std_logic_vector(1427,AMPL_WIDTH),
conv_std_logic_vector(1427,AMPL_WIDTH),
conv_std_logic_vector(1428,AMPL_WIDTH),
conv_std_logic_vector(1428,AMPL_WIDTH),
conv_std_logic_vector(1429,AMPL_WIDTH),
conv_std_logic_vector(1430,AMPL_WIDTH),
conv_std_logic_vector(1430,AMPL_WIDTH),
conv_std_logic_vector(1431,AMPL_WIDTH),
conv_std_logic_vector(1431,AMPL_WIDTH),
conv_std_logic_vector(1432,AMPL_WIDTH),
conv_std_logic_vector(1432,AMPL_WIDTH),
conv_std_logic_vector(1433,AMPL_WIDTH),
conv_std_logic_vector(1434,AMPL_WIDTH),
conv_std_logic_vector(1434,AMPL_WIDTH),
conv_std_logic_vector(1435,AMPL_WIDTH),
conv_std_logic_vector(1435,AMPL_WIDTH),
conv_std_logic_vector(1436,AMPL_WIDTH),
conv_std_logic_vector(1436,AMPL_WIDTH),
conv_std_logic_vector(1437,AMPL_WIDTH),
conv_std_logic_vector(1437,AMPL_WIDTH),
conv_std_logic_vector(1438,AMPL_WIDTH),
conv_std_logic_vector(1439,AMPL_WIDTH),
conv_std_logic_vector(1439,AMPL_WIDTH),
conv_std_logic_vector(1440,AMPL_WIDTH),
conv_std_logic_vector(1440,AMPL_WIDTH),
conv_std_logic_vector(1441,AMPL_WIDTH),
conv_std_logic_vector(1441,AMPL_WIDTH),
conv_std_logic_vector(1442,AMPL_WIDTH),
conv_std_logic_vector(1442,AMPL_WIDTH),
conv_std_logic_vector(1443,AMPL_WIDTH),
conv_std_logic_vector(1444,AMPL_WIDTH),
conv_std_logic_vector(1444,AMPL_WIDTH),
conv_std_logic_vector(1445,AMPL_WIDTH),
conv_std_logic_vector(1445,AMPL_WIDTH),
conv_std_logic_vector(1446,AMPL_WIDTH),
conv_std_logic_vector(1446,AMPL_WIDTH),
conv_std_logic_vector(1447,AMPL_WIDTH),
conv_std_logic_vector(1447,AMPL_WIDTH),
conv_std_logic_vector(1448,AMPL_WIDTH),
conv_std_logic_vector(1449,AMPL_WIDTH),
conv_std_logic_vector(1449,AMPL_WIDTH),
conv_std_logic_vector(1450,AMPL_WIDTH),
conv_std_logic_vector(1450,AMPL_WIDTH),
conv_std_logic_vector(1451,AMPL_WIDTH),
conv_std_logic_vector(1451,AMPL_WIDTH),
conv_std_logic_vector(1452,AMPL_WIDTH),
conv_std_logic_vector(1452,AMPL_WIDTH),
conv_std_logic_vector(1453,AMPL_WIDTH),
conv_std_logic_vector(1454,AMPL_WIDTH),
conv_std_logic_vector(1454,AMPL_WIDTH),
conv_std_logic_vector(1455,AMPL_WIDTH),
conv_std_logic_vector(1455,AMPL_WIDTH),
conv_std_logic_vector(1456,AMPL_WIDTH),
conv_std_logic_vector(1456,AMPL_WIDTH),
conv_std_logic_vector(1457,AMPL_WIDTH),
conv_std_logic_vector(1457,AMPL_WIDTH),
conv_std_logic_vector(1458,AMPL_WIDTH),
conv_std_logic_vector(1459,AMPL_WIDTH),
conv_std_logic_vector(1459,AMPL_WIDTH),
conv_std_logic_vector(1460,AMPL_WIDTH),
conv_std_logic_vector(1460,AMPL_WIDTH),
conv_std_logic_vector(1461,AMPL_WIDTH),
conv_std_logic_vector(1461,AMPL_WIDTH),
conv_std_logic_vector(1462,AMPL_WIDTH),
conv_std_logic_vector(1462,AMPL_WIDTH),
conv_std_logic_vector(1463,AMPL_WIDTH),
conv_std_logic_vector(1463,AMPL_WIDTH),
conv_std_logic_vector(1464,AMPL_WIDTH),
conv_std_logic_vector(1465,AMPL_WIDTH),
conv_std_logic_vector(1465,AMPL_WIDTH),
conv_std_logic_vector(1466,AMPL_WIDTH),
conv_std_logic_vector(1466,AMPL_WIDTH),
conv_std_logic_vector(1467,AMPL_WIDTH),
conv_std_logic_vector(1467,AMPL_WIDTH),
conv_std_logic_vector(1468,AMPL_WIDTH),
conv_std_logic_vector(1468,AMPL_WIDTH),
conv_std_logic_vector(1469,AMPL_WIDTH),
conv_std_logic_vector(1469,AMPL_WIDTH),
conv_std_logic_vector(1470,AMPL_WIDTH),
conv_std_logic_vector(1471,AMPL_WIDTH),
conv_std_logic_vector(1471,AMPL_WIDTH),
conv_std_logic_vector(1472,AMPL_WIDTH),
conv_std_logic_vector(1472,AMPL_WIDTH),
conv_std_logic_vector(1473,AMPL_WIDTH),
conv_std_logic_vector(1473,AMPL_WIDTH),
conv_std_logic_vector(1474,AMPL_WIDTH),
conv_std_logic_vector(1474,AMPL_WIDTH),
conv_std_logic_vector(1475,AMPL_WIDTH),
conv_std_logic_vector(1475,AMPL_WIDTH),
conv_std_logic_vector(1476,AMPL_WIDTH),
conv_std_logic_vector(1477,AMPL_WIDTH),
conv_std_logic_vector(1477,AMPL_WIDTH),
conv_std_logic_vector(1478,AMPL_WIDTH),
conv_std_logic_vector(1478,AMPL_WIDTH),
conv_std_logic_vector(1479,AMPL_WIDTH),
conv_std_logic_vector(1479,AMPL_WIDTH),
conv_std_logic_vector(1480,AMPL_WIDTH),
conv_std_logic_vector(1480,AMPL_WIDTH),
conv_std_logic_vector(1481,AMPL_WIDTH),
conv_std_logic_vector(1481,AMPL_WIDTH),
conv_std_logic_vector(1482,AMPL_WIDTH),
conv_std_logic_vector(1483,AMPL_WIDTH),
conv_std_logic_vector(1483,AMPL_WIDTH),
conv_std_logic_vector(1484,AMPL_WIDTH),
conv_std_logic_vector(1484,AMPL_WIDTH),
conv_std_logic_vector(1485,AMPL_WIDTH),
conv_std_logic_vector(1485,AMPL_WIDTH),
conv_std_logic_vector(1486,AMPL_WIDTH),
conv_std_logic_vector(1486,AMPL_WIDTH),
conv_std_logic_vector(1487,AMPL_WIDTH),
conv_std_logic_vector(1487,AMPL_WIDTH),
conv_std_logic_vector(1488,AMPL_WIDTH),
conv_std_logic_vector(1488,AMPL_WIDTH),
conv_std_logic_vector(1489,AMPL_WIDTH),
conv_std_logic_vector(1490,AMPL_WIDTH),
conv_std_logic_vector(1490,AMPL_WIDTH),
conv_std_logic_vector(1491,AMPL_WIDTH),
conv_std_logic_vector(1491,AMPL_WIDTH),
conv_std_logic_vector(1492,AMPL_WIDTH),
conv_std_logic_vector(1492,AMPL_WIDTH),
conv_std_logic_vector(1493,AMPL_WIDTH),
conv_std_logic_vector(1493,AMPL_WIDTH),
conv_std_logic_vector(1494,AMPL_WIDTH),
conv_std_logic_vector(1494,AMPL_WIDTH),
conv_std_logic_vector(1495,AMPL_WIDTH),
conv_std_logic_vector(1495,AMPL_WIDTH),
conv_std_logic_vector(1496,AMPL_WIDTH),
conv_std_logic_vector(1497,AMPL_WIDTH),
conv_std_logic_vector(1497,AMPL_WIDTH),
conv_std_logic_vector(1498,AMPL_WIDTH),
conv_std_logic_vector(1498,AMPL_WIDTH),
conv_std_logic_vector(1499,AMPL_WIDTH),
conv_std_logic_vector(1499,AMPL_WIDTH),
conv_std_logic_vector(1500,AMPL_WIDTH),
conv_std_logic_vector(1500,AMPL_WIDTH),
conv_std_logic_vector(1501,AMPL_WIDTH),
conv_std_logic_vector(1501,AMPL_WIDTH),
conv_std_logic_vector(1502,AMPL_WIDTH),
conv_std_logic_vector(1502,AMPL_WIDTH),
conv_std_logic_vector(1503,AMPL_WIDTH),
conv_std_logic_vector(1503,AMPL_WIDTH),
conv_std_logic_vector(1504,AMPL_WIDTH),
conv_std_logic_vector(1505,AMPL_WIDTH),
conv_std_logic_vector(1505,AMPL_WIDTH),
conv_std_logic_vector(1506,AMPL_WIDTH),
conv_std_logic_vector(1506,AMPL_WIDTH),
conv_std_logic_vector(1507,AMPL_WIDTH),
conv_std_logic_vector(1507,AMPL_WIDTH),
conv_std_logic_vector(1508,AMPL_WIDTH),
conv_std_logic_vector(1508,AMPL_WIDTH),
conv_std_logic_vector(1509,AMPL_WIDTH),
conv_std_logic_vector(1509,AMPL_WIDTH),
conv_std_logic_vector(1510,AMPL_WIDTH),
conv_std_logic_vector(1510,AMPL_WIDTH),
conv_std_logic_vector(1511,AMPL_WIDTH),
conv_std_logic_vector(1511,AMPL_WIDTH),
conv_std_logic_vector(1512,AMPL_WIDTH),
conv_std_logic_vector(1513,AMPL_WIDTH),
conv_std_logic_vector(1513,AMPL_WIDTH),
conv_std_logic_vector(1514,AMPL_WIDTH),
conv_std_logic_vector(1514,AMPL_WIDTH),
conv_std_logic_vector(1515,AMPL_WIDTH),
conv_std_logic_vector(1515,AMPL_WIDTH),
conv_std_logic_vector(1516,AMPL_WIDTH),
conv_std_logic_vector(1516,AMPL_WIDTH),
conv_std_logic_vector(1517,AMPL_WIDTH),
conv_std_logic_vector(1517,AMPL_WIDTH),
conv_std_logic_vector(1518,AMPL_WIDTH),
conv_std_logic_vector(1518,AMPL_WIDTH),
conv_std_logic_vector(1519,AMPL_WIDTH),
conv_std_logic_vector(1519,AMPL_WIDTH),
conv_std_logic_vector(1520,AMPL_WIDTH),
conv_std_logic_vector(1520,AMPL_WIDTH),
conv_std_logic_vector(1521,AMPL_WIDTH),
conv_std_logic_vector(1521,AMPL_WIDTH),
conv_std_logic_vector(1522,AMPL_WIDTH),
conv_std_logic_vector(1523,AMPL_WIDTH),
conv_std_logic_vector(1523,AMPL_WIDTH),
conv_std_logic_vector(1524,AMPL_WIDTH),
conv_std_logic_vector(1524,AMPL_WIDTH),
conv_std_logic_vector(1525,AMPL_WIDTH),
conv_std_logic_vector(1525,AMPL_WIDTH),
conv_std_logic_vector(1526,AMPL_WIDTH),
conv_std_logic_vector(1526,AMPL_WIDTH),
conv_std_logic_vector(1527,AMPL_WIDTH),
conv_std_logic_vector(1527,AMPL_WIDTH),
conv_std_logic_vector(1528,AMPL_WIDTH),
conv_std_logic_vector(1528,AMPL_WIDTH),
conv_std_logic_vector(1529,AMPL_WIDTH),
conv_std_logic_vector(1529,AMPL_WIDTH),
conv_std_logic_vector(1530,AMPL_WIDTH),
conv_std_logic_vector(1530,AMPL_WIDTH),
conv_std_logic_vector(1531,AMPL_WIDTH),
conv_std_logic_vector(1531,AMPL_WIDTH),
conv_std_logic_vector(1532,AMPL_WIDTH),
conv_std_logic_vector(1532,AMPL_WIDTH),
conv_std_logic_vector(1533,AMPL_WIDTH),
conv_std_logic_vector(1533,AMPL_WIDTH),
conv_std_logic_vector(1534,AMPL_WIDTH),
conv_std_logic_vector(1535,AMPL_WIDTH),
conv_std_logic_vector(1535,AMPL_WIDTH),
conv_std_logic_vector(1536,AMPL_WIDTH),
conv_std_logic_vector(1536,AMPL_WIDTH),
conv_std_logic_vector(1537,AMPL_WIDTH),
conv_std_logic_vector(1537,AMPL_WIDTH),
conv_std_logic_vector(1538,AMPL_WIDTH),
conv_std_logic_vector(1538,AMPL_WIDTH),
conv_std_logic_vector(1539,AMPL_WIDTH),
conv_std_logic_vector(1539,AMPL_WIDTH),
conv_std_logic_vector(1540,AMPL_WIDTH),
conv_std_logic_vector(1540,AMPL_WIDTH),
conv_std_logic_vector(1541,AMPL_WIDTH),
conv_std_logic_vector(1541,AMPL_WIDTH),
conv_std_logic_vector(1542,AMPL_WIDTH),
conv_std_logic_vector(1542,AMPL_WIDTH),
conv_std_logic_vector(1543,AMPL_WIDTH),
conv_std_logic_vector(1543,AMPL_WIDTH),
conv_std_logic_vector(1544,AMPL_WIDTH),
conv_std_logic_vector(1544,AMPL_WIDTH),
conv_std_logic_vector(1545,AMPL_WIDTH),
conv_std_logic_vector(1545,AMPL_WIDTH),
conv_std_logic_vector(1546,AMPL_WIDTH),
conv_std_logic_vector(1546,AMPL_WIDTH),
conv_std_logic_vector(1547,AMPL_WIDTH),
conv_std_logic_vector(1547,AMPL_WIDTH),
conv_std_logic_vector(1548,AMPL_WIDTH),
conv_std_logic_vector(1548,AMPL_WIDTH),
conv_std_logic_vector(1549,AMPL_WIDTH),
conv_std_logic_vector(1549,AMPL_WIDTH),
conv_std_logic_vector(1550,AMPL_WIDTH),
conv_std_logic_vector(1551,AMPL_WIDTH),
conv_std_logic_vector(1551,AMPL_WIDTH),
conv_std_logic_vector(1552,AMPL_WIDTH),
conv_std_logic_vector(1552,AMPL_WIDTH),
conv_std_logic_vector(1553,AMPL_WIDTH),
conv_std_logic_vector(1553,AMPL_WIDTH),
conv_std_logic_vector(1554,AMPL_WIDTH),
conv_std_logic_vector(1554,AMPL_WIDTH),
conv_std_logic_vector(1555,AMPL_WIDTH),
conv_std_logic_vector(1555,AMPL_WIDTH),
conv_std_logic_vector(1556,AMPL_WIDTH),
conv_std_logic_vector(1556,AMPL_WIDTH),
conv_std_logic_vector(1557,AMPL_WIDTH),
conv_std_logic_vector(1557,AMPL_WIDTH),
conv_std_logic_vector(1558,AMPL_WIDTH),
conv_std_logic_vector(1558,AMPL_WIDTH),
conv_std_logic_vector(1559,AMPL_WIDTH),
conv_std_logic_vector(1559,AMPL_WIDTH),
conv_std_logic_vector(1560,AMPL_WIDTH),
conv_std_logic_vector(1560,AMPL_WIDTH),
conv_std_logic_vector(1561,AMPL_WIDTH),
conv_std_logic_vector(1561,AMPL_WIDTH),
conv_std_logic_vector(1562,AMPL_WIDTH),
conv_std_logic_vector(1562,AMPL_WIDTH),
conv_std_logic_vector(1563,AMPL_WIDTH),
conv_std_logic_vector(1563,AMPL_WIDTH),
conv_std_logic_vector(1564,AMPL_WIDTH),
conv_std_logic_vector(1564,AMPL_WIDTH),
conv_std_logic_vector(1565,AMPL_WIDTH),
conv_std_logic_vector(1565,AMPL_WIDTH),
conv_std_logic_vector(1566,AMPL_WIDTH),
conv_std_logic_vector(1566,AMPL_WIDTH),
conv_std_logic_vector(1567,AMPL_WIDTH),
conv_std_logic_vector(1567,AMPL_WIDTH),
conv_std_logic_vector(1568,AMPL_WIDTH),
conv_std_logic_vector(1568,AMPL_WIDTH),
conv_std_logic_vector(1569,AMPL_WIDTH),
conv_std_logic_vector(1569,AMPL_WIDTH),
conv_std_logic_vector(1570,AMPL_WIDTH),
conv_std_logic_vector(1570,AMPL_WIDTH),
conv_std_logic_vector(1571,AMPL_WIDTH),
conv_std_logic_vector(1571,AMPL_WIDTH),
conv_std_logic_vector(1572,AMPL_WIDTH),
conv_std_logic_vector(1572,AMPL_WIDTH),
conv_std_logic_vector(1573,AMPL_WIDTH),
conv_std_logic_vector(1573,AMPL_WIDTH),
conv_std_logic_vector(1574,AMPL_WIDTH),
conv_std_logic_vector(1574,AMPL_WIDTH),
conv_std_logic_vector(1575,AMPL_WIDTH),
conv_std_logic_vector(1575,AMPL_WIDTH),
conv_std_logic_vector(1576,AMPL_WIDTH),
conv_std_logic_vector(1576,AMPL_WIDTH),
conv_std_logic_vector(1577,AMPL_WIDTH),
conv_std_logic_vector(1577,AMPL_WIDTH),
conv_std_logic_vector(1578,AMPL_WIDTH),
conv_std_logic_vector(1578,AMPL_WIDTH),
conv_std_logic_vector(1579,AMPL_WIDTH),
conv_std_logic_vector(1579,AMPL_WIDTH),
conv_std_logic_vector(1580,AMPL_WIDTH),
conv_std_logic_vector(1580,AMPL_WIDTH),
conv_std_logic_vector(1581,AMPL_WIDTH),
conv_std_logic_vector(1581,AMPL_WIDTH),
conv_std_logic_vector(1582,AMPL_WIDTH),
conv_std_logic_vector(1582,AMPL_WIDTH),
conv_std_logic_vector(1583,AMPL_WIDTH),
conv_std_logic_vector(1583,AMPL_WIDTH),
conv_std_logic_vector(1584,AMPL_WIDTH),
conv_std_logic_vector(1584,AMPL_WIDTH),
conv_std_logic_vector(1585,AMPL_WIDTH),
conv_std_logic_vector(1585,AMPL_WIDTH),
conv_std_logic_vector(1586,AMPL_WIDTH),
conv_std_logic_vector(1586,AMPL_WIDTH),
conv_std_logic_vector(1587,AMPL_WIDTH),
conv_std_logic_vector(1587,AMPL_WIDTH),
conv_std_logic_vector(1588,AMPL_WIDTH),
conv_std_logic_vector(1588,AMPL_WIDTH),
conv_std_logic_vector(1589,AMPL_WIDTH),
conv_std_logic_vector(1589,AMPL_WIDTH),
conv_std_logic_vector(1590,AMPL_WIDTH),
conv_std_logic_vector(1590,AMPL_WIDTH),
conv_std_logic_vector(1591,AMPL_WIDTH),
conv_std_logic_vector(1591,AMPL_WIDTH),
conv_std_logic_vector(1592,AMPL_WIDTH),
conv_std_logic_vector(1592,AMPL_WIDTH),
conv_std_logic_vector(1593,AMPL_WIDTH),
conv_std_logic_vector(1593,AMPL_WIDTH),
conv_std_logic_vector(1594,AMPL_WIDTH),
conv_std_logic_vector(1594,AMPL_WIDTH),
conv_std_logic_vector(1595,AMPL_WIDTH),
conv_std_logic_vector(1595,AMPL_WIDTH),
conv_std_logic_vector(1596,AMPL_WIDTH),
conv_std_logic_vector(1596,AMPL_WIDTH),
conv_std_logic_vector(1597,AMPL_WIDTH),
conv_std_logic_vector(1597,AMPL_WIDTH),
conv_std_logic_vector(1598,AMPL_WIDTH),
conv_std_logic_vector(1598,AMPL_WIDTH),
conv_std_logic_vector(1599,AMPL_WIDTH),
conv_std_logic_vector(1599,AMPL_WIDTH),
conv_std_logic_vector(1600,AMPL_WIDTH),
conv_std_logic_vector(1600,AMPL_WIDTH),
conv_std_logic_vector(1601,AMPL_WIDTH),
conv_std_logic_vector(1601,AMPL_WIDTH),
conv_std_logic_vector(1602,AMPL_WIDTH),
conv_std_logic_vector(1602,AMPL_WIDTH),
conv_std_logic_vector(1603,AMPL_WIDTH),
conv_std_logic_vector(1603,AMPL_WIDTH),
conv_std_logic_vector(1604,AMPL_WIDTH),
conv_std_logic_vector(1604,AMPL_WIDTH),
conv_std_logic_vector(1605,AMPL_WIDTH),
conv_std_logic_vector(1605,AMPL_WIDTH),
conv_std_logic_vector(1606,AMPL_WIDTH),
conv_std_logic_vector(1606,AMPL_WIDTH),
conv_std_logic_vector(1606,AMPL_WIDTH),
conv_std_logic_vector(1607,AMPL_WIDTH),
conv_std_logic_vector(1607,AMPL_WIDTH),
conv_std_logic_vector(1608,AMPL_WIDTH),
conv_std_logic_vector(1608,AMPL_WIDTH),
conv_std_logic_vector(1609,AMPL_WIDTH),
conv_std_logic_vector(1609,AMPL_WIDTH),
conv_std_logic_vector(1610,AMPL_WIDTH),
conv_std_logic_vector(1610,AMPL_WIDTH),
conv_std_logic_vector(1611,AMPL_WIDTH),
conv_std_logic_vector(1611,AMPL_WIDTH),
conv_std_logic_vector(1612,AMPL_WIDTH),
conv_std_logic_vector(1612,AMPL_WIDTH),
conv_std_logic_vector(1613,AMPL_WIDTH),
conv_std_logic_vector(1613,AMPL_WIDTH),
conv_std_logic_vector(1614,AMPL_WIDTH),
conv_std_logic_vector(1614,AMPL_WIDTH),
conv_std_logic_vector(1615,AMPL_WIDTH),
conv_std_logic_vector(1615,AMPL_WIDTH),
conv_std_logic_vector(1616,AMPL_WIDTH),
conv_std_logic_vector(1616,AMPL_WIDTH),
conv_std_logic_vector(1617,AMPL_WIDTH),
conv_std_logic_vector(1617,AMPL_WIDTH),
conv_std_logic_vector(1618,AMPL_WIDTH),
conv_std_logic_vector(1618,AMPL_WIDTH),
conv_std_logic_vector(1619,AMPL_WIDTH),
conv_std_logic_vector(1619,AMPL_WIDTH),
conv_std_logic_vector(1620,AMPL_WIDTH),
conv_std_logic_vector(1620,AMPL_WIDTH),
conv_std_logic_vector(1620,AMPL_WIDTH),
conv_std_logic_vector(1621,AMPL_WIDTH),
conv_std_logic_vector(1621,AMPL_WIDTH),
conv_std_logic_vector(1622,AMPL_WIDTH),
conv_std_logic_vector(1622,AMPL_WIDTH),
conv_std_logic_vector(1623,AMPL_WIDTH),
conv_std_logic_vector(1623,AMPL_WIDTH),
conv_std_logic_vector(1624,AMPL_WIDTH),
conv_std_logic_vector(1624,AMPL_WIDTH),
conv_std_logic_vector(1625,AMPL_WIDTH),
conv_std_logic_vector(1625,AMPL_WIDTH),
conv_std_logic_vector(1626,AMPL_WIDTH),
conv_std_logic_vector(1626,AMPL_WIDTH),
conv_std_logic_vector(1627,AMPL_WIDTH),
conv_std_logic_vector(1627,AMPL_WIDTH),
conv_std_logic_vector(1628,AMPL_WIDTH),
conv_std_logic_vector(1628,AMPL_WIDTH),
conv_std_logic_vector(1629,AMPL_WIDTH),
conv_std_logic_vector(1629,AMPL_WIDTH),
conv_std_logic_vector(1630,AMPL_WIDTH),
conv_std_logic_vector(1630,AMPL_WIDTH),
conv_std_logic_vector(1631,AMPL_WIDTH),
conv_std_logic_vector(1631,AMPL_WIDTH),
conv_std_logic_vector(1631,AMPL_WIDTH),
conv_std_logic_vector(1632,AMPL_WIDTH),
conv_std_logic_vector(1632,AMPL_WIDTH),
conv_std_logic_vector(1633,AMPL_WIDTH),
conv_std_logic_vector(1633,AMPL_WIDTH),
conv_std_logic_vector(1634,AMPL_WIDTH),
conv_std_logic_vector(1634,AMPL_WIDTH),
conv_std_logic_vector(1635,AMPL_WIDTH),
conv_std_logic_vector(1635,AMPL_WIDTH),
conv_std_logic_vector(1636,AMPL_WIDTH),
conv_std_logic_vector(1636,AMPL_WIDTH),
conv_std_logic_vector(1637,AMPL_WIDTH),
conv_std_logic_vector(1637,AMPL_WIDTH),
conv_std_logic_vector(1638,AMPL_WIDTH),
conv_std_logic_vector(1638,AMPL_WIDTH),
conv_std_logic_vector(1639,AMPL_WIDTH),
conv_std_logic_vector(1639,AMPL_WIDTH),
conv_std_logic_vector(1639,AMPL_WIDTH),
conv_std_logic_vector(1640,AMPL_WIDTH),
conv_std_logic_vector(1640,AMPL_WIDTH),
conv_std_logic_vector(1641,AMPL_WIDTH),
conv_std_logic_vector(1641,AMPL_WIDTH),
conv_std_logic_vector(1642,AMPL_WIDTH),
conv_std_logic_vector(1642,AMPL_WIDTH),
conv_std_logic_vector(1643,AMPL_WIDTH),
conv_std_logic_vector(1643,AMPL_WIDTH),
conv_std_logic_vector(1644,AMPL_WIDTH),
conv_std_logic_vector(1644,AMPL_WIDTH),
conv_std_logic_vector(1645,AMPL_WIDTH),
conv_std_logic_vector(1645,AMPL_WIDTH),
conv_std_logic_vector(1646,AMPL_WIDTH),
conv_std_logic_vector(1646,AMPL_WIDTH),
conv_std_logic_vector(1647,AMPL_WIDTH),
conv_std_logic_vector(1647,AMPL_WIDTH),
conv_std_logic_vector(1647,AMPL_WIDTH),
conv_std_logic_vector(1648,AMPL_WIDTH),
conv_std_logic_vector(1648,AMPL_WIDTH),
conv_std_logic_vector(1649,AMPL_WIDTH),
conv_std_logic_vector(1649,AMPL_WIDTH),
conv_std_logic_vector(1650,AMPL_WIDTH),
conv_std_logic_vector(1650,AMPL_WIDTH),
conv_std_logic_vector(1651,AMPL_WIDTH),
conv_std_logic_vector(1651,AMPL_WIDTH),
conv_std_logic_vector(1652,AMPL_WIDTH),
conv_std_logic_vector(1652,AMPL_WIDTH),
conv_std_logic_vector(1653,AMPL_WIDTH),
conv_std_logic_vector(1653,AMPL_WIDTH),
conv_std_logic_vector(1653,AMPL_WIDTH),
conv_std_logic_vector(1654,AMPL_WIDTH),
conv_std_logic_vector(1654,AMPL_WIDTH),
conv_std_logic_vector(1655,AMPL_WIDTH),
conv_std_logic_vector(1655,AMPL_WIDTH),
conv_std_logic_vector(1656,AMPL_WIDTH),
conv_std_logic_vector(1656,AMPL_WIDTH),
conv_std_logic_vector(1657,AMPL_WIDTH),
conv_std_logic_vector(1657,AMPL_WIDTH),
conv_std_logic_vector(1658,AMPL_WIDTH),
conv_std_logic_vector(1658,AMPL_WIDTH),
conv_std_logic_vector(1659,AMPL_WIDTH),
conv_std_logic_vector(1659,AMPL_WIDTH),
conv_std_logic_vector(1659,AMPL_WIDTH),
conv_std_logic_vector(1660,AMPL_WIDTH),
conv_std_logic_vector(1660,AMPL_WIDTH),
conv_std_logic_vector(1661,AMPL_WIDTH),
conv_std_logic_vector(1661,AMPL_WIDTH),
conv_std_logic_vector(1662,AMPL_WIDTH),
conv_std_logic_vector(1662,AMPL_WIDTH),
conv_std_logic_vector(1663,AMPL_WIDTH),
conv_std_logic_vector(1663,AMPL_WIDTH),
conv_std_logic_vector(1664,AMPL_WIDTH),
conv_std_logic_vector(1664,AMPL_WIDTH),
conv_std_logic_vector(1665,AMPL_WIDTH),
conv_std_logic_vector(1665,AMPL_WIDTH),
conv_std_logic_vector(1665,AMPL_WIDTH),
conv_std_logic_vector(1666,AMPL_WIDTH),
conv_std_logic_vector(1666,AMPL_WIDTH),
conv_std_logic_vector(1667,AMPL_WIDTH),
conv_std_logic_vector(1667,AMPL_WIDTH),
conv_std_logic_vector(1668,AMPL_WIDTH),
conv_std_logic_vector(1668,AMPL_WIDTH),
conv_std_logic_vector(1669,AMPL_WIDTH),
conv_std_logic_vector(1669,AMPL_WIDTH),
conv_std_logic_vector(1670,AMPL_WIDTH),
conv_std_logic_vector(1670,AMPL_WIDTH),
conv_std_logic_vector(1670,AMPL_WIDTH),
conv_std_logic_vector(1671,AMPL_WIDTH),
conv_std_logic_vector(1671,AMPL_WIDTH),
conv_std_logic_vector(1672,AMPL_WIDTH),
conv_std_logic_vector(1672,AMPL_WIDTH),
conv_std_logic_vector(1673,AMPL_WIDTH),
conv_std_logic_vector(1673,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1675,AMPL_WIDTH),
conv_std_logic_vector(1675,AMPL_WIDTH),
conv_std_logic_vector(1676,AMPL_WIDTH),
conv_std_logic_vector(1676,AMPL_WIDTH),
conv_std_logic_vector(1677,AMPL_WIDTH),
conv_std_logic_vector(1677,AMPL_WIDTH),
conv_std_logic_vector(1678,AMPL_WIDTH),
conv_std_logic_vector(1678,AMPL_WIDTH),
conv_std_logic_vector(1679,AMPL_WIDTH),
conv_std_logic_vector(1679,AMPL_WIDTH),
conv_std_logic_vector(1679,AMPL_WIDTH),
conv_std_logic_vector(1680,AMPL_WIDTH),
conv_std_logic_vector(1680,AMPL_WIDTH),
conv_std_logic_vector(1681,AMPL_WIDTH),
conv_std_logic_vector(1681,AMPL_WIDTH),
conv_std_logic_vector(1682,AMPL_WIDTH),
conv_std_logic_vector(1682,AMPL_WIDTH),
conv_std_logic_vector(1683,AMPL_WIDTH),
conv_std_logic_vector(1683,AMPL_WIDTH),
conv_std_logic_vector(1683,AMPL_WIDTH),
conv_std_logic_vector(1684,AMPL_WIDTH),
conv_std_logic_vector(1684,AMPL_WIDTH),
conv_std_logic_vector(1685,AMPL_WIDTH),
conv_std_logic_vector(1685,AMPL_WIDTH),
conv_std_logic_vector(1686,AMPL_WIDTH),
conv_std_logic_vector(1686,AMPL_WIDTH),
conv_std_logic_vector(1687,AMPL_WIDTH),
conv_std_logic_vector(1687,AMPL_WIDTH),
conv_std_logic_vector(1687,AMPL_WIDTH),
conv_std_logic_vector(1688,AMPL_WIDTH),
conv_std_logic_vector(1688,AMPL_WIDTH),
conv_std_logic_vector(1689,AMPL_WIDTH),
conv_std_logic_vector(1689,AMPL_WIDTH),
conv_std_logic_vector(1690,AMPL_WIDTH),
conv_std_logic_vector(1690,AMPL_WIDTH),
conv_std_logic_vector(1691,AMPL_WIDTH),
conv_std_logic_vector(1691,AMPL_WIDTH),
conv_std_logic_vector(1691,AMPL_WIDTH),
conv_std_logic_vector(1692,AMPL_WIDTH),
conv_std_logic_vector(1692,AMPL_WIDTH),
conv_std_logic_vector(1693,AMPL_WIDTH),
conv_std_logic_vector(1693,AMPL_WIDTH),
conv_std_logic_vector(1694,AMPL_WIDTH),
conv_std_logic_vector(1694,AMPL_WIDTH),
conv_std_logic_vector(1695,AMPL_WIDTH),
conv_std_logic_vector(1695,AMPL_WIDTH),
conv_std_logic_vector(1695,AMPL_WIDTH),
conv_std_logic_vector(1696,AMPL_WIDTH),
conv_std_logic_vector(1696,AMPL_WIDTH),
conv_std_logic_vector(1697,AMPL_WIDTH),
conv_std_logic_vector(1697,AMPL_WIDTH),
conv_std_logic_vector(1698,AMPL_WIDTH),
conv_std_logic_vector(1698,AMPL_WIDTH),
conv_std_logic_vector(1699,AMPL_WIDTH),
conv_std_logic_vector(1699,AMPL_WIDTH),
conv_std_logic_vector(1699,AMPL_WIDTH),
conv_std_logic_vector(1700,AMPL_WIDTH),
conv_std_logic_vector(1700,AMPL_WIDTH),
conv_std_logic_vector(1701,AMPL_WIDTH),
conv_std_logic_vector(1701,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1703,AMPL_WIDTH),
conv_std_logic_vector(1703,AMPL_WIDTH),
conv_std_logic_vector(1704,AMPL_WIDTH),
conv_std_logic_vector(1704,AMPL_WIDTH),
conv_std_logic_vector(1705,AMPL_WIDTH),
conv_std_logic_vector(1705,AMPL_WIDTH),
conv_std_logic_vector(1705,AMPL_WIDTH),
conv_std_logic_vector(1706,AMPL_WIDTH),
conv_std_logic_vector(1706,AMPL_WIDTH),
conv_std_logic_vector(1707,AMPL_WIDTH),
conv_std_logic_vector(1707,AMPL_WIDTH),
conv_std_logic_vector(1708,AMPL_WIDTH),
conv_std_logic_vector(1708,AMPL_WIDTH),
conv_std_logic_vector(1709,AMPL_WIDTH),
conv_std_logic_vector(1709,AMPL_WIDTH),
conv_std_logic_vector(1709,AMPL_WIDTH),
conv_std_logic_vector(1710,AMPL_WIDTH),
conv_std_logic_vector(1710,AMPL_WIDTH),
conv_std_logic_vector(1711,AMPL_WIDTH),
conv_std_logic_vector(1711,AMPL_WIDTH),
conv_std_logic_vector(1712,AMPL_WIDTH),
conv_std_logic_vector(1712,AMPL_WIDTH),
conv_std_logic_vector(1712,AMPL_WIDTH),
conv_std_logic_vector(1713,AMPL_WIDTH),
conv_std_logic_vector(1713,AMPL_WIDTH),
conv_std_logic_vector(1714,AMPL_WIDTH),
conv_std_logic_vector(1714,AMPL_WIDTH),
conv_std_logic_vector(1715,AMPL_WIDTH),
conv_std_logic_vector(1715,AMPL_WIDTH),
conv_std_logic_vector(1715,AMPL_WIDTH),
conv_std_logic_vector(1716,AMPL_WIDTH),
conv_std_logic_vector(1716,AMPL_WIDTH),
conv_std_logic_vector(1717,AMPL_WIDTH),
conv_std_logic_vector(1717,AMPL_WIDTH),
conv_std_logic_vector(1718,AMPL_WIDTH),
conv_std_logic_vector(1718,AMPL_WIDTH),
conv_std_logic_vector(1718,AMPL_WIDTH),
conv_std_logic_vector(1719,AMPL_WIDTH),
conv_std_logic_vector(1719,AMPL_WIDTH),
conv_std_logic_vector(1720,AMPL_WIDTH),
conv_std_logic_vector(1720,AMPL_WIDTH),
conv_std_logic_vector(1721,AMPL_WIDTH),
conv_std_logic_vector(1721,AMPL_WIDTH),
conv_std_logic_vector(1721,AMPL_WIDTH),
conv_std_logic_vector(1722,AMPL_WIDTH),
conv_std_logic_vector(1722,AMPL_WIDTH),
conv_std_logic_vector(1723,AMPL_WIDTH),
conv_std_logic_vector(1723,AMPL_WIDTH),
conv_std_logic_vector(1724,AMPL_WIDTH),
conv_std_logic_vector(1724,AMPL_WIDTH),
conv_std_logic_vector(1724,AMPL_WIDTH),
conv_std_logic_vector(1725,AMPL_WIDTH),
conv_std_logic_vector(1725,AMPL_WIDTH),
conv_std_logic_vector(1726,AMPL_WIDTH),
conv_std_logic_vector(1726,AMPL_WIDTH),
conv_std_logic_vector(1726,AMPL_WIDTH),
conv_std_logic_vector(1727,AMPL_WIDTH),
conv_std_logic_vector(1727,AMPL_WIDTH),
conv_std_logic_vector(1728,AMPL_WIDTH),
conv_std_logic_vector(1728,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1730,AMPL_WIDTH),
conv_std_logic_vector(1730,AMPL_WIDTH),
conv_std_logic_vector(1731,AMPL_WIDTH),
conv_std_logic_vector(1731,AMPL_WIDTH),
conv_std_logic_vector(1732,AMPL_WIDTH),
conv_std_logic_vector(1732,AMPL_WIDTH),
conv_std_logic_vector(1732,AMPL_WIDTH),
conv_std_logic_vector(1733,AMPL_WIDTH),
conv_std_logic_vector(1733,AMPL_WIDTH),
conv_std_logic_vector(1734,AMPL_WIDTH),
conv_std_logic_vector(1734,AMPL_WIDTH),
conv_std_logic_vector(1734,AMPL_WIDTH),
conv_std_logic_vector(1735,AMPL_WIDTH),
conv_std_logic_vector(1735,AMPL_WIDTH),
conv_std_logic_vector(1736,AMPL_WIDTH),
conv_std_logic_vector(1736,AMPL_WIDTH),
conv_std_logic_vector(1737,AMPL_WIDTH),
conv_std_logic_vector(1737,AMPL_WIDTH),
conv_std_logic_vector(1737,AMPL_WIDTH),
conv_std_logic_vector(1738,AMPL_WIDTH),
conv_std_logic_vector(1738,AMPL_WIDTH),
conv_std_logic_vector(1739,AMPL_WIDTH),
conv_std_logic_vector(1739,AMPL_WIDTH),
conv_std_logic_vector(1739,AMPL_WIDTH),
conv_std_logic_vector(1740,AMPL_WIDTH),
conv_std_logic_vector(1740,AMPL_WIDTH),
conv_std_logic_vector(1741,AMPL_WIDTH),
conv_std_logic_vector(1741,AMPL_WIDTH),
conv_std_logic_vector(1741,AMPL_WIDTH),
conv_std_logic_vector(1742,AMPL_WIDTH),
conv_std_logic_vector(1742,AMPL_WIDTH),
conv_std_logic_vector(1743,AMPL_WIDTH),
conv_std_logic_vector(1743,AMPL_WIDTH),
conv_std_logic_vector(1744,AMPL_WIDTH),
conv_std_logic_vector(1744,AMPL_WIDTH),
conv_std_logic_vector(1744,AMPL_WIDTH),
conv_std_logic_vector(1745,AMPL_WIDTH),
conv_std_logic_vector(1745,AMPL_WIDTH),
conv_std_logic_vector(1746,AMPL_WIDTH),
conv_std_logic_vector(1746,AMPL_WIDTH),
conv_std_logic_vector(1746,AMPL_WIDTH),
conv_std_logic_vector(1747,AMPL_WIDTH),
conv_std_logic_vector(1747,AMPL_WIDTH),
conv_std_logic_vector(1748,AMPL_WIDTH),
conv_std_logic_vector(1748,AMPL_WIDTH),
conv_std_logic_vector(1748,AMPL_WIDTH),
conv_std_logic_vector(1749,AMPL_WIDTH),
conv_std_logic_vector(1749,AMPL_WIDTH),
conv_std_logic_vector(1750,AMPL_WIDTH),
conv_std_logic_vector(1750,AMPL_WIDTH),
conv_std_logic_vector(1751,AMPL_WIDTH),
conv_std_logic_vector(1751,AMPL_WIDTH),
conv_std_logic_vector(1751,AMPL_WIDTH),
conv_std_logic_vector(1752,AMPL_WIDTH),
conv_std_logic_vector(1752,AMPL_WIDTH),
conv_std_logic_vector(1753,AMPL_WIDTH),
conv_std_logic_vector(1753,AMPL_WIDTH),
conv_std_logic_vector(1753,AMPL_WIDTH),
conv_std_logic_vector(1754,AMPL_WIDTH),
conv_std_logic_vector(1754,AMPL_WIDTH),
conv_std_logic_vector(1755,AMPL_WIDTH),
conv_std_logic_vector(1755,AMPL_WIDTH),
conv_std_logic_vector(1755,AMPL_WIDTH),
conv_std_logic_vector(1756,AMPL_WIDTH),
conv_std_logic_vector(1756,AMPL_WIDTH),
conv_std_logic_vector(1757,AMPL_WIDTH),
conv_std_logic_vector(1757,AMPL_WIDTH),
conv_std_logic_vector(1757,AMPL_WIDTH),
conv_std_logic_vector(1758,AMPL_WIDTH),
conv_std_logic_vector(1758,AMPL_WIDTH),
conv_std_logic_vector(1759,AMPL_WIDTH),
conv_std_logic_vector(1759,AMPL_WIDTH),
conv_std_logic_vector(1759,AMPL_WIDTH),
conv_std_logic_vector(1760,AMPL_WIDTH),
conv_std_logic_vector(1760,AMPL_WIDTH),
conv_std_logic_vector(1761,AMPL_WIDTH),
conv_std_logic_vector(1761,AMPL_WIDTH),
conv_std_logic_vector(1761,AMPL_WIDTH),
conv_std_logic_vector(1762,AMPL_WIDTH),
conv_std_logic_vector(1762,AMPL_WIDTH),
conv_std_logic_vector(1763,AMPL_WIDTH),
conv_std_logic_vector(1763,AMPL_WIDTH),
conv_std_logic_vector(1763,AMPL_WIDTH),
conv_std_logic_vector(1764,AMPL_WIDTH),
conv_std_logic_vector(1764,AMPL_WIDTH),
conv_std_logic_vector(1765,AMPL_WIDTH),
conv_std_logic_vector(1765,AMPL_WIDTH),
conv_std_logic_vector(1765,AMPL_WIDTH),
conv_std_logic_vector(1766,AMPL_WIDTH),
conv_std_logic_vector(1766,AMPL_WIDTH),
conv_std_logic_vector(1767,AMPL_WIDTH),
conv_std_logic_vector(1767,AMPL_WIDTH),
conv_std_logic_vector(1767,AMPL_WIDTH),
conv_std_logic_vector(1768,AMPL_WIDTH),
conv_std_logic_vector(1768,AMPL_WIDTH),
conv_std_logic_vector(1769,AMPL_WIDTH),
conv_std_logic_vector(1769,AMPL_WIDTH),
conv_std_logic_vector(1769,AMPL_WIDTH),
conv_std_logic_vector(1770,AMPL_WIDTH),
conv_std_logic_vector(1770,AMPL_WIDTH),
conv_std_logic_vector(1771,AMPL_WIDTH),
conv_std_logic_vector(1771,AMPL_WIDTH),
conv_std_logic_vector(1771,AMPL_WIDTH),
conv_std_logic_vector(1772,AMPL_WIDTH),
conv_std_logic_vector(1772,AMPL_WIDTH),
conv_std_logic_vector(1772,AMPL_WIDTH),
conv_std_logic_vector(1773,AMPL_WIDTH),
conv_std_logic_vector(1773,AMPL_WIDTH),
conv_std_logic_vector(1774,AMPL_WIDTH),
conv_std_logic_vector(1774,AMPL_WIDTH),
conv_std_logic_vector(1774,AMPL_WIDTH),
conv_std_logic_vector(1775,AMPL_WIDTH),
conv_std_logic_vector(1775,AMPL_WIDTH),
conv_std_logic_vector(1776,AMPL_WIDTH),
conv_std_logic_vector(1776,AMPL_WIDTH),
conv_std_logic_vector(1776,AMPL_WIDTH),
conv_std_logic_vector(1777,AMPL_WIDTH),
conv_std_logic_vector(1777,AMPL_WIDTH),
conv_std_logic_vector(1778,AMPL_WIDTH),
conv_std_logic_vector(1778,AMPL_WIDTH),
conv_std_logic_vector(1778,AMPL_WIDTH),
conv_std_logic_vector(1779,AMPL_WIDTH),
conv_std_logic_vector(1779,AMPL_WIDTH),
conv_std_logic_vector(1780,AMPL_WIDTH),
conv_std_logic_vector(1780,AMPL_WIDTH),
conv_std_logic_vector(1780,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1782,AMPL_WIDTH),
conv_std_logic_vector(1782,AMPL_WIDTH),
conv_std_logic_vector(1783,AMPL_WIDTH),
conv_std_logic_vector(1783,AMPL_WIDTH),
conv_std_logic_vector(1783,AMPL_WIDTH),
conv_std_logic_vector(1784,AMPL_WIDTH),
conv_std_logic_vector(1784,AMPL_WIDTH),
conv_std_logic_vector(1785,AMPL_WIDTH),
conv_std_logic_vector(1785,AMPL_WIDTH),
conv_std_logic_vector(1785,AMPL_WIDTH),
conv_std_logic_vector(1786,AMPL_WIDTH),
conv_std_logic_vector(1786,AMPL_WIDTH),
conv_std_logic_vector(1786,AMPL_WIDTH),
conv_std_logic_vector(1787,AMPL_WIDTH),
conv_std_logic_vector(1787,AMPL_WIDTH),
conv_std_logic_vector(1788,AMPL_WIDTH),
conv_std_logic_vector(1788,AMPL_WIDTH),
conv_std_logic_vector(1788,AMPL_WIDTH),
conv_std_logic_vector(1789,AMPL_WIDTH),
conv_std_logic_vector(1789,AMPL_WIDTH),
conv_std_logic_vector(1790,AMPL_WIDTH),
conv_std_logic_vector(1790,AMPL_WIDTH),
conv_std_logic_vector(1790,AMPL_WIDTH),
conv_std_logic_vector(1791,AMPL_WIDTH),
conv_std_logic_vector(1791,AMPL_WIDTH),
conv_std_logic_vector(1791,AMPL_WIDTH),
conv_std_logic_vector(1792,AMPL_WIDTH),
conv_std_logic_vector(1792,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1794,AMPL_WIDTH),
conv_std_logic_vector(1794,AMPL_WIDTH),
conv_std_logic_vector(1794,AMPL_WIDTH),
conv_std_logic_vector(1795,AMPL_WIDTH),
conv_std_logic_vector(1795,AMPL_WIDTH),
conv_std_logic_vector(1796,AMPL_WIDTH),
conv_std_logic_vector(1796,AMPL_WIDTH),
conv_std_logic_vector(1796,AMPL_WIDTH),
conv_std_logic_vector(1797,AMPL_WIDTH),
conv_std_logic_vector(1797,AMPL_WIDTH),
conv_std_logic_vector(1797,AMPL_WIDTH),
conv_std_logic_vector(1798,AMPL_WIDTH),
conv_std_logic_vector(1798,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1800,AMPL_WIDTH),
conv_std_logic_vector(1800,AMPL_WIDTH),
conv_std_logic_vector(1800,AMPL_WIDTH),
conv_std_logic_vector(1801,AMPL_WIDTH),
conv_std_logic_vector(1801,AMPL_WIDTH),
conv_std_logic_vector(1802,AMPL_WIDTH),
conv_std_logic_vector(1802,AMPL_WIDTH),
conv_std_logic_vector(1802,AMPL_WIDTH),
conv_std_logic_vector(1803,AMPL_WIDTH),
conv_std_logic_vector(1803,AMPL_WIDTH),
conv_std_logic_vector(1803,AMPL_WIDTH),
conv_std_logic_vector(1804,AMPL_WIDTH),
conv_std_logic_vector(1804,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1806,AMPL_WIDTH),
conv_std_logic_vector(1806,AMPL_WIDTH),
conv_std_logic_vector(1806,AMPL_WIDTH),
conv_std_logic_vector(1807,AMPL_WIDTH),
conv_std_logic_vector(1807,AMPL_WIDTH),
conv_std_logic_vector(1808,AMPL_WIDTH),
conv_std_logic_vector(1808,AMPL_WIDTH),
conv_std_logic_vector(1808,AMPL_WIDTH),
conv_std_logic_vector(1809,AMPL_WIDTH),
conv_std_logic_vector(1809,AMPL_WIDTH),
conv_std_logic_vector(1809,AMPL_WIDTH),
conv_std_logic_vector(1810,AMPL_WIDTH),
conv_std_logic_vector(1810,AMPL_WIDTH),
conv_std_logic_vector(1810,AMPL_WIDTH),
conv_std_logic_vector(1811,AMPL_WIDTH),
conv_std_logic_vector(1811,AMPL_WIDTH),
conv_std_logic_vector(1812,AMPL_WIDTH),
conv_std_logic_vector(1812,AMPL_WIDTH),
conv_std_logic_vector(1812,AMPL_WIDTH),
conv_std_logic_vector(1813,AMPL_WIDTH),
conv_std_logic_vector(1813,AMPL_WIDTH),
conv_std_logic_vector(1813,AMPL_WIDTH),
conv_std_logic_vector(1814,AMPL_WIDTH),
conv_std_logic_vector(1814,AMPL_WIDTH),
conv_std_logic_vector(1814,AMPL_WIDTH),
conv_std_logic_vector(1815,AMPL_WIDTH),
conv_std_logic_vector(1815,AMPL_WIDTH),
conv_std_logic_vector(1816,AMPL_WIDTH),
conv_std_logic_vector(1816,AMPL_WIDTH),
conv_std_logic_vector(1816,AMPL_WIDTH),
conv_std_logic_vector(1817,AMPL_WIDTH),
conv_std_logic_vector(1817,AMPL_WIDTH),
conv_std_logic_vector(1817,AMPL_WIDTH),
conv_std_logic_vector(1818,AMPL_WIDTH),
conv_std_logic_vector(1818,AMPL_WIDTH),
conv_std_logic_vector(1818,AMPL_WIDTH),
conv_std_logic_vector(1819,AMPL_WIDTH),
conv_std_logic_vector(1819,AMPL_WIDTH),
conv_std_logic_vector(1820,AMPL_WIDTH),
conv_std_logic_vector(1820,AMPL_WIDTH),
conv_std_logic_vector(1820,AMPL_WIDTH),
conv_std_logic_vector(1821,AMPL_WIDTH),
conv_std_logic_vector(1821,AMPL_WIDTH),
conv_std_logic_vector(1821,AMPL_WIDTH),
conv_std_logic_vector(1822,AMPL_WIDTH),
conv_std_logic_vector(1822,AMPL_WIDTH),
conv_std_logic_vector(1822,AMPL_WIDTH),
conv_std_logic_vector(1823,AMPL_WIDTH),
conv_std_logic_vector(1823,AMPL_WIDTH),
conv_std_logic_vector(1823,AMPL_WIDTH),
conv_std_logic_vector(1824,AMPL_WIDTH),
conv_std_logic_vector(1824,AMPL_WIDTH),
conv_std_logic_vector(1825,AMPL_WIDTH),
conv_std_logic_vector(1825,AMPL_WIDTH),
conv_std_logic_vector(1825,AMPL_WIDTH),
conv_std_logic_vector(1826,AMPL_WIDTH),
conv_std_logic_vector(1826,AMPL_WIDTH),
conv_std_logic_vector(1826,AMPL_WIDTH),
conv_std_logic_vector(1827,AMPL_WIDTH),
conv_std_logic_vector(1827,AMPL_WIDTH),
conv_std_logic_vector(1827,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1829,AMPL_WIDTH),
conv_std_logic_vector(1829,AMPL_WIDTH),
conv_std_logic_vector(1829,AMPL_WIDTH),
conv_std_logic_vector(1830,AMPL_WIDTH),
conv_std_logic_vector(1830,AMPL_WIDTH),
conv_std_logic_vector(1831,AMPL_WIDTH),
conv_std_logic_vector(1831,AMPL_WIDTH),
conv_std_logic_vector(1831,AMPL_WIDTH),
conv_std_logic_vector(1832,AMPL_WIDTH),
conv_std_logic_vector(1832,AMPL_WIDTH),
conv_std_logic_vector(1832,AMPL_WIDTH),
conv_std_logic_vector(1833,AMPL_WIDTH),
conv_std_logic_vector(1833,AMPL_WIDTH),
conv_std_logic_vector(1833,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1835,AMPL_WIDTH),
conv_std_logic_vector(1835,AMPL_WIDTH),
conv_std_logic_vector(1835,AMPL_WIDTH),
conv_std_logic_vector(1836,AMPL_WIDTH),
conv_std_logic_vector(1836,AMPL_WIDTH),
conv_std_logic_vector(1836,AMPL_WIDTH),
conv_std_logic_vector(1837,AMPL_WIDTH),
conv_std_logic_vector(1837,AMPL_WIDTH),
conv_std_logic_vector(1838,AMPL_WIDTH),
conv_std_logic_vector(1838,AMPL_WIDTH),
conv_std_logic_vector(1838,AMPL_WIDTH),
conv_std_logic_vector(1839,AMPL_WIDTH),
conv_std_logic_vector(1839,AMPL_WIDTH),
conv_std_logic_vector(1839,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1841,AMPL_WIDTH),
conv_std_logic_vector(1841,AMPL_WIDTH),
conv_std_logic_vector(1841,AMPL_WIDTH),
conv_std_logic_vector(1842,AMPL_WIDTH),
conv_std_logic_vector(1842,AMPL_WIDTH),
conv_std_logic_vector(1842,AMPL_WIDTH),
conv_std_logic_vector(1843,AMPL_WIDTH),
conv_std_logic_vector(1843,AMPL_WIDTH),
conv_std_logic_vector(1843,AMPL_WIDTH),
conv_std_logic_vector(1844,AMPL_WIDTH),
conv_std_logic_vector(1844,AMPL_WIDTH),
conv_std_logic_vector(1844,AMPL_WIDTH),
conv_std_logic_vector(1845,AMPL_WIDTH),
conv_std_logic_vector(1845,AMPL_WIDTH),
conv_std_logic_vector(1845,AMPL_WIDTH),
conv_std_logic_vector(1846,AMPL_WIDTH),
conv_std_logic_vector(1846,AMPL_WIDTH),
conv_std_logic_vector(1846,AMPL_WIDTH),
conv_std_logic_vector(1847,AMPL_WIDTH),
conv_std_logic_vector(1847,AMPL_WIDTH),
conv_std_logic_vector(1847,AMPL_WIDTH),
conv_std_logic_vector(1848,AMPL_WIDTH),
conv_std_logic_vector(1848,AMPL_WIDTH),
conv_std_logic_vector(1848,AMPL_WIDTH),
conv_std_logic_vector(1849,AMPL_WIDTH),
conv_std_logic_vector(1849,AMPL_WIDTH),
conv_std_logic_vector(1849,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1851,AMPL_WIDTH),
conv_std_logic_vector(1851,AMPL_WIDTH),
conv_std_logic_vector(1851,AMPL_WIDTH),
conv_std_logic_vector(1852,AMPL_WIDTH),
conv_std_logic_vector(1852,AMPL_WIDTH),
conv_std_logic_vector(1852,AMPL_WIDTH),
conv_std_logic_vector(1853,AMPL_WIDTH),
conv_std_logic_vector(1853,AMPL_WIDTH),
conv_std_logic_vector(1853,AMPL_WIDTH),
conv_std_logic_vector(1854,AMPL_WIDTH),
conv_std_logic_vector(1854,AMPL_WIDTH),
conv_std_logic_vector(1854,AMPL_WIDTH),
conv_std_logic_vector(1855,AMPL_WIDTH),
conv_std_logic_vector(1855,AMPL_WIDTH),
conv_std_logic_vector(1855,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1857,AMPL_WIDTH),
conv_std_logic_vector(1857,AMPL_WIDTH),
conv_std_logic_vector(1857,AMPL_WIDTH),
conv_std_logic_vector(1858,AMPL_WIDTH),
conv_std_logic_vector(1858,AMPL_WIDTH),
conv_std_logic_vector(1858,AMPL_WIDTH),
conv_std_logic_vector(1859,AMPL_WIDTH),
conv_std_logic_vector(1859,AMPL_WIDTH),
conv_std_logic_vector(1859,AMPL_WIDTH),
conv_std_logic_vector(1860,AMPL_WIDTH),
conv_std_logic_vector(1860,AMPL_WIDTH),
conv_std_logic_vector(1860,AMPL_WIDTH),
conv_std_logic_vector(1861,AMPL_WIDTH),
conv_std_logic_vector(1861,AMPL_WIDTH),
conv_std_logic_vector(1861,AMPL_WIDTH),
conv_std_logic_vector(1862,AMPL_WIDTH),
conv_std_logic_vector(1862,AMPL_WIDTH),
conv_std_logic_vector(1862,AMPL_WIDTH),
conv_std_logic_vector(1863,AMPL_WIDTH),
conv_std_logic_vector(1863,AMPL_WIDTH),
conv_std_logic_vector(1863,AMPL_WIDTH),
conv_std_logic_vector(1864,AMPL_WIDTH),
conv_std_logic_vector(1864,AMPL_WIDTH),
conv_std_logic_vector(1864,AMPL_WIDTH),
conv_std_logic_vector(1865,AMPL_WIDTH),
conv_std_logic_vector(1865,AMPL_WIDTH),
conv_std_logic_vector(1865,AMPL_WIDTH),
conv_std_logic_vector(1866,AMPL_WIDTH),
conv_std_logic_vector(1866,AMPL_WIDTH),
conv_std_logic_vector(1866,AMPL_WIDTH),
conv_std_logic_vector(1867,AMPL_WIDTH),
conv_std_logic_vector(1867,AMPL_WIDTH),
conv_std_logic_vector(1867,AMPL_WIDTH),
conv_std_logic_vector(1868,AMPL_WIDTH),
conv_std_logic_vector(1868,AMPL_WIDTH),
conv_std_logic_vector(1868,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1870,AMPL_WIDTH),
conv_std_logic_vector(1870,AMPL_WIDTH),
conv_std_logic_vector(1870,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1872,AMPL_WIDTH),
conv_std_logic_vector(1872,AMPL_WIDTH),
conv_std_logic_vector(1872,AMPL_WIDTH),
conv_std_logic_vector(1873,AMPL_WIDTH),
conv_std_logic_vector(1873,AMPL_WIDTH),
conv_std_logic_vector(1873,AMPL_WIDTH),
conv_std_logic_vector(1874,AMPL_WIDTH),
conv_std_logic_vector(1874,AMPL_WIDTH),
conv_std_logic_vector(1874,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1876,AMPL_WIDTH),
conv_std_logic_vector(1876,AMPL_WIDTH),
conv_std_logic_vector(1876,AMPL_WIDTH),
conv_std_logic_vector(1877,AMPL_WIDTH),
conv_std_logic_vector(1877,AMPL_WIDTH),
conv_std_logic_vector(1877,AMPL_WIDTH),
conv_std_logic_vector(1878,AMPL_WIDTH),
conv_std_logic_vector(1878,AMPL_WIDTH),
conv_std_logic_vector(1878,AMPL_WIDTH),
conv_std_logic_vector(1879,AMPL_WIDTH),
conv_std_logic_vector(1879,AMPL_WIDTH),
conv_std_logic_vector(1879,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1882,AMPL_WIDTH),
conv_std_logic_vector(1882,AMPL_WIDTH),
conv_std_logic_vector(1882,AMPL_WIDTH),
conv_std_logic_vector(1883,AMPL_WIDTH),
conv_std_logic_vector(1883,AMPL_WIDTH),
conv_std_logic_vector(1883,AMPL_WIDTH),
conv_std_logic_vector(1884,AMPL_WIDTH),
conv_std_logic_vector(1884,AMPL_WIDTH),
conv_std_logic_vector(1884,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1886,AMPL_WIDTH),
conv_std_logic_vector(1886,AMPL_WIDTH),
conv_std_logic_vector(1886,AMPL_WIDTH),
conv_std_logic_vector(1887,AMPL_WIDTH),
conv_std_logic_vector(1887,AMPL_WIDTH),
conv_std_logic_vector(1887,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1889,AMPL_WIDTH),
conv_std_logic_vector(1889,AMPL_WIDTH),
conv_std_logic_vector(1889,AMPL_WIDTH),
conv_std_logic_vector(1890,AMPL_WIDTH),
conv_std_logic_vector(1890,AMPL_WIDTH),
conv_std_logic_vector(1890,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1892,AMPL_WIDTH),
conv_std_logic_vector(1892,AMPL_WIDTH),
conv_std_logic_vector(1892,AMPL_WIDTH),
conv_std_logic_vector(1893,AMPL_WIDTH),
conv_std_logic_vector(1893,AMPL_WIDTH),
conv_std_logic_vector(1893,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1895,AMPL_WIDTH),
conv_std_logic_vector(1895,AMPL_WIDTH),
conv_std_logic_vector(1895,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1898,AMPL_WIDTH),
conv_std_logic_vector(1898,AMPL_WIDTH),
conv_std_logic_vector(1898,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1900,AMPL_WIDTH),
conv_std_logic_vector(1900,AMPL_WIDTH),
conv_std_logic_vector(1900,AMPL_WIDTH),
conv_std_logic_vector(1901,AMPL_WIDTH),
conv_std_logic_vector(1901,AMPL_WIDTH),
conv_std_logic_vector(1901,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1903,AMPL_WIDTH),
conv_std_logic_vector(1903,AMPL_WIDTH),
conv_std_logic_vector(1903,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1905,AMPL_WIDTH),
conv_std_logic_vector(1905,AMPL_WIDTH),
conv_std_logic_vector(1905,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1907,AMPL_WIDTH),
conv_std_logic_vector(1907,AMPL_WIDTH),
conv_std_logic_vector(1907,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1911,AMPL_WIDTH),
conv_std_logic_vector(1911,AMPL_WIDTH),
conv_std_logic_vector(1911,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1914,AMPL_WIDTH),
conv_std_logic_vector(1914,AMPL_WIDTH),
conv_std_logic_vector(1914,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1916,AMPL_WIDTH),
conv_std_logic_vector(1916,AMPL_WIDTH),
conv_std_logic_vector(1916,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1919,AMPL_WIDTH),
conv_std_logic_vector(1919,AMPL_WIDTH),
conv_std_logic_vector(1919,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1922,AMPL_WIDTH),
conv_std_logic_vector(1922,AMPL_WIDTH),
conv_std_logic_vector(1922,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1926,AMPL_WIDTH),
conv_std_logic_vector(1926,AMPL_WIDTH),
conv_std_logic_vector(1926,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1931,AMPL_WIDTH),
conv_std_logic_vector(1931,AMPL_WIDTH),
conv_std_logic_vector(1931,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 14;
constant AMPL_WIDTH : integer := 12;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(512,AMPL_WIDTH),
conv_std_logic_vector(513,AMPL_WIDTH),
conv_std_logic_vector(513,AMPL_WIDTH),
conv_std_logic_vector(514,AMPL_WIDTH),
conv_std_logic_vector(515,AMPL_WIDTH),
conv_std_logic_vector(516,AMPL_WIDTH),
conv_std_logic_vector(516,AMPL_WIDTH),
conv_std_logic_vector(517,AMPL_WIDTH),
conv_std_logic_vector(518,AMPL_WIDTH),
conv_std_logic_vector(519,AMPL_WIDTH),
conv_std_logic_vector(519,AMPL_WIDTH),
conv_std_logic_vector(520,AMPL_WIDTH),
conv_std_logic_vector(521,AMPL_WIDTH),
conv_std_logic_vector(522,AMPL_WIDTH),
conv_std_logic_vector(522,AMPL_WIDTH),
conv_std_logic_vector(523,AMPL_WIDTH),
conv_std_logic_vector(524,AMPL_WIDTH),
conv_std_logic_vector(525,AMPL_WIDTH),
conv_std_logic_vector(526,AMPL_WIDTH),
conv_std_logic_vector(526,AMPL_WIDTH),
conv_std_logic_vector(527,AMPL_WIDTH),
conv_std_logic_vector(528,AMPL_WIDTH),
conv_std_logic_vector(529,AMPL_WIDTH),
conv_std_logic_vector(529,AMPL_WIDTH),
conv_std_logic_vector(530,AMPL_WIDTH),
conv_std_logic_vector(531,AMPL_WIDTH),
conv_std_logic_vector(532,AMPL_WIDTH),
conv_std_logic_vector(532,AMPL_WIDTH),
conv_std_logic_vector(533,AMPL_WIDTH),
conv_std_logic_vector(534,AMPL_WIDTH),
conv_std_logic_vector(535,AMPL_WIDTH),
conv_std_logic_vector(535,AMPL_WIDTH),
conv_std_logic_vector(536,AMPL_WIDTH),
conv_std_logic_vector(537,AMPL_WIDTH),
conv_std_logic_vector(538,AMPL_WIDTH),
conv_std_logic_vector(538,AMPL_WIDTH),
conv_std_logic_vector(539,AMPL_WIDTH),
conv_std_logic_vector(540,AMPL_WIDTH),
conv_std_logic_vector(541,AMPL_WIDTH),
conv_std_logic_vector(541,AMPL_WIDTH),
conv_std_logic_vector(542,AMPL_WIDTH),
conv_std_logic_vector(543,AMPL_WIDTH),
conv_std_logic_vector(544,AMPL_WIDTH),
conv_std_logic_vector(544,AMPL_WIDTH),
conv_std_logic_vector(545,AMPL_WIDTH),
conv_std_logic_vector(546,AMPL_WIDTH),
conv_std_logic_vector(547,AMPL_WIDTH),
conv_std_logic_vector(547,AMPL_WIDTH),
conv_std_logic_vector(548,AMPL_WIDTH),
conv_std_logic_vector(549,AMPL_WIDTH),
conv_std_logic_vector(550,AMPL_WIDTH),
conv_std_logic_vector(550,AMPL_WIDTH),
conv_std_logic_vector(551,AMPL_WIDTH),
conv_std_logic_vector(552,AMPL_WIDTH),
conv_std_logic_vector(553,AMPL_WIDTH),
conv_std_logic_vector(554,AMPL_WIDTH),
conv_std_logic_vector(554,AMPL_WIDTH),
conv_std_logic_vector(555,AMPL_WIDTH),
conv_std_logic_vector(556,AMPL_WIDTH),
conv_std_logic_vector(557,AMPL_WIDTH),
conv_std_logic_vector(557,AMPL_WIDTH),
conv_std_logic_vector(558,AMPL_WIDTH),
conv_std_logic_vector(559,AMPL_WIDTH),
conv_std_logic_vector(560,AMPL_WIDTH),
conv_std_logic_vector(560,AMPL_WIDTH),
conv_std_logic_vector(561,AMPL_WIDTH),
conv_std_logic_vector(562,AMPL_WIDTH),
conv_std_logic_vector(563,AMPL_WIDTH),
conv_std_logic_vector(563,AMPL_WIDTH),
conv_std_logic_vector(564,AMPL_WIDTH),
conv_std_logic_vector(565,AMPL_WIDTH),
conv_std_logic_vector(566,AMPL_WIDTH),
conv_std_logic_vector(566,AMPL_WIDTH),
conv_std_logic_vector(567,AMPL_WIDTH),
conv_std_logic_vector(568,AMPL_WIDTH),
conv_std_logic_vector(569,AMPL_WIDTH),
conv_std_logic_vector(569,AMPL_WIDTH),
conv_std_logic_vector(570,AMPL_WIDTH),
conv_std_logic_vector(571,AMPL_WIDTH),
conv_std_logic_vector(572,AMPL_WIDTH),
conv_std_logic_vector(572,AMPL_WIDTH),
conv_std_logic_vector(573,AMPL_WIDTH),
conv_std_logic_vector(574,AMPL_WIDTH),
conv_std_logic_vector(575,AMPL_WIDTH),
conv_std_logic_vector(575,AMPL_WIDTH),
conv_std_logic_vector(576,AMPL_WIDTH),
conv_std_logic_vector(577,AMPL_WIDTH),
conv_std_logic_vector(578,AMPL_WIDTH),
conv_std_logic_vector(578,AMPL_WIDTH),
conv_std_logic_vector(579,AMPL_WIDTH),
conv_std_logic_vector(580,AMPL_WIDTH),
conv_std_logic_vector(581,AMPL_WIDTH),
conv_std_logic_vector(581,AMPL_WIDTH),
conv_std_logic_vector(582,AMPL_WIDTH),
conv_std_logic_vector(583,AMPL_WIDTH),
conv_std_logic_vector(584,AMPL_WIDTH),
conv_std_logic_vector(584,AMPL_WIDTH),
conv_std_logic_vector(585,AMPL_WIDTH),
conv_std_logic_vector(586,AMPL_WIDTH),
conv_std_logic_vector(587,AMPL_WIDTH),
conv_std_logic_vector(587,AMPL_WIDTH),
conv_std_logic_vector(588,AMPL_WIDTH),
conv_std_logic_vector(589,AMPL_WIDTH),
conv_std_logic_vector(590,AMPL_WIDTH),
conv_std_logic_vector(590,AMPL_WIDTH),
conv_std_logic_vector(591,AMPL_WIDTH),
conv_std_logic_vector(592,AMPL_WIDTH),
conv_std_logic_vector(593,AMPL_WIDTH),
conv_std_logic_vector(593,AMPL_WIDTH),
conv_std_logic_vector(594,AMPL_WIDTH),
conv_std_logic_vector(595,AMPL_WIDTH),
conv_std_logic_vector(596,AMPL_WIDTH),
conv_std_logic_vector(596,AMPL_WIDTH),
conv_std_logic_vector(597,AMPL_WIDTH),
conv_std_logic_vector(598,AMPL_WIDTH),
conv_std_logic_vector(599,AMPL_WIDTH),
conv_std_logic_vector(599,AMPL_WIDTH),
conv_std_logic_vector(600,AMPL_WIDTH),
conv_std_logic_vector(601,AMPL_WIDTH),
conv_std_logic_vector(602,AMPL_WIDTH),
conv_std_logic_vector(602,AMPL_WIDTH),
conv_std_logic_vector(603,AMPL_WIDTH),
conv_std_logic_vector(604,AMPL_WIDTH),
conv_std_logic_vector(605,AMPL_WIDTH),
conv_std_logic_vector(605,AMPL_WIDTH),
conv_std_logic_vector(606,AMPL_WIDTH),
conv_std_logic_vector(607,AMPL_WIDTH),
conv_std_logic_vector(608,AMPL_WIDTH),
conv_std_logic_vector(608,AMPL_WIDTH),
conv_std_logic_vector(609,AMPL_WIDTH),
conv_std_logic_vector(610,AMPL_WIDTH),
conv_std_logic_vector(611,AMPL_WIDTH),
conv_std_logic_vector(611,AMPL_WIDTH),
conv_std_logic_vector(612,AMPL_WIDTH),
conv_std_logic_vector(613,AMPL_WIDTH),
conv_std_logic_vector(614,AMPL_WIDTH),
conv_std_logic_vector(614,AMPL_WIDTH),
conv_std_logic_vector(615,AMPL_WIDTH),
conv_std_logic_vector(616,AMPL_WIDTH),
conv_std_logic_vector(617,AMPL_WIDTH),
conv_std_logic_vector(617,AMPL_WIDTH),
conv_std_logic_vector(618,AMPL_WIDTH),
conv_std_logic_vector(619,AMPL_WIDTH),
conv_std_logic_vector(620,AMPL_WIDTH),
conv_std_logic_vector(620,AMPL_WIDTH),
conv_std_logic_vector(621,AMPL_WIDTH),
conv_std_logic_vector(622,AMPL_WIDTH),
conv_std_logic_vector(623,AMPL_WIDTH),
conv_std_logic_vector(623,AMPL_WIDTH),
conv_std_logic_vector(624,AMPL_WIDTH),
conv_std_logic_vector(625,AMPL_WIDTH),
conv_std_logic_vector(626,AMPL_WIDTH),
conv_std_logic_vector(626,AMPL_WIDTH),
conv_std_logic_vector(627,AMPL_WIDTH),
conv_std_logic_vector(628,AMPL_WIDTH),
conv_std_logic_vector(629,AMPL_WIDTH),
conv_std_logic_vector(629,AMPL_WIDTH),
conv_std_logic_vector(630,AMPL_WIDTH),
conv_std_logic_vector(631,AMPL_WIDTH),
conv_std_logic_vector(632,AMPL_WIDTH),
conv_std_logic_vector(632,AMPL_WIDTH),
conv_std_logic_vector(633,AMPL_WIDTH),
conv_std_logic_vector(634,AMPL_WIDTH),
conv_std_logic_vector(635,AMPL_WIDTH),
conv_std_logic_vector(635,AMPL_WIDTH),
conv_std_logic_vector(636,AMPL_WIDTH),
conv_std_logic_vector(637,AMPL_WIDTH),
conv_std_logic_vector(638,AMPL_WIDTH),
conv_std_logic_vector(638,AMPL_WIDTH),
conv_std_logic_vector(639,AMPL_WIDTH),
conv_std_logic_vector(640,AMPL_WIDTH),
conv_std_logic_vector(641,AMPL_WIDTH),
conv_std_logic_vector(641,AMPL_WIDTH),
conv_std_logic_vector(642,AMPL_WIDTH),
conv_std_logic_vector(643,AMPL_WIDTH),
conv_std_logic_vector(644,AMPL_WIDTH),
conv_std_logic_vector(644,AMPL_WIDTH),
conv_std_logic_vector(645,AMPL_WIDTH),
conv_std_logic_vector(646,AMPL_WIDTH),
conv_std_logic_vector(647,AMPL_WIDTH),
conv_std_logic_vector(647,AMPL_WIDTH),
conv_std_logic_vector(648,AMPL_WIDTH),
conv_std_logic_vector(649,AMPL_WIDTH),
conv_std_logic_vector(650,AMPL_WIDTH),
conv_std_logic_vector(650,AMPL_WIDTH),
conv_std_logic_vector(651,AMPL_WIDTH),
conv_std_logic_vector(652,AMPL_WIDTH),
conv_std_logic_vector(653,AMPL_WIDTH),
conv_std_logic_vector(653,AMPL_WIDTH),
conv_std_logic_vector(654,AMPL_WIDTH),
conv_std_logic_vector(655,AMPL_WIDTH),
conv_std_logic_vector(656,AMPL_WIDTH),
conv_std_logic_vector(656,AMPL_WIDTH),
conv_std_logic_vector(657,AMPL_WIDTH),
conv_std_logic_vector(658,AMPL_WIDTH),
conv_std_logic_vector(658,AMPL_WIDTH),
conv_std_logic_vector(659,AMPL_WIDTH),
conv_std_logic_vector(660,AMPL_WIDTH),
conv_std_logic_vector(661,AMPL_WIDTH),
conv_std_logic_vector(661,AMPL_WIDTH),
conv_std_logic_vector(662,AMPL_WIDTH),
conv_std_logic_vector(663,AMPL_WIDTH),
conv_std_logic_vector(664,AMPL_WIDTH),
conv_std_logic_vector(664,AMPL_WIDTH),
conv_std_logic_vector(665,AMPL_WIDTH),
conv_std_logic_vector(666,AMPL_WIDTH),
conv_std_logic_vector(667,AMPL_WIDTH),
conv_std_logic_vector(667,AMPL_WIDTH),
conv_std_logic_vector(668,AMPL_WIDTH),
conv_std_logic_vector(669,AMPL_WIDTH),
conv_std_logic_vector(670,AMPL_WIDTH),
conv_std_logic_vector(670,AMPL_WIDTH),
conv_std_logic_vector(671,AMPL_WIDTH),
conv_std_logic_vector(672,AMPL_WIDTH),
conv_std_logic_vector(673,AMPL_WIDTH),
conv_std_logic_vector(673,AMPL_WIDTH),
conv_std_logic_vector(674,AMPL_WIDTH),
conv_std_logic_vector(675,AMPL_WIDTH),
conv_std_logic_vector(676,AMPL_WIDTH),
conv_std_logic_vector(676,AMPL_WIDTH),
conv_std_logic_vector(677,AMPL_WIDTH),
conv_std_logic_vector(678,AMPL_WIDTH),
conv_std_logic_vector(679,AMPL_WIDTH),
conv_std_logic_vector(679,AMPL_WIDTH),
conv_std_logic_vector(680,AMPL_WIDTH),
conv_std_logic_vector(681,AMPL_WIDTH),
conv_std_logic_vector(681,AMPL_WIDTH),
conv_std_logic_vector(682,AMPL_WIDTH),
conv_std_logic_vector(683,AMPL_WIDTH),
conv_std_logic_vector(684,AMPL_WIDTH),
conv_std_logic_vector(684,AMPL_WIDTH),
conv_std_logic_vector(685,AMPL_WIDTH),
conv_std_logic_vector(686,AMPL_WIDTH),
conv_std_logic_vector(687,AMPL_WIDTH),
conv_std_logic_vector(687,AMPL_WIDTH),
conv_std_logic_vector(688,AMPL_WIDTH),
conv_std_logic_vector(689,AMPL_WIDTH),
conv_std_logic_vector(690,AMPL_WIDTH),
conv_std_logic_vector(690,AMPL_WIDTH),
conv_std_logic_vector(691,AMPL_WIDTH),
conv_std_logic_vector(692,AMPL_WIDTH),
conv_std_logic_vector(693,AMPL_WIDTH),
conv_std_logic_vector(693,AMPL_WIDTH),
conv_std_logic_vector(694,AMPL_WIDTH),
conv_std_logic_vector(695,AMPL_WIDTH),
conv_std_logic_vector(696,AMPL_WIDTH),
conv_std_logic_vector(696,AMPL_WIDTH),
conv_std_logic_vector(697,AMPL_WIDTH),
conv_std_logic_vector(698,AMPL_WIDTH),
conv_std_logic_vector(698,AMPL_WIDTH),
conv_std_logic_vector(699,AMPL_WIDTH),
conv_std_logic_vector(700,AMPL_WIDTH),
conv_std_logic_vector(701,AMPL_WIDTH),
conv_std_logic_vector(701,AMPL_WIDTH),
conv_std_logic_vector(702,AMPL_WIDTH),
conv_std_logic_vector(703,AMPL_WIDTH),
conv_std_logic_vector(704,AMPL_WIDTH),
conv_std_logic_vector(704,AMPL_WIDTH),
conv_std_logic_vector(705,AMPL_WIDTH),
conv_std_logic_vector(706,AMPL_WIDTH),
conv_std_logic_vector(707,AMPL_WIDTH),
conv_std_logic_vector(707,AMPL_WIDTH),
conv_std_logic_vector(708,AMPL_WIDTH),
conv_std_logic_vector(709,AMPL_WIDTH),
conv_std_logic_vector(710,AMPL_WIDTH),
conv_std_logic_vector(710,AMPL_WIDTH),
conv_std_logic_vector(711,AMPL_WIDTH),
conv_std_logic_vector(712,AMPL_WIDTH),
conv_std_logic_vector(712,AMPL_WIDTH),
conv_std_logic_vector(713,AMPL_WIDTH),
conv_std_logic_vector(714,AMPL_WIDTH),
conv_std_logic_vector(715,AMPL_WIDTH),
conv_std_logic_vector(715,AMPL_WIDTH),
conv_std_logic_vector(716,AMPL_WIDTH),
conv_std_logic_vector(717,AMPL_WIDTH),
conv_std_logic_vector(718,AMPL_WIDTH),
conv_std_logic_vector(718,AMPL_WIDTH),
conv_std_logic_vector(719,AMPL_WIDTH),
conv_std_logic_vector(720,AMPL_WIDTH),
conv_std_logic_vector(721,AMPL_WIDTH),
conv_std_logic_vector(721,AMPL_WIDTH),
conv_std_logic_vector(722,AMPL_WIDTH),
conv_std_logic_vector(723,AMPL_WIDTH),
conv_std_logic_vector(724,AMPL_WIDTH),
conv_std_logic_vector(724,AMPL_WIDTH),
conv_std_logic_vector(725,AMPL_WIDTH),
conv_std_logic_vector(726,AMPL_WIDTH),
conv_std_logic_vector(726,AMPL_WIDTH),
conv_std_logic_vector(727,AMPL_WIDTH),
conv_std_logic_vector(728,AMPL_WIDTH),
conv_std_logic_vector(729,AMPL_WIDTH),
conv_std_logic_vector(729,AMPL_WIDTH),
conv_std_logic_vector(730,AMPL_WIDTH),
conv_std_logic_vector(731,AMPL_WIDTH),
conv_std_logic_vector(732,AMPL_WIDTH),
conv_std_logic_vector(732,AMPL_WIDTH),
conv_std_logic_vector(733,AMPL_WIDTH),
conv_std_logic_vector(734,AMPL_WIDTH),
conv_std_logic_vector(735,AMPL_WIDTH),
conv_std_logic_vector(735,AMPL_WIDTH),
conv_std_logic_vector(736,AMPL_WIDTH),
conv_std_logic_vector(737,AMPL_WIDTH),
conv_std_logic_vector(737,AMPL_WIDTH),
conv_std_logic_vector(738,AMPL_WIDTH),
conv_std_logic_vector(739,AMPL_WIDTH),
conv_std_logic_vector(740,AMPL_WIDTH),
conv_std_logic_vector(740,AMPL_WIDTH),
conv_std_logic_vector(741,AMPL_WIDTH),
conv_std_logic_vector(742,AMPL_WIDTH),
conv_std_logic_vector(743,AMPL_WIDTH),
conv_std_logic_vector(743,AMPL_WIDTH),
conv_std_logic_vector(744,AMPL_WIDTH),
conv_std_logic_vector(745,AMPL_WIDTH),
conv_std_logic_vector(745,AMPL_WIDTH),
conv_std_logic_vector(746,AMPL_WIDTH),
conv_std_logic_vector(747,AMPL_WIDTH),
conv_std_logic_vector(748,AMPL_WIDTH),
conv_std_logic_vector(748,AMPL_WIDTH),
conv_std_logic_vector(749,AMPL_WIDTH),
conv_std_logic_vector(750,AMPL_WIDTH),
conv_std_logic_vector(751,AMPL_WIDTH),
conv_std_logic_vector(751,AMPL_WIDTH),
conv_std_logic_vector(752,AMPL_WIDTH),
conv_std_logic_vector(753,AMPL_WIDTH),
conv_std_logic_vector(754,AMPL_WIDTH),
conv_std_logic_vector(754,AMPL_WIDTH),
conv_std_logic_vector(755,AMPL_WIDTH),
conv_std_logic_vector(756,AMPL_WIDTH),
conv_std_logic_vector(756,AMPL_WIDTH),
conv_std_logic_vector(757,AMPL_WIDTH),
conv_std_logic_vector(758,AMPL_WIDTH),
conv_std_logic_vector(759,AMPL_WIDTH),
conv_std_logic_vector(759,AMPL_WIDTH),
conv_std_logic_vector(760,AMPL_WIDTH),
conv_std_logic_vector(761,AMPL_WIDTH),
conv_std_logic_vector(762,AMPL_WIDTH),
conv_std_logic_vector(762,AMPL_WIDTH),
conv_std_logic_vector(763,AMPL_WIDTH),
conv_std_logic_vector(764,AMPL_WIDTH),
conv_std_logic_vector(764,AMPL_WIDTH),
conv_std_logic_vector(765,AMPL_WIDTH),
conv_std_logic_vector(766,AMPL_WIDTH),
conv_std_logic_vector(767,AMPL_WIDTH),
conv_std_logic_vector(767,AMPL_WIDTH),
conv_std_logic_vector(768,AMPL_WIDTH),
conv_std_logic_vector(769,AMPL_WIDTH),
conv_std_logic_vector(770,AMPL_WIDTH),
conv_std_logic_vector(770,AMPL_WIDTH),
conv_std_logic_vector(771,AMPL_WIDTH),
conv_std_logic_vector(772,AMPL_WIDTH),
conv_std_logic_vector(772,AMPL_WIDTH),
conv_std_logic_vector(773,AMPL_WIDTH),
conv_std_logic_vector(774,AMPL_WIDTH),
conv_std_logic_vector(775,AMPL_WIDTH),
conv_std_logic_vector(775,AMPL_WIDTH),
conv_std_logic_vector(776,AMPL_WIDTH),
conv_std_logic_vector(777,AMPL_WIDTH),
conv_std_logic_vector(778,AMPL_WIDTH),
conv_std_logic_vector(778,AMPL_WIDTH),
conv_std_logic_vector(779,AMPL_WIDTH),
conv_std_logic_vector(780,AMPL_WIDTH),
conv_std_logic_vector(780,AMPL_WIDTH),
conv_std_logic_vector(781,AMPL_WIDTH),
conv_std_logic_vector(782,AMPL_WIDTH),
conv_std_logic_vector(783,AMPL_WIDTH),
conv_std_logic_vector(783,AMPL_WIDTH),
conv_std_logic_vector(784,AMPL_WIDTH),
conv_std_logic_vector(785,AMPL_WIDTH),
conv_std_logic_vector(786,AMPL_WIDTH),
conv_std_logic_vector(786,AMPL_WIDTH),
conv_std_logic_vector(787,AMPL_WIDTH),
conv_std_logic_vector(788,AMPL_WIDTH),
conv_std_logic_vector(788,AMPL_WIDTH),
conv_std_logic_vector(789,AMPL_WIDTH),
conv_std_logic_vector(790,AMPL_WIDTH),
conv_std_logic_vector(791,AMPL_WIDTH),
conv_std_logic_vector(791,AMPL_WIDTH),
conv_std_logic_vector(792,AMPL_WIDTH),
conv_std_logic_vector(793,AMPL_WIDTH),
conv_std_logic_vector(793,AMPL_WIDTH),
conv_std_logic_vector(794,AMPL_WIDTH),
conv_std_logic_vector(795,AMPL_WIDTH),
conv_std_logic_vector(796,AMPL_WIDTH),
conv_std_logic_vector(796,AMPL_WIDTH),
conv_std_logic_vector(797,AMPL_WIDTH),
conv_std_logic_vector(798,AMPL_WIDTH),
conv_std_logic_vector(799,AMPL_WIDTH),
conv_std_logic_vector(799,AMPL_WIDTH),
conv_std_logic_vector(800,AMPL_WIDTH),
conv_std_logic_vector(801,AMPL_WIDTH),
conv_std_logic_vector(801,AMPL_WIDTH),
conv_std_logic_vector(802,AMPL_WIDTH),
conv_std_logic_vector(803,AMPL_WIDTH),
conv_std_logic_vector(804,AMPL_WIDTH),
conv_std_logic_vector(804,AMPL_WIDTH),
conv_std_logic_vector(805,AMPL_WIDTH),
conv_std_logic_vector(806,AMPL_WIDTH),
conv_std_logic_vector(807,AMPL_WIDTH),
conv_std_logic_vector(807,AMPL_WIDTH),
conv_std_logic_vector(808,AMPL_WIDTH),
conv_std_logic_vector(809,AMPL_WIDTH),
conv_std_logic_vector(809,AMPL_WIDTH),
conv_std_logic_vector(810,AMPL_WIDTH),
conv_std_logic_vector(811,AMPL_WIDTH),
conv_std_logic_vector(812,AMPL_WIDTH),
conv_std_logic_vector(812,AMPL_WIDTH),
conv_std_logic_vector(813,AMPL_WIDTH),
conv_std_logic_vector(814,AMPL_WIDTH),
conv_std_logic_vector(814,AMPL_WIDTH),
conv_std_logic_vector(815,AMPL_WIDTH),
conv_std_logic_vector(816,AMPL_WIDTH),
conv_std_logic_vector(817,AMPL_WIDTH),
conv_std_logic_vector(817,AMPL_WIDTH),
conv_std_logic_vector(818,AMPL_WIDTH),
conv_std_logic_vector(819,AMPL_WIDTH),
conv_std_logic_vector(819,AMPL_WIDTH),
conv_std_logic_vector(820,AMPL_WIDTH),
conv_std_logic_vector(821,AMPL_WIDTH),
conv_std_logic_vector(822,AMPL_WIDTH),
conv_std_logic_vector(822,AMPL_WIDTH),
conv_std_logic_vector(823,AMPL_WIDTH),
conv_std_logic_vector(824,AMPL_WIDTH),
conv_std_logic_vector(825,AMPL_WIDTH),
conv_std_logic_vector(825,AMPL_WIDTH),
conv_std_logic_vector(826,AMPL_WIDTH),
conv_std_logic_vector(827,AMPL_WIDTH),
conv_std_logic_vector(827,AMPL_WIDTH),
conv_std_logic_vector(828,AMPL_WIDTH),
conv_std_logic_vector(829,AMPL_WIDTH),
conv_std_logic_vector(830,AMPL_WIDTH),
conv_std_logic_vector(830,AMPL_WIDTH),
conv_std_logic_vector(831,AMPL_WIDTH),
conv_std_logic_vector(832,AMPL_WIDTH),
conv_std_logic_vector(832,AMPL_WIDTH),
conv_std_logic_vector(833,AMPL_WIDTH),
conv_std_logic_vector(834,AMPL_WIDTH),
conv_std_logic_vector(835,AMPL_WIDTH),
conv_std_logic_vector(835,AMPL_WIDTH),
conv_std_logic_vector(836,AMPL_WIDTH),
conv_std_logic_vector(837,AMPL_WIDTH),
conv_std_logic_vector(837,AMPL_WIDTH),
conv_std_logic_vector(838,AMPL_WIDTH),
conv_std_logic_vector(839,AMPL_WIDTH),
conv_std_logic_vector(840,AMPL_WIDTH),
conv_std_logic_vector(840,AMPL_WIDTH),
conv_std_logic_vector(841,AMPL_WIDTH),
conv_std_logic_vector(842,AMPL_WIDTH),
conv_std_logic_vector(842,AMPL_WIDTH),
conv_std_logic_vector(843,AMPL_WIDTH),
conv_std_logic_vector(844,AMPL_WIDTH),
conv_std_logic_vector(845,AMPL_WIDTH),
conv_std_logic_vector(845,AMPL_WIDTH),
conv_std_logic_vector(846,AMPL_WIDTH),
conv_std_logic_vector(847,AMPL_WIDTH),
conv_std_logic_vector(847,AMPL_WIDTH),
conv_std_logic_vector(848,AMPL_WIDTH),
conv_std_logic_vector(849,AMPL_WIDTH),
conv_std_logic_vector(850,AMPL_WIDTH),
conv_std_logic_vector(850,AMPL_WIDTH),
conv_std_logic_vector(851,AMPL_WIDTH),
conv_std_logic_vector(852,AMPL_WIDTH),
conv_std_logic_vector(852,AMPL_WIDTH),
conv_std_logic_vector(853,AMPL_WIDTH),
conv_std_logic_vector(854,AMPL_WIDTH),
conv_std_logic_vector(855,AMPL_WIDTH),
conv_std_logic_vector(855,AMPL_WIDTH),
conv_std_logic_vector(856,AMPL_WIDTH),
conv_std_logic_vector(857,AMPL_WIDTH),
conv_std_logic_vector(857,AMPL_WIDTH),
conv_std_logic_vector(858,AMPL_WIDTH),
conv_std_logic_vector(859,AMPL_WIDTH),
conv_std_logic_vector(860,AMPL_WIDTH),
conv_std_logic_vector(860,AMPL_WIDTH),
conv_std_logic_vector(861,AMPL_WIDTH),
conv_std_logic_vector(862,AMPL_WIDTH),
conv_std_logic_vector(862,AMPL_WIDTH),
conv_std_logic_vector(863,AMPL_WIDTH),
conv_std_logic_vector(864,AMPL_WIDTH),
conv_std_logic_vector(865,AMPL_WIDTH),
conv_std_logic_vector(865,AMPL_WIDTH),
conv_std_logic_vector(866,AMPL_WIDTH),
conv_std_logic_vector(867,AMPL_WIDTH),
conv_std_logic_vector(867,AMPL_WIDTH),
conv_std_logic_vector(868,AMPL_WIDTH),
conv_std_logic_vector(869,AMPL_WIDTH),
conv_std_logic_vector(870,AMPL_WIDTH),
conv_std_logic_vector(870,AMPL_WIDTH),
conv_std_logic_vector(871,AMPL_WIDTH),
conv_std_logic_vector(872,AMPL_WIDTH),
conv_std_logic_vector(872,AMPL_WIDTH),
conv_std_logic_vector(873,AMPL_WIDTH),
conv_std_logic_vector(874,AMPL_WIDTH),
conv_std_logic_vector(874,AMPL_WIDTH),
conv_std_logic_vector(875,AMPL_WIDTH),
conv_std_logic_vector(876,AMPL_WIDTH),
conv_std_logic_vector(877,AMPL_WIDTH),
conv_std_logic_vector(877,AMPL_WIDTH),
conv_std_logic_vector(878,AMPL_WIDTH),
conv_std_logic_vector(879,AMPL_WIDTH),
conv_std_logic_vector(879,AMPL_WIDTH),
conv_std_logic_vector(880,AMPL_WIDTH),
conv_std_logic_vector(881,AMPL_WIDTH),
conv_std_logic_vector(882,AMPL_WIDTH),
conv_std_logic_vector(882,AMPL_WIDTH),
conv_std_logic_vector(883,AMPL_WIDTH),
conv_std_logic_vector(884,AMPL_WIDTH),
conv_std_logic_vector(884,AMPL_WIDTH),
conv_std_logic_vector(885,AMPL_WIDTH),
conv_std_logic_vector(886,AMPL_WIDTH),
conv_std_logic_vector(887,AMPL_WIDTH),
conv_std_logic_vector(887,AMPL_WIDTH),
conv_std_logic_vector(888,AMPL_WIDTH),
conv_std_logic_vector(889,AMPL_WIDTH),
conv_std_logic_vector(889,AMPL_WIDTH),
conv_std_logic_vector(890,AMPL_WIDTH),
conv_std_logic_vector(891,AMPL_WIDTH),
conv_std_logic_vector(891,AMPL_WIDTH),
conv_std_logic_vector(892,AMPL_WIDTH),
conv_std_logic_vector(893,AMPL_WIDTH),
conv_std_logic_vector(894,AMPL_WIDTH),
conv_std_logic_vector(894,AMPL_WIDTH),
conv_std_logic_vector(895,AMPL_WIDTH),
conv_std_logic_vector(896,AMPL_WIDTH),
conv_std_logic_vector(896,AMPL_WIDTH),
conv_std_logic_vector(897,AMPL_WIDTH),
conv_std_logic_vector(898,AMPL_WIDTH),
conv_std_logic_vector(899,AMPL_WIDTH),
conv_std_logic_vector(899,AMPL_WIDTH),
conv_std_logic_vector(900,AMPL_WIDTH),
conv_std_logic_vector(901,AMPL_WIDTH),
conv_std_logic_vector(901,AMPL_WIDTH),
conv_std_logic_vector(902,AMPL_WIDTH),
conv_std_logic_vector(903,AMPL_WIDTH),
conv_std_logic_vector(903,AMPL_WIDTH),
conv_std_logic_vector(904,AMPL_WIDTH),
conv_std_logic_vector(905,AMPL_WIDTH),
conv_std_logic_vector(906,AMPL_WIDTH),
conv_std_logic_vector(906,AMPL_WIDTH),
conv_std_logic_vector(907,AMPL_WIDTH),
conv_std_logic_vector(908,AMPL_WIDTH),
conv_std_logic_vector(908,AMPL_WIDTH),
conv_std_logic_vector(909,AMPL_WIDTH),
conv_std_logic_vector(910,AMPL_WIDTH),
conv_std_logic_vector(911,AMPL_WIDTH),
conv_std_logic_vector(911,AMPL_WIDTH),
conv_std_logic_vector(912,AMPL_WIDTH),
conv_std_logic_vector(913,AMPL_WIDTH),
conv_std_logic_vector(913,AMPL_WIDTH),
conv_std_logic_vector(914,AMPL_WIDTH),
conv_std_logic_vector(915,AMPL_WIDTH),
conv_std_logic_vector(915,AMPL_WIDTH),
conv_std_logic_vector(916,AMPL_WIDTH),
conv_std_logic_vector(917,AMPL_WIDTH),
conv_std_logic_vector(918,AMPL_WIDTH),
conv_std_logic_vector(918,AMPL_WIDTH),
conv_std_logic_vector(919,AMPL_WIDTH),
conv_std_logic_vector(920,AMPL_WIDTH),
conv_std_logic_vector(920,AMPL_WIDTH),
conv_std_logic_vector(921,AMPL_WIDTH),
conv_std_logic_vector(922,AMPL_WIDTH),
conv_std_logic_vector(922,AMPL_WIDTH),
conv_std_logic_vector(923,AMPL_WIDTH),
conv_std_logic_vector(924,AMPL_WIDTH),
conv_std_logic_vector(925,AMPL_WIDTH),
conv_std_logic_vector(925,AMPL_WIDTH),
conv_std_logic_vector(926,AMPL_WIDTH),
conv_std_logic_vector(927,AMPL_WIDTH),
conv_std_logic_vector(927,AMPL_WIDTH),
conv_std_logic_vector(928,AMPL_WIDTH),
conv_std_logic_vector(929,AMPL_WIDTH),
conv_std_logic_vector(929,AMPL_WIDTH),
conv_std_logic_vector(930,AMPL_WIDTH),
conv_std_logic_vector(931,AMPL_WIDTH),
conv_std_logic_vector(932,AMPL_WIDTH),
conv_std_logic_vector(932,AMPL_WIDTH),
conv_std_logic_vector(933,AMPL_WIDTH),
conv_std_logic_vector(934,AMPL_WIDTH),
conv_std_logic_vector(934,AMPL_WIDTH),
conv_std_logic_vector(935,AMPL_WIDTH),
conv_std_logic_vector(936,AMPL_WIDTH),
conv_std_logic_vector(936,AMPL_WIDTH),
conv_std_logic_vector(937,AMPL_WIDTH),
conv_std_logic_vector(938,AMPL_WIDTH),
conv_std_logic_vector(939,AMPL_WIDTH),
conv_std_logic_vector(939,AMPL_WIDTH),
conv_std_logic_vector(940,AMPL_WIDTH),
conv_std_logic_vector(941,AMPL_WIDTH),
conv_std_logic_vector(941,AMPL_WIDTH),
conv_std_logic_vector(942,AMPL_WIDTH),
conv_std_logic_vector(943,AMPL_WIDTH),
conv_std_logic_vector(943,AMPL_WIDTH),
conv_std_logic_vector(944,AMPL_WIDTH),
conv_std_logic_vector(945,AMPL_WIDTH),
conv_std_logic_vector(946,AMPL_WIDTH),
conv_std_logic_vector(946,AMPL_WIDTH),
conv_std_logic_vector(947,AMPL_WIDTH),
conv_std_logic_vector(948,AMPL_WIDTH),
conv_std_logic_vector(948,AMPL_WIDTH),
conv_std_logic_vector(949,AMPL_WIDTH),
conv_std_logic_vector(950,AMPL_WIDTH),
conv_std_logic_vector(950,AMPL_WIDTH),
conv_std_logic_vector(951,AMPL_WIDTH),
conv_std_logic_vector(952,AMPL_WIDTH),
conv_std_logic_vector(952,AMPL_WIDTH),
conv_std_logic_vector(953,AMPL_WIDTH),
conv_std_logic_vector(954,AMPL_WIDTH),
conv_std_logic_vector(955,AMPL_WIDTH),
conv_std_logic_vector(955,AMPL_WIDTH),
conv_std_logic_vector(956,AMPL_WIDTH),
conv_std_logic_vector(957,AMPL_WIDTH),
conv_std_logic_vector(957,AMPL_WIDTH),
conv_std_logic_vector(958,AMPL_WIDTH),
conv_std_logic_vector(959,AMPL_WIDTH),
conv_std_logic_vector(959,AMPL_WIDTH),
conv_std_logic_vector(960,AMPL_WIDTH),
conv_std_logic_vector(961,AMPL_WIDTH),
conv_std_logic_vector(961,AMPL_WIDTH),
conv_std_logic_vector(962,AMPL_WIDTH),
conv_std_logic_vector(963,AMPL_WIDTH),
conv_std_logic_vector(964,AMPL_WIDTH),
conv_std_logic_vector(964,AMPL_WIDTH),
conv_std_logic_vector(965,AMPL_WIDTH),
conv_std_logic_vector(966,AMPL_WIDTH),
conv_std_logic_vector(966,AMPL_WIDTH),
conv_std_logic_vector(967,AMPL_WIDTH),
conv_std_logic_vector(968,AMPL_WIDTH),
conv_std_logic_vector(968,AMPL_WIDTH),
conv_std_logic_vector(969,AMPL_WIDTH),
conv_std_logic_vector(970,AMPL_WIDTH),
conv_std_logic_vector(970,AMPL_WIDTH),
conv_std_logic_vector(971,AMPL_WIDTH),
conv_std_logic_vector(972,AMPL_WIDTH),
conv_std_logic_vector(973,AMPL_WIDTH),
conv_std_logic_vector(973,AMPL_WIDTH),
conv_std_logic_vector(974,AMPL_WIDTH),
conv_std_logic_vector(975,AMPL_WIDTH),
conv_std_logic_vector(975,AMPL_WIDTH),
conv_std_logic_vector(976,AMPL_WIDTH),
conv_std_logic_vector(977,AMPL_WIDTH),
conv_std_logic_vector(977,AMPL_WIDTH),
conv_std_logic_vector(978,AMPL_WIDTH),
conv_std_logic_vector(979,AMPL_WIDTH),
conv_std_logic_vector(979,AMPL_WIDTH),
conv_std_logic_vector(980,AMPL_WIDTH),
conv_std_logic_vector(981,AMPL_WIDTH),
conv_std_logic_vector(982,AMPL_WIDTH),
conv_std_logic_vector(982,AMPL_WIDTH),
conv_std_logic_vector(983,AMPL_WIDTH),
conv_std_logic_vector(984,AMPL_WIDTH),
conv_std_logic_vector(984,AMPL_WIDTH),
conv_std_logic_vector(985,AMPL_WIDTH),
conv_std_logic_vector(986,AMPL_WIDTH),
conv_std_logic_vector(986,AMPL_WIDTH),
conv_std_logic_vector(987,AMPL_WIDTH),
conv_std_logic_vector(988,AMPL_WIDTH),
conv_std_logic_vector(988,AMPL_WIDTH),
conv_std_logic_vector(989,AMPL_WIDTH),
conv_std_logic_vector(990,AMPL_WIDTH),
conv_std_logic_vector(990,AMPL_WIDTH),
conv_std_logic_vector(991,AMPL_WIDTH),
conv_std_logic_vector(992,AMPL_WIDTH),
conv_std_logic_vector(993,AMPL_WIDTH),
conv_std_logic_vector(993,AMPL_WIDTH),
conv_std_logic_vector(994,AMPL_WIDTH),
conv_std_logic_vector(995,AMPL_WIDTH),
conv_std_logic_vector(995,AMPL_WIDTH),
conv_std_logic_vector(996,AMPL_WIDTH),
conv_std_logic_vector(997,AMPL_WIDTH),
conv_std_logic_vector(997,AMPL_WIDTH),
conv_std_logic_vector(998,AMPL_WIDTH),
conv_std_logic_vector(999,AMPL_WIDTH),
conv_std_logic_vector(999,AMPL_WIDTH),
conv_std_logic_vector(1000,AMPL_WIDTH),
conv_std_logic_vector(1001,AMPL_WIDTH),
conv_std_logic_vector(1001,AMPL_WIDTH),
conv_std_logic_vector(1002,AMPL_WIDTH),
conv_std_logic_vector(1003,AMPL_WIDTH),
conv_std_logic_vector(1003,AMPL_WIDTH),
conv_std_logic_vector(1004,AMPL_WIDTH),
conv_std_logic_vector(1005,AMPL_WIDTH),
conv_std_logic_vector(1006,AMPL_WIDTH),
conv_std_logic_vector(1006,AMPL_WIDTH),
conv_std_logic_vector(1007,AMPL_WIDTH),
conv_std_logic_vector(1008,AMPL_WIDTH),
conv_std_logic_vector(1008,AMPL_WIDTH),
conv_std_logic_vector(1009,AMPL_WIDTH),
conv_std_logic_vector(1010,AMPL_WIDTH),
conv_std_logic_vector(1010,AMPL_WIDTH),
conv_std_logic_vector(1011,AMPL_WIDTH),
conv_std_logic_vector(1012,AMPL_WIDTH),
conv_std_logic_vector(1012,AMPL_WIDTH),
conv_std_logic_vector(1013,AMPL_WIDTH),
conv_std_logic_vector(1014,AMPL_WIDTH),
conv_std_logic_vector(1014,AMPL_WIDTH),
conv_std_logic_vector(1015,AMPL_WIDTH),
conv_std_logic_vector(1016,AMPL_WIDTH),
conv_std_logic_vector(1016,AMPL_WIDTH),
conv_std_logic_vector(1017,AMPL_WIDTH),
conv_std_logic_vector(1018,AMPL_WIDTH),
conv_std_logic_vector(1019,AMPL_WIDTH),
conv_std_logic_vector(1019,AMPL_WIDTH),
conv_std_logic_vector(1020,AMPL_WIDTH),
conv_std_logic_vector(1021,AMPL_WIDTH),
conv_std_logic_vector(1021,AMPL_WIDTH),
conv_std_logic_vector(1022,AMPL_WIDTH),
conv_std_logic_vector(1023,AMPL_WIDTH),
conv_std_logic_vector(1023,AMPL_WIDTH),
conv_std_logic_vector(1024,AMPL_WIDTH),
conv_std_logic_vector(1025,AMPL_WIDTH),
conv_std_logic_vector(1025,AMPL_WIDTH),
conv_std_logic_vector(1026,AMPL_WIDTH),
conv_std_logic_vector(1027,AMPL_WIDTH),
conv_std_logic_vector(1027,AMPL_WIDTH),
conv_std_logic_vector(1028,AMPL_WIDTH),
conv_std_logic_vector(1029,AMPL_WIDTH),
conv_std_logic_vector(1029,AMPL_WIDTH),
conv_std_logic_vector(1030,AMPL_WIDTH),
conv_std_logic_vector(1031,AMPL_WIDTH),
conv_std_logic_vector(1031,AMPL_WIDTH),
conv_std_logic_vector(1032,AMPL_WIDTH),
conv_std_logic_vector(1033,AMPL_WIDTH),
conv_std_logic_vector(1033,AMPL_WIDTH),
conv_std_logic_vector(1034,AMPL_WIDTH),
conv_std_logic_vector(1035,AMPL_WIDTH),
conv_std_logic_vector(1035,AMPL_WIDTH),
conv_std_logic_vector(1036,AMPL_WIDTH),
conv_std_logic_vector(1037,AMPL_WIDTH),
conv_std_logic_vector(1038,AMPL_WIDTH),
conv_std_logic_vector(1038,AMPL_WIDTH),
conv_std_logic_vector(1039,AMPL_WIDTH),
conv_std_logic_vector(1040,AMPL_WIDTH),
conv_std_logic_vector(1040,AMPL_WIDTH),
conv_std_logic_vector(1041,AMPL_WIDTH),
conv_std_logic_vector(1042,AMPL_WIDTH),
conv_std_logic_vector(1042,AMPL_WIDTH),
conv_std_logic_vector(1043,AMPL_WIDTH),
conv_std_logic_vector(1044,AMPL_WIDTH),
conv_std_logic_vector(1044,AMPL_WIDTH),
conv_std_logic_vector(1045,AMPL_WIDTH),
conv_std_logic_vector(1046,AMPL_WIDTH),
conv_std_logic_vector(1046,AMPL_WIDTH),
conv_std_logic_vector(1047,AMPL_WIDTH),
conv_std_logic_vector(1048,AMPL_WIDTH),
conv_std_logic_vector(1048,AMPL_WIDTH),
conv_std_logic_vector(1049,AMPL_WIDTH),
conv_std_logic_vector(1050,AMPL_WIDTH),
conv_std_logic_vector(1050,AMPL_WIDTH),
conv_std_logic_vector(1051,AMPL_WIDTH),
conv_std_logic_vector(1052,AMPL_WIDTH),
conv_std_logic_vector(1052,AMPL_WIDTH),
conv_std_logic_vector(1053,AMPL_WIDTH),
conv_std_logic_vector(1054,AMPL_WIDTH),
conv_std_logic_vector(1054,AMPL_WIDTH),
conv_std_logic_vector(1055,AMPL_WIDTH),
conv_std_logic_vector(1056,AMPL_WIDTH),
conv_std_logic_vector(1056,AMPL_WIDTH),
conv_std_logic_vector(1057,AMPL_WIDTH),
conv_std_logic_vector(1058,AMPL_WIDTH),
conv_std_logic_vector(1058,AMPL_WIDTH),
conv_std_logic_vector(1059,AMPL_WIDTH),
conv_std_logic_vector(1060,AMPL_WIDTH),
conv_std_logic_vector(1060,AMPL_WIDTH),
conv_std_logic_vector(1061,AMPL_WIDTH),
conv_std_logic_vector(1062,AMPL_WIDTH),
conv_std_logic_vector(1062,AMPL_WIDTH),
conv_std_logic_vector(1063,AMPL_WIDTH),
conv_std_logic_vector(1064,AMPL_WIDTH),
conv_std_logic_vector(1064,AMPL_WIDTH),
conv_std_logic_vector(1065,AMPL_WIDTH),
conv_std_logic_vector(1066,AMPL_WIDTH),
conv_std_logic_vector(1066,AMPL_WIDTH),
conv_std_logic_vector(1067,AMPL_WIDTH),
conv_std_logic_vector(1068,AMPL_WIDTH),
conv_std_logic_vector(1068,AMPL_WIDTH),
conv_std_logic_vector(1069,AMPL_WIDTH),
conv_std_logic_vector(1070,AMPL_WIDTH),
conv_std_logic_vector(1070,AMPL_WIDTH),
conv_std_logic_vector(1071,AMPL_WIDTH),
conv_std_logic_vector(1072,AMPL_WIDTH),
conv_std_logic_vector(1072,AMPL_WIDTH),
conv_std_logic_vector(1073,AMPL_WIDTH),
conv_std_logic_vector(1074,AMPL_WIDTH),
conv_std_logic_vector(1075,AMPL_WIDTH),
conv_std_logic_vector(1075,AMPL_WIDTH),
conv_std_logic_vector(1076,AMPL_WIDTH),
conv_std_logic_vector(1077,AMPL_WIDTH),
conv_std_logic_vector(1077,AMPL_WIDTH),
conv_std_logic_vector(1078,AMPL_WIDTH),
conv_std_logic_vector(1079,AMPL_WIDTH),
conv_std_logic_vector(1079,AMPL_WIDTH),
conv_std_logic_vector(1080,AMPL_WIDTH),
conv_std_logic_vector(1081,AMPL_WIDTH),
conv_std_logic_vector(1081,AMPL_WIDTH),
conv_std_logic_vector(1082,AMPL_WIDTH),
conv_std_logic_vector(1083,AMPL_WIDTH),
conv_std_logic_vector(1083,AMPL_WIDTH),
conv_std_logic_vector(1084,AMPL_WIDTH),
conv_std_logic_vector(1085,AMPL_WIDTH),
conv_std_logic_vector(1085,AMPL_WIDTH),
conv_std_logic_vector(1086,AMPL_WIDTH),
conv_std_logic_vector(1087,AMPL_WIDTH),
conv_std_logic_vector(1087,AMPL_WIDTH),
conv_std_logic_vector(1088,AMPL_WIDTH),
conv_std_logic_vector(1088,AMPL_WIDTH),
conv_std_logic_vector(1089,AMPL_WIDTH),
conv_std_logic_vector(1090,AMPL_WIDTH),
conv_std_logic_vector(1090,AMPL_WIDTH),
conv_std_logic_vector(1091,AMPL_WIDTH),
conv_std_logic_vector(1092,AMPL_WIDTH),
conv_std_logic_vector(1092,AMPL_WIDTH),
conv_std_logic_vector(1093,AMPL_WIDTH),
conv_std_logic_vector(1094,AMPL_WIDTH),
conv_std_logic_vector(1094,AMPL_WIDTH),
conv_std_logic_vector(1095,AMPL_WIDTH),
conv_std_logic_vector(1096,AMPL_WIDTH),
conv_std_logic_vector(1096,AMPL_WIDTH),
conv_std_logic_vector(1097,AMPL_WIDTH),
conv_std_logic_vector(1098,AMPL_WIDTH),
conv_std_logic_vector(1098,AMPL_WIDTH),
conv_std_logic_vector(1099,AMPL_WIDTH),
conv_std_logic_vector(1100,AMPL_WIDTH),
conv_std_logic_vector(1100,AMPL_WIDTH),
conv_std_logic_vector(1101,AMPL_WIDTH),
conv_std_logic_vector(1102,AMPL_WIDTH),
conv_std_logic_vector(1102,AMPL_WIDTH),
conv_std_logic_vector(1103,AMPL_WIDTH),
conv_std_logic_vector(1104,AMPL_WIDTH),
conv_std_logic_vector(1104,AMPL_WIDTH),
conv_std_logic_vector(1105,AMPL_WIDTH),
conv_std_logic_vector(1106,AMPL_WIDTH),
conv_std_logic_vector(1106,AMPL_WIDTH),
conv_std_logic_vector(1107,AMPL_WIDTH),
conv_std_logic_vector(1108,AMPL_WIDTH),
conv_std_logic_vector(1108,AMPL_WIDTH),
conv_std_logic_vector(1109,AMPL_WIDTH),
conv_std_logic_vector(1110,AMPL_WIDTH),
conv_std_logic_vector(1110,AMPL_WIDTH),
conv_std_logic_vector(1111,AMPL_WIDTH),
conv_std_logic_vector(1112,AMPL_WIDTH),
conv_std_logic_vector(1112,AMPL_WIDTH),
conv_std_logic_vector(1113,AMPL_WIDTH),
conv_std_logic_vector(1114,AMPL_WIDTH),
conv_std_logic_vector(1114,AMPL_WIDTH),
conv_std_logic_vector(1115,AMPL_WIDTH),
conv_std_logic_vector(1116,AMPL_WIDTH),
conv_std_logic_vector(1116,AMPL_WIDTH),
conv_std_logic_vector(1117,AMPL_WIDTH),
conv_std_logic_vector(1118,AMPL_WIDTH),
conv_std_logic_vector(1118,AMPL_WIDTH),
conv_std_logic_vector(1119,AMPL_WIDTH),
conv_std_logic_vector(1120,AMPL_WIDTH),
conv_std_logic_vector(1120,AMPL_WIDTH),
conv_std_logic_vector(1121,AMPL_WIDTH),
conv_std_logic_vector(1122,AMPL_WIDTH),
conv_std_logic_vector(1122,AMPL_WIDTH),
conv_std_logic_vector(1123,AMPL_WIDTH),
conv_std_logic_vector(1124,AMPL_WIDTH),
conv_std_logic_vector(1124,AMPL_WIDTH),
conv_std_logic_vector(1125,AMPL_WIDTH),
conv_std_logic_vector(1125,AMPL_WIDTH),
conv_std_logic_vector(1126,AMPL_WIDTH),
conv_std_logic_vector(1127,AMPL_WIDTH),
conv_std_logic_vector(1127,AMPL_WIDTH),
conv_std_logic_vector(1128,AMPL_WIDTH),
conv_std_logic_vector(1129,AMPL_WIDTH),
conv_std_logic_vector(1129,AMPL_WIDTH),
conv_std_logic_vector(1130,AMPL_WIDTH),
conv_std_logic_vector(1131,AMPL_WIDTH),
conv_std_logic_vector(1131,AMPL_WIDTH),
conv_std_logic_vector(1132,AMPL_WIDTH),
conv_std_logic_vector(1133,AMPL_WIDTH),
conv_std_logic_vector(1133,AMPL_WIDTH),
conv_std_logic_vector(1134,AMPL_WIDTH),
conv_std_logic_vector(1135,AMPL_WIDTH),
conv_std_logic_vector(1135,AMPL_WIDTH),
conv_std_logic_vector(1136,AMPL_WIDTH),
conv_std_logic_vector(1137,AMPL_WIDTH),
conv_std_logic_vector(1137,AMPL_WIDTH),
conv_std_logic_vector(1138,AMPL_WIDTH),
conv_std_logic_vector(1139,AMPL_WIDTH),
conv_std_logic_vector(1139,AMPL_WIDTH),
conv_std_logic_vector(1140,AMPL_WIDTH),
conv_std_logic_vector(1141,AMPL_WIDTH),
conv_std_logic_vector(1141,AMPL_WIDTH),
conv_std_logic_vector(1142,AMPL_WIDTH),
conv_std_logic_vector(1142,AMPL_WIDTH),
conv_std_logic_vector(1143,AMPL_WIDTH),
conv_std_logic_vector(1144,AMPL_WIDTH),
conv_std_logic_vector(1144,AMPL_WIDTH),
conv_std_logic_vector(1145,AMPL_WIDTH),
conv_std_logic_vector(1146,AMPL_WIDTH),
conv_std_logic_vector(1146,AMPL_WIDTH),
conv_std_logic_vector(1147,AMPL_WIDTH),
conv_std_logic_vector(1148,AMPL_WIDTH),
conv_std_logic_vector(1148,AMPL_WIDTH),
conv_std_logic_vector(1149,AMPL_WIDTH),
conv_std_logic_vector(1150,AMPL_WIDTH),
conv_std_logic_vector(1150,AMPL_WIDTH),
conv_std_logic_vector(1151,AMPL_WIDTH),
conv_std_logic_vector(1152,AMPL_WIDTH),
conv_std_logic_vector(1152,AMPL_WIDTH),
conv_std_logic_vector(1153,AMPL_WIDTH),
conv_std_logic_vector(1154,AMPL_WIDTH),
conv_std_logic_vector(1154,AMPL_WIDTH),
conv_std_logic_vector(1155,AMPL_WIDTH),
conv_std_logic_vector(1155,AMPL_WIDTH),
conv_std_logic_vector(1156,AMPL_WIDTH),
conv_std_logic_vector(1157,AMPL_WIDTH),
conv_std_logic_vector(1157,AMPL_WIDTH),
conv_std_logic_vector(1158,AMPL_WIDTH),
conv_std_logic_vector(1159,AMPL_WIDTH),
conv_std_logic_vector(1159,AMPL_WIDTH),
conv_std_logic_vector(1160,AMPL_WIDTH),
conv_std_logic_vector(1161,AMPL_WIDTH),
conv_std_logic_vector(1161,AMPL_WIDTH),
conv_std_logic_vector(1162,AMPL_WIDTH),
conv_std_logic_vector(1163,AMPL_WIDTH),
conv_std_logic_vector(1163,AMPL_WIDTH),
conv_std_logic_vector(1164,AMPL_WIDTH),
conv_std_logic_vector(1165,AMPL_WIDTH),
conv_std_logic_vector(1165,AMPL_WIDTH),
conv_std_logic_vector(1166,AMPL_WIDTH),
conv_std_logic_vector(1166,AMPL_WIDTH),
conv_std_logic_vector(1167,AMPL_WIDTH),
conv_std_logic_vector(1168,AMPL_WIDTH),
conv_std_logic_vector(1168,AMPL_WIDTH),
conv_std_logic_vector(1169,AMPL_WIDTH),
conv_std_logic_vector(1170,AMPL_WIDTH),
conv_std_logic_vector(1170,AMPL_WIDTH),
conv_std_logic_vector(1171,AMPL_WIDTH),
conv_std_logic_vector(1172,AMPL_WIDTH),
conv_std_logic_vector(1172,AMPL_WIDTH),
conv_std_logic_vector(1173,AMPL_WIDTH),
conv_std_logic_vector(1174,AMPL_WIDTH),
conv_std_logic_vector(1174,AMPL_WIDTH),
conv_std_logic_vector(1175,AMPL_WIDTH),
conv_std_logic_vector(1175,AMPL_WIDTH),
conv_std_logic_vector(1176,AMPL_WIDTH),
conv_std_logic_vector(1177,AMPL_WIDTH),
conv_std_logic_vector(1177,AMPL_WIDTH),
conv_std_logic_vector(1178,AMPL_WIDTH),
conv_std_logic_vector(1179,AMPL_WIDTH),
conv_std_logic_vector(1179,AMPL_WIDTH),
conv_std_logic_vector(1180,AMPL_WIDTH),
conv_std_logic_vector(1181,AMPL_WIDTH),
conv_std_logic_vector(1181,AMPL_WIDTH),
conv_std_logic_vector(1182,AMPL_WIDTH),
conv_std_logic_vector(1183,AMPL_WIDTH),
conv_std_logic_vector(1183,AMPL_WIDTH),
conv_std_logic_vector(1184,AMPL_WIDTH),
conv_std_logic_vector(1184,AMPL_WIDTH),
conv_std_logic_vector(1185,AMPL_WIDTH),
conv_std_logic_vector(1186,AMPL_WIDTH),
conv_std_logic_vector(1186,AMPL_WIDTH),
conv_std_logic_vector(1187,AMPL_WIDTH),
conv_std_logic_vector(1188,AMPL_WIDTH),
conv_std_logic_vector(1188,AMPL_WIDTH),
conv_std_logic_vector(1189,AMPL_WIDTH),
conv_std_logic_vector(1190,AMPL_WIDTH),
conv_std_logic_vector(1190,AMPL_WIDTH),
conv_std_logic_vector(1191,AMPL_WIDTH),
conv_std_logic_vector(1191,AMPL_WIDTH),
conv_std_logic_vector(1192,AMPL_WIDTH),
conv_std_logic_vector(1193,AMPL_WIDTH),
conv_std_logic_vector(1193,AMPL_WIDTH),
conv_std_logic_vector(1194,AMPL_WIDTH),
conv_std_logic_vector(1195,AMPL_WIDTH),
conv_std_logic_vector(1195,AMPL_WIDTH),
conv_std_logic_vector(1196,AMPL_WIDTH),
conv_std_logic_vector(1197,AMPL_WIDTH),
conv_std_logic_vector(1197,AMPL_WIDTH),
conv_std_logic_vector(1198,AMPL_WIDTH),
conv_std_logic_vector(1198,AMPL_WIDTH),
conv_std_logic_vector(1199,AMPL_WIDTH),
conv_std_logic_vector(1200,AMPL_WIDTH),
conv_std_logic_vector(1200,AMPL_WIDTH),
conv_std_logic_vector(1201,AMPL_WIDTH),
conv_std_logic_vector(1202,AMPL_WIDTH),
conv_std_logic_vector(1202,AMPL_WIDTH),
conv_std_logic_vector(1203,AMPL_WIDTH),
conv_std_logic_vector(1204,AMPL_WIDTH),
conv_std_logic_vector(1204,AMPL_WIDTH),
conv_std_logic_vector(1205,AMPL_WIDTH),
conv_std_logic_vector(1205,AMPL_WIDTH),
conv_std_logic_vector(1206,AMPL_WIDTH),
conv_std_logic_vector(1207,AMPL_WIDTH),
conv_std_logic_vector(1207,AMPL_WIDTH),
conv_std_logic_vector(1208,AMPL_WIDTH),
conv_std_logic_vector(1209,AMPL_WIDTH),
conv_std_logic_vector(1209,AMPL_WIDTH),
conv_std_logic_vector(1210,AMPL_WIDTH),
conv_std_logic_vector(1211,AMPL_WIDTH),
conv_std_logic_vector(1211,AMPL_WIDTH),
conv_std_logic_vector(1212,AMPL_WIDTH),
conv_std_logic_vector(1212,AMPL_WIDTH),
conv_std_logic_vector(1213,AMPL_WIDTH),
conv_std_logic_vector(1214,AMPL_WIDTH),
conv_std_logic_vector(1214,AMPL_WIDTH),
conv_std_logic_vector(1215,AMPL_WIDTH),
conv_std_logic_vector(1216,AMPL_WIDTH),
conv_std_logic_vector(1216,AMPL_WIDTH),
conv_std_logic_vector(1217,AMPL_WIDTH),
conv_std_logic_vector(1218,AMPL_WIDTH),
conv_std_logic_vector(1218,AMPL_WIDTH),
conv_std_logic_vector(1219,AMPL_WIDTH),
conv_std_logic_vector(1219,AMPL_WIDTH),
conv_std_logic_vector(1220,AMPL_WIDTH),
conv_std_logic_vector(1221,AMPL_WIDTH),
conv_std_logic_vector(1221,AMPL_WIDTH),
conv_std_logic_vector(1222,AMPL_WIDTH),
conv_std_logic_vector(1223,AMPL_WIDTH),
conv_std_logic_vector(1223,AMPL_WIDTH),
conv_std_logic_vector(1224,AMPL_WIDTH),
conv_std_logic_vector(1224,AMPL_WIDTH),
conv_std_logic_vector(1225,AMPL_WIDTH),
conv_std_logic_vector(1226,AMPL_WIDTH),
conv_std_logic_vector(1226,AMPL_WIDTH),
conv_std_logic_vector(1227,AMPL_WIDTH),
conv_std_logic_vector(1228,AMPL_WIDTH),
conv_std_logic_vector(1228,AMPL_WIDTH),
conv_std_logic_vector(1229,AMPL_WIDTH),
conv_std_logic_vector(1229,AMPL_WIDTH),
conv_std_logic_vector(1230,AMPL_WIDTH),
conv_std_logic_vector(1231,AMPL_WIDTH),
conv_std_logic_vector(1231,AMPL_WIDTH),
conv_std_logic_vector(1232,AMPL_WIDTH),
conv_std_logic_vector(1233,AMPL_WIDTH),
conv_std_logic_vector(1233,AMPL_WIDTH),
conv_std_logic_vector(1234,AMPL_WIDTH),
conv_std_logic_vector(1234,AMPL_WIDTH),
conv_std_logic_vector(1235,AMPL_WIDTH),
conv_std_logic_vector(1236,AMPL_WIDTH),
conv_std_logic_vector(1236,AMPL_WIDTH),
conv_std_logic_vector(1237,AMPL_WIDTH),
conv_std_logic_vector(1238,AMPL_WIDTH),
conv_std_logic_vector(1238,AMPL_WIDTH),
conv_std_logic_vector(1239,AMPL_WIDTH),
conv_std_logic_vector(1239,AMPL_WIDTH),
conv_std_logic_vector(1240,AMPL_WIDTH),
conv_std_logic_vector(1241,AMPL_WIDTH),
conv_std_logic_vector(1241,AMPL_WIDTH),
conv_std_logic_vector(1242,AMPL_WIDTH),
conv_std_logic_vector(1243,AMPL_WIDTH),
conv_std_logic_vector(1243,AMPL_WIDTH),
conv_std_logic_vector(1244,AMPL_WIDTH),
conv_std_logic_vector(1244,AMPL_WIDTH),
conv_std_logic_vector(1245,AMPL_WIDTH),
conv_std_logic_vector(1246,AMPL_WIDTH),
conv_std_logic_vector(1246,AMPL_WIDTH),
conv_std_logic_vector(1247,AMPL_WIDTH),
conv_std_logic_vector(1248,AMPL_WIDTH),
conv_std_logic_vector(1248,AMPL_WIDTH),
conv_std_logic_vector(1249,AMPL_WIDTH),
conv_std_logic_vector(1249,AMPL_WIDTH),
conv_std_logic_vector(1250,AMPL_WIDTH),
conv_std_logic_vector(1251,AMPL_WIDTH),
conv_std_logic_vector(1251,AMPL_WIDTH),
conv_std_logic_vector(1252,AMPL_WIDTH),
conv_std_logic_vector(1253,AMPL_WIDTH),
conv_std_logic_vector(1253,AMPL_WIDTH),
conv_std_logic_vector(1254,AMPL_WIDTH),
conv_std_logic_vector(1254,AMPL_WIDTH),
conv_std_logic_vector(1255,AMPL_WIDTH),
conv_std_logic_vector(1256,AMPL_WIDTH),
conv_std_logic_vector(1256,AMPL_WIDTH),
conv_std_logic_vector(1257,AMPL_WIDTH),
conv_std_logic_vector(1258,AMPL_WIDTH),
conv_std_logic_vector(1258,AMPL_WIDTH),
conv_std_logic_vector(1259,AMPL_WIDTH),
conv_std_logic_vector(1259,AMPL_WIDTH),
conv_std_logic_vector(1260,AMPL_WIDTH),
conv_std_logic_vector(1261,AMPL_WIDTH),
conv_std_logic_vector(1261,AMPL_WIDTH),
conv_std_logic_vector(1262,AMPL_WIDTH),
conv_std_logic_vector(1262,AMPL_WIDTH),
conv_std_logic_vector(1263,AMPL_WIDTH),
conv_std_logic_vector(1264,AMPL_WIDTH),
conv_std_logic_vector(1264,AMPL_WIDTH),
conv_std_logic_vector(1265,AMPL_WIDTH),
conv_std_logic_vector(1266,AMPL_WIDTH),
conv_std_logic_vector(1266,AMPL_WIDTH),
conv_std_logic_vector(1267,AMPL_WIDTH),
conv_std_logic_vector(1267,AMPL_WIDTH),
conv_std_logic_vector(1268,AMPL_WIDTH),
conv_std_logic_vector(1269,AMPL_WIDTH),
conv_std_logic_vector(1269,AMPL_WIDTH),
conv_std_logic_vector(1270,AMPL_WIDTH),
conv_std_logic_vector(1270,AMPL_WIDTH),
conv_std_logic_vector(1271,AMPL_WIDTH),
conv_std_logic_vector(1272,AMPL_WIDTH),
conv_std_logic_vector(1272,AMPL_WIDTH),
conv_std_logic_vector(1273,AMPL_WIDTH),
conv_std_logic_vector(1274,AMPL_WIDTH),
conv_std_logic_vector(1274,AMPL_WIDTH),
conv_std_logic_vector(1275,AMPL_WIDTH),
conv_std_logic_vector(1275,AMPL_WIDTH),
conv_std_logic_vector(1276,AMPL_WIDTH),
conv_std_logic_vector(1277,AMPL_WIDTH),
conv_std_logic_vector(1277,AMPL_WIDTH),
conv_std_logic_vector(1278,AMPL_WIDTH),
conv_std_logic_vector(1278,AMPL_WIDTH),
conv_std_logic_vector(1279,AMPL_WIDTH),
conv_std_logic_vector(1280,AMPL_WIDTH),
conv_std_logic_vector(1280,AMPL_WIDTH),
conv_std_logic_vector(1281,AMPL_WIDTH),
conv_std_logic_vector(1282,AMPL_WIDTH),
conv_std_logic_vector(1282,AMPL_WIDTH),
conv_std_logic_vector(1283,AMPL_WIDTH),
conv_std_logic_vector(1283,AMPL_WIDTH),
conv_std_logic_vector(1284,AMPL_WIDTH),
conv_std_logic_vector(1285,AMPL_WIDTH),
conv_std_logic_vector(1285,AMPL_WIDTH),
conv_std_logic_vector(1286,AMPL_WIDTH),
conv_std_logic_vector(1286,AMPL_WIDTH),
conv_std_logic_vector(1287,AMPL_WIDTH),
conv_std_logic_vector(1288,AMPL_WIDTH),
conv_std_logic_vector(1288,AMPL_WIDTH),
conv_std_logic_vector(1289,AMPL_WIDTH),
conv_std_logic_vector(1289,AMPL_WIDTH),
conv_std_logic_vector(1290,AMPL_WIDTH),
conv_std_logic_vector(1291,AMPL_WIDTH),
conv_std_logic_vector(1291,AMPL_WIDTH),
conv_std_logic_vector(1292,AMPL_WIDTH),
conv_std_logic_vector(1293,AMPL_WIDTH),
conv_std_logic_vector(1293,AMPL_WIDTH),
conv_std_logic_vector(1294,AMPL_WIDTH),
conv_std_logic_vector(1294,AMPL_WIDTH),
conv_std_logic_vector(1295,AMPL_WIDTH),
conv_std_logic_vector(1296,AMPL_WIDTH),
conv_std_logic_vector(1296,AMPL_WIDTH),
conv_std_logic_vector(1297,AMPL_WIDTH),
conv_std_logic_vector(1297,AMPL_WIDTH),
conv_std_logic_vector(1298,AMPL_WIDTH),
conv_std_logic_vector(1299,AMPL_WIDTH),
conv_std_logic_vector(1299,AMPL_WIDTH),
conv_std_logic_vector(1300,AMPL_WIDTH),
conv_std_logic_vector(1300,AMPL_WIDTH),
conv_std_logic_vector(1301,AMPL_WIDTH),
conv_std_logic_vector(1302,AMPL_WIDTH),
conv_std_logic_vector(1302,AMPL_WIDTH),
conv_std_logic_vector(1303,AMPL_WIDTH),
conv_std_logic_vector(1303,AMPL_WIDTH),
conv_std_logic_vector(1304,AMPL_WIDTH),
conv_std_logic_vector(1305,AMPL_WIDTH),
conv_std_logic_vector(1305,AMPL_WIDTH),
conv_std_logic_vector(1306,AMPL_WIDTH),
conv_std_logic_vector(1306,AMPL_WIDTH),
conv_std_logic_vector(1307,AMPL_WIDTH),
conv_std_logic_vector(1308,AMPL_WIDTH),
conv_std_logic_vector(1308,AMPL_WIDTH),
conv_std_logic_vector(1309,AMPL_WIDTH),
conv_std_logic_vector(1309,AMPL_WIDTH),
conv_std_logic_vector(1310,AMPL_WIDTH),
conv_std_logic_vector(1311,AMPL_WIDTH),
conv_std_logic_vector(1311,AMPL_WIDTH),
conv_std_logic_vector(1312,AMPL_WIDTH),
conv_std_logic_vector(1313,AMPL_WIDTH),
conv_std_logic_vector(1313,AMPL_WIDTH),
conv_std_logic_vector(1314,AMPL_WIDTH),
conv_std_logic_vector(1314,AMPL_WIDTH),
conv_std_logic_vector(1315,AMPL_WIDTH),
conv_std_logic_vector(1316,AMPL_WIDTH),
conv_std_logic_vector(1316,AMPL_WIDTH),
conv_std_logic_vector(1317,AMPL_WIDTH),
conv_std_logic_vector(1317,AMPL_WIDTH),
conv_std_logic_vector(1318,AMPL_WIDTH),
conv_std_logic_vector(1319,AMPL_WIDTH),
conv_std_logic_vector(1319,AMPL_WIDTH),
conv_std_logic_vector(1320,AMPL_WIDTH),
conv_std_logic_vector(1320,AMPL_WIDTH),
conv_std_logic_vector(1321,AMPL_WIDTH),
conv_std_logic_vector(1322,AMPL_WIDTH),
conv_std_logic_vector(1322,AMPL_WIDTH),
conv_std_logic_vector(1323,AMPL_WIDTH),
conv_std_logic_vector(1323,AMPL_WIDTH),
conv_std_logic_vector(1324,AMPL_WIDTH),
conv_std_logic_vector(1325,AMPL_WIDTH),
conv_std_logic_vector(1325,AMPL_WIDTH),
conv_std_logic_vector(1326,AMPL_WIDTH),
conv_std_logic_vector(1326,AMPL_WIDTH),
conv_std_logic_vector(1327,AMPL_WIDTH),
conv_std_logic_vector(1328,AMPL_WIDTH),
conv_std_logic_vector(1328,AMPL_WIDTH),
conv_std_logic_vector(1329,AMPL_WIDTH),
conv_std_logic_vector(1329,AMPL_WIDTH),
conv_std_logic_vector(1330,AMPL_WIDTH),
conv_std_logic_vector(1330,AMPL_WIDTH),
conv_std_logic_vector(1331,AMPL_WIDTH),
conv_std_logic_vector(1332,AMPL_WIDTH),
conv_std_logic_vector(1332,AMPL_WIDTH),
conv_std_logic_vector(1333,AMPL_WIDTH),
conv_std_logic_vector(1333,AMPL_WIDTH),
conv_std_logic_vector(1334,AMPL_WIDTH),
conv_std_logic_vector(1335,AMPL_WIDTH),
conv_std_logic_vector(1335,AMPL_WIDTH),
conv_std_logic_vector(1336,AMPL_WIDTH),
conv_std_logic_vector(1336,AMPL_WIDTH),
conv_std_logic_vector(1337,AMPL_WIDTH),
conv_std_logic_vector(1338,AMPL_WIDTH),
conv_std_logic_vector(1338,AMPL_WIDTH),
conv_std_logic_vector(1339,AMPL_WIDTH),
conv_std_logic_vector(1339,AMPL_WIDTH),
conv_std_logic_vector(1340,AMPL_WIDTH),
conv_std_logic_vector(1341,AMPL_WIDTH),
conv_std_logic_vector(1341,AMPL_WIDTH),
conv_std_logic_vector(1342,AMPL_WIDTH),
conv_std_logic_vector(1342,AMPL_WIDTH),
conv_std_logic_vector(1343,AMPL_WIDTH),
conv_std_logic_vector(1344,AMPL_WIDTH),
conv_std_logic_vector(1344,AMPL_WIDTH),
conv_std_logic_vector(1345,AMPL_WIDTH),
conv_std_logic_vector(1345,AMPL_WIDTH),
conv_std_logic_vector(1346,AMPL_WIDTH),
conv_std_logic_vector(1347,AMPL_WIDTH),
conv_std_logic_vector(1347,AMPL_WIDTH),
conv_std_logic_vector(1348,AMPL_WIDTH),
conv_std_logic_vector(1348,AMPL_WIDTH),
conv_std_logic_vector(1349,AMPL_WIDTH),
conv_std_logic_vector(1349,AMPL_WIDTH),
conv_std_logic_vector(1350,AMPL_WIDTH),
conv_std_logic_vector(1351,AMPL_WIDTH),
conv_std_logic_vector(1351,AMPL_WIDTH),
conv_std_logic_vector(1352,AMPL_WIDTH),
conv_std_logic_vector(1352,AMPL_WIDTH),
conv_std_logic_vector(1353,AMPL_WIDTH),
conv_std_logic_vector(1354,AMPL_WIDTH),
conv_std_logic_vector(1354,AMPL_WIDTH),
conv_std_logic_vector(1355,AMPL_WIDTH),
conv_std_logic_vector(1355,AMPL_WIDTH),
conv_std_logic_vector(1356,AMPL_WIDTH),
conv_std_logic_vector(1357,AMPL_WIDTH),
conv_std_logic_vector(1357,AMPL_WIDTH),
conv_std_logic_vector(1358,AMPL_WIDTH),
conv_std_logic_vector(1358,AMPL_WIDTH),
conv_std_logic_vector(1359,AMPL_WIDTH),
conv_std_logic_vector(1359,AMPL_WIDTH),
conv_std_logic_vector(1360,AMPL_WIDTH),
conv_std_logic_vector(1361,AMPL_WIDTH),
conv_std_logic_vector(1361,AMPL_WIDTH),
conv_std_logic_vector(1362,AMPL_WIDTH),
conv_std_logic_vector(1362,AMPL_WIDTH),
conv_std_logic_vector(1363,AMPL_WIDTH),
conv_std_logic_vector(1364,AMPL_WIDTH),
conv_std_logic_vector(1364,AMPL_WIDTH),
conv_std_logic_vector(1365,AMPL_WIDTH),
conv_std_logic_vector(1365,AMPL_WIDTH),
conv_std_logic_vector(1366,AMPL_WIDTH),
conv_std_logic_vector(1367,AMPL_WIDTH),
conv_std_logic_vector(1367,AMPL_WIDTH),
conv_std_logic_vector(1368,AMPL_WIDTH),
conv_std_logic_vector(1368,AMPL_WIDTH),
conv_std_logic_vector(1369,AMPL_WIDTH),
conv_std_logic_vector(1369,AMPL_WIDTH),
conv_std_logic_vector(1370,AMPL_WIDTH),
conv_std_logic_vector(1371,AMPL_WIDTH),
conv_std_logic_vector(1371,AMPL_WIDTH),
conv_std_logic_vector(1372,AMPL_WIDTH),
conv_std_logic_vector(1372,AMPL_WIDTH),
conv_std_logic_vector(1373,AMPL_WIDTH),
conv_std_logic_vector(1374,AMPL_WIDTH),
conv_std_logic_vector(1374,AMPL_WIDTH),
conv_std_logic_vector(1375,AMPL_WIDTH),
conv_std_logic_vector(1375,AMPL_WIDTH),
conv_std_logic_vector(1376,AMPL_WIDTH),
conv_std_logic_vector(1376,AMPL_WIDTH),
conv_std_logic_vector(1377,AMPL_WIDTH),
conv_std_logic_vector(1378,AMPL_WIDTH),
conv_std_logic_vector(1378,AMPL_WIDTH),
conv_std_logic_vector(1379,AMPL_WIDTH),
conv_std_logic_vector(1379,AMPL_WIDTH),
conv_std_logic_vector(1380,AMPL_WIDTH),
conv_std_logic_vector(1380,AMPL_WIDTH),
conv_std_logic_vector(1381,AMPL_WIDTH),
conv_std_logic_vector(1382,AMPL_WIDTH),
conv_std_logic_vector(1382,AMPL_WIDTH),
conv_std_logic_vector(1383,AMPL_WIDTH),
conv_std_logic_vector(1383,AMPL_WIDTH),
conv_std_logic_vector(1384,AMPL_WIDTH),
conv_std_logic_vector(1385,AMPL_WIDTH),
conv_std_logic_vector(1385,AMPL_WIDTH),
conv_std_logic_vector(1386,AMPL_WIDTH),
conv_std_logic_vector(1386,AMPL_WIDTH),
conv_std_logic_vector(1387,AMPL_WIDTH),
conv_std_logic_vector(1387,AMPL_WIDTH),
conv_std_logic_vector(1388,AMPL_WIDTH),
conv_std_logic_vector(1389,AMPL_WIDTH),
conv_std_logic_vector(1389,AMPL_WIDTH),
conv_std_logic_vector(1390,AMPL_WIDTH),
conv_std_logic_vector(1390,AMPL_WIDTH),
conv_std_logic_vector(1391,AMPL_WIDTH),
conv_std_logic_vector(1391,AMPL_WIDTH),
conv_std_logic_vector(1392,AMPL_WIDTH),
conv_std_logic_vector(1393,AMPL_WIDTH),
conv_std_logic_vector(1393,AMPL_WIDTH),
conv_std_logic_vector(1394,AMPL_WIDTH),
conv_std_logic_vector(1394,AMPL_WIDTH),
conv_std_logic_vector(1395,AMPL_WIDTH),
conv_std_logic_vector(1395,AMPL_WIDTH),
conv_std_logic_vector(1396,AMPL_WIDTH),
conv_std_logic_vector(1397,AMPL_WIDTH),
conv_std_logic_vector(1397,AMPL_WIDTH),
conv_std_logic_vector(1398,AMPL_WIDTH),
conv_std_logic_vector(1398,AMPL_WIDTH),
conv_std_logic_vector(1399,AMPL_WIDTH),
conv_std_logic_vector(1400,AMPL_WIDTH),
conv_std_logic_vector(1400,AMPL_WIDTH),
conv_std_logic_vector(1401,AMPL_WIDTH),
conv_std_logic_vector(1401,AMPL_WIDTH),
conv_std_logic_vector(1402,AMPL_WIDTH),
conv_std_logic_vector(1402,AMPL_WIDTH),
conv_std_logic_vector(1403,AMPL_WIDTH),
conv_std_logic_vector(1404,AMPL_WIDTH),
conv_std_logic_vector(1404,AMPL_WIDTH),
conv_std_logic_vector(1405,AMPL_WIDTH),
conv_std_logic_vector(1405,AMPL_WIDTH),
conv_std_logic_vector(1406,AMPL_WIDTH),
conv_std_logic_vector(1406,AMPL_WIDTH),
conv_std_logic_vector(1407,AMPL_WIDTH),
conv_std_logic_vector(1408,AMPL_WIDTH),
conv_std_logic_vector(1408,AMPL_WIDTH),
conv_std_logic_vector(1409,AMPL_WIDTH),
conv_std_logic_vector(1409,AMPL_WIDTH),
conv_std_logic_vector(1410,AMPL_WIDTH),
conv_std_logic_vector(1410,AMPL_WIDTH),
conv_std_logic_vector(1411,AMPL_WIDTH),
conv_std_logic_vector(1411,AMPL_WIDTH),
conv_std_logic_vector(1412,AMPL_WIDTH),
conv_std_logic_vector(1413,AMPL_WIDTH),
conv_std_logic_vector(1413,AMPL_WIDTH),
conv_std_logic_vector(1414,AMPL_WIDTH),
conv_std_logic_vector(1414,AMPL_WIDTH),
conv_std_logic_vector(1415,AMPL_WIDTH),
conv_std_logic_vector(1415,AMPL_WIDTH),
conv_std_logic_vector(1416,AMPL_WIDTH),
conv_std_logic_vector(1417,AMPL_WIDTH),
conv_std_logic_vector(1417,AMPL_WIDTH),
conv_std_logic_vector(1418,AMPL_WIDTH),
conv_std_logic_vector(1418,AMPL_WIDTH),
conv_std_logic_vector(1419,AMPL_WIDTH),
conv_std_logic_vector(1419,AMPL_WIDTH),
conv_std_logic_vector(1420,AMPL_WIDTH),
conv_std_logic_vector(1421,AMPL_WIDTH),
conv_std_logic_vector(1421,AMPL_WIDTH),
conv_std_logic_vector(1422,AMPL_WIDTH),
conv_std_logic_vector(1422,AMPL_WIDTH),
conv_std_logic_vector(1423,AMPL_WIDTH),
conv_std_logic_vector(1423,AMPL_WIDTH),
conv_std_logic_vector(1424,AMPL_WIDTH),
conv_std_logic_vector(1425,AMPL_WIDTH),
conv_std_logic_vector(1425,AMPL_WIDTH),
conv_std_logic_vector(1426,AMPL_WIDTH),
conv_std_logic_vector(1426,AMPL_WIDTH),
conv_std_logic_vector(1427,AMPL_WIDTH),
conv_std_logic_vector(1427,AMPL_WIDTH),
conv_std_logic_vector(1428,AMPL_WIDTH),
conv_std_logic_vector(1428,AMPL_WIDTH),
conv_std_logic_vector(1429,AMPL_WIDTH),
conv_std_logic_vector(1430,AMPL_WIDTH),
conv_std_logic_vector(1430,AMPL_WIDTH),
conv_std_logic_vector(1431,AMPL_WIDTH),
conv_std_logic_vector(1431,AMPL_WIDTH),
conv_std_logic_vector(1432,AMPL_WIDTH),
conv_std_logic_vector(1432,AMPL_WIDTH),
conv_std_logic_vector(1433,AMPL_WIDTH),
conv_std_logic_vector(1434,AMPL_WIDTH),
conv_std_logic_vector(1434,AMPL_WIDTH),
conv_std_logic_vector(1435,AMPL_WIDTH),
conv_std_logic_vector(1435,AMPL_WIDTH),
conv_std_logic_vector(1436,AMPL_WIDTH),
conv_std_logic_vector(1436,AMPL_WIDTH),
conv_std_logic_vector(1437,AMPL_WIDTH),
conv_std_logic_vector(1437,AMPL_WIDTH),
conv_std_logic_vector(1438,AMPL_WIDTH),
conv_std_logic_vector(1439,AMPL_WIDTH),
conv_std_logic_vector(1439,AMPL_WIDTH),
conv_std_logic_vector(1440,AMPL_WIDTH),
conv_std_logic_vector(1440,AMPL_WIDTH),
conv_std_logic_vector(1441,AMPL_WIDTH),
conv_std_logic_vector(1441,AMPL_WIDTH),
conv_std_logic_vector(1442,AMPL_WIDTH),
conv_std_logic_vector(1442,AMPL_WIDTH),
conv_std_logic_vector(1443,AMPL_WIDTH),
conv_std_logic_vector(1444,AMPL_WIDTH),
conv_std_logic_vector(1444,AMPL_WIDTH),
conv_std_logic_vector(1445,AMPL_WIDTH),
conv_std_logic_vector(1445,AMPL_WIDTH),
conv_std_logic_vector(1446,AMPL_WIDTH),
conv_std_logic_vector(1446,AMPL_WIDTH),
conv_std_logic_vector(1447,AMPL_WIDTH),
conv_std_logic_vector(1447,AMPL_WIDTH),
conv_std_logic_vector(1448,AMPL_WIDTH),
conv_std_logic_vector(1449,AMPL_WIDTH),
conv_std_logic_vector(1449,AMPL_WIDTH),
conv_std_logic_vector(1450,AMPL_WIDTH),
conv_std_logic_vector(1450,AMPL_WIDTH),
conv_std_logic_vector(1451,AMPL_WIDTH),
conv_std_logic_vector(1451,AMPL_WIDTH),
conv_std_logic_vector(1452,AMPL_WIDTH),
conv_std_logic_vector(1452,AMPL_WIDTH),
conv_std_logic_vector(1453,AMPL_WIDTH),
conv_std_logic_vector(1454,AMPL_WIDTH),
conv_std_logic_vector(1454,AMPL_WIDTH),
conv_std_logic_vector(1455,AMPL_WIDTH),
conv_std_logic_vector(1455,AMPL_WIDTH),
conv_std_logic_vector(1456,AMPL_WIDTH),
conv_std_logic_vector(1456,AMPL_WIDTH),
conv_std_logic_vector(1457,AMPL_WIDTH),
conv_std_logic_vector(1457,AMPL_WIDTH),
conv_std_logic_vector(1458,AMPL_WIDTH),
conv_std_logic_vector(1459,AMPL_WIDTH),
conv_std_logic_vector(1459,AMPL_WIDTH),
conv_std_logic_vector(1460,AMPL_WIDTH),
conv_std_logic_vector(1460,AMPL_WIDTH),
conv_std_logic_vector(1461,AMPL_WIDTH),
conv_std_logic_vector(1461,AMPL_WIDTH),
conv_std_logic_vector(1462,AMPL_WIDTH),
conv_std_logic_vector(1462,AMPL_WIDTH),
conv_std_logic_vector(1463,AMPL_WIDTH),
conv_std_logic_vector(1463,AMPL_WIDTH),
conv_std_logic_vector(1464,AMPL_WIDTH),
conv_std_logic_vector(1465,AMPL_WIDTH),
conv_std_logic_vector(1465,AMPL_WIDTH),
conv_std_logic_vector(1466,AMPL_WIDTH),
conv_std_logic_vector(1466,AMPL_WIDTH),
conv_std_logic_vector(1467,AMPL_WIDTH),
conv_std_logic_vector(1467,AMPL_WIDTH),
conv_std_logic_vector(1468,AMPL_WIDTH),
conv_std_logic_vector(1468,AMPL_WIDTH),
conv_std_logic_vector(1469,AMPL_WIDTH),
conv_std_logic_vector(1469,AMPL_WIDTH),
conv_std_logic_vector(1470,AMPL_WIDTH),
conv_std_logic_vector(1471,AMPL_WIDTH),
conv_std_logic_vector(1471,AMPL_WIDTH),
conv_std_logic_vector(1472,AMPL_WIDTH),
conv_std_logic_vector(1472,AMPL_WIDTH),
conv_std_logic_vector(1473,AMPL_WIDTH),
conv_std_logic_vector(1473,AMPL_WIDTH),
conv_std_logic_vector(1474,AMPL_WIDTH),
conv_std_logic_vector(1474,AMPL_WIDTH),
conv_std_logic_vector(1475,AMPL_WIDTH),
conv_std_logic_vector(1475,AMPL_WIDTH),
conv_std_logic_vector(1476,AMPL_WIDTH),
conv_std_logic_vector(1477,AMPL_WIDTH),
conv_std_logic_vector(1477,AMPL_WIDTH),
conv_std_logic_vector(1478,AMPL_WIDTH),
conv_std_logic_vector(1478,AMPL_WIDTH),
conv_std_logic_vector(1479,AMPL_WIDTH),
conv_std_logic_vector(1479,AMPL_WIDTH),
conv_std_logic_vector(1480,AMPL_WIDTH),
conv_std_logic_vector(1480,AMPL_WIDTH),
conv_std_logic_vector(1481,AMPL_WIDTH),
conv_std_logic_vector(1481,AMPL_WIDTH),
conv_std_logic_vector(1482,AMPL_WIDTH),
conv_std_logic_vector(1483,AMPL_WIDTH),
conv_std_logic_vector(1483,AMPL_WIDTH),
conv_std_logic_vector(1484,AMPL_WIDTH),
conv_std_logic_vector(1484,AMPL_WIDTH),
conv_std_logic_vector(1485,AMPL_WIDTH),
conv_std_logic_vector(1485,AMPL_WIDTH),
conv_std_logic_vector(1486,AMPL_WIDTH),
conv_std_logic_vector(1486,AMPL_WIDTH),
conv_std_logic_vector(1487,AMPL_WIDTH),
conv_std_logic_vector(1487,AMPL_WIDTH),
conv_std_logic_vector(1488,AMPL_WIDTH),
conv_std_logic_vector(1488,AMPL_WIDTH),
conv_std_logic_vector(1489,AMPL_WIDTH),
conv_std_logic_vector(1490,AMPL_WIDTH),
conv_std_logic_vector(1490,AMPL_WIDTH),
conv_std_logic_vector(1491,AMPL_WIDTH),
conv_std_logic_vector(1491,AMPL_WIDTH),
conv_std_logic_vector(1492,AMPL_WIDTH),
conv_std_logic_vector(1492,AMPL_WIDTH),
conv_std_logic_vector(1493,AMPL_WIDTH),
conv_std_logic_vector(1493,AMPL_WIDTH),
conv_std_logic_vector(1494,AMPL_WIDTH),
conv_std_logic_vector(1494,AMPL_WIDTH),
conv_std_logic_vector(1495,AMPL_WIDTH),
conv_std_logic_vector(1495,AMPL_WIDTH),
conv_std_logic_vector(1496,AMPL_WIDTH),
conv_std_logic_vector(1497,AMPL_WIDTH),
conv_std_logic_vector(1497,AMPL_WIDTH),
conv_std_logic_vector(1498,AMPL_WIDTH),
conv_std_logic_vector(1498,AMPL_WIDTH),
conv_std_logic_vector(1499,AMPL_WIDTH),
conv_std_logic_vector(1499,AMPL_WIDTH),
conv_std_logic_vector(1500,AMPL_WIDTH),
conv_std_logic_vector(1500,AMPL_WIDTH),
conv_std_logic_vector(1501,AMPL_WIDTH),
conv_std_logic_vector(1501,AMPL_WIDTH),
conv_std_logic_vector(1502,AMPL_WIDTH),
conv_std_logic_vector(1502,AMPL_WIDTH),
conv_std_logic_vector(1503,AMPL_WIDTH),
conv_std_logic_vector(1503,AMPL_WIDTH),
conv_std_logic_vector(1504,AMPL_WIDTH),
conv_std_logic_vector(1505,AMPL_WIDTH),
conv_std_logic_vector(1505,AMPL_WIDTH),
conv_std_logic_vector(1506,AMPL_WIDTH),
conv_std_logic_vector(1506,AMPL_WIDTH),
conv_std_logic_vector(1507,AMPL_WIDTH),
conv_std_logic_vector(1507,AMPL_WIDTH),
conv_std_logic_vector(1508,AMPL_WIDTH),
conv_std_logic_vector(1508,AMPL_WIDTH),
conv_std_logic_vector(1509,AMPL_WIDTH),
conv_std_logic_vector(1509,AMPL_WIDTH),
conv_std_logic_vector(1510,AMPL_WIDTH),
conv_std_logic_vector(1510,AMPL_WIDTH),
conv_std_logic_vector(1511,AMPL_WIDTH),
conv_std_logic_vector(1511,AMPL_WIDTH),
conv_std_logic_vector(1512,AMPL_WIDTH),
conv_std_logic_vector(1513,AMPL_WIDTH),
conv_std_logic_vector(1513,AMPL_WIDTH),
conv_std_logic_vector(1514,AMPL_WIDTH),
conv_std_logic_vector(1514,AMPL_WIDTH),
conv_std_logic_vector(1515,AMPL_WIDTH),
conv_std_logic_vector(1515,AMPL_WIDTH),
conv_std_logic_vector(1516,AMPL_WIDTH),
conv_std_logic_vector(1516,AMPL_WIDTH),
conv_std_logic_vector(1517,AMPL_WIDTH),
conv_std_logic_vector(1517,AMPL_WIDTH),
conv_std_logic_vector(1518,AMPL_WIDTH),
conv_std_logic_vector(1518,AMPL_WIDTH),
conv_std_logic_vector(1519,AMPL_WIDTH),
conv_std_logic_vector(1519,AMPL_WIDTH),
conv_std_logic_vector(1520,AMPL_WIDTH),
conv_std_logic_vector(1520,AMPL_WIDTH),
conv_std_logic_vector(1521,AMPL_WIDTH),
conv_std_logic_vector(1521,AMPL_WIDTH),
conv_std_logic_vector(1522,AMPL_WIDTH),
conv_std_logic_vector(1523,AMPL_WIDTH),
conv_std_logic_vector(1523,AMPL_WIDTH),
conv_std_logic_vector(1524,AMPL_WIDTH),
conv_std_logic_vector(1524,AMPL_WIDTH),
conv_std_logic_vector(1525,AMPL_WIDTH),
conv_std_logic_vector(1525,AMPL_WIDTH),
conv_std_logic_vector(1526,AMPL_WIDTH),
conv_std_logic_vector(1526,AMPL_WIDTH),
conv_std_logic_vector(1527,AMPL_WIDTH),
conv_std_logic_vector(1527,AMPL_WIDTH),
conv_std_logic_vector(1528,AMPL_WIDTH),
conv_std_logic_vector(1528,AMPL_WIDTH),
conv_std_logic_vector(1529,AMPL_WIDTH),
conv_std_logic_vector(1529,AMPL_WIDTH),
conv_std_logic_vector(1530,AMPL_WIDTH),
conv_std_logic_vector(1530,AMPL_WIDTH),
conv_std_logic_vector(1531,AMPL_WIDTH),
conv_std_logic_vector(1531,AMPL_WIDTH),
conv_std_logic_vector(1532,AMPL_WIDTH),
conv_std_logic_vector(1532,AMPL_WIDTH),
conv_std_logic_vector(1533,AMPL_WIDTH),
conv_std_logic_vector(1533,AMPL_WIDTH),
conv_std_logic_vector(1534,AMPL_WIDTH),
conv_std_logic_vector(1535,AMPL_WIDTH),
conv_std_logic_vector(1535,AMPL_WIDTH),
conv_std_logic_vector(1536,AMPL_WIDTH),
conv_std_logic_vector(1536,AMPL_WIDTH),
conv_std_logic_vector(1537,AMPL_WIDTH),
conv_std_logic_vector(1537,AMPL_WIDTH),
conv_std_logic_vector(1538,AMPL_WIDTH),
conv_std_logic_vector(1538,AMPL_WIDTH),
conv_std_logic_vector(1539,AMPL_WIDTH),
conv_std_logic_vector(1539,AMPL_WIDTH),
conv_std_logic_vector(1540,AMPL_WIDTH),
conv_std_logic_vector(1540,AMPL_WIDTH),
conv_std_logic_vector(1541,AMPL_WIDTH),
conv_std_logic_vector(1541,AMPL_WIDTH),
conv_std_logic_vector(1542,AMPL_WIDTH),
conv_std_logic_vector(1542,AMPL_WIDTH),
conv_std_logic_vector(1543,AMPL_WIDTH),
conv_std_logic_vector(1543,AMPL_WIDTH),
conv_std_logic_vector(1544,AMPL_WIDTH),
conv_std_logic_vector(1544,AMPL_WIDTH),
conv_std_logic_vector(1545,AMPL_WIDTH),
conv_std_logic_vector(1545,AMPL_WIDTH),
conv_std_logic_vector(1546,AMPL_WIDTH),
conv_std_logic_vector(1546,AMPL_WIDTH),
conv_std_logic_vector(1547,AMPL_WIDTH),
conv_std_logic_vector(1547,AMPL_WIDTH),
conv_std_logic_vector(1548,AMPL_WIDTH),
conv_std_logic_vector(1548,AMPL_WIDTH),
conv_std_logic_vector(1549,AMPL_WIDTH),
conv_std_logic_vector(1549,AMPL_WIDTH),
conv_std_logic_vector(1550,AMPL_WIDTH),
conv_std_logic_vector(1551,AMPL_WIDTH),
conv_std_logic_vector(1551,AMPL_WIDTH),
conv_std_logic_vector(1552,AMPL_WIDTH),
conv_std_logic_vector(1552,AMPL_WIDTH),
conv_std_logic_vector(1553,AMPL_WIDTH),
conv_std_logic_vector(1553,AMPL_WIDTH),
conv_std_logic_vector(1554,AMPL_WIDTH),
conv_std_logic_vector(1554,AMPL_WIDTH),
conv_std_logic_vector(1555,AMPL_WIDTH),
conv_std_logic_vector(1555,AMPL_WIDTH),
conv_std_logic_vector(1556,AMPL_WIDTH),
conv_std_logic_vector(1556,AMPL_WIDTH),
conv_std_logic_vector(1557,AMPL_WIDTH),
conv_std_logic_vector(1557,AMPL_WIDTH),
conv_std_logic_vector(1558,AMPL_WIDTH),
conv_std_logic_vector(1558,AMPL_WIDTH),
conv_std_logic_vector(1559,AMPL_WIDTH),
conv_std_logic_vector(1559,AMPL_WIDTH),
conv_std_logic_vector(1560,AMPL_WIDTH),
conv_std_logic_vector(1560,AMPL_WIDTH),
conv_std_logic_vector(1561,AMPL_WIDTH),
conv_std_logic_vector(1561,AMPL_WIDTH),
conv_std_logic_vector(1562,AMPL_WIDTH),
conv_std_logic_vector(1562,AMPL_WIDTH),
conv_std_logic_vector(1563,AMPL_WIDTH),
conv_std_logic_vector(1563,AMPL_WIDTH),
conv_std_logic_vector(1564,AMPL_WIDTH),
conv_std_logic_vector(1564,AMPL_WIDTH),
conv_std_logic_vector(1565,AMPL_WIDTH),
conv_std_logic_vector(1565,AMPL_WIDTH),
conv_std_logic_vector(1566,AMPL_WIDTH),
conv_std_logic_vector(1566,AMPL_WIDTH),
conv_std_logic_vector(1567,AMPL_WIDTH),
conv_std_logic_vector(1567,AMPL_WIDTH),
conv_std_logic_vector(1568,AMPL_WIDTH),
conv_std_logic_vector(1568,AMPL_WIDTH),
conv_std_logic_vector(1569,AMPL_WIDTH),
conv_std_logic_vector(1569,AMPL_WIDTH),
conv_std_logic_vector(1570,AMPL_WIDTH),
conv_std_logic_vector(1570,AMPL_WIDTH),
conv_std_logic_vector(1571,AMPL_WIDTH),
conv_std_logic_vector(1571,AMPL_WIDTH),
conv_std_logic_vector(1572,AMPL_WIDTH),
conv_std_logic_vector(1572,AMPL_WIDTH),
conv_std_logic_vector(1573,AMPL_WIDTH),
conv_std_logic_vector(1573,AMPL_WIDTH),
conv_std_logic_vector(1574,AMPL_WIDTH),
conv_std_logic_vector(1574,AMPL_WIDTH),
conv_std_logic_vector(1575,AMPL_WIDTH),
conv_std_logic_vector(1575,AMPL_WIDTH),
conv_std_logic_vector(1576,AMPL_WIDTH),
conv_std_logic_vector(1576,AMPL_WIDTH),
conv_std_logic_vector(1577,AMPL_WIDTH),
conv_std_logic_vector(1577,AMPL_WIDTH),
conv_std_logic_vector(1578,AMPL_WIDTH),
conv_std_logic_vector(1578,AMPL_WIDTH),
conv_std_logic_vector(1579,AMPL_WIDTH),
conv_std_logic_vector(1579,AMPL_WIDTH),
conv_std_logic_vector(1580,AMPL_WIDTH),
conv_std_logic_vector(1580,AMPL_WIDTH),
conv_std_logic_vector(1581,AMPL_WIDTH),
conv_std_logic_vector(1581,AMPL_WIDTH),
conv_std_logic_vector(1582,AMPL_WIDTH),
conv_std_logic_vector(1582,AMPL_WIDTH),
conv_std_logic_vector(1583,AMPL_WIDTH),
conv_std_logic_vector(1583,AMPL_WIDTH),
conv_std_logic_vector(1584,AMPL_WIDTH),
conv_std_logic_vector(1584,AMPL_WIDTH),
conv_std_logic_vector(1585,AMPL_WIDTH),
conv_std_logic_vector(1585,AMPL_WIDTH),
conv_std_logic_vector(1586,AMPL_WIDTH),
conv_std_logic_vector(1586,AMPL_WIDTH),
conv_std_logic_vector(1587,AMPL_WIDTH),
conv_std_logic_vector(1587,AMPL_WIDTH),
conv_std_logic_vector(1588,AMPL_WIDTH),
conv_std_logic_vector(1588,AMPL_WIDTH),
conv_std_logic_vector(1589,AMPL_WIDTH),
conv_std_logic_vector(1589,AMPL_WIDTH),
conv_std_logic_vector(1590,AMPL_WIDTH),
conv_std_logic_vector(1590,AMPL_WIDTH),
conv_std_logic_vector(1591,AMPL_WIDTH),
conv_std_logic_vector(1591,AMPL_WIDTH),
conv_std_logic_vector(1592,AMPL_WIDTH),
conv_std_logic_vector(1592,AMPL_WIDTH),
conv_std_logic_vector(1593,AMPL_WIDTH),
conv_std_logic_vector(1593,AMPL_WIDTH),
conv_std_logic_vector(1594,AMPL_WIDTH),
conv_std_logic_vector(1594,AMPL_WIDTH),
conv_std_logic_vector(1595,AMPL_WIDTH),
conv_std_logic_vector(1595,AMPL_WIDTH),
conv_std_logic_vector(1596,AMPL_WIDTH),
conv_std_logic_vector(1596,AMPL_WIDTH),
conv_std_logic_vector(1597,AMPL_WIDTH),
conv_std_logic_vector(1597,AMPL_WIDTH),
conv_std_logic_vector(1598,AMPL_WIDTH),
conv_std_logic_vector(1598,AMPL_WIDTH),
conv_std_logic_vector(1599,AMPL_WIDTH),
conv_std_logic_vector(1599,AMPL_WIDTH),
conv_std_logic_vector(1600,AMPL_WIDTH),
conv_std_logic_vector(1600,AMPL_WIDTH),
conv_std_logic_vector(1601,AMPL_WIDTH),
conv_std_logic_vector(1601,AMPL_WIDTH),
conv_std_logic_vector(1602,AMPL_WIDTH),
conv_std_logic_vector(1602,AMPL_WIDTH),
conv_std_logic_vector(1603,AMPL_WIDTH),
conv_std_logic_vector(1603,AMPL_WIDTH),
conv_std_logic_vector(1604,AMPL_WIDTH),
conv_std_logic_vector(1604,AMPL_WIDTH),
conv_std_logic_vector(1605,AMPL_WIDTH),
conv_std_logic_vector(1605,AMPL_WIDTH),
conv_std_logic_vector(1606,AMPL_WIDTH),
conv_std_logic_vector(1606,AMPL_WIDTH),
conv_std_logic_vector(1606,AMPL_WIDTH),
conv_std_logic_vector(1607,AMPL_WIDTH),
conv_std_logic_vector(1607,AMPL_WIDTH),
conv_std_logic_vector(1608,AMPL_WIDTH),
conv_std_logic_vector(1608,AMPL_WIDTH),
conv_std_logic_vector(1609,AMPL_WIDTH),
conv_std_logic_vector(1609,AMPL_WIDTH),
conv_std_logic_vector(1610,AMPL_WIDTH),
conv_std_logic_vector(1610,AMPL_WIDTH),
conv_std_logic_vector(1611,AMPL_WIDTH),
conv_std_logic_vector(1611,AMPL_WIDTH),
conv_std_logic_vector(1612,AMPL_WIDTH),
conv_std_logic_vector(1612,AMPL_WIDTH),
conv_std_logic_vector(1613,AMPL_WIDTH),
conv_std_logic_vector(1613,AMPL_WIDTH),
conv_std_logic_vector(1614,AMPL_WIDTH),
conv_std_logic_vector(1614,AMPL_WIDTH),
conv_std_logic_vector(1615,AMPL_WIDTH),
conv_std_logic_vector(1615,AMPL_WIDTH),
conv_std_logic_vector(1616,AMPL_WIDTH),
conv_std_logic_vector(1616,AMPL_WIDTH),
conv_std_logic_vector(1617,AMPL_WIDTH),
conv_std_logic_vector(1617,AMPL_WIDTH),
conv_std_logic_vector(1618,AMPL_WIDTH),
conv_std_logic_vector(1618,AMPL_WIDTH),
conv_std_logic_vector(1619,AMPL_WIDTH),
conv_std_logic_vector(1619,AMPL_WIDTH),
conv_std_logic_vector(1620,AMPL_WIDTH),
conv_std_logic_vector(1620,AMPL_WIDTH),
conv_std_logic_vector(1620,AMPL_WIDTH),
conv_std_logic_vector(1621,AMPL_WIDTH),
conv_std_logic_vector(1621,AMPL_WIDTH),
conv_std_logic_vector(1622,AMPL_WIDTH),
conv_std_logic_vector(1622,AMPL_WIDTH),
conv_std_logic_vector(1623,AMPL_WIDTH),
conv_std_logic_vector(1623,AMPL_WIDTH),
conv_std_logic_vector(1624,AMPL_WIDTH),
conv_std_logic_vector(1624,AMPL_WIDTH),
conv_std_logic_vector(1625,AMPL_WIDTH),
conv_std_logic_vector(1625,AMPL_WIDTH),
conv_std_logic_vector(1626,AMPL_WIDTH),
conv_std_logic_vector(1626,AMPL_WIDTH),
conv_std_logic_vector(1627,AMPL_WIDTH),
conv_std_logic_vector(1627,AMPL_WIDTH),
conv_std_logic_vector(1628,AMPL_WIDTH),
conv_std_logic_vector(1628,AMPL_WIDTH),
conv_std_logic_vector(1629,AMPL_WIDTH),
conv_std_logic_vector(1629,AMPL_WIDTH),
conv_std_logic_vector(1630,AMPL_WIDTH),
conv_std_logic_vector(1630,AMPL_WIDTH),
conv_std_logic_vector(1631,AMPL_WIDTH),
conv_std_logic_vector(1631,AMPL_WIDTH),
conv_std_logic_vector(1631,AMPL_WIDTH),
conv_std_logic_vector(1632,AMPL_WIDTH),
conv_std_logic_vector(1632,AMPL_WIDTH),
conv_std_logic_vector(1633,AMPL_WIDTH),
conv_std_logic_vector(1633,AMPL_WIDTH),
conv_std_logic_vector(1634,AMPL_WIDTH),
conv_std_logic_vector(1634,AMPL_WIDTH),
conv_std_logic_vector(1635,AMPL_WIDTH),
conv_std_logic_vector(1635,AMPL_WIDTH),
conv_std_logic_vector(1636,AMPL_WIDTH),
conv_std_logic_vector(1636,AMPL_WIDTH),
conv_std_logic_vector(1637,AMPL_WIDTH),
conv_std_logic_vector(1637,AMPL_WIDTH),
conv_std_logic_vector(1638,AMPL_WIDTH),
conv_std_logic_vector(1638,AMPL_WIDTH),
conv_std_logic_vector(1639,AMPL_WIDTH),
conv_std_logic_vector(1639,AMPL_WIDTH),
conv_std_logic_vector(1639,AMPL_WIDTH),
conv_std_logic_vector(1640,AMPL_WIDTH),
conv_std_logic_vector(1640,AMPL_WIDTH),
conv_std_logic_vector(1641,AMPL_WIDTH),
conv_std_logic_vector(1641,AMPL_WIDTH),
conv_std_logic_vector(1642,AMPL_WIDTH),
conv_std_logic_vector(1642,AMPL_WIDTH),
conv_std_logic_vector(1643,AMPL_WIDTH),
conv_std_logic_vector(1643,AMPL_WIDTH),
conv_std_logic_vector(1644,AMPL_WIDTH),
conv_std_logic_vector(1644,AMPL_WIDTH),
conv_std_logic_vector(1645,AMPL_WIDTH),
conv_std_logic_vector(1645,AMPL_WIDTH),
conv_std_logic_vector(1646,AMPL_WIDTH),
conv_std_logic_vector(1646,AMPL_WIDTH),
conv_std_logic_vector(1647,AMPL_WIDTH),
conv_std_logic_vector(1647,AMPL_WIDTH),
conv_std_logic_vector(1647,AMPL_WIDTH),
conv_std_logic_vector(1648,AMPL_WIDTH),
conv_std_logic_vector(1648,AMPL_WIDTH),
conv_std_logic_vector(1649,AMPL_WIDTH),
conv_std_logic_vector(1649,AMPL_WIDTH),
conv_std_logic_vector(1650,AMPL_WIDTH),
conv_std_logic_vector(1650,AMPL_WIDTH),
conv_std_logic_vector(1651,AMPL_WIDTH),
conv_std_logic_vector(1651,AMPL_WIDTH),
conv_std_logic_vector(1652,AMPL_WIDTH),
conv_std_logic_vector(1652,AMPL_WIDTH),
conv_std_logic_vector(1653,AMPL_WIDTH),
conv_std_logic_vector(1653,AMPL_WIDTH),
conv_std_logic_vector(1653,AMPL_WIDTH),
conv_std_logic_vector(1654,AMPL_WIDTH),
conv_std_logic_vector(1654,AMPL_WIDTH),
conv_std_logic_vector(1655,AMPL_WIDTH),
conv_std_logic_vector(1655,AMPL_WIDTH),
conv_std_logic_vector(1656,AMPL_WIDTH),
conv_std_logic_vector(1656,AMPL_WIDTH),
conv_std_logic_vector(1657,AMPL_WIDTH),
conv_std_logic_vector(1657,AMPL_WIDTH),
conv_std_logic_vector(1658,AMPL_WIDTH),
conv_std_logic_vector(1658,AMPL_WIDTH),
conv_std_logic_vector(1659,AMPL_WIDTH),
conv_std_logic_vector(1659,AMPL_WIDTH),
conv_std_logic_vector(1659,AMPL_WIDTH),
conv_std_logic_vector(1660,AMPL_WIDTH),
conv_std_logic_vector(1660,AMPL_WIDTH),
conv_std_logic_vector(1661,AMPL_WIDTH),
conv_std_logic_vector(1661,AMPL_WIDTH),
conv_std_logic_vector(1662,AMPL_WIDTH),
conv_std_logic_vector(1662,AMPL_WIDTH),
conv_std_logic_vector(1663,AMPL_WIDTH),
conv_std_logic_vector(1663,AMPL_WIDTH),
conv_std_logic_vector(1664,AMPL_WIDTH),
conv_std_logic_vector(1664,AMPL_WIDTH),
conv_std_logic_vector(1665,AMPL_WIDTH),
conv_std_logic_vector(1665,AMPL_WIDTH),
conv_std_logic_vector(1665,AMPL_WIDTH),
conv_std_logic_vector(1666,AMPL_WIDTH),
conv_std_logic_vector(1666,AMPL_WIDTH),
conv_std_logic_vector(1667,AMPL_WIDTH),
conv_std_logic_vector(1667,AMPL_WIDTH),
conv_std_logic_vector(1668,AMPL_WIDTH),
conv_std_logic_vector(1668,AMPL_WIDTH),
conv_std_logic_vector(1669,AMPL_WIDTH),
conv_std_logic_vector(1669,AMPL_WIDTH),
conv_std_logic_vector(1670,AMPL_WIDTH),
conv_std_logic_vector(1670,AMPL_WIDTH),
conv_std_logic_vector(1670,AMPL_WIDTH),
conv_std_logic_vector(1671,AMPL_WIDTH),
conv_std_logic_vector(1671,AMPL_WIDTH),
conv_std_logic_vector(1672,AMPL_WIDTH),
conv_std_logic_vector(1672,AMPL_WIDTH),
conv_std_logic_vector(1673,AMPL_WIDTH),
conv_std_logic_vector(1673,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1675,AMPL_WIDTH),
conv_std_logic_vector(1675,AMPL_WIDTH),
conv_std_logic_vector(1676,AMPL_WIDTH),
conv_std_logic_vector(1676,AMPL_WIDTH),
conv_std_logic_vector(1677,AMPL_WIDTH),
conv_std_logic_vector(1677,AMPL_WIDTH),
conv_std_logic_vector(1678,AMPL_WIDTH),
conv_std_logic_vector(1678,AMPL_WIDTH),
conv_std_logic_vector(1679,AMPL_WIDTH),
conv_std_logic_vector(1679,AMPL_WIDTH),
conv_std_logic_vector(1679,AMPL_WIDTH),
conv_std_logic_vector(1680,AMPL_WIDTH),
conv_std_logic_vector(1680,AMPL_WIDTH),
conv_std_logic_vector(1681,AMPL_WIDTH),
conv_std_logic_vector(1681,AMPL_WIDTH),
conv_std_logic_vector(1682,AMPL_WIDTH),
conv_std_logic_vector(1682,AMPL_WIDTH),
conv_std_logic_vector(1683,AMPL_WIDTH),
conv_std_logic_vector(1683,AMPL_WIDTH),
conv_std_logic_vector(1683,AMPL_WIDTH),
conv_std_logic_vector(1684,AMPL_WIDTH),
conv_std_logic_vector(1684,AMPL_WIDTH),
conv_std_logic_vector(1685,AMPL_WIDTH),
conv_std_logic_vector(1685,AMPL_WIDTH),
conv_std_logic_vector(1686,AMPL_WIDTH),
conv_std_logic_vector(1686,AMPL_WIDTH),
conv_std_logic_vector(1687,AMPL_WIDTH),
conv_std_logic_vector(1687,AMPL_WIDTH),
conv_std_logic_vector(1687,AMPL_WIDTH),
conv_std_logic_vector(1688,AMPL_WIDTH),
conv_std_logic_vector(1688,AMPL_WIDTH),
conv_std_logic_vector(1689,AMPL_WIDTH),
conv_std_logic_vector(1689,AMPL_WIDTH),
conv_std_logic_vector(1690,AMPL_WIDTH),
conv_std_logic_vector(1690,AMPL_WIDTH),
conv_std_logic_vector(1691,AMPL_WIDTH),
conv_std_logic_vector(1691,AMPL_WIDTH),
conv_std_logic_vector(1691,AMPL_WIDTH),
conv_std_logic_vector(1692,AMPL_WIDTH),
conv_std_logic_vector(1692,AMPL_WIDTH),
conv_std_logic_vector(1693,AMPL_WIDTH),
conv_std_logic_vector(1693,AMPL_WIDTH),
conv_std_logic_vector(1694,AMPL_WIDTH),
conv_std_logic_vector(1694,AMPL_WIDTH),
conv_std_logic_vector(1695,AMPL_WIDTH),
conv_std_logic_vector(1695,AMPL_WIDTH),
conv_std_logic_vector(1695,AMPL_WIDTH),
conv_std_logic_vector(1696,AMPL_WIDTH),
conv_std_logic_vector(1696,AMPL_WIDTH),
conv_std_logic_vector(1697,AMPL_WIDTH),
conv_std_logic_vector(1697,AMPL_WIDTH),
conv_std_logic_vector(1698,AMPL_WIDTH),
conv_std_logic_vector(1698,AMPL_WIDTH),
conv_std_logic_vector(1699,AMPL_WIDTH),
conv_std_logic_vector(1699,AMPL_WIDTH),
conv_std_logic_vector(1699,AMPL_WIDTH),
conv_std_logic_vector(1700,AMPL_WIDTH),
conv_std_logic_vector(1700,AMPL_WIDTH),
conv_std_logic_vector(1701,AMPL_WIDTH),
conv_std_logic_vector(1701,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1703,AMPL_WIDTH),
conv_std_logic_vector(1703,AMPL_WIDTH),
conv_std_logic_vector(1704,AMPL_WIDTH),
conv_std_logic_vector(1704,AMPL_WIDTH),
conv_std_logic_vector(1705,AMPL_WIDTH),
conv_std_logic_vector(1705,AMPL_WIDTH),
conv_std_logic_vector(1705,AMPL_WIDTH),
conv_std_logic_vector(1706,AMPL_WIDTH),
conv_std_logic_vector(1706,AMPL_WIDTH),
conv_std_logic_vector(1707,AMPL_WIDTH),
conv_std_logic_vector(1707,AMPL_WIDTH),
conv_std_logic_vector(1708,AMPL_WIDTH),
conv_std_logic_vector(1708,AMPL_WIDTH),
conv_std_logic_vector(1709,AMPL_WIDTH),
conv_std_logic_vector(1709,AMPL_WIDTH),
conv_std_logic_vector(1709,AMPL_WIDTH),
conv_std_logic_vector(1710,AMPL_WIDTH),
conv_std_logic_vector(1710,AMPL_WIDTH),
conv_std_logic_vector(1711,AMPL_WIDTH),
conv_std_logic_vector(1711,AMPL_WIDTH),
conv_std_logic_vector(1712,AMPL_WIDTH),
conv_std_logic_vector(1712,AMPL_WIDTH),
conv_std_logic_vector(1712,AMPL_WIDTH),
conv_std_logic_vector(1713,AMPL_WIDTH),
conv_std_logic_vector(1713,AMPL_WIDTH),
conv_std_logic_vector(1714,AMPL_WIDTH),
conv_std_logic_vector(1714,AMPL_WIDTH),
conv_std_logic_vector(1715,AMPL_WIDTH),
conv_std_logic_vector(1715,AMPL_WIDTH),
conv_std_logic_vector(1715,AMPL_WIDTH),
conv_std_logic_vector(1716,AMPL_WIDTH),
conv_std_logic_vector(1716,AMPL_WIDTH),
conv_std_logic_vector(1717,AMPL_WIDTH),
conv_std_logic_vector(1717,AMPL_WIDTH),
conv_std_logic_vector(1718,AMPL_WIDTH),
conv_std_logic_vector(1718,AMPL_WIDTH),
conv_std_logic_vector(1718,AMPL_WIDTH),
conv_std_logic_vector(1719,AMPL_WIDTH),
conv_std_logic_vector(1719,AMPL_WIDTH),
conv_std_logic_vector(1720,AMPL_WIDTH),
conv_std_logic_vector(1720,AMPL_WIDTH),
conv_std_logic_vector(1721,AMPL_WIDTH),
conv_std_logic_vector(1721,AMPL_WIDTH),
conv_std_logic_vector(1721,AMPL_WIDTH),
conv_std_logic_vector(1722,AMPL_WIDTH),
conv_std_logic_vector(1722,AMPL_WIDTH),
conv_std_logic_vector(1723,AMPL_WIDTH),
conv_std_logic_vector(1723,AMPL_WIDTH),
conv_std_logic_vector(1724,AMPL_WIDTH),
conv_std_logic_vector(1724,AMPL_WIDTH),
conv_std_logic_vector(1724,AMPL_WIDTH),
conv_std_logic_vector(1725,AMPL_WIDTH),
conv_std_logic_vector(1725,AMPL_WIDTH),
conv_std_logic_vector(1726,AMPL_WIDTH),
conv_std_logic_vector(1726,AMPL_WIDTH),
conv_std_logic_vector(1726,AMPL_WIDTH),
conv_std_logic_vector(1727,AMPL_WIDTH),
conv_std_logic_vector(1727,AMPL_WIDTH),
conv_std_logic_vector(1728,AMPL_WIDTH),
conv_std_logic_vector(1728,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1730,AMPL_WIDTH),
conv_std_logic_vector(1730,AMPL_WIDTH),
conv_std_logic_vector(1731,AMPL_WIDTH),
conv_std_logic_vector(1731,AMPL_WIDTH),
conv_std_logic_vector(1732,AMPL_WIDTH),
conv_std_logic_vector(1732,AMPL_WIDTH),
conv_std_logic_vector(1732,AMPL_WIDTH),
conv_std_logic_vector(1733,AMPL_WIDTH),
conv_std_logic_vector(1733,AMPL_WIDTH),
conv_std_logic_vector(1734,AMPL_WIDTH),
conv_std_logic_vector(1734,AMPL_WIDTH),
conv_std_logic_vector(1734,AMPL_WIDTH),
conv_std_logic_vector(1735,AMPL_WIDTH),
conv_std_logic_vector(1735,AMPL_WIDTH),
conv_std_logic_vector(1736,AMPL_WIDTH),
conv_std_logic_vector(1736,AMPL_WIDTH),
conv_std_logic_vector(1737,AMPL_WIDTH),
conv_std_logic_vector(1737,AMPL_WIDTH),
conv_std_logic_vector(1737,AMPL_WIDTH),
conv_std_logic_vector(1738,AMPL_WIDTH),
conv_std_logic_vector(1738,AMPL_WIDTH),
conv_std_logic_vector(1739,AMPL_WIDTH),
conv_std_logic_vector(1739,AMPL_WIDTH),
conv_std_logic_vector(1739,AMPL_WIDTH),
conv_std_logic_vector(1740,AMPL_WIDTH),
conv_std_logic_vector(1740,AMPL_WIDTH),
conv_std_logic_vector(1741,AMPL_WIDTH),
conv_std_logic_vector(1741,AMPL_WIDTH),
conv_std_logic_vector(1741,AMPL_WIDTH),
conv_std_logic_vector(1742,AMPL_WIDTH),
conv_std_logic_vector(1742,AMPL_WIDTH),
conv_std_logic_vector(1743,AMPL_WIDTH),
conv_std_logic_vector(1743,AMPL_WIDTH),
conv_std_logic_vector(1744,AMPL_WIDTH),
conv_std_logic_vector(1744,AMPL_WIDTH),
conv_std_logic_vector(1744,AMPL_WIDTH),
conv_std_logic_vector(1745,AMPL_WIDTH),
conv_std_logic_vector(1745,AMPL_WIDTH),
conv_std_logic_vector(1746,AMPL_WIDTH),
conv_std_logic_vector(1746,AMPL_WIDTH),
conv_std_logic_vector(1746,AMPL_WIDTH),
conv_std_logic_vector(1747,AMPL_WIDTH),
conv_std_logic_vector(1747,AMPL_WIDTH),
conv_std_logic_vector(1748,AMPL_WIDTH),
conv_std_logic_vector(1748,AMPL_WIDTH),
conv_std_logic_vector(1748,AMPL_WIDTH),
conv_std_logic_vector(1749,AMPL_WIDTH),
conv_std_logic_vector(1749,AMPL_WIDTH),
conv_std_logic_vector(1750,AMPL_WIDTH),
conv_std_logic_vector(1750,AMPL_WIDTH),
conv_std_logic_vector(1751,AMPL_WIDTH),
conv_std_logic_vector(1751,AMPL_WIDTH),
conv_std_logic_vector(1751,AMPL_WIDTH),
conv_std_logic_vector(1752,AMPL_WIDTH),
conv_std_logic_vector(1752,AMPL_WIDTH),
conv_std_logic_vector(1753,AMPL_WIDTH),
conv_std_logic_vector(1753,AMPL_WIDTH),
conv_std_logic_vector(1753,AMPL_WIDTH),
conv_std_logic_vector(1754,AMPL_WIDTH),
conv_std_logic_vector(1754,AMPL_WIDTH),
conv_std_logic_vector(1755,AMPL_WIDTH),
conv_std_logic_vector(1755,AMPL_WIDTH),
conv_std_logic_vector(1755,AMPL_WIDTH),
conv_std_logic_vector(1756,AMPL_WIDTH),
conv_std_logic_vector(1756,AMPL_WIDTH),
conv_std_logic_vector(1757,AMPL_WIDTH),
conv_std_logic_vector(1757,AMPL_WIDTH),
conv_std_logic_vector(1757,AMPL_WIDTH),
conv_std_logic_vector(1758,AMPL_WIDTH),
conv_std_logic_vector(1758,AMPL_WIDTH),
conv_std_logic_vector(1759,AMPL_WIDTH),
conv_std_logic_vector(1759,AMPL_WIDTH),
conv_std_logic_vector(1759,AMPL_WIDTH),
conv_std_logic_vector(1760,AMPL_WIDTH),
conv_std_logic_vector(1760,AMPL_WIDTH),
conv_std_logic_vector(1761,AMPL_WIDTH),
conv_std_logic_vector(1761,AMPL_WIDTH),
conv_std_logic_vector(1761,AMPL_WIDTH),
conv_std_logic_vector(1762,AMPL_WIDTH),
conv_std_logic_vector(1762,AMPL_WIDTH),
conv_std_logic_vector(1763,AMPL_WIDTH),
conv_std_logic_vector(1763,AMPL_WIDTH),
conv_std_logic_vector(1763,AMPL_WIDTH),
conv_std_logic_vector(1764,AMPL_WIDTH),
conv_std_logic_vector(1764,AMPL_WIDTH),
conv_std_logic_vector(1765,AMPL_WIDTH),
conv_std_logic_vector(1765,AMPL_WIDTH),
conv_std_logic_vector(1765,AMPL_WIDTH),
conv_std_logic_vector(1766,AMPL_WIDTH),
conv_std_logic_vector(1766,AMPL_WIDTH),
conv_std_logic_vector(1767,AMPL_WIDTH),
conv_std_logic_vector(1767,AMPL_WIDTH),
conv_std_logic_vector(1767,AMPL_WIDTH),
conv_std_logic_vector(1768,AMPL_WIDTH),
conv_std_logic_vector(1768,AMPL_WIDTH),
conv_std_logic_vector(1769,AMPL_WIDTH),
conv_std_logic_vector(1769,AMPL_WIDTH),
conv_std_logic_vector(1769,AMPL_WIDTH),
conv_std_logic_vector(1770,AMPL_WIDTH),
conv_std_logic_vector(1770,AMPL_WIDTH),
conv_std_logic_vector(1771,AMPL_WIDTH),
conv_std_logic_vector(1771,AMPL_WIDTH),
conv_std_logic_vector(1771,AMPL_WIDTH),
conv_std_logic_vector(1772,AMPL_WIDTH),
conv_std_logic_vector(1772,AMPL_WIDTH),
conv_std_logic_vector(1772,AMPL_WIDTH),
conv_std_logic_vector(1773,AMPL_WIDTH),
conv_std_logic_vector(1773,AMPL_WIDTH),
conv_std_logic_vector(1774,AMPL_WIDTH),
conv_std_logic_vector(1774,AMPL_WIDTH),
conv_std_logic_vector(1774,AMPL_WIDTH),
conv_std_logic_vector(1775,AMPL_WIDTH),
conv_std_logic_vector(1775,AMPL_WIDTH),
conv_std_logic_vector(1776,AMPL_WIDTH),
conv_std_logic_vector(1776,AMPL_WIDTH),
conv_std_logic_vector(1776,AMPL_WIDTH),
conv_std_logic_vector(1777,AMPL_WIDTH),
conv_std_logic_vector(1777,AMPL_WIDTH),
conv_std_logic_vector(1778,AMPL_WIDTH),
conv_std_logic_vector(1778,AMPL_WIDTH),
conv_std_logic_vector(1778,AMPL_WIDTH),
conv_std_logic_vector(1779,AMPL_WIDTH),
conv_std_logic_vector(1779,AMPL_WIDTH),
conv_std_logic_vector(1780,AMPL_WIDTH),
conv_std_logic_vector(1780,AMPL_WIDTH),
conv_std_logic_vector(1780,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1782,AMPL_WIDTH),
conv_std_logic_vector(1782,AMPL_WIDTH),
conv_std_logic_vector(1783,AMPL_WIDTH),
conv_std_logic_vector(1783,AMPL_WIDTH),
conv_std_logic_vector(1783,AMPL_WIDTH),
conv_std_logic_vector(1784,AMPL_WIDTH),
conv_std_logic_vector(1784,AMPL_WIDTH),
conv_std_logic_vector(1785,AMPL_WIDTH),
conv_std_logic_vector(1785,AMPL_WIDTH),
conv_std_logic_vector(1785,AMPL_WIDTH),
conv_std_logic_vector(1786,AMPL_WIDTH),
conv_std_logic_vector(1786,AMPL_WIDTH),
conv_std_logic_vector(1786,AMPL_WIDTH),
conv_std_logic_vector(1787,AMPL_WIDTH),
conv_std_logic_vector(1787,AMPL_WIDTH),
conv_std_logic_vector(1788,AMPL_WIDTH),
conv_std_logic_vector(1788,AMPL_WIDTH),
conv_std_logic_vector(1788,AMPL_WIDTH),
conv_std_logic_vector(1789,AMPL_WIDTH),
conv_std_logic_vector(1789,AMPL_WIDTH),
conv_std_logic_vector(1790,AMPL_WIDTH),
conv_std_logic_vector(1790,AMPL_WIDTH),
conv_std_logic_vector(1790,AMPL_WIDTH),
conv_std_logic_vector(1791,AMPL_WIDTH),
conv_std_logic_vector(1791,AMPL_WIDTH),
conv_std_logic_vector(1791,AMPL_WIDTH),
conv_std_logic_vector(1792,AMPL_WIDTH),
conv_std_logic_vector(1792,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1794,AMPL_WIDTH),
conv_std_logic_vector(1794,AMPL_WIDTH),
conv_std_logic_vector(1794,AMPL_WIDTH),
conv_std_logic_vector(1795,AMPL_WIDTH),
conv_std_logic_vector(1795,AMPL_WIDTH),
conv_std_logic_vector(1796,AMPL_WIDTH),
conv_std_logic_vector(1796,AMPL_WIDTH),
conv_std_logic_vector(1796,AMPL_WIDTH),
conv_std_logic_vector(1797,AMPL_WIDTH),
conv_std_logic_vector(1797,AMPL_WIDTH),
conv_std_logic_vector(1797,AMPL_WIDTH),
conv_std_logic_vector(1798,AMPL_WIDTH),
conv_std_logic_vector(1798,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1800,AMPL_WIDTH),
conv_std_logic_vector(1800,AMPL_WIDTH),
conv_std_logic_vector(1800,AMPL_WIDTH),
conv_std_logic_vector(1801,AMPL_WIDTH),
conv_std_logic_vector(1801,AMPL_WIDTH),
conv_std_logic_vector(1802,AMPL_WIDTH),
conv_std_logic_vector(1802,AMPL_WIDTH),
conv_std_logic_vector(1802,AMPL_WIDTH),
conv_std_logic_vector(1803,AMPL_WIDTH),
conv_std_logic_vector(1803,AMPL_WIDTH),
conv_std_logic_vector(1803,AMPL_WIDTH),
conv_std_logic_vector(1804,AMPL_WIDTH),
conv_std_logic_vector(1804,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1806,AMPL_WIDTH),
conv_std_logic_vector(1806,AMPL_WIDTH),
conv_std_logic_vector(1806,AMPL_WIDTH),
conv_std_logic_vector(1807,AMPL_WIDTH),
conv_std_logic_vector(1807,AMPL_WIDTH),
conv_std_logic_vector(1808,AMPL_WIDTH),
conv_std_logic_vector(1808,AMPL_WIDTH),
conv_std_logic_vector(1808,AMPL_WIDTH),
conv_std_logic_vector(1809,AMPL_WIDTH),
conv_std_logic_vector(1809,AMPL_WIDTH),
conv_std_logic_vector(1809,AMPL_WIDTH),
conv_std_logic_vector(1810,AMPL_WIDTH),
conv_std_logic_vector(1810,AMPL_WIDTH),
conv_std_logic_vector(1810,AMPL_WIDTH),
conv_std_logic_vector(1811,AMPL_WIDTH),
conv_std_logic_vector(1811,AMPL_WIDTH),
conv_std_logic_vector(1812,AMPL_WIDTH),
conv_std_logic_vector(1812,AMPL_WIDTH),
conv_std_logic_vector(1812,AMPL_WIDTH),
conv_std_logic_vector(1813,AMPL_WIDTH),
conv_std_logic_vector(1813,AMPL_WIDTH),
conv_std_logic_vector(1813,AMPL_WIDTH),
conv_std_logic_vector(1814,AMPL_WIDTH),
conv_std_logic_vector(1814,AMPL_WIDTH),
conv_std_logic_vector(1814,AMPL_WIDTH),
conv_std_logic_vector(1815,AMPL_WIDTH),
conv_std_logic_vector(1815,AMPL_WIDTH),
conv_std_logic_vector(1816,AMPL_WIDTH),
conv_std_logic_vector(1816,AMPL_WIDTH),
conv_std_logic_vector(1816,AMPL_WIDTH),
conv_std_logic_vector(1817,AMPL_WIDTH),
conv_std_logic_vector(1817,AMPL_WIDTH),
conv_std_logic_vector(1817,AMPL_WIDTH),
conv_std_logic_vector(1818,AMPL_WIDTH),
conv_std_logic_vector(1818,AMPL_WIDTH),
conv_std_logic_vector(1818,AMPL_WIDTH),
conv_std_logic_vector(1819,AMPL_WIDTH),
conv_std_logic_vector(1819,AMPL_WIDTH),
conv_std_logic_vector(1820,AMPL_WIDTH),
conv_std_logic_vector(1820,AMPL_WIDTH),
conv_std_logic_vector(1820,AMPL_WIDTH),
conv_std_logic_vector(1821,AMPL_WIDTH),
conv_std_logic_vector(1821,AMPL_WIDTH),
conv_std_logic_vector(1821,AMPL_WIDTH),
conv_std_logic_vector(1822,AMPL_WIDTH),
conv_std_logic_vector(1822,AMPL_WIDTH),
conv_std_logic_vector(1822,AMPL_WIDTH),
conv_std_logic_vector(1823,AMPL_WIDTH),
conv_std_logic_vector(1823,AMPL_WIDTH),
conv_std_logic_vector(1823,AMPL_WIDTH),
conv_std_logic_vector(1824,AMPL_WIDTH),
conv_std_logic_vector(1824,AMPL_WIDTH),
conv_std_logic_vector(1825,AMPL_WIDTH),
conv_std_logic_vector(1825,AMPL_WIDTH),
conv_std_logic_vector(1825,AMPL_WIDTH),
conv_std_logic_vector(1826,AMPL_WIDTH),
conv_std_logic_vector(1826,AMPL_WIDTH),
conv_std_logic_vector(1826,AMPL_WIDTH),
conv_std_logic_vector(1827,AMPL_WIDTH),
conv_std_logic_vector(1827,AMPL_WIDTH),
conv_std_logic_vector(1827,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1829,AMPL_WIDTH),
conv_std_logic_vector(1829,AMPL_WIDTH),
conv_std_logic_vector(1829,AMPL_WIDTH),
conv_std_logic_vector(1830,AMPL_WIDTH),
conv_std_logic_vector(1830,AMPL_WIDTH),
conv_std_logic_vector(1831,AMPL_WIDTH),
conv_std_logic_vector(1831,AMPL_WIDTH),
conv_std_logic_vector(1831,AMPL_WIDTH),
conv_std_logic_vector(1832,AMPL_WIDTH),
conv_std_logic_vector(1832,AMPL_WIDTH),
conv_std_logic_vector(1832,AMPL_WIDTH),
conv_std_logic_vector(1833,AMPL_WIDTH),
conv_std_logic_vector(1833,AMPL_WIDTH),
conv_std_logic_vector(1833,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1835,AMPL_WIDTH),
conv_std_logic_vector(1835,AMPL_WIDTH),
conv_std_logic_vector(1835,AMPL_WIDTH),
conv_std_logic_vector(1836,AMPL_WIDTH),
conv_std_logic_vector(1836,AMPL_WIDTH),
conv_std_logic_vector(1836,AMPL_WIDTH),
conv_std_logic_vector(1837,AMPL_WIDTH),
conv_std_logic_vector(1837,AMPL_WIDTH),
conv_std_logic_vector(1838,AMPL_WIDTH),
conv_std_logic_vector(1838,AMPL_WIDTH),
conv_std_logic_vector(1838,AMPL_WIDTH),
conv_std_logic_vector(1839,AMPL_WIDTH),
conv_std_logic_vector(1839,AMPL_WIDTH),
conv_std_logic_vector(1839,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1841,AMPL_WIDTH),
conv_std_logic_vector(1841,AMPL_WIDTH),
conv_std_logic_vector(1841,AMPL_WIDTH),
conv_std_logic_vector(1842,AMPL_WIDTH),
conv_std_logic_vector(1842,AMPL_WIDTH),
conv_std_logic_vector(1842,AMPL_WIDTH),
conv_std_logic_vector(1843,AMPL_WIDTH),
conv_std_logic_vector(1843,AMPL_WIDTH),
conv_std_logic_vector(1843,AMPL_WIDTH),
conv_std_logic_vector(1844,AMPL_WIDTH),
conv_std_logic_vector(1844,AMPL_WIDTH),
conv_std_logic_vector(1844,AMPL_WIDTH),
conv_std_logic_vector(1845,AMPL_WIDTH),
conv_std_logic_vector(1845,AMPL_WIDTH),
conv_std_logic_vector(1845,AMPL_WIDTH),
conv_std_logic_vector(1846,AMPL_WIDTH),
conv_std_logic_vector(1846,AMPL_WIDTH),
conv_std_logic_vector(1846,AMPL_WIDTH),
conv_std_logic_vector(1847,AMPL_WIDTH),
conv_std_logic_vector(1847,AMPL_WIDTH),
conv_std_logic_vector(1847,AMPL_WIDTH),
conv_std_logic_vector(1848,AMPL_WIDTH),
conv_std_logic_vector(1848,AMPL_WIDTH),
conv_std_logic_vector(1848,AMPL_WIDTH),
conv_std_logic_vector(1849,AMPL_WIDTH),
conv_std_logic_vector(1849,AMPL_WIDTH),
conv_std_logic_vector(1849,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1851,AMPL_WIDTH),
conv_std_logic_vector(1851,AMPL_WIDTH),
conv_std_logic_vector(1851,AMPL_WIDTH),
conv_std_logic_vector(1852,AMPL_WIDTH),
conv_std_logic_vector(1852,AMPL_WIDTH),
conv_std_logic_vector(1852,AMPL_WIDTH),
conv_std_logic_vector(1853,AMPL_WIDTH),
conv_std_logic_vector(1853,AMPL_WIDTH),
conv_std_logic_vector(1853,AMPL_WIDTH),
conv_std_logic_vector(1854,AMPL_WIDTH),
conv_std_logic_vector(1854,AMPL_WIDTH),
conv_std_logic_vector(1854,AMPL_WIDTH),
conv_std_logic_vector(1855,AMPL_WIDTH),
conv_std_logic_vector(1855,AMPL_WIDTH),
conv_std_logic_vector(1855,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1857,AMPL_WIDTH),
conv_std_logic_vector(1857,AMPL_WIDTH),
conv_std_logic_vector(1857,AMPL_WIDTH),
conv_std_logic_vector(1858,AMPL_WIDTH),
conv_std_logic_vector(1858,AMPL_WIDTH),
conv_std_logic_vector(1858,AMPL_WIDTH),
conv_std_logic_vector(1859,AMPL_WIDTH),
conv_std_logic_vector(1859,AMPL_WIDTH),
conv_std_logic_vector(1859,AMPL_WIDTH),
conv_std_logic_vector(1860,AMPL_WIDTH),
conv_std_logic_vector(1860,AMPL_WIDTH),
conv_std_logic_vector(1860,AMPL_WIDTH),
conv_std_logic_vector(1861,AMPL_WIDTH),
conv_std_logic_vector(1861,AMPL_WIDTH),
conv_std_logic_vector(1861,AMPL_WIDTH),
conv_std_logic_vector(1862,AMPL_WIDTH),
conv_std_logic_vector(1862,AMPL_WIDTH),
conv_std_logic_vector(1862,AMPL_WIDTH),
conv_std_logic_vector(1863,AMPL_WIDTH),
conv_std_logic_vector(1863,AMPL_WIDTH),
conv_std_logic_vector(1863,AMPL_WIDTH),
conv_std_logic_vector(1864,AMPL_WIDTH),
conv_std_logic_vector(1864,AMPL_WIDTH),
conv_std_logic_vector(1864,AMPL_WIDTH),
conv_std_logic_vector(1865,AMPL_WIDTH),
conv_std_logic_vector(1865,AMPL_WIDTH),
conv_std_logic_vector(1865,AMPL_WIDTH),
conv_std_logic_vector(1866,AMPL_WIDTH),
conv_std_logic_vector(1866,AMPL_WIDTH),
conv_std_logic_vector(1866,AMPL_WIDTH),
conv_std_logic_vector(1867,AMPL_WIDTH),
conv_std_logic_vector(1867,AMPL_WIDTH),
conv_std_logic_vector(1867,AMPL_WIDTH),
conv_std_logic_vector(1868,AMPL_WIDTH),
conv_std_logic_vector(1868,AMPL_WIDTH),
conv_std_logic_vector(1868,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1870,AMPL_WIDTH),
conv_std_logic_vector(1870,AMPL_WIDTH),
conv_std_logic_vector(1870,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1872,AMPL_WIDTH),
conv_std_logic_vector(1872,AMPL_WIDTH),
conv_std_logic_vector(1872,AMPL_WIDTH),
conv_std_logic_vector(1873,AMPL_WIDTH),
conv_std_logic_vector(1873,AMPL_WIDTH),
conv_std_logic_vector(1873,AMPL_WIDTH),
conv_std_logic_vector(1874,AMPL_WIDTH),
conv_std_logic_vector(1874,AMPL_WIDTH),
conv_std_logic_vector(1874,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1876,AMPL_WIDTH),
conv_std_logic_vector(1876,AMPL_WIDTH),
conv_std_logic_vector(1876,AMPL_WIDTH),
conv_std_logic_vector(1877,AMPL_WIDTH),
conv_std_logic_vector(1877,AMPL_WIDTH),
conv_std_logic_vector(1877,AMPL_WIDTH),
conv_std_logic_vector(1878,AMPL_WIDTH),
conv_std_logic_vector(1878,AMPL_WIDTH),
conv_std_logic_vector(1878,AMPL_WIDTH),
conv_std_logic_vector(1879,AMPL_WIDTH),
conv_std_logic_vector(1879,AMPL_WIDTH),
conv_std_logic_vector(1879,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1882,AMPL_WIDTH),
conv_std_logic_vector(1882,AMPL_WIDTH),
conv_std_logic_vector(1882,AMPL_WIDTH),
conv_std_logic_vector(1883,AMPL_WIDTH),
conv_std_logic_vector(1883,AMPL_WIDTH),
conv_std_logic_vector(1883,AMPL_WIDTH),
conv_std_logic_vector(1884,AMPL_WIDTH),
conv_std_logic_vector(1884,AMPL_WIDTH),
conv_std_logic_vector(1884,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1886,AMPL_WIDTH),
conv_std_logic_vector(1886,AMPL_WIDTH),
conv_std_logic_vector(1886,AMPL_WIDTH),
conv_std_logic_vector(1887,AMPL_WIDTH),
conv_std_logic_vector(1887,AMPL_WIDTH),
conv_std_logic_vector(1887,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1889,AMPL_WIDTH),
conv_std_logic_vector(1889,AMPL_WIDTH),
conv_std_logic_vector(1889,AMPL_WIDTH),
conv_std_logic_vector(1890,AMPL_WIDTH),
conv_std_logic_vector(1890,AMPL_WIDTH),
conv_std_logic_vector(1890,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1892,AMPL_WIDTH),
conv_std_logic_vector(1892,AMPL_WIDTH),
conv_std_logic_vector(1892,AMPL_WIDTH),
conv_std_logic_vector(1893,AMPL_WIDTH),
conv_std_logic_vector(1893,AMPL_WIDTH),
conv_std_logic_vector(1893,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1895,AMPL_WIDTH),
conv_std_logic_vector(1895,AMPL_WIDTH),
conv_std_logic_vector(1895,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1898,AMPL_WIDTH),
conv_std_logic_vector(1898,AMPL_WIDTH),
conv_std_logic_vector(1898,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1900,AMPL_WIDTH),
conv_std_logic_vector(1900,AMPL_WIDTH),
conv_std_logic_vector(1900,AMPL_WIDTH),
conv_std_logic_vector(1901,AMPL_WIDTH),
conv_std_logic_vector(1901,AMPL_WIDTH),
conv_std_logic_vector(1901,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1903,AMPL_WIDTH),
conv_std_logic_vector(1903,AMPL_WIDTH),
conv_std_logic_vector(1903,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1905,AMPL_WIDTH),
conv_std_logic_vector(1905,AMPL_WIDTH),
conv_std_logic_vector(1905,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1907,AMPL_WIDTH),
conv_std_logic_vector(1907,AMPL_WIDTH),
conv_std_logic_vector(1907,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1911,AMPL_WIDTH),
conv_std_logic_vector(1911,AMPL_WIDTH),
conv_std_logic_vector(1911,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1914,AMPL_WIDTH),
conv_std_logic_vector(1914,AMPL_WIDTH),
conv_std_logic_vector(1914,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1916,AMPL_WIDTH),
conv_std_logic_vector(1916,AMPL_WIDTH),
conv_std_logic_vector(1916,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1919,AMPL_WIDTH),
conv_std_logic_vector(1919,AMPL_WIDTH),
conv_std_logic_vector(1919,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1922,AMPL_WIDTH),
conv_std_logic_vector(1922,AMPL_WIDTH),
conv_std_logic_vector(1922,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1926,AMPL_WIDTH),
conv_std_logic_vector(1926,AMPL_WIDTH),
conv_std_logic_vector(1926,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1931,AMPL_WIDTH),
conv_std_logic_vector(1931,AMPL_WIDTH),
conv_std_logic_vector(1931,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library zpuino;
use zpuino.pad.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_Analog is
port (
miso : out std_logic;
mosi : in std_logic;
sck : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_Analog;
architecture Behavioral of Wing_Analog is
signal T: std_logic;
begin
T <= '0';
--Outputs
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= sck;
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= mosi;
--Inputs (be sure to leave the output enabled)
miso <= wt_miso(6) when T = '0' else 'Z';
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity DAS_RF is
port(
clock : in vl_logic;
data : in vl_logic_vector(15 downto 0);
rdaddress : in vl_logic_vector(13 downto 0);
wraddress : in vl_logic_vector(13 downto 0);
wren : in vl_logic;
q : out vl_logic_vector(15 downto 0)
);
end DAS_RF;
|
library verilog;
use verilog.vl_types.all;
entity DAS_RF is
port(
clock : in vl_logic;
data : in vl_logic_vector(15 downto 0);
rdaddress : in vl_logic_vector(13 downto 0);
wraddress : in vl_logic_vector(13 downto 0);
wren : in vl_logic;
q : out vl_logic_vector(15 downto 0)
);
end DAS_RF;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:58:46 04/02/2017
-- Design Name:
-- Module Name: D:/VHDL/UART_TEST/tb_top.vhd
-- Project Name: UART_TEST
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_top IS
END tb_top;
ARCHITECTURE behavior OF tb_top IS
constant max_counter: natural := (11538500 / 9600) - 1;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top
PORT(
clk_50mhz : IN std_logic;
rs232_dce_txd : OUT std_logic;
rs232_dce_rxd : IN std_logic;
led : OUT std_logic_vector(7 downto 0);
buttons : IN std_logic_vector(7 downto 0);
rot_a: in std_logic;
rot_b: in std_logic;
rot_center: in std_logic
);
END COMPONENT;
--Inputs
signal clk_50mhz : std_logic := '0';
signal rs232_dce_rxd : std_logic := '0';
signal buttons : std_logic_vector(7 downto 0) := (others => '0');
signal rot_center : std_logic := '0';
signal rot_a : std_logic := '0';
signal rot_b : std_logic := '1';
--Outputs
signal rs232_dce_txd : std_logic;
signal led : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_50mhz_period : time := 20 ns;
type state_type is (
s_start,
s_data,
s_stop
);
signal state: state_type := s_start;
type bufer_type is array (0 to 2**15) of std_logic_vector(7 downto 0);
signal buff: bufer_type := (
-- (X"AA"),
-- (X"55"),
-- (X"00"),
-- (X"08"),
-- (X"01"),
-- (X"81"),
-- (X"81"),
-- (X"0F"),
-- (X"F0"),
-- (X"3C"),
-- (X"C3"),
-- (X"7E"),
-- (X"E7"),
-- (X"01"),
-- (X"02"),
-- (X"03"),
(X"AA"),
(X"55"),
(X"00"),
(X"05"),
(X"01"),
(X"01"),
(X"02"),
(X"03"),
(X"04"),
(X"05"),
(X"AA"),
(X"55"),
(X"00"),
(X"01"),
(X"06"),
(X"58"),
(X"AA"),
(X"55"),
(X"00"),
(X"02"),
(X"06"),
(X"F0"),
(X"58"),
(X"AA"),
(X"55"),
(X"00"),
(X"01"),
(X"06"),
(X"FA"),
others => (others => '0')
);
signal buff_out: bufer_type := (others => (others => '0'));
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top PORT MAP (
clk_50mhz => clk_50mhz,
rs232_dce_txd => rs232_dce_txd,
rs232_dce_rxd => rs232_dce_rxd,
led => led,
buttons => buttons,
rot_a => rot_a,
rot_b => rot_b,
rot_center => rot_center
);
-- Clock process definitions
clk_50mhz_process :process
begin
clk_50mhz <= '0';
wait for clk_50mhz_period/2;
clk_50mhz <= '1';
wait for clk_50mhz_period/2;
end process;
-- Stimulus process
stim_proc: process(clk_50mhz)
variable bit_i: integer := 0;
variable i: integer := 0;
variable bit_counter: integer := max_counter;
begin
if rising_edge(clk_50mhz) then
if i < 29 then
case state is
when s_start =>
rs232_dce_rxd <= '0';
state <= s_data;
bit_counter := max_counter-1 + ((max_counter-1) / 2) - 1;
report "bitcounter = "&integer'image(bit_counter);
when s_data =>
if bit_counter = 0 then
bit_counter := max_counter - 2;
if bit_i = 8 then
report "next byte " severity note;
bit_i := 0;
i := i + 1;
state <= s_stop;
rs232_dce_rxd <= '1';
else
rs232_dce_rxd <= buff(i)(bit_i);
bit_i := bit_i + 1;
end if;
else
bit_counter := bit_counter - 1;
end if;
when s_stop =>
if bit_counter = 0 then
state <= s_start;
else
bit_counter := bit_counter - 1;
end if;
end case;
else
rot_center <= '0';
end if;
end if;
end process;
--buttons <= X"F0";
END;
|
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