content stringlengths 1 1.04M ⌀ |
|---|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_ok_4_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY InterfaceWithVHDLUnconstrainedArrayImportedType2 IS
GENERIC(
SIZE_X : INTEGER := 3
);
PORT(
din_0 : IN UNSIGNED(7 DOWNTO 0);
din_1 : IN UNSIGNED(7 DOWNTO 0);
din_2 : IN UNSIGNED(7 DOWNTO 0);
d... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity U232C_RECV is
generic (
WTIME : std_logic_vector(15 downto 0) := x"1B17");
port (
CLK : in std_logic;
OK : in std_logic;
RX : in std_logic;
DATA : out std_logic_vector (7 downto 0);
RECVED : out std_logic);
end U232C_RECV;... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (c) 2017 Stephan Nolting / IMS, Leibniz Univ. Hannover
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software wi... |
-- Copyright (c) 2017 Stephan Nolting / IMS, Leibniz Univ. Hannover
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software wi... |
-- wasca_reset_controller_0.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_reset_controller_0 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "both";
SYNC_DEPTH : intege... |
-- wasca_reset_controller_0.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_reset_controller_0 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "both";
SYNC_DEPTH : intege... |
-- wasca_reset_controller_0.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_reset_controller_0 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "both";
SYNC_DEPTH : intege... |
-- wasca_reset_controller_0.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_reset_controller_0 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "both";
SYNC_DEPTH : intege... |
-- wasca_reset_controller_0.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_reset_controller_0 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "both";
SYNC_DEPTH : intege... |
-- wasca_reset_controller_0.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_reset_controller_0 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "both";
SYNC_DEPTH : intege... |
-- NEED RESULT: ARCH00555: Signal declarations - composite globally static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-----------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:08:15 11/19/2013
-- Design Name:
-- Module Name: HalfAdder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:04:25 05/29/2014
-- Design Name:
-- Module Name: FSM1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: ... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- Design : Register array acting as data cache
-- Project : Tomasulo Processor
-- Author : Rohit Goel
-- Company : University of Southern California
-- Following is the VHDL code for a dual-port RAM with a write clock.
-- There is... |
---- Memory ------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.processor_functions.all;
------------------------------------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : tb_wave_gen
-- Project : Exercise 06
-------------------------------------------------------------------------------
-- File : tb_wave_gen.vhd
-- Author : Erno Salminen <ege@tiibetinhanhi.cs.tut.fi>
-- Company :
--... |
-------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric buffered packet sink
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : xwb_fabric_sink.vhd
-- Author : Tomasz Wlost... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\Shifter_8_bit.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- -----------------------------------------... |
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- ADS1281 filter package.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
... |
------------------------------------------------------------------------------
-- @file adder_full.vhd
-- @brief Implementes a simple 1 bit half adder that can be used to make full
-- adders and vector adders.
-- @see adder_full_tb
-------------------------------------------------------------------------------
librar... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- implements n-th order prbs with common polynomials y = x^n + x^(n-1) + 1
entity prbs is
generic (
n : positive;
width : positive
);
port (
clk : in std_logic;
clk_en : in std_logic;
rst : in std_logic;
q : out std_logic_vector(wi... |
entity tb_if02 is
end tb_if02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_if02 is
signal i, o: std_logic_vector(7 downto 0);
signal s : std_logic;
begin
dut: entity work.if02
port map (i, s, o);
process
begin
i <= b"01011010";
s <= '0';
wait for 1 ns;
assert o =... |
-- $Id$
--
------------------------------------------------------------------------------
-- Package Name: avmblib
-- Description: Avnet MicroBoard components
--
-- Dependencies: -
-- Tool versions: xst 13.4; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-24 ??? 1.0 ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
entity ram is
generic(
depth : integer;
width : integer
);
port(
ctrl : in ctrl_t;
read_addr ... |
entity top2 is
generic (
ok : boolean := false
);
port (
clk : in bit;
inp : in bit;
outp : out bit);
end;
architecture beh of top2 is
begin
assert ok report "my assert message";
outp <= inp;
end beh;
|
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code mu... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_eba_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-... |
------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
----... |
----------------------------------------------------------------------------------
-- Create Date: 15:31:16 04/11/2017
-- Module Name: incrementador - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity incrementador is... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
termina... |
library ieee;
use ieee.std_logic_1164.all;
entity sign is
port(a: in std_logic_vector(15 downto 0);
y: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of sign is
begin
process (a)
variable v : std_logic_vector(15 downto 0);
begin
if (a(0)='1') t... |
library ieee;
use ieee.std_logic_1164.all;
entity sign is
port(a: in std_logic_vector(15 downto 0);
y: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of sign is
begin
process (a)
variable v : std_logic_vector(15 downto 0);
begin
if (a(0)='1') t... |
library ieee;
use ieee.std_logic_1164.all;
entity sign is
port(a: in std_logic_vector(15 downto 0);
y: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of sign is
begin
process (a)
variable v : std_logic_vector(15 downto 0);
begin
if (a(0)='1') t... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natu... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natu... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natu... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natu... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natu... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natu... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natu... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natu... |
-- NEED RESULT: ARCH00249: All tests for Section 2.2 passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-----------------------------------------------------------------------------... |
--
-- 6502 compatible microprocessor core
--
-- Version : 0245
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redist... |
-- Inertial assignment
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture arch of ENT00001_Test_Bench is
signal i : integer := 0;
signal o1 : integer := 0;
signal o2 : integer := 0;
begin
terminator : process
begin
i <= 1 after 5 us, 0 after 10 us, 1 after 20 ... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright... |
architecture RTL of FIFO is
attribute coordinate of comp_1:component is (0.0, 17.5);
ATTRIBUTE coordinate OF comp_1:component IS (0.0, 17.5);
begin
end architecture RTL;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 22:04:02 2017
-- Host : DarkCube running 64-bit major releas... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library verilog;
use verilog.vl_types.all;
entity maquina is
port(
SW : in vl_logic_vector(4 downto 0);
LEDG : out vl_logic_vector(0 downto 0);
LEDR : out vl_logic_vector(0 downto 0);
HEX0 : out vl_logic_vector(6 downto 0);
... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
-- This is the top-level of the fp68030 design, instantiating
-- all top IP blocks, connecting things to external FPGA pins
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <ccl@xunit.de>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redis... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:50:17 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 14;
constant AMPL_WIDTH : integer := 12;
type lut_type is arr... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 14;
constant AMPL_WIDTH : integer := 12;
type lut_type is arr... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
library verilog;
use verilog.vl_types.all;
entity DAS_RF is
port(
clock : in vl_logic;
data : in vl_logic_vector(15 downto 0);
rdaddress : in vl_logic_vector(13 downto 0);
wraddress : in vl_logic_vector(13 downto 0);
wren ... |
library verilog;
use verilog.vl_types.all;
entity DAS_RF is
port(
clock : in vl_logic;
data : in vl_logic_vector(15 downto 0);
rdaddress : in vl_logic_vector(13 downto 0);
wraddress : in vl_logic_vector(13 downto 0);
wren ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:58:46 04/02/2017
-- Design Name:
-- Module Name: D:/VHDL/UART_TEST/tb_top.vhd
-- Project Name: UART_TEST
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Be... |
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