content stringlengths 1 1.04M ⌀ |
|---|
--------------------------------------------------------------------------------
-- obj_code_pkg.vhdl -- Application object code in vhdl constant string format.
--------------------------------------------------------------------------------
-- Built for project 'CPU tester'.
-------------------------------------------... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:30:03 02/06/2015
-- Design Name:
-- Module Name: addN_testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenc... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:30:03 02/06/2015
-- Design Name:
-- Module Name: addN_testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenc... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
term... |
-------------------------------------------------------------------------------------
-- FILE NAME : shift_bytes.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
-----------------------------------------------... |
-- DDR controller
constant CFG_DDR2SP : integer := CONFIG_DDR2SP;
constant CFG_DDR2SP_INIT : integer := CONFIG_DDR2SP_INIT;
constant CFG_DDR2SP_FREQ : integer := CONFIG_DDR2SP_FREQ;
constant CFG_DDR2SP_DATAWIDTH : integer := CONFIG_DDR2SP_DATAWIDTH;
constant CFG_DDR2SP_COL : integ... |
-- DDR controller
constant CFG_DDR2SP : integer := CONFIG_DDR2SP;
constant CFG_DDR2SP_INIT : integer := CONFIG_DDR2SP_INIT;
constant CFG_DDR2SP_FREQ : integer := CONFIG_DDR2SP_FREQ;
constant CFG_DDR2SP_DATAWIDTH : integer := CONFIG_DDR2SP_DATAWIDTH;
constant CFG_DDR2SP_COL : integ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tp1 is
port (
clk: in std_logic
);
end;
architecture tp1_arq of tp1 is
begin
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLAH16bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CarryIn: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC;
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
SomaResult:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END CLAH16bits;
ARCHITECTURE strc_CLAH16bits of CLAH16bits is
... |
-- modelled according to IEEE Std 1801-2015, 11.2
package upf is
function supply_on (
constant supply_name : string;
constant voltage : real)
return boolean;
function supply_partial_on (
constant supply_name : string;
constant voltage : real)
return boolean;
function supply_off... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This fil... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... |
entity var4 is
end;
use work.pkg.all;
architecture behav of var4 is
begin
process
variable v1 : rec_4;
variable v2 : rec_4dyn;
begin
v2 := v1;
wait;
end process;
end behav;
|
entity var4 is
end;
use work.pkg.all;
architecture behav of var4 is
begin
process
variable v1 : rec_4;
variable v2 : rec_4dyn;
begin
v2 := v1;
wait;
end process;
end behav;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity real_time_clock_tb is
end;
architecture tb of real_time_clock_tb is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal req : t_io_re... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity real_time_clock_tb is
end;
architecture tb of real_time_clock_tb is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal req : t_io_re... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity real_time_clock_tb is
end;
architecture tb of real_time_clock_tb is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal req : t_io_re... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity real_time_clock_tb is
end;
architecture tb of real_time_clock_tb is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal req : t_io_re... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity real_time_clock_tb is
end;
architecture tb of real_time_clock_tb is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal req : t_io_re... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity projeto_2 is
port (
entrada : in std_logic_vector (2 downto 0) := "000";
reset : in std_logic := '0';
enable : in std_logic := '1';
clk : in std_logic;
saida : out std_logic_vector (2 downto 0)
);
end projeto_2;
architecture B... |
entity FIFO is
end entity FIFO;
--vhdl_comp_off
entity FIFO is
--vhdl_comp_on
entity FIFO is
end entity;
|
--************************************************************************************************
-- PM_FETCH_DEC(internal module) for AVR core
-- Version 2.6! (Special version for the JTAG OCD)
-- Designed by Ruslan Lepetenok 14.11.2001
-- Modified 31.05.06
-- Modification:
-- Registered ramre/ramwe output... |
--************************************************************************************************
-- PM_FETCH_DEC(internal module) for AVR core
-- Version 2.6! (Special version for the JTAG OCD)
-- Designed by Ruslan Lepetenok 14.11.2001
-- Modified 31.05.06
-- Modification:
-- Registered ramre/ramwe output... |
--************************************************************************************************
-- PM_FETCH_DEC(internal module) for AVR core
-- Version 2.6! (Special version for the JTAG OCD)
-- Designed by Ruslan Lepetenok 14.11.2001
-- Modified 31.05.06
-- Modification:
-- Registered ramre/ramwe output... |
--************************************************************************************************
-- PM_FETCH_DEC(internal module) for AVR core
-- Version 2.6! (Special version for the JTAG OCD)
-- Designed by Ruslan Lepetenok 14.11.2001
-- Modified 31.05.06
-- Modification:
-- Registered ramre/ramwe output... |
entity const4 is
end entity;
architecture test of const4 is
type int2d is array (natural range <>, natural range <>) of integer;
constant c : int2d := (
( 0, 3, 4, 5 ),
( 6, 7, 8, 9 ) );
begin
process is
begin
assert c'length(1) = 2;
assert c'length(2) = 4;
a... |
entity const4 is
end entity;
architecture test of const4 is
type int2d is array (natural range <>, natural range <>) of integer;
constant c : int2d := (
( 0, 3, 4, 5 ),
( 6, 7, 8, 9 ) );
begin
process is
begin
assert c'length(1) = 2;
assert c'length(2) = 4;
a... |
entity const4 is
end entity;
architecture test of const4 is
type int2d is array (natural range <>, natural range <>) of integer;
constant c : int2d := (
( 0, 3, 4, 5 ),
( 6, 7, 8, 9 ) );
begin
process is
begin
assert c'length(1) = 2;
assert c'length(2) = 4;
a... |
entity const4 is
end entity;
architecture test of const4 is
type int2d is array (natural range <>, natural range <>) of integer;
constant c : int2d := (
( 0, 3, 4, 5 ),
( 6, 7, 8, 9 ) );
begin
process is
begin
assert c'length(1) = 2;
assert c'length(2) = 4;
a... |
entity const4 is
end entity;
architecture test of const4 is
type int2d is array (natural range <>, natural range <>) of integer;
constant c : int2d := (
( 0, 3, 4, 5 ),
( 6, 7, 8, 9 ) );
begin
process is
begin
assert c'length(1) = 2;
assert c'length(2) = 4;
a... |
-- VHDL Entity R6502_TC.Reg_SP.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:42:53 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity Reg_SP is
port(
a... |
-- VHDL Entity R6502_TC.Reg_SP.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:42:53 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity Reg_SP is
port(
a... |
library verilog;
use verilog.vl_types.all;
entity inicial is
generic(
A : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0);
B : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi1);
C : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi0);
D : vl_logic_v... |
-------------------------------------------------------------------------------
-- uartlite_tx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xi... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_m_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 06:48:17 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity somadorSubtrator is
Port ( a0 : in STD_LOGIC;
a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
b0 : in STD_LOGIC;
b1 : in STD_LOGIC;
b2 : in STD_LOGIC;
sel : in STD_LOGIC;
s0 : out STD_LOGIC;
... |
-------------------------------------------------------------------------------
-- Title : Goertel Muxes
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Goertel Muxes
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
------------------------------------------------------------------------... |
-- NEED RESULT: ARCH00337.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: A... |
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cordic_lib.all;
library floatfixlib;
use floatfixlib.float_pkg.all;
entity tester_ram_interna is
generic(
N_BITS_COORD : integer := 32 --- REVISAR
);
port(
clk_i: in std_logic; -- Clock general
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FeqDiv is
Generic( width : integer );
Port( clkIn : in STD_LOGIC;
clkOut : out STD_LOGIC);
end FeqDiv;
architecture Behavioral of FeqDiv is
signal inner : STD_LOGIC_VECTOR(1 to width);
attribute KEEP : string;
attribute KEEP of cl... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-------------------------------------------------------------------------------
-- xps_intc_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_intc_v2_00_a;
use xps_intc_v2_00_... |
architecture rtl of fifo is
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is RECORD
a : std_logic;
b : std_logic;
end record t_record;
begin
end architecture rtl;
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_host_controller
-- Date:2015-01-18
-- Author: Gideon
-- Description:
--------------------------------------------------------------------------------
library ieee;
use... |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_host_controller
-- Date:2015-01-18
-- Author: Gideon
-- Description:
--------------------------------------------------------------------------------
library ieee;
use... |
library IEEE;
use IEEE.std_logic_1164.all;
entity SCIT1 is
port (A, B, CIN : in std_logic;
COUT, S : out std_logic
);
end entity SCIT1;
architecture SCIT1_BODY of SCIT1 is
begin
VYSTUP : process (A, B, CIN)
begin
S <= A xor B xor CIN after 2 ns;
end process;
PRENOS : process (A, B, CIN)
begin
CO... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
------------------------------------------------------------------------------
---- ----
---- Lattuino CPU configuration ----
---- ----
----... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.amba.all;
use work.iface.all;
entity ahbtest is
port (
rst : in std_logic;
clk : in clk_type;
-- peripheral bus
-- pbi : in APB_Slv_In_Type; -- peripheral bus in
-- ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.amba.all;
use work.iface.all;
entity ahbtest is
port (
rst : in std_logic;
clk : in clk_type;
-- peripheral bus
-- pbi : in APB_Slv_In_Type; -- peripheral bus in
-- ... |
entity t1 is
err;
end t1;
|
entity t1 is
err;
end t1;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity stack_in_MUX is
port(sel : in std_logic_vector(2 downto 0);
ctl_immediate : in std_logic_vector(31 downto 0);
ALU_result : in std_logic... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity stack_in_MUX is
port(sel : in std_logic_vector(2 downto 0);
ctl_immediate : in std_logic_vector(31 downto 0);
ALU_result : in std_logic... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMIN... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:27:55 2017
-- Host : GILAMONSTER running 64-bit major rel... |
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