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-------------------------------------------------------------------------------- -- obj_code_pkg.vhdl -- Application object code in vhdl constant string format. -------------------------------------------------------------------------------- -- Built for project 'CPU tester'. -------------------------------------------------------------------------------- -- This file contains object code in the form of a VHDL byte table constant. -- This constant can be used to initialize FPGA memories for synthesis or -- simulation. -- Note that the object code is stored as a plain byte table in byte address -- order. This table knows nothing of data endianess and can be used to -- initialize 32-, 16- or 8-bit-wide memory -- memory initialization functions -- can be found in package mips_pkg. -------------------------------------------------------------------------------- -- This source file may be used and distributed without -- restriction provided that this copyright statement is not -- removed from the file and that any derivative work contains -- the original copyright notice and the associated disclaimer. -- -- This source file is free software; you can redistribute it -- and/or modify it under the terms of the GNU Lesser General -- Public License as published by the Free Software Foundation; -- either version 2.1 of the License, or (at your option) any -- later version. -- -- This source is distributed in the hope that it will be -- useful, but WITHOUT ANY WARRANTY; without even the implied -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- PURPOSE. See the GNU Lesser General Public License for more -- details. -- -- You should have received a copy of the GNU Lesser General -- Public License along with this source; if not, download it -- from http://www.opencores.org/lgpl.shtml -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.ION_INTERFACES_PKG.all; use work.ION_INTERNAL_PKG.all; package OBJ_CODE_PKG is -- Simulation or synthesis parameters ------------------------------------------ constant CODE_MEM_SIZE : integer := 4096; constant DATA_MEM_SIZE : integer := 1024; -- Memory initialization data -------------------------------------------------- constant OBJ_CODE : t_obj_code(0 to 10563) := ( X"10", X"00", X"00", X"74", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", 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X"36", X"9b", X"00", X"00", X"03", X"e0", X"00", X"08", X"36", X"bb", X"00", X"00", X"03", X"e0", X"00", X"08", X"36", X"db", X"00", X"00", X"03", X"e0", X"00", X"08", X"36", X"fb", X"00", X"00", X"03", X"e0", X"00", X"08", X"37", X"1b", X"00", X"00", X"03", X"e0", X"00", X"08", X"37", X"3b", X"00", X"00", X"03", X"e0", X"00", X"08", X"37", X"5b", X"00", X"00", X"03", X"e0", X"00", X"08", X"37", X"7b", X"00", X"00", X"03", X"e0", X"00", X"08", X"37", X"9a", X"00", X"00", X"03", X"e0", X"00", X"08", X"8f", X"bb", X"ff", X"f0", X"03", X"e0", X"00", X"08", X"37", X"db", X"00", X"00", X"03", X"e0", X"00", X"08", X"8f", X"bb", X"ff", X"ec" ); constant INIT_DATA : t_obj_code(0 to 0) := (others => X"00"); end package OBJ_CODE_PKG;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_explutpos IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_explutpos; ARCHITECTURE rtl OF dp_explutpos IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(1023,11); WHEN "0000000001" => manhi <= conv_std_logic_vector(6025384,24); manlo <= conv_std_logic_vector(185882474,28); exponent <= conv_std_logic_vector(1024,11); WHEN "0000000010" => manhi <= conv_std_logic_vector(14214731,24); manlo <= conv_std_logic_vector(148168110,28); exponent <= conv_std_logic_vector(1025,11); WHEN "0000000011" => manhi <= conv_std_logic_vector(4283995,24); manlo <= conv_std_logic_vector(258978054,28); exponent <= conv_std_logic_vector(1027,11); WHEN "0000000100" => manhi <= conv_std_logic_vector(11847938,24); manlo <= conv_std_logic_vector(237451864,28); exponent <= conv_std_logic_vector(1028,11); WHEN "0000000101" => manhi <= conv_std_logic_vector(2675593,24); manlo <= conv_std_logic_vector(158348175,28); exponent <= conv_std_logic_vector(1030,11); WHEN "0000000110" => manhi <= conv_std_logic_vector(9661893,24); manlo <= conv_std_logic_vector(110149775,28); exponent <= conv_std_logic_vector(1031,11); WHEN "0000000111" => manhi <= conv_std_logic_vector(1190021,24); manlo <= conv_std_logic_vector(179232170,28); exponent <= conv_std_logic_vector(1033,11); WHEN "0000001000" => manhi <= conv_std_logic_vector(7642791,24); manlo <= conv_std_logic_vector(222760046,28); exponent <= conv_std_logic_vector(1034,11); WHEN "0000001001" => manhi <= conv_std_logic_vector(16413015,24); manlo <= conv_std_logic_vector(205983618,28); exponent <= conv_std_logic_vector(1035,11); WHEN "0000001010" => manhi <= conv_std_logic_vector(5777884,24); manlo <= conv_std_logic_vector(261424480,28); exponent <= conv_std_logic_vector(1037,11); WHEN "0000001011" => manhi <= conv_std_logic_vector(13878344,24); manlo <= conv_std_logic_vector(149835647,28); exponent <= conv_std_logic_vector(1038,11); WHEN "0000001100" => manhi <= conv_std_logic_vector(4055397,24); manlo <= conv_std_logic_vector(80968858,28); exponent <= conv_std_logic_vector(1040,11); WHEN "0000001101" => manhi <= conv_std_logic_vector(11537241,24); manlo <= conv_std_logic_vector(23775573,28); exponent <= conv_std_logic_vector(1041,11); WHEN "0000001110" => manhi <= conv_std_logic_vector(2464452,24); manlo <= conv_std_logic_vector(146736599,28); exponent <= conv_std_logic_vector(1043,11); WHEN "0000001111" => manhi <= conv_std_logic_vector(9374922,24); manlo <= conv_std_logic_vector(263006855,28); exponent <= conv_std_logic_vector(1044,11); WHEN "0000010000" => manhi <= conv_std_logic_vector(995005,24); manlo <= conv_std_logic_vector(11010080,28); exponent <= conv_std_logic_vector(1046,11); WHEN "0000010001" => manhi <= conv_std_logic_vector(7377736,24); manlo <= conv_std_logic_vector(202286329,28); exponent <= conv_std_logic_vector(1047,11); WHEN "0000010010" => manhi <= conv_std_logic_vector(16052768,24); manlo <= conv_std_logic_vector(152649917,28); exponent <= conv_std_logic_vector(1048,11); WHEN "0000010011" => manhi <= conv_std_logic_vector(5533071,24); manlo <= conv_std_logic_vector(166536930,28); exponent <= conv_std_logic_vector(1050,11); WHEN "0000010100" => manhi <= conv_std_logic_vector(13545608,24); manlo <= conv_std_logic_vector(191424516,28); exponent <= conv_std_logic_vector(1051,11); WHEN "0000010101" => manhi <= conv_std_logic_vector(3829279,24); manlo <= conv_std_logic_vector(228519165,28); exponent <= conv_std_logic_vector(1053,11); WHEN "0000010110" => manhi <= conv_std_logic_vector(11229915,24); manlo <= conv_std_logic_vector(163853824,28); exponent <= conv_std_logic_vector(1054,11); WHEN "0000010111" => manhi <= conv_std_logic_vector(2255603,24); manlo <= conv_std_logic_vector(61996481,28); exponent <= conv_std_logic_vector(1056,11); WHEN "0000011000" => manhi <= conv_std_logic_vector(9091067,24); manlo <= conv_std_logic_vector(88563639,28); exponent <= conv_std_logic_vector(1057,11); WHEN "0000011001" => manhi <= conv_std_logic_vector(802105,24); manlo <= conv_std_logic_vector(34169545,28); exponent <= conv_std_logic_vector(1059,11); WHEN "0000011010" => manhi <= conv_std_logic_vector(7115558,24); manlo <= conv_std_logic_vector(157969244,28); exponent <= conv_std_logic_vector(1060,11); WHEN "0000011011" => manhi <= conv_std_logic_vector(15696431,24); manlo <= conv_std_logic_vector(133591837,28); exponent <= conv_std_logic_vector(1061,11); WHEN "0000011100" => manhi <= conv_std_logic_vector(5290915,24); manlo <= conv_std_logic_vector(127285146,28); exponent <= conv_std_logic_vector(1063,11); WHEN "0000011101" => manhi <= conv_std_logic_vector(13216484,24); manlo <= conv_std_logic_vector(103923798,28); exponent <= conv_std_logic_vector(1064,11); WHEN "0000011110" => manhi <= conv_std_logic_vector(3605616,24); manlo <= conv_std_logic_vector(183249133,28); exponent <= conv_std_logic_vector(1066,11); WHEN "0000011111" => manhi <= conv_std_logic_vector(10925925,24); manlo <= conv_std_logic_vector(227336045,28); exponent <= conv_std_logic_vector(1067,11); WHEN "0000100000" => manhi <= conv_std_logic_vector(2049020,24); manlo <= conv_std_logic_vector(206267948,28); exponent <= conv_std_logic_vector(1069,11); WHEN "0000100001" => manhi <= conv_std_logic_vector(8810292,24); manlo <= conv_std_logic_vector(175265666,28); exponent <= conv_std_logic_vector(1070,11); WHEN "0000100010" => manhi <= conv_std_logic_vector(611298,24); manlo <= conv_std_logic_vector(255467255,28); exponent <= conv_std_logic_vector(1072,11); WHEN "0000100011" => manhi <= conv_std_logic_vector(6856226,24); manlo <= conv_std_logic_vector(29134171,28); exponent <= conv_std_logic_vector(1073,11); WHEN "0000100100" => manhi <= conv_std_logic_vector(15343962,24); manlo <= conv_std_logic_vector(30543222,28); exponent <= conv_std_logic_vector(1074,11); WHEN "0000100101" => manhi <= conv_std_logic_vector(5051387,24); manlo <= conv_std_logic_vector(186253338,28); exponent <= conv_std_logic_vector(1076,11); WHEN "0000100110" => manhi <= conv_std_logic_vector(12890932,24); manlo <= conv_std_logic_vector(102222951,28); exponent <= conv_std_logic_vector(1077,11); WHEN "0000100111" => manhi <= conv_std_logic_vector(3384381,24); manlo <= conv_std_logic_vector(42116377,28); exponent <= conv_std_logic_vector(1079,11); WHEN "0000101000" => manhi <= conv_std_logic_vector(10625235,24); manlo <= conv_std_logic_vector(158954218,28); exponent <= conv_std_logic_vector(1080,11); WHEN "0000101001" => manhi <= conv_std_logic_vector(1844680,24); manlo <= conv_std_logic_vector(148858978,28); exponent <= conv_std_logic_vector(1082,11); WHEN "0000101010" => manhi <= conv_std_logic_vector(8532565,24); manlo <= conv_std_logic_vector(136319321,28); exponent <= conv_std_logic_vector(1083,11); WHEN "0000101011" => manhi <= conv_std_logic_vector(422563,24); manlo <= conv_std_logic_vector(211728497,28); exponent <= conv_std_logic_vector(1085,11); WHEN "0000101100" => manhi <= conv_std_logic_vector(6599708,24); manlo <= conv_std_logic_vector(114522162,28); exponent <= conv_std_logic_vector(1086,11); WHEN "0000101101" => manhi <= conv_std_logic_vector(14995318,24); manlo <= conv_std_logic_vector(117328318,28); exponent <= conv_std_logic_vector(1087,11); WHEN "0000101110" => manhi <= conv_std_logic_vector(4814459,24); manlo <= conv_std_logic_vector(201622499,28); exponent <= conv_std_logic_vector(1089,11); WHEN "0000101111" => manhi <= conv_std_logic_vector(12568913,24); manlo <= conv_std_logic_vector(246987638,28); exponent <= conv_std_logic_vector(1090,11); WHEN "0000110000" => manhi <= conv_std_logic_vector(3165546,24); manlo <= conv_std_logic_vector(248128843,28); exponent <= conv_std_logic_vector(1092,11); WHEN "0000110001" => manhi <= conv_std_logic_vector(10327809,24); manlo <= conv_std_logic_vector(8929872,28); exponent <= conv_std_logic_vector(1093,11); WHEN "0000110010" => manhi <= conv_std_logic_vector(1642558,24); manlo <= conv_std_logic_vector(67636037,28); exponent <= conv_std_logic_vector(1095,11); WHEN "0000110011" => manhi <= conv_std_logic_vector(8257852,24); manlo <= conv_std_logic_vector(219235425,28); exponent <= conv_std_logic_vector(1096,11); WHEN "0000110100" => manhi <= conv_std_logic_vector(235877,24); manlo <= conv_std_logic_vector(42862412,28); exponent <= conv_std_logic_vector(1098,11); WHEN "0000110101" => manhi <= conv_std_logic_vector(6345974,24); manlo <= conv_std_logic_vector(265996080,28); exponent <= conv_std_logic_vector(1099,11); WHEN "0000110110" => manhi <= conv_std_logic_vector(14650458,24); manlo <= conv_std_logic_vector(253213243,28); exponent <= conv_std_logic_vector(1100,11); WHEN "0000110111" => manhi <= conv_std_logic_vector(4580103,24); manlo <= conv_std_logic_vector(114693785,28); exponent <= conv_std_logic_vector(1102,11); WHEN "0000111000" => manhi <= conv_std_logic_vector(12250390,24); manlo <= conv_std_logic_vector(174984615,28); exponent <= conv_std_logic_vector(1103,11); WHEN "0000111001" => manhi <= conv_std_logic_vector(2949087,24); manlo <= conv_std_logic_vector(247325089,28); exponent <= conv_std_logic_vector(1105,11); WHEN "0000111010" => manhi <= conv_std_logic_vector(10033610,24); manlo <= conv_std_logic_vector(200264553,28); exponent <= conv_std_logic_vector(1106,11); WHEN "0000111011" => manhi <= conv_std_logic_vector(1442629,24); manlo <= conv_std_logic_vector(211375075,28); exponent <= conv_std_logic_vector(1108,11); WHEN "0000111100" => manhi <= conv_std_logic_vector(7986121,24); manlo <= conv_std_logic_vector(231029862,28); exponent <= conv_std_logic_vector(1109,11); WHEN "0000111101" => manhi <= conv_std_logic_vector(51216,24); manlo <= conv_std_logic_vector(222707863,28); exponent <= conv_std_logic_vector(1111,11); WHEN "0000111110" => manhi <= conv_std_logic_vector(6094995,24); manlo <= conv_std_logic_vector(155999272,28); exponent <= conv_std_logic_vector(1112,11); WHEN "0000111111" => manhi <= conv_std_logic_vector(14309342,24); manlo <= conv_std_logic_vector(150013864,28); exponent <= conv_std_logic_vector(1113,11); WHEN "0001000000" => manhi <= conv_std_logic_vector(4348290,24); manlo <= conv_std_logic_vector(217421773,28); exponent <= conv_std_logic_vector(1115,11); WHEN "0001000001" => manhi <= conv_std_logic_vector(11935324,24); manlo <= conv_std_logic_vector(171597361,28); exponent <= conv_std_logic_vector(1116,11); WHEN "0001000010" => manhi <= conv_std_logic_vector(2734978,24); manlo <= conv_std_logic_vector(98553735,28); exponent <= conv_std_logic_vector(1118,11); WHEN "0001000011" => manhi <= conv_std_logic_vector(9742605,24); manlo <= conv_std_logic_vector(185429986,28); exponent <= conv_std_logic_vector(1119,11); WHEN "0001000100" => manhi <= conv_std_logic_vector(1244871,24); manlo <= conv_std_logic_vector(93685501,28); exponent <= conv_std_logic_vector(1121,11); WHEN "0001000101" => manhi <= conv_std_logic_vector(7717340,24); manlo <= conv_std_logic_vector(74048432,28); exponent <= conv_std_logic_vector(1122,11); WHEN "0001000110" => manhi <= conv_std_logic_vector(16514337,24); manlo <= conv_std_logic_vector(163855108,28); exponent <= conv_std_logic_vector(1123,11); WHEN "0001000111" => manhi <= conv_std_logic_vector(5846740,24); manlo <= conv_std_logic_vector(81895750,28); exponent <= conv_std_logic_vector(1125,11); WHEN "0001001000" => manhi <= conv_std_logic_vector(13971928,24); manlo <= conv_std_logic_vector(176088988,28); exponent <= conv_std_logic_vector(1126,11); WHEN "0001001001" => manhi <= conv_std_logic_vector(4118994,24); manlo <= conv_std_logic_vector(77780251,28); exponent <= conv_std_logic_vector(1128,11); WHEN "0001001010" => manhi <= conv_std_logic_vector(11623678,24); manlo <= conv_std_logic_vector(95871356,28); exponent <= conv_std_logic_vector(1129,11); WHEN "0001001011" => manhi <= conv_std_logic_vector(2523192,24); manlo <= conv_std_logic_vector(204213760,28); exponent <= conv_std_logic_vector(1131,11); WHEN "0001001100" => manhi <= conv_std_logic_vector(9454759,24); manlo <= conv_std_logic_vector(55860552,28); exponent <= conv_std_logic_vector(1132,11); WHEN "0001001101" => manhi <= conv_std_logic_vector(1049259,24); manlo <= conv_std_logic_vector(102861624,28); exponent <= conv_std_logic_vector(1134,11); WHEN "0001001110" => manhi <= conv_std_logic_vector(7451476,24); manlo <= conv_std_logic_vector(13367584,28); exponent <= conv_std_logic_vector(1135,11); WHEN "0001001111" => manhi <= conv_std_logic_vector(16152990,24); manlo <= conv_std_logic_vector(178012490,28); exponent <= conv_std_logic_vector(1136,11); WHEN "0001010000" => manhi <= conv_std_logic_vector(5601179,24); manlo <= conv_std_logic_vector(159708139,28); exponent <= conv_std_logic_vector(1138,11); WHEN "0001010001" => manhi <= conv_std_logic_vector(13638177,24); manlo <= conv_std_logic_vector(12864164,28); exponent <= conv_std_logic_vector(1139,11); WHEN "0001010010" => manhi <= conv_std_logic_vector(3892186,24); manlo <= conv_std_logic_vector(149492240,28); exponent <= conv_std_logic_vector(1141,11); WHEN "0001010011" => manhi <= conv_std_logic_vector(11315414,24); manlo <= conv_std_logic_vector(184620728,28); exponent <= conv_std_logic_vector(1142,11); WHEN "0001010100" => manhi <= conv_std_logic_vector(2313705,24); manlo <= conv_std_logic_vector(235697385,28); exponent <= conv_std_logic_vector(1144,11); WHEN "0001010101" => manhi <= conv_std_logic_vector(9170037,24); manlo <= conv_std_logic_vector(3974263,28); exponent <= conv_std_logic_vector(1145,11); WHEN "0001010110" => manhi <= conv_std_logic_vector(855770,24); manlo <= conv_std_logic_vector(158952336,28); exponent <= conv_std_logic_vector(1147,11); WHEN "0001010111" => manhi <= conv_std_logic_vector(7188497,24); manlo <= conv_std_logic_vector(138900038,28); exponent <= conv_std_logic_vector(1148,11); WHEN "0001011000" => manhi <= conv_std_logic_vector(15795565,24); manlo <= conv_std_logic_vector(209449517,28); exponent <= conv_std_logic_vector(1149,11); WHEN "0001011001" => manhi <= conv_std_logic_vector(5358284,24); manlo <= conv_std_logic_vector(54736896,28); exponent <= conv_std_logic_vector(1151,11); WHEN "0001011010" => manhi <= conv_std_logic_vector(13308047,24); manlo <= conv_std_logic_vector(264159588,28); exponent <= conv_std_logic_vector(1152,11); WHEN "0001011011" => manhi <= conv_std_logic_vector(3667840,24); manlo <= conv_std_logic_vector(160544132,28); exponent <= conv_std_logic_vector(1154,11); WHEN "0001011100" => manhi <= conv_std_logic_vector(11010496,24); manlo <= conv_std_logic_vector(245935181,28); exponent <= conv_std_logic_vector(1155,11); WHEN "0001011101" => manhi <= conv_std_logic_vector(2106492,24); manlo <= conv_std_logic_vector(206325441,28); exponent <= conv_std_logic_vector(1157,11); WHEN "0001011110" => manhi <= conv_std_logic_vector(8888405,24); manlo <= conv_std_logic_vector(53641237,28); exponent <= conv_std_logic_vector(1158,11); WHEN "0001011111" => manhi <= conv_std_logic_vector(664381,24); manlo <= conv_std_logic_vector(249887163,28); exponent <= conv_std_logic_vector(1160,11); WHEN "0001100000" => manhi <= conv_std_logic_vector(6928373,24); manlo <= conv_std_logic_vector(95946938,28); exponent <= conv_std_logic_vector(1161,11); WHEN "0001100001" => manhi <= conv_std_logic_vector(15442020,24); manlo <= conv_std_logic_vector(105121290,28); exponent <= conv_std_logic_vector(1162,11); WHEN "0001100010" => manhi <= conv_std_logic_vector(5118025,24); manlo <= conv_std_logic_vector(54367076,28); exponent <= conv_std_logic_vector(1164,11); WHEN "0001100011" => manhi <= conv_std_logic_vector(12981502,24); manlo <= conv_std_logic_vector(39000129,28); exponent <= conv_std_logic_vector(1165,11); WHEN "0001100100" => manhi <= conv_std_logic_vector(3445929,24); manlo <= conv_std_logic_vector(186063861,28); exponent <= conv_std_logic_vector(1167,11); WHEN "0001100101" => manhi <= conv_std_logic_vector(10708888,24); manlo <= conv_std_logic_vector(194877084,28); exponent <= conv_std_logic_vector(1168,11); WHEN "0001100110" => manhi <= conv_std_logic_vector(1901528,24); manlo <= conv_std_logic_vector(202114223,28); exponent <= conv_std_logic_vector(1170,11); WHEN "0001100111" => manhi <= conv_std_logic_vector(8609830,24); manlo <= conv_std_logic_vector(59099508,28); exponent <= conv_std_logic_vector(1171,11); WHEN "0001101000" => manhi <= conv_std_logic_vector(475070,24); manlo <= conv_std_logic_vector(162304029,28); exponent <= conv_std_logic_vector(1173,11); WHEN "0001101001" => manhi <= conv_std_logic_vector(6671072,24); manlo <= conv_std_logic_vector(157938310,28); exponent <= conv_std_logic_vector(1174,11); WHEN "0001101010" => manhi <= conv_std_logic_vector(15092312,24); manlo <= conv_std_logic_vector(104450792,28); exponent <= conv_std_logic_vector(1175,11); WHEN "0001101011" => manhi <= conv_std_logic_vector(4880373,24); manlo <= conv_std_logic_vector(261837049,28); exponent <= conv_std_logic_vector(1177,11); WHEN "0001101100" => manhi <= conv_std_logic_vector(12658500,24); manlo <= conv_std_logic_vector(171583716,28); exponent <= conv_std_logic_vector(1178,11); WHEN "0001101101" => manhi <= conv_std_logic_vector(3226427,24); manlo <= conv_std_logic_vector(110595717,28); exponent <= conv_std_logic_vector(1180,11); WHEN "0001101110" => manhi <= conv_std_logic_vector(10410554,24); manlo <= conv_std_logic_vector(52320382,28); exponent <= conv_std_logic_vector(1181,11); WHEN "0001101111" => manhi <= conv_std_logic_vector(1698789,24); manlo <= conv_std_logic_vector(112550995,28); exponent <= conv_std_logic_vector(1183,11); WHEN "0001110000" => manhi <= conv_std_logic_vector(8334278,24); manlo <= conv_std_logic_vector(240753534,28); exponent <= conv_std_logic_vector(1184,11); WHEN "0001110001" => manhi <= conv_std_logic_vector(287814,24); manlo <= conv_std_logic_vector(17691391,28); exponent <= conv_std_logic_vector(1186,11); WHEN "0001110010" => manhi <= conv_std_logic_vector(6416564,24); manlo <= conv_std_logic_vector(151700710,28); exponent <= conv_std_logic_vector(1187,11); WHEN "0001110011" => manhi <= conv_std_logic_vector(14746400,24); manlo <= conv_std_logic_vector(32676275,28); exponent <= conv_std_logic_vector(1188,11); WHEN "0001110100" => manhi <= conv_std_logic_vector(4645302,24); manlo <= conv_std_logic_vector(58452725,28); exponent <= conv_std_logic_vector(1190,11); WHEN "0001110101" => manhi <= conv_std_logic_vector(12339004,24); manlo <= conv_std_logic_vector(267247876,28); exponent <= conv_std_logic_vector(1191,11); WHEN "0001110110" => manhi <= conv_std_logic_vector(3009307,24); manlo <= conv_std_logic_vector(164126253,28); exponent <= conv_std_logic_vector(1193,11); WHEN "0001110111" => manhi <= conv_std_logic_vector(10115457,24); manlo <= conv_std_logic_vector(212237584,28); exponent <= conv_std_logic_vector(1194,11); WHEN "0001111000" => manhi <= conv_std_logic_vector(1498250,24); manlo <= conv_std_logic_vector(166684427,28); exponent <= conv_std_logic_vector(1196,11); WHEN "0001111001" => manhi <= conv_std_logic_vector(8061718,24); manlo <= conv_std_logic_vector(110371593,28); exponent <= conv_std_logic_vector(1197,11); WHEN "0001111010" => manhi <= conv_std_logic_vector(102590,24); manlo <= conv_std_logic_vector(3231911,28); exponent <= conv_std_logic_vector(1199,11); WHEN "0001111011" => manhi <= conv_std_logic_vector(6164818,24); manlo <= conv_std_logic_vector(261783833,28); exponent <= conv_std_logic_vector(1200,11); WHEN "0001111100" => manhi <= conv_std_logic_vector(14404242,24); manlo <= conv_std_logic_vector(104825991,28); exponent <= conv_std_logic_vector(1201,11); WHEN "0001111101" => manhi <= conv_std_logic_vector(4412781,24); manlo <= conv_std_logic_vector(250166254,28); exponent <= conv_std_logic_vector(1203,11); WHEN "0001111110" => manhi <= conv_std_logic_vector(12022977,24); manlo <= conv_std_logic_vector(43417082,28); exponent <= conv_std_logic_vector(1204,11); WHEN "0001111111" => manhi <= conv_std_logic_vector(2794544,24); manlo <= conv_std_logic_vector(115942082,28); exponent <= conv_std_logic_vector(1206,11); WHEN "0010000000" => manhi <= conv_std_logic_vector(9823564,24); manlo <= conv_std_logic_vector(98386456,28); exponent <= conv_std_logic_vector(1207,11); WHEN "0010000001" => manhi <= conv_std_logic_vector(1299888,24); manlo <= conv_std_logic_vector(127046227,28); exponent <= conv_std_logic_vector(1209,11); WHEN "0010000010" => manhi <= conv_std_logic_vector(7792116,24); manlo <= conv_std_logic_vector(80649262,28); exponent <= conv_std_logic_vector(1210,11); WHEN "0010000011" => manhi <= conv_std_logic_vector(16615968,24); manlo <= conv_std_logic_vector(205307910,28); exponent <= conv_std_logic_vector(1211,11); WHEN "0010000100" => manhi <= conv_std_logic_vector(5915805,24); manlo <= conv_std_logic_vector(224185017,28); exponent <= conv_std_logic_vector(1213,11); WHEN "0010000101" => manhi <= conv_std_logic_vector(14065798,24); manlo <= conv_std_logic_vector(119094636,28); exponent <= conv_std_logic_vector(1214,11); WHEN "0010000110" => manhi <= conv_std_logic_vector(4182785,24); manlo <= conv_std_logic_vector(113890892,28); exponent <= conv_std_logic_vector(1216,11); WHEN "0010000111" => manhi <= conv_std_logic_vector(11710379,24); manlo <= conv_std_logic_vector(133692518,28); exponent <= conv_std_logic_vector(1217,11); WHEN "0010001000" => manhi <= conv_std_logic_vector(2582112,24); manlo <= conv_std_logic_vector(79109485,28); exponent <= conv_std_logic_vector(1219,11); WHEN "0010001001" => manhi <= conv_std_logic_vector(9534839,24); manlo <= conv_std_logic_vector(42234535,28); exponent <= conv_std_logic_vector(1220,11); WHEN "0010001010" => manhi <= conv_std_logic_vector(1103679,24); manlo <= conv_std_logic_vector(94193887,28); exponent <= conv_std_logic_vector(1222,11); WHEN "0010001011" => manhi <= conv_std_logic_vector(7525440,24); manlo <= conv_std_logic_vector(121994268,28); exponent <= conv_std_logic_vector(1223,11); WHEN "0010001100" => manhi <= conv_std_logic_vector(16253518,24); manlo <= conv_std_logic_vector(191052573,28); exponent <= conv_std_logic_vector(1224,11); WHEN "0010001101" => manhi <= conv_std_logic_vector(5669495,24); manlo <= conv_std_logic_vector(130696997,28); exponent <= conv_std_logic_vector(1226,11); WHEN "0010001110" => manhi <= conv_std_logic_vector(13731027,24); manlo <= conv_std_logic_vector(260846837,28); exponent <= conv_std_logic_vector(1227,11); WHEN "0010001111" => manhi <= conv_std_logic_vector(3955285,24); manlo <= conv_std_logic_vector(80970159,28); exponent <= conv_std_logic_vector(1229,11); WHEN "0010010000" => manhi <= conv_std_logic_vector(11401174,24); manlo <= conv_std_logic_vector(207600506,28); exponent <= conv_std_logic_vector(1230,11); WHEN "0010010001" => manhi <= conv_std_logic_vector(2371985,24); manlo <= conv_std_logic_vector(241221170,28); exponent <= conv_std_logic_vector(1232,11); WHEN "0010010010" => manhi <= conv_std_logic_vector(9249247,24); manlo <= conv_std_logic_vector(208105818,28); exponent <= conv_std_logic_vector(1233,11); WHEN "0010010011" => manhi <= conv_std_logic_vector(909599,24); manlo <= conv_std_logic_vector(237519888,28); exponent <= conv_std_logic_vector(1235,11); WHEN "0010010100" => manhi <= conv_std_logic_vector(7261659,24); manlo <= conv_std_logic_vector(29935335,28); exponent <= conv_std_logic_vector(1236,11); WHEN "0010010101" => manhi <= conv_std_logic_vector(15895002,24); manlo <= conv_std_logic_vector(186862656,28); exponent <= conv_std_logic_vector(1237,11); WHEN "0010010110" => manhi <= conv_std_logic_vector(5425858,24); manlo <= conv_std_logic_vector(159524243,28); exponent <= conv_std_logic_vector(1239,11); WHEN "0010010111" => manhi <= conv_std_logic_vector(13399891,24); manlo <= conv_std_logic_vector(27586577,28); exponent <= conv_std_logic_vector(1240,11); WHEN "0010011000" => manhi <= conv_std_logic_vector(3730254,24); manlo <= conv_std_logic_vector(125689310,28); exponent <= conv_std_logic_vector(1242,11); WHEN "0010011001" => manhi <= conv_std_logic_vector(11095326,24); manlo <= conv_std_logic_vector(43144000,28); exponent <= conv_std_logic_vector(1243,11); WHEN "0010011010" => manhi <= conv_std_logic_vector(2164140,24); manlo <= conv_std_logic_vector(58280992,28); exponent <= conv_std_logic_vector(1245,11); WHEN "0010011011" => manhi <= conv_std_logic_vector(8966756,24); manlo <= conv_std_logic_vector(55210422,28); exponent <= conv_std_logic_vector(1246,11); WHEN "0010011100" => manhi <= conv_std_logic_vector(717626,24); manlo <= conv_std_logic_vector(257633658,28); exponent <= conv_std_logic_vector(1248,11); WHEN "0010011101" => manhi <= conv_std_logic_vector(7000740,24); manlo <= conv_std_logic_vector(229413090,28); exponent <= conv_std_logic_vector(1249,11); WHEN "0010011110" => manhi <= conv_std_logic_vector(15540378,24); manlo <= conv_std_logic_vector(4808337,28); exponent <= conv_std_logic_vector(1250,11); WHEN "0010011111" => manhi <= conv_std_logic_vector(5184866,24); manlo <= conv_std_logic_vector(37474138,28); exponent <= conv_std_logic_vector(1252,11); WHEN "0010100000" => manhi <= conv_std_logic_vector(13072348,24); manlo <= conv_std_logic_vector(106730632,28); exponent <= conv_std_logic_vector(1253,11); WHEN "0010100001" => manhi <= conv_std_logic_vector(3507666,24); manlo <= conv_std_logic_vector(32844500,28); exponent <= conv_std_logic_vector(1255,11); WHEN "0010100010" => manhi <= conv_std_logic_vector(10792797,24); manlo <= conv_std_logic_vector(62496090,28); exponent <= conv_std_logic_vector(1256,11); WHEN "0010100011" => manhi <= conv_std_logic_vector(1958550,24); manlo <= conv_std_logic_vector(132952012,28); exponent <= conv_std_logic_vector(1258,11); WHEN "0010100100" => manhi <= conv_std_logic_vector(8687330,24); manlo <= conv_std_logic_vector(215605290,28); exponent <= conv_std_logic_vector(1259,11); WHEN "0010100101" => manhi <= conv_std_logic_vector(527737,24); manlo <= conv_std_logic_vector(190928911,28); exponent <= conv_std_logic_vector(1261,11); WHEN "0010100110" => manhi <= conv_std_logic_vector(6742654,24); manlo <= conv_std_logic_vector(163162889,28); exponent <= conv_std_logic_vector(1262,11); WHEN "0010100111" => manhi <= conv_std_logic_vector(15189602,24); manlo <= conv_std_logic_vector(118241780,28); exponent <= conv_std_logic_vector(1263,11); WHEN "0010101000" => manhi <= conv_std_logic_vector(4946489,24); manlo <= conv_std_logic_vector(112771062,28); exponent <= conv_std_logic_vector(1265,11); WHEN "0010101001" => manhi <= conv_std_logic_vector(12748360,24); manlo <= conv_std_logic_vector(226864003,28); exponent <= conv_std_logic_vector(1266,11); WHEN "0010101010" => manhi <= conv_std_logic_vector(3287493,24); manlo <= conv_std_logic_vector(202192272,28); exponent <= conv_std_logic_vector(1268,11); WHEN "0010101011" => manhi <= conv_std_logic_vector(10493551,24); manlo <= conv_std_logic_vector(257093553,28); exponent <= conv_std_logic_vector(1269,11); WHEN "0010101100" => manhi <= conv_std_logic_vector(1755192,24); manlo <= conv_std_logic_vector(66281405,28); exponent <= conv_std_logic_vector(1271,11); WHEN "0010101101" => manhi <= conv_std_logic_vector(8410938,24); manlo <= conv_std_logic_vector(77199396,28); exponent <= conv_std_logic_vector(1272,11); WHEN "0010101110" => manhi <= conv_std_logic_vector(339909,24); manlo <= conv_std_logic_vector(140417186,28); exponent <= conv_std_logic_vector(1274,11); WHEN "0010101111" => manhi <= conv_std_logic_vector(6487369,24); manlo <= conv_std_logic_vector(169769464,28); exponent <= conv_std_logic_vector(1275,11); WHEN "0010110000" => manhi <= conv_std_logic_vector(14842634,24); manlo <= conv_std_logic_vector(49834035,28); exponent <= conv_std_logic_vector(1276,11); WHEN "0010110001" => manhi <= conv_std_logic_vector(4710700,24); manlo <= conv_std_logic_vector(11961455,28); exponent <= conv_std_logic_vector(1278,11); WHEN "0010110010" => manhi <= conv_std_logic_vector(12427889,24); manlo <= conv_std_logic_vector(230234502,28); exponent <= conv_std_logic_vector(1279,11); WHEN "0010110011" => manhi <= conv_std_logic_vector(3069711,24); manlo <= conv_std_logic_vector(36989233,28); exponent <= conv_std_logic_vector(1281,11); WHEN "0010110100" => manhi <= conv_std_logic_vector(10197554,24); manlo <= conv_std_logic_vector(186484869,28); exponent <= conv_std_logic_vector(1282,11); WHEN "0010110101" => manhi <= conv_std_logic_vector(1554041,24); manlo <= conv_std_logic_vector(67530342,28); exponent <= conv_std_logic_vector(1284,11); WHEN "0010110110" => manhi <= conv_std_logic_vector(8137545,24); manlo <= conv_std_logic_vector(198608842,28); exponent <= conv_std_logic_vector(1285,11); WHEN "0010110111" => manhi <= conv_std_logic_vector(154120,24); manlo <= conv_std_logic_vector(6569319,28); exponent <= conv_std_logic_vector(1287,11); WHEN "0010111000" => manhi <= conv_std_logic_vector(6234855,24); manlo <= conv_std_logic_vector(140506894,28); exponent <= conv_std_logic_vector(1288,11); WHEN "0010111001" => manhi <= conv_std_logic_vector(14499431,24); manlo <= conv_std_logic_vector(249287529,28); exponent <= conv_std_logic_vector(1289,11); WHEN "0010111010" => manhi <= conv_std_logic_vector(4477469,24); manlo <= conv_std_logic_vector(249618841,28); exponent <= conv_std_logic_vector(1291,11); WHEN "0010111011" => manhi <= conv_std_logic_vector(12110897,24); manlo <= conv_std_logic_vector(71519058,28); exponent <= conv_std_logic_vector(1292,11); WHEN "0010111100" => manhi <= conv_std_logic_vector(2854292,24); manlo <= conv_std_logic_vector(90637320,28); exponent <= conv_std_logic_vector(1294,11); WHEN "0010111101" => manhi <= conv_std_logic_vector(9904770,24); manlo <= conv_std_logic_vector(50932558,28); exponent <= conv_std_logic_vector(1295,11); WHEN "0010111110" => manhi <= conv_std_logic_vector(1355073,24); manlo <= conv_std_logic_vector(148093260,28); exponent <= conv_std_logic_vector(1297,11); WHEN "0010111111" => manhi <= conv_std_logic_vector(7867120,24); manlo <= conv_std_logic_vector(160620741,28); exponent <= conv_std_logic_vector(1298,11); WHEN "0011000000" => manhi <= conv_std_logic_vector(16717910,24); manlo <= conv_std_logic_vector(46942270,28); exponent <= conv_std_logic_vector(1299,11); WHEN "0011000001" => manhi <= conv_std_logic_vector(5985082,24); manlo <= conv_std_logic_vector(55237426,28); exponent <= conv_std_logic_vector(1301,11); WHEN "0011000010" => manhi <= conv_std_logic_vector(14159954,24); manlo <= conv_std_logic_vector(212966668,28); exponent <= conv_std_logic_vector(1302,11); WHEN "0011000011" => manhi <= conv_std_logic_vector(4246771,24); manlo <= conv_std_logic_vector(79962334,28); exponent <= conv_std_logic_vector(1304,11); WHEN "0011000100" => manhi <= conv_std_logic_vector(11797345,24); manlo <= conv_std_logic_vector(85038862,28); exponent <= conv_std_logic_vector(1305,11); WHEN "0011000101" => manhi <= conv_std_logic_vector(2641211,24); manlo <= conv_std_logic_vector(186806322,28); exponent <= conv_std_logic_vector(1307,11); WHEN "0011000110" => manhi <= conv_std_logic_vector(9615163,24); manlo <= conv_std_logic_vector(153415152,28); exponent <= conv_std_logic_vector(1308,11); WHEN "0011000111" => manhi <= conv_std_logic_vector(1158265,24); manlo <= conv_std_logic_vector(120731907,28); exponent <= conv_std_logic_vector(1310,11); WHEN "0011001000" => manhi <= conv_std_logic_vector(7599630,24); manlo <= conv_std_logic_vector(175764921,28); exponent <= conv_std_logic_vector(1311,11); WHEN "0011001001" => manhi <= conv_std_logic_vector(16354353,24); manlo <= conv_std_logic_vector(174054693,28); exponent <= conv_std_logic_vector(1312,11); WHEN "0011001010" => manhi <= conv_std_logic_vector(5738019,24); manlo <= conv_std_logic_vector(249885394,28); exponent <= conv_std_logic_vector(1314,11); WHEN "0011001011" => manhi <= conv_std_logic_vector(13824162,24); manlo <= conv_std_logic_vector(93203713,28); exponent <= conv_std_logic_vector(1315,11); WHEN "0011001100" => manhi <= conv_std_logic_vector(4018576,24); manlo <= conv_std_logic_vector(180323091,28); exponent <= conv_std_logic_vector(1317,11); WHEN "0011001101" => manhi <= conv_std_logic_vector(11487196,24); manlo <= conv_std_logic_vector(178245939,28); exponent <= conv_std_logic_vector(1318,11); WHEN "0011001110" => manhi <= conv_std_logic_vector(2430443,24); manlo <= conv_std_logic_vector(223919964,28); exponent <= conv_std_logic_vector(1320,11); WHEN "0011001111" => manhi <= conv_std_logic_vector(9328700,24); manlo <= conv_std_logic_vector(93205956,28); exponent <= conv_std_logic_vector(1321,11); WHEN "0011010000" => manhi <= conv_std_logic_vector(963593,24); manlo <= conv_std_logic_vector(135688620,28); exponent <= conv_std_logic_vector(1323,11); WHEN "0011010001" => manhi <= conv_std_logic_vector(7335044,24); manlo <= conv_std_logic_vector(13542358,28); exponent <= conv_std_logic_vector(1324,11); WHEN "0011010010" => manhi <= conv_std_logic_vector(15994743,24); manlo <= conv_std_logic_vector(45394459,28); exponent <= conv_std_logic_vector(1325,11); WHEN "0011010011" => manhi <= conv_std_logic_vector(5493639,24); manlo <= conv_std_logic_vector(73308838,28); exponent <= conv_std_logic_vector(1327,11); WHEN "0011010100" => manhi <= conv_std_logic_vector(13492014,24); manlo <= conv_std_logic_vector(160135181,28); exponent <= conv_std_logic_vector(1328,11); WHEN "0011010101" => manhi <= conv_std_logic_vector(3792858,24); manlo <= conv_std_logic_vector(234346738,28); exponent <= conv_std_logic_vector(1330,11); WHEN "0011010110" => manhi <= conv_std_logic_vector(11180414,24); manlo <= conv_std_logic_vector(98964646,28); exponent <= conv_std_logic_vector(1331,11); WHEN "0011010111" => manhi <= conv_std_logic_vector(2221963,24); manlo <= conv_std_logic_vector(174344531,28); exponent <= conv_std_logic_vector(1333,11); WHEN "0011011000" => manhi <= conv_std_logic_vector(9045346,24); manlo <= conv_std_logic_vector(106947534,28); exponent <= conv_std_logic_vector(1334,11); WHEN "0011011001" => manhi <= conv_std_logic_vector(771034,24); manlo <= conv_std_logic_vector(143065990,28); exponent <= conv_std_logic_vector(1336,11); WHEN "0011011010" => manhi <= conv_std_logic_vector(7073329,24); manlo <= conv_std_logic_vector(73148434,28); exponent <= conv_std_logic_vector(1337,11); WHEN "0011011011" => manhi <= conv_std_logic_vector(15639035,24); manlo <= conv_std_logic_vector(243346703,28); exponent <= conv_std_logic_vector(1338,11); WHEN "0011011100" => manhi <= conv_std_logic_vector(5251911,24); manlo <= conv_std_logic_vector(33842377,28); exponent <= conv_std_logic_vector(1340,11); WHEN "0011011101" => manhi <= conv_std_logic_vector(13163471,24); manlo <= conv_std_logic_vector(263552292,28); exponent <= conv_std_logic_vector(1341,11); WHEN "0011011110" => manhi <= conv_std_logic_vector(3569591,24); manlo <= conv_std_logic_vector(4866264,28); exponent <= conv_std_logic_vector(1343,11); WHEN "0011011111" => manhi <= conv_std_logic_vector(10876961,24); manlo <= conv_std_logic_vector(239517036,28); exponent <= conv_std_logic_vector(1344,11); WHEN "0011100000" => manhi <= conv_std_logic_vector(2015746,24); manlo <= conv_std_logic_vector(83586287,28); exponent <= conv_std_logic_vector(1346,11); WHEN "0011100001" => manhi <= conv_std_logic_vector(8765067,24); manlo <= conv_std_logic_vector(262254542,28); exponent <= conv_std_logic_vector(1347,11); WHEN "0011100010" => manhi <= conv_std_logic_vector(580565,24); manlo <= conv_std_logic_vector(160521039,28); exponent <= conv_std_logic_vector(1349,11); WHEN "0011100011" => manhi <= conv_std_logic_vector(6814455,24); manlo <= conv_std_logic_vector(40288155,28); exponent <= conv_std_logic_vector(1350,11); WHEN "0011100100" => manhi <= conv_std_logic_vector(15287189,24); manlo <= conv_std_logic_vector(132910147,28); exponent <= conv_std_logic_vector(1351,11); WHEN "0011100101" => manhi <= conv_std_logic_vector(5012806,24); manlo <= conv_std_logic_vector(187753904,28); exponent <= conv_std_logic_vector(1353,11); WHEN "0011100110" => manhi <= conv_std_logic_vector(12838495,24); manlo <= conv_std_logic_vector(100071648,28); exponent <= conv_std_logic_vector(1354,11); WHEN "0011100111" => manhi <= conv_std_logic_vector(3348746,24); manlo <= conv_std_logic_vector(138348888,28); exponent <= conv_std_logic_vector(1356,11); WHEN "0011101000" => manhi <= conv_std_logic_vector(10576803,24); manlo <= conv_std_logic_vector(24941937,28); exponent <= conv_std_logic_vector(1357,11); WHEN "0011101001" => manhi <= conv_std_logic_vector(1811767,24); manlo <= conv_std_logic_vector(69497619,28); exponent <= conv_std_logic_vector(1359,11); WHEN "0011101010" => manhi <= conv_std_logic_vector(8487831,24); manlo <= conv_std_logic_vector(188199296,28); exponent <= conv_std_logic_vector(1360,11); WHEN "0011101011" => manhi <= conv_std_logic_vector(392164,24); manlo <= conv_std_logic_vector(4096525,28); exponent <= conv_std_logic_vector(1362,11); WHEN "0011101100" => manhi <= conv_std_logic_vector(6558390,24); manlo <= conv_std_logic_vector(228356857,28); exponent <= conv_std_logic_vector(1363,11); WHEN "0011101101" => manhi <= conv_std_logic_vector(14939162,24); manlo <= conv_std_logic_vector(7826265,28); exponent <= conv_std_logic_vector(1364,11); WHEN "0011101110" => manhi <= conv_std_logic_vector(4776297,24); manlo <= conv_std_logic_vector(138324122,28); exponent <= conv_std_logic_vector(1366,11); WHEN "0011101111" => manhi <= conv_std_logic_vector(12517046,24); manlo <= conv_std_logic_vector(17190560,28); exponent <= conv_std_logic_vector(1367,11); WHEN "0011110000" => manhi <= conv_std_logic_vector(3130299,24); manlo <= conv_std_logic_vector(16562242,28); exponent <= conv_std_logic_vector(1369,11); WHEN "0011110001" => manhi <= conv_std_logic_vector(10279902,24); manlo <= conv_std_logic_vector(59323104,28); exponent <= conv_std_logic_vector(1370,11); WHEN "0011110010" => manhi <= conv_std_logic_vector(1610002,24); manlo <= conv_std_logic_vector(53056333,28); exponent <= conv_std_logic_vector(1372,11); WHEN "0011110011" => manhi <= conv_std_logic_vector(8213604,24); manlo <= conv_std_logic_vector(147986337,28); exponent <= conv_std_logic_vector(1373,11); WHEN "0011110100" => manhi <= conv_std_logic_vector(205807,24); manlo <= conv_std_logic_vector(92802035,28); exponent <= conv_std_logic_vector(1375,11); WHEN "0011110101" => manhi <= conv_std_logic_vector(6305105,24); manlo <= conv_std_logic_vector(235277170,28); exponent <= conv_std_logic_vector(1376,11); WHEN "0011110110" => manhi <= conv_std_logic_vector(14594912,24); manlo <= conv_std_logic_vector(15497684,28); exponent <= conv_std_logic_vector(1377,11); WHEN "0011110111" => manhi <= conv_std_logic_vector(4542355,24); manlo <= conv_std_logic_vector(108677892,28); exponent <= conv_std_logic_vector(1379,11); WHEN "0011111000" => manhi <= conv_std_logic_vector(12199085,24); manlo <= conv_std_logic_vector(206743222,28); exponent <= conv_std_logic_vector(1380,11); WHEN "0011111001" => manhi <= conv_std_logic_vector(2914222,24); manlo <= conv_std_logic_vector(171652524,28); exponent <= conv_std_logic_vector(1382,11); WHEN "0011111010" => manhi <= conv_std_logic_vector(9986223,24); manlo <= conv_std_logic_vector(245598061,28); exponent <= conv_std_logic_vector(1383,11); WHEN "0011111011" => manhi <= conv_std_logic_vector(1410427,24); manlo <= conv_std_logic_vector(26024388,28); exponent <= conv_std_logic_vector(1385,11); WHEN "0011111100" => manhi <= conv_std_logic_vector(7942353,24); manlo <= conv_std_logic_vector(232590388,28); exponent <= conv_std_logic_vector(1386,11); WHEN "0011111101" => manhi <= conv_std_logic_vector(21473,24); manlo <= conv_std_logic_vector(105719295,28); exponent <= conv_std_logic_vector(1388,11); WHEN "0011111110" => manhi <= conv_std_logic_vector(6054570,24); manlo <= conv_std_logic_vector(16265786,28); exponent <= conv_std_logic_vector(1389,11); WHEN "0011111111" => manhi <= conv_std_logic_vector(14254398,24); manlo <= conv_std_logic_vector(155662944,28); exponent <= conv_std_logic_vector(1390,11); WHEN "0100000000" => manhi <= conv_std_logic_vector(4310952,24); manlo <= conv_std_logic_vector(135577274,28); exponent <= conv_std_logic_vector(1392,11); WHEN "0100000001" => manhi <= conv_std_logic_vector(11884576,24); manlo <= conv_std_logic_vector(166805756,28); exponent <= conv_std_logic_vector(1393,11); WHEN "0100000010" => manhi <= conv_std_logic_vector(2700491,24); manlo <= conv_std_logic_vector(137829044,28); exponent <= conv_std_logic_vector(1395,11); WHEN "0100000011" => manhi <= conv_std_logic_vector(9695733,24); manlo <= conv_std_logic_vector(52863001,28); exponent <= conv_std_logic_vector(1396,11); WHEN "0100000100" => manhi <= conv_std_logic_vector(1213018,24); manlo <= conv_std_logic_vector(50179603,28); exponent <= conv_std_logic_vector(1398,11); WHEN "0100000101" => manhi <= conv_std_logic_vector(7674047,24); manlo <= conv_std_logic_vector(91276680,28); exponent <= conv_std_logic_vector(1399,11); WHEN "0100000110" => manhi <= conv_std_logic_vector(16455496,24); manlo <= conv_std_logic_vector(110068760,28); exponent <= conv_std_logic_vector(1400,11); WHEN "0100000111" => manhi <= conv_std_logic_vector(5806753,24); manlo <= conv_std_logic_vector(151304445,28); exponent <= conv_std_logic_vector(1402,11); WHEN "0100001000" => manhi <= conv_std_logic_vector(13917581,24); manlo <= conv_std_logic_vector(10650184,28); exponent <= conv_std_logic_vector(1403,11); WHEN "0100001001" => manhi <= conv_std_logic_vector(4082061,24); manlo <= conv_std_logic_vector(68530707,28); exponent <= conv_std_logic_vector(1405,11); WHEN "0100001010" => manhi <= conv_std_logic_vector(11573481,24); manlo <= conv_std_logic_vector(42662756,28); exponent <= conv_std_logic_vector(1406,11); WHEN "0100001011" => manhi <= conv_std_logic_vector(2489080,24); manlo <= conv_std_logic_vector(61154162,28); exponent <= conv_std_logic_vector(1408,11); WHEN "0100001100" => manhi <= conv_std_logic_vector(9408395,24); manlo <= conv_std_logic_vector(125867240,28); exponent <= conv_std_logic_vector(1409,11); WHEN "0100001101" => manhi <= conv_std_logic_vector(1017751,24); manlo <= conv_std_logic_vector(256555705,28); exponent <= conv_std_logic_vector(1411,11); WHEN "0100001110" => manhi <= conv_std_logic_vector(7408653,24); manlo <= conv_std_logic_vector(4309896,28); exponent <= conv_std_logic_vector(1412,11); WHEN "0100001111" => manhi <= conv_std_logic_vector(16094788,24); manlo <= conv_std_logic_vector(33800670,28); exponent <= conv_std_logic_vector(1413,11); WHEN "0100010000" => manhi <= conv_std_logic_vector(5561626,24); manlo <= conv_std_logic_vector(233573192,28); exponent <= conv_std_logic_vector(1415,11); WHEN "0100010001" => manhi <= conv_std_logic_vector(13584419,24); manlo <= conv_std_logic_vector(86257801,28); exponent <= conv_std_logic_vector(1416,11); WHEN "0100010010" => manhi <= conv_std_logic_vector(3855654,24); manlo <= conv_std_logic_vector(105782775,28); exponent <= conv_std_logic_vector(1418,11); WHEN "0100010011" => manhi <= conv_std_logic_vector(11265762,24); manlo <= conv_std_logic_vector(88738762,28); exponent <= conv_std_logic_vector(1419,11); WHEN "0100010100" => manhi <= conv_std_logic_vector(2279963,24); manlo <= conv_std_logic_vector(161858527,28); exponent <= conv_std_logic_vector(1421,11); WHEN "0100010101" => manhi <= conv_std_logic_vector(9124176,24); manlo <= conv_std_logic_vector(136423424,28); exponent <= conv_std_logic_vector(1422,11); WHEN "0100010110" => manhi <= conv_std_logic_vector(824605,24); manlo <= conv_std_logic_vector(39384255,28); exponent <= conv_std_logic_vector(1424,11); WHEN "0100010111" => manhi <= conv_std_logic_vector(7146139,24); manlo <= conv_std_logic_vector(76626123,28); exponent <= conv_std_logic_vector(1425,11); WHEN "0100011000" => manhi <= conv_std_logic_vector(15737994,24); manlo <= conv_std_logic_vector(261485765,28); exponent <= conv_std_logic_vector(1426,11); WHEN "0100011001" => manhi <= conv_std_logic_vector(5319160,24); manlo <= conv_std_logic_vector(210684009,28); exponent <= conv_std_logic_vector(1428,11); WHEN "0100011010" => manhi <= conv_std_logic_vector(13254873,24); manlo <= conv_std_logic_vector(199859160,28); exponent <= conv_std_logic_vector(1429,11); WHEN "0100011011" => manhi <= conv_std_logic_vector(3631704,24); manlo <= conv_std_logic_vector(256571707,28); exponent <= conv_std_logic_vector(1431,11); WHEN "0100011100" => manhi <= conv_std_logic_vector(10961383,24); manlo <= conv_std_logic_vector(130542749,28); exponent <= conv_std_logic_vector(1432,11); WHEN "0100011101" => manhi <= conv_std_logic_vector(2073116,24); manlo <= conv_std_logic_vector(196665136,28); exponent <= conv_std_logic_vector(1434,11); WHEN "0100011110" => manhi <= conv_std_logic_vector(8843042,24); manlo <= conv_std_logic_vector(124490661,28); exponent <= conv_std_logic_vector(1435,11); WHEN "0100011111" => manhi <= conv_std_logic_vector(633554,24); manlo <= conv_std_logic_vector(202834752,28); exponent <= conv_std_logic_vector(1437,11); WHEN "0100100000" => manhi <= conv_std_logic_vector(6886474,24); manlo <= conv_std_logic_vector(236822279,28); exponent <= conv_std_logic_vector(1438,11); WHEN "0100100001" => manhi <= conv_std_logic_vector(15385074,24); manlo <= conv_std_logic_vector(123405487,28); exponent <= conv_std_logic_vector(1439,11); WHEN "0100100010" => manhi <= conv_std_logic_vector(5079326,24); manlo <= conv_std_logic_vector(115311954,28); exponent <= conv_std_logic_vector(1441,11); WHEN "0100100011" => manhi <= conv_std_logic_vector(12928905,24); manlo <= conv_std_logic_vector(16004876,28); exponent <= conv_std_logic_vector(1442,11); WHEN "0100100100" => manhi <= conv_std_logic_vector(3410186,24); manlo <= conv_std_logic_vector(71831800,28); exponent <= conv_std_logic_vector(1444,11); WHEN "0100100101" => manhi <= conv_std_logic_vector(10660308,24); manlo <= conv_std_logic_vector(100367284,28); exponent <= conv_std_logic_vector(1445,11); WHEN "0100100110" => manhi <= conv_std_logic_vector(1868514,24); manlo <= conv_std_logic_vector(263299419,28); exponent <= conv_std_logic_vector(1447,11); WHEN "0100100111" => manhi <= conv_std_logic_vector(8564959,24); manlo <= conv_std_logic_vector(228656810,28); exponent <= conv_std_logic_vector(1448,11); WHEN "0100101000" => manhi <= conv_std_logic_vector(444578,24); manlo <= conv_std_logic_vector(7489141,28); exponent <= conv_std_logic_vector(1450,11); WHEN "0100101001" => manhi <= conv_std_logic_vector(6629628,24); manlo <= conv_std_logic_vector(236156491,28); exponent <= conv_std_logic_vector(1451,11); WHEN "0100101010" => manhi <= conv_std_logic_vector(15035984,24); manlo <= conv_std_logic_vector(147396312,28); exponent <= conv_std_logic_vector(1452,11); WHEN "0100101011" => manhi <= conv_std_logic_vector(4842095,24); manlo <= conv_std_logic_vector(64271882,28); exponent <= conv_std_logic_vector(1454,11); WHEN "0100101100" => manhi <= conv_std_logic_vector(12606474,24); manlo <= conv_std_logic_vector(118909770,28); exponent <= conv_std_logic_vector(1455,11); WHEN "0100101101" => manhi <= conv_std_logic_vector(3191071,24); manlo <= conv_std_logic_vector(253953386,28); exponent <= conv_std_logic_vector(1457,11); WHEN "0100101110" => manhi <= conv_std_logic_vector(10362501,24); manlo <= conv_std_logic_vector(36129498,28); exponent <= conv_std_logic_vector(1458,11); WHEN "0100101111" => manhi <= conv_std_logic_vector(1666133,24); manlo <= conv_std_logic_vector(262830684,28); exponent <= conv_std_logic_vector(1460,11); WHEN "0100110000" => manhi <= conv_std_logic_vector(8289895,24); manlo <= conv_std_logic_vector(148197046,28); exponent <= conv_std_logic_vector(1461,11); WHEN "0100110001" => manhi <= conv_std_logic_vector(257652,24); manlo <= conv_std_logic_vector(122404338,28); exponent <= conv_std_logic_vector(1463,11); WHEN "0100110010" => manhi <= conv_std_logic_vector(6375570,24); manlo <= conv_std_logic_vector(184430245,28); exponent <= conv_std_logic_vector(1464,11); WHEN "0100110011" => manhi <= conv_std_logic_vector(14690683,24); manlo <= conv_std_logic_vector(178457687,28); exponent <= conv_std_logic_vector(1465,11); WHEN "0100110100" => manhi <= conv_std_logic_vector(4607438,24); manlo <= conv_std_logic_vector(257605193,28); exponent <= conv_std_logic_vector(1467,11); WHEN "0100110101" => manhi <= conv_std_logic_vector(12287543,24); manlo <= conv_std_logic_vector(132163446,28); exponent <= conv_std_logic_vector(1468,11); WHEN "0100110110" => manhi <= conv_std_logic_vector(2974335,24); manlo <= conv_std_logic_vector(240020217,28); exponent <= conv_std_logic_vector(1470,11); WHEN "0100110111" => manhi <= conv_std_logic_vector(10067926,24); manlo <= conv_std_logic_vector(80224641,28); exponent <= conv_std_logic_vector(1471,11); WHEN "0100111000" => manhi <= conv_std_logic_vector(1465949,24); manlo <= conv_std_logic_vector(167328478,28); exponent <= conv_std_logic_vector(1473,11); WHEN "0100111001" => manhi <= conv_std_logic_vector(8017816,24); manlo <= conv_std_logic_vector(215756784,28); exponent <= conv_std_logic_vector(1474,11); WHEN "0100111010" => manhi <= conv_std_logic_vector(72755,24); manlo <= conv_std_logic_vector(208473528,28); exponent <= conv_std_logic_vector(1476,11); WHEN "0100111011" => manhi <= conv_std_logic_vector(6124270,24); manlo <= conv_std_logic_vector(12139444,28); exponent <= conv_std_logic_vector(1477,11); WHEN "0100111100" => manhi <= conv_std_logic_vector(14349130,24); manlo <= conv_std_logic_vector(182729110,28); exponent <= conv_std_logic_vector(1478,11); WHEN "0100111101" => manhi <= conv_std_logic_vector(4375329,24); manlo <= conv_std_logic_vector(172370119,28); exponent <= conv_std_logic_vector(1480,11); WHEN "0100111110" => manhi <= conv_std_logic_vector(11972074,24); manlo <= conv_std_logic_vector(59679792,28); exponent <= conv_std_logic_vector(1481,11); WHEN "0100111111" => manhi <= conv_std_logic_vector(2759952,24); manlo <= conv_std_logic_vector(80023302,28); exponent <= conv_std_logic_vector(1483,11); WHEN "0101000000" => manhi <= conv_std_logic_vector(9776548,24); manlo <= conv_std_logic_vector(209956608,28); exponent <= conv_std_logic_vector(1484,11); WHEN "0101000001" => manhi <= conv_std_logic_vector(1267938,24); manlo <= conv_std_logic_vector(19091951,28); exponent <= conv_std_logic_vector(1486,11); WHEN "0101000010" => manhi <= conv_std_logic_vector(7748691,24); manlo <= conv_std_logic_vector(54127000,28); exponent <= conv_std_logic_vector(1487,11); WHEN "0101000011" => manhi <= conv_std_logic_vector(16556947,24); manlo <= conv_std_logic_vector(251347868,28); exponent <= conv_std_logic_vector(1488,11); WHEN "0101000100" => manhi <= conv_std_logic_vector(5875697,24); manlo <= conv_std_logic_vector(6377900,28); exponent <= conv_std_logic_vector(1490,11); WHEN "0101000101" => manhi <= conv_std_logic_vector(14011284,24); manlo <= conv_std_logic_vector(246175281,28); exponent <= conv_std_logic_vector(1491,11); WHEN "0101000110" => manhi <= conv_std_logic_vector(4145739,24); manlo <= conv_std_logic_vector(172360927,28); exponent <= conv_std_logic_vector(1493,11); WHEN "0101000111" => manhi <= conv_std_logic_vector(11660029,24); manlo <= conv_std_logic_vector(16047086,28); exponent <= conv_std_logic_vector(1494,11); WHEN "0101001000" => manhi <= conv_std_logic_vector(2547895,24); manlo <= conv_std_logic_vector(167600151,28); exponent <= conv_std_logic_vector(1496,11); WHEN "0101001001" => manhi <= conv_std_logic_vector(9488333,24); manlo <= conv_std_logic_vector(236416250,28); exponent <= conv_std_logic_vector(1497,11); WHEN "0101001010" => manhi <= conv_std_logic_vector(1072075,24); manlo <= conv_std_logic_vector(198323037,28); exponent <= conv_std_logic_vector(1499,11); WHEN "0101001011" => manhi <= conv_std_logic_vector(7482486,24); manlo <= conv_std_logic_vector(185820926,28); exponent <= conv_std_logic_vector(1500,11); WHEN "0101001100" => manhi <= conv_std_logic_vector(16195138,24); manlo <= conv_std_logic_vector(133160968,28); exponent <= conv_std_logic_vector(1501,11); WHEN "0101001101" => manhi <= conv_std_logic_vector(5629822,24); manlo <= conv_std_logic_vector(4574050,28); exponent <= conv_std_logic_vector(1503,11); WHEN "0101001110" => manhi <= conv_std_logic_vector(13677106,24); manlo <= conv_std_logic_vector(36414601,28); exponent <= conv_std_logic_vector(1504,11); WHEN "0101001111" => manhi <= conv_std_logic_vector(3918641,24); manlo <= conv_std_logic_vector(165046798,28); exponent <= conv_std_logic_vector(1506,11); WHEN "0101010000" => manhi <= conv_std_logic_vector(11351370,24); manlo <= conv_std_logic_vector(225326735,28); exponent <= conv_std_logic_vector(1507,11); WHEN "0101010001" => manhi <= conv_std_logic_vector(2338140,24); manlo <= conv_std_logic_vector(165476611,28); exponent <= conv_std_logic_vector(1509,11); WHEN "0101010010" => manhi <= conv_std_logic_vector(9203247,24); manlo <= conv_std_logic_vector(71807303,28); exponent <= conv_std_logic_vector(1510,11); WHEN "0101010011" => manhi <= conv_std_logic_vector(878339,24); manlo <= conv_std_logic_vector(80195176,28); exponent <= conv_std_logic_vector(1512,11); WHEN "0101010100" => manhi <= conv_std_logic_vector(7219171,24); manlo <= conv_std_logic_vector(153001068,28); exponent <= conv_std_logic_vector(1513,11); WHEN "0101010101" => manhi <= conv_std_logic_vector(15837256,24); manlo <= conv_std_logic_vector(37596960,28); exponent <= conv_std_logic_vector(1514,11); WHEN "0101010110" => manhi <= conv_std_logic_vector(5386615,24); manlo <= conv_std_logic_vector(198850796,28); exponent <= conv_std_logic_vector(1516,11); WHEN "0101010111" => manhi <= conv_std_logic_vector(13346554,24); manlo <= conv_std_logic_vector(143609986,28); exponent <= conv_std_logic_vector(1517,11); WHEN "0101011000" => manhi <= conv_std_logic_vector(3694008,24); manlo <= conv_std_logic_vector(137568494,28); exponent <= conv_std_logic_vector(1519,11); WHEN "0101011001" => manhi <= conv_std_logic_vector(11046062,24); manlo <= conv_std_logic_vector(214558683,28); exponent <= conv_std_logic_vector(1520,11); WHEN "0101011010" => manhi <= conv_std_logic_vector(2130662,24); manlo <= conv_std_logic_vector(78401205,28); exponent <= conv_std_logic_vector(1522,11); WHEN "0101011011" => manhi <= conv_std_logic_vector(8921254,24); manlo <= conv_std_logic_vector(265219821,28); exponent <= conv_std_logic_vector(1523,11); WHEN "0101011100" => manhi <= conv_std_logic_vector(686705,24); manlo <= conv_std_logic_vector(181591149,28); exponent <= conv_std_logic_vector(1525,11); WHEN "0101011101" => manhi <= conv_std_logic_vector(6958714,24); manlo <= conv_std_logic_vector(127078273,28); exponent <= conv_std_logic_vector(1526,11); WHEN "0101011110" => manhi <= conv_std_logic_vector(15483258,24); manlo <= conv_std_logic_vector(65420394,28); exponent <= conv_std_logic_vector(1527,11); WHEN "0101011111" => manhi <= conv_std_logic_vector(5146049,24); manlo <= conv_std_logic_vector(61347424,28); exponent <= conv_std_logic_vector(1529,11); WHEN "0101100000" => manhi <= conv_std_logic_vector(13019590,24); manlo <= conv_std_logic_vector(200148168,28); exponent <= conv_std_logic_vector(1530,11); WHEN "0101100001" => manhi <= conv_std_logic_vector(3471813,24); manlo <= conv_std_logic_vector(155873600,28); exponent <= conv_std_logic_vector(1532,11); WHEN "0101100010" => manhi <= conv_std_logic_vector(10744068,24); manlo <= conv_std_logic_vector(154763366,28); exponent <= conv_std_logic_vector(1533,11); WHEN "0101100011" => manhi <= conv_std_logic_vector(1925435,24); manlo <= conv_std_logic_vector(252346422,28); exponent <= conv_std_logic_vector(1535,11); WHEN "0101100100" => manhi <= conv_std_logic_vector(8642323,24); manlo <= conv_std_logic_vector(122496413,28); exponent <= conv_std_logic_vector(1536,11); WHEN "0101100101" => manhi <= conv_std_logic_vector(497152,24); manlo <= conv_std_logic_vector(12881703,28); exponent <= conv_std_logic_vector(1538,11); WHEN "0101100110" => manhi <= conv_std_logic_vector(6701084,24); manlo <= conv_std_logic_vector(102402698,28); exponent <= conv_std_logic_vector(1539,11); WHEN "0101100111" => manhi <= conv_std_logic_vector(15133102,24); manlo <= conv_std_logic_vector(173151546,28); exponent <= conv_std_logic_vector(1540,11); WHEN "0101101000" => manhi <= conv_std_logic_vector(4908093,24); manlo <= conv_std_logic_vector(222341698,28); exponent <= conv_std_logic_vector(1542,11); WHEN "0101101001" => manhi <= conv_std_logic_vector(12696175,24); manlo <= conv_std_logic_vector(221558290,28); exponent <= conv_std_logic_vector(1543,11); WHEN "0101101010" => manhi <= conv_std_logic_vector(3252030,24); manlo <= conv_std_logic_vector(95425703,28); exponent <= conv_std_logic_vector(1545,11); WHEN "0101101011" => manhi <= conv_std_logic_vector(10445352,24); manlo <= conv_std_logic_vector(54472775,28); exponent <= conv_std_logic_vector(1546,11); WHEN "0101101100" => manhi <= conv_std_logic_vector(1722437,24); manlo <= conv_std_logic_vector(31541381,28); exponent <= conv_std_logic_vector(1548,11); WHEN "0101101101" => manhi <= conv_std_logic_vector(8366419,24); manlo <= conv_std_logic_vector(121077564,28); exponent <= conv_std_logic_vector(1549,11); WHEN "0101101110" => manhi <= conv_std_logic_vector(309655,24); manlo <= conv_std_logic_vector(224679493,28); exponent <= conv_std_logic_vector(1551,11); WHEN "0101101111" => manhi <= conv_std_logic_vector(6446250,24); manlo <= conv_std_logic_vector(163707479,28); exponent <= conv_std_logic_vector(1552,11); WHEN "0101110000" => manhi <= conv_std_logic_vector(14786747,24); manlo <= conv_std_logic_vector(171718440,28); exponent <= conv_std_logic_vector(1553,11); WHEN "0101110001" => manhi <= conv_std_logic_vector(4672721,24); manlo <= conv_std_logic_vector(53414720,28); exponent <= conv_std_logic_vector(1555,11); WHEN "0101110010" => manhi <= conv_std_logic_vector(12376271,24); manlo <= conv_std_logic_vector(68395953,28); exponent <= conv_std_logic_vector(1556,11); WHEN "0101110011" => manhi <= conv_std_logic_vector(3034632,24); manlo <= conv_std_logic_vector(177229210,28); exponent <= conv_std_logic_vector(1558,11); WHEN "0101110100" => manhi <= conv_std_logic_vector(10149878,24); manlo <= conv_std_logic_vector(27015960,28); exponent <= conv_std_logic_vector(1559,11); WHEN "0101110101" => manhi <= conv_std_logic_vector(1521641,24); manlo <= conv_std_logic_vector(173609470,28); exponent <= conv_std_logic_vector(1561,11); WHEN "0101110110" => manhi <= conv_std_logic_vector(8093510,24); manlo <= conv_std_logic_vector(29891310,28); exponent <= conv_std_logic_vector(1562,11); WHEN "0101110111" => manhi <= conv_std_logic_vector(124194,24); manlo <= conv_std_logic_vector(191198183,28); exponent <= conv_std_logic_vector(1564,11); WHEN "0101111000" => manhi <= conv_std_logic_vector(6194182,24); manlo <= conv_std_logic_vector(216692261,28); exponent <= conv_std_logic_vector(1565,11); WHEN "0101111001" => manhi <= conv_std_logic_vector(14444151,24); manlo <= conv_std_logic_vector(261994424,28); exponent <= conv_std_logic_vector(1566,11); WHEN "0101111010" => manhi <= conv_std_logic_vector(4439903,24); manlo <= conv_std_logic_vector(82463931,28); exponent <= conv_std_logic_vector(1568,11); WHEN "0101111011" => manhi <= conv_std_logic_vector(12059838,24); manlo <= conv_std_logic_vector(250318074,28); exponent <= conv_std_logic_vector(1569,11); WHEN "0101111100" => manhi <= conv_std_logic_vector(2819594,24); manlo <= conv_std_logic_vector(161686084,28); exponent <= conv_std_logic_vector(1571,11); WHEN "0101111101" => manhi <= conv_std_logic_vector(9857611,24); manlo <= conv_std_logic_vector(20946108,28); exponent <= conv_std_logic_vector(1572,11); WHEN "0101111110" => manhi <= conv_std_logic_vector(1323025,24); manlo <= conv_std_logic_vector(164440795,28); exponent <= conv_std_logic_vector(1574,11); WHEN "0101111111" => manhi <= conv_std_logic_vector(7823562,24); manlo <= conv_std_logic_vector(250479918,28); exponent <= conv_std_logic_vector(1575,11); WHEN "0110000000" => manhi <= conv_std_logic_vector(16658709,24); manlo <= conv_std_logic_vector(45608811,28); exponent <= conv_std_logic_vector(1576,11); WHEN "0110000001" => manhi <= conv_std_logic_vector(5944850,24); manlo <= conv_std_logic_vector(255488281,28); exponent <= conv_std_logic_vector(1578,11); WHEN "0110000010" => manhi <= conv_std_logic_vector(14105274,24); manlo <= conv_std_logic_vector(228172930,28); exponent <= conv_std_logic_vector(1579,11); WHEN "0110000011" => manhi <= conv_std_logic_vector(4209612,24); manlo <= conv_std_logic_vector(113758652,28); exponent <= conv_std_logic_vector(1581,11); WHEN "0110000100" => manhi <= conv_std_logic_vector(11746841,24); manlo <= conv_std_logic_vector(45816542,28); exponent <= conv_std_logic_vector(1582,11); WHEN "0110000101" => manhi <= conv_std_logic_vector(2606890,24); manlo <= conv_std_logic_vector(153074390,28); exponent <= conv_std_logic_vector(1584,11); WHEN "0110000110" => manhi <= conv_std_logic_vector(9568516,24); manlo <= conv_std_logic_vector(87350878,28); exponent <= conv_std_logic_vector(1585,11); WHEN "0110000111" => manhi <= conv_std_logic_vector(1126565,24); manlo <= conv_std_logic_vector(96475766,28); exponent <= conv_std_logic_vector(1587,11); WHEN "0110001000" => manhi <= conv_std_logic_vector(7556545,24); manlo <= conv_std_logic_vector(205347948,28); exponent <= conv_std_logic_vector(1588,11); WHEN "0110001001" => manhi <= conv_std_logic_vector(16295795,24); manlo <= conv_std_logic_vector(56881285,28); exponent <= conv_std_logic_vector(1589,11); WHEN "0110001010" => manhi <= conv_std_logic_vector(5698225,24); manlo <= conv_std_logic_vector(93263076,28); exponent <= conv_std_logic_vector(1591,11); WHEN "0110001011" => manhi <= conv_std_logic_vector(13770075,24); manlo <= conv_std_logic_vector(241769289,28); exponent <= conv_std_logic_vector(1592,11); WHEN "0110001100" => manhi <= conv_std_logic_vector(3981821,24); manlo <= conv_std_logic_vector(32359920,28); exponent <= conv_std_logic_vector(1594,11); WHEN "0110001101" => manhi <= conv_std_logic_vector(11437240,24); manlo <= conv_std_logic_vector(185367850,28); exponent <= conv_std_logic_vector(1595,11); WHEN "0110001110" => manhi <= conv_std_logic_vector(2396495,24); manlo <= conv_std_logic_vector(61858550,28); exponent <= conv_std_logic_vector(1597,11); WHEN "0110001111" => manhi <= conv_std_logic_vector(9282559,24); manlo <= conv_std_logic_vector(110304027,28); exponent <= conv_std_logic_vector(1598,11); WHEN "0110010000" => manhi <= conv_std_logic_vector(932237,24); manlo <= conv_std_logic_vector(131077892,28); exponent <= conv_std_logic_vector(1600,11); WHEN "0110010001" => manhi <= conv_std_logic_vector(7292426,24); manlo <= conv_std_logic_vector(215982528,28); exponent <= conv_std_logic_vector(1601,11); WHEN "0110010010" => manhi <= conv_std_logic_vector(15936820,24); manlo <= conv_std_logic_vector(87676082,28); exponent <= conv_std_logic_vector(1602,11); WHEN "0110010011" => manhi <= conv_std_logic_vector(5454276,24); manlo <= conv_std_logic_vector(166577430,28); exponent <= conv_std_logic_vector(1604,11); WHEN "0110010100" => manhi <= conv_std_logic_vector(13438515,24); manlo <= conv_std_logic_vector(55023964,28); exponent <= conv_std_logic_vector(1605,11); WHEN "0110010101" => manhi <= conv_std_logic_vector(3756502,24); manlo <= conv_std_logic_vector(71679026,28); exponent <= conv_std_logic_vector(1607,11); WHEN "0110010110" => manhi <= conv_std_logic_vector(11131000,24); manlo <= conv_std_logic_vector(165886683,28); exponent <= conv_std_logic_vector(1608,11); WHEN "0110010111" => manhi <= conv_std_logic_vector(2188383,24); manlo <= conv_std_logic_vector(140750309,28); exponent <= conv_std_logic_vector(1610,11); WHEN "0110011000" => manhi <= conv_std_logic_vector(8999706,24); manlo <= conv_std_logic_vector(74200045,28); exponent <= conv_std_logic_vector(1611,11); WHEN "0110011001" => manhi <= conv_std_logic_vector(740018,24); manlo <= conv_std_logic_vector(229350227,28); exponent <= conv_std_logic_vector(1613,11); WHEN "0110011010" => manhi <= conv_std_logic_vector(7031174,24); manlo <= conv_std_logic_vector(159659309,28); exponent <= conv_std_logic_vector(1614,11); WHEN "0110011011" => manhi <= conv_std_logic_vector(15581741,24); manlo <= conv_std_logic_vector(203828183,28); exponent <= conv_std_logic_vector(1615,11); WHEN "0110011100" => manhi <= conv_std_logic_vector(5212975,24); manlo <= conv_std_logic_vector(192268981,28); exponent <= conv_std_logic_vector(1617,11); WHEN "0110011101" => manhi <= conv_std_logic_vector(13110553,24); manlo <= conv_std_logic_vector(73367990,28); exponent <= conv_std_logic_vector(1618,11); WHEN "0110011110" => manhi <= conv_std_logic_vector(3533629,24); manlo <= conv_std_logic_vector(7303751,28); exponent <= conv_std_logic_vector(1620,11); WHEN "0110011111" => manhi <= conv_std_logic_vector(10828084,24); manlo <= conv_std_logic_vector(128595197,28); exponent <= conv_std_logic_vector(1621,11); WHEN "0110100000" => manhi <= conv_std_logic_vector(1982530,24); manlo <= conv_std_logic_vector(178601213,28); exponent <= conv_std_logic_vector(1623,11); WHEN "0110100001" => manhi <= conv_std_logic_vector(8719923,24); manlo <= conv_std_logic_vector(62665264,28); exponent <= conv_std_logic_vector(1624,11); WHEN "0110100010" => manhi <= conv_std_logic_vector(549886,24); manlo <= conv_std_logic_vector(151395401,28); exponent <= conv_std_logic_vector(1626,11); WHEN "0110100011" => manhi <= conv_std_logic_vector(6772758,24); manlo <= conv_std_logic_vector(5307652,28); exponent <= conv_std_logic_vector(1627,11); WHEN "0110100100" => manhi <= conv_std_logic_vector(15230517,24); manlo <= conv_std_logic_vector(58871965,28); exponent <= conv_std_logic_vector(1628,11); WHEN "0110100101" => manhi <= conv_std_logic_vector(4974293,24); manlo <= conv_std_logic_vector(240265124,28); exponent <= conv_std_logic_vector(1630,11); WHEN "0110100110" => manhi <= conv_std_logic_vector(12786151,24); manlo <= conv_std_logic_vector(11983156,28); exponent <= conv_std_logic_vector(1631,11); WHEN "0110100111" => manhi <= conv_std_logic_vector(3313174,24); manlo <= conv_std_logic_vector(229882212,28); exponent <= conv_std_logic_vector(1633,11); WHEN "0110101000" => manhi <= conv_std_logic_vector(10528456,24); manlo <= conv_std_logic_vector(52550536,28); exponent <= conv_std_logic_vector(1634,11); WHEN "0110101001" => manhi <= conv_std_logic_vector(1778912,24); manlo <= conv_std_logic_vector(36481057,28); exponent <= conv_std_logic_vector(1636,11); WHEN "0110101010" => manhi <= conv_std_logic_vector(8443176,24); manlo <= conv_std_logic_vector(257480801,28); exponent <= conv_std_logic_vector(1637,11); WHEN "0110101011" => manhi <= conv_std_logic_vector(361817,24); manlo <= conv_std_logic_vector(260890045,28); exponent <= conv_std_logic_vector(1639,11); WHEN "0110101100" => manhi <= conv_std_logic_vector(6517146,24); manlo <= conv_std_logic_vector(80951272,28); exponent <= conv_std_logic_vector(1640,11); WHEN "0110101101" => manhi <= conv_std_logic_vector(14883104,24); manlo <= conv_std_logic_vector(234866389,28); exponent <= conv_std_logic_vector(1641,11); WHEN "0110101110" => manhi <= conv_std_logic_vector(4738202,24); manlo <= conv_std_logic_vector(195793257,28); exponent <= conv_std_logic_vector(1643,11); WHEN "0110101111" => manhi <= conv_std_logic_vector(12465269,24); manlo <= conv_std_logic_vector(236730454,28); exponent <= conv_std_logic_vector(1644,11); WHEN "0110110000" => manhi <= conv_std_logic_vector(3095113,24); manlo <= conv_std_logic_vector(133661452,28); exponent <= conv_std_logic_vector(1646,11); WHEN "0110110001" => manhi <= conv_std_logic_vector(10232080,24); manlo <= conv_std_logic_vector(21926822,28); exponent <= conv_std_logic_vector(1647,11); WHEN "0110110010" => manhi <= conv_std_logic_vector(1577503,24); manlo <= conv_std_logic_vector(183764948,28); exponent <= conv_std_logic_vector(1649,11); WHEN "0110110011" => manhi <= conv_std_logic_vector(8169434,24); manlo <= conv_std_logic_vector(132210812,28); exponent <= conv_std_logic_vector(1650,11); WHEN "0110110100" => manhi <= conv_std_logic_vector(175790,24); manlo <= conv_std_logic_vector(182183516,28); exponent <= conv_std_logic_vector(1652,11); WHEN "0110110101" => manhi <= conv_std_logic_vector(6264308,24); manlo <= conv_std_logic_vector(267417858,28); exponent <= conv_std_logic_vector(1653,11); WHEN "0110110110" => manhi <= conv_std_logic_vector(14539463,24); manlo <= conv_std_logic_vector(93573944,28); exponent <= conv_std_logic_vector(1654,11); WHEN "0110110111" => manhi <= conv_std_logic_vector(4504674,24); manlo <= conv_std_logic_vector(26907375,28); exponent <= conv_std_logic_vector(1656,11); WHEN "0110111000" => manhi <= conv_std_logic_vector(12147871,24); manlo <= conv_std_logic_vector(152302066,28); exponent <= conv_std_logic_vector(1657,11); WHEN "0110111001" => manhi <= conv_std_logic_vector(2879418,24); manlo <= conv_std_logic_vector(263131635,28); exponent <= conv_std_logic_vector(1659,11); WHEN "0110111010" => manhi <= conv_std_logic_vector(9938920,24); manlo <= conv_std_logic_vector(224874222,28); exponent <= conv_std_logic_vector(1660,11); WHEN "0110111011" => manhi <= conv_std_logic_vector(1378281,24); manlo <= conv_std_logic_vector(86745210,28); exponent <= conv_std_logic_vector(1662,11); WHEN "0110111100" => manhi <= conv_std_logic_vector(7898663,24); manlo <= conv_std_logic_vector(61761420,28); exponent <= conv_std_logic_vector(1663,11); WHEN "0110111101" => manhi <= conv_std_logic_vector(16760781,24); manlo <= conv_std_logic_vector(15082626,28); exponent <= conv_std_logic_vector(1664,11); WHEN "0110111110" => manhi <= conv_std_logic_vector(6014215,24); manlo <= conv_std_logic_vector(265801199,28); exponent <= conv_std_logic_vector(1666,11); WHEN "0110111111" => manhi <= conv_std_logic_vector(14199551,24); manlo <= conv_std_logic_vector(191056853,28); exponent <= conv_std_logic_vector(1667,11); WHEN "0111000000" => manhi <= conv_std_logic_vector(4273680,24); manlo <= conv_std_logic_vector(52024524,28); exponent <= conv_std_logic_vector(1669,11); WHEN "0111000001" => manhi <= conv_std_logic_vector(11833918,24); manlo <= conv_std_logic_vector(80047690,28); exponent <= conv_std_logic_vector(1670,11); WHEN "0111000010" => manhi <= conv_std_logic_vector(2666065,24); manlo <= conv_std_logic_vector(164712049,28); exponent <= conv_std_logic_vector(1672,11); WHEN "0111000011" => manhi <= conv_std_logic_vector(9648943,24); manlo <= conv_std_logic_vector(147084012,28); exponent <= conv_std_logic_vector(1673,11); WHEN "0111000100" => manhi <= conv_std_logic_vector(1181221,24); manlo <= conv_std_logic_vector(86912647,28); exponent <= conv_std_logic_vector(1675,11); WHEN "0111000101" => manhi <= conv_std_logic_vector(7630830,24); manlo <= conv_std_logic_vector(247596521,28); exponent <= conv_std_logic_vector(1676,11); WHEN "0111000110" => manhi <= conv_std_logic_vector(16396759,24); manlo <= conv_std_logic_vector(56002502,28); exponent <= conv_std_logic_vector(1677,11); WHEN "0111000111" => manhi <= conv_std_logic_vector(5766837,24); manlo <= conv_std_logic_vector(133369322,28); exponent <= conv_std_logic_vector(1679,11); WHEN "0111001000" => manhi <= conv_std_logic_vector(13863329,24); manlo <= conv_std_logic_vector(128884889,28); exponent <= conv_std_logic_vector(1680,11); WHEN "0111001001" => manhi <= conv_std_logic_vector(4045193,24); manlo <= conv_std_logic_vector(133729186,28); exponent <= conv_std_logic_vector(1682,11); WHEN "0111001010" => manhi <= conv_std_logic_vector(11523372,24); manlo <= conv_std_logic_vector(183024104,28); exponent <= conv_std_logic_vector(1683,11); WHEN "0111001011" => manhi <= conv_std_logic_vector(2455027,24); manlo <= conv_std_logic_vector(264977965,28); exponent <= conv_std_logic_vector(1685,11); WHEN "0111001100" => manhi <= conv_std_logic_vector(9362113,24); manlo <= conv_std_logic_vector(181285013,28); exponent <= conv_std_logic_vector(1686,11); WHEN "0111001101" => manhi <= conv_std_logic_vector(986300,24); manlo <= conv_std_logic_vector(58020653,28); exponent <= conv_std_logic_vector(1688,11); WHEN "0111001110" => manhi <= conv_std_logic_vector(7365905,24); manlo <= conv_std_logic_vector(179835810,28); exponent <= conv_std_logic_vector(1689,11); WHEN "0111001111" => manhi <= conv_std_logic_vector(16036688,24); manlo <= conv_std_logic_vector(123168298,28); exponent <= conv_std_logic_vector(1690,11); WHEN "0111010000" => manhi <= conv_std_logic_vector(5522144,24); manlo <= conv_std_logic_vector(14176725,28); exponent <= conv_std_logic_vector(1692,11); WHEN "0111010001" => manhi <= conv_std_logic_vector(13530756,24); manlo <= conv_std_logic_vector(163453775,28); exponent <= conv_std_logic_vector(1693,11); WHEN "0111010010" => manhi <= conv_std_logic_vector(3819186,24); manlo <= conv_std_logic_vector(214764608,28); exponent <= conv_std_logic_vector(1695,11); WHEN "0111010011" => manhi <= conv_std_logic_vector(11216197,24); manlo <= conv_std_logic_vector(196364225,28); exponent <= conv_std_logic_vector(1696,11); WHEN "0111010100" => manhi <= conv_std_logic_vector(2246280,24); manlo <= conv_std_logic_vector(259235483,28); exponent <= conv_std_logic_vector(1698,11); WHEN "0111010101" => manhi <= conv_std_logic_vector(9078397,24); manlo <= conv_std_logic_vector(15526664,28); exponent <= conv_std_logic_vector(1699,11); WHEN "0111010110" => manhi <= conv_std_logic_vector(793494,24); manlo <= conv_std_logic_vector(210641201,28); exponent <= conv_std_logic_vector(1701,11); WHEN "0111010111" => manhi <= conv_std_logic_vector(7103855,24); manlo <= conv_std_logic_vector(246847656,28); exponent <= conv_std_logic_vector(1702,11); WHEN "0111011000" => manhi <= conv_std_logic_vector(15680525,24); manlo <= conv_std_logic_vector(247378795,28); exponent <= conv_std_logic_vector(1703,11); WHEN "0111011001" => manhi <= conv_std_logic_vector(5280106,24); manlo <= conv_std_logic_vector(138122391,28); exponent <= conv_std_logic_vector(1705,11); WHEN "0111011010" => manhi <= conv_std_logic_vector(13201793,24); manlo <= conv_std_logic_vector(130963079,28); exponent <= conv_std_logic_vector(1706,11); WHEN "0111011011" => manhi <= conv_std_logic_vector(3595633,24); manlo <= conv_std_logic_vector(48727293,28); exponent <= conv_std_logic_vector(1708,11); WHEN "0111011100" => manhi <= conv_std_logic_vector(10912356,24); manlo <= conv_std_logic_vector(231400966,28); exponent <= conv_std_logic_vector(1709,11); WHEN "0111011101" => manhi <= conv_std_logic_vector(2039799,24); manlo <= conv_std_logic_vector(184459756,28); exponent <= conv_std_logic_vector(1711,11); WHEN "0111011110" => manhi <= conv_std_logic_vector(8797759,24); manlo <= conv_std_logic_vector(242699544,28); exponent <= conv_std_logic_vector(1712,11); WHEN "0111011111" => manhi <= conv_std_logic_vector(602782,24); manlo <= conv_std_logic_vector(17680793,28); exponent <= conv_std_logic_vector(1714,11); WHEN "0111100000" => manhi <= conv_std_logic_vector(6844650,24); manlo <= conv_std_logic_vector(123627565,28); exponent <= conv_std_logic_vector(1715,11); WHEN "0111100001" => manhi <= conv_std_logic_vector(15328229,24); manlo <= conv_std_logic_vector(47512453,28); exponent <= conv_std_logic_vector(1716,11); WHEN "0111100010" => manhi <= conv_std_logic_vector(5040696,24); manlo <= conv_std_logic_vector(14711664,28); exponent <= conv_std_logic_vector(1718,11); WHEN "0111100011" => manhi <= conv_std_logic_vector(12876400,24); manlo <= conv_std_logic_vector(251456186,28); exponent <= conv_std_logic_vector(1719,11); WHEN "0111100100" => manhi <= conv_std_logic_vector(3374506,24); manlo <= conv_std_logic_vector(4512772,28); exponent <= conv_std_logic_vector(1721,11); WHEN "0111100101" => manhi <= conv_std_logic_vector(10611813,24); manlo <= conv_std_logic_vector(237626642,28); exponent <= conv_std_logic_vector(1722,11); WHEN "0111100110" => manhi <= conv_std_logic_vector(1835559,24); manlo <= conv_std_logic_vector(150064655,28); exponent <= conv_std_logic_vector(1724,11); WHEN "0111100111" => manhi <= conv_std_logic_vector(8520168,24); manlo <= conv_std_logic_vector(211971382,28); exponent <= conv_std_logic_vector(1725,11); WHEN "0111101000" => manhi <= conv_std_logic_vector(414139,24); manlo <= conv_std_logic_vector(92694471,28); exponent <= conv_std_logic_vector(1727,11); WHEN "0111101001" => manhi <= conv_std_logic_vector(6588258,24); manlo <= conv_std_logic_vector(112977613,28); exponent <= conv_std_logic_vector(1728,11); WHEN "0111101010" => manhi <= conv_std_logic_vector(14979756,24); manlo <= conv_std_logic_vector(71348470,28); exponent <= conv_std_logic_vector(1729,11); WHEN "0111101011" => manhi <= conv_std_logic_vector(4803884,24); manlo <= conv_std_logic_vector(42747344,28); exponent <= conv_std_logic_vector(1731,11); WHEN "0111101100" => manhi <= conv_std_logic_vector(12554540,24); manlo <= conv_std_logic_vector(53825836,28); exponent <= conv_std_logic_vector(1732,11); WHEN "0111101101" => manhi <= conv_std_logic_vector(3155778,24); manlo <= conv_std_logic_vector(260157975,28); exponent <= conv_std_logic_vector(1734,11); WHEN "0111101110" => manhi <= conv_std_logic_vector(10314533,24); manlo <= conv_std_logic_vector(1535990,28); exponent <= conv_std_logic_vector(1735,11); WHEN "0111101111" => manhi <= conv_std_logic_vector(1633536,24); manlo <= conv_std_logic_vector(68681060,28); exponent <= conv_std_logic_vector(1737,11); WHEN "0111110000" => manhi <= conv_std_logic_vector(8245590,24); manlo <= conv_std_logic_vector(175202070,28); exponent <= conv_std_logic_vector(1738,11); WHEN "0111110001" => manhi <= conv_std_logic_vector(227544,24); manlo <= conv_std_logic_vector(41675965,28); exponent <= conv_std_logic_vector(1740,11); WHEN "0111110010" => manhi <= conv_std_logic_vector(6334649,24); manlo <= conv_std_logic_vector(70777607,28); exponent <= conv_std_logic_vector(1741,11); WHEN "0111110011" => manhi <= conv_std_logic_vector(14635065,24); manlo <= conv_std_logic_vector(183612561,28); exponent <= conv_std_logic_vector(1742,11); WHEN "0111110100" => manhi <= conv_std_logic_vector(4569642,24); manlo <= conv_std_logic_vector(167240760,28); exponent <= conv_std_logic_vector(1744,11); WHEN "0111110101" => manhi <= conv_std_logic_vector(12236172,24); manlo <= conv_std_logic_vector(253623266,28); exponent <= conv_std_logic_vector(1745,11); WHEN "0111110110" => manhi <= conv_std_logic_vector(2939425,24); manlo <= conv_std_logic_vector(265128301,28); exponent <= conv_std_logic_vector(1747,11); WHEN "0111110111" => manhi <= conv_std_logic_vector(10020478,24); manlo <= conv_std_logic_vector(219223569,28); exponent <= conv_std_logic_vector(1748,11); WHEN "0111111000" => manhi <= conv_std_logic_vector(1433705,24); manlo <= conv_std_logic_vector(192250058,28); exponent <= conv_std_logic_vector(1750,11); WHEN "0111111001" => manhi <= conv_std_logic_vector(7973992,24); manlo <= conv_std_logic_vector(212144821,28); exponent <= conv_std_logic_vector(1751,11); WHEN "0111111010" => manhi <= conv_std_logic_vector(42974,24); manlo <= conv_std_logic_vector(72952107,28); exponent <= conv_std_logic_vector(1753,11); WHEN "0111111011" => manhi <= conv_std_logic_vector(6083792,24); manlo <= conv_std_logic_vector(210315148,28); exponent <= conv_std_logic_vector(1754,11); WHEN "0111111100" => manhi <= conv_std_logic_vector(14294116,24); manlo <= conv_std_logic_vector(101520926,28); exponent <= conv_std_logic_vector(1755,11); WHEN "0111111101" => manhi <= conv_std_logic_vector(4337943,24); manlo <= conv_std_logic_vector(146945490,28); exponent <= conv_std_logic_vector(1757,11); WHEN "0111111110" => manhi <= conv_std_logic_vector(11921261,24); manlo <= conv_std_logic_vector(67478049,28); exponent <= conv_std_logic_vector(1758,11); WHEN "0111111111" => manhi <= conv_std_logic_vector(2725421,24); manlo <= conv_std_logic_vector(81662013,28); exponent <= conv_std_logic_vector(1760,11); WHEN "1000000000" => manhi <= conv_std_logic_vector(9729616,24); manlo <= conv_std_logic_vector(79332654,28); exponent <= conv_std_logic_vector(1761,11); WHEN "1000000001" => manhi <= conv_std_logic_vector(1236044,24); manlo <= conv_std_logic_vector(37511845,28); exponent <= conv_std_logic_vector(1763,11); WHEN "1000000010" => manhi <= conv_std_logic_vector(7705342,24); manlo <= conv_std_logic_vector(229400607,28); exponent <= conv_std_logic_vector(1764,11); WHEN "1000000011" => manhi <= conv_std_logic_vector(16498031,24); manlo <= conv_std_logic_vector(113896411,28); exponent <= conv_std_logic_vector(1765,11); WHEN "1000000100" => manhi <= conv_std_logic_vector(5835659,24); manlo <= conv_std_logic_vector(27578100,28); exponent <= conv_std_logic_vector(1767,11); WHEN "1000000101" => manhi <= conv_std_logic_vector(13956867,24); manlo <= conv_std_logic_vector(198774093,28); exponent <= conv_std_logic_vector(1768,11); WHEN "1000000110" => manhi <= conv_std_logic_vector(4108759,24); manlo <= conv_std_logic_vector(90336304,28); exponent <= conv_std_logic_vector(1770,11); WHEN "1000000111" => manhi <= conv_std_logic_vector(11609767,24); manlo <= conv_std_logic_vector(164675818,28); exponent <= conv_std_logic_vector(1771,11); WHEN "1000001000" => manhi <= conv_std_logic_vector(2513739,24); manlo <= conv_std_logic_vector(115510945,28); exponent <= conv_std_logic_vector(1773,11); WHEN "1000001001" => manhi <= conv_std_logic_vector(9441910,24); manlo <= conv_std_logic_vector(214725537,28); exponent <= conv_std_logic_vector(1774,11); WHEN "1000001010" => manhi <= conv_std_logic_vector(1040527,24); manlo <= conv_std_logic_vector(264292986,28); exponent <= conv_std_logic_vector(1776,11); WHEN "1000001011" => manhi <= conv_std_logic_vector(7439608,24); manlo <= conv_std_logic_vector(227819416,28); exponent <= conv_std_logic_vector(1777,11); WHEN "1000001100" => manhi <= conv_std_logic_vector(16136861,24); manlo <= conv_std_logic_vector(124712281,28); exponent <= conv_std_logic_vector(1778,11); WHEN "1000001101" => manhi <= conv_std_logic_vector(5590218,24); manlo <= conv_std_logic_vector(179347558,28); exponent <= conv_std_logic_vector(1780,11); WHEN "1000001110" => manhi <= conv_std_logic_vector(13623279,24); manlo <= conv_std_logic_vector(162081347,28); exponent <= conv_std_logic_vector(1781,11); WHEN "1000001111" => manhi <= conv_std_logic_vector(3882062,24); manlo <= conv_std_logic_vector(186291443,28); exponent <= conv_std_logic_vector(1783,11); WHEN "1000010000" => manhi <= conv_std_logic_vector(11301654,24); manlo <= conv_std_logic_vector(250040022,28); exponent <= conv_std_logic_vector(1784,11); WHEN "1000010001" => manhi <= conv_std_logic_vector(2304355,24); manlo <= conv_std_logic_vector(41383777,28); exponent <= conv_std_logic_vector(1786,11); WHEN "1000010010" => manhi <= conv_std_logic_vector(9157328,24); manlo <= conv_std_logic_vector(17021400,28); exponent <= conv_std_logic_vector(1787,11); WHEN "1000010011" => manhi <= conv_std_logic_vector(847133,24); manlo <= conv_std_logic_vector(258834653,28); exponent <= conv_std_logic_vector(1789,11); WHEN "1000010100" => manhi <= conv_std_logic_vector(7176759,24); manlo <= conv_std_logic_vector(33041815,28); exponent <= conv_std_logic_vector(1790,11); WHEN "1000010101" => manhi <= conv_std_logic_vector(15779611,24); manlo <= conv_std_logic_vector(174007449,28); exponent <= conv_std_logic_vector(1791,11); WHEN "1000010110" => manhi <= conv_std_logic_vector(5347442,24); manlo <= conv_std_logic_vector(66333886,28); exponent <= conv_std_logic_vector(1793,11); WHEN "1000010111" => manhi <= conv_std_logic_vector(13293312,24); manlo <= conv_std_logic_vector(63618366,28); exponent <= conv_std_logic_vector(1794,11); WHEN "1000011000" => manhi <= conv_std_logic_vector(3657826,24); manlo <= conv_std_logic_vector(166348998,28); exponent <= conv_std_logic_vector(1796,11); WHEN "1000011001" => manhi <= conv_std_logic_vector(10996886,24); manlo <= conv_std_logic_vector(136487624,28); exponent <= conv_std_logic_vector(1797,11); WHEN "1000011010" => manhi <= conv_std_logic_vector(2097243,24); manlo <= conv_std_logic_vector(144317262,28); exponent <= conv_std_logic_vector(1799,11); WHEN "1000011011" => manhi <= conv_std_logic_vector(8875834,24); manlo <= conv_std_logic_vector(51419886,28); exponent <= conv_std_logic_vector(1800,11); WHEN "1000011100" => manhi <= conv_std_logic_vector(655839,24); manlo <= conv_std_logic_vector(12096311,28); exponent <= conv_std_logic_vector(1802,11); WHEN "1000011101" => manhi <= conv_std_logic_vector(6916762,24); manlo <= conv_std_logic_vector(99793437,28); exponent <= conv_std_logic_vector(1803,11); WHEN "1000011110" => manhi <= conv_std_logic_vector(15426239,24); manlo <= conv_std_logic_vector(114334116,28); exponent <= conv_std_logic_vector(1804,11); WHEN "1000011111" => manhi <= conv_std_logic_vector(5107300,24); manlo <= conv_std_logic_vector(248161218,28); exponent <= conv_std_logic_vector(1806,11); WHEN "1000100000" => manhi <= conv_std_logic_vector(12966926,24); manlo <= conv_std_logic_vector(91321506,28); exponent <= conv_std_logic_vector(1807,11); WHEN "1000100001" => manhi <= conv_std_logic_vector(3436024,24); manlo <= conv_std_logic_vector(109150055,28); exponent <= conv_std_logic_vector(1809,11); WHEN "1000100010" => manhi <= conv_std_logic_vector(10695426,24); manlo <= conv_std_logic_vector(12291314,28); exponent <= conv_std_logic_vector(1810,11); WHEN "1000100011" => manhi <= conv_std_logic_vector(1892379,24); manlo <= conv_std_logic_vector(245137096,28); exponent <= conv_std_logic_vector(1812,11); WHEN "1000100100" => manhi <= conv_std_logic_vector(8597395,24); manlo <= conv_std_logic_vector(176569250,28); exponent <= conv_std_logic_vector(1813,11); WHEN "1000100101" => manhi <= conv_std_logic_vector(466620,24); manlo <= conv_std_logic_vector(119019308,28); exponent <= conv_std_logic_vector(1815,11); WHEN "1000100110" => manhi <= conv_std_logic_vector(6659587,24); manlo <= conv_std_logic_vector(168706814,28); exponent <= conv_std_logic_vector(1816,11); WHEN "1000100111" => manhi <= conv_std_logic_vector(15076702,24); manlo <= conv_std_logic_vector(190651618,28); exponent <= conv_std_logic_vector(1817,11); WHEN "1000101000" => manhi <= conv_std_logic_vector(4869766,24); manlo <= conv_std_logic_vector(26523901,28); exponent <= conv_std_logic_vector(1819,11); WHEN "1000101001" => manhi <= conv_std_logic_vector(12644083,24); manlo <= conv_std_logic_vector(10760420,28); exponent <= conv_std_logic_vector(1820,11); WHEN "1000101010" => manhi <= conv_std_logic_vector(3216629,24); manlo <= conv_std_logic_vector(171149379,28); exponent <= conv_std_logic_vector(1822,11); WHEN "1000101011" => manhi <= conv_std_logic_vector(10397237,24); manlo <= conv_std_logic_vector(171483537,28); exponent <= conv_std_logic_vector(1823,11); WHEN "1000101100" => manhi <= conv_std_logic_vector(1689739,24); manlo <= conv_std_logic_vector(236540182,28); exponent <= conv_std_logic_vector(1825,11); WHEN "1000101101" => manhi <= conv_std_logic_vector(8321979,24); manlo <= conv_std_logic_vector(80365386,28); exponent <= conv_std_logic_vector(1826,11); WHEN "1000101110" => manhi <= conv_std_logic_vector(279455,24); manlo <= conv_std_logic_vector(167185714,28); exponent <= conv_std_logic_vector(1828,11); WHEN "1000101111" => manhi <= conv_std_logic_vector(6405204,24); manlo <= conv_std_logic_vector(70637708,28); exponent <= conv_std_logic_vector(1829,11); WHEN "1000110000" => manhi <= conv_std_logic_vector(14730959,24); manlo <= conv_std_logic_vector(233674466,28); exponent <= conv_std_logic_vector(1830,11); WHEN "1000110001" => manhi <= conv_std_logic_vector(4634809,24); manlo <= conv_std_logic_vector(128626627,28); exponent <= conv_std_logic_vector(1832,11); WHEN "1000110010" => manhi <= conv_std_logic_vector(12324743,24); manlo <= conv_std_logic_vector(237637056,28); exponent <= conv_std_logic_vector(1833,11); WHEN "1000110011" => manhi <= conv_std_logic_vector(2999616,24); manlo <= conv_std_logic_vector(48899908,28); exponent <= conv_std_logic_vector(1835,11); WHEN "1000110100" => manhi <= conv_std_logic_vector(10102285,24); manlo <= conv_std_logic_vector(207402206,28); exponent <= conv_std_logic_vector(1836,11); WHEN "1000110101" => manhi <= conv_std_logic_vector(1489299,24); manlo <= conv_std_logic_vector(82314533,28); exponent <= conv_std_logic_vector(1838,11); WHEN "1000110110" => manhi <= conv_std_logic_vector(8049552,24); manlo <= conv_std_logic_vector(84197942,28); exponent <= conv_std_logic_vector(1839,11); WHEN "1000110111" => manhi <= conv_std_logic_vector(94322,24); manlo <= conv_std_logic_vector(78275083,28); exponent <= conv_std_logic_vector(1841,11); WHEN "1000111000" => manhi <= conv_std_logic_vector(6153581,24); manlo <= conv_std_logic_vector(262556746,28); exponent <= conv_std_logic_vector(1842,11); WHEN "1000111001" => manhi <= conv_std_logic_vector(14388969,24); manlo <= conv_std_logic_vector(195412276,28); exponent <= conv_std_logic_vector(1843,11); WHEN "1000111010" => manhi <= conv_std_logic_vector(4402403,24); manlo <= conv_std_logic_vector(21925377,28); exponent <= conv_std_logic_vector(1845,11); WHEN "1000111011" => manhi <= conv_std_logic_vector(12008870,24); manlo <= conv_std_logic_vector(225943576,28); exponent <= conv_std_logic_vector(1846,11); WHEN "1000111100" => manhi <= conv_std_logic_vector(2784958,24); manlo <= conv_std_logic_vector(51959162,28); exponent <= conv_std_logic_vector(1848,11); WHEN "1000111101" => manhi <= conv_std_logic_vector(9810535,24); manlo <= conv_std_logic_vector(85297068,28); exponent <= conv_std_logic_vector(1849,11); WHEN "1000111110" => manhi <= conv_std_logic_vector(1291034,24); manlo <= conv_std_logic_vector(85003113,28); exponent <= conv_std_logic_vector(1851,11); WHEN "1000111111" => manhi <= conv_std_logic_vector(7780082,24); manlo <= conv_std_logic_vector(68159752,28); exponent <= conv_std_logic_vector(1852,11); WHEN "1001000000" => manhi <= conv_std_logic_vector(16599612,24); manlo <= conv_std_logic_vector(214703512,28); exponent <= conv_std_logic_vector(1853,11); WHEN "1001000001" => manhi <= conv_std_logic_vector(5904690,24); manlo <= conv_std_logic_vector(215968023,28); exponent <= conv_std_logic_vector(1855,11); WHEN "1001000010" => manhi <= conv_std_logic_vector(14050691,24); manlo <= conv_std_logic_vector(147853227,28); exponent <= conv_std_logic_vector(1856,11); WHEN "1001000011" => manhi <= conv_std_logic_vector(4172519,24); manlo <= conv_std_logic_vector(60716388,28); exponent <= conv_std_logic_vector(1858,11); WHEN "1001000100" => manhi <= conv_std_logic_vector(11696426,24); manlo <= conv_std_logic_vector(77359100,28); exponent <= conv_std_logic_vector(1859,11); WHEN "1001000101" => manhi <= conv_std_logic_vector(2572630,24); manlo <= conv_std_logic_vector(28321055,28); exponent <= conv_std_logic_vector(1861,11); WHEN "1001000110" => manhi <= conv_std_logic_vector(9521951,24); manlo <= conv_std_logic_vector(141206574,28); exponent <= conv_std_logic_vector(1862,11); WHEN "1001000111" => manhi <= conv_std_logic_vector(1094921,24); manlo <= conv_std_logic_vector(79834212,28); exponent <= conv_std_logic_vector(1864,11); WHEN "1001001000" => manhi <= conv_std_logic_vector(7513537,24); manlo <= conv_std_logic_vector(6880382,28); exponent <= conv_std_logic_vector(1865,11); WHEN "1001001001" => manhi <= conv_std_logic_vector(16237340,24); manlo <= conv_std_logic_vector(73707069,28); exponent <= conv_std_logic_vector(1866,11); WHEN "1001001010" => manhi <= conv_std_logic_vector(5658501,24); manlo <= conv_std_logic_vector(26563701,28); exponent <= conv_std_logic_vector(1868,11); WHEN "1001001011" => manhi <= conv_std_logic_vector(13716085,24); manlo <= conv_std_logic_vector(13226359,28); exponent <= conv_std_logic_vector(1869,11); WHEN "1001001100" => manhi <= conv_std_logic_vector(3945130,24); manlo <= conv_std_logic_vector(143073903,28); exponent <= conv_std_logic_vector(1871,11); WHEN "1001001101" => manhi <= conv_std_logic_vector(11387373,24); manlo <= conv_std_logic_vector(3175990,28); exponent <= conv_std_logic_vector(1872,11); WHEN "1001001110" => manhi <= conv_std_logic_vector(2362606,24); manlo <= conv_std_logic_vector(168904878,28); exponent <= conv_std_logic_vector(1874,11); WHEN "1001001111" => manhi <= conv_std_logic_vector(9236500,24); manlo <= conv_std_logic_vector(7105104,28); exponent <= conv_std_logic_vector(1875,11); WHEN "1001010000" => manhi <= conv_std_logic_vector(900936,24); manlo <= conv_std_logic_vector(239272854,28); exponent <= conv_std_logic_vector(1877,11); WHEN "1001010001" => manhi <= conv_std_logic_vector(7249884,24); manlo <= conv_std_logic_vector(236935482,28); exponent <= conv_std_logic_vector(1878,11); WHEN "1001010010" => manhi <= conv_std_logic_vector(15878999,24); manlo <= conv_std_logic_vector(230836932,28); exponent <= conv_std_logic_vector(1879,11); WHEN "1001010011" => manhi <= conv_std_logic_vector(5414983,24); manlo <= conv_std_logic_vector(144840810,28); exponent <= conv_std_logic_vector(1881,11); WHEN "1001010100" => manhi <= conv_std_logic_vector(13385110,24); manlo <= conv_std_logic_vector(99584369,28); exponent <= conv_std_logic_vector(1882,11); WHEN "1001010101" => manhi <= conv_std_logic_vector(3720209,24); manlo <= conv_std_logic_vector(246845719,28); exponent <= conv_std_logic_vector(1884,11); WHEN "1001010110" => manhi <= conv_std_logic_vector(11081674,24); manlo <= conv_std_logic_vector(54674652,28); exponent <= conv_std_logic_vector(1885,11); WHEN "1001010111" => manhi <= conv_std_logic_vector(2154862,24); manlo <= conv_std_logic_vector(201440422,28); exponent <= conv_std_logic_vector(1887,11); WHEN "1001011000" => manhi <= conv_std_logic_vector(8954146,24); manlo <= conv_std_logic_vector(220416825,28); exponent <= conv_std_logic_vector(1888,11); WHEN "1001011001" => manhi <= conv_std_logic_vector(709057,24); manlo <= conv_std_logic_vector(266967657,28); exponent <= conv_std_logic_vector(1890,11); WHEN "1001011010" => manhi <= conv_std_logic_vector(6989094,24); manlo <= conv_std_logic_vector(113654547,28); exponent <= conv_std_logic_vector(1891,11); WHEN "1001011011" => manhi <= conv_std_logic_vector(15524548,24); manlo <= conv_std_logic_vector(235342013,28); exponent <= conv_std_logic_vector(1892,11); WHEN "1001011100" => manhi <= conv_std_logic_vector(5174109,24); manlo <= conv_std_logic_vector(32986511,28); exponent <= conv_std_logic_vector(1894,11); WHEN "1001011101" => manhi <= conv_std_logic_vector(13057728,24); manlo <= conv_std_logic_vector(25787653,28); exponent <= conv_std_logic_vector(1895,11); WHEN "1001011110" => manhi <= conv_std_logic_vector(3497730,24); manlo <= conv_std_logic_vector(160351868,28); exponent <= conv_std_logic_vector(1897,11); WHEN "1001011111" => manhi <= conv_std_logic_vector(10779293,24); manlo <= conv_std_logic_vector(121946709,28); exponent <= conv_std_logic_vector(1898,11); WHEN "1001100000" => manhi <= conv_std_logic_vector(1949373,24); manlo <= conv_std_logic_vector(194974600,28); exponent <= conv_std_logic_vector(1900,11); WHEN "1001100001" => manhi <= conv_std_logic_vector(8674858,24); manlo <= conv_std_logic_vector(75445083,28); exponent <= conv_std_logic_vector(1901,11); WHEN "1001100010" => manhi <= conv_std_logic_vector(519261,24); manlo <= conv_std_logic_vector(202318540,28); exponent <= conv_std_logic_vector(1903,11); WHEN "1001100011" => manhi <= conv_std_logic_vector(6731134,24); manlo <= conv_std_logic_vector(157600610,28); exponent <= conv_std_logic_vector(1904,11); WHEN "1001100100" => manhi <= conv_std_logic_vector(15173945,24); manlo <= conv_std_logic_vector(29256816,28); exponent <= conv_std_logic_vector(1905,11); WHEN "1001100101" => manhi <= conv_std_logic_vector(4935849,24); manlo <= conv_std_logic_vector(42999013,28); exponent <= conv_std_logic_vector(1907,11); WHEN "1001100110" => manhi <= conv_std_logic_vector(12733899,24); manlo <= conv_std_logic_vector(62421287,28); exponent <= conv_std_logic_vector(1908,11); WHEN "1001100111" => manhi <= conv_std_logic_vector(3277666,24); manlo <= conv_std_logic_vector(18399062,28); exponent <= conv_std_logic_vector(1910,11); WHEN "1001101000" => manhi <= conv_std_logic_vector(10480194,24); manlo <= conv_std_logic_vector(201166396,28); exponent <= conv_std_logic_vector(1911,11); WHEN "1001101001" => manhi <= conv_std_logic_vector(1746115,24); manlo <= conv_std_logic_vector(22209480,28); exponent <= conv_std_logic_vector(1913,11); WHEN "1001101010" => manhi <= conv_std_logic_vector(8398601,24); manlo <= conv_std_logic_vector(38216343,28); exponent <= conv_std_logic_vector(1914,11); WHEN "1001101011" => manhi <= conv_std_logic_vector(331525,24); manlo <= conv_std_logic_vector(151310615,28); exponent <= conv_std_logic_vector(1916,11); WHEN "1001101100" => manhi <= conv_std_logic_vector(6475974,24); manlo <= conv_std_logic_vector(174528998,28); exponent <= conv_std_logic_vector(1917,11); WHEN "1001101101" => manhi <= conv_std_logic_vector(14827146,24); manlo <= conv_std_logic_vector(214487191,28); exponent <= conv_std_logic_vector(1918,11); WHEN "1001101110" => manhi <= conv_std_logic_vector(4700175,24); manlo <= conv_std_logic_vector(73593076,28); exponent <= conv_std_logic_vector(1920,11); WHEN "1001101111" => manhi <= conv_std_logic_vector(12413585,24); manlo <= conv_std_logic_vector(56806573,28); exponent <= conv_std_logic_vector(1921,11); WHEN "1001110000" => manhi <= conv_std_logic_vector(3059990,24); manlo <= conv_std_logic_vector(32998071,28); exponent <= conv_std_logic_vector(1923,11); WHEN "1001110001" => manhi <= conv_std_logic_vector(10184342,24); manlo <= conv_std_logic_vector(125003687,28); exponent <= conv_std_logic_vector(1924,11); WHEN "1001110010" => manhi <= conv_std_logic_vector(1545062,24); manlo <= conv_std_logic_vector(164026180,28); exponent <= conv_std_logic_vector(1926,11); WHEN "1001110011" => manhi <= conv_std_logic_vector(8125342,24); manlo <= conv_std_logic_vector(134803968,28); exponent <= conv_std_logic_vector(1927,11); WHEN "1001110100" => manhi <= conv_std_logic_vector(145827,24); manlo <= conv_std_logic_vector(17356019,28); exponent <= conv_std_logic_vector(1929,11); WHEN "1001110101" => manhi <= conv_std_logic_vector(6223584,24); manlo <= conv_std_logic_vector(59711433,28); exponent <= conv_std_logic_vector(1930,11); WHEN "1001110110" => manhi <= conv_std_logic_vector(14484112,24); manlo <= conv_std_logic_vector(172427100,28); exponent <= conv_std_logic_vector(1931,11); WHEN "1001110111" => manhi <= conv_std_logic_vector(4467059,24); manlo <= conv_std_logic_vector(106163660,28); exponent <= conv_std_logic_vector(1933,11); WHEN "1001111000" => manhi <= conv_std_logic_vector(12096747,24); manlo <= conv_std_logic_vector(237074316,28); exponent <= conv_std_logic_vector(1934,11); WHEN "1001111001" => manhi <= conv_std_logic_vector(2844676,24); manlo <= conv_std_logic_vector(224090291,28); exponent <= conv_std_logic_vector(1936,11); WHEN "1001111010" => manhi <= conv_std_logic_vector(9891701,24); manlo <= conv_std_logic_vector(98356275,28); exponent <= conv_std_logic_vector(1937,11); WHEN "1001111011" => manhi <= conv_std_logic_vector(1346192,24); manlo <= conv_std_logic_vector(98098154,28); exponent <= conv_std_logic_vector(1939,11); WHEN "1001111100" => manhi <= conv_std_logic_vector(7855049,24); manlo <= conv_std_logic_vector(218711727,28); exponent <= conv_std_logic_vector(1940,11); WHEN "1001111101" => manhi <= conv_std_logic_vector(16701504,24); manlo <= conv_std_logic_vector(74899902,28); exponent <= conv_std_logic_vector(1941,11); WHEN "1001111110" => manhi <= conv_std_logic_vector(5973933,24); manlo <= conv_std_logic_vector(65399866,28); exponent <= conv_std_logic_vector(1943,11); WHEN "1001111111" => manhi <= conv_std_logic_vector(14144801,24); manlo <= conv_std_logic_vector(210121699,28); exponent <= conv_std_logic_vector(1944,11); WHEN "1010000000" => manhi <= conv_std_logic_vector(4236473,24); manlo <= conv_std_logic_vector(203888522,28); exponent <= conv_std_logic_vector(1946,11); WHEN "1010000001" => manhi <= conv_std_logic_vector(11783349,24); manlo <= conv_std_logic_vector(137203293,28); exponent <= conv_std_logic_vector(1947,11); WHEN "1010000010" => manhi <= conv_std_logic_vector(2631700,24); manlo <= conv_std_logic_vector(150283410,28); exponent <= conv_std_logic_vector(1949,11); WHEN "1010000011" => manhi <= conv_std_logic_vector(9602236,24); manlo <= conv_std_logic_vector(160352104,28); exponent <= conv_std_logic_vector(1950,11); WHEN "1010000100" => manhi <= conv_std_logic_vector(1149480,24); manlo <= conv_std_logic_vector(177173803,28); exponent <= conv_std_logic_vector(1952,11); WHEN "1010000101" => manhi <= conv_std_logic_vector(7587690,24); manlo <= conv_std_logic_vector(238268718,28); exponent <= conv_std_logic_vector(1953,11); WHEN "1010000110" => manhi <= conv_std_logic_vector(16338125,24); manlo <= conv_std_logic_vector(220749839,28); exponent <= conv_std_logic_vector(1954,11); WHEN "1010000111" => manhi <= conv_std_logic_vector(5726991,24); manlo <= conv_std_logic_vector(262994505,28); exponent <= conv_std_logic_vector(1956,11); WHEN "1010001000" => manhi <= conv_std_logic_vector(13809173,24); manlo <= conv_std_logic_vector(216783842,28); exponent <= conv_std_logic_vector(1957,11); WHEN "1010001001" => manhi <= conv_std_logic_vector(4008390,24); manlo <= conv_std_logic_vector(242405077,28); exponent <= conv_std_logic_vector(1959,11); WHEN "1010001010" => manhi <= conv_std_logic_vector(11473352,24); manlo <= conv_std_logic_vector(206426515,28); exponent <= conv_std_logic_vector(1960,11); WHEN "1010001011" => manhi <= conv_std_logic_vector(2421035,24); manlo <= conv_std_logic_vector(250208807,28); exponent <= conv_std_logic_vector(1962,11); WHEN "1010001100" => manhi <= conv_std_logic_vector(9315913,24); manlo <= conv_std_logic_vector(183235034,28); exponent <= conv_std_logic_vector(1963,11); WHEN "1010001101" => manhi <= conv_std_logic_vector(954904,24); manlo <= conv_std_logic_vector(17706469,28); exponent <= conv_std_logic_vector(1965,11); WHEN "1010001110" => manhi <= conv_std_logic_vector(7323233,24); manlo <= conv_std_logic_vector(235600136,28); exponent <= conv_std_logic_vector(1966,11); WHEN "1010001111" => manhi <= conv_std_logic_vector(15978691,24); manlo <= conv_std_logic_vector(128873524,28); exponent <= conv_std_logic_vector(1967,11); WHEN "1010010000" => manhi <= conv_std_logic_vector(5482731,24); manlo <= conv_std_logic_vector(5222268,28); exponent <= conv_std_logic_vector(1969,11); WHEN "1010010001" => manhi <= conv_std_logic_vector(13477188,24); manlo <= conv_std_logic_vector(199372940,28); exponent <= conv_std_logic_vector(1970,11); WHEN "1010010010" => manhi <= conv_std_logic_vector(3782783,24); manlo <= conv_std_logic_vector(177367827,28); exponent <= conv_std_logic_vector(1972,11); WHEN "1010010011" => manhi <= conv_std_logic_vector(11166720,24); manlo <= conv_std_logic_vector(197425116,28); exponent <= conv_std_logic_vector(1973,11); WHEN "1010010100" => manhi <= conv_std_logic_vector(2212657,24); manlo <= conv_std_logic_vector(231097832,28); exponent <= conv_std_logic_vector(1975,11); WHEN "1010010101" => manhi <= conv_std_logic_vector(9032698,24); manlo <= conv_std_logic_vector(139698050,28); exponent <= conv_std_logic_vector(1976,11); WHEN "1010010110" => manhi <= conv_std_logic_vector(762439,24); manlo <= conv_std_logic_vector(109718127,28); exponent <= conv_std_logic_vector(1978,11); WHEN "1010010111" => manhi <= conv_std_logic_vector(7061647,24); manlo <= conv_std_logic_vector(77173752,28); exponent <= conv_std_logic_vector(1979,11); WHEN "1010011000" => manhi <= conv_std_logic_vector(15623158,24); manlo <= conv_std_logic_vector(118851961,28); exponent <= conv_std_logic_vector(1980,11); WHEN "1010011001" => manhi <= conv_std_logic_vector(5241121,24); manlo <= conv_std_logic_vector(72680114,28); exponent <= conv_std_logic_vector(1982,11); WHEN "1010011010" => manhi <= conv_std_logic_vector(13148807,24); manlo <= conv_std_logic_vector(12881486,28); exponent <= conv_std_logic_vector(1983,11); WHEN "1010011011" => manhi <= conv_std_logic_vector(3559625,24); manlo <= conv_std_logic_vector(43579850,28); exponent <= conv_std_logic_vector(1985,11); WHEN "1010011100" => manhi <= conv_std_logic_vector(10863416,24); manlo <= conv_std_logic_vector(238889758,28); exponent <= conv_std_logic_vector(1986,11); WHEN "1010011101" => manhi <= conv_std_logic_vector(2006541,24); manlo <= conv_std_logic_vector(141721451,28); exponent <= conv_std_logic_vector(1988,11); WHEN "1010011110" => manhi <= conv_std_logic_vector(8752557,24); manlo <= conv_std_logic_vector(101792997,28); exponent <= conv_std_logic_vector(1989,11); WHEN "1010011111" => manhi <= conv_std_logic_vector(572063,24); manlo <= conv_std_logic_vector(205445723,28); exponent <= conv_std_logic_vector(1991,11); WHEN "1010100000" => manhi <= conv_std_logic_vector(6802899,24); manlo <= conv_std_logic_vector(258099270,28); exponent <= conv_std_logic_vector(1992,11); WHEN "1010100001" => manhi <= conv_std_logic_vector(15271484,24); manlo <= conv_std_logic_vector(98124990,28); exponent <= conv_std_logic_vector(1993,11); WHEN "1010100010" => manhi <= conv_std_logic_vector(5002133,24); manlo <= conv_std_logic_vector(256985826,28); exponent <= conv_std_logic_vector(1995,11); WHEN "1010100011" => manhi <= conv_std_logic_vector(12823989,24); manlo <= conv_std_logic_vector(164377270,28); exponent <= conv_std_logic_vector(1996,11); WHEN "1010100100" => manhi <= conv_std_logic_vector(3338888,24); manlo <= conv_std_logic_vector(222569178,28); exponent <= conv_std_logic_vector(1998,11); WHEN "1010100101" => manhi <= conv_std_logic_vector(10563405,24); manlo <= conv_std_logic_vector(29046646,28); exponent <= conv_std_logic_vector(1999,11); WHEN "1010100110" => manhi <= conv_std_logic_vector(1802662,24); manlo <= conv_std_logic_vector(103161316,28); exponent <= conv_std_logic_vector(2001,11); WHEN "1010100111" => manhi <= conv_std_logic_vector(8475456,24); manlo <= conv_std_logic_vector(239852126,28); exponent <= conv_std_logic_vector(2002,11); WHEN "1010101000" => manhi <= conv_std_logic_vector(383754,24); manlo <= conv_std_logic_vector(123914668,28); exponent <= conv_std_logic_vector(2004,11); WHEN "1010101001" => manhi <= conv_std_logic_vector(6546961,24); manlo <= conv_std_logic_vector(22084044,28); exponent <= conv_std_logic_vector(2005,11); WHEN "1010101010" => manhi <= conv_std_logic_vector(14923627,24); manlo <= conv_std_logic_vector(97508377,28); exponent <= conv_std_logic_vector(2006,11); WHEN "1010101011" => manhi <= conv_std_logic_vector(4765740,24); manlo <= conv_std_logic_vector(165164368,28); exponent <= conv_std_logic_vector(2008,11); WHEN "1010101100" => manhi <= conv_std_logic_vector(12502697,24); manlo <= conv_std_logic_vector(201140216,28); exponent <= conv_std_logic_vector(2009,11); WHEN "1010101101" => manhi <= conv_std_logic_vector(3120548,24); manlo <= conv_std_logic_vector(99561759,28); exponent <= conv_std_logic_vector(2011,11); WHEN "1010101110" => manhi <= conv_std_logic_vector(10266649,24); manlo <= conv_std_logic_vector(176679877,28); exponent <= conv_std_logic_vector(2012,11); WHEN "1010101111" => manhi <= conv_std_logic_vector(1600996,24); manlo <= conv_std_logic_vector(39589446,28); exponent <= conv_std_logic_vector(2014,11); WHEN "1010110000" => manhi <= conv_std_logic_vector(8201364,24); manlo <= conv_std_logic_vector(16114999,28); exponent <= conv_std_logic_vector(2015,11); WHEN "1010110001" => manhi <= conv_std_logic_vector(197489,24); manlo <= conv_std_logic_vector(18649371,28); exponent <= conv_std_logic_vector(2017,11); WHEN "1010110010" => manhi <= conv_std_logic_vector(6293800,24); manlo <= conv_std_logic_vector(44802372,28); exponent <= conv_std_logic_vector(2018,11); WHEN "1010110011" => manhi <= conv_std_logic_vector(14579546,24); manlo <= conv_std_logic_vector(1419236,28); exponent <= conv_std_logic_vector(2019,11); WHEN "1010110100" => manhi <= conv_std_logic_vector(4531913,24); manlo <= conv_std_logic_vector(24044223,28); exponent <= conv_std_logic_vector(2021,11); WHEN "1010110101" => manhi <= conv_std_logic_vector(12184893,24); manlo <= conv_std_logic_vector(51602800,28); exponent <= conv_std_logic_vector(2022,11); WHEN "1010110110" => manhi <= conv_std_logic_vector(2904577,24); manlo <= conv_std_logic_vector(210124577,28); exponent <= conv_std_logic_vector(2024,11); WHEN "1010110111" => manhi <= conv_std_logic_vector(9973115,24); manlo <= conv_std_logic_vector(52505388,28); exponent <= conv_std_logic_vector(2025,11); WHEN "1010111000" => manhi <= conv_std_logic_vector(1401518,24); manlo <= conv_std_logic_vector(214362802,28); exponent <= conv_std_logic_vector(2027,11); WHEN "1010111001" => manhi <= conv_std_logic_vector(7930246,24); manlo <= conv_std_logic_vector(62721516,28); exponent <= conv_std_logic_vector(2028,11); WHEN "1010111010" => manhi <= conv_std_logic_vector(13245,24); manlo <= conv_std_logic_vector(108520727,28); exponent <= conv_std_logic_vector(2030,11); WHEN "1010111011" => manhi <= conv_std_logic_vector(6043387,24); manlo <= conv_std_logic_vector(17001813,28); exponent <= conv_std_logic_vector(2031,11); WHEN "1010111100" => manhi <= conv_std_logic_vector(14239199,24); manlo <= conv_std_logic_vector(83422350,28); exponent <= conv_std_logic_vector(2032,11); WHEN "1010111101" => manhi <= conv_std_logic_vector(4300623,24); manlo <= conv_std_logic_vector(142486326,28); exponent <= conv_std_logic_vector(2034,11); WHEN "1010111110" => manhi <= conv_std_logic_vector(11870538,24); manlo <= conv_std_logic_vector(24126621,28); exponent <= conv_std_logic_vector(2035,11); WHEN "1010111111" => manhi <= conv_std_logic_vector(2690951,24); manlo <= conv_std_logic_vector(91850592,28); exponent <= conv_std_logic_vector(2037,11); WHEN "1011000000" => manhi <= conv_std_logic_vector(9682766,24); manlo <= conv_std_logic_vector(203960059,28); exponent <= conv_std_logic_vector(2038,11); WHEN "1011000001" => manhi <= conv_std_logic_vector(1204206,24); manlo <= conv_std_logic_vector(155513539,28); exponent <= conv_std_logic_vector(2040,11); WHEN "1011000010" => manhi <= conv_std_logic_vector(7662071,24); manlo <= conv_std_logic_vector(33184566,28); exponent <= conv_std_logic_vector(2041,11); WHEN "1011000011" => manhi <= conv_std_logic_vector(16439219,24); manlo <= conv_std_logic_vector(11896414,28); exponent <= conv_std_logic_vector(2042,11); WHEN "1011000100" => manhi <= conv_std_logic_vector(5795691,24); manlo <= conv_std_logic_vector(254151921,28); exponent <= conv_std_logic_vector(2044,11); WHEN "1011000101" => manhi <= conv_std_logic_vector(13902546,24); manlo <= conv_std_logic_vector(199613595,28); exponent <= conv_std_logic_vector(2045,11); WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_explutpos IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_explutpos; ARCHITECTURE rtl OF dp_explutpos IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(1023,11); WHEN "0000000001" => manhi <= conv_std_logic_vector(6025384,24); manlo <= conv_std_logic_vector(185882474,28); exponent <= conv_std_logic_vector(1024,11); WHEN "0000000010" => manhi <= conv_std_logic_vector(14214731,24); manlo <= conv_std_logic_vector(148168110,28); exponent <= conv_std_logic_vector(1025,11); WHEN "0000000011" => manhi <= conv_std_logic_vector(4283995,24); manlo <= conv_std_logic_vector(258978054,28); exponent <= conv_std_logic_vector(1027,11); WHEN "0000000100" => manhi <= conv_std_logic_vector(11847938,24); manlo <= conv_std_logic_vector(237451864,28); exponent <= conv_std_logic_vector(1028,11); WHEN "0000000101" => manhi <= conv_std_logic_vector(2675593,24); manlo <= conv_std_logic_vector(158348175,28); exponent <= conv_std_logic_vector(1030,11); WHEN "0000000110" => manhi <= conv_std_logic_vector(9661893,24); manlo <= conv_std_logic_vector(110149775,28); exponent <= conv_std_logic_vector(1031,11); WHEN "0000000111" => manhi <= conv_std_logic_vector(1190021,24); manlo <= conv_std_logic_vector(179232170,28); exponent <= conv_std_logic_vector(1033,11); WHEN "0000001000" => manhi <= conv_std_logic_vector(7642791,24); manlo <= conv_std_logic_vector(222760046,28); exponent <= conv_std_logic_vector(1034,11); WHEN "0000001001" => manhi <= conv_std_logic_vector(16413015,24); manlo <= conv_std_logic_vector(205983618,28); exponent <= conv_std_logic_vector(1035,11); WHEN "0000001010" => manhi <= conv_std_logic_vector(5777884,24); manlo <= conv_std_logic_vector(261424480,28); exponent <= conv_std_logic_vector(1037,11); WHEN "0000001011" => manhi <= conv_std_logic_vector(13878344,24); manlo <= conv_std_logic_vector(149835647,28); exponent <= conv_std_logic_vector(1038,11); WHEN "0000001100" => manhi <= conv_std_logic_vector(4055397,24); manlo <= conv_std_logic_vector(80968858,28); exponent <= conv_std_logic_vector(1040,11); WHEN "0000001101" => manhi <= conv_std_logic_vector(11537241,24); manlo <= conv_std_logic_vector(23775573,28); exponent <= conv_std_logic_vector(1041,11); WHEN "0000001110" => manhi <= conv_std_logic_vector(2464452,24); manlo <= conv_std_logic_vector(146736599,28); exponent <= conv_std_logic_vector(1043,11); WHEN "0000001111" => manhi <= conv_std_logic_vector(9374922,24); manlo <= conv_std_logic_vector(263006855,28); exponent <= conv_std_logic_vector(1044,11); WHEN "0000010000" => manhi <= conv_std_logic_vector(995005,24); manlo <= conv_std_logic_vector(11010080,28); exponent <= conv_std_logic_vector(1046,11); WHEN "0000010001" => manhi <= conv_std_logic_vector(7377736,24); manlo <= conv_std_logic_vector(202286329,28); exponent <= conv_std_logic_vector(1047,11); WHEN "0000010010" => manhi <= conv_std_logic_vector(16052768,24); manlo <= conv_std_logic_vector(152649917,28); exponent <= conv_std_logic_vector(1048,11); WHEN "0000010011" => manhi <= conv_std_logic_vector(5533071,24); manlo <= conv_std_logic_vector(166536930,28); exponent <= conv_std_logic_vector(1050,11); WHEN "0000010100" => manhi <= conv_std_logic_vector(13545608,24); manlo <= conv_std_logic_vector(191424516,28); exponent <= conv_std_logic_vector(1051,11); WHEN "0000010101" => manhi <= conv_std_logic_vector(3829279,24); manlo <= conv_std_logic_vector(228519165,28); exponent <= conv_std_logic_vector(1053,11); WHEN "0000010110" => manhi <= conv_std_logic_vector(11229915,24); manlo <= conv_std_logic_vector(163853824,28); exponent <= conv_std_logic_vector(1054,11); WHEN "0000010111" => manhi <= conv_std_logic_vector(2255603,24); manlo <= conv_std_logic_vector(61996481,28); exponent <= conv_std_logic_vector(1056,11); WHEN "0000011000" => manhi <= conv_std_logic_vector(9091067,24); manlo <= conv_std_logic_vector(88563639,28); exponent <= conv_std_logic_vector(1057,11); WHEN "0000011001" => manhi <= conv_std_logic_vector(802105,24); manlo <= conv_std_logic_vector(34169545,28); exponent <= conv_std_logic_vector(1059,11); WHEN "0000011010" => manhi <= conv_std_logic_vector(7115558,24); manlo <= conv_std_logic_vector(157969244,28); exponent <= conv_std_logic_vector(1060,11); WHEN "0000011011" => manhi <= conv_std_logic_vector(15696431,24); manlo <= conv_std_logic_vector(133591837,28); exponent <= conv_std_logic_vector(1061,11); WHEN "0000011100" => manhi <= conv_std_logic_vector(5290915,24); manlo <= conv_std_logic_vector(127285146,28); exponent <= conv_std_logic_vector(1063,11); WHEN "0000011101" => manhi <= conv_std_logic_vector(13216484,24); manlo <= conv_std_logic_vector(103923798,28); exponent <= conv_std_logic_vector(1064,11); WHEN "0000011110" => manhi <= conv_std_logic_vector(3605616,24); manlo <= conv_std_logic_vector(183249133,28); exponent <= conv_std_logic_vector(1066,11); WHEN "0000011111" => manhi <= conv_std_logic_vector(10925925,24); manlo <= conv_std_logic_vector(227336045,28); exponent <= conv_std_logic_vector(1067,11); WHEN "0000100000" => manhi <= conv_std_logic_vector(2049020,24); manlo <= conv_std_logic_vector(206267948,28); exponent <= conv_std_logic_vector(1069,11); WHEN "0000100001" => manhi <= conv_std_logic_vector(8810292,24); manlo <= conv_std_logic_vector(175265666,28); exponent <= conv_std_logic_vector(1070,11); WHEN "0000100010" => manhi <= conv_std_logic_vector(611298,24); manlo <= conv_std_logic_vector(255467255,28); exponent <= conv_std_logic_vector(1072,11); WHEN "0000100011" => manhi <= conv_std_logic_vector(6856226,24); manlo <= conv_std_logic_vector(29134171,28); exponent <= conv_std_logic_vector(1073,11); WHEN "0000100100" => manhi <= conv_std_logic_vector(15343962,24); manlo <= conv_std_logic_vector(30543222,28); exponent <= conv_std_logic_vector(1074,11); WHEN "0000100101" => manhi <= conv_std_logic_vector(5051387,24); manlo <= conv_std_logic_vector(186253338,28); exponent <= conv_std_logic_vector(1076,11); WHEN "0000100110" => manhi <= conv_std_logic_vector(12890932,24); manlo <= conv_std_logic_vector(102222951,28); exponent <= conv_std_logic_vector(1077,11); WHEN "0000100111" => manhi <= conv_std_logic_vector(3384381,24); manlo <= conv_std_logic_vector(42116377,28); exponent <= conv_std_logic_vector(1079,11); WHEN "0000101000" => manhi <= conv_std_logic_vector(10625235,24); manlo <= conv_std_logic_vector(158954218,28); exponent <= conv_std_logic_vector(1080,11); WHEN "0000101001" => manhi <= conv_std_logic_vector(1844680,24); manlo <= conv_std_logic_vector(148858978,28); exponent <= conv_std_logic_vector(1082,11); WHEN "0000101010" => manhi <= conv_std_logic_vector(8532565,24); manlo <= conv_std_logic_vector(136319321,28); exponent <= conv_std_logic_vector(1083,11); WHEN "0000101011" => manhi <= conv_std_logic_vector(422563,24); manlo <= conv_std_logic_vector(211728497,28); exponent <= conv_std_logic_vector(1085,11); WHEN "0000101100" => manhi <= conv_std_logic_vector(6599708,24); manlo <= conv_std_logic_vector(114522162,28); exponent <= conv_std_logic_vector(1086,11); WHEN "0000101101" => manhi <= conv_std_logic_vector(14995318,24); manlo <= conv_std_logic_vector(117328318,28); exponent <= conv_std_logic_vector(1087,11); WHEN "0000101110" => manhi <= conv_std_logic_vector(4814459,24); manlo <= conv_std_logic_vector(201622499,28); exponent <= conv_std_logic_vector(1089,11); WHEN "0000101111" => manhi <= conv_std_logic_vector(12568913,24); manlo <= conv_std_logic_vector(246987638,28); exponent <= conv_std_logic_vector(1090,11); WHEN "0000110000" => manhi <= conv_std_logic_vector(3165546,24); manlo <= conv_std_logic_vector(248128843,28); exponent <= conv_std_logic_vector(1092,11); WHEN "0000110001" => manhi <= conv_std_logic_vector(10327809,24); manlo <= conv_std_logic_vector(8929872,28); exponent <= conv_std_logic_vector(1093,11); WHEN "0000110010" => manhi <= conv_std_logic_vector(1642558,24); manlo <= conv_std_logic_vector(67636037,28); exponent <= conv_std_logic_vector(1095,11); WHEN "0000110011" => manhi <= conv_std_logic_vector(8257852,24); manlo <= conv_std_logic_vector(219235425,28); exponent <= conv_std_logic_vector(1096,11); WHEN "0000110100" => manhi <= conv_std_logic_vector(235877,24); manlo <= conv_std_logic_vector(42862412,28); exponent <= conv_std_logic_vector(1098,11); WHEN "0000110101" => manhi <= conv_std_logic_vector(6345974,24); manlo <= conv_std_logic_vector(265996080,28); exponent <= conv_std_logic_vector(1099,11); WHEN "0000110110" => manhi <= conv_std_logic_vector(14650458,24); manlo <= conv_std_logic_vector(253213243,28); exponent <= conv_std_logic_vector(1100,11); WHEN "0000110111" => manhi <= conv_std_logic_vector(4580103,24); manlo <= conv_std_logic_vector(114693785,28); exponent <= conv_std_logic_vector(1102,11); WHEN "0000111000" => manhi <= conv_std_logic_vector(12250390,24); manlo <= conv_std_logic_vector(174984615,28); exponent <= conv_std_logic_vector(1103,11); WHEN "0000111001" => manhi <= conv_std_logic_vector(2949087,24); manlo <= conv_std_logic_vector(247325089,28); exponent <= conv_std_logic_vector(1105,11); WHEN "0000111010" => manhi <= conv_std_logic_vector(10033610,24); manlo <= conv_std_logic_vector(200264553,28); exponent <= conv_std_logic_vector(1106,11); WHEN "0000111011" => manhi <= conv_std_logic_vector(1442629,24); manlo <= conv_std_logic_vector(211375075,28); exponent <= conv_std_logic_vector(1108,11); WHEN "0000111100" => manhi <= conv_std_logic_vector(7986121,24); manlo <= conv_std_logic_vector(231029862,28); exponent <= conv_std_logic_vector(1109,11); WHEN "0000111101" => manhi <= conv_std_logic_vector(51216,24); manlo <= conv_std_logic_vector(222707863,28); exponent <= conv_std_logic_vector(1111,11); WHEN "0000111110" => manhi <= conv_std_logic_vector(6094995,24); manlo <= conv_std_logic_vector(155999272,28); exponent <= conv_std_logic_vector(1112,11); WHEN "0000111111" => manhi <= conv_std_logic_vector(14309342,24); manlo <= conv_std_logic_vector(150013864,28); exponent <= conv_std_logic_vector(1113,11); WHEN "0001000000" => manhi <= conv_std_logic_vector(4348290,24); manlo <= conv_std_logic_vector(217421773,28); exponent <= conv_std_logic_vector(1115,11); WHEN "0001000001" => manhi <= conv_std_logic_vector(11935324,24); manlo <= conv_std_logic_vector(171597361,28); exponent <= conv_std_logic_vector(1116,11); WHEN "0001000010" => manhi <= conv_std_logic_vector(2734978,24); manlo <= conv_std_logic_vector(98553735,28); exponent <= conv_std_logic_vector(1118,11); WHEN "0001000011" => manhi <= conv_std_logic_vector(9742605,24); manlo <= conv_std_logic_vector(185429986,28); exponent <= conv_std_logic_vector(1119,11); WHEN "0001000100" => manhi <= conv_std_logic_vector(1244871,24); manlo <= conv_std_logic_vector(93685501,28); exponent <= conv_std_logic_vector(1121,11); WHEN "0001000101" => manhi <= conv_std_logic_vector(7717340,24); manlo <= conv_std_logic_vector(74048432,28); exponent <= conv_std_logic_vector(1122,11); WHEN "0001000110" => manhi <= conv_std_logic_vector(16514337,24); manlo <= conv_std_logic_vector(163855108,28); exponent <= conv_std_logic_vector(1123,11); WHEN "0001000111" => manhi <= conv_std_logic_vector(5846740,24); manlo <= conv_std_logic_vector(81895750,28); exponent <= conv_std_logic_vector(1125,11); WHEN "0001001000" => manhi <= conv_std_logic_vector(13971928,24); manlo <= conv_std_logic_vector(176088988,28); exponent <= conv_std_logic_vector(1126,11); WHEN "0001001001" => manhi <= conv_std_logic_vector(4118994,24); manlo <= conv_std_logic_vector(77780251,28); exponent <= conv_std_logic_vector(1128,11); WHEN "0001001010" => manhi <= conv_std_logic_vector(11623678,24); manlo <= conv_std_logic_vector(95871356,28); exponent <= conv_std_logic_vector(1129,11); WHEN "0001001011" => manhi <= conv_std_logic_vector(2523192,24); manlo <= conv_std_logic_vector(204213760,28); exponent <= conv_std_logic_vector(1131,11); WHEN "0001001100" => manhi <= conv_std_logic_vector(9454759,24); manlo <= conv_std_logic_vector(55860552,28); exponent <= conv_std_logic_vector(1132,11); WHEN "0001001101" => manhi <= conv_std_logic_vector(1049259,24); manlo <= conv_std_logic_vector(102861624,28); exponent <= conv_std_logic_vector(1134,11); WHEN "0001001110" => manhi <= conv_std_logic_vector(7451476,24); manlo <= conv_std_logic_vector(13367584,28); exponent <= conv_std_logic_vector(1135,11); WHEN "0001001111" => manhi <= conv_std_logic_vector(16152990,24); manlo <= conv_std_logic_vector(178012490,28); exponent <= conv_std_logic_vector(1136,11); WHEN "0001010000" => manhi <= conv_std_logic_vector(5601179,24); manlo <= conv_std_logic_vector(159708139,28); exponent <= conv_std_logic_vector(1138,11); WHEN "0001010001" => manhi <= conv_std_logic_vector(13638177,24); manlo <= conv_std_logic_vector(12864164,28); exponent <= conv_std_logic_vector(1139,11); WHEN "0001010010" => manhi <= conv_std_logic_vector(3892186,24); manlo <= conv_std_logic_vector(149492240,28); exponent <= conv_std_logic_vector(1141,11); WHEN "0001010011" => manhi <= conv_std_logic_vector(11315414,24); manlo <= conv_std_logic_vector(184620728,28); exponent <= conv_std_logic_vector(1142,11); WHEN "0001010100" => manhi <= conv_std_logic_vector(2313705,24); manlo <= conv_std_logic_vector(235697385,28); exponent <= conv_std_logic_vector(1144,11); WHEN "0001010101" => manhi <= conv_std_logic_vector(9170037,24); manlo <= conv_std_logic_vector(3974263,28); exponent <= conv_std_logic_vector(1145,11); WHEN "0001010110" => manhi <= conv_std_logic_vector(855770,24); manlo <= conv_std_logic_vector(158952336,28); exponent <= conv_std_logic_vector(1147,11); WHEN "0001010111" => manhi <= conv_std_logic_vector(7188497,24); manlo <= conv_std_logic_vector(138900038,28); exponent <= conv_std_logic_vector(1148,11); WHEN "0001011000" => manhi <= conv_std_logic_vector(15795565,24); manlo <= conv_std_logic_vector(209449517,28); exponent <= conv_std_logic_vector(1149,11); WHEN "0001011001" => manhi <= conv_std_logic_vector(5358284,24); manlo <= conv_std_logic_vector(54736896,28); exponent <= conv_std_logic_vector(1151,11); WHEN "0001011010" => manhi <= conv_std_logic_vector(13308047,24); manlo <= conv_std_logic_vector(264159588,28); exponent <= conv_std_logic_vector(1152,11); WHEN "0001011011" => manhi <= conv_std_logic_vector(3667840,24); manlo <= conv_std_logic_vector(160544132,28); exponent <= conv_std_logic_vector(1154,11); WHEN "0001011100" => manhi <= conv_std_logic_vector(11010496,24); manlo <= conv_std_logic_vector(245935181,28); exponent <= conv_std_logic_vector(1155,11); WHEN "0001011101" => manhi <= conv_std_logic_vector(2106492,24); manlo <= conv_std_logic_vector(206325441,28); exponent <= conv_std_logic_vector(1157,11); WHEN "0001011110" => manhi <= conv_std_logic_vector(8888405,24); manlo <= conv_std_logic_vector(53641237,28); exponent <= conv_std_logic_vector(1158,11); WHEN "0001011111" => manhi <= conv_std_logic_vector(664381,24); manlo <= conv_std_logic_vector(249887163,28); exponent <= conv_std_logic_vector(1160,11); WHEN "0001100000" => manhi <= conv_std_logic_vector(6928373,24); manlo <= conv_std_logic_vector(95946938,28); exponent <= conv_std_logic_vector(1161,11); WHEN "0001100001" => manhi <= conv_std_logic_vector(15442020,24); manlo <= conv_std_logic_vector(105121290,28); exponent <= conv_std_logic_vector(1162,11); WHEN "0001100010" => manhi <= conv_std_logic_vector(5118025,24); manlo <= conv_std_logic_vector(54367076,28); exponent <= conv_std_logic_vector(1164,11); WHEN "0001100011" => manhi <= conv_std_logic_vector(12981502,24); manlo <= conv_std_logic_vector(39000129,28); exponent <= conv_std_logic_vector(1165,11); WHEN "0001100100" => manhi <= conv_std_logic_vector(3445929,24); manlo <= conv_std_logic_vector(186063861,28); exponent <= conv_std_logic_vector(1167,11); WHEN "0001100101" => manhi <= conv_std_logic_vector(10708888,24); manlo <= conv_std_logic_vector(194877084,28); exponent <= conv_std_logic_vector(1168,11); WHEN "0001100110" => manhi <= conv_std_logic_vector(1901528,24); manlo <= conv_std_logic_vector(202114223,28); exponent <= conv_std_logic_vector(1170,11); WHEN "0001100111" => manhi <= conv_std_logic_vector(8609830,24); manlo <= conv_std_logic_vector(59099508,28); exponent <= conv_std_logic_vector(1171,11); WHEN "0001101000" => manhi <= conv_std_logic_vector(475070,24); manlo <= conv_std_logic_vector(162304029,28); exponent <= conv_std_logic_vector(1173,11); WHEN "0001101001" => manhi <= conv_std_logic_vector(6671072,24); manlo <= conv_std_logic_vector(157938310,28); exponent <= conv_std_logic_vector(1174,11); WHEN "0001101010" => manhi <= conv_std_logic_vector(15092312,24); manlo <= conv_std_logic_vector(104450792,28); exponent <= conv_std_logic_vector(1175,11); WHEN "0001101011" => manhi <= conv_std_logic_vector(4880373,24); manlo <= conv_std_logic_vector(261837049,28); exponent <= conv_std_logic_vector(1177,11); WHEN "0001101100" => manhi <= conv_std_logic_vector(12658500,24); manlo <= conv_std_logic_vector(171583716,28); exponent <= conv_std_logic_vector(1178,11); WHEN "0001101101" => manhi <= conv_std_logic_vector(3226427,24); manlo <= conv_std_logic_vector(110595717,28); exponent <= conv_std_logic_vector(1180,11); WHEN "0001101110" => manhi <= conv_std_logic_vector(10410554,24); manlo <= conv_std_logic_vector(52320382,28); exponent <= conv_std_logic_vector(1181,11); WHEN "0001101111" => manhi <= conv_std_logic_vector(1698789,24); manlo <= conv_std_logic_vector(112550995,28); exponent <= conv_std_logic_vector(1183,11); WHEN "0001110000" => manhi <= conv_std_logic_vector(8334278,24); manlo <= conv_std_logic_vector(240753534,28); exponent <= conv_std_logic_vector(1184,11); WHEN "0001110001" => manhi <= conv_std_logic_vector(287814,24); manlo <= conv_std_logic_vector(17691391,28); exponent <= conv_std_logic_vector(1186,11); WHEN "0001110010" => manhi <= conv_std_logic_vector(6416564,24); manlo <= conv_std_logic_vector(151700710,28); exponent <= conv_std_logic_vector(1187,11); WHEN "0001110011" => manhi <= conv_std_logic_vector(14746400,24); manlo <= conv_std_logic_vector(32676275,28); exponent <= conv_std_logic_vector(1188,11); WHEN "0001110100" => manhi <= conv_std_logic_vector(4645302,24); manlo <= conv_std_logic_vector(58452725,28); exponent <= conv_std_logic_vector(1190,11); WHEN "0001110101" => manhi <= conv_std_logic_vector(12339004,24); manlo <= conv_std_logic_vector(267247876,28); exponent <= conv_std_logic_vector(1191,11); WHEN "0001110110" => manhi <= conv_std_logic_vector(3009307,24); manlo <= conv_std_logic_vector(164126253,28); exponent <= conv_std_logic_vector(1193,11); WHEN "0001110111" => manhi <= conv_std_logic_vector(10115457,24); manlo <= conv_std_logic_vector(212237584,28); exponent <= conv_std_logic_vector(1194,11); WHEN "0001111000" => manhi <= conv_std_logic_vector(1498250,24); manlo <= conv_std_logic_vector(166684427,28); exponent <= conv_std_logic_vector(1196,11); WHEN "0001111001" => manhi <= conv_std_logic_vector(8061718,24); manlo <= conv_std_logic_vector(110371593,28); exponent <= conv_std_logic_vector(1197,11); WHEN "0001111010" => manhi <= conv_std_logic_vector(102590,24); manlo <= conv_std_logic_vector(3231911,28); exponent <= conv_std_logic_vector(1199,11); WHEN "0001111011" => manhi <= conv_std_logic_vector(6164818,24); manlo <= conv_std_logic_vector(261783833,28); exponent <= conv_std_logic_vector(1200,11); WHEN "0001111100" => manhi <= conv_std_logic_vector(14404242,24); manlo <= conv_std_logic_vector(104825991,28); exponent <= conv_std_logic_vector(1201,11); WHEN "0001111101" => manhi <= conv_std_logic_vector(4412781,24); manlo <= conv_std_logic_vector(250166254,28); exponent <= conv_std_logic_vector(1203,11); WHEN "0001111110" => manhi <= conv_std_logic_vector(12022977,24); manlo <= conv_std_logic_vector(43417082,28); exponent <= conv_std_logic_vector(1204,11); WHEN "0001111111" => manhi <= conv_std_logic_vector(2794544,24); manlo <= conv_std_logic_vector(115942082,28); exponent <= conv_std_logic_vector(1206,11); WHEN "0010000000" => manhi <= conv_std_logic_vector(9823564,24); manlo <= conv_std_logic_vector(98386456,28); exponent <= conv_std_logic_vector(1207,11); WHEN "0010000001" => manhi <= conv_std_logic_vector(1299888,24); manlo <= conv_std_logic_vector(127046227,28); exponent <= conv_std_logic_vector(1209,11); WHEN "0010000010" => manhi <= conv_std_logic_vector(7792116,24); manlo <= conv_std_logic_vector(80649262,28); exponent <= conv_std_logic_vector(1210,11); WHEN "0010000011" => manhi <= conv_std_logic_vector(16615968,24); manlo <= conv_std_logic_vector(205307910,28); exponent <= conv_std_logic_vector(1211,11); WHEN "0010000100" => manhi <= conv_std_logic_vector(5915805,24); manlo <= conv_std_logic_vector(224185017,28); exponent <= conv_std_logic_vector(1213,11); WHEN "0010000101" => manhi <= conv_std_logic_vector(14065798,24); manlo <= conv_std_logic_vector(119094636,28); exponent <= conv_std_logic_vector(1214,11); WHEN "0010000110" => manhi <= conv_std_logic_vector(4182785,24); manlo <= conv_std_logic_vector(113890892,28); exponent <= conv_std_logic_vector(1216,11); WHEN "0010000111" => manhi <= conv_std_logic_vector(11710379,24); manlo <= conv_std_logic_vector(133692518,28); exponent <= conv_std_logic_vector(1217,11); WHEN "0010001000" => manhi <= conv_std_logic_vector(2582112,24); manlo <= conv_std_logic_vector(79109485,28); exponent <= conv_std_logic_vector(1219,11); WHEN "0010001001" => manhi <= conv_std_logic_vector(9534839,24); manlo <= conv_std_logic_vector(42234535,28); exponent <= conv_std_logic_vector(1220,11); WHEN "0010001010" => manhi <= conv_std_logic_vector(1103679,24); manlo <= conv_std_logic_vector(94193887,28); exponent <= conv_std_logic_vector(1222,11); WHEN "0010001011" => manhi <= conv_std_logic_vector(7525440,24); manlo <= conv_std_logic_vector(121994268,28); exponent <= conv_std_logic_vector(1223,11); WHEN "0010001100" => manhi <= conv_std_logic_vector(16253518,24); manlo <= conv_std_logic_vector(191052573,28); exponent <= conv_std_logic_vector(1224,11); WHEN "0010001101" => manhi <= conv_std_logic_vector(5669495,24); manlo <= conv_std_logic_vector(130696997,28); exponent <= conv_std_logic_vector(1226,11); WHEN "0010001110" => manhi <= conv_std_logic_vector(13731027,24); manlo <= conv_std_logic_vector(260846837,28); exponent <= conv_std_logic_vector(1227,11); WHEN "0010001111" => manhi <= conv_std_logic_vector(3955285,24); manlo <= conv_std_logic_vector(80970159,28); exponent <= conv_std_logic_vector(1229,11); WHEN "0010010000" => manhi <= conv_std_logic_vector(11401174,24); manlo <= conv_std_logic_vector(207600506,28); exponent <= conv_std_logic_vector(1230,11); WHEN "0010010001" => manhi <= conv_std_logic_vector(2371985,24); manlo <= conv_std_logic_vector(241221170,28); exponent <= conv_std_logic_vector(1232,11); WHEN "0010010010" => manhi <= conv_std_logic_vector(9249247,24); manlo <= conv_std_logic_vector(208105818,28); exponent <= conv_std_logic_vector(1233,11); WHEN "0010010011" => manhi <= conv_std_logic_vector(909599,24); manlo <= conv_std_logic_vector(237519888,28); exponent <= conv_std_logic_vector(1235,11); WHEN "0010010100" => manhi <= conv_std_logic_vector(7261659,24); manlo <= conv_std_logic_vector(29935335,28); exponent <= conv_std_logic_vector(1236,11); WHEN "0010010101" => manhi <= conv_std_logic_vector(15895002,24); manlo <= conv_std_logic_vector(186862656,28); exponent <= conv_std_logic_vector(1237,11); WHEN "0010010110" => manhi <= conv_std_logic_vector(5425858,24); manlo <= conv_std_logic_vector(159524243,28); exponent <= conv_std_logic_vector(1239,11); WHEN "0010010111" => manhi <= conv_std_logic_vector(13399891,24); manlo <= conv_std_logic_vector(27586577,28); exponent <= conv_std_logic_vector(1240,11); WHEN "0010011000" => manhi <= conv_std_logic_vector(3730254,24); manlo <= conv_std_logic_vector(125689310,28); exponent <= conv_std_logic_vector(1242,11); WHEN "0010011001" => manhi <= conv_std_logic_vector(11095326,24); manlo <= conv_std_logic_vector(43144000,28); exponent <= conv_std_logic_vector(1243,11); WHEN "0010011010" => manhi <= conv_std_logic_vector(2164140,24); manlo <= conv_std_logic_vector(58280992,28); exponent <= conv_std_logic_vector(1245,11); WHEN "0010011011" => manhi <= conv_std_logic_vector(8966756,24); manlo <= conv_std_logic_vector(55210422,28); exponent <= conv_std_logic_vector(1246,11); WHEN "0010011100" => manhi <= conv_std_logic_vector(717626,24); manlo <= conv_std_logic_vector(257633658,28); exponent <= conv_std_logic_vector(1248,11); WHEN "0010011101" => manhi <= conv_std_logic_vector(7000740,24); manlo <= conv_std_logic_vector(229413090,28); exponent <= conv_std_logic_vector(1249,11); WHEN "0010011110" => manhi <= conv_std_logic_vector(15540378,24); manlo <= conv_std_logic_vector(4808337,28); exponent <= conv_std_logic_vector(1250,11); WHEN "0010011111" => manhi <= conv_std_logic_vector(5184866,24); manlo <= conv_std_logic_vector(37474138,28); exponent <= conv_std_logic_vector(1252,11); WHEN "0010100000" => manhi <= conv_std_logic_vector(13072348,24); manlo <= conv_std_logic_vector(106730632,28); exponent <= conv_std_logic_vector(1253,11); WHEN "0010100001" => manhi <= conv_std_logic_vector(3507666,24); manlo <= conv_std_logic_vector(32844500,28); exponent <= conv_std_logic_vector(1255,11); WHEN "0010100010" => manhi <= conv_std_logic_vector(10792797,24); manlo <= conv_std_logic_vector(62496090,28); exponent <= conv_std_logic_vector(1256,11); WHEN "0010100011" => manhi <= conv_std_logic_vector(1958550,24); manlo <= conv_std_logic_vector(132952012,28); exponent <= conv_std_logic_vector(1258,11); WHEN "0010100100" => manhi <= conv_std_logic_vector(8687330,24); manlo <= conv_std_logic_vector(215605290,28); exponent <= conv_std_logic_vector(1259,11); WHEN "0010100101" => manhi <= conv_std_logic_vector(527737,24); manlo <= conv_std_logic_vector(190928911,28); exponent <= conv_std_logic_vector(1261,11); WHEN "0010100110" => manhi <= conv_std_logic_vector(6742654,24); manlo <= conv_std_logic_vector(163162889,28); exponent <= conv_std_logic_vector(1262,11); WHEN "0010100111" => manhi <= conv_std_logic_vector(15189602,24); manlo <= conv_std_logic_vector(118241780,28); exponent <= conv_std_logic_vector(1263,11); WHEN "0010101000" => manhi <= conv_std_logic_vector(4946489,24); manlo <= conv_std_logic_vector(112771062,28); exponent <= conv_std_logic_vector(1265,11); WHEN "0010101001" => manhi <= conv_std_logic_vector(12748360,24); manlo <= conv_std_logic_vector(226864003,28); exponent <= conv_std_logic_vector(1266,11); WHEN "0010101010" => manhi <= conv_std_logic_vector(3287493,24); manlo <= conv_std_logic_vector(202192272,28); exponent <= conv_std_logic_vector(1268,11); WHEN "0010101011" => manhi <= conv_std_logic_vector(10493551,24); manlo <= conv_std_logic_vector(257093553,28); exponent <= conv_std_logic_vector(1269,11); WHEN "0010101100" => manhi <= conv_std_logic_vector(1755192,24); manlo <= conv_std_logic_vector(66281405,28); exponent <= conv_std_logic_vector(1271,11); WHEN "0010101101" => manhi <= conv_std_logic_vector(8410938,24); manlo <= conv_std_logic_vector(77199396,28); exponent <= conv_std_logic_vector(1272,11); WHEN "0010101110" => manhi <= conv_std_logic_vector(339909,24); manlo <= conv_std_logic_vector(140417186,28); exponent <= conv_std_logic_vector(1274,11); WHEN "0010101111" => manhi <= conv_std_logic_vector(6487369,24); manlo <= conv_std_logic_vector(169769464,28); exponent <= conv_std_logic_vector(1275,11); WHEN "0010110000" => manhi <= conv_std_logic_vector(14842634,24); manlo <= conv_std_logic_vector(49834035,28); exponent <= conv_std_logic_vector(1276,11); WHEN "0010110001" => manhi <= conv_std_logic_vector(4710700,24); manlo <= conv_std_logic_vector(11961455,28); exponent <= conv_std_logic_vector(1278,11); WHEN "0010110010" => manhi <= conv_std_logic_vector(12427889,24); manlo <= conv_std_logic_vector(230234502,28); exponent <= conv_std_logic_vector(1279,11); WHEN "0010110011" => manhi <= conv_std_logic_vector(3069711,24); manlo <= conv_std_logic_vector(36989233,28); exponent <= conv_std_logic_vector(1281,11); WHEN "0010110100" => manhi <= conv_std_logic_vector(10197554,24); manlo <= conv_std_logic_vector(186484869,28); exponent <= conv_std_logic_vector(1282,11); WHEN "0010110101" => manhi <= conv_std_logic_vector(1554041,24); manlo <= conv_std_logic_vector(67530342,28); exponent <= conv_std_logic_vector(1284,11); WHEN "0010110110" => manhi <= conv_std_logic_vector(8137545,24); manlo <= conv_std_logic_vector(198608842,28); exponent <= conv_std_logic_vector(1285,11); WHEN "0010110111" => manhi <= conv_std_logic_vector(154120,24); manlo <= conv_std_logic_vector(6569319,28); exponent <= conv_std_logic_vector(1287,11); WHEN "0010111000" => manhi <= conv_std_logic_vector(6234855,24); manlo <= conv_std_logic_vector(140506894,28); exponent <= conv_std_logic_vector(1288,11); WHEN "0010111001" => manhi <= conv_std_logic_vector(14499431,24); manlo <= conv_std_logic_vector(249287529,28); exponent <= conv_std_logic_vector(1289,11); WHEN "0010111010" => manhi <= conv_std_logic_vector(4477469,24); manlo <= conv_std_logic_vector(249618841,28); exponent <= conv_std_logic_vector(1291,11); WHEN "0010111011" => manhi <= conv_std_logic_vector(12110897,24); manlo <= conv_std_logic_vector(71519058,28); exponent <= conv_std_logic_vector(1292,11); WHEN "0010111100" => manhi <= conv_std_logic_vector(2854292,24); manlo <= conv_std_logic_vector(90637320,28); exponent <= conv_std_logic_vector(1294,11); WHEN "0010111101" => manhi <= conv_std_logic_vector(9904770,24); manlo <= conv_std_logic_vector(50932558,28); exponent <= conv_std_logic_vector(1295,11); WHEN "0010111110" => manhi <= conv_std_logic_vector(1355073,24); manlo <= conv_std_logic_vector(148093260,28); exponent <= conv_std_logic_vector(1297,11); WHEN "0010111111" => manhi <= conv_std_logic_vector(7867120,24); manlo <= conv_std_logic_vector(160620741,28); exponent <= conv_std_logic_vector(1298,11); WHEN "0011000000" => manhi <= conv_std_logic_vector(16717910,24); manlo <= conv_std_logic_vector(46942270,28); exponent <= conv_std_logic_vector(1299,11); WHEN "0011000001" => manhi <= conv_std_logic_vector(5985082,24); manlo <= conv_std_logic_vector(55237426,28); exponent <= conv_std_logic_vector(1301,11); WHEN "0011000010" => manhi <= conv_std_logic_vector(14159954,24); manlo <= conv_std_logic_vector(212966668,28); exponent <= conv_std_logic_vector(1302,11); WHEN "0011000011" => manhi <= conv_std_logic_vector(4246771,24); manlo <= conv_std_logic_vector(79962334,28); exponent <= conv_std_logic_vector(1304,11); WHEN "0011000100" => manhi <= conv_std_logic_vector(11797345,24); manlo <= conv_std_logic_vector(85038862,28); exponent <= conv_std_logic_vector(1305,11); WHEN "0011000101" => manhi <= conv_std_logic_vector(2641211,24); manlo <= conv_std_logic_vector(186806322,28); exponent <= conv_std_logic_vector(1307,11); WHEN "0011000110" => manhi <= conv_std_logic_vector(9615163,24); manlo <= conv_std_logic_vector(153415152,28); exponent <= conv_std_logic_vector(1308,11); WHEN "0011000111" => manhi <= conv_std_logic_vector(1158265,24); manlo <= conv_std_logic_vector(120731907,28); exponent <= conv_std_logic_vector(1310,11); WHEN "0011001000" => manhi <= conv_std_logic_vector(7599630,24); manlo <= conv_std_logic_vector(175764921,28); exponent <= conv_std_logic_vector(1311,11); WHEN "0011001001" => manhi <= conv_std_logic_vector(16354353,24); manlo <= conv_std_logic_vector(174054693,28); exponent <= conv_std_logic_vector(1312,11); WHEN "0011001010" => manhi <= conv_std_logic_vector(5738019,24); manlo <= conv_std_logic_vector(249885394,28); exponent <= conv_std_logic_vector(1314,11); WHEN "0011001011" => manhi <= conv_std_logic_vector(13824162,24); manlo <= conv_std_logic_vector(93203713,28); exponent <= conv_std_logic_vector(1315,11); WHEN "0011001100" => manhi <= conv_std_logic_vector(4018576,24); manlo <= conv_std_logic_vector(180323091,28); exponent <= conv_std_logic_vector(1317,11); WHEN "0011001101" => manhi <= conv_std_logic_vector(11487196,24); manlo <= conv_std_logic_vector(178245939,28); exponent <= conv_std_logic_vector(1318,11); WHEN "0011001110" => manhi <= conv_std_logic_vector(2430443,24); manlo <= conv_std_logic_vector(223919964,28); exponent <= conv_std_logic_vector(1320,11); WHEN "0011001111" => manhi <= conv_std_logic_vector(9328700,24); manlo <= conv_std_logic_vector(93205956,28); exponent <= conv_std_logic_vector(1321,11); WHEN "0011010000" => manhi <= conv_std_logic_vector(963593,24); manlo <= conv_std_logic_vector(135688620,28); exponent <= conv_std_logic_vector(1323,11); WHEN "0011010001" => manhi <= conv_std_logic_vector(7335044,24); manlo <= conv_std_logic_vector(13542358,28); exponent <= conv_std_logic_vector(1324,11); WHEN "0011010010" => manhi <= conv_std_logic_vector(15994743,24); manlo <= conv_std_logic_vector(45394459,28); exponent <= conv_std_logic_vector(1325,11); WHEN "0011010011" => manhi <= conv_std_logic_vector(5493639,24); manlo <= conv_std_logic_vector(73308838,28); exponent <= conv_std_logic_vector(1327,11); WHEN "0011010100" => manhi <= conv_std_logic_vector(13492014,24); manlo <= conv_std_logic_vector(160135181,28); exponent <= conv_std_logic_vector(1328,11); WHEN "0011010101" => manhi <= conv_std_logic_vector(3792858,24); manlo <= conv_std_logic_vector(234346738,28); exponent <= conv_std_logic_vector(1330,11); WHEN "0011010110" => manhi <= conv_std_logic_vector(11180414,24); manlo <= conv_std_logic_vector(98964646,28); exponent <= conv_std_logic_vector(1331,11); WHEN "0011010111" => manhi <= conv_std_logic_vector(2221963,24); manlo <= conv_std_logic_vector(174344531,28); exponent <= conv_std_logic_vector(1333,11); WHEN "0011011000" => manhi <= conv_std_logic_vector(9045346,24); manlo <= conv_std_logic_vector(106947534,28); exponent <= conv_std_logic_vector(1334,11); WHEN "0011011001" => manhi <= conv_std_logic_vector(771034,24); manlo <= conv_std_logic_vector(143065990,28); exponent <= conv_std_logic_vector(1336,11); WHEN "0011011010" => manhi <= conv_std_logic_vector(7073329,24); manlo <= conv_std_logic_vector(73148434,28); exponent <= conv_std_logic_vector(1337,11); WHEN "0011011011" => manhi <= conv_std_logic_vector(15639035,24); manlo <= conv_std_logic_vector(243346703,28); exponent <= conv_std_logic_vector(1338,11); WHEN "0011011100" => manhi <= conv_std_logic_vector(5251911,24); manlo <= conv_std_logic_vector(33842377,28); exponent <= conv_std_logic_vector(1340,11); WHEN "0011011101" => manhi <= conv_std_logic_vector(13163471,24); manlo <= conv_std_logic_vector(263552292,28); exponent <= conv_std_logic_vector(1341,11); WHEN "0011011110" => manhi <= conv_std_logic_vector(3569591,24); manlo <= conv_std_logic_vector(4866264,28); exponent <= conv_std_logic_vector(1343,11); WHEN "0011011111" => manhi <= conv_std_logic_vector(10876961,24); manlo <= conv_std_logic_vector(239517036,28); exponent <= conv_std_logic_vector(1344,11); WHEN "0011100000" => manhi <= conv_std_logic_vector(2015746,24); manlo <= conv_std_logic_vector(83586287,28); exponent <= conv_std_logic_vector(1346,11); WHEN "0011100001" => manhi <= conv_std_logic_vector(8765067,24); manlo <= conv_std_logic_vector(262254542,28); exponent <= conv_std_logic_vector(1347,11); WHEN "0011100010" => manhi <= conv_std_logic_vector(580565,24); manlo <= conv_std_logic_vector(160521039,28); exponent <= conv_std_logic_vector(1349,11); WHEN "0011100011" => manhi <= conv_std_logic_vector(6814455,24); manlo <= conv_std_logic_vector(40288155,28); exponent <= conv_std_logic_vector(1350,11); WHEN "0011100100" => manhi <= conv_std_logic_vector(15287189,24); manlo <= conv_std_logic_vector(132910147,28); exponent <= conv_std_logic_vector(1351,11); WHEN "0011100101" => manhi <= conv_std_logic_vector(5012806,24); manlo <= conv_std_logic_vector(187753904,28); exponent <= conv_std_logic_vector(1353,11); WHEN "0011100110" => manhi <= conv_std_logic_vector(12838495,24); manlo <= conv_std_logic_vector(100071648,28); exponent <= conv_std_logic_vector(1354,11); WHEN "0011100111" => manhi <= conv_std_logic_vector(3348746,24); manlo <= conv_std_logic_vector(138348888,28); exponent <= conv_std_logic_vector(1356,11); WHEN "0011101000" => manhi <= conv_std_logic_vector(10576803,24); manlo <= conv_std_logic_vector(24941937,28); exponent <= conv_std_logic_vector(1357,11); WHEN "0011101001" => manhi <= conv_std_logic_vector(1811767,24); manlo <= conv_std_logic_vector(69497619,28); exponent <= conv_std_logic_vector(1359,11); WHEN "0011101010" => manhi <= conv_std_logic_vector(8487831,24); manlo <= conv_std_logic_vector(188199296,28); exponent <= conv_std_logic_vector(1360,11); WHEN "0011101011" => manhi <= conv_std_logic_vector(392164,24); manlo <= conv_std_logic_vector(4096525,28); exponent <= conv_std_logic_vector(1362,11); WHEN "0011101100" => manhi <= conv_std_logic_vector(6558390,24); manlo <= conv_std_logic_vector(228356857,28); exponent <= conv_std_logic_vector(1363,11); WHEN "0011101101" => manhi <= conv_std_logic_vector(14939162,24); manlo <= conv_std_logic_vector(7826265,28); exponent <= conv_std_logic_vector(1364,11); WHEN "0011101110" => manhi <= conv_std_logic_vector(4776297,24); manlo <= conv_std_logic_vector(138324122,28); exponent <= conv_std_logic_vector(1366,11); WHEN "0011101111" => manhi <= conv_std_logic_vector(12517046,24); manlo <= conv_std_logic_vector(17190560,28); exponent <= conv_std_logic_vector(1367,11); WHEN "0011110000" => manhi <= conv_std_logic_vector(3130299,24); manlo <= conv_std_logic_vector(16562242,28); exponent <= conv_std_logic_vector(1369,11); WHEN "0011110001" => manhi <= conv_std_logic_vector(10279902,24); manlo <= conv_std_logic_vector(59323104,28); exponent <= conv_std_logic_vector(1370,11); WHEN "0011110010" => manhi <= conv_std_logic_vector(1610002,24); manlo <= conv_std_logic_vector(53056333,28); exponent <= conv_std_logic_vector(1372,11); WHEN "0011110011" => manhi <= conv_std_logic_vector(8213604,24); manlo <= conv_std_logic_vector(147986337,28); exponent <= conv_std_logic_vector(1373,11); WHEN "0011110100" => manhi <= conv_std_logic_vector(205807,24); manlo <= conv_std_logic_vector(92802035,28); exponent <= conv_std_logic_vector(1375,11); WHEN "0011110101" => manhi <= conv_std_logic_vector(6305105,24); manlo <= conv_std_logic_vector(235277170,28); exponent <= conv_std_logic_vector(1376,11); WHEN "0011110110" => manhi <= conv_std_logic_vector(14594912,24); manlo <= conv_std_logic_vector(15497684,28); exponent <= conv_std_logic_vector(1377,11); WHEN "0011110111" => manhi <= conv_std_logic_vector(4542355,24); manlo <= conv_std_logic_vector(108677892,28); exponent <= conv_std_logic_vector(1379,11); WHEN "0011111000" => manhi <= conv_std_logic_vector(12199085,24); manlo <= conv_std_logic_vector(206743222,28); exponent <= conv_std_logic_vector(1380,11); WHEN "0011111001" => manhi <= conv_std_logic_vector(2914222,24); manlo <= conv_std_logic_vector(171652524,28); exponent <= conv_std_logic_vector(1382,11); WHEN "0011111010" => manhi <= conv_std_logic_vector(9986223,24); manlo <= conv_std_logic_vector(245598061,28); exponent <= conv_std_logic_vector(1383,11); WHEN "0011111011" => manhi <= conv_std_logic_vector(1410427,24); manlo <= conv_std_logic_vector(26024388,28); exponent <= conv_std_logic_vector(1385,11); WHEN "0011111100" => manhi <= conv_std_logic_vector(7942353,24); manlo <= conv_std_logic_vector(232590388,28); exponent <= conv_std_logic_vector(1386,11); WHEN "0011111101" => manhi <= conv_std_logic_vector(21473,24); manlo <= conv_std_logic_vector(105719295,28); exponent <= conv_std_logic_vector(1388,11); WHEN "0011111110" => manhi <= conv_std_logic_vector(6054570,24); manlo <= conv_std_logic_vector(16265786,28); exponent <= conv_std_logic_vector(1389,11); WHEN "0011111111" => manhi <= conv_std_logic_vector(14254398,24); manlo <= conv_std_logic_vector(155662944,28); exponent <= conv_std_logic_vector(1390,11); WHEN "0100000000" => manhi <= conv_std_logic_vector(4310952,24); manlo <= conv_std_logic_vector(135577274,28); exponent <= conv_std_logic_vector(1392,11); WHEN "0100000001" => manhi <= conv_std_logic_vector(11884576,24); manlo <= conv_std_logic_vector(166805756,28); exponent <= conv_std_logic_vector(1393,11); WHEN "0100000010" => manhi <= conv_std_logic_vector(2700491,24); manlo <= conv_std_logic_vector(137829044,28); exponent <= conv_std_logic_vector(1395,11); WHEN "0100000011" => manhi <= conv_std_logic_vector(9695733,24); manlo <= conv_std_logic_vector(52863001,28); exponent <= conv_std_logic_vector(1396,11); WHEN "0100000100" => manhi <= conv_std_logic_vector(1213018,24); manlo <= conv_std_logic_vector(50179603,28); exponent <= conv_std_logic_vector(1398,11); WHEN "0100000101" => manhi <= conv_std_logic_vector(7674047,24); manlo <= conv_std_logic_vector(91276680,28); exponent <= conv_std_logic_vector(1399,11); WHEN "0100000110" => manhi <= conv_std_logic_vector(16455496,24); manlo <= conv_std_logic_vector(110068760,28); exponent <= conv_std_logic_vector(1400,11); WHEN "0100000111" => manhi <= conv_std_logic_vector(5806753,24); manlo <= conv_std_logic_vector(151304445,28); exponent <= conv_std_logic_vector(1402,11); WHEN "0100001000" => manhi <= conv_std_logic_vector(13917581,24); manlo <= conv_std_logic_vector(10650184,28); exponent <= conv_std_logic_vector(1403,11); WHEN "0100001001" => manhi <= conv_std_logic_vector(4082061,24); manlo <= conv_std_logic_vector(68530707,28); exponent <= conv_std_logic_vector(1405,11); WHEN "0100001010" => manhi <= conv_std_logic_vector(11573481,24); manlo <= conv_std_logic_vector(42662756,28); exponent <= conv_std_logic_vector(1406,11); WHEN "0100001011" => manhi <= conv_std_logic_vector(2489080,24); manlo <= conv_std_logic_vector(61154162,28); exponent <= conv_std_logic_vector(1408,11); WHEN "0100001100" => manhi <= conv_std_logic_vector(9408395,24); manlo <= conv_std_logic_vector(125867240,28); exponent <= conv_std_logic_vector(1409,11); WHEN "0100001101" => manhi <= conv_std_logic_vector(1017751,24); manlo <= conv_std_logic_vector(256555705,28); exponent <= conv_std_logic_vector(1411,11); WHEN "0100001110" => manhi <= conv_std_logic_vector(7408653,24); manlo <= conv_std_logic_vector(4309896,28); exponent <= conv_std_logic_vector(1412,11); WHEN "0100001111" => manhi <= conv_std_logic_vector(16094788,24); manlo <= conv_std_logic_vector(33800670,28); exponent <= conv_std_logic_vector(1413,11); WHEN "0100010000" => manhi <= conv_std_logic_vector(5561626,24); manlo <= conv_std_logic_vector(233573192,28); exponent <= conv_std_logic_vector(1415,11); WHEN "0100010001" => manhi <= conv_std_logic_vector(13584419,24); manlo <= conv_std_logic_vector(86257801,28); exponent <= conv_std_logic_vector(1416,11); WHEN "0100010010" => manhi <= conv_std_logic_vector(3855654,24); manlo <= conv_std_logic_vector(105782775,28); exponent <= conv_std_logic_vector(1418,11); WHEN "0100010011" => manhi <= conv_std_logic_vector(11265762,24); manlo <= conv_std_logic_vector(88738762,28); exponent <= conv_std_logic_vector(1419,11); WHEN "0100010100" => manhi <= conv_std_logic_vector(2279963,24); manlo <= conv_std_logic_vector(161858527,28); exponent <= conv_std_logic_vector(1421,11); WHEN "0100010101" => manhi <= conv_std_logic_vector(9124176,24); manlo <= conv_std_logic_vector(136423424,28); exponent <= conv_std_logic_vector(1422,11); WHEN "0100010110" => manhi <= conv_std_logic_vector(824605,24); manlo <= conv_std_logic_vector(39384255,28); exponent <= conv_std_logic_vector(1424,11); WHEN "0100010111" => manhi <= conv_std_logic_vector(7146139,24); manlo <= conv_std_logic_vector(76626123,28); exponent <= conv_std_logic_vector(1425,11); WHEN "0100011000" => manhi <= conv_std_logic_vector(15737994,24); manlo <= conv_std_logic_vector(261485765,28); exponent <= conv_std_logic_vector(1426,11); WHEN "0100011001" => manhi <= conv_std_logic_vector(5319160,24); manlo <= conv_std_logic_vector(210684009,28); exponent <= conv_std_logic_vector(1428,11); WHEN "0100011010" => manhi <= conv_std_logic_vector(13254873,24); manlo <= conv_std_logic_vector(199859160,28); exponent <= conv_std_logic_vector(1429,11); WHEN "0100011011" => manhi <= conv_std_logic_vector(3631704,24); manlo <= conv_std_logic_vector(256571707,28); exponent <= conv_std_logic_vector(1431,11); WHEN "0100011100" => manhi <= conv_std_logic_vector(10961383,24); manlo <= conv_std_logic_vector(130542749,28); exponent <= conv_std_logic_vector(1432,11); WHEN "0100011101" => manhi <= conv_std_logic_vector(2073116,24); manlo <= conv_std_logic_vector(196665136,28); exponent <= conv_std_logic_vector(1434,11); WHEN "0100011110" => manhi <= conv_std_logic_vector(8843042,24); manlo <= conv_std_logic_vector(124490661,28); exponent <= conv_std_logic_vector(1435,11); WHEN "0100011111" => manhi <= conv_std_logic_vector(633554,24); manlo <= conv_std_logic_vector(202834752,28); exponent <= conv_std_logic_vector(1437,11); WHEN "0100100000" => manhi <= conv_std_logic_vector(6886474,24); manlo <= conv_std_logic_vector(236822279,28); exponent <= conv_std_logic_vector(1438,11); WHEN "0100100001" => manhi <= conv_std_logic_vector(15385074,24); manlo <= conv_std_logic_vector(123405487,28); exponent <= conv_std_logic_vector(1439,11); WHEN "0100100010" => manhi <= conv_std_logic_vector(5079326,24); manlo <= conv_std_logic_vector(115311954,28); exponent <= conv_std_logic_vector(1441,11); WHEN "0100100011" => manhi <= conv_std_logic_vector(12928905,24); manlo <= conv_std_logic_vector(16004876,28); exponent <= conv_std_logic_vector(1442,11); WHEN "0100100100" => manhi <= conv_std_logic_vector(3410186,24); manlo <= conv_std_logic_vector(71831800,28); exponent <= conv_std_logic_vector(1444,11); WHEN "0100100101" => manhi <= conv_std_logic_vector(10660308,24); manlo <= conv_std_logic_vector(100367284,28); exponent <= conv_std_logic_vector(1445,11); WHEN "0100100110" => manhi <= conv_std_logic_vector(1868514,24); manlo <= conv_std_logic_vector(263299419,28); exponent <= conv_std_logic_vector(1447,11); WHEN "0100100111" => manhi <= conv_std_logic_vector(8564959,24); manlo <= conv_std_logic_vector(228656810,28); exponent <= conv_std_logic_vector(1448,11); WHEN "0100101000" => manhi <= conv_std_logic_vector(444578,24); manlo <= conv_std_logic_vector(7489141,28); exponent <= conv_std_logic_vector(1450,11); WHEN "0100101001" => manhi <= conv_std_logic_vector(6629628,24); manlo <= conv_std_logic_vector(236156491,28); exponent <= conv_std_logic_vector(1451,11); WHEN "0100101010" => manhi <= conv_std_logic_vector(15035984,24); manlo <= conv_std_logic_vector(147396312,28); exponent <= conv_std_logic_vector(1452,11); WHEN "0100101011" => manhi <= conv_std_logic_vector(4842095,24); manlo <= conv_std_logic_vector(64271882,28); exponent <= conv_std_logic_vector(1454,11); WHEN "0100101100" => manhi <= conv_std_logic_vector(12606474,24); manlo <= conv_std_logic_vector(118909770,28); exponent <= conv_std_logic_vector(1455,11); WHEN "0100101101" => manhi <= conv_std_logic_vector(3191071,24); manlo <= conv_std_logic_vector(253953386,28); exponent <= conv_std_logic_vector(1457,11); WHEN "0100101110" => manhi <= conv_std_logic_vector(10362501,24); manlo <= conv_std_logic_vector(36129498,28); exponent <= conv_std_logic_vector(1458,11); WHEN "0100101111" => manhi <= conv_std_logic_vector(1666133,24); manlo <= conv_std_logic_vector(262830684,28); exponent <= conv_std_logic_vector(1460,11); WHEN "0100110000" => manhi <= conv_std_logic_vector(8289895,24); manlo <= conv_std_logic_vector(148197046,28); exponent <= conv_std_logic_vector(1461,11); WHEN "0100110001" => manhi <= conv_std_logic_vector(257652,24); manlo <= conv_std_logic_vector(122404338,28); exponent <= conv_std_logic_vector(1463,11); WHEN "0100110010" => manhi <= conv_std_logic_vector(6375570,24); manlo <= conv_std_logic_vector(184430245,28); exponent <= conv_std_logic_vector(1464,11); WHEN "0100110011" => manhi <= conv_std_logic_vector(14690683,24); manlo <= conv_std_logic_vector(178457687,28); exponent <= conv_std_logic_vector(1465,11); WHEN "0100110100" => manhi <= conv_std_logic_vector(4607438,24); manlo <= conv_std_logic_vector(257605193,28); exponent <= conv_std_logic_vector(1467,11); WHEN "0100110101" => manhi <= conv_std_logic_vector(12287543,24); manlo <= conv_std_logic_vector(132163446,28); exponent <= conv_std_logic_vector(1468,11); WHEN "0100110110" => manhi <= conv_std_logic_vector(2974335,24); manlo <= conv_std_logic_vector(240020217,28); exponent <= conv_std_logic_vector(1470,11); WHEN "0100110111" => manhi <= conv_std_logic_vector(10067926,24); manlo <= conv_std_logic_vector(80224641,28); exponent <= conv_std_logic_vector(1471,11); WHEN "0100111000" => manhi <= conv_std_logic_vector(1465949,24); manlo <= conv_std_logic_vector(167328478,28); exponent <= conv_std_logic_vector(1473,11); WHEN "0100111001" => manhi <= conv_std_logic_vector(8017816,24); manlo <= conv_std_logic_vector(215756784,28); exponent <= conv_std_logic_vector(1474,11); WHEN "0100111010" => manhi <= conv_std_logic_vector(72755,24); manlo <= conv_std_logic_vector(208473528,28); exponent <= conv_std_logic_vector(1476,11); WHEN "0100111011" => manhi <= conv_std_logic_vector(6124270,24); manlo <= conv_std_logic_vector(12139444,28); exponent <= conv_std_logic_vector(1477,11); WHEN "0100111100" => manhi <= conv_std_logic_vector(14349130,24); manlo <= conv_std_logic_vector(182729110,28); exponent <= conv_std_logic_vector(1478,11); WHEN "0100111101" => manhi <= conv_std_logic_vector(4375329,24); manlo <= conv_std_logic_vector(172370119,28); exponent <= conv_std_logic_vector(1480,11); WHEN "0100111110" => manhi <= conv_std_logic_vector(11972074,24); manlo <= conv_std_logic_vector(59679792,28); exponent <= conv_std_logic_vector(1481,11); WHEN "0100111111" => manhi <= conv_std_logic_vector(2759952,24); manlo <= conv_std_logic_vector(80023302,28); exponent <= conv_std_logic_vector(1483,11); WHEN "0101000000" => manhi <= conv_std_logic_vector(9776548,24); manlo <= conv_std_logic_vector(209956608,28); exponent <= conv_std_logic_vector(1484,11); WHEN "0101000001" => manhi <= conv_std_logic_vector(1267938,24); manlo <= conv_std_logic_vector(19091951,28); exponent <= conv_std_logic_vector(1486,11); WHEN "0101000010" => manhi <= conv_std_logic_vector(7748691,24); manlo <= conv_std_logic_vector(54127000,28); exponent <= conv_std_logic_vector(1487,11); WHEN "0101000011" => manhi <= conv_std_logic_vector(16556947,24); manlo <= conv_std_logic_vector(251347868,28); exponent <= conv_std_logic_vector(1488,11); WHEN "0101000100" => manhi <= conv_std_logic_vector(5875697,24); manlo <= conv_std_logic_vector(6377900,28); exponent <= conv_std_logic_vector(1490,11); WHEN "0101000101" => manhi <= conv_std_logic_vector(14011284,24); manlo <= conv_std_logic_vector(246175281,28); exponent <= conv_std_logic_vector(1491,11); WHEN "0101000110" => manhi <= conv_std_logic_vector(4145739,24); manlo <= conv_std_logic_vector(172360927,28); exponent <= conv_std_logic_vector(1493,11); WHEN "0101000111" => manhi <= conv_std_logic_vector(11660029,24); manlo <= conv_std_logic_vector(16047086,28); exponent <= conv_std_logic_vector(1494,11); WHEN "0101001000" => manhi <= conv_std_logic_vector(2547895,24); manlo <= conv_std_logic_vector(167600151,28); exponent <= conv_std_logic_vector(1496,11); WHEN "0101001001" => manhi <= conv_std_logic_vector(9488333,24); manlo <= conv_std_logic_vector(236416250,28); exponent <= conv_std_logic_vector(1497,11); WHEN "0101001010" => manhi <= conv_std_logic_vector(1072075,24); manlo <= conv_std_logic_vector(198323037,28); exponent <= conv_std_logic_vector(1499,11); WHEN "0101001011" => manhi <= conv_std_logic_vector(7482486,24); manlo <= conv_std_logic_vector(185820926,28); exponent <= conv_std_logic_vector(1500,11); WHEN "0101001100" => manhi <= conv_std_logic_vector(16195138,24); manlo <= conv_std_logic_vector(133160968,28); exponent <= conv_std_logic_vector(1501,11); WHEN "0101001101" => manhi <= conv_std_logic_vector(5629822,24); manlo <= conv_std_logic_vector(4574050,28); exponent <= conv_std_logic_vector(1503,11); WHEN "0101001110" => manhi <= conv_std_logic_vector(13677106,24); manlo <= conv_std_logic_vector(36414601,28); exponent <= conv_std_logic_vector(1504,11); WHEN "0101001111" => manhi <= conv_std_logic_vector(3918641,24); manlo <= conv_std_logic_vector(165046798,28); exponent <= conv_std_logic_vector(1506,11); WHEN "0101010000" => manhi <= conv_std_logic_vector(11351370,24); manlo <= conv_std_logic_vector(225326735,28); exponent <= conv_std_logic_vector(1507,11); WHEN "0101010001" => manhi <= conv_std_logic_vector(2338140,24); manlo <= conv_std_logic_vector(165476611,28); exponent <= conv_std_logic_vector(1509,11); WHEN "0101010010" => manhi <= conv_std_logic_vector(9203247,24); manlo <= conv_std_logic_vector(71807303,28); exponent <= conv_std_logic_vector(1510,11); WHEN "0101010011" => manhi <= conv_std_logic_vector(878339,24); manlo <= conv_std_logic_vector(80195176,28); exponent <= conv_std_logic_vector(1512,11); WHEN "0101010100" => manhi <= conv_std_logic_vector(7219171,24); manlo <= conv_std_logic_vector(153001068,28); exponent <= conv_std_logic_vector(1513,11); WHEN "0101010101" => manhi <= conv_std_logic_vector(15837256,24); manlo <= conv_std_logic_vector(37596960,28); exponent <= conv_std_logic_vector(1514,11); WHEN "0101010110" => manhi <= conv_std_logic_vector(5386615,24); manlo <= conv_std_logic_vector(198850796,28); exponent <= conv_std_logic_vector(1516,11); WHEN "0101010111" => manhi <= conv_std_logic_vector(13346554,24); manlo <= conv_std_logic_vector(143609986,28); exponent <= conv_std_logic_vector(1517,11); WHEN "0101011000" => manhi <= conv_std_logic_vector(3694008,24); manlo <= conv_std_logic_vector(137568494,28); exponent <= conv_std_logic_vector(1519,11); WHEN "0101011001" => manhi <= conv_std_logic_vector(11046062,24); manlo <= conv_std_logic_vector(214558683,28); exponent <= conv_std_logic_vector(1520,11); WHEN "0101011010" => manhi <= conv_std_logic_vector(2130662,24); manlo <= conv_std_logic_vector(78401205,28); exponent <= conv_std_logic_vector(1522,11); WHEN "0101011011" => manhi <= conv_std_logic_vector(8921254,24); manlo <= conv_std_logic_vector(265219821,28); exponent <= conv_std_logic_vector(1523,11); WHEN "0101011100" => manhi <= conv_std_logic_vector(686705,24); manlo <= conv_std_logic_vector(181591149,28); exponent <= conv_std_logic_vector(1525,11); WHEN "0101011101" => manhi <= conv_std_logic_vector(6958714,24); manlo <= conv_std_logic_vector(127078273,28); exponent <= conv_std_logic_vector(1526,11); WHEN "0101011110" => manhi <= conv_std_logic_vector(15483258,24); manlo <= conv_std_logic_vector(65420394,28); exponent <= conv_std_logic_vector(1527,11); WHEN "0101011111" => manhi <= conv_std_logic_vector(5146049,24); manlo <= conv_std_logic_vector(61347424,28); exponent <= conv_std_logic_vector(1529,11); WHEN "0101100000" => manhi <= conv_std_logic_vector(13019590,24); manlo <= conv_std_logic_vector(200148168,28); exponent <= conv_std_logic_vector(1530,11); WHEN "0101100001" => manhi <= conv_std_logic_vector(3471813,24); manlo <= conv_std_logic_vector(155873600,28); exponent <= conv_std_logic_vector(1532,11); WHEN "0101100010" => manhi <= conv_std_logic_vector(10744068,24); manlo <= conv_std_logic_vector(154763366,28); exponent <= conv_std_logic_vector(1533,11); WHEN "0101100011" => manhi <= conv_std_logic_vector(1925435,24); manlo <= conv_std_logic_vector(252346422,28); exponent <= conv_std_logic_vector(1535,11); WHEN "0101100100" => manhi <= conv_std_logic_vector(8642323,24); manlo <= conv_std_logic_vector(122496413,28); exponent <= conv_std_logic_vector(1536,11); WHEN "0101100101" => manhi <= conv_std_logic_vector(497152,24); manlo <= conv_std_logic_vector(12881703,28); exponent <= conv_std_logic_vector(1538,11); WHEN "0101100110" => manhi <= conv_std_logic_vector(6701084,24); manlo <= conv_std_logic_vector(102402698,28); exponent <= conv_std_logic_vector(1539,11); WHEN "0101100111" => manhi <= conv_std_logic_vector(15133102,24); manlo <= conv_std_logic_vector(173151546,28); exponent <= conv_std_logic_vector(1540,11); WHEN "0101101000" => manhi <= conv_std_logic_vector(4908093,24); manlo <= conv_std_logic_vector(222341698,28); exponent <= conv_std_logic_vector(1542,11); WHEN "0101101001" => manhi <= conv_std_logic_vector(12696175,24); manlo <= conv_std_logic_vector(221558290,28); exponent <= conv_std_logic_vector(1543,11); WHEN "0101101010" => manhi <= conv_std_logic_vector(3252030,24); manlo <= conv_std_logic_vector(95425703,28); exponent <= conv_std_logic_vector(1545,11); WHEN "0101101011" => manhi <= conv_std_logic_vector(10445352,24); manlo <= conv_std_logic_vector(54472775,28); exponent <= conv_std_logic_vector(1546,11); WHEN "0101101100" => manhi <= conv_std_logic_vector(1722437,24); manlo <= conv_std_logic_vector(31541381,28); exponent <= conv_std_logic_vector(1548,11); WHEN "0101101101" => manhi <= conv_std_logic_vector(8366419,24); manlo <= conv_std_logic_vector(121077564,28); exponent <= conv_std_logic_vector(1549,11); WHEN "0101101110" => manhi <= conv_std_logic_vector(309655,24); manlo <= conv_std_logic_vector(224679493,28); exponent <= conv_std_logic_vector(1551,11); WHEN "0101101111" => manhi <= conv_std_logic_vector(6446250,24); manlo <= conv_std_logic_vector(163707479,28); exponent <= conv_std_logic_vector(1552,11); WHEN "0101110000" => manhi <= conv_std_logic_vector(14786747,24); manlo <= conv_std_logic_vector(171718440,28); exponent <= conv_std_logic_vector(1553,11); WHEN "0101110001" => manhi <= conv_std_logic_vector(4672721,24); manlo <= conv_std_logic_vector(53414720,28); exponent <= conv_std_logic_vector(1555,11); WHEN "0101110010" => manhi <= conv_std_logic_vector(12376271,24); manlo <= conv_std_logic_vector(68395953,28); exponent <= conv_std_logic_vector(1556,11); WHEN "0101110011" => manhi <= conv_std_logic_vector(3034632,24); manlo <= conv_std_logic_vector(177229210,28); exponent <= conv_std_logic_vector(1558,11); WHEN "0101110100" => manhi <= conv_std_logic_vector(10149878,24); manlo <= conv_std_logic_vector(27015960,28); exponent <= conv_std_logic_vector(1559,11); WHEN "0101110101" => manhi <= conv_std_logic_vector(1521641,24); manlo <= conv_std_logic_vector(173609470,28); exponent <= conv_std_logic_vector(1561,11); WHEN "0101110110" => manhi <= conv_std_logic_vector(8093510,24); manlo <= conv_std_logic_vector(29891310,28); exponent <= conv_std_logic_vector(1562,11); WHEN "0101110111" => manhi <= conv_std_logic_vector(124194,24); manlo <= conv_std_logic_vector(191198183,28); exponent <= conv_std_logic_vector(1564,11); WHEN "0101111000" => manhi <= conv_std_logic_vector(6194182,24); manlo <= conv_std_logic_vector(216692261,28); exponent <= conv_std_logic_vector(1565,11); WHEN "0101111001" => manhi <= conv_std_logic_vector(14444151,24); manlo <= conv_std_logic_vector(261994424,28); exponent <= conv_std_logic_vector(1566,11); WHEN "0101111010" => manhi <= conv_std_logic_vector(4439903,24); manlo <= conv_std_logic_vector(82463931,28); exponent <= conv_std_logic_vector(1568,11); WHEN "0101111011" => manhi <= conv_std_logic_vector(12059838,24); manlo <= conv_std_logic_vector(250318074,28); exponent <= conv_std_logic_vector(1569,11); WHEN "0101111100" => manhi <= conv_std_logic_vector(2819594,24); manlo <= conv_std_logic_vector(161686084,28); exponent <= conv_std_logic_vector(1571,11); WHEN "0101111101" => manhi <= conv_std_logic_vector(9857611,24); manlo <= conv_std_logic_vector(20946108,28); exponent <= conv_std_logic_vector(1572,11); WHEN "0101111110" => manhi <= conv_std_logic_vector(1323025,24); manlo <= conv_std_logic_vector(164440795,28); exponent <= conv_std_logic_vector(1574,11); WHEN "0101111111" => manhi <= conv_std_logic_vector(7823562,24); manlo <= conv_std_logic_vector(250479918,28); exponent <= conv_std_logic_vector(1575,11); WHEN "0110000000" => manhi <= conv_std_logic_vector(16658709,24); manlo <= conv_std_logic_vector(45608811,28); exponent <= conv_std_logic_vector(1576,11); WHEN "0110000001" => manhi <= conv_std_logic_vector(5944850,24); manlo <= conv_std_logic_vector(255488281,28); exponent <= conv_std_logic_vector(1578,11); WHEN "0110000010" => manhi <= conv_std_logic_vector(14105274,24); manlo <= conv_std_logic_vector(228172930,28); exponent <= conv_std_logic_vector(1579,11); WHEN "0110000011" => manhi <= conv_std_logic_vector(4209612,24); manlo <= conv_std_logic_vector(113758652,28); exponent <= conv_std_logic_vector(1581,11); WHEN "0110000100" => manhi <= conv_std_logic_vector(11746841,24); manlo <= conv_std_logic_vector(45816542,28); exponent <= conv_std_logic_vector(1582,11); WHEN "0110000101" => manhi <= conv_std_logic_vector(2606890,24); manlo <= conv_std_logic_vector(153074390,28); exponent <= conv_std_logic_vector(1584,11); WHEN "0110000110" => manhi <= conv_std_logic_vector(9568516,24); manlo <= conv_std_logic_vector(87350878,28); exponent <= conv_std_logic_vector(1585,11); WHEN "0110000111" => manhi <= conv_std_logic_vector(1126565,24); manlo <= conv_std_logic_vector(96475766,28); exponent <= conv_std_logic_vector(1587,11); WHEN "0110001000" => manhi <= conv_std_logic_vector(7556545,24); manlo <= conv_std_logic_vector(205347948,28); exponent <= conv_std_logic_vector(1588,11); WHEN "0110001001" => manhi <= conv_std_logic_vector(16295795,24); manlo <= conv_std_logic_vector(56881285,28); exponent <= conv_std_logic_vector(1589,11); WHEN "0110001010" => manhi <= conv_std_logic_vector(5698225,24); manlo <= conv_std_logic_vector(93263076,28); exponent <= conv_std_logic_vector(1591,11); WHEN "0110001011" => manhi <= conv_std_logic_vector(13770075,24); manlo <= conv_std_logic_vector(241769289,28); exponent <= conv_std_logic_vector(1592,11); WHEN "0110001100" => manhi <= conv_std_logic_vector(3981821,24); manlo <= conv_std_logic_vector(32359920,28); exponent <= conv_std_logic_vector(1594,11); WHEN "0110001101" => manhi <= conv_std_logic_vector(11437240,24); manlo <= conv_std_logic_vector(185367850,28); exponent <= conv_std_logic_vector(1595,11); WHEN "0110001110" => manhi <= conv_std_logic_vector(2396495,24); manlo <= conv_std_logic_vector(61858550,28); exponent <= conv_std_logic_vector(1597,11); WHEN "0110001111" => manhi <= conv_std_logic_vector(9282559,24); manlo <= conv_std_logic_vector(110304027,28); exponent <= conv_std_logic_vector(1598,11); WHEN "0110010000" => manhi <= conv_std_logic_vector(932237,24); manlo <= conv_std_logic_vector(131077892,28); exponent <= conv_std_logic_vector(1600,11); WHEN "0110010001" => manhi <= conv_std_logic_vector(7292426,24); manlo <= conv_std_logic_vector(215982528,28); exponent <= conv_std_logic_vector(1601,11); WHEN "0110010010" => manhi <= conv_std_logic_vector(15936820,24); manlo <= conv_std_logic_vector(87676082,28); exponent <= conv_std_logic_vector(1602,11); WHEN "0110010011" => manhi <= conv_std_logic_vector(5454276,24); manlo <= conv_std_logic_vector(166577430,28); exponent <= conv_std_logic_vector(1604,11); WHEN "0110010100" => manhi <= conv_std_logic_vector(13438515,24); manlo <= conv_std_logic_vector(55023964,28); exponent <= conv_std_logic_vector(1605,11); WHEN "0110010101" => manhi <= conv_std_logic_vector(3756502,24); manlo <= conv_std_logic_vector(71679026,28); exponent <= conv_std_logic_vector(1607,11); WHEN "0110010110" => manhi <= conv_std_logic_vector(11131000,24); manlo <= conv_std_logic_vector(165886683,28); exponent <= conv_std_logic_vector(1608,11); WHEN "0110010111" => manhi <= conv_std_logic_vector(2188383,24); manlo <= conv_std_logic_vector(140750309,28); exponent <= conv_std_logic_vector(1610,11); WHEN "0110011000" => manhi <= conv_std_logic_vector(8999706,24); manlo <= conv_std_logic_vector(74200045,28); exponent <= conv_std_logic_vector(1611,11); WHEN "0110011001" => manhi <= conv_std_logic_vector(740018,24); manlo <= conv_std_logic_vector(229350227,28); exponent <= conv_std_logic_vector(1613,11); WHEN "0110011010" => manhi <= conv_std_logic_vector(7031174,24); manlo <= conv_std_logic_vector(159659309,28); exponent <= conv_std_logic_vector(1614,11); WHEN "0110011011" => manhi <= conv_std_logic_vector(15581741,24); manlo <= conv_std_logic_vector(203828183,28); exponent <= conv_std_logic_vector(1615,11); WHEN "0110011100" => manhi <= conv_std_logic_vector(5212975,24); manlo <= conv_std_logic_vector(192268981,28); exponent <= conv_std_logic_vector(1617,11); WHEN "0110011101" => manhi <= conv_std_logic_vector(13110553,24); manlo <= conv_std_logic_vector(73367990,28); exponent <= conv_std_logic_vector(1618,11); WHEN "0110011110" => manhi <= conv_std_logic_vector(3533629,24); manlo <= conv_std_logic_vector(7303751,28); exponent <= conv_std_logic_vector(1620,11); WHEN "0110011111" => manhi <= conv_std_logic_vector(10828084,24); manlo <= conv_std_logic_vector(128595197,28); exponent <= conv_std_logic_vector(1621,11); WHEN "0110100000" => manhi <= conv_std_logic_vector(1982530,24); manlo <= conv_std_logic_vector(178601213,28); exponent <= conv_std_logic_vector(1623,11); WHEN "0110100001" => manhi <= conv_std_logic_vector(8719923,24); manlo <= conv_std_logic_vector(62665264,28); exponent <= conv_std_logic_vector(1624,11); WHEN "0110100010" => manhi <= conv_std_logic_vector(549886,24); manlo <= conv_std_logic_vector(151395401,28); exponent <= conv_std_logic_vector(1626,11); WHEN "0110100011" => manhi <= conv_std_logic_vector(6772758,24); manlo <= conv_std_logic_vector(5307652,28); exponent <= conv_std_logic_vector(1627,11); WHEN "0110100100" => manhi <= conv_std_logic_vector(15230517,24); manlo <= conv_std_logic_vector(58871965,28); exponent <= conv_std_logic_vector(1628,11); WHEN "0110100101" => manhi <= conv_std_logic_vector(4974293,24); manlo <= conv_std_logic_vector(240265124,28); exponent <= conv_std_logic_vector(1630,11); WHEN "0110100110" => manhi <= conv_std_logic_vector(12786151,24); manlo <= conv_std_logic_vector(11983156,28); exponent <= conv_std_logic_vector(1631,11); WHEN "0110100111" => manhi <= conv_std_logic_vector(3313174,24); manlo <= conv_std_logic_vector(229882212,28); exponent <= conv_std_logic_vector(1633,11); WHEN "0110101000" => manhi <= conv_std_logic_vector(10528456,24); manlo <= conv_std_logic_vector(52550536,28); exponent <= conv_std_logic_vector(1634,11); WHEN "0110101001" => manhi <= conv_std_logic_vector(1778912,24); manlo <= conv_std_logic_vector(36481057,28); exponent <= conv_std_logic_vector(1636,11); WHEN "0110101010" => manhi <= conv_std_logic_vector(8443176,24); manlo <= conv_std_logic_vector(257480801,28); exponent <= conv_std_logic_vector(1637,11); WHEN "0110101011" => manhi <= conv_std_logic_vector(361817,24); manlo <= conv_std_logic_vector(260890045,28); exponent <= conv_std_logic_vector(1639,11); WHEN "0110101100" => manhi <= conv_std_logic_vector(6517146,24); manlo <= conv_std_logic_vector(80951272,28); exponent <= conv_std_logic_vector(1640,11); WHEN "0110101101" => manhi <= conv_std_logic_vector(14883104,24); manlo <= conv_std_logic_vector(234866389,28); exponent <= conv_std_logic_vector(1641,11); WHEN "0110101110" => manhi <= conv_std_logic_vector(4738202,24); manlo <= conv_std_logic_vector(195793257,28); exponent <= conv_std_logic_vector(1643,11); WHEN "0110101111" => manhi <= conv_std_logic_vector(12465269,24); manlo <= conv_std_logic_vector(236730454,28); exponent <= conv_std_logic_vector(1644,11); WHEN "0110110000" => manhi <= conv_std_logic_vector(3095113,24); manlo <= conv_std_logic_vector(133661452,28); exponent <= conv_std_logic_vector(1646,11); WHEN "0110110001" => manhi <= conv_std_logic_vector(10232080,24); manlo <= conv_std_logic_vector(21926822,28); exponent <= conv_std_logic_vector(1647,11); WHEN "0110110010" => manhi <= conv_std_logic_vector(1577503,24); manlo <= conv_std_logic_vector(183764948,28); exponent <= conv_std_logic_vector(1649,11); WHEN "0110110011" => manhi <= conv_std_logic_vector(8169434,24); manlo <= conv_std_logic_vector(132210812,28); exponent <= conv_std_logic_vector(1650,11); WHEN "0110110100" => manhi <= conv_std_logic_vector(175790,24); manlo <= conv_std_logic_vector(182183516,28); exponent <= conv_std_logic_vector(1652,11); WHEN "0110110101" => manhi <= conv_std_logic_vector(6264308,24); manlo <= conv_std_logic_vector(267417858,28); exponent <= conv_std_logic_vector(1653,11); WHEN "0110110110" => manhi <= conv_std_logic_vector(14539463,24); manlo <= conv_std_logic_vector(93573944,28); exponent <= conv_std_logic_vector(1654,11); WHEN "0110110111" => manhi <= conv_std_logic_vector(4504674,24); manlo <= conv_std_logic_vector(26907375,28); exponent <= conv_std_logic_vector(1656,11); WHEN "0110111000" => manhi <= conv_std_logic_vector(12147871,24); manlo <= conv_std_logic_vector(152302066,28); exponent <= conv_std_logic_vector(1657,11); WHEN "0110111001" => manhi <= conv_std_logic_vector(2879418,24); manlo <= conv_std_logic_vector(263131635,28); exponent <= conv_std_logic_vector(1659,11); WHEN "0110111010" => manhi <= conv_std_logic_vector(9938920,24); manlo <= conv_std_logic_vector(224874222,28); exponent <= conv_std_logic_vector(1660,11); WHEN "0110111011" => manhi <= conv_std_logic_vector(1378281,24); manlo <= conv_std_logic_vector(86745210,28); exponent <= conv_std_logic_vector(1662,11); WHEN "0110111100" => manhi <= conv_std_logic_vector(7898663,24); manlo <= conv_std_logic_vector(61761420,28); exponent <= conv_std_logic_vector(1663,11); WHEN "0110111101" => manhi <= conv_std_logic_vector(16760781,24); manlo <= conv_std_logic_vector(15082626,28); exponent <= conv_std_logic_vector(1664,11); WHEN "0110111110" => manhi <= conv_std_logic_vector(6014215,24); manlo <= conv_std_logic_vector(265801199,28); exponent <= conv_std_logic_vector(1666,11); WHEN "0110111111" => manhi <= conv_std_logic_vector(14199551,24); manlo <= conv_std_logic_vector(191056853,28); exponent <= conv_std_logic_vector(1667,11); WHEN "0111000000" => manhi <= conv_std_logic_vector(4273680,24); manlo <= conv_std_logic_vector(52024524,28); exponent <= conv_std_logic_vector(1669,11); WHEN "0111000001" => manhi <= conv_std_logic_vector(11833918,24); manlo <= conv_std_logic_vector(80047690,28); exponent <= conv_std_logic_vector(1670,11); WHEN "0111000010" => manhi <= conv_std_logic_vector(2666065,24); manlo <= conv_std_logic_vector(164712049,28); exponent <= conv_std_logic_vector(1672,11); WHEN "0111000011" => manhi <= conv_std_logic_vector(9648943,24); manlo <= conv_std_logic_vector(147084012,28); exponent <= conv_std_logic_vector(1673,11); WHEN "0111000100" => manhi <= conv_std_logic_vector(1181221,24); manlo <= conv_std_logic_vector(86912647,28); exponent <= conv_std_logic_vector(1675,11); WHEN "0111000101" => manhi <= conv_std_logic_vector(7630830,24); manlo <= conv_std_logic_vector(247596521,28); exponent <= conv_std_logic_vector(1676,11); WHEN "0111000110" => manhi <= conv_std_logic_vector(16396759,24); manlo <= conv_std_logic_vector(56002502,28); exponent <= conv_std_logic_vector(1677,11); WHEN "0111000111" => manhi <= conv_std_logic_vector(5766837,24); manlo <= conv_std_logic_vector(133369322,28); exponent <= conv_std_logic_vector(1679,11); WHEN "0111001000" => manhi <= conv_std_logic_vector(13863329,24); manlo <= conv_std_logic_vector(128884889,28); exponent <= conv_std_logic_vector(1680,11); WHEN "0111001001" => manhi <= conv_std_logic_vector(4045193,24); manlo <= conv_std_logic_vector(133729186,28); exponent <= conv_std_logic_vector(1682,11); WHEN "0111001010" => manhi <= conv_std_logic_vector(11523372,24); manlo <= conv_std_logic_vector(183024104,28); exponent <= conv_std_logic_vector(1683,11); WHEN "0111001011" => manhi <= conv_std_logic_vector(2455027,24); manlo <= conv_std_logic_vector(264977965,28); exponent <= conv_std_logic_vector(1685,11); WHEN "0111001100" => manhi <= conv_std_logic_vector(9362113,24); manlo <= conv_std_logic_vector(181285013,28); exponent <= conv_std_logic_vector(1686,11); WHEN "0111001101" => manhi <= conv_std_logic_vector(986300,24); manlo <= conv_std_logic_vector(58020653,28); exponent <= conv_std_logic_vector(1688,11); WHEN "0111001110" => manhi <= conv_std_logic_vector(7365905,24); manlo <= conv_std_logic_vector(179835810,28); exponent <= conv_std_logic_vector(1689,11); WHEN "0111001111" => manhi <= conv_std_logic_vector(16036688,24); manlo <= conv_std_logic_vector(123168298,28); exponent <= conv_std_logic_vector(1690,11); WHEN "0111010000" => manhi <= conv_std_logic_vector(5522144,24); manlo <= conv_std_logic_vector(14176725,28); exponent <= conv_std_logic_vector(1692,11); WHEN "0111010001" => manhi <= conv_std_logic_vector(13530756,24); manlo <= conv_std_logic_vector(163453775,28); exponent <= conv_std_logic_vector(1693,11); WHEN "0111010010" => manhi <= conv_std_logic_vector(3819186,24); manlo <= conv_std_logic_vector(214764608,28); exponent <= conv_std_logic_vector(1695,11); WHEN "0111010011" => manhi <= conv_std_logic_vector(11216197,24); manlo <= conv_std_logic_vector(196364225,28); exponent <= conv_std_logic_vector(1696,11); WHEN "0111010100" => manhi <= conv_std_logic_vector(2246280,24); manlo <= conv_std_logic_vector(259235483,28); exponent <= conv_std_logic_vector(1698,11); WHEN "0111010101" => manhi <= conv_std_logic_vector(9078397,24); manlo <= conv_std_logic_vector(15526664,28); exponent <= conv_std_logic_vector(1699,11); WHEN "0111010110" => manhi <= conv_std_logic_vector(793494,24); manlo <= conv_std_logic_vector(210641201,28); exponent <= conv_std_logic_vector(1701,11); WHEN "0111010111" => manhi <= conv_std_logic_vector(7103855,24); manlo <= conv_std_logic_vector(246847656,28); exponent <= conv_std_logic_vector(1702,11); WHEN "0111011000" => manhi <= conv_std_logic_vector(15680525,24); manlo <= conv_std_logic_vector(247378795,28); exponent <= conv_std_logic_vector(1703,11); WHEN "0111011001" => manhi <= conv_std_logic_vector(5280106,24); manlo <= conv_std_logic_vector(138122391,28); exponent <= conv_std_logic_vector(1705,11); WHEN "0111011010" => manhi <= conv_std_logic_vector(13201793,24); manlo <= conv_std_logic_vector(130963079,28); exponent <= conv_std_logic_vector(1706,11); WHEN "0111011011" => manhi <= conv_std_logic_vector(3595633,24); manlo <= conv_std_logic_vector(48727293,28); exponent <= conv_std_logic_vector(1708,11); WHEN "0111011100" => manhi <= conv_std_logic_vector(10912356,24); manlo <= conv_std_logic_vector(231400966,28); exponent <= conv_std_logic_vector(1709,11); WHEN "0111011101" => manhi <= conv_std_logic_vector(2039799,24); manlo <= conv_std_logic_vector(184459756,28); exponent <= conv_std_logic_vector(1711,11); WHEN "0111011110" => manhi <= conv_std_logic_vector(8797759,24); manlo <= conv_std_logic_vector(242699544,28); exponent <= conv_std_logic_vector(1712,11); WHEN "0111011111" => manhi <= conv_std_logic_vector(602782,24); manlo <= conv_std_logic_vector(17680793,28); exponent <= conv_std_logic_vector(1714,11); WHEN "0111100000" => manhi <= conv_std_logic_vector(6844650,24); manlo <= conv_std_logic_vector(123627565,28); exponent <= conv_std_logic_vector(1715,11); WHEN "0111100001" => manhi <= conv_std_logic_vector(15328229,24); manlo <= conv_std_logic_vector(47512453,28); exponent <= conv_std_logic_vector(1716,11); WHEN "0111100010" => manhi <= conv_std_logic_vector(5040696,24); manlo <= conv_std_logic_vector(14711664,28); exponent <= conv_std_logic_vector(1718,11); WHEN "0111100011" => manhi <= conv_std_logic_vector(12876400,24); manlo <= conv_std_logic_vector(251456186,28); exponent <= conv_std_logic_vector(1719,11); WHEN "0111100100" => manhi <= conv_std_logic_vector(3374506,24); manlo <= conv_std_logic_vector(4512772,28); exponent <= conv_std_logic_vector(1721,11); WHEN "0111100101" => manhi <= conv_std_logic_vector(10611813,24); manlo <= conv_std_logic_vector(237626642,28); exponent <= conv_std_logic_vector(1722,11); WHEN "0111100110" => manhi <= conv_std_logic_vector(1835559,24); manlo <= conv_std_logic_vector(150064655,28); exponent <= conv_std_logic_vector(1724,11); WHEN "0111100111" => manhi <= conv_std_logic_vector(8520168,24); manlo <= conv_std_logic_vector(211971382,28); exponent <= conv_std_logic_vector(1725,11); WHEN "0111101000" => manhi <= conv_std_logic_vector(414139,24); manlo <= conv_std_logic_vector(92694471,28); exponent <= conv_std_logic_vector(1727,11); WHEN "0111101001" => manhi <= conv_std_logic_vector(6588258,24); manlo <= conv_std_logic_vector(112977613,28); exponent <= conv_std_logic_vector(1728,11); WHEN "0111101010" => manhi <= conv_std_logic_vector(14979756,24); manlo <= conv_std_logic_vector(71348470,28); exponent <= conv_std_logic_vector(1729,11); WHEN "0111101011" => manhi <= conv_std_logic_vector(4803884,24); manlo <= conv_std_logic_vector(42747344,28); exponent <= conv_std_logic_vector(1731,11); WHEN "0111101100" => manhi <= conv_std_logic_vector(12554540,24); manlo <= conv_std_logic_vector(53825836,28); exponent <= conv_std_logic_vector(1732,11); WHEN "0111101101" => manhi <= conv_std_logic_vector(3155778,24); manlo <= conv_std_logic_vector(260157975,28); exponent <= conv_std_logic_vector(1734,11); WHEN "0111101110" => manhi <= conv_std_logic_vector(10314533,24); manlo <= conv_std_logic_vector(1535990,28); exponent <= conv_std_logic_vector(1735,11); WHEN "0111101111" => manhi <= conv_std_logic_vector(1633536,24); manlo <= conv_std_logic_vector(68681060,28); exponent <= conv_std_logic_vector(1737,11); WHEN "0111110000" => manhi <= conv_std_logic_vector(8245590,24); manlo <= conv_std_logic_vector(175202070,28); exponent <= conv_std_logic_vector(1738,11); WHEN "0111110001" => manhi <= conv_std_logic_vector(227544,24); manlo <= conv_std_logic_vector(41675965,28); exponent <= conv_std_logic_vector(1740,11); WHEN "0111110010" => manhi <= conv_std_logic_vector(6334649,24); manlo <= conv_std_logic_vector(70777607,28); exponent <= conv_std_logic_vector(1741,11); WHEN "0111110011" => manhi <= conv_std_logic_vector(14635065,24); manlo <= conv_std_logic_vector(183612561,28); exponent <= conv_std_logic_vector(1742,11); WHEN "0111110100" => manhi <= conv_std_logic_vector(4569642,24); manlo <= conv_std_logic_vector(167240760,28); exponent <= conv_std_logic_vector(1744,11); WHEN "0111110101" => manhi <= conv_std_logic_vector(12236172,24); manlo <= conv_std_logic_vector(253623266,28); exponent <= conv_std_logic_vector(1745,11); WHEN "0111110110" => manhi <= conv_std_logic_vector(2939425,24); manlo <= conv_std_logic_vector(265128301,28); exponent <= conv_std_logic_vector(1747,11); WHEN "0111110111" => manhi <= conv_std_logic_vector(10020478,24); manlo <= conv_std_logic_vector(219223569,28); exponent <= conv_std_logic_vector(1748,11); WHEN "0111111000" => manhi <= conv_std_logic_vector(1433705,24); manlo <= conv_std_logic_vector(192250058,28); exponent <= conv_std_logic_vector(1750,11); WHEN "0111111001" => manhi <= conv_std_logic_vector(7973992,24); manlo <= conv_std_logic_vector(212144821,28); exponent <= conv_std_logic_vector(1751,11); WHEN "0111111010" => manhi <= conv_std_logic_vector(42974,24); manlo <= conv_std_logic_vector(72952107,28); exponent <= conv_std_logic_vector(1753,11); WHEN "0111111011" => manhi <= conv_std_logic_vector(6083792,24); manlo <= conv_std_logic_vector(210315148,28); exponent <= conv_std_logic_vector(1754,11); WHEN "0111111100" => manhi <= conv_std_logic_vector(14294116,24); manlo <= conv_std_logic_vector(101520926,28); exponent <= conv_std_logic_vector(1755,11); WHEN "0111111101" => manhi <= conv_std_logic_vector(4337943,24); manlo <= conv_std_logic_vector(146945490,28); exponent <= conv_std_logic_vector(1757,11); WHEN "0111111110" => manhi <= conv_std_logic_vector(11921261,24); manlo <= conv_std_logic_vector(67478049,28); exponent <= conv_std_logic_vector(1758,11); WHEN "0111111111" => manhi <= conv_std_logic_vector(2725421,24); manlo <= conv_std_logic_vector(81662013,28); exponent <= conv_std_logic_vector(1760,11); WHEN "1000000000" => manhi <= conv_std_logic_vector(9729616,24); manlo <= conv_std_logic_vector(79332654,28); exponent <= conv_std_logic_vector(1761,11); WHEN "1000000001" => manhi <= conv_std_logic_vector(1236044,24); manlo <= conv_std_logic_vector(37511845,28); exponent <= conv_std_logic_vector(1763,11); WHEN "1000000010" => manhi <= conv_std_logic_vector(7705342,24); manlo <= conv_std_logic_vector(229400607,28); exponent <= conv_std_logic_vector(1764,11); WHEN "1000000011" => manhi <= conv_std_logic_vector(16498031,24); manlo <= conv_std_logic_vector(113896411,28); exponent <= conv_std_logic_vector(1765,11); WHEN "1000000100" => manhi <= conv_std_logic_vector(5835659,24); manlo <= conv_std_logic_vector(27578100,28); exponent <= conv_std_logic_vector(1767,11); WHEN "1000000101" => manhi <= conv_std_logic_vector(13956867,24); manlo <= conv_std_logic_vector(198774093,28); exponent <= conv_std_logic_vector(1768,11); WHEN "1000000110" => manhi <= conv_std_logic_vector(4108759,24); manlo <= conv_std_logic_vector(90336304,28); exponent <= conv_std_logic_vector(1770,11); WHEN "1000000111" => manhi <= conv_std_logic_vector(11609767,24); manlo <= conv_std_logic_vector(164675818,28); exponent <= conv_std_logic_vector(1771,11); WHEN "1000001000" => manhi <= conv_std_logic_vector(2513739,24); manlo <= conv_std_logic_vector(115510945,28); exponent <= conv_std_logic_vector(1773,11); WHEN "1000001001" => manhi <= conv_std_logic_vector(9441910,24); manlo <= conv_std_logic_vector(214725537,28); exponent <= conv_std_logic_vector(1774,11); WHEN "1000001010" => manhi <= conv_std_logic_vector(1040527,24); manlo <= conv_std_logic_vector(264292986,28); exponent <= conv_std_logic_vector(1776,11); WHEN "1000001011" => manhi <= conv_std_logic_vector(7439608,24); manlo <= conv_std_logic_vector(227819416,28); exponent <= conv_std_logic_vector(1777,11); WHEN "1000001100" => manhi <= conv_std_logic_vector(16136861,24); manlo <= conv_std_logic_vector(124712281,28); exponent <= conv_std_logic_vector(1778,11); WHEN "1000001101" => manhi <= conv_std_logic_vector(5590218,24); manlo <= conv_std_logic_vector(179347558,28); exponent <= conv_std_logic_vector(1780,11); WHEN "1000001110" => manhi <= conv_std_logic_vector(13623279,24); manlo <= conv_std_logic_vector(162081347,28); exponent <= conv_std_logic_vector(1781,11); WHEN "1000001111" => manhi <= conv_std_logic_vector(3882062,24); manlo <= conv_std_logic_vector(186291443,28); exponent <= conv_std_logic_vector(1783,11); WHEN "1000010000" => manhi <= conv_std_logic_vector(11301654,24); manlo <= conv_std_logic_vector(250040022,28); exponent <= conv_std_logic_vector(1784,11); WHEN "1000010001" => manhi <= conv_std_logic_vector(2304355,24); manlo <= conv_std_logic_vector(41383777,28); exponent <= conv_std_logic_vector(1786,11); WHEN "1000010010" => manhi <= conv_std_logic_vector(9157328,24); manlo <= conv_std_logic_vector(17021400,28); exponent <= conv_std_logic_vector(1787,11); WHEN "1000010011" => manhi <= conv_std_logic_vector(847133,24); manlo <= conv_std_logic_vector(258834653,28); exponent <= conv_std_logic_vector(1789,11); WHEN "1000010100" => manhi <= conv_std_logic_vector(7176759,24); manlo <= conv_std_logic_vector(33041815,28); exponent <= conv_std_logic_vector(1790,11); WHEN "1000010101" => manhi <= conv_std_logic_vector(15779611,24); manlo <= conv_std_logic_vector(174007449,28); exponent <= conv_std_logic_vector(1791,11); WHEN "1000010110" => manhi <= conv_std_logic_vector(5347442,24); manlo <= conv_std_logic_vector(66333886,28); exponent <= conv_std_logic_vector(1793,11); WHEN "1000010111" => manhi <= conv_std_logic_vector(13293312,24); manlo <= conv_std_logic_vector(63618366,28); exponent <= conv_std_logic_vector(1794,11); WHEN "1000011000" => manhi <= conv_std_logic_vector(3657826,24); manlo <= conv_std_logic_vector(166348998,28); exponent <= conv_std_logic_vector(1796,11); WHEN "1000011001" => manhi <= conv_std_logic_vector(10996886,24); manlo <= conv_std_logic_vector(136487624,28); exponent <= conv_std_logic_vector(1797,11); WHEN "1000011010" => manhi <= conv_std_logic_vector(2097243,24); manlo <= conv_std_logic_vector(144317262,28); exponent <= conv_std_logic_vector(1799,11); WHEN "1000011011" => manhi <= conv_std_logic_vector(8875834,24); manlo <= conv_std_logic_vector(51419886,28); exponent <= conv_std_logic_vector(1800,11); WHEN "1000011100" => manhi <= conv_std_logic_vector(655839,24); manlo <= conv_std_logic_vector(12096311,28); exponent <= conv_std_logic_vector(1802,11); WHEN "1000011101" => manhi <= conv_std_logic_vector(6916762,24); manlo <= conv_std_logic_vector(99793437,28); exponent <= conv_std_logic_vector(1803,11); WHEN "1000011110" => manhi <= conv_std_logic_vector(15426239,24); manlo <= conv_std_logic_vector(114334116,28); exponent <= conv_std_logic_vector(1804,11); WHEN "1000011111" => manhi <= conv_std_logic_vector(5107300,24); manlo <= conv_std_logic_vector(248161218,28); exponent <= conv_std_logic_vector(1806,11); WHEN "1000100000" => manhi <= conv_std_logic_vector(12966926,24); manlo <= conv_std_logic_vector(91321506,28); exponent <= conv_std_logic_vector(1807,11); WHEN "1000100001" => manhi <= conv_std_logic_vector(3436024,24); manlo <= conv_std_logic_vector(109150055,28); exponent <= conv_std_logic_vector(1809,11); WHEN "1000100010" => manhi <= conv_std_logic_vector(10695426,24); manlo <= conv_std_logic_vector(12291314,28); exponent <= conv_std_logic_vector(1810,11); WHEN "1000100011" => manhi <= conv_std_logic_vector(1892379,24); manlo <= conv_std_logic_vector(245137096,28); exponent <= conv_std_logic_vector(1812,11); WHEN "1000100100" => manhi <= conv_std_logic_vector(8597395,24); manlo <= conv_std_logic_vector(176569250,28); exponent <= conv_std_logic_vector(1813,11); WHEN "1000100101" => manhi <= conv_std_logic_vector(466620,24); manlo <= conv_std_logic_vector(119019308,28); exponent <= conv_std_logic_vector(1815,11); WHEN "1000100110" => manhi <= conv_std_logic_vector(6659587,24); manlo <= conv_std_logic_vector(168706814,28); exponent <= conv_std_logic_vector(1816,11); WHEN "1000100111" => manhi <= conv_std_logic_vector(15076702,24); manlo <= conv_std_logic_vector(190651618,28); exponent <= conv_std_logic_vector(1817,11); WHEN "1000101000" => manhi <= conv_std_logic_vector(4869766,24); manlo <= conv_std_logic_vector(26523901,28); exponent <= conv_std_logic_vector(1819,11); WHEN "1000101001" => manhi <= conv_std_logic_vector(12644083,24); manlo <= conv_std_logic_vector(10760420,28); exponent <= conv_std_logic_vector(1820,11); WHEN "1000101010" => manhi <= conv_std_logic_vector(3216629,24); manlo <= conv_std_logic_vector(171149379,28); exponent <= conv_std_logic_vector(1822,11); WHEN "1000101011" => manhi <= conv_std_logic_vector(10397237,24); manlo <= conv_std_logic_vector(171483537,28); exponent <= conv_std_logic_vector(1823,11); WHEN "1000101100" => manhi <= conv_std_logic_vector(1689739,24); manlo <= conv_std_logic_vector(236540182,28); exponent <= conv_std_logic_vector(1825,11); WHEN "1000101101" => manhi <= conv_std_logic_vector(8321979,24); manlo <= conv_std_logic_vector(80365386,28); exponent <= conv_std_logic_vector(1826,11); WHEN "1000101110" => manhi <= conv_std_logic_vector(279455,24); manlo <= conv_std_logic_vector(167185714,28); exponent <= conv_std_logic_vector(1828,11); WHEN "1000101111" => manhi <= conv_std_logic_vector(6405204,24); manlo <= conv_std_logic_vector(70637708,28); exponent <= conv_std_logic_vector(1829,11); WHEN "1000110000" => manhi <= conv_std_logic_vector(14730959,24); manlo <= conv_std_logic_vector(233674466,28); exponent <= conv_std_logic_vector(1830,11); WHEN "1000110001" => manhi <= conv_std_logic_vector(4634809,24); manlo <= conv_std_logic_vector(128626627,28); exponent <= conv_std_logic_vector(1832,11); WHEN "1000110010" => manhi <= conv_std_logic_vector(12324743,24); manlo <= conv_std_logic_vector(237637056,28); exponent <= conv_std_logic_vector(1833,11); WHEN "1000110011" => manhi <= conv_std_logic_vector(2999616,24); manlo <= conv_std_logic_vector(48899908,28); exponent <= conv_std_logic_vector(1835,11); WHEN "1000110100" => manhi <= conv_std_logic_vector(10102285,24); manlo <= conv_std_logic_vector(207402206,28); exponent <= conv_std_logic_vector(1836,11); WHEN "1000110101" => manhi <= conv_std_logic_vector(1489299,24); manlo <= conv_std_logic_vector(82314533,28); exponent <= conv_std_logic_vector(1838,11); WHEN "1000110110" => manhi <= conv_std_logic_vector(8049552,24); manlo <= conv_std_logic_vector(84197942,28); exponent <= conv_std_logic_vector(1839,11); WHEN "1000110111" => manhi <= conv_std_logic_vector(94322,24); manlo <= conv_std_logic_vector(78275083,28); exponent <= conv_std_logic_vector(1841,11); WHEN "1000111000" => manhi <= conv_std_logic_vector(6153581,24); manlo <= conv_std_logic_vector(262556746,28); exponent <= conv_std_logic_vector(1842,11); WHEN "1000111001" => manhi <= conv_std_logic_vector(14388969,24); manlo <= conv_std_logic_vector(195412276,28); exponent <= conv_std_logic_vector(1843,11); WHEN "1000111010" => manhi <= conv_std_logic_vector(4402403,24); manlo <= conv_std_logic_vector(21925377,28); exponent <= conv_std_logic_vector(1845,11); WHEN "1000111011" => manhi <= conv_std_logic_vector(12008870,24); manlo <= conv_std_logic_vector(225943576,28); exponent <= conv_std_logic_vector(1846,11); WHEN "1000111100" => manhi <= conv_std_logic_vector(2784958,24); manlo <= conv_std_logic_vector(51959162,28); exponent <= conv_std_logic_vector(1848,11); WHEN "1000111101" => manhi <= conv_std_logic_vector(9810535,24); manlo <= conv_std_logic_vector(85297068,28); exponent <= conv_std_logic_vector(1849,11); WHEN "1000111110" => manhi <= conv_std_logic_vector(1291034,24); manlo <= conv_std_logic_vector(85003113,28); exponent <= conv_std_logic_vector(1851,11); WHEN "1000111111" => manhi <= conv_std_logic_vector(7780082,24); manlo <= conv_std_logic_vector(68159752,28); exponent <= conv_std_logic_vector(1852,11); WHEN "1001000000" => manhi <= conv_std_logic_vector(16599612,24); manlo <= conv_std_logic_vector(214703512,28); exponent <= conv_std_logic_vector(1853,11); WHEN "1001000001" => manhi <= conv_std_logic_vector(5904690,24); manlo <= conv_std_logic_vector(215968023,28); exponent <= conv_std_logic_vector(1855,11); WHEN "1001000010" => manhi <= conv_std_logic_vector(14050691,24); manlo <= conv_std_logic_vector(147853227,28); exponent <= conv_std_logic_vector(1856,11); WHEN "1001000011" => manhi <= conv_std_logic_vector(4172519,24); manlo <= conv_std_logic_vector(60716388,28); exponent <= conv_std_logic_vector(1858,11); WHEN "1001000100" => manhi <= conv_std_logic_vector(11696426,24); manlo <= conv_std_logic_vector(77359100,28); exponent <= conv_std_logic_vector(1859,11); WHEN "1001000101" => manhi <= conv_std_logic_vector(2572630,24); manlo <= conv_std_logic_vector(28321055,28); exponent <= conv_std_logic_vector(1861,11); WHEN "1001000110" => manhi <= conv_std_logic_vector(9521951,24); manlo <= conv_std_logic_vector(141206574,28); exponent <= conv_std_logic_vector(1862,11); WHEN "1001000111" => manhi <= conv_std_logic_vector(1094921,24); manlo <= conv_std_logic_vector(79834212,28); exponent <= conv_std_logic_vector(1864,11); WHEN "1001001000" => manhi <= conv_std_logic_vector(7513537,24); manlo <= conv_std_logic_vector(6880382,28); exponent <= conv_std_logic_vector(1865,11); WHEN "1001001001" => manhi <= conv_std_logic_vector(16237340,24); manlo <= conv_std_logic_vector(73707069,28); exponent <= conv_std_logic_vector(1866,11); WHEN "1001001010" => manhi <= conv_std_logic_vector(5658501,24); manlo <= conv_std_logic_vector(26563701,28); exponent <= conv_std_logic_vector(1868,11); WHEN "1001001011" => manhi <= conv_std_logic_vector(13716085,24); manlo <= conv_std_logic_vector(13226359,28); exponent <= conv_std_logic_vector(1869,11); WHEN "1001001100" => manhi <= conv_std_logic_vector(3945130,24); manlo <= conv_std_logic_vector(143073903,28); exponent <= conv_std_logic_vector(1871,11); WHEN "1001001101" => manhi <= conv_std_logic_vector(11387373,24); manlo <= conv_std_logic_vector(3175990,28); exponent <= conv_std_logic_vector(1872,11); WHEN "1001001110" => manhi <= conv_std_logic_vector(2362606,24); manlo <= conv_std_logic_vector(168904878,28); exponent <= conv_std_logic_vector(1874,11); WHEN "1001001111" => manhi <= conv_std_logic_vector(9236500,24); manlo <= conv_std_logic_vector(7105104,28); exponent <= conv_std_logic_vector(1875,11); WHEN "1001010000" => manhi <= conv_std_logic_vector(900936,24); manlo <= conv_std_logic_vector(239272854,28); exponent <= conv_std_logic_vector(1877,11); WHEN "1001010001" => manhi <= conv_std_logic_vector(7249884,24); manlo <= conv_std_logic_vector(236935482,28); exponent <= conv_std_logic_vector(1878,11); WHEN "1001010010" => manhi <= conv_std_logic_vector(15878999,24); manlo <= conv_std_logic_vector(230836932,28); exponent <= conv_std_logic_vector(1879,11); WHEN "1001010011" => manhi <= conv_std_logic_vector(5414983,24); manlo <= conv_std_logic_vector(144840810,28); exponent <= conv_std_logic_vector(1881,11); WHEN "1001010100" => manhi <= conv_std_logic_vector(13385110,24); manlo <= conv_std_logic_vector(99584369,28); exponent <= conv_std_logic_vector(1882,11); WHEN "1001010101" => manhi <= conv_std_logic_vector(3720209,24); manlo <= conv_std_logic_vector(246845719,28); exponent <= conv_std_logic_vector(1884,11); WHEN "1001010110" => manhi <= conv_std_logic_vector(11081674,24); manlo <= conv_std_logic_vector(54674652,28); exponent <= conv_std_logic_vector(1885,11); WHEN "1001010111" => manhi <= conv_std_logic_vector(2154862,24); manlo <= conv_std_logic_vector(201440422,28); exponent <= conv_std_logic_vector(1887,11); WHEN "1001011000" => manhi <= conv_std_logic_vector(8954146,24); manlo <= conv_std_logic_vector(220416825,28); exponent <= conv_std_logic_vector(1888,11); WHEN "1001011001" => manhi <= conv_std_logic_vector(709057,24); manlo <= conv_std_logic_vector(266967657,28); exponent <= conv_std_logic_vector(1890,11); WHEN "1001011010" => manhi <= conv_std_logic_vector(6989094,24); manlo <= conv_std_logic_vector(113654547,28); exponent <= conv_std_logic_vector(1891,11); WHEN "1001011011" => manhi <= conv_std_logic_vector(15524548,24); manlo <= conv_std_logic_vector(235342013,28); exponent <= conv_std_logic_vector(1892,11); WHEN "1001011100" => manhi <= conv_std_logic_vector(5174109,24); manlo <= conv_std_logic_vector(32986511,28); exponent <= conv_std_logic_vector(1894,11); WHEN "1001011101" => manhi <= conv_std_logic_vector(13057728,24); manlo <= conv_std_logic_vector(25787653,28); exponent <= conv_std_logic_vector(1895,11); WHEN "1001011110" => manhi <= conv_std_logic_vector(3497730,24); manlo <= conv_std_logic_vector(160351868,28); exponent <= conv_std_logic_vector(1897,11); WHEN "1001011111" => manhi <= conv_std_logic_vector(10779293,24); manlo <= conv_std_logic_vector(121946709,28); exponent <= conv_std_logic_vector(1898,11); WHEN "1001100000" => manhi <= conv_std_logic_vector(1949373,24); manlo <= conv_std_logic_vector(194974600,28); exponent <= conv_std_logic_vector(1900,11); WHEN "1001100001" => manhi <= conv_std_logic_vector(8674858,24); manlo <= conv_std_logic_vector(75445083,28); exponent <= conv_std_logic_vector(1901,11); WHEN "1001100010" => manhi <= conv_std_logic_vector(519261,24); manlo <= conv_std_logic_vector(202318540,28); exponent <= conv_std_logic_vector(1903,11); WHEN "1001100011" => manhi <= conv_std_logic_vector(6731134,24); manlo <= conv_std_logic_vector(157600610,28); exponent <= conv_std_logic_vector(1904,11); WHEN "1001100100" => manhi <= conv_std_logic_vector(15173945,24); manlo <= conv_std_logic_vector(29256816,28); exponent <= conv_std_logic_vector(1905,11); WHEN "1001100101" => manhi <= conv_std_logic_vector(4935849,24); manlo <= conv_std_logic_vector(42999013,28); exponent <= conv_std_logic_vector(1907,11); WHEN "1001100110" => manhi <= conv_std_logic_vector(12733899,24); manlo <= conv_std_logic_vector(62421287,28); exponent <= conv_std_logic_vector(1908,11); WHEN "1001100111" => manhi <= conv_std_logic_vector(3277666,24); manlo <= conv_std_logic_vector(18399062,28); exponent <= conv_std_logic_vector(1910,11); WHEN "1001101000" => manhi <= conv_std_logic_vector(10480194,24); manlo <= conv_std_logic_vector(201166396,28); exponent <= conv_std_logic_vector(1911,11); WHEN "1001101001" => manhi <= conv_std_logic_vector(1746115,24); manlo <= conv_std_logic_vector(22209480,28); exponent <= conv_std_logic_vector(1913,11); WHEN "1001101010" => manhi <= conv_std_logic_vector(8398601,24); manlo <= conv_std_logic_vector(38216343,28); exponent <= conv_std_logic_vector(1914,11); WHEN "1001101011" => manhi <= conv_std_logic_vector(331525,24); manlo <= conv_std_logic_vector(151310615,28); exponent <= conv_std_logic_vector(1916,11); WHEN "1001101100" => manhi <= conv_std_logic_vector(6475974,24); manlo <= conv_std_logic_vector(174528998,28); exponent <= conv_std_logic_vector(1917,11); WHEN "1001101101" => manhi <= conv_std_logic_vector(14827146,24); manlo <= conv_std_logic_vector(214487191,28); exponent <= conv_std_logic_vector(1918,11); WHEN "1001101110" => manhi <= conv_std_logic_vector(4700175,24); manlo <= conv_std_logic_vector(73593076,28); exponent <= conv_std_logic_vector(1920,11); WHEN "1001101111" => manhi <= conv_std_logic_vector(12413585,24); manlo <= conv_std_logic_vector(56806573,28); exponent <= conv_std_logic_vector(1921,11); WHEN "1001110000" => manhi <= conv_std_logic_vector(3059990,24); manlo <= conv_std_logic_vector(32998071,28); exponent <= conv_std_logic_vector(1923,11); WHEN "1001110001" => manhi <= conv_std_logic_vector(10184342,24); manlo <= conv_std_logic_vector(125003687,28); exponent <= conv_std_logic_vector(1924,11); WHEN "1001110010" => manhi <= conv_std_logic_vector(1545062,24); manlo <= conv_std_logic_vector(164026180,28); exponent <= conv_std_logic_vector(1926,11); WHEN "1001110011" => manhi <= conv_std_logic_vector(8125342,24); manlo <= conv_std_logic_vector(134803968,28); exponent <= conv_std_logic_vector(1927,11); WHEN "1001110100" => manhi <= conv_std_logic_vector(145827,24); manlo <= conv_std_logic_vector(17356019,28); exponent <= conv_std_logic_vector(1929,11); WHEN "1001110101" => manhi <= conv_std_logic_vector(6223584,24); manlo <= conv_std_logic_vector(59711433,28); exponent <= conv_std_logic_vector(1930,11); WHEN "1001110110" => manhi <= conv_std_logic_vector(14484112,24); manlo <= conv_std_logic_vector(172427100,28); exponent <= conv_std_logic_vector(1931,11); WHEN "1001110111" => manhi <= conv_std_logic_vector(4467059,24); manlo <= conv_std_logic_vector(106163660,28); exponent <= conv_std_logic_vector(1933,11); WHEN "1001111000" => manhi <= conv_std_logic_vector(12096747,24); manlo <= conv_std_logic_vector(237074316,28); exponent <= conv_std_logic_vector(1934,11); WHEN "1001111001" => manhi <= conv_std_logic_vector(2844676,24); manlo <= conv_std_logic_vector(224090291,28); exponent <= conv_std_logic_vector(1936,11); WHEN "1001111010" => manhi <= conv_std_logic_vector(9891701,24); manlo <= conv_std_logic_vector(98356275,28); exponent <= conv_std_logic_vector(1937,11); WHEN "1001111011" => manhi <= conv_std_logic_vector(1346192,24); manlo <= conv_std_logic_vector(98098154,28); exponent <= conv_std_logic_vector(1939,11); WHEN "1001111100" => manhi <= conv_std_logic_vector(7855049,24); manlo <= conv_std_logic_vector(218711727,28); exponent <= conv_std_logic_vector(1940,11); WHEN "1001111101" => manhi <= conv_std_logic_vector(16701504,24); manlo <= conv_std_logic_vector(74899902,28); exponent <= conv_std_logic_vector(1941,11); WHEN "1001111110" => manhi <= conv_std_logic_vector(5973933,24); manlo <= conv_std_logic_vector(65399866,28); exponent <= conv_std_logic_vector(1943,11); WHEN "1001111111" => manhi <= conv_std_logic_vector(14144801,24); manlo <= conv_std_logic_vector(210121699,28); exponent <= conv_std_logic_vector(1944,11); WHEN "1010000000" => manhi <= conv_std_logic_vector(4236473,24); manlo <= conv_std_logic_vector(203888522,28); exponent <= conv_std_logic_vector(1946,11); WHEN "1010000001" => manhi <= conv_std_logic_vector(11783349,24); manlo <= conv_std_logic_vector(137203293,28); exponent <= conv_std_logic_vector(1947,11); WHEN "1010000010" => manhi <= conv_std_logic_vector(2631700,24); manlo <= conv_std_logic_vector(150283410,28); exponent <= conv_std_logic_vector(1949,11); WHEN "1010000011" => manhi <= conv_std_logic_vector(9602236,24); manlo <= conv_std_logic_vector(160352104,28); exponent <= conv_std_logic_vector(1950,11); WHEN "1010000100" => manhi <= conv_std_logic_vector(1149480,24); manlo <= conv_std_logic_vector(177173803,28); exponent <= conv_std_logic_vector(1952,11); WHEN "1010000101" => manhi <= conv_std_logic_vector(7587690,24); manlo <= conv_std_logic_vector(238268718,28); exponent <= conv_std_logic_vector(1953,11); WHEN "1010000110" => manhi <= conv_std_logic_vector(16338125,24); manlo <= conv_std_logic_vector(220749839,28); exponent <= conv_std_logic_vector(1954,11); WHEN "1010000111" => manhi <= conv_std_logic_vector(5726991,24); manlo <= conv_std_logic_vector(262994505,28); exponent <= conv_std_logic_vector(1956,11); WHEN "1010001000" => manhi <= conv_std_logic_vector(13809173,24); manlo <= conv_std_logic_vector(216783842,28); exponent <= conv_std_logic_vector(1957,11); WHEN "1010001001" => manhi <= conv_std_logic_vector(4008390,24); manlo <= conv_std_logic_vector(242405077,28); exponent <= conv_std_logic_vector(1959,11); WHEN "1010001010" => manhi <= conv_std_logic_vector(11473352,24); manlo <= conv_std_logic_vector(206426515,28); exponent <= conv_std_logic_vector(1960,11); WHEN "1010001011" => manhi <= conv_std_logic_vector(2421035,24); manlo <= conv_std_logic_vector(250208807,28); exponent <= conv_std_logic_vector(1962,11); WHEN "1010001100" => manhi <= conv_std_logic_vector(9315913,24); manlo <= conv_std_logic_vector(183235034,28); exponent <= conv_std_logic_vector(1963,11); WHEN "1010001101" => manhi <= conv_std_logic_vector(954904,24); manlo <= conv_std_logic_vector(17706469,28); exponent <= conv_std_logic_vector(1965,11); WHEN "1010001110" => manhi <= conv_std_logic_vector(7323233,24); manlo <= conv_std_logic_vector(235600136,28); exponent <= conv_std_logic_vector(1966,11); WHEN "1010001111" => manhi <= conv_std_logic_vector(15978691,24); manlo <= conv_std_logic_vector(128873524,28); exponent <= conv_std_logic_vector(1967,11); WHEN "1010010000" => manhi <= conv_std_logic_vector(5482731,24); manlo <= conv_std_logic_vector(5222268,28); exponent <= conv_std_logic_vector(1969,11); WHEN "1010010001" => manhi <= conv_std_logic_vector(13477188,24); manlo <= conv_std_logic_vector(199372940,28); exponent <= conv_std_logic_vector(1970,11); WHEN "1010010010" => manhi <= conv_std_logic_vector(3782783,24); manlo <= conv_std_logic_vector(177367827,28); exponent <= conv_std_logic_vector(1972,11); WHEN "1010010011" => manhi <= conv_std_logic_vector(11166720,24); manlo <= conv_std_logic_vector(197425116,28); exponent <= conv_std_logic_vector(1973,11); WHEN "1010010100" => manhi <= conv_std_logic_vector(2212657,24); manlo <= conv_std_logic_vector(231097832,28); exponent <= conv_std_logic_vector(1975,11); WHEN "1010010101" => manhi <= conv_std_logic_vector(9032698,24); manlo <= conv_std_logic_vector(139698050,28); exponent <= conv_std_logic_vector(1976,11); WHEN "1010010110" => manhi <= conv_std_logic_vector(762439,24); manlo <= conv_std_logic_vector(109718127,28); exponent <= conv_std_logic_vector(1978,11); WHEN "1010010111" => manhi <= conv_std_logic_vector(7061647,24); manlo <= conv_std_logic_vector(77173752,28); exponent <= conv_std_logic_vector(1979,11); WHEN "1010011000" => manhi <= conv_std_logic_vector(15623158,24); manlo <= conv_std_logic_vector(118851961,28); exponent <= conv_std_logic_vector(1980,11); WHEN "1010011001" => manhi <= conv_std_logic_vector(5241121,24); manlo <= conv_std_logic_vector(72680114,28); exponent <= conv_std_logic_vector(1982,11); WHEN "1010011010" => manhi <= conv_std_logic_vector(13148807,24); manlo <= conv_std_logic_vector(12881486,28); exponent <= conv_std_logic_vector(1983,11); WHEN "1010011011" => manhi <= conv_std_logic_vector(3559625,24); manlo <= conv_std_logic_vector(43579850,28); exponent <= conv_std_logic_vector(1985,11); WHEN "1010011100" => manhi <= conv_std_logic_vector(10863416,24); manlo <= conv_std_logic_vector(238889758,28); exponent <= conv_std_logic_vector(1986,11); WHEN "1010011101" => manhi <= conv_std_logic_vector(2006541,24); manlo <= conv_std_logic_vector(141721451,28); exponent <= conv_std_logic_vector(1988,11); WHEN "1010011110" => manhi <= conv_std_logic_vector(8752557,24); manlo <= conv_std_logic_vector(101792997,28); exponent <= conv_std_logic_vector(1989,11); WHEN "1010011111" => manhi <= conv_std_logic_vector(572063,24); manlo <= conv_std_logic_vector(205445723,28); exponent <= conv_std_logic_vector(1991,11); WHEN "1010100000" => manhi <= conv_std_logic_vector(6802899,24); manlo <= conv_std_logic_vector(258099270,28); exponent <= conv_std_logic_vector(1992,11); WHEN "1010100001" => manhi <= conv_std_logic_vector(15271484,24); manlo <= conv_std_logic_vector(98124990,28); exponent <= conv_std_logic_vector(1993,11); WHEN "1010100010" => manhi <= conv_std_logic_vector(5002133,24); manlo <= conv_std_logic_vector(256985826,28); exponent <= conv_std_logic_vector(1995,11); WHEN "1010100011" => manhi <= conv_std_logic_vector(12823989,24); manlo <= conv_std_logic_vector(164377270,28); exponent <= conv_std_logic_vector(1996,11); WHEN "1010100100" => manhi <= conv_std_logic_vector(3338888,24); manlo <= conv_std_logic_vector(222569178,28); exponent <= conv_std_logic_vector(1998,11); WHEN "1010100101" => manhi <= conv_std_logic_vector(10563405,24); manlo <= conv_std_logic_vector(29046646,28); exponent <= conv_std_logic_vector(1999,11); WHEN "1010100110" => manhi <= conv_std_logic_vector(1802662,24); manlo <= conv_std_logic_vector(103161316,28); exponent <= conv_std_logic_vector(2001,11); WHEN "1010100111" => manhi <= conv_std_logic_vector(8475456,24); manlo <= conv_std_logic_vector(239852126,28); exponent <= conv_std_logic_vector(2002,11); WHEN "1010101000" => manhi <= conv_std_logic_vector(383754,24); manlo <= conv_std_logic_vector(123914668,28); exponent <= conv_std_logic_vector(2004,11); WHEN "1010101001" => manhi <= conv_std_logic_vector(6546961,24); manlo <= conv_std_logic_vector(22084044,28); exponent <= conv_std_logic_vector(2005,11); WHEN "1010101010" => manhi <= conv_std_logic_vector(14923627,24); manlo <= conv_std_logic_vector(97508377,28); exponent <= conv_std_logic_vector(2006,11); WHEN "1010101011" => manhi <= conv_std_logic_vector(4765740,24); manlo <= conv_std_logic_vector(165164368,28); exponent <= conv_std_logic_vector(2008,11); WHEN "1010101100" => manhi <= conv_std_logic_vector(12502697,24); manlo <= conv_std_logic_vector(201140216,28); exponent <= conv_std_logic_vector(2009,11); WHEN "1010101101" => manhi <= conv_std_logic_vector(3120548,24); manlo <= conv_std_logic_vector(99561759,28); exponent <= conv_std_logic_vector(2011,11); WHEN "1010101110" => manhi <= conv_std_logic_vector(10266649,24); manlo <= conv_std_logic_vector(176679877,28); exponent <= conv_std_logic_vector(2012,11); WHEN "1010101111" => manhi <= conv_std_logic_vector(1600996,24); manlo <= conv_std_logic_vector(39589446,28); exponent <= conv_std_logic_vector(2014,11); WHEN "1010110000" => manhi <= conv_std_logic_vector(8201364,24); manlo <= conv_std_logic_vector(16114999,28); exponent <= conv_std_logic_vector(2015,11); WHEN "1010110001" => manhi <= conv_std_logic_vector(197489,24); manlo <= conv_std_logic_vector(18649371,28); exponent <= conv_std_logic_vector(2017,11); WHEN "1010110010" => manhi <= conv_std_logic_vector(6293800,24); manlo <= conv_std_logic_vector(44802372,28); exponent <= conv_std_logic_vector(2018,11); WHEN "1010110011" => manhi <= conv_std_logic_vector(14579546,24); manlo <= conv_std_logic_vector(1419236,28); exponent <= conv_std_logic_vector(2019,11); WHEN "1010110100" => manhi <= conv_std_logic_vector(4531913,24); manlo <= conv_std_logic_vector(24044223,28); exponent <= conv_std_logic_vector(2021,11); WHEN "1010110101" => manhi <= conv_std_logic_vector(12184893,24); manlo <= conv_std_logic_vector(51602800,28); exponent <= conv_std_logic_vector(2022,11); WHEN "1010110110" => manhi <= conv_std_logic_vector(2904577,24); manlo <= conv_std_logic_vector(210124577,28); exponent <= conv_std_logic_vector(2024,11); WHEN "1010110111" => manhi <= conv_std_logic_vector(9973115,24); manlo <= conv_std_logic_vector(52505388,28); exponent <= conv_std_logic_vector(2025,11); WHEN "1010111000" => manhi <= conv_std_logic_vector(1401518,24); manlo <= conv_std_logic_vector(214362802,28); exponent <= conv_std_logic_vector(2027,11); WHEN "1010111001" => manhi <= conv_std_logic_vector(7930246,24); manlo <= conv_std_logic_vector(62721516,28); exponent <= conv_std_logic_vector(2028,11); WHEN "1010111010" => manhi <= conv_std_logic_vector(13245,24); manlo <= conv_std_logic_vector(108520727,28); exponent <= conv_std_logic_vector(2030,11); WHEN "1010111011" => manhi <= conv_std_logic_vector(6043387,24); manlo <= conv_std_logic_vector(17001813,28); exponent <= conv_std_logic_vector(2031,11); WHEN "1010111100" => manhi <= conv_std_logic_vector(14239199,24); manlo <= conv_std_logic_vector(83422350,28); exponent <= conv_std_logic_vector(2032,11); WHEN "1010111101" => manhi <= conv_std_logic_vector(4300623,24); manlo <= conv_std_logic_vector(142486326,28); exponent <= conv_std_logic_vector(2034,11); WHEN "1010111110" => manhi <= conv_std_logic_vector(11870538,24); manlo <= conv_std_logic_vector(24126621,28); exponent <= conv_std_logic_vector(2035,11); WHEN "1010111111" => manhi <= conv_std_logic_vector(2690951,24); manlo <= conv_std_logic_vector(91850592,28); exponent <= conv_std_logic_vector(2037,11); WHEN "1011000000" => manhi <= conv_std_logic_vector(9682766,24); manlo <= conv_std_logic_vector(203960059,28); exponent <= conv_std_logic_vector(2038,11); WHEN "1011000001" => manhi <= conv_std_logic_vector(1204206,24); manlo <= conv_std_logic_vector(155513539,28); exponent <= conv_std_logic_vector(2040,11); WHEN "1011000010" => manhi <= conv_std_logic_vector(7662071,24); manlo <= conv_std_logic_vector(33184566,28); exponent <= conv_std_logic_vector(2041,11); WHEN "1011000011" => manhi <= conv_std_logic_vector(16439219,24); manlo <= conv_std_logic_vector(11896414,28); exponent <= conv_std_logic_vector(2042,11); WHEN "1011000100" => manhi <= conv_std_logic_vector(5795691,24); manlo <= conv_std_logic_vector(254151921,28); exponent <= conv_std_logic_vector(2044,11); WHEN "1011000101" => manhi <= conv_std_logic_vector(13902546,24); manlo <= conv_std_logic_vector(199613595,28); exponent <= conv_std_logic_vector(2045,11); WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_explutpos IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_explutpos; ARCHITECTURE rtl OF dp_explutpos IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(1023,11); WHEN "0000000001" => manhi <= conv_std_logic_vector(6025384,24); manlo <= conv_std_logic_vector(185882474,28); exponent <= conv_std_logic_vector(1024,11); WHEN "0000000010" => manhi <= conv_std_logic_vector(14214731,24); manlo <= conv_std_logic_vector(148168110,28); exponent <= conv_std_logic_vector(1025,11); WHEN "0000000011" => manhi <= conv_std_logic_vector(4283995,24); manlo <= conv_std_logic_vector(258978054,28); exponent <= conv_std_logic_vector(1027,11); WHEN "0000000100" => manhi <= conv_std_logic_vector(11847938,24); manlo <= conv_std_logic_vector(237451864,28); exponent <= conv_std_logic_vector(1028,11); WHEN "0000000101" => manhi <= conv_std_logic_vector(2675593,24); manlo <= conv_std_logic_vector(158348175,28); exponent <= conv_std_logic_vector(1030,11); WHEN "0000000110" => manhi <= conv_std_logic_vector(9661893,24); manlo <= conv_std_logic_vector(110149775,28); exponent <= conv_std_logic_vector(1031,11); WHEN "0000000111" => manhi <= conv_std_logic_vector(1190021,24); manlo <= conv_std_logic_vector(179232170,28); exponent <= conv_std_logic_vector(1033,11); WHEN "0000001000" => manhi <= conv_std_logic_vector(7642791,24); manlo <= conv_std_logic_vector(222760046,28); exponent <= conv_std_logic_vector(1034,11); WHEN "0000001001" => manhi <= conv_std_logic_vector(16413015,24); manlo <= conv_std_logic_vector(205983618,28); exponent <= conv_std_logic_vector(1035,11); WHEN "0000001010" => manhi <= conv_std_logic_vector(5777884,24); manlo <= conv_std_logic_vector(261424480,28); exponent <= conv_std_logic_vector(1037,11); WHEN "0000001011" => manhi <= conv_std_logic_vector(13878344,24); manlo <= conv_std_logic_vector(149835647,28); exponent <= conv_std_logic_vector(1038,11); WHEN "0000001100" => manhi <= conv_std_logic_vector(4055397,24); manlo <= conv_std_logic_vector(80968858,28); exponent <= conv_std_logic_vector(1040,11); WHEN "0000001101" => manhi <= conv_std_logic_vector(11537241,24); manlo <= conv_std_logic_vector(23775573,28); exponent <= conv_std_logic_vector(1041,11); WHEN "0000001110" => manhi <= conv_std_logic_vector(2464452,24); manlo <= conv_std_logic_vector(146736599,28); exponent <= conv_std_logic_vector(1043,11); WHEN "0000001111" => manhi <= conv_std_logic_vector(9374922,24); manlo <= conv_std_logic_vector(263006855,28); exponent <= conv_std_logic_vector(1044,11); WHEN "0000010000" => manhi <= conv_std_logic_vector(995005,24); manlo <= conv_std_logic_vector(11010080,28); exponent <= conv_std_logic_vector(1046,11); WHEN "0000010001" => manhi <= conv_std_logic_vector(7377736,24); manlo <= conv_std_logic_vector(202286329,28); exponent <= conv_std_logic_vector(1047,11); WHEN "0000010010" => manhi <= conv_std_logic_vector(16052768,24); manlo <= conv_std_logic_vector(152649917,28); exponent <= conv_std_logic_vector(1048,11); WHEN "0000010011" => manhi <= conv_std_logic_vector(5533071,24); manlo <= conv_std_logic_vector(166536930,28); exponent <= conv_std_logic_vector(1050,11); WHEN "0000010100" => manhi <= conv_std_logic_vector(13545608,24); manlo <= conv_std_logic_vector(191424516,28); exponent <= conv_std_logic_vector(1051,11); WHEN "0000010101" => manhi <= conv_std_logic_vector(3829279,24); manlo <= conv_std_logic_vector(228519165,28); exponent <= conv_std_logic_vector(1053,11); WHEN "0000010110" => manhi <= conv_std_logic_vector(11229915,24); manlo <= conv_std_logic_vector(163853824,28); exponent <= conv_std_logic_vector(1054,11); WHEN "0000010111" => manhi <= conv_std_logic_vector(2255603,24); manlo <= conv_std_logic_vector(61996481,28); exponent <= conv_std_logic_vector(1056,11); WHEN "0000011000" => manhi <= conv_std_logic_vector(9091067,24); manlo <= conv_std_logic_vector(88563639,28); exponent <= conv_std_logic_vector(1057,11); WHEN "0000011001" => manhi <= conv_std_logic_vector(802105,24); manlo <= conv_std_logic_vector(34169545,28); exponent <= conv_std_logic_vector(1059,11); WHEN "0000011010" => manhi <= conv_std_logic_vector(7115558,24); manlo <= conv_std_logic_vector(157969244,28); exponent <= conv_std_logic_vector(1060,11); WHEN "0000011011" => manhi <= conv_std_logic_vector(15696431,24); manlo <= conv_std_logic_vector(133591837,28); exponent <= conv_std_logic_vector(1061,11); WHEN "0000011100" => manhi <= conv_std_logic_vector(5290915,24); manlo <= conv_std_logic_vector(127285146,28); exponent <= conv_std_logic_vector(1063,11); WHEN "0000011101" => manhi <= conv_std_logic_vector(13216484,24); manlo <= conv_std_logic_vector(103923798,28); exponent <= conv_std_logic_vector(1064,11); WHEN "0000011110" => manhi <= conv_std_logic_vector(3605616,24); manlo <= conv_std_logic_vector(183249133,28); exponent <= conv_std_logic_vector(1066,11); WHEN "0000011111" => manhi <= conv_std_logic_vector(10925925,24); manlo <= conv_std_logic_vector(227336045,28); exponent <= conv_std_logic_vector(1067,11); WHEN "0000100000" => manhi <= conv_std_logic_vector(2049020,24); manlo <= conv_std_logic_vector(206267948,28); exponent <= conv_std_logic_vector(1069,11); WHEN "0000100001" => manhi <= conv_std_logic_vector(8810292,24); manlo <= conv_std_logic_vector(175265666,28); exponent <= conv_std_logic_vector(1070,11); WHEN "0000100010" => manhi <= conv_std_logic_vector(611298,24); manlo <= conv_std_logic_vector(255467255,28); exponent <= conv_std_logic_vector(1072,11); WHEN "0000100011" => manhi <= conv_std_logic_vector(6856226,24); manlo <= conv_std_logic_vector(29134171,28); exponent <= conv_std_logic_vector(1073,11); WHEN "0000100100" => manhi <= conv_std_logic_vector(15343962,24); manlo <= conv_std_logic_vector(30543222,28); exponent <= conv_std_logic_vector(1074,11); WHEN "0000100101" => manhi <= conv_std_logic_vector(5051387,24); manlo <= conv_std_logic_vector(186253338,28); exponent <= conv_std_logic_vector(1076,11); WHEN "0000100110" => manhi <= conv_std_logic_vector(12890932,24); manlo <= conv_std_logic_vector(102222951,28); exponent <= conv_std_logic_vector(1077,11); WHEN "0000100111" => manhi <= conv_std_logic_vector(3384381,24); manlo <= conv_std_logic_vector(42116377,28); exponent <= conv_std_logic_vector(1079,11); WHEN "0000101000" => manhi <= conv_std_logic_vector(10625235,24); manlo <= conv_std_logic_vector(158954218,28); exponent <= conv_std_logic_vector(1080,11); WHEN "0000101001" => manhi <= conv_std_logic_vector(1844680,24); manlo <= conv_std_logic_vector(148858978,28); exponent <= conv_std_logic_vector(1082,11); WHEN "0000101010" => manhi <= conv_std_logic_vector(8532565,24); manlo <= conv_std_logic_vector(136319321,28); exponent <= conv_std_logic_vector(1083,11); WHEN "0000101011" => manhi <= conv_std_logic_vector(422563,24); manlo <= conv_std_logic_vector(211728497,28); exponent <= conv_std_logic_vector(1085,11); WHEN "0000101100" => manhi <= conv_std_logic_vector(6599708,24); manlo <= conv_std_logic_vector(114522162,28); exponent <= conv_std_logic_vector(1086,11); WHEN "0000101101" => manhi <= conv_std_logic_vector(14995318,24); manlo <= conv_std_logic_vector(117328318,28); exponent <= conv_std_logic_vector(1087,11); WHEN "0000101110" => manhi <= conv_std_logic_vector(4814459,24); manlo <= conv_std_logic_vector(201622499,28); exponent <= conv_std_logic_vector(1089,11); WHEN "0000101111" => manhi <= conv_std_logic_vector(12568913,24); manlo <= conv_std_logic_vector(246987638,28); exponent <= conv_std_logic_vector(1090,11); WHEN "0000110000" => manhi <= conv_std_logic_vector(3165546,24); manlo <= conv_std_logic_vector(248128843,28); exponent <= conv_std_logic_vector(1092,11); WHEN "0000110001" => manhi <= conv_std_logic_vector(10327809,24); manlo <= conv_std_logic_vector(8929872,28); exponent <= conv_std_logic_vector(1093,11); WHEN "0000110010" => manhi <= conv_std_logic_vector(1642558,24); manlo <= conv_std_logic_vector(67636037,28); exponent <= conv_std_logic_vector(1095,11); WHEN "0000110011" => manhi <= conv_std_logic_vector(8257852,24); manlo <= conv_std_logic_vector(219235425,28); exponent <= conv_std_logic_vector(1096,11); WHEN "0000110100" => manhi <= conv_std_logic_vector(235877,24); manlo <= conv_std_logic_vector(42862412,28); exponent <= conv_std_logic_vector(1098,11); WHEN "0000110101" => manhi <= conv_std_logic_vector(6345974,24); manlo <= conv_std_logic_vector(265996080,28); exponent <= conv_std_logic_vector(1099,11); WHEN "0000110110" => manhi <= conv_std_logic_vector(14650458,24); manlo <= conv_std_logic_vector(253213243,28); exponent <= conv_std_logic_vector(1100,11); WHEN "0000110111" => manhi <= conv_std_logic_vector(4580103,24); manlo <= conv_std_logic_vector(114693785,28); exponent <= conv_std_logic_vector(1102,11); WHEN "0000111000" => manhi <= conv_std_logic_vector(12250390,24); manlo <= conv_std_logic_vector(174984615,28); exponent <= conv_std_logic_vector(1103,11); WHEN "0000111001" => manhi <= conv_std_logic_vector(2949087,24); manlo <= conv_std_logic_vector(247325089,28); exponent <= conv_std_logic_vector(1105,11); WHEN "0000111010" => manhi <= conv_std_logic_vector(10033610,24); manlo <= conv_std_logic_vector(200264553,28); exponent <= conv_std_logic_vector(1106,11); WHEN "0000111011" => manhi <= conv_std_logic_vector(1442629,24); manlo <= conv_std_logic_vector(211375075,28); exponent <= conv_std_logic_vector(1108,11); WHEN "0000111100" => manhi <= conv_std_logic_vector(7986121,24); manlo <= conv_std_logic_vector(231029862,28); exponent <= conv_std_logic_vector(1109,11); WHEN "0000111101" => manhi <= conv_std_logic_vector(51216,24); manlo <= conv_std_logic_vector(222707863,28); exponent <= conv_std_logic_vector(1111,11); WHEN "0000111110" => manhi <= conv_std_logic_vector(6094995,24); manlo <= conv_std_logic_vector(155999272,28); exponent <= conv_std_logic_vector(1112,11); WHEN "0000111111" => manhi <= conv_std_logic_vector(14309342,24); manlo <= conv_std_logic_vector(150013864,28); exponent <= conv_std_logic_vector(1113,11); WHEN "0001000000" => manhi <= conv_std_logic_vector(4348290,24); manlo <= conv_std_logic_vector(217421773,28); exponent <= conv_std_logic_vector(1115,11); WHEN "0001000001" => manhi <= conv_std_logic_vector(11935324,24); manlo <= conv_std_logic_vector(171597361,28); exponent <= conv_std_logic_vector(1116,11); WHEN "0001000010" => manhi <= conv_std_logic_vector(2734978,24); manlo <= conv_std_logic_vector(98553735,28); exponent <= conv_std_logic_vector(1118,11); WHEN "0001000011" => manhi <= conv_std_logic_vector(9742605,24); manlo <= conv_std_logic_vector(185429986,28); exponent <= conv_std_logic_vector(1119,11); WHEN "0001000100" => manhi <= conv_std_logic_vector(1244871,24); manlo <= conv_std_logic_vector(93685501,28); exponent <= conv_std_logic_vector(1121,11); WHEN "0001000101" => manhi <= conv_std_logic_vector(7717340,24); manlo <= conv_std_logic_vector(74048432,28); exponent <= conv_std_logic_vector(1122,11); WHEN "0001000110" => manhi <= conv_std_logic_vector(16514337,24); manlo <= conv_std_logic_vector(163855108,28); exponent <= conv_std_logic_vector(1123,11); WHEN "0001000111" => manhi <= conv_std_logic_vector(5846740,24); manlo <= conv_std_logic_vector(81895750,28); exponent <= conv_std_logic_vector(1125,11); WHEN "0001001000" => manhi <= conv_std_logic_vector(13971928,24); manlo <= conv_std_logic_vector(176088988,28); exponent <= conv_std_logic_vector(1126,11); WHEN "0001001001" => manhi <= conv_std_logic_vector(4118994,24); manlo <= conv_std_logic_vector(77780251,28); exponent <= conv_std_logic_vector(1128,11); WHEN "0001001010" => manhi <= conv_std_logic_vector(11623678,24); manlo <= conv_std_logic_vector(95871356,28); exponent <= conv_std_logic_vector(1129,11); WHEN "0001001011" => manhi <= conv_std_logic_vector(2523192,24); manlo <= conv_std_logic_vector(204213760,28); exponent <= conv_std_logic_vector(1131,11); WHEN "0001001100" => manhi <= conv_std_logic_vector(9454759,24); manlo <= conv_std_logic_vector(55860552,28); exponent <= conv_std_logic_vector(1132,11); WHEN "0001001101" => manhi <= conv_std_logic_vector(1049259,24); manlo <= conv_std_logic_vector(102861624,28); exponent <= conv_std_logic_vector(1134,11); WHEN "0001001110" => manhi <= conv_std_logic_vector(7451476,24); manlo <= conv_std_logic_vector(13367584,28); exponent <= conv_std_logic_vector(1135,11); WHEN "0001001111" => manhi <= conv_std_logic_vector(16152990,24); manlo <= conv_std_logic_vector(178012490,28); exponent <= conv_std_logic_vector(1136,11); WHEN "0001010000" => manhi <= conv_std_logic_vector(5601179,24); manlo <= conv_std_logic_vector(159708139,28); exponent <= conv_std_logic_vector(1138,11); WHEN "0001010001" => manhi <= conv_std_logic_vector(13638177,24); manlo <= conv_std_logic_vector(12864164,28); exponent <= conv_std_logic_vector(1139,11); WHEN "0001010010" => manhi <= conv_std_logic_vector(3892186,24); manlo <= conv_std_logic_vector(149492240,28); exponent <= conv_std_logic_vector(1141,11); WHEN "0001010011" => manhi <= conv_std_logic_vector(11315414,24); manlo <= conv_std_logic_vector(184620728,28); exponent <= conv_std_logic_vector(1142,11); WHEN "0001010100" => manhi <= conv_std_logic_vector(2313705,24); manlo <= conv_std_logic_vector(235697385,28); exponent <= conv_std_logic_vector(1144,11); WHEN "0001010101" => manhi <= conv_std_logic_vector(9170037,24); manlo <= conv_std_logic_vector(3974263,28); exponent <= conv_std_logic_vector(1145,11); WHEN "0001010110" => manhi <= conv_std_logic_vector(855770,24); manlo <= conv_std_logic_vector(158952336,28); exponent <= conv_std_logic_vector(1147,11); WHEN "0001010111" => manhi <= conv_std_logic_vector(7188497,24); manlo <= conv_std_logic_vector(138900038,28); exponent <= conv_std_logic_vector(1148,11); WHEN "0001011000" => manhi <= conv_std_logic_vector(15795565,24); manlo <= conv_std_logic_vector(209449517,28); exponent <= conv_std_logic_vector(1149,11); WHEN "0001011001" => manhi <= conv_std_logic_vector(5358284,24); manlo <= conv_std_logic_vector(54736896,28); exponent <= conv_std_logic_vector(1151,11); WHEN "0001011010" => manhi <= conv_std_logic_vector(13308047,24); manlo <= conv_std_logic_vector(264159588,28); exponent <= conv_std_logic_vector(1152,11); WHEN "0001011011" => manhi <= conv_std_logic_vector(3667840,24); manlo <= conv_std_logic_vector(160544132,28); exponent <= conv_std_logic_vector(1154,11); WHEN "0001011100" => manhi <= conv_std_logic_vector(11010496,24); manlo <= conv_std_logic_vector(245935181,28); exponent <= conv_std_logic_vector(1155,11); WHEN "0001011101" => manhi <= conv_std_logic_vector(2106492,24); manlo <= conv_std_logic_vector(206325441,28); exponent <= conv_std_logic_vector(1157,11); WHEN "0001011110" => manhi <= conv_std_logic_vector(8888405,24); manlo <= conv_std_logic_vector(53641237,28); exponent <= conv_std_logic_vector(1158,11); WHEN "0001011111" => manhi <= conv_std_logic_vector(664381,24); manlo <= conv_std_logic_vector(249887163,28); exponent <= conv_std_logic_vector(1160,11); WHEN "0001100000" => manhi <= conv_std_logic_vector(6928373,24); manlo <= conv_std_logic_vector(95946938,28); exponent <= conv_std_logic_vector(1161,11); WHEN "0001100001" => manhi <= conv_std_logic_vector(15442020,24); manlo <= conv_std_logic_vector(105121290,28); exponent <= conv_std_logic_vector(1162,11); WHEN "0001100010" => manhi <= conv_std_logic_vector(5118025,24); manlo <= conv_std_logic_vector(54367076,28); exponent <= conv_std_logic_vector(1164,11); WHEN "0001100011" => manhi <= conv_std_logic_vector(12981502,24); manlo <= conv_std_logic_vector(39000129,28); exponent <= conv_std_logic_vector(1165,11); WHEN "0001100100" => manhi <= conv_std_logic_vector(3445929,24); manlo <= conv_std_logic_vector(186063861,28); exponent <= conv_std_logic_vector(1167,11); WHEN "0001100101" => manhi <= conv_std_logic_vector(10708888,24); manlo <= conv_std_logic_vector(194877084,28); exponent <= conv_std_logic_vector(1168,11); WHEN "0001100110" => manhi <= conv_std_logic_vector(1901528,24); manlo <= conv_std_logic_vector(202114223,28); exponent <= conv_std_logic_vector(1170,11); WHEN "0001100111" => manhi <= conv_std_logic_vector(8609830,24); manlo <= conv_std_logic_vector(59099508,28); exponent <= conv_std_logic_vector(1171,11); WHEN "0001101000" => manhi <= conv_std_logic_vector(475070,24); manlo <= conv_std_logic_vector(162304029,28); exponent <= conv_std_logic_vector(1173,11); WHEN "0001101001" => manhi <= conv_std_logic_vector(6671072,24); manlo <= conv_std_logic_vector(157938310,28); exponent <= conv_std_logic_vector(1174,11); WHEN "0001101010" => manhi <= conv_std_logic_vector(15092312,24); manlo <= conv_std_logic_vector(104450792,28); exponent <= conv_std_logic_vector(1175,11); WHEN "0001101011" => manhi <= conv_std_logic_vector(4880373,24); manlo <= conv_std_logic_vector(261837049,28); exponent <= conv_std_logic_vector(1177,11); WHEN "0001101100" => manhi <= conv_std_logic_vector(12658500,24); manlo <= conv_std_logic_vector(171583716,28); exponent <= conv_std_logic_vector(1178,11); WHEN "0001101101" => manhi <= conv_std_logic_vector(3226427,24); manlo <= conv_std_logic_vector(110595717,28); exponent <= conv_std_logic_vector(1180,11); WHEN "0001101110" => manhi <= conv_std_logic_vector(10410554,24); manlo <= conv_std_logic_vector(52320382,28); exponent <= conv_std_logic_vector(1181,11); WHEN "0001101111" => manhi <= conv_std_logic_vector(1698789,24); manlo <= conv_std_logic_vector(112550995,28); exponent <= conv_std_logic_vector(1183,11); WHEN "0001110000" => manhi <= conv_std_logic_vector(8334278,24); manlo <= conv_std_logic_vector(240753534,28); exponent <= conv_std_logic_vector(1184,11); WHEN "0001110001" => manhi <= conv_std_logic_vector(287814,24); manlo <= conv_std_logic_vector(17691391,28); exponent <= conv_std_logic_vector(1186,11); WHEN "0001110010" => manhi <= conv_std_logic_vector(6416564,24); manlo <= conv_std_logic_vector(151700710,28); exponent <= conv_std_logic_vector(1187,11); WHEN "0001110011" => manhi <= conv_std_logic_vector(14746400,24); manlo <= conv_std_logic_vector(32676275,28); exponent <= conv_std_logic_vector(1188,11); WHEN "0001110100" => manhi <= conv_std_logic_vector(4645302,24); manlo <= conv_std_logic_vector(58452725,28); exponent <= conv_std_logic_vector(1190,11); WHEN "0001110101" => manhi <= conv_std_logic_vector(12339004,24); manlo <= conv_std_logic_vector(267247876,28); exponent <= conv_std_logic_vector(1191,11); WHEN "0001110110" => manhi <= conv_std_logic_vector(3009307,24); manlo <= conv_std_logic_vector(164126253,28); exponent <= conv_std_logic_vector(1193,11); WHEN "0001110111" => manhi <= conv_std_logic_vector(10115457,24); manlo <= conv_std_logic_vector(212237584,28); exponent <= conv_std_logic_vector(1194,11); WHEN "0001111000" => manhi <= conv_std_logic_vector(1498250,24); manlo <= conv_std_logic_vector(166684427,28); exponent <= conv_std_logic_vector(1196,11); WHEN "0001111001" => manhi <= conv_std_logic_vector(8061718,24); manlo <= conv_std_logic_vector(110371593,28); exponent <= conv_std_logic_vector(1197,11); WHEN "0001111010" => manhi <= conv_std_logic_vector(102590,24); manlo <= conv_std_logic_vector(3231911,28); exponent <= conv_std_logic_vector(1199,11); WHEN "0001111011" => manhi <= conv_std_logic_vector(6164818,24); manlo <= conv_std_logic_vector(261783833,28); exponent <= conv_std_logic_vector(1200,11); WHEN "0001111100" => manhi <= conv_std_logic_vector(14404242,24); manlo <= conv_std_logic_vector(104825991,28); exponent <= conv_std_logic_vector(1201,11); WHEN "0001111101" => manhi <= conv_std_logic_vector(4412781,24); manlo <= conv_std_logic_vector(250166254,28); exponent <= conv_std_logic_vector(1203,11); WHEN "0001111110" => manhi <= conv_std_logic_vector(12022977,24); manlo <= conv_std_logic_vector(43417082,28); exponent <= conv_std_logic_vector(1204,11); WHEN "0001111111" => manhi <= conv_std_logic_vector(2794544,24); manlo <= conv_std_logic_vector(115942082,28); exponent <= conv_std_logic_vector(1206,11); WHEN "0010000000" => manhi <= conv_std_logic_vector(9823564,24); manlo <= conv_std_logic_vector(98386456,28); exponent <= conv_std_logic_vector(1207,11); WHEN "0010000001" => manhi <= conv_std_logic_vector(1299888,24); manlo <= conv_std_logic_vector(127046227,28); exponent <= conv_std_logic_vector(1209,11); WHEN "0010000010" => manhi <= conv_std_logic_vector(7792116,24); manlo <= conv_std_logic_vector(80649262,28); exponent <= conv_std_logic_vector(1210,11); WHEN "0010000011" => manhi <= conv_std_logic_vector(16615968,24); manlo <= conv_std_logic_vector(205307910,28); exponent <= conv_std_logic_vector(1211,11); WHEN "0010000100" => manhi <= conv_std_logic_vector(5915805,24); manlo <= conv_std_logic_vector(224185017,28); exponent <= conv_std_logic_vector(1213,11); WHEN "0010000101" => manhi <= conv_std_logic_vector(14065798,24); manlo <= conv_std_logic_vector(119094636,28); exponent <= conv_std_logic_vector(1214,11); WHEN "0010000110" => manhi <= conv_std_logic_vector(4182785,24); manlo <= conv_std_logic_vector(113890892,28); exponent <= conv_std_logic_vector(1216,11); WHEN "0010000111" => manhi <= conv_std_logic_vector(11710379,24); manlo <= conv_std_logic_vector(133692518,28); exponent <= conv_std_logic_vector(1217,11); WHEN "0010001000" => manhi <= conv_std_logic_vector(2582112,24); manlo <= conv_std_logic_vector(79109485,28); exponent <= conv_std_logic_vector(1219,11); WHEN "0010001001" => manhi <= conv_std_logic_vector(9534839,24); manlo <= conv_std_logic_vector(42234535,28); exponent <= conv_std_logic_vector(1220,11); WHEN "0010001010" => manhi <= conv_std_logic_vector(1103679,24); manlo <= conv_std_logic_vector(94193887,28); exponent <= conv_std_logic_vector(1222,11); WHEN "0010001011" => manhi <= conv_std_logic_vector(7525440,24); manlo <= conv_std_logic_vector(121994268,28); exponent <= conv_std_logic_vector(1223,11); WHEN "0010001100" => manhi <= conv_std_logic_vector(16253518,24); manlo <= conv_std_logic_vector(191052573,28); exponent <= conv_std_logic_vector(1224,11); WHEN "0010001101" => manhi <= conv_std_logic_vector(5669495,24); manlo <= conv_std_logic_vector(130696997,28); exponent <= conv_std_logic_vector(1226,11); WHEN "0010001110" => manhi <= conv_std_logic_vector(13731027,24); manlo <= conv_std_logic_vector(260846837,28); exponent <= conv_std_logic_vector(1227,11); WHEN "0010001111" => manhi <= conv_std_logic_vector(3955285,24); manlo <= conv_std_logic_vector(80970159,28); exponent <= conv_std_logic_vector(1229,11); WHEN "0010010000" => manhi <= conv_std_logic_vector(11401174,24); manlo <= conv_std_logic_vector(207600506,28); exponent <= conv_std_logic_vector(1230,11); WHEN "0010010001" => manhi <= conv_std_logic_vector(2371985,24); manlo <= conv_std_logic_vector(241221170,28); exponent <= conv_std_logic_vector(1232,11); WHEN "0010010010" => manhi <= conv_std_logic_vector(9249247,24); manlo <= conv_std_logic_vector(208105818,28); exponent <= conv_std_logic_vector(1233,11); WHEN "0010010011" => manhi <= conv_std_logic_vector(909599,24); manlo <= conv_std_logic_vector(237519888,28); exponent <= conv_std_logic_vector(1235,11); WHEN "0010010100" => manhi <= conv_std_logic_vector(7261659,24); manlo <= conv_std_logic_vector(29935335,28); exponent <= conv_std_logic_vector(1236,11); WHEN "0010010101" => manhi <= conv_std_logic_vector(15895002,24); manlo <= conv_std_logic_vector(186862656,28); exponent <= conv_std_logic_vector(1237,11); WHEN "0010010110" => manhi <= conv_std_logic_vector(5425858,24); manlo <= conv_std_logic_vector(159524243,28); exponent <= conv_std_logic_vector(1239,11); WHEN "0010010111" => manhi <= conv_std_logic_vector(13399891,24); manlo <= conv_std_logic_vector(27586577,28); exponent <= conv_std_logic_vector(1240,11); WHEN "0010011000" => manhi <= conv_std_logic_vector(3730254,24); manlo <= conv_std_logic_vector(125689310,28); exponent <= conv_std_logic_vector(1242,11); WHEN "0010011001" => manhi <= conv_std_logic_vector(11095326,24); manlo <= conv_std_logic_vector(43144000,28); exponent <= conv_std_logic_vector(1243,11); WHEN "0010011010" => manhi <= conv_std_logic_vector(2164140,24); manlo <= conv_std_logic_vector(58280992,28); exponent <= conv_std_logic_vector(1245,11); WHEN "0010011011" => manhi <= conv_std_logic_vector(8966756,24); manlo <= conv_std_logic_vector(55210422,28); exponent <= conv_std_logic_vector(1246,11); WHEN "0010011100" => manhi <= conv_std_logic_vector(717626,24); manlo <= conv_std_logic_vector(257633658,28); exponent <= conv_std_logic_vector(1248,11); WHEN "0010011101" => manhi <= conv_std_logic_vector(7000740,24); manlo <= conv_std_logic_vector(229413090,28); exponent <= conv_std_logic_vector(1249,11); WHEN "0010011110" => manhi <= conv_std_logic_vector(15540378,24); manlo <= conv_std_logic_vector(4808337,28); exponent <= conv_std_logic_vector(1250,11); WHEN "0010011111" => manhi <= conv_std_logic_vector(5184866,24); manlo <= conv_std_logic_vector(37474138,28); exponent <= conv_std_logic_vector(1252,11); WHEN "0010100000" => manhi <= conv_std_logic_vector(13072348,24); manlo <= conv_std_logic_vector(106730632,28); exponent <= conv_std_logic_vector(1253,11); WHEN "0010100001" => manhi <= conv_std_logic_vector(3507666,24); manlo <= conv_std_logic_vector(32844500,28); exponent <= conv_std_logic_vector(1255,11); WHEN "0010100010" => manhi <= conv_std_logic_vector(10792797,24); manlo <= conv_std_logic_vector(62496090,28); exponent <= conv_std_logic_vector(1256,11); WHEN "0010100011" => manhi <= conv_std_logic_vector(1958550,24); manlo <= conv_std_logic_vector(132952012,28); exponent <= conv_std_logic_vector(1258,11); WHEN "0010100100" => manhi <= conv_std_logic_vector(8687330,24); manlo <= conv_std_logic_vector(215605290,28); exponent <= conv_std_logic_vector(1259,11); WHEN "0010100101" => manhi <= conv_std_logic_vector(527737,24); manlo <= conv_std_logic_vector(190928911,28); exponent <= conv_std_logic_vector(1261,11); WHEN "0010100110" => manhi <= conv_std_logic_vector(6742654,24); manlo <= conv_std_logic_vector(163162889,28); exponent <= conv_std_logic_vector(1262,11); WHEN "0010100111" => manhi <= conv_std_logic_vector(15189602,24); manlo <= conv_std_logic_vector(118241780,28); exponent <= conv_std_logic_vector(1263,11); WHEN "0010101000" => manhi <= conv_std_logic_vector(4946489,24); manlo <= conv_std_logic_vector(112771062,28); exponent <= conv_std_logic_vector(1265,11); WHEN "0010101001" => manhi <= conv_std_logic_vector(12748360,24); manlo <= conv_std_logic_vector(226864003,28); exponent <= conv_std_logic_vector(1266,11); WHEN "0010101010" => manhi <= conv_std_logic_vector(3287493,24); manlo <= conv_std_logic_vector(202192272,28); exponent <= conv_std_logic_vector(1268,11); WHEN "0010101011" => manhi <= conv_std_logic_vector(10493551,24); manlo <= conv_std_logic_vector(257093553,28); exponent <= conv_std_logic_vector(1269,11); WHEN "0010101100" => manhi <= conv_std_logic_vector(1755192,24); manlo <= conv_std_logic_vector(66281405,28); exponent <= conv_std_logic_vector(1271,11); WHEN "0010101101" => manhi <= conv_std_logic_vector(8410938,24); manlo <= conv_std_logic_vector(77199396,28); exponent <= conv_std_logic_vector(1272,11); WHEN "0010101110" => manhi <= conv_std_logic_vector(339909,24); manlo <= conv_std_logic_vector(140417186,28); exponent <= conv_std_logic_vector(1274,11); WHEN "0010101111" => manhi <= conv_std_logic_vector(6487369,24); manlo <= conv_std_logic_vector(169769464,28); exponent <= conv_std_logic_vector(1275,11); WHEN "0010110000" => manhi <= conv_std_logic_vector(14842634,24); manlo <= conv_std_logic_vector(49834035,28); exponent <= conv_std_logic_vector(1276,11); WHEN "0010110001" => manhi <= conv_std_logic_vector(4710700,24); manlo <= conv_std_logic_vector(11961455,28); exponent <= conv_std_logic_vector(1278,11); WHEN "0010110010" => manhi <= conv_std_logic_vector(12427889,24); manlo <= conv_std_logic_vector(230234502,28); exponent <= conv_std_logic_vector(1279,11); WHEN "0010110011" => manhi <= conv_std_logic_vector(3069711,24); manlo <= conv_std_logic_vector(36989233,28); exponent <= conv_std_logic_vector(1281,11); WHEN "0010110100" => manhi <= conv_std_logic_vector(10197554,24); manlo <= conv_std_logic_vector(186484869,28); exponent <= conv_std_logic_vector(1282,11); WHEN "0010110101" => manhi <= conv_std_logic_vector(1554041,24); manlo <= conv_std_logic_vector(67530342,28); exponent <= conv_std_logic_vector(1284,11); WHEN "0010110110" => manhi <= conv_std_logic_vector(8137545,24); manlo <= conv_std_logic_vector(198608842,28); exponent <= conv_std_logic_vector(1285,11); WHEN "0010110111" => manhi <= conv_std_logic_vector(154120,24); manlo <= conv_std_logic_vector(6569319,28); exponent <= conv_std_logic_vector(1287,11); WHEN "0010111000" => manhi <= conv_std_logic_vector(6234855,24); manlo <= conv_std_logic_vector(140506894,28); exponent <= conv_std_logic_vector(1288,11); WHEN "0010111001" => manhi <= conv_std_logic_vector(14499431,24); manlo <= conv_std_logic_vector(249287529,28); exponent <= conv_std_logic_vector(1289,11); WHEN "0010111010" => manhi <= conv_std_logic_vector(4477469,24); manlo <= conv_std_logic_vector(249618841,28); exponent <= conv_std_logic_vector(1291,11); WHEN "0010111011" => manhi <= conv_std_logic_vector(12110897,24); manlo <= conv_std_logic_vector(71519058,28); exponent <= conv_std_logic_vector(1292,11); WHEN "0010111100" => manhi <= conv_std_logic_vector(2854292,24); manlo <= conv_std_logic_vector(90637320,28); exponent <= conv_std_logic_vector(1294,11); WHEN "0010111101" => manhi <= conv_std_logic_vector(9904770,24); manlo <= conv_std_logic_vector(50932558,28); exponent <= conv_std_logic_vector(1295,11); WHEN "0010111110" => manhi <= conv_std_logic_vector(1355073,24); manlo <= conv_std_logic_vector(148093260,28); exponent <= conv_std_logic_vector(1297,11); WHEN "0010111111" => manhi <= conv_std_logic_vector(7867120,24); manlo <= conv_std_logic_vector(160620741,28); exponent <= conv_std_logic_vector(1298,11); WHEN "0011000000" => manhi <= conv_std_logic_vector(16717910,24); manlo <= conv_std_logic_vector(46942270,28); exponent <= conv_std_logic_vector(1299,11); WHEN "0011000001" => manhi <= conv_std_logic_vector(5985082,24); manlo <= conv_std_logic_vector(55237426,28); exponent <= conv_std_logic_vector(1301,11); WHEN "0011000010" => manhi <= conv_std_logic_vector(14159954,24); manlo <= conv_std_logic_vector(212966668,28); exponent <= conv_std_logic_vector(1302,11); WHEN "0011000011" => manhi <= conv_std_logic_vector(4246771,24); manlo <= conv_std_logic_vector(79962334,28); exponent <= conv_std_logic_vector(1304,11); WHEN "0011000100" => manhi <= conv_std_logic_vector(11797345,24); manlo <= conv_std_logic_vector(85038862,28); exponent <= conv_std_logic_vector(1305,11); WHEN "0011000101" => manhi <= conv_std_logic_vector(2641211,24); manlo <= conv_std_logic_vector(186806322,28); exponent <= conv_std_logic_vector(1307,11); WHEN "0011000110" => manhi <= conv_std_logic_vector(9615163,24); manlo <= conv_std_logic_vector(153415152,28); exponent <= conv_std_logic_vector(1308,11); WHEN "0011000111" => manhi <= conv_std_logic_vector(1158265,24); manlo <= conv_std_logic_vector(120731907,28); exponent <= conv_std_logic_vector(1310,11); WHEN "0011001000" => manhi <= conv_std_logic_vector(7599630,24); manlo <= conv_std_logic_vector(175764921,28); exponent <= conv_std_logic_vector(1311,11); WHEN "0011001001" => manhi <= conv_std_logic_vector(16354353,24); manlo <= conv_std_logic_vector(174054693,28); exponent <= conv_std_logic_vector(1312,11); WHEN "0011001010" => manhi <= conv_std_logic_vector(5738019,24); manlo <= conv_std_logic_vector(249885394,28); exponent <= conv_std_logic_vector(1314,11); WHEN "0011001011" => manhi <= conv_std_logic_vector(13824162,24); manlo <= conv_std_logic_vector(93203713,28); exponent <= conv_std_logic_vector(1315,11); WHEN "0011001100" => manhi <= conv_std_logic_vector(4018576,24); manlo <= conv_std_logic_vector(180323091,28); exponent <= conv_std_logic_vector(1317,11); WHEN "0011001101" => manhi <= conv_std_logic_vector(11487196,24); manlo <= conv_std_logic_vector(178245939,28); exponent <= conv_std_logic_vector(1318,11); WHEN "0011001110" => manhi <= conv_std_logic_vector(2430443,24); manlo <= conv_std_logic_vector(223919964,28); exponent <= conv_std_logic_vector(1320,11); WHEN "0011001111" => manhi <= conv_std_logic_vector(9328700,24); manlo <= conv_std_logic_vector(93205956,28); exponent <= conv_std_logic_vector(1321,11); WHEN "0011010000" => manhi <= conv_std_logic_vector(963593,24); manlo <= conv_std_logic_vector(135688620,28); exponent <= conv_std_logic_vector(1323,11); WHEN "0011010001" => manhi <= conv_std_logic_vector(7335044,24); manlo <= conv_std_logic_vector(13542358,28); exponent <= conv_std_logic_vector(1324,11); WHEN "0011010010" => manhi <= conv_std_logic_vector(15994743,24); manlo <= conv_std_logic_vector(45394459,28); exponent <= conv_std_logic_vector(1325,11); WHEN "0011010011" => manhi <= conv_std_logic_vector(5493639,24); manlo <= conv_std_logic_vector(73308838,28); exponent <= conv_std_logic_vector(1327,11); WHEN "0011010100" => manhi <= conv_std_logic_vector(13492014,24); manlo <= conv_std_logic_vector(160135181,28); exponent <= conv_std_logic_vector(1328,11); WHEN "0011010101" => manhi <= conv_std_logic_vector(3792858,24); manlo <= conv_std_logic_vector(234346738,28); exponent <= conv_std_logic_vector(1330,11); WHEN "0011010110" => manhi <= conv_std_logic_vector(11180414,24); manlo <= conv_std_logic_vector(98964646,28); exponent <= conv_std_logic_vector(1331,11); WHEN "0011010111" => manhi <= conv_std_logic_vector(2221963,24); manlo <= conv_std_logic_vector(174344531,28); exponent <= conv_std_logic_vector(1333,11); WHEN "0011011000" => manhi <= conv_std_logic_vector(9045346,24); manlo <= conv_std_logic_vector(106947534,28); exponent <= conv_std_logic_vector(1334,11); WHEN "0011011001" => manhi <= conv_std_logic_vector(771034,24); manlo <= conv_std_logic_vector(143065990,28); exponent <= conv_std_logic_vector(1336,11); WHEN "0011011010" => manhi <= conv_std_logic_vector(7073329,24); manlo <= conv_std_logic_vector(73148434,28); exponent <= conv_std_logic_vector(1337,11); WHEN "0011011011" => manhi <= conv_std_logic_vector(15639035,24); manlo <= conv_std_logic_vector(243346703,28); exponent <= conv_std_logic_vector(1338,11); WHEN "0011011100" => manhi <= conv_std_logic_vector(5251911,24); manlo <= conv_std_logic_vector(33842377,28); exponent <= conv_std_logic_vector(1340,11); WHEN "0011011101" => manhi <= conv_std_logic_vector(13163471,24); manlo <= conv_std_logic_vector(263552292,28); exponent <= conv_std_logic_vector(1341,11); WHEN "0011011110" => manhi <= conv_std_logic_vector(3569591,24); manlo <= conv_std_logic_vector(4866264,28); exponent <= conv_std_logic_vector(1343,11); WHEN "0011011111" => manhi <= conv_std_logic_vector(10876961,24); manlo <= conv_std_logic_vector(239517036,28); exponent <= conv_std_logic_vector(1344,11); WHEN "0011100000" => manhi <= conv_std_logic_vector(2015746,24); manlo <= conv_std_logic_vector(83586287,28); exponent <= conv_std_logic_vector(1346,11); WHEN "0011100001" => manhi <= conv_std_logic_vector(8765067,24); manlo <= conv_std_logic_vector(262254542,28); exponent <= conv_std_logic_vector(1347,11); WHEN "0011100010" => manhi <= conv_std_logic_vector(580565,24); manlo <= conv_std_logic_vector(160521039,28); exponent <= conv_std_logic_vector(1349,11); WHEN "0011100011" => manhi <= conv_std_logic_vector(6814455,24); manlo <= conv_std_logic_vector(40288155,28); exponent <= conv_std_logic_vector(1350,11); WHEN "0011100100" => manhi <= conv_std_logic_vector(15287189,24); manlo <= conv_std_logic_vector(132910147,28); exponent <= conv_std_logic_vector(1351,11); WHEN "0011100101" => manhi <= conv_std_logic_vector(5012806,24); manlo <= conv_std_logic_vector(187753904,28); exponent <= conv_std_logic_vector(1353,11); WHEN "0011100110" => manhi <= conv_std_logic_vector(12838495,24); manlo <= conv_std_logic_vector(100071648,28); exponent <= conv_std_logic_vector(1354,11); WHEN "0011100111" => manhi <= conv_std_logic_vector(3348746,24); manlo <= conv_std_logic_vector(138348888,28); exponent <= conv_std_logic_vector(1356,11); WHEN "0011101000" => manhi <= conv_std_logic_vector(10576803,24); manlo <= conv_std_logic_vector(24941937,28); exponent <= conv_std_logic_vector(1357,11); WHEN "0011101001" => manhi <= conv_std_logic_vector(1811767,24); manlo <= conv_std_logic_vector(69497619,28); exponent <= conv_std_logic_vector(1359,11); WHEN "0011101010" => manhi <= conv_std_logic_vector(8487831,24); manlo <= conv_std_logic_vector(188199296,28); exponent <= conv_std_logic_vector(1360,11); WHEN "0011101011" => manhi <= conv_std_logic_vector(392164,24); manlo <= conv_std_logic_vector(4096525,28); exponent <= conv_std_logic_vector(1362,11); WHEN "0011101100" => manhi <= conv_std_logic_vector(6558390,24); manlo <= conv_std_logic_vector(228356857,28); exponent <= conv_std_logic_vector(1363,11); WHEN "0011101101" => manhi <= conv_std_logic_vector(14939162,24); manlo <= conv_std_logic_vector(7826265,28); exponent <= conv_std_logic_vector(1364,11); WHEN "0011101110" => manhi <= conv_std_logic_vector(4776297,24); manlo <= conv_std_logic_vector(138324122,28); exponent <= conv_std_logic_vector(1366,11); WHEN "0011101111" => manhi <= conv_std_logic_vector(12517046,24); manlo <= conv_std_logic_vector(17190560,28); exponent <= conv_std_logic_vector(1367,11); WHEN "0011110000" => manhi <= conv_std_logic_vector(3130299,24); manlo <= conv_std_logic_vector(16562242,28); exponent <= conv_std_logic_vector(1369,11); WHEN "0011110001" => manhi <= conv_std_logic_vector(10279902,24); manlo <= conv_std_logic_vector(59323104,28); exponent <= conv_std_logic_vector(1370,11); WHEN "0011110010" => manhi <= conv_std_logic_vector(1610002,24); manlo <= conv_std_logic_vector(53056333,28); exponent <= conv_std_logic_vector(1372,11); WHEN "0011110011" => manhi <= conv_std_logic_vector(8213604,24); manlo <= conv_std_logic_vector(147986337,28); exponent <= conv_std_logic_vector(1373,11); WHEN "0011110100" => manhi <= conv_std_logic_vector(205807,24); manlo <= conv_std_logic_vector(92802035,28); exponent <= conv_std_logic_vector(1375,11); WHEN "0011110101" => manhi <= conv_std_logic_vector(6305105,24); manlo <= conv_std_logic_vector(235277170,28); exponent <= conv_std_logic_vector(1376,11); WHEN "0011110110" => manhi <= conv_std_logic_vector(14594912,24); manlo <= conv_std_logic_vector(15497684,28); exponent <= conv_std_logic_vector(1377,11); WHEN "0011110111" => manhi <= conv_std_logic_vector(4542355,24); manlo <= conv_std_logic_vector(108677892,28); exponent <= conv_std_logic_vector(1379,11); WHEN "0011111000" => manhi <= conv_std_logic_vector(12199085,24); manlo <= conv_std_logic_vector(206743222,28); exponent <= conv_std_logic_vector(1380,11); WHEN "0011111001" => manhi <= conv_std_logic_vector(2914222,24); manlo <= conv_std_logic_vector(171652524,28); exponent <= conv_std_logic_vector(1382,11); WHEN "0011111010" => manhi <= conv_std_logic_vector(9986223,24); manlo <= conv_std_logic_vector(245598061,28); exponent <= conv_std_logic_vector(1383,11); WHEN "0011111011" => manhi <= conv_std_logic_vector(1410427,24); manlo <= conv_std_logic_vector(26024388,28); exponent <= conv_std_logic_vector(1385,11); WHEN "0011111100" => manhi <= conv_std_logic_vector(7942353,24); manlo <= conv_std_logic_vector(232590388,28); exponent <= conv_std_logic_vector(1386,11); WHEN "0011111101" => manhi <= conv_std_logic_vector(21473,24); manlo <= conv_std_logic_vector(105719295,28); exponent <= conv_std_logic_vector(1388,11); WHEN "0011111110" => manhi <= conv_std_logic_vector(6054570,24); manlo <= conv_std_logic_vector(16265786,28); exponent <= conv_std_logic_vector(1389,11); WHEN "0011111111" => manhi <= conv_std_logic_vector(14254398,24); manlo <= conv_std_logic_vector(155662944,28); exponent <= conv_std_logic_vector(1390,11); WHEN "0100000000" => manhi <= conv_std_logic_vector(4310952,24); manlo <= conv_std_logic_vector(135577274,28); exponent <= conv_std_logic_vector(1392,11); WHEN "0100000001" => manhi <= conv_std_logic_vector(11884576,24); manlo <= conv_std_logic_vector(166805756,28); exponent <= conv_std_logic_vector(1393,11); WHEN "0100000010" => manhi <= conv_std_logic_vector(2700491,24); manlo <= conv_std_logic_vector(137829044,28); exponent <= conv_std_logic_vector(1395,11); WHEN "0100000011" => manhi <= conv_std_logic_vector(9695733,24); manlo <= conv_std_logic_vector(52863001,28); exponent <= conv_std_logic_vector(1396,11); WHEN "0100000100" => manhi <= conv_std_logic_vector(1213018,24); manlo <= conv_std_logic_vector(50179603,28); exponent <= conv_std_logic_vector(1398,11); WHEN "0100000101" => manhi <= conv_std_logic_vector(7674047,24); manlo <= conv_std_logic_vector(91276680,28); exponent <= conv_std_logic_vector(1399,11); WHEN "0100000110" => manhi <= conv_std_logic_vector(16455496,24); manlo <= conv_std_logic_vector(110068760,28); exponent <= conv_std_logic_vector(1400,11); WHEN "0100000111" => manhi <= conv_std_logic_vector(5806753,24); manlo <= conv_std_logic_vector(151304445,28); exponent <= conv_std_logic_vector(1402,11); WHEN "0100001000" => manhi <= conv_std_logic_vector(13917581,24); manlo <= conv_std_logic_vector(10650184,28); exponent <= conv_std_logic_vector(1403,11); WHEN "0100001001" => manhi <= conv_std_logic_vector(4082061,24); manlo <= conv_std_logic_vector(68530707,28); exponent <= conv_std_logic_vector(1405,11); WHEN "0100001010" => manhi <= conv_std_logic_vector(11573481,24); manlo <= conv_std_logic_vector(42662756,28); exponent <= conv_std_logic_vector(1406,11); WHEN "0100001011" => manhi <= conv_std_logic_vector(2489080,24); manlo <= conv_std_logic_vector(61154162,28); exponent <= conv_std_logic_vector(1408,11); WHEN "0100001100" => manhi <= conv_std_logic_vector(9408395,24); manlo <= conv_std_logic_vector(125867240,28); exponent <= conv_std_logic_vector(1409,11); WHEN "0100001101" => manhi <= conv_std_logic_vector(1017751,24); manlo <= conv_std_logic_vector(256555705,28); exponent <= conv_std_logic_vector(1411,11); WHEN "0100001110" => manhi <= conv_std_logic_vector(7408653,24); manlo <= conv_std_logic_vector(4309896,28); exponent <= conv_std_logic_vector(1412,11); WHEN "0100001111" => manhi <= conv_std_logic_vector(16094788,24); manlo <= conv_std_logic_vector(33800670,28); exponent <= conv_std_logic_vector(1413,11); WHEN "0100010000" => manhi <= conv_std_logic_vector(5561626,24); manlo <= conv_std_logic_vector(233573192,28); exponent <= conv_std_logic_vector(1415,11); WHEN "0100010001" => manhi <= conv_std_logic_vector(13584419,24); manlo <= conv_std_logic_vector(86257801,28); exponent <= conv_std_logic_vector(1416,11); WHEN "0100010010" => manhi <= conv_std_logic_vector(3855654,24); manlo <= conv_std_logic_vector(105782775,28); exponent <= conv_std_logic_vector(1418,11); WHEN "0100010011" => manhi <= conv_std_logic_vector(11265762,24); manlo <= conv_std_logic_vector(88738762,28); exponent <= conv_std_logic_vector(1419,11); WHEN "0100010100" => manhi <= conv_std_logic_vector(2279963,24); manlo <= conv_std_logic_vector(161858527,28); exponent <= conv_std_logic_vector(1421,11); WHEN "0100010101" => manhi <= conv_std_logic_vector(9124176,24); manlo <= conv_std_logic_vector(136423424,28); exponent <= conv_std_logic_vector(1422,11); WHEN "0100010110" => manhi <= conv_std_logic_vector(824605,24); manlo <= conv_std_logic_vector(39384255,28); exponent <= conv_std_logic_vector(1424,11); WHEN "0100010111" => manhi <= conv_std_logic_vector(7146139,24); manlo <= conv_std_logic_vector(76626123,28); exponent <= conv_std_logic_vector(1425,11); WHEN "0100011000" => manhi <= conv_std_logic_vector(15737994,24); manlo <= conv_std_logic_vector(261485765,28); exponent <= conv_std_logic_vector(1426,11); WHEN "0100011001" => manhi <= conv_std_logic_vector(5319160,24); manlo <= conv_std_logic_vector(210684009,28); exponent <= conv_std_logic_vector(1428,11); WHEN "0100011010" => manhi <= conv_std_logic_vector(13254873,24); manlo <= conv_std_logic_vector(199859160,28); exponent <= conv_std_logic_vector(1429,11); WHEN "0100011011" => manhi <= conv_std_logic_vector(3631704,24); manlo <= conv_std_logic_vector(256571707,28); exponent <= conv_std_logic_vector(1431,11); WHEN "0100011100" => manhi <= conv_std_logic_vector(10961383,24); manlo <= conv_std_logic_vector(130542749,28); exponent <= conv_std_logic_vector(1432,11); WHEN "0100011101" => manhi <= conv_std_logic_vector(2073116,24); manlo <= conv_std_logic_vector(196665136,28); exponent <= conv_std_logic_vector(1434,11); WHEN "0100011110" => manhi <= conv_std_logic_vector(8843042,24); manlo <= conv_std_logic_vector(124490661,28); exponent <= conv_std_logic_vector(1435,11); WHEN "0100011111" => manhi <= conv_std_logic_vector(633554,24); manlo <= conv_std_logic_vector(202834752,28); exponent <= conv_std_logic_vector(1437,11); WHEN "0100100000" => manhi <= conv_std_logic_vector(6886474,24); manlo <= conv_std_logic_vector(236822279,28); exponent <= conv_std_logic_vector(1438,11); WHEN "0100100001" => manhi <= conv_std_logic_vector(15385074,24); manlo <= conv_std_logic_vector(123405487,28); exponent <= conv_std_logic_vector(1439,11); WHEN "0100100010" => manhi <= conv_std_logic_vector(5079326,24); manlo <= conv_std_logic_vector(115311954,28); exponent <= conv_std_logic_vector(1441,11); WHEN "0100100011" => manhi <= conv_std_logic_vector(12928905,24); manlo <= conv_std_logic_vector(16004876,28); exponent <= conv_std_logic_vector(1442,11); WHEN "0100100100" => manhi <= conv_std_logic_vector(3410186,24); manlo <= conv_std_logic_vector(71831800,28); exponent <= conv_std_logic_vector(1444,11); WHEN "0100100101" => manhi <= conv_std_logic_vector(10660308,24); manlo <= conv_std_logic_vector(100367284,28); exponent <= conv_std_logic_vector(1445,11); WHEN "0100100110" => manhi <= conv_std_logic_vector(1868514,24); manlo <= conv_std_logic_vector(263299419,28); exponent <= conv_std_logic_vector(1447,11); WHEN "0100100111" => manhi <= conv_std_logic_vector(8564959,24); manlo <= conv_std_logic_vector(228656810,28); exponent <= conv_std_logic_vector(1448,11); WHEN "0100101000" => manhi <= conv_std_logic_vector(444578,24); manlo <= conv_std_logic_vector(7489141,28); exponent <= conv_std_logic_vector(1450,11); WHEN "0100101001" => manhi <= conv_std_logic_vector(6629628,24); manlo <= conv_std_logic_vector(236156491,28); exponent <= conv_std_logic_vector(1451,11); WHEN "0100101010" => manhi <= conv_std_logic_vector(15035984,24); manlo <= conv_std_logic_vector(147396312,28); exponent <= conv_std_logic_vector(1452,11); WHEN "0100101011" => manhi <= conv_std_logic_vector(4842095,24); manlo <= conv_std_logic_vector(64271882,28); exponent <= conv_std_logic_vector(1454,11); WHEN "0100101100" => manhi <= conv_std_logic_vector(12606474,24); manlo <= conv_std_logic_vector(118909770,28); exponent <= conv_std_logic_vector(1455,11); WHEN "0100101101" => manhi <= conv_std_logic_vector(3191071,24); manlo <= conv_std_logic_vector(253953386,28); exponent <= conv_std_logic_vector(1457,11); WHEN "0100101110" => manhi <= conv_std_logic_vector(10362501,24); manlo <= conv_std_logic_vector(36129498,28); exponent <= conv_std_logic_vector(1458,11); WHEN "0100101111" => manhi <= conv_std_logic_vector(1666133,24); manlo <= conv_std_logic_vector(262830684,28); exponent <= conv_std_logic_vector(1460,11); WHEN "0100110000" => manhi <= conv_std_logic_vector(8289895,24); manlo <= conv_std_logic_vector(148197046,28); exponent <= conv_std_logic_vector(1461,11); WHEN "0100110001" => manhi <= conv_std_logic_vector(257652,24); manlo <= conv_std_logic_vector(122404338,28); exponent <= conv_std_logic_vector(1463,11); WHEN "0100110010" => manhi <= conv_std_logic_vector(6375570,24); manlo <= conv_std_logic_vector(184430245,28); exponent <= conv_std_logic_vector(1464,11); WHEN "0100110011" => manhi <= conv_std_logic_vector(14690683,24); manlo <= conv_std_logic_vector(178457687,28); exponent <= conv_std_logic_vector(1465,11); WHEN "0100110100" => manhi <= conv_std_logic_vector(4607438,24); manlo <= conv_std_logic_vector(257605193,28); exponent <= conv_std_logic_vector(1467,11); WHEN "0100110101" => manhi <= conv_std_logic_vector(12287543,24); manlo <= conv_std_logic_vector(132163446,28); exponent <= conv_std_logic_vector(1468,11); WHEN "0100110110" => manhi <= conv_std_logic_vector(2974335,24); manlo <= conv_std_logic_vector(240020217,28); exponent <= conv_std_logic_vector(1470,11); WHEN "0100110111" => manhi <= conv_std_logic_vector(10067926,24); manlo <= conv_std_logic_vector(80224641,28); exponent <= conv_std_logic_vector(1471,11); WHEN "0100111000" => manhi <= conv_std_logic_vector(1465949,24); manlo <= conv_std_logic_vector(167328478,28); exponent <= conv_std_logic_vector(1473,11); WHEN "0100111001" => manhi <= conv_std_logic_vector(8017816,24); manlo <= conv_std_logic_vector(215756784,28); exponent <= conv_std_logic_vector(1474,11); WHEN "0100111010" => manhi <= conv_std_logic_vector(72755,24); manlo <= conv_std_logic_vector(208473528,28); exponent <= conv_std_logic_vector(1476,11); WHEN "0100111011" => manhi <= conv_std_logic_vector(6124270,24); manlo <= conv_std_logic_vector(12139444,28); exponent <= conv_std_logic_vector(1477,11); WHEN "0100111100" => manhi <= conv_std_logic_vector(14349130,24); manlo <= conv_std_logic_vector(182729110,28); exponent <= conv_std_logic_vector(1478,11); WHEN "0100111101" => manhi <= conv_std_logic_vector(4375329,24); manlo <= conv_std_logic_vector(172370119,28); exponent <= conv_std_logic_vector(1480,11); WHEN "0100111110" => manhi <= conv_std_logic_vector(11972074,24); manlo <= conv_std_logic_vector(59679792,28); exponent <= conv_std_logic_vector(1481,11); WHEN "0100111111" => manhi <= conv_std_logic_vector(2759952,24); manlo <= conv_std_logic_vector(80023302,28); exponent <= conv_std_logic_vector(1483,11); WHEN "0101000000" => manhi <= conv_std_logic_vector(9776548,24); manlo <= conv_std_logic_vector(209956608,28); exponent <= conv_std_logic_vector(1484,11); WHEN "0101000001" => manhi <= conv_std_logic_vector(1267938,24); manlo <= conv_std_logic_vector(19091951,28); exponent <= conv_std_logic_vector(1486,11); WHEN "0101000010" => manhi <= conv_std_logic_vector(7748691,24); manlo <= conv_std_logic_vector(54127000,28); exponent <= conv_std_logic_vector(1487,11); WHEN "0101000011" => manhi <= conv_std_logic_vector(16556947,24); manlo <= conv_std_logic_vector(251347868,28); exponent <= conv_std_logic_vector(1488,11); WHEN "0101000100" => manhi <= conv_std_logic_vector(5875697,24); manlo <= conv_std_logic_vector(6377900,28); exponent <= conv_std_logic_vector(1490,11); WHEN "0101000101" => manhi <= conv_std_logic_vector(14011284,24); manlo <= conv_std_logic_vector(246175281,28); exponent <= conv_std_logic_vector(1491,11); WHEN "0101000110" => manhi <= conv_std_logic_vector(4145739,24); manlo <= conv_std_logic_vector(172360927,28); exponent <= conv_std_logic_vector(1493,11); WHEN "0101000111" => manhi <= conv_std_logic_vector(11660029,24); manlo <= conv_std_logic_vector(16047086,28); exponent <= conv_std_logic_vector(1494,11); WHEN "0101001000" => manhi <= conv_std_logic_vector(2547895,24); manlo <= conv_std_logic_vector(167600151,28); exponent <= conv_std_logic_vector(1496,11); WHEN "0101001001" => manhi <= conv_std_logic_vector(9488333,24); manlo <= conv_std_logic_vector(236416250,28); exponent <= conv_std_logic_vector(1497,11); WHEN "0101001010" => manhi <= conv_std_logic_vector(1072075,24); manlo <= conv_std_logic_vector(198323037,28); exponent <= conv_std_logic_vector(1499,11); WHEN "0101001011" => manhi <= conv_std_logic_vector(7482486,24); manlo <= conv_std_logic_vector(185820926,28); exponent <= conv_std_logic_vector(1500,11); WHEN "0101001100" => manhi <= conv_std_logic_vector(16195138,24); manlo <= conv_std_logic_vector(133160968,28); exponent <= conv_std_logic_vector(1501,11); WHEN "0101001101" => manhi <= conv_std_logic_vector(5629822,24); manlo <= conv_std_logic_vector(4574050,28); exponent <= conv_std_logic_vector(1503,11); WHEN "0101001110" => manhi <= conv_std_logic_vector(13677106,24); manlo <= conv_std_logic_vector(36414601,28); exponent <= conv_std_logic_vector(1504,11); WHEN "0101001111" => manhi <= conv_std_logic_vector(3918641,24); manlo <= conv_std_logic_vector(165046798,28); exponent <= conv_std_logic_vector(1506,11); WHEN "0101010000" => manhi <= conv_std_logic_vector(11351370,24); manlo <= conv_std_logic_vector(225326735,28); exponent <= conv_std_logic_vector(1507,11); WHEN "0101010001" => manhi <= conv_std_logic_vector(2338140,24); manlo <= conv_std_logic_vector(165476611,28); exponent <= conv_std_logic_vector(1509,11); WHEN "0101010010" => manhi <= conv_std_logic_vector(9203247,24); manlo <= conv_std_logic_vector(71807303,28); exponent <= conv_std_logic_vector(1510,11); WHEN "0101010011" => manhi <= conv_std_logic_vector(878339,24); manlo <= conv_std_logic_vector(80195176,28); exponent <= conv_std_logic_vector(1512,11); WHEN "0101010100" => manhi <= conv_std_logic_vector(7219171,24); manlo <= conv_std_logic_vector(153001068,28); exponent <= conv_std_logic_vector(1513,11); WHEN "0101010101" => manhi <= conv_std_logic_vector(15837256,24); manlo <= conv_std_logic_vector(37596960,28); exponent <= conv_std_logic_vector(1514,11); WHEN "0101010110" => manhi <= conv_std_logic_vector(5386615,24); manlo <= conv_std_logic_vector(198850796,28); exponent <= conv_std_logic_vector(1516,11); WHEN "0101010111" => manhi <= conv_std_logic_vector(13346554,24); manlo <= conv_std_logic_vector(143609986,28); exponent <= conv_std_logic_vector(1517,11); WHEN "0101011000" => manhi <= conv_std_logic_vector(3694008,24); manlo <= conv_std_logic_vector(137568494,28); exponent <= conv_std_logic_vector(1519,11); WHEN "0101011001" => manhi <= conv_std_logic_vector(11046062,24); manlo <= conv_std_logic_vector(214558683,28); exponent <= conv_std_logic_vector(1520,11); WHEN "0101011010" => manhi <= conv_std_logic_vector(2130662,24); manlo <= conv_std_logic_vector(78401205,28); exponent <= conv_std_logic_vector(1522,11); WHEN "0101011011" => manhi <= conv_std_logic_vector(8921254,24); manlo <= conv_std_logic_vector(265219821,28); exponent <= conv_std_logic_vector(1523,11); WHEN "0101011100" => manhi <= conv_std_logic_vector(686705,24); manlo <= conv_std_logic_vector(181591149,28); exponent <= conv_std_logic_vector(1525,11); WHEN "0101011101" => manhi <= conv_std_logic_vector(6958714,24); manlo <= conv_std_logic_vector(127078273,28); exponent <= conv_std_logic_vector(1526,11); WHEN "0101011110" => manhi <= conv_std_logic_vector(15483258,24); manlo <= conv_std_logic_vector(65420394,28); exponent <= conv_std_logic_vector(1527,11); WHEN "0101011111" => manhi <= conv_std_logic_vector(5146049,24); manlo <= conv_std_logic_vector(61347424,28); exponent <= conv_std_logic_vector(1529,11); WHEN "0101100000" => manhi <= conv_std_logic_vector(13019590,24); manlo <= conv_std_logic_vector(200148168,28); exponent <= conv_std_logic_vector(1530,11); WHEN "0101100001" => manhi <= conv_std_logic_vector(3471813,24); manlo <= conv_std_logic_vector(155873600,28); exponent <= conv_std_logic_vector(1532,11); WHEN "0101100010" => manhi <= conv_std_logic_vector(10744068,24); manlo <= conv_std_logic_vector(154763366,28); exponent <= conv_std_logic_vector(1533,11); WHEN "0101100011" => manhi <= conv_std_logic_vector(1925435,24); manlo <= conv_std_logic_vector(252346422,28); exponent <= conv_std_logic_vector(1535,11); WHEN "0101100100" => manhi <= conv_std_logic_vector(8642323,24); manlo <= conv_std_logic_vector(122496413,28); exponent <= conv_std_logic_vector(1536,11); WHEN "0101100101" => manhi <= conv_std_logic_vector(497152,24); manlo <= conv_std_logic_vector(12881703,28); exponent <= conv_std_logic_vector(1538,11); WHEN "0101100110" => manhi <= conv_std_logic_vector(6701084,24); manlo <= conv_std_logic_vector(102402698,28); exponent <= conv_std_logic_vector(1539,11); WHEN "0101100111" => manhi <= conv_std_logic_vector(15133102,24); manlo <= conv_std_logic_vector(173151546,28); exponent <= conv_std_logic_vector(1540,11); WHEN "0101101000" => manhi <= conv_std_logic_vector(4908093,24); manlo <= conv_std_logic_vector(222341698,28); exponent <= conv_std_logic_vector(1542,11); WHEN "0101101001" => manhi <= conv_std_logic_vector(12696175,24); manlo <= conv_std_logic_vector(221558290,28); exponent <= conv_std_logic_vector(1543,11); WHEN "0101101010" => manhi <= conv_std_logic_vector(3252030,24); manlo <= conv_std_logic_vector(95425703,28); exponent <= conv_std_logic_vector(1545,11); WHEN "0101101011" => manhi <= conv_std_logic_vector(10445352,24); manlo <= conv_std_logic_vector(54472775,28); exponent <= conv_std_logic_vector(1546,11); WHEN "0101101100" => manhi <= conv_std_logic_vector(1722437,24); manlo <= conv_std_logic_vector(31541381,28); exponent <= conv_std_logic_vector(1548,11); WHEN "0101101101" => manhi <= conv_std_logic_vector(8366419,24); manlo <= conv_std_logic_vector(121077564,28); exponent <= conv_std_logic_vector(1549,11); WHEN "0101101110" => manhi <= conv_std_logic_vector(309655,24); manlo <= conv_std_logic_vector(224679493,28); exponent <= conv_std_logic_vector(1551,11); WHEN "0101101111" => manhi <= conv_std_logic_vector(6446250,24); manlo <= conv_std_logic_vector(163707479,28); exponent <= conv_std_logic_vector(1552,11); WHEN "0101110000" => manhi <= conv_std_logic_vector(14786747,24); manlo <= conv_std_logic_vector(171718440,28); exponent <= conv_std_logic_vector(1553,11); WHEN "0101110001" => manhi <= conv_std_logic_vector(4672721,24); manlo <= conv_std_logic_vector(53414720,28); exponent <= conv_std_logic_vector(1555,11); WHEN "0101110010" => manhi <= conv_std_logic_vector(12376271,24); manlo <= conv_std_logic_vector(68395953,28); exponent <= conv_std_logic_vector(1556,11); WHEN "0101110011" => manhi <= conv_std_logic_vector(3034632,24); manlo <= conv_std_logic_vector(177229210,28); exponent <= conv_std_logic_vector(1558,11); WHEN "0101110100" => manhi <= conv_std_logic_vector(10149878,24); manlo <= conv_std_logic_vector(27015960,28); exponent <= conv_std_logic_vector(1559,11); WHEN "0101110101" => manhi <= conv_std_logic_vector(1521641,24); manlo <= conv_std_logic_vector(173609470,28); exponent <= conv_std_logic_vector(1561,11); WHEN "0101110110" => manhi <= conv_std_logic_vector(8093510,24); manlo <= conv_std_logic_vector(29891310,28); exponent <= conv_std_logic_vector(1562,11); WHEN "0101110111" => manhi <= conv_std_logic_vector(124194,24); manlo <= conv_std_logic_vector(191198183,28); exponent <= conv_std_logic_vector(1564,11); WHEN "0101111000" => manhi <= conv_std_logic_vector(6194182,24); manlo <= conv_std_logic_vector(216692261,28); exponent <= conv_std_logic_vector(1565,11); WHEN "0101111001" => manhi <= conv_std_logic_vector(14444151,24); manlo <= conv_std_logic_vector(261994424,28); exponent <= conv_std_logic_vector(1566,11); WHEN "0101111010" => manhi <= conv_std_logic_vector(4439903,24); manlo <= conv_std_logic_vector(82463931,28); exponent <= conv_std_logic_vector(1568,11); WHEN "0101111011" => manhi <= conv_std_logic_vector(12059838,24); manlo <= conv_std_logic_vector(250318074,28); exponent <= conv_std_logic_vector(1569,11); WHEN "0101111100" => manhi <= conv_std_logic_vector(2819594,24); manlo <= conv_std_logic_vector(161686084,28); exponent <= conv_std_logic_vector(1571,11); WHEN "0101111101" => manhi <= conv_std_logic_vector(9857611,24); manlo <= conv_std_logic_vector(20946108,28); exponent <= conv_std_logic_vector(1572,11); WHEN "0101111110" => manhi <= conv_std_logic_vector(1323025,24); manlo <= conv_std_logic_vector(164440795,28); exponent <= conv_std_logic_vector(1574,11); WHEN "0101111111" => manhi <= conv_std_logic_vector(7823562,24); manlo <= conv_std_logic_vector(250479918,28); exponent <= conv_std_logic_vector(1575,11); WHEN "0110000000" => manhi <= conv_std_logic_vector(16658709,24); manlo <= conv_std_logic_vector(45608811,28); exponent <= conv_std_logic_vector(1576,11); WHEN "0110000001" => manhi <= conv_std_logic_vector(5944850,24); manlo <= conv_std_logic_vector(255488281,28); exponent <= conv_std_logic_vector(1578,11); WHEN "0110000010" => manhi <= conv_std_logic_vector(14105274,24); manlo <= conv_std_logic_vector(228172930,28); exponent <= conv_std_logic_vector(1579,11); WHEN "0110000011" => manhi <= conv_std_logic_vector(4209612,24); manlo <= conv_std_logic_vector(113758652,28); exponent <= conv_std_logic_vector(1581,11); WHEN "0110000100" => manhi <= conv_std_logic_vector(11746841,24); manlo <= conv_std_logic_vector(45816542,28); exponent <= conv_std_logic_vector(1582,11); WHEN "0110000101" => manhi <= conv_std_logic_vector(2606890,24); manlo <= conv_std_logic_vector(153074390,28); exponent <= conv_std_logic_vector(1584,11); WHEN "0110000110" => manhi <= conv_std_logic_vector(9568516,24); manlo <= conv_std_logic_vector(87350878,28); exponent <= conv_std_logic_vector(1585,11); WHEN "0110000111" => manhi <= conv_std_logic_vector(1126565,24); manlo <= conv_std_logic_vector(96475766,28); exponent <= conv_std_logic_vector(1587,11); WHEN "0110001000" => manhi <= conv_std_logic_vector(7556545,24); manlo <= conv_std_logic_vector(205347948,28); exponent <= conv_std_logic_vector(1588,11); WHEN "0110001001" => manhi <= conv_std_logic_vector(16295795,24); manlo <= conv_std_logic_vector(56881285,28); exponent <= conv_std_logic_vector(1589,11); WHEN "0110001010" => manhi <= conv_std_logic_vector(5698225,24); manlo <= conv_std_logic_vector(93263076,28); exponent <= conv_std_logic_vector(1591,11); WHEN "0110001011" => manhi <= conv_std_logic_vector(13770075,24); manlo <= conv_std_logic_vector(241769289,28); exponent <= conv_std_logic_vector(1592,11); WHEN "0110001100" => manhi <= conv_std_logic_vector(3981821,24); manlo <= conv_std_logic_vector(32359920,28); exponent <= conv_std_logic_vector(1594,11); WHEN "0110001101" => manhi <= conv_std_logic_vector(11437240,24); manlo <= conv_std_logic_vector(185367850,28); exponent <= conv_std_logic_vector(1595,11); WHEN "0110001110" => manhi <= conv_std_logic_vector(2396495,24); manlo <= conv_std_logic_vector(61858550,28); exponent <= conv_std_logic_vector(1597,11); WHEN "0110001111" => manhi <= conv_std_logic_vector(9282559,24); manlo <= conv_std_logic_vector(110304027,28); exponent <= conv_std_logic_vector(1598,11); WHEN "0110010000" => manhi <= conv_std_logic_vector(932237,24); manlo <= conv_std_logic_vector(131077892,28); exponent <= conv_std_logic_vector(1600,11); WHEN "0110010001" => manhi <= conv_std_logic_vector(7292426,24); manlo <= conv_std_logic_vector(215982528,28); exponent <= conv_std_logic_vector(1601,11); WHEN "0110010010" => manhi <= conv_std_logic_vector(15936820,24); manlo <= conv_std_logic_vector(87676082,28); exponent <= conv_std_logic_vector(1602,11); WHEN "0110010011" => manhi <= conv_std_logic_vector(5454276,24); manlo <= conv_std_logic_vector(166577430,28); exponent <= conv_std_logic_vector(1604,11); WHEN "0110010100" => manhi <= conv_std_logic_vector(13438515,24); manlo <= conv_std_logic_vector(55023964,28); exponent <= conv_std_logic_vector(1605,11); WHEN "0110010101" => manhi <= conv_std_logic_vector(3756502,24); manlo <= conv_std_logic_vector(71679026,28); exponent <= conv_std_logic_vector(1607,11); WHEN "0110010110" => manhi <= conv_std_logic_vector(11131000,24); manlo <= conv_std_logic_vector(165886683,28); exponent <= conv_std_logic_vector(1608,11); WHEN "0110010111" => manhi <= conv_std_logic_vector(2188383,24); manlo <= conv_std_logic_vector(140750309,28); exponent <= conv_std_logic_vector(1610,11); WHEN "0110011000" => manhi <= conv_std_logic_vector(8999706,24); manlo <= conv_std_logic_vector(74200045,28); exponent <= conv_std_logic_vector(1611,11); WHEN "0110011001" => manhi <= conv_std_logic_vector(740018,24); manlo <= conv_std_logic_vector(229350227,28); exponent <= conv_std_logic_vector(1613,11); WHEN "0110011010" => manhi <= conv_std_logic_vector(7031174,24); manlo <= conv_std_logic_vector(159659309,28); exponent <= conv_std_logic_vector(1614,11); WHEN "0110011011" => manhi <= conv_std_logic_vector(15581741,24); manlo <= conv_std_logic_vector(203828183,28); exponent <= conv_std_logic_vector(1615,11); WHEN "0110011100" => manhi <= conv_std_logic_vector(5212975,24); manlo <= conv_std_logic_vector(192268981,28); exponent <= conv_std_logic_vector(1617,11); WHEN "0110011101" => manhi <= conv_std_logic_vector(13110553,24); manlo <= conv_std_logic_vector(73367990,28); exponent <= conv_std_logic_vector(1618,11); WHEN "0110011110" => manhi <= conv_std_logic_vector(3533629,24); manlo <= conv_std_logic_vector(7303751,28); exponent <= conv_std_logic_vector(1620,11); WHEN "0110011111" => manhi <= conv_std_logic_vector(10828084,24); manlo <= conv_std_logic_vector(128595197,28); exponent <= conv_std_logic_vector(1621,11); WHEN "0110100000" => manhi <= conv_std_logic_vector(1982530,24); manlo <= conv_std_logic_vector(178601213,28); exponent <= conv_std_logic_vector(1623,11); WHEN "0110100001" => manhi <= conv_std_logic_vector(8719923,24); manlo <= conv_std_logic_vector(62665264,28); exponent <= conv_std_logic_vector(1624,11); WHEN "0110100010" => manhi <= conv_std_logic_vector(549886,24); manlo <= conv_std_logic_vector(151395401,28); exponent <= conv_std_logic_vector(1626,11); WHEN "0110100011" => manhi <= conv_std_logic_vector(6772758,24); manlo <= conv_std_logic_vector(5307652,28); exponent <= conv_std_logic_vector(1627,11); WHEN "0110100100" => manhi <= conv_std_logic_vector(15230517,24); manlo <= conv_std_logic_vector(58871965,28); exponent <= conv_std_logic_vector(1628,11); WHEN "0110100101" => manhi <= conv_std_logic_vector(4974293,24); manlo <= conv_std_logic_vector(240265124,28); exponent <= conv_std_logic_vector(1630,11); WHEN "0110100110" => manhi <= conv_std_logic_vector(12786151,24); manlo <= conv_std_logic_vector(11983156,28); exponent <= conv_std_logic_vector(1631,11); WHEN "0110100111" => manhi <= conv_std_logic_vector(3313174,24); manlo <= conv_std_logic_vector(229882212,28); exponent <= conv_std_logic_vector(1633,11); WHEN "0110101000" => manhi <= conv_std_logic_vector(10528456,24); manlo <= conv_std_logic_vector(52550536,28); exponent <= conv_std_logic_vector(1634,11); WHEN "0110101001" => manhi <= conv_std_logic_vector(1778912,24); manlo <= conv_std_logic_vector(36481057,28); exponent <= conv_std_logic_vector(1636,11); WHEN "0110101010" => manhi <= conv_std_logic_vector(8443176,24); manlo <= conv_std_logic_vector(257480801,28); exponent <= conv_std_logic_vector(1637,11); WHEN "0110101011" => manhi <= conv_std_logic_vector(361817,24); manlo <= conv_std_logic_vector(260890045,28); exponent <= conv_std_logic_vector(1639,11); WHEN "0110101100" => manhi <= conv_std_logic_vector(6517146,24); manlo <= conv_std_logic_vector(80951272,28); exponent <= conv_std_logic_vector(1640,11); WHEN "0110101101" => manhi <= conv_std_logic_vector(14883104,24); manlo <= conv_std_logic_vector(234866389,28); exponent <= conv_std_logic_vector(1641,11); WHEN "0110101110" => manhi <= conv_std_logic_vector(4738202,24); manlo <= conv_std_logic_vector(195793257,28); exponent <= conv_std_logic_vector(1643,11); WHEN "0110101111" => manhi <= conv_std_logic_vector(12465269,24); manlo <= conv_std_logic_vector(236730454,28); exponent <= conv_std_logic_vector(1644,11); WHEN "0110110000" => manhi <= conv_std_logic_vector(3095113,24); manlo <= conv_std_logic_vector(133661452,28); exponent <= conv_std_logic_vector(1646,11); WHEN "0110110001" => manhi <= conv_std_logic_vector(10232080,24); manlo <= conv_std_logic_vector(21926822,28); exponent <= conv_std_logic_vector(1647,11); WHEN "0110110010" => manhi <= conv_std_logic_vector(1577503,24); manlo <= conv_std_logic_vector(183764948,28); exponent <= conv_std_logic_vector(1649,11); WHEN "0110110011" => manhi <= conv_std_logic_vector(8169434,24); manlo <= conv_std_logic_vector(132210812,28); exponent <= conv_std_logic_vector(1650,11); WHEN "0110110100" => manhi <= conv_std_logic_vector(175790,24); manlo <= conv_std_logic_vector(182183516,28); exponent <= conv_std_logic_vector(1652,11); WHEN "0110110101" => manhi <= conv_std_logic_vector(6264308,24); manlo <= conv_std_logic_vector(267417858,28); exponent <= conv_std_logic_vector(1653,11); WHEN "0110110110" => manhi <= conv_std_logic_vector(14539463,24); manlo <= conv_std_logic_vector(93573944,28); exponent <= conv_std_logic_vector(1654,11); WHEN "0110110111" => manhi <= conv_std_logic_vector(4504674,24); manlo <= conv_std_logic_vector(26907375,28); exponent <= conv_std_logic_vector(1656,11); WHEN "0110111000" => manhi <= conv_std_logic_vector(12147871,24); manlo <= conv_std_logic_vector(152302066,28); exponent <= conv_std_logic_vector(1657,11); WHEN "0110111001" => manhi <= conv_std_logic_vector(2879418,24); manlo <= conv_std_logic_vector(263131635,28); exponent <= conv_std_logic_vector(1659,11); WHEN "0110111010" => manhi <= conv_std_logic_vector(9938920,24); manlo <= conv_std_logic_vector(224874222,28); exponent <= conv_std_logic_vector(1660,11); WHEN "0110111011" => manhi <= conv_std_logic_vector(1378281,24); manlo <= conv_std_logic_vector(86745210,28); exponent <= conv_std_logic_vector(1662,11); WHEN "0110111100" => manhi <= conv_std_logic_vector(7898663,24); manlo <= conv_std_logic_vector(61761420,28); exponent <= conv_std_logic_vector(1663,11); WHEN "0110111101" => manhi <= conv_std_logic_vector(16760781,24); manlo <= conv_std_logic_vector(15082626,28); exponent <= conv_std_logic_vector(1664,11); WHEN "0110111110" => manhi <= conv_std_logic_vector(6014215,24); manlo <= conv_std_logic_vector(265801199,28); exponent <= conv_std_logic_vector(1666,11); WHEN "0110111111" => manhi <= conv_std_logic_vector(14199551,24); manlo <= conv_std_logic_vector(191056853,28); exponent <= conv_std_logic_vector(1667,11); WHEN "0111000000" => manhi <= conv_std_logic_vector(4273680,24); manlo <= conv_std_logic_vector(52024524,28); exponent <= conv_std_logic_vector(1669,11); WHEN "0111000001" => manhi <= conv_std_logic_vector(11833918,24); manlo <= conv_std_logic_vector(80047690,28); exponent <= conv_std_logic_vector(1670,11); WHEN "0111000010" => manhi <= conv_std_logic_vector(2666065,24); manlo <= conv_std_logic_vector(164712049,28); exponent <= conv_std_logic_vector(1672,11); WHEN "0111000011" => manhi <= conv_std_logic_vector(9648943,24); manlo <= conv_std_logic_vector(147084012,28); exponent <= conv_std_logic_vector(1673,11); WHEN "0111000100" => manhi <= conv_std_logic_vector(1181221,24); manlo <= conv_std_logic_vector(86912647,28); exponent <= conv_std_logic_vector(1675,11); WHEN "0111000101" => manhi <= conv_std_logic_vector(7630830,24); manlo <= conv_std_logic_vector(247596521,28); exponent <= conv_std_logic_vector(1676,11); WHEN "0111000110" => manhi <= conv_std_logic_vector(16396759,24); manlo <= conv_std_logic_vector(56002502,28); exponent <= conv_std_logic_vector(1677,11); WHEN "0111000111" => manhi <= conv_std_logic_vector(5766837,24); manlo <= conv_std_logic_vector(133369322,28); exponent <= conv_std_logic_vector(1679,11); WHEN "0111001000" => manhi <= conv_std_logic_vector(13863329,24); manlo <= conv_std_logic_vector(128884889,28); exponent <= conv_std_logic_vector(1680,11); WHEN "0111001001" => manhi <= conv_std_logic_vector(4045193,24); manlo <= conv_std_logic_vector(133729186,28); exponent <= conv_std_logic_vector(1682,11); WHEN "0111001010" => manhi <= conv_std_logic_vector(11523372,24); manlo <= conv_std_logic_vector(183024104,28); exponent <= conv_std_logic_vector(1683,11); WHEN "0111001011" => manhi <= conv_std_logic_vector(2455027,24); manlo <= conv_std_logic_vector(264977965,28); exponent <= conv_std_logic_vector(1685,11); WHEN "0111001100" => manhi <= conv_std_logic_vector(9362113,24); manlo <= conv_std_logic_vector(181285013,28); exponent <= conv_std_logic_vector(1686,11); WHEN "0111001101" => manhi <= conv_std_logic_vector(986300,24); manlo <= conv_std_logic_vector(58020653,28); exponent <= conv_std_logic_vector(1688,11); WHEN "0111001110" => manhi <= conv_std_logic_vector(7365905,24); manlo <= conv_std_logic_vector(179835810,28); exponent <= conv_std_logic_vector(1689,11); WHEN "0111001111" => manhi <= conv_std_logic_vector(16036688,24); manlo <= conv_std_logic_vector(123168298,28); exponent <= conv_std_logic_vector(1690,11); WHEN "0111010000" => manhi <= conv_std_logic_vector(5522144,24); manlo <= conv_std_logic_vector(14176725,28); exponent <= conv_std_logic_vector(1692,11); WHEN "0111010001" => manhi <= conv_std_logic_vector(13530756,24); manlo <= conv_std_logic_vector(163453775,28); exponent <= conv_std_logic_vector(1693,11); WHEN "0111010010" => manhi <= conv_std_logic_vector(3819186,24); manlo <= conv_std_logic_vector(214764608,28); exponent <= conv_std_logic_vector(1695,11); WHEN "0111010011" => manhi <= conv_std_logic_vector(11216197,24); manlo <= conv_std_logic_vector(196364225,28); exponent <= conv_std_logic_vector(1696,11); WHEN "0111010100" => manhi <= conv_std_logic_vector(2246280,24); manlo <= conv_std_logic_vector(259235483,28); exponent <= conv_std_logic_vector(1698,11); WHEN "0111010101" => manhi <= conv_std_logic_vector(9078397,24); manlo <= conv_std_logic_vector(15526664,28); exponent <= conv_std_logic_vector(1699,11); WHEN "0111010110" => manhi <= conv_std_logic_vector(793494,24); manlo <= conv_std_logic_vector(210641201,28); exponent <= conv_std_logic_vector(1701,11); WHEN "0111010111" => manhi <= conv_std_logic_vector(7103855,24); manlo <= conv_std_logic_vector(246847656,28); exponent <= conv_std_logic_vector(1702,11); WHEN "0111011000" => manhi <= conv_std_logic_vector(15680525,24); manlo <= conv_std_logic_vector(247378795,28); exponent <= conv_std_logic_vector(1703,11); WHEN "0111011001" => manhi <= conv_std_logic_vector(5280106,24); manlo <= conv_std_logic_vector(138122391,28); exponent <= conv_std_logic_vector(1705,11); WHEN "0111011010" => manhi <= conv_std_logic_vector(13201793,24); manlo <= conv_std_logic_vector(130963079,28); exponent <= conv_std_logic_vector(1706,11); WHEN "0111011011" => manhi <= conv_std_logic_vector(3595633,24); manlo <= conv_std_logic_vector(48727293,28); exponent <= conv_std_logic_vector(1708,11); WHEN "0111011100" => manhi <= conv_std_logic_vector(10912356,24); manlo <= conv_std_logic_vector(231400966,28); exponent <= conv_std_logic_vector(1709,11); WHEN "0111011101" => manhi <= conv_std_logic_vector(2039799,24); manlo <= conv_std_logic_vector(184459756,28); exponent <= conv_std_logic_vector(1711,11); WHEN "0111011110" => manhi <= conv_std_logic_vector(8797759,24); manlo <= conv_std_logic_vector(242699544,28); exponent <= conv_std_logic_vector(1712,11); WHEN "0111011111" => manhi <= conv_std_logic_vector(602782,24); manlo <= conv_std_logic_vector(17680793,28); exponent <= conv_std_logic_vector(1714,11); WHEN "0111100000" => manhi <= conv_std_logic_vector(6844650,24); manlo <= conv_std_logic_vector(123627565,28); exponent <= conv_std_logic_vector(1715,11); WHEN "0111100001" => manhi <= conv_std_logic_vector(15328229,24); manlo <= conv_std_logic_vector(47512453,28); exponent <= conv_std_logic_vector(1716,11); WHEN "0111100010" => manhi <= conv_std_logic_vector(5040696,24); manlo <= conv_std_logic_vector(14711664,28); exponent <= conv_std_logic_vector(1718,11); WHEN "0111100011" => manhi <= conv_std_logic_vector(12876400,24); manlo <= conv_std_logic_vector(251456186,28); exponent <= conv_std_logic_vector(1719,11); WHEN "0111100100" => manhi <= conv_std_logic_vector(3374506,24); manlo <= conv_std_logic_vector(4512772,28); exponent <= conv_std_logic_vector(1721,11); WHEN "0111100101" => manhi <= conv_std_logic_vector(10611813,24); manlo <= conv_std_logic_vector(237626642,28); exponent <= conv_std_logic_vector(1722,11); WHEN "0111100110" => manhi <= conv_std_logic_vector(1835559,24); manlo <= conv_std_logic_vector(150064655,28); exponent <= conv_std_logic_vector(1724,11); WHEN "0111100111" => manhi <= conv_std_logic_vector(8520168,24); manlo <= conv_std_logic_vector(211971382,28); exponent <= conv_std_logic_vector(1725,11); WHEN "0111101000" => manhi <= conv_std_logic_vector(414139,24); manlo <= conv_std_logic_vector(92694471,28); exponent <= conv_std_logic_vector(1727,11); WHEN "0111101001" => manhi <= conv_std_logic_vector(6588258,24); manlo <= conv_std_logic_vector(112977613,28); exponent <= conv_std_logic_vector(1728,11); WHEN "0111101010" => manhi <= conv_std_logic_vector(14979756,24); manlo <= conv_std_logic_vector(71348470,28); exponent <= conv_std_logic_vector(1729,11); WHEN "0111101011" => manhi <= conv_std_logic_vector(4803884,24); manlo <= conv_std_logic_vector(42747344,28); exponent <= conv_std_logic_vector(1731,11); WHEN "0111101100" => manhi <= conv_std_logic_vector(12554540,24); manlo <= conv_std_logic_vector(53825836,28); exponent <= conv_std_logic_vector(1732,11); WHEN "0111101101" => manhi <= conv_std_logic_vector(3155778,24); manlo <= conv_std_logic_vector(260157975,28); exponent <= conv_std_logic_vector(1734,11); WHEN "0111101110" => manhi <= conv_std_logic_vector(10314533,24); manlo <= conv_std_logic_vector(1535990,28); exponent <= conv_std_logic_vector(1735,11); WHEN "0111101111" => manhi <= conv_std_logic_vector(1633536,24); manlo <= conv_std_logic_vector(68681060,28); exponent <= conv_std_logic_vector(1737,11); WHEN "0111110000" => manhi <= conv_std_logic_vector(8245590,24); manlo <= conv_std_logic_vector(175202070,28); exponent <= conv_std_logic_vector(1738,11); WHEN "0111110001" => manhi <= conv_std_logic_vector(227544,24); manlo <= conv_std_logic_vector(41675965,28); exponent <= conv_std_logic_vector(1740,11); WHEN "0111110010" => manhi <= conv_std_logic_vector(6334649,24); manlo <= conv_std_logic_vector(70777607,28); exponent <= conv_std_logic_vector(1741,11); WHEN "0111110011" => manhi <= conv_std_logic_vector(14635065,24); manlo <= conv_std_logic_vector(183612561,28); exponent <= conv_std_logic_vector(1742,11); WHEN "0111110100" => manhi <= conv_std_logic_vector(4569642,24); manlo <= conv_std_logic_vector(167240760,28); exponent <= conv_std_logic_vector(1744,11); WHEN "0111110101" => manhi <= conv_std_logic_vector(12236172,24); manlo <= conv_std_logic_vector(253623266,28); exponent <= conv_std_logic_vector(1745,11); WHEN "0111110110" => manhi <= conv_std_logic_vector(2939425,24); manlo <= conv_std_logic_vector(265128301,28); exponent <= conv_std_logic_vector(1747,11); WHEN "0111110111" => manhi <= conv_std_logic_vector(10020478,24); manlo <= conv_std_logic_vector(219223569,28); exponent <= conv_std_logic_vector(1748,11); WHEN "0111111000" => manhi <= conv_std_logic_vector(1433705,24); manlo <= conv_std_logic_vector(192250058,28); exponent <= conv_std_logic_vector(1750,11); WHEN "0111111001" => manhi <= conv_std_logic_vector(7973992,24); manlo <= conv_std_logic_vector(212144821,28); exponent <= conv_std_logic_vector(1751,11); WHEN "0111111010" => manhi <= conv_std_logic_vector(42974,24); manlo <= conv_std_logic_vector(72952107,28); exponent <= conv_std_logic_vector(1753,11); WHEN "0111111011" => manhi <= conv_std_logic_vector(6083792,24); manlo <= conv_std_logic_vector(210315148,28); exponent <= conv_std_logic_vector(1754,11); WHEN "0111111100" => manhi <= conv_std_logic_vector(14294116,24); manlo <= conv_std_logic_vector(101520926,28); exponent <= conv_std_logic_vector(1755,11); WHEN "0111111101" => manhi <= conv_std_logic_vector(4337943,24); manlo <= conv_std_logic_vector(146945490,28); exponent <= conv_std_logic_vector(1757,11); WHEN "0111111110" => manhi <= conv_std_logic_vector(11921261,24); manlo <= conv_std_logic_vector(67478049,28); exponent <= conv_std_logic_vector(1758,11); WHEN "0111111111" => manhi <= conv_std_logic_vector(2725421,24); manlo <= conv_std_logic_vector(81662013,28); exponent <= conv_std_logic_vector(1760,11); WHEN "1000000000" => manhi <= conv_std_logic_vector(9729616,24); manlo <= conv_std_logic_vector(79332654,28); exponent <= conv_std_logic_vector(1761,11); WHEN "1000000001" => manhi <= conv_std_logic_vector(1236044,24); manlo <= conv_std_logic_vector(37511845,28); exponent <= conv_std_logic_vector(1763,11); WHEN "1000000010" => manhi <= conv_std_logic_vector(7705342,24); manlo <= conv_std_logic_vector(229400607,28); exponent <= conv_std_logic_vector(1764,11); WHEN "1000000011" => manhi <= conv_std_logic_vector(16498031,24); manlo <= conv_std_logic_vector(113896411,28); exponent <= conv_std_logic_vector(1765,11); WHEN "1000000100" => manhi <= conv_std_logic_vector(5835659,24); manlo <= conv_std_logic_vector(27578100,28); exponent <= conv_std_logic_vector(1767,11); WHEN "1000000101" => manhi <= conv_std_logic_vector(13956867,24); manlo <= conv_std_logic_vector(198774093,28); exponent <= conv_std_logic_vector(1768,11); WHEN "1000000110" => manhi <= conv_std_logic_vector(4108759,24); manlo <= conv_std_logic_vector(90336304,28); exponent <= conv_std_logic_vector(1770,11); WHEN "1000000111" => manhi <= conv_std_logic_vector(11609767,24); manlo <= conv_std_logic_vector(164675818,28); exponent <= conv_std_logic_vector(1771,11); WHEN "1000001000" => manhi <= conv_std_logic_vector(2513739,24); manlo <= conv_std_logic_vector(115510945,28); exponent <= conv_std_logic_vector(1773,11); WHEN "1000001001" => manhi <= conv_std_logic_vector(9441910,24); manlo <= conv_std_logic_vector(214725537,28); exponent <= conv_std_logic_vector(1774,11); WHEN "1000001010" => manhi <= conv_std_logic_vector(1040527,24); manlo <= conv_std_logic_vector(264292986,28); exponent <= conv_std_logic_vector(1776,11); WHEN "1000001011" => manhi <= conv_std_logic_vector(7439608,24); manlo <= conv_std_logic_vector(227819416,28); exponent <= conv_std_logic_vector(1777,11); WHEN "1000001100" => manhi <= conv_std_logic_vector(16136861,24); manlo <= conv_std_logic_vector(124712281,28); exponent <= conv_std_logic_vector(1778,11); WHEN "1000001101" => manhi <= conv_std_logic_vector(5590218,24); manlo <= conv_std_logic_vector(179347558,28); exponent <= conv_std_logic_vector(1780,11); WHEN "1000001110" => manhi <= conv_std_logic_vector(13623279,24); manlo <= conv_std_logic_vector(162081347,28); exponent <= conv_std_logic_vector(1781,11); WHEN "1000001111" => manhi <= conv_std_logic_vector(3882062,24); manlo <= conv_std_logic_vector(186291443,28); exponent <= conv_std_logic_vector(1783,11); WHEN "1000010000" => manhi <= conv_std_logic_vector(11301654,24); manlo <= conv_std_logic_vector(250040022,28); exponent <= conv_std_logic_vector(1784,11); WHEN "1000010001" => manhi <= conv_std_logic_vector(2304355,24); manlo <= conv_std_logic_vector(41383777,28); exponent <= conv_std_logic_vector(1786,11); WHEN "1000010010" => manhi <= conv_std_logic_vector(9157328,24); manlo <= conv_std_logic_vector(17021400,28); exponent <= conv_std_logic_vector(1787,11); WHEN "1000010011" => manhi <= conv_std_logic_vector(847133,24); manlo <= conv_std_logic_vector(258834653,28); exponent <= conv_std_logic_vector(1789,11); WHEN "1000010100" => manhi <= conv_std_logic_vector(7176759,24); manlo <= conv_std_logic_vector(33041815,28); exponent <= conv_std_logic_vector(1790,11); WHEN "1000010101" => manhi <= conv_std_logic_vector(15779611,24); manlo <= conv_std_logic_vector(174007449,28); exponent <= conv_std_logic_vector(1791,11); WHEN "1000010110" => manhi <= conv_std_logic_vector(5347442,24); manlo <= conv_std_logic_vector(66333886,28); exponent <= conv_std_logic_vector(1793,11); WHEN "1000010111" => manhi <= conv_std_logic_vector(13293312,24); manlo <= conv_std_logic_vector(63618366,28); exponent <= conv_std_logic_vector(1794,11); WHEN "1000011000" => manhi <= conv_std_logic_vector(3657826,24); manlo <= conv_std_logic_vector(166348998,28); exponent <= conv_std_logic_vector(1796,11); WHEN "1000011001" => manhi <= conv_std_logic_vector(10996886,24); manlo <= conv_std_logic_vector(136487624,28); exponent <= conv_std_logic_vector(1797,11); WHEN "1000011010" => manhi <= conv_std_logic_vector(2097243,24); manlo <= conv_std_logic_vector(144317262,28); exponent <= conv_std_logic_vector(1799,11); WHEN "1000011011" => manhi <= conv_std_logic_vector(8875834,24); manlo <= conv_std_logic_vector(51419886,28); exponent <= conv_std_logic_vector(1800,11); WHEN "1000011100" => manhi <= conv_std_logic_vector(655839,24); manlo <= conv_std_logic_vector(12096311,28); exponent <= conv_std_logic_vector(1802,11); WHEN "1000011101" => manhi <= conv_std_logic_vector(6916762,24); manlo <= conv_std_logic_vector(99793437,28); exponent <= conv_std_logic_vector(1803,11); WHEN "1000011110" => manhi <= conv_std_logic_vector(15426239,24); manlo <= conv_std_logic_vector(114334116,28); exponent <= conv_std_logic_vector(1804,11); WHEN "1000011111" => manhi <= conv_std_logic_vector(5107300,24); manlo <= conv_std_logic_vector(248161218,28); exponent <= conv_std_logic_vector(1806,11); WHEN "1000100000" => manhi <= conv_std_logic_vector(12966926,24); manlo <= conv_std_logic_vector(91321506,28); exponent <= conv_std_logic_vector(1807,11); WHEN "1000100001" => manhi <= conv_std_logic_vector(3436024,24); manlo <= conv_std_logic_vector(109150055,28); exponent <= conv_std_logic_vector(1809,11); WHEN "1000100010" => manhi <= conv_std_logic_vector(10695426,24); manlo <= conv_std_logic_vector(12291314,28); exponent <= conv_std_logic_vector(1810,11); WHEN "1000100011" => manhi <= conv_std_logic_vector(1892379,24); manlo <= conv_std_logic_vector(245137096,28); exponent <= conv_std_logic_vector(1812,11); WHEN "1000100100" => manhi <= conv_std_logic_vector(8597395,24); manlo <= conv_std_logic_vector(176569250,28); exponent <= conv_std_logic_vector(1813,11); WHEN "1000100101" => manhi <= conv_std_logic_vector(466620,24); manlo <= conv_std_logic_vector(119019308,28); exponent <= conv_std_logic_vector(1815,11); WHEN "1000100110" => manhi <= conv_std_logic_vector(6659587,24); manlo <= conv_std_logic_vector(168706814,28); exponent <= conv_std_logic_vector(1816,11); WHEN "1000100111" => manhi <= conv_std_logic_vector(15076702,24); manlo <= conv_std_logic_vector(190651618,28); exponent <= conv_std_logic_vector(1817,11); WHEN "1000101000" => manhi <= conv_std_logic_vector(4869766,24); manlo <= conv_std_logic_vector(26523901,28); exponent <= conv_std_logic_vector(1819,11); WHEN "1000101001" => manhi <= conv_std_logic_vector(12644083,24); manlo <= conv_std_logic_vector(10760420,28); exponent <= conv_std_logic_vector(1820,11); WHEN "1000101010" => manhi <= conv_std_logic_vector(3216629,24); manlo <= conv_std_logic_vector(171149379,28); exponent <= conv_std_logic_vector(1822,11); WHEN "1000101011" => manhi <= conv_std_logic_vector(10397237,24); manlo <= conv_std_logic_vector(171483537,28); exponent <= conv_std_logic_vector(1823,11); WHEN "1000101100" => manhi <= conv_std_logic_vector(1689739,24); manlo <= conv_std_logic_vector(236540182,28); exponent <= conv_std_logic_vector(1825,11); WHEN "1000101101" => manhi <= conv_std_logic_vector(8321979,24); manlo <= conv_std_logic_vector(80365386,28); exponent <= conv_std_logic_vector(1826,11); WHEN "1000101110" => manhi <= conv_std_logic_vector(279455,24); manlo <= conv_std_logic_vector(167185714,28); exponent <= conv_std_logic_vector(1828,11); WHEN "1000101111" => manhi <= conv_std_logic_vector(6405204,24); manlo <= conv_std_logic_vector(70637708,28); exponent <= conv_std_logic_vector(1829,11); WHEN "1000110000" => manhi <= conv_std_logic_vector(14730959,24); manlo <= conv_std_logic_vector(233674466,28); exponent <= conv_std_logic_vector(1830,11); WHEN "1000110001" => manhi <= conv_std_logic_vector(4634809,24); manlo <= conv_std_logic_vector(128626627,28); exponent <= conv_std_logic_vector(1832,11); WHEN "1000110010" => manhi <= conv_std_logic_vector(12324743,24); manlo <= conv_std_logic_vector(237637056,28); exponent <= conv_std_logic_vector(1833,11); WHEN "1000110011" => manhi <= conv_std_logic_vector(2999616,24); manlo <= conv_std_logic_vector(48899908,28); exponent <= conv_std_logic_vector(1835,11); WHEN "1000110100" => manhi <= conv_std_logic_vector(10102285,24); manlo <= conv_std_logic_vector(207402206,28); exponent <= conv_std_logic_vector(1836,11); WHEN "1000110101" => manhi <= conv_std_logic_vector(1489299,24); manlo <= conv_std_logic_vector(82314533,28); exponent <= conv_std_logic_vector(1838,11); WHEN "1000110110" => manhi <= conv_std_logic_vector(8049552,24); manlo <= conv_std_logic_vector(84197942,28); exponent <= conv_std_logic_vector(1839,11); WHEN "1000110111" => manhi <= conv_std_logic_vector(94322,24); manlo <= conv_std_logic_vector(78275083,28); exponent <= conv_std_logic_vector(1841,11); WHEN "1000111000" => manhi <= conv_std_logic_vector(6153581,24); manlo <= conv_std_logic_vector(262556746,28); exponent <= conv_std_logic_vector(1842,11); WHEN "1000111001" => manhi <= conv_std_logic_vector(14388969,24); manlo <= conv_std_logic_vector(195412276,28); exponent <= conv_std_logic_vector(1843,11); WHEN "1000111010" => manhi <= conv_std_logic_vector(4402403,24); manlo <= conv_std_logic_vector(21925377,28); exponent <= conv_std_logic_vector(1845,11); WHEN "1000111011" => manhi <= conv_std_logic_vector(12008870,24); manlo <= conv_std_logic_vector(225943576,28); exponent <= conv_std_logic_vector(1846,11); WHEN "1000111100" => manhi <= conv_std_logic_vector(2784958,24); manlo <= conv_std_logic_vector(51959162,28); exponent <= conv_std_logic_vector(1848,11); WHEN "1000111101" => manhi <= conv_std_logic_vector(9810535,24); manlo <= conv_std_logic_vector(85297068,28); exponent <= conv_std_logic_vector(1849,11); WHEN "1000111110" => manhi <= conv_std_logic_vector(1291034,24); manlo <= conv_std_logic_vector(85003113,28); exponent <= conv_std_logic_vector(1851,11); WHEN "1000111111" => manhi <= conv_std_logic_vector(7780082,24); manlo <= conv_std_logic_vector(68159752,28); exponent <= conv_std_logic_vector(1852,11); WHEN "1001000000" => manhi <= conv_std_logic_vector(16599612,24); manlo <= conv_std_logic_vector(214703512,28); exponent <= conv_std_logic_vector(1853,11); WHEN "1001000001" => manhi <= conv_std_logic_vector(5904690,24); manlo <= conv_std_logic_vector(215968023,28); exponent <= conv_std_logic_vector(1855,11); WHEN "1001000010" => manhi <= conv_std_logic_vector(14050691,24); manlo <= conv_std_logic_vector(147853227,28); exponent <= conv_std_logic_vector(1856,11); WHEN "1001000011" => manhi <= conv_std_logic_vector(4172519,24); manlo <= conv_std_logic_vector(60716388,28); exponent <= conv_std_logic_vector(1858,11); WHEN "1001000100" => manhi <= conv_std_logic_vector(11696426,24); manlo <= conv_std_logic_vector(77359100,28); exponent <= conv_std_logic_vector(1859,11); WHEN "1001000101" => manhi <= conv_std_logic_vector(2572630,24); manlo <= conv_std_logic_vector(28321055,28); exponent <= conv_std_logic_vector(1861,11); WHEN "1001000110" => manhi <= conv_std_logic_vector(9521951,24); manlo <= conv_std_logic_vector(141206574,28); exponent <= conv_std_logic_vector(1862,11); WHEN "1001000111" => manhi <= conv_std_logic_vector(1094921,24); manlo <= conv_std_logic_vector(79834212,28); exponent <= conv_std_logic_vector(1864,11); WHEN "1001001000" => manhi <= conv_std_logic_vector(7513537,24); manlo <= conv_std_logic_vector(6880382,28); exponent <= conv_std_logic_vector(1865,11); WHEN "1001001001" => manhi <= conv_std_logic_vector(16237340,24); manlo <= conv_std_logic_vector(73707069,28); exponent <= conv_std_logic_vector(1866,11); WHEN "1001001010" => manhi <= conv_std_logic_vector(5658501,24); manlo <= conv_std_logic_vector(26563701,28); exponent <= conv_std_logic_vector(1868,11); WHEN "1001001011" => manhi <= conv_std_logic_vector(13716085,24); manlo <= conv_std_logic_vector(13226359,28); exponent <= conv_std_logic_vector(1869,11); WHEN "1001001100" => manhi <= conv_std_logic_vector(3945130,24); manlo <= conv_std_logic_vector(143073903,28); exponent <= conv_std_logic_vector(1871,11); WHEN "1001001101" => manhi <= conv_std_logic_vector(11387373,24); manlo <= conv_std_logic_vector(3175990,28); exponent <= conv_std_logic_vector(1872,11); WHEN "1001001110" => manhi <= conv_std_logic_vector(2362606,24); manlo <= conv_std_logic_vector(168904878,28); exponent <= conv_std_logic_vector(1874,11); WHEN "1001001111" => manhi <= conv_std_logic_vector(9236500,24); manlo <= conv_std_logic_vector(7105104,28); exponent <= conv_std_logic_vector(1875,11); WHEN "1001010000" => manhi <= conv_std_logic_vector(900936,24); manlo <= conv_std_logic_vector(239272854,28); exponent <= conv_std_logic_vector(1877,11); WHEN "1001010001" => manhi <= conv_std_logic_vector(7249884,24); manlo <= conv_std_logic_vector(236935482,28); exponent <= conv_std_logic_vector(1878,11); WHEN "1001010010" => manhi <= conv_std_logic_vector(15878999,24); manlo <= conv_std_logic_vector(230836932,28); exponent <= conv_std_logic_vector(1879,11); WHEN "1001010011" => manhi <= conv_std_logic_vector(5414983,24); manlo <= conv_std_logic_vector(144840810,28); exponent <= conv_std_logic_vector(1881,11); WHEN "1001010100" => manhi <= conv_std_logic_vector(13385110,24); manlo <= conv_std_logic_vector(99584369,28); exponent <= conv_std_logic_vector(1882,11); WHEN "1001010101" => manhi <= conv_std_logic_vector(3720209,24); manlo <= conv_std_logic_vector(246845719,28); exponent <= conv_std_logic_vector(1884,11); WHEN "1001010110" => manhi <= conv_std_logic_vector(11081674,24); manlo <= conv_std_logic_vector(54674652,28); exponent <= conv_std_logic_vector(1885,11); WHEN "1001010111" => manhi <= conv_std_logic_vector(2154862,24); manlo <= conv_std_logic_vector(201440422,28); exponent <= conv_std_logic_vector(1887,11); WHEN "1001011000" => manhi <= conv_std_logic_vector(8954146,24); manlo <= conv_std_logic_vector(220416825,28); exponent <= conv_std_logic_vector(1888,11); WHEN "1001011001" => manhi <= conv_std_logic_vector(709057,24); manlo <= conv_std_logic_vector(266967657,28); exponent <= conv_std_logic_vector(1890,11); WHEN "1001011010" => manhi <= conv_std_logic_vector(6989094,24); manlo <= conv_std_logic_vector(113654547,28); exponent <= conv_std_logic_vector(1891,11); WHEN "1001011011" => manhi <= conv_std_logic_vector(15524548,24); manlo <= conv_std_logic_vector(235342013,28); exponent <= conv_std_logic_vector(1892,11); WHEN "1001011100" => manhi <= conv_std_logic_vector(5174109,24); manlo <= conv_std_logic_vector(32986511,28); exponent <= conv_std_logic_vector(1894,11); WHEN "1001011101" => manhi <= conv_std_logic_vector(13057728,24); manlo <= conv_std_logic_vector(25787653,28); exponent <= conv_std_logic_vector(1895,11); WHEN "1001011110" => manhi <= conv_std_logic_vector(3497730,24); manlo <= conv_std_logic_vector(160351868,28); exponent <= conv_std_logic_vector(1897,11); WHEN "1001011111" => manhi <= conv_std_logic_vector(10779293,24); manlo <= conv_std_logic_vector(121946709,28); exponent <= conv_std_logic_vector(1898,11); WHEN "1001100000" => manhi <= conv_std_logic_vector(1949373,24); manlo <= conv_std_logic_vector(194974600,28); exponent <= conv_std_logic_vector(1900,11); WHEN "1001100001" => manhi <= conv_std_logic_vector(8674858,24); manlo <= conv_std_logic_vector(75445083,28); exponent <= conv_std_logic_vector(1901,11); WHEN "1001100010" => manhi <= conv_std_logic_vector(519261,24); manlo <= conv_std_logic_vector(202318540,28); exponent <= conv_std_logic_vector(1903,11); WHEN "1001100011" => manhi <= conv_std_logic_vector(6731134,24); manlo <= conv_std_logic_vector(157600610,28); exponent <= conv_std_logic_vector(1904,11); WHEN "1001100100" => manhi <= conv_std_logic_vector(15173945,24); manlo <= conv_std_logic_vector(29256816,28); exponent <= conv_std_logic_vector(1905,11); WHEN "1001100101" => manhi <= conv_std_logic_vector(4935849,24); manlo <= conv_std_logic_vector(42999013,28); exponent <= conv_std_logic_vector(1907,11); WHEN "1001100110" => manhi <= conv_std_logic_vector(12733899,24); manlo <= conv_std_logic_vector(62421287,28); exponent <= conv_std_logic_vector(1908,11); WHEN "1001100111" => manhi <= conv_std_logic_vector(3277666,24); manlo <= conv_std_logic_vector(18399062,28); exponent <= conv_std_logic_vector(1910,11); WHEN "1001101000" => manhi <= conv_std_logic_vector(10480194,24); manlo <= conv_std_logic_vector(201166396,28); exponent <= conv_std_logic_vector(1911,11); WHEN "1001101001" => manhi <= conv_std_logic_vector(1746115,24); manlo <= conv_std_logic_vector(22209480,28); exponent <= conv_std_logic_vector(1913,11); WHEN "1001101010" => manhi <= conv_std_logic_vector(8398601,24); manlo <= conv_std_logic_vector(38216343,28); exponent <= conv_std_logic_vector(1914,11); WHEN "1001101011" => manhi <= conv_std_logic_vector(331525,24); manlo <= conv_std_logic_vector(151310615,28); exponent <= conv_std_logic_vector(1916,11); WHEN "1001101100" => manhi <= conv_std_logic_vector(6475974,24); manlo <= conv_std_logic_vector(174528998,28); exponent <= conv_std_logic_vector(1917,11); WHEN "1001101101" => manhi <= conv_std_logic_vector(14827146,24); manlo <= conv_std_logic_vector(214487191,28); exponent <= conv_std_logic_vector(1918,11); WHEN "1001101110" => manhi <= conv_std_logic_vector(4700175,24); manlo <= conv_std_logic_vector(73593076,28); exponent <= conv_std_logic_vector(1920,11); WHEN "1001101111" => manhi <= conv_std_logic_vector(12413585,24); manlo <= conv_std_logic_vector(56806573,28); exponent <= conv_std_logic_vector(1921,11); WHEN "1001110000" => manhi <= conv_std_logic_vector(3059990,24); manlo <= conv_std_logic_vector(32998071,28); exponent <= conv_std_logic_vector(1923,11); WHEN "1001110001" => manhi <= conv_std_logic_vector(10184342,24); manlo <= conv_std_logic_vector(125003687,28); exponent <= conv_std_logic_vector(1924,11); WHEN "1001110010" => manhi <= conv_std_logic_vector(1545062,24); manlo <= conv_std_logic_vector(164026180,28); exponent <= conv_std_logic_vector(1926,11); WHEN "1001110011" => manhi <= conv_std_logic_vector(8125342,24); manlo <= conv_std_logic_vector(134803968,28); exponent <= conv_std_logic_vector(1927,11); WHEN "1001110100" => manhi <= conv_std_logic_vector(145827,24); manlo <= conv_std_logic_vector(17356019,28); exponent <= conv_std_logic_vector(1929,11); WHEN "1001110101" => manhi <= conv_std_logic_vector(6223584,24); manlo <= conv_std_logic_vector(59711433,28); exponent <= conv_std_logic_vector(1930,11); WHEN "1001110110" => manhi <= conv_std_logic_vector(14484112,24); manlo <= conv_std_logic_vector(172427100,28); exponent <= conv_std_logic_vector(1931,11); WHEN "1001110111" => manhi <= conv_std_logic_vector(4467059,24); manlo <= conv_std_logic_vector(106163660,28); exponent <= conv_std_logic_vector(1933,11); WHEN "1001111000" => manhi <= conv_std_logic_vector(12096747,24); manlo <= conv_std_logic_vector(237074316,28); exponent <= conv_std_logic_vector(1934,11); WHEN "1001111001" => manhi <= conv_std_logic_vector(2844676,24); manlo <= conv_std_logic_vector(224090291,28); exponent <= conv_std_logic_vector(1936,11); WHEN "1001111010" => manhi <= conv_std_logic_vector(9891701,24); manlo <= conv_std_logic_vector(98356275,28); exponent <= conv_std_logic_vector(1937,11); WHEN "1001111011" => manhi <= conv_std_logic_vector(1346192,24); manlo <= conv_std_logic_vector(98098154,28); exponent <= conv_std_logic_vector(1939,11); WHEN "1001111100" => manhi <= conv_std_logic_vector(7855049,24); manlo <= conv_std_logic_vector(218711727,28); exponent <= conv_std_logic_vector(1940,11); WHEN "1001111101" => manhi <= conv_std_logic_vector(16701504,24); manlo <= conv_std_logic_vector(74899902,28); exponent <= conv_std_logic_vector(1941,11); WHEN "1001111110" => manhi <= conv_std_logic_vector(5973933,24); manlo <= conv_std_logic_vector(65399866,28); exponent <= conv_std_logic_vector(1943,11); WHEN "1001111111" => manhi <= conv_std_logic_vector(14144801,24); manlo <= conv_std_logic_vector(210121699,28); exponent <= conv_std_logic_vector(1944,11); WHEN "1010000000" => manhi <= conv_std_logic_vector(4236473,24); manlo <= conv_std_logic_vector(203888522,28); exponent <= conv_std_logic_vector(1946,11); WHEN "1010000001" => manhi <= conv_std_logic_vector(11783349,24); manlo <= conv_std_logic_vector(137203293,28); exponent <= conv_std_logic_vector(1947,11); WHEN "1010000010" => manhi <= conv_std_logic_vector(2631700,24); manlo <= conv_std_logic_vector(150283410,28); exponent <= conv_std_logic_vector(1949,11); WHEN "1010000011" => manhi <= conv_std_logic_vector(9602236,24); manlo <= conv_std_logic_vector(160352104,28); exponent <= conv_std_logic_vector(1950,11); WHEN "1010000100" => manhi <= conv_std_logic_vector(1149480,24); manlo <= conv_std_logic_vector(177173803,28); exponent <= conv_std_logic_vector(1952,11); WHEN "1010000101" => manhi <= conv_std_logic_vector(7587690,24); manlo <= conv_std_logic_vector(238268718,28); exponent <= conv_std_logic_vector(1953,11); WHEN "1010000110" => manhi <= conv_std_logic_vector(16338125,24); manlo <= conv_std_logic_vector(220749839,28); exponent <= conv_std_logic_vector(1954,11); WHEN "1010000111" => manhi <= conv_std_logic_vector(5726991,24); manlo <= conv_std_logic_vector(262994505,28); exponent <= conv_std_logic_vector(1956,11); WHEN "1010001000" => manhi <= conv_std_logic_vector(13809173,24); manlo <= conv_std_logic_vector(216783842,28); exponent <= conv_std_logic_vector(1957,11); WHEN "1010001001" => manhi <= conv_std_logic_vector(4008390,24); manlo <= conv_std_logic_vector(242405077,28); exponent <= conv_std_logic_vector(1959,11); WHEN "1010001010" => manhi <= conv_std_logic_vector(11473352,24); manlo <= conv_std_logic_vector(206426515,28); exponent <= conv_std_logic_vector(1960,11); WHEN "1010001011" => manhi <= conv_std_logic_vector(2421035,24); manlo <= conv_std_logic_vector(250208807,28); exponent <= conv_std_logic_vector(1962,11); WHEN "1010001100" => manhi <= conv_std_logic_vector(9315913,24); manlo <= conv_std_logic_vector(183235034,28); exponent <= conv_std_logic_vector(1963,11); WHEN "1010001101" => manhi <= conv_std_logic_vector(954904,24); manlo <= conv_std_logic_vector(17706469,28); exponent <= conv_std_logic_vector(1965,11); WHEN "1010001110" => manhi <= conv_std_logic_vector(7323233,24); manlo <= conv_std_logic_vector(235600136,28); exponent <= conv_std_logic_vector(1966,11); WHEN "1010001111" => manhi <= conv_std_logic_vector(15978691,24); manlo <= conv_std_logic_vector(128873524,28); exponent <= conv_std_logic_vector(1967,11); WHEN "1010010000" => manhi <= conv_std_logic_vector(5482731,24); manlo <= conv_std_logic_vector(5222268,28); exponent <= conv_std_logic_vector(1969,11); WHEN "1010010001" => manhi <= conv_std_logic_vector(13477188,24); manlo <= conv_std_logic_vector(199372940,28); exponent <= conv_std_logic_vector(1970,11); WHEN "1010010010" => manhi <= conv_std_logic_vector(3782783,24); manlo <= conv_std_logic_vector(177367827,28); exponent <= conv_std_logic_vector(1972,11); WHEN "1010010011" => manhi <= conv_std_logic_vector(11166720,24); manlo <= conv_std_logic_vector(197425116,28); exponent <= conv_std_logic_vector(1973,11); WHEN "1010010100" => manhi <= conv_std_logic_vector(2212657,24); manlo <= conv_std_logic_vector(231097832,28); exponent <= conv_std_logic_vector(1975,11); WHEN "1010010101" => manhi <= conv_std_logic_vector(9032698,24); manlo <= conv_std_logic_vector(139698050,28); exponent <= conv_std_logic_vector(1976,11); WHEN "1010010110" => manhi <= conv_std_logic_vector(762439,24); manlo <= conv_std_logic_vector(109718127,28); exponent <= conv_std_logic_vector(1978,11); WHEN "1010010111" => manhi <= conv_std_logic_vector(7061647,24); manlo <= conv_std_logic_vector(77173752,28); exponent <= conv_std_logic_vector(1979,11); WHEN "1010011000" => manhi <= conv_std_logic_vector(15623158,24); manlo <= conv_std_logic_vector(118851961,28); exponent <= conv_std_logic_vector(1980,11); WHEN "1010011001" => manhi <= conv_std_logic_vector(5241121,24); manlo <= conv_std_logic_vector(72680114,28); exponent <= conv_std_logic_vector(1982,11); WHEN "1010011010" => manhi <= conv_std_logic_vector(13148807,24); manlo <= conv_std_logic_vector(12881486,28); exponent <= conv_std_logic_vector(1983,11); WHEN "1010011011" => manhi <= conv_std_logic_vector(3559625,24); manlo <= conv_std_logic_vector(43579850,28); exponent <= conv_std_logic_vector(1985,11); WHEN "1010011100" => manhi <= conv_std_logic_vector(10863416,24); manlo <= conv_std_logic_vector(238889758,28); exponent <= conv_std_logic_vector(1986,11); WHEN "1010011101" => manhi <= conv_std_logic_vector(2006541,24); manlo <= conv_std_logic_vector(141721451,28); exponent <= conv_std_logic_vector(1988,11); WHEN "1010011110" => manhi <= conv_std_logic_vector(8752557,24); manlo <= conv_std_logic_vector(101792997,28); exponent <= conv_std_logic_vector(1989,11); WHEN "1010011111" => manhi <= conv_std_logic_vector(572063,24); manlo <= conv_std_logic_vector(205445723,28); exponent <= conv_std_logic_vector(1991,11); WHEN "1010100000" => manhi <= conv_std_logic_vector(6802899,24); manlo <= conv_std_logic_vector(258099270,28); exponent <= conv_std_logic_vector(1992,11); WHEN "1010100001" => manhi <= conv_std_logic_vector(15271484,24); manlo <= conv_std_logic_vector(98124990,28); exponent <= conv_std_logic_vector(1993,11); WHEN "1010100010" => manhi <= conv_std_logic_vector(5002133,24); manlo <= conv_std_logic_vector(256985826,28); exponent <= conv_std_logic_vector(1995,11); WHEN "1010100011" => manhi <= conv_std_logic_vector(12823989,24); manlo <= conv_std_logic_vector(164377270,28); exponent <= conv_std_logic_vector(1996,11); WHEN "1010100100" => manhi <= conv_std_logic_vector(3338888,24); manlo <= conv_std_logic_vector(222569178,28); exponent <= conv_std_logic_vector(1998,11); WHEN "1010100101" => manhi <= conv_std_logic_vector(10563405,24); manlo <= conv_std_logic_vector(29046646,28); exponent <= conv_std_logic_vector(1999,11); WHEN "1010100110" => manhi <= conv_std_logic_vector(1802662,24); manlo <= conv_std_logic_vector(103161316,28); exponent <= conv_std_logic_vector(2001,11); WHEN "1010100111" => manhi <= conv_std_logic_vector(8475456,24); manlo <= conv_std_logic_vector(239852126,28); exponent <= conv_std_logic_vector(2002,11); WHEN "1010101000" => manhi <= conv_std_logic_vector(383754,24); manlo <= conv_std_logic_vector(123914668,28); exponent <= conv_std_logic_vector(2004,11); WHEN "1010101001" => manhi <= conv_std_logic_vector(6546961,24); manlo <= conv_std_logic_vector(22084044,28); exponent <= conv_std_logic_vector(2005,11); WHEN "1010101010" => manhi <= conv_std_logic_vector(14923627,24); manlo <= conv_std_logic_vector(97508377,28); exponent <= conv_std_logic_vector(2006,11); WHEN "1010101011" => manhi <= conv_std_logic_vector(4765740,24); manlo <= conv_std_logic_vector(165164368,28); exponent <= conv_std_logic_vector(2008,11); WHEN "1010101100" => manhi <= conv_std_logic_vector(12502697,24); manlo <= conv_std_logic_vector(201140216,28); exponent <= conv_std_logic_vector(2009,11); WHEN "1010101101" => manhi <= conv_std_logic_vector(3120548,24); manlo <= conv_std_logic_vector(99561759,28); exponent <= conv_std_logic_vector(2011,11); WHEN "1010101110" => manhi <= conv_std_logic_vector(10266649,24); manlo <= conv_std_logic_vector(176679877,28); exponent <= conv_std_logic_vector(2012,11); WHEN "1010101111" => manhi <= conv_std_logic_vector(1600996,24); manlo <= conv_std_logic_vector(39589446,28); exponent <= conv_std_logic_vector(2014,11); WHEN "1010110000" => manhi <= conv_std_logic_vector(8201364,24); manlo <= conv_std_logic_vector(16114999,28); exponent <= conv_std_logic_vector(2015,11); WHEN "1010110001" => manhi <= conv_std_logic_vector(197489,24); manlo <= conv_std_logic_vector(18649371,28); exponent <= conv_std_logic_vector(2017,11); WHEN "1010110010" => manhi <= conv_std_logic_vector(6293800,24); manlo <= conv_std_logic_vector(44802372,28); exponent <= conv_std_logic_vector(2018,11); WHEN "1010110011" => manhi <= conv_std_logic_vector(14579546,24); manlo <= conv_std_logic_vector(1419236,28); exponent <= conv_std_logic_vector(2019,11); WHEN "1010110100" => manhi <= conv_std_logic_vector(4531913,24); manlo <= conv_std_logic_vector(24044223,28); exponent <= conv_std_logic_vector(2021,11); WHEN "1010110101" => manhi <= conv_std_logic_vector(12184893,24); manlo <= conv_std_logic_vector(51602800,28); exponent <= conv_std_logic_vector(2022,11); WHEN "1010110110" => manhi <= conv_std_logic_vector(2904577,24); manlo <= conv_std_logic_vector(210124577,28); exponent <= conv_std_logic_vector(2024,11); WHEN "1010110111" => manhi <= conv_std_logic_vector(9973115,24); manlo <= conv_std_logic_vector(52505388,28); exponent <= conv_std_logic_vector(2025,11); WHEN "1010111000" => manhi <= conv_std_logic_vector(1401518,24); manlo <= conv_std_logic_vector(214362802,28); exponent <= conv_std_logic_vector(2027,11); WHEN "1010111001" => manhi <= conv_std_logic_vector(7930246,24); manlo <= conv_std_logic_vector(62721516,28); exponent <= conv_std_logic_vector(2028,11); WHEN "1010111010" => manhi <= conv_std_logic_vector(13245,24); manlo <= conv_std_logic_vector(108520727,28); exponent <= conv_std_logic_vector(2030,11); WHEN "1010111011" => manhi <= conv_std_logic_vector(6043387,24); manlo <= conv_std_logic_vector(17001813,28); exponent <= conv_std_logic_vector(2031,11); WHEN "1010111100" => manhi <= conv_std_logic_vector(14239199,24); manlo <= conv_std_logic_vector(83422350,28); exponent <= conv_std_logic_vector(2032,11); WHEN "1010111101" => manhi <= conv_std_logic_vector(4300623,24); manlo <= conv_std_logic_vector(142486326,28); exponent <= conv_std_logic_vector(2034,11); WHEN "1010111110" => manhi <= conv_std_logic_vector(11870538,24); manlo <= conv_std_logic_vector(24126621,28); exponent <= conv_std_logic_vector(2035,11); WHEN "1010111111" => manhi <= conv_std_logic_vector(2690951,24); manlo <= conv_std_logic_vector(91850592,28); exponent <= conv_std_logic_vector(2037,11); WHEN "1011000000" => manhi <= conv_std_logic_vector(9682766,24); manlo <= conv_std_logic_vector(203960059,28); exponent <= conv_std_logic_vector(2038,11); WHEN "1011000001" => manhi <= conv_std_logic_vector(1204206,24); manlo <= conv_std_logic_vector(155513539,28); exponent <= conv_std_logic_vector(2040,11); WHEN "1011000010" => manhi <= conv_std_logic_vector(7662071,24); manlo <= conv_std_logic_vector(33184566,28); exponent <= conv_std_logic_vector(2041,11); WHEN "1011000011" => manhi <= conv_std_logic_vector(16439219,24); manlo <= conv_std_logic_vector(11896414,28); exponent <= conv_std_logic_vector(2042,11); WHEN "1011000100" => manhi <= conv_std_logic_vector(5795691,24); manlo <= conv_std_logic_vector(254151921,28); exponent <= conv_std_logic_vector(2044,11); WHEN "1011000101" => manhi <= conv_std_logic_vector(13902546,24); manlo <= conv_std_logic_vector(199613595,28); exponent <= conv_std_logic_vector(2045,11); WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_explutpos IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_explutpos; ARCHITECTURE rtl OF dp_explutpos IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(1023,11); WHEN "0000000001" => manhi <= conv_std_logic_vector(6025384,24); manlo <= conv_std_logic_vector(185882474,28); exponent <= conv_std_logic_vector(1024,11); WHEN "0000000010" => manhi <= conv_std_logic_vector(14214731,24); manlo <= conv_std_logic_vector(148168110,28); exponent <= conv_std_logic_vector(1025,11); WHEN "0000000011" => manhi <= conv_std_logic_vector(4283995,24); manlo <= conv_std_logic_vector(258978054,28); exponent <= conv_std_logic_vector(1027,11); WHEN "0000000100" => manhi <= conv_std_logic_vector(11847938,24); manlo <= conv_std_logic_vector(237451864,28); exponent <= conv_std_logic_vector(1028,11); WHEN "0000000101" => manhi <= conv_std_logic_vector(2675593,24); manlo <= conv_std_logic_vector(158348175,28); exponent <= conv_std_logic_vector(1030,11); WHEN "0000000110" => manhi <= conv_std_logic_vector(9661893,24); manlo <= conv_std_logic_vector(110149775,28); exponent <= conv_std_logic_vector(1031,11); WHEN "0000000111" => manhi <= conv_std_logic_vector(1190021,24); manlo <= conv_std_logic_vector(179232170,28); exponent <= conv_std_logic_vector(1033,11); WHEN "0000001000" => manhi <= conv_std_logic_vector(7642791,24); manlo <= conv_std_logic_vector(222760046,28); exponent <= conv_std_logic_vector(1034,11); WHEN "0000001001" => manhi <= conv_std_logic_vector(16413015,24); manlo <= conv_std_logic_vector(205983618,28); exponent <= conv_std_logic_vector(1035,11); WHEN "0000001010" => manhi <= conv_std_logic_vector(5777884,24); manlo <= conv_std_logic_vector(261424480,28); exponent <= conv_std_logic_vector(1037,11); WHEN "0000001011" => manhi <= conv_std_logic_vector(13878344,24); manlo <= conv_std_logic_vector(149835647,28); exponent <= conv_std_logic_vector(1038,11); WHEN "0000001100" => manhi <= conv_std_logic_vector(4055397,24); manlo <= conv_std_logic_vector(80968858,28); exponent <= conv_std_logic_vector(1040,11); WHEN "0000001101" => manhi <= conv_std_logic_vector(11537241,24); manlo <= conv_std_logic_vector(23775573,28); exponent <= conv_std_logic_vector(1041,11); WHEN "0000001110" => manhi <= conv_std_logic_vector(2464452,24); manlo <= conv_std_logic_vector(146736599,28); exponent <= conv_std_logic_vector(1043,11); WHEN "0000001111" => manhi <= conv_std_logic_vector(9374922,24); manlo <= conv_std_logic_vector(263006855,28); exponent <= conv_std_logic_vector(1044,11); WHEN "0000010000" => manhi <= conv_std_logic_vector(995005,24); manlo <= conv_std_logic_vector(11010080,28); exponent <= conv_std_logic_vector(1046,11); WHEN "0000010001" => manhi <= conv_std_logic_vector(7377736,24); manlo <= conv_std_logic_vector(202286329,28); exponent <= conv_std_logic_vector(1047,11); WHEN "0000010010" => manhi <= conv_std_logic_vector(16052768,24); manlo <= conv_std_logic_vector(152649917,28); exponent <= conv_std_logic_vector(1048,11); WHEN "0000010011" => manhi <= conv_std_logic_vector(5533071,24); manlo <= conv_std_logic_vector(166536930,28); exponent <= conv_std_logic_vector(1050,11); WHEN "0000010100" => manhi <= conv_std_logic_vector(13545608,24); manlo <= conv_std_logic_vector(191424516,28); exponent <= conv_std_logic_vector(1051,11); WHEN "0000010101" => manhi <= conv_std_logic_vector(3829279,24); manlo <= conv_std_logic_vector(228519165,28); exponent <= conv_std_logic_vector(1053,11); WHEN "0000010110" => manhi <= conv_std_logic_vector(11229915,24); manlo <= conv_std_logic_vector(163853824,28); exponent <= conv_std_logic_vector(1054,11); WHEN "0000010111" => manhi <= conv_std_logic_vector(2255603,24); manlo <= conv_std_logic_vector(61996481,28); exponent <= conv_std_logic_vector(1056,11); WHEN "0000011000" => manhi <= conv_std_logic_vector(9091067,24); manlo <= conv_std_logic_vector(88563639,28); exponent <= conv_std_logic_vector(1057,11); WHEN "0000011001" => manhi <= conv_std_logic_vector(802105,24); manlo <= conv_std_logic_vector(34169545,28); exponent <= conv_std_logic_vector(1059,11); WHEN "0000011010" => manhi <= conv_std_logic_vector(7115558,24); manlo <= conv_std_logic_vector(157969244,28); exponent <= conv_std_logic_vector(1060,11); WHEN "0000011011" => manhi <= conv_std_logic_vector(15696431,24); manlo <= conv_std_logic_vector(133591837,28); exponent <= conv_std_logic_vector(1061,11); WHEN "0000011100" => manhi <= conv_std_logic_vector(5290915,24); manlo <= conv_std_logic_vector(127285146,28); exponent <= conv_std_logic_vector(1063,11); WHEN "0000011101" => manhi <= conv_std_logic_vector(13216484,24); manlo <= conv_std_logic_vector(103923798,28); exponent <= conv_std_logic_vector(1064,11); WHEN "0000011110" => manhi <= conv_std_logic_vector(3605616,24); manlo <= conv_std_logic_vector(183249133,28); exponent <= conv_std_logic_vector(1066,11); WHEN "0000011111" => manhi <= conv_std_logic_vector(10925925,24); manlo <= conv_std_logic_vector(227336045,28); exponent <= conv_std_logic_vector(1067,11); WHEN "0000100000" => manhi <= conv_std_logic_vector(2049020,24); manlo <= conv_std_logic_vector(206267948,28); exponent <= conv_std_logic_vector(1069,11); WHEN "0000100001" => manhi <= conv_std_logic_vector(8810292,24); manlo <= conv_std_logic_vector(175265666,28); exponent <= conv_std_logic_vector(1070,11); WHEN "0000100010" => manhi <= conv_std_logic_vector(611298,24); manlo <= conv_std_logic_vector(255467255,28); exponent <= conv_std_logic_vector(1072,11); WHEN "0000100011" => manhi <= conv_std_logic_vector(6856226,24); manlo <= conv_std_logic_vector(29134171,28); exponent <= conv_std_logic_vector(1073,11); WHEN "0000100100" => manhi <= conv_std_logic_vector(15343962,24); manlo <= conv_std_logic_vector(30543222,28); exponent <= conv_std_logic_vector(1074,11); WHEN "0000100101" => manhi <= conv_std_logic_vector(5051387,24); manlo <= conv_std_logic_vector(186253338,28); exponent <= conv_std_logic_vector(1076,11); WHEN "0000100110" => manhi <= conv_std_logic_vector(12890932,24); manlo <= conv_std_logic_vector(102222951,28); exponent <= conv_std_logic_vector(1077,11); WHEN "0000100111" => manhi <= conv_std_logic_vector(3384381,24); manlo <= conv_std_logic_vector(42116377,28); exponent <= conv_std_logic_vector(1079,11); WHEN "0000101000" => manhi <= conv_std_logic_vector(10625235,24); manlo <= conv_std_logic_vector(158954218,28); exponent <= conv_std_logic_vector(1080,11); WHEN "0000101001" => manhi <= conv_std_logic_vector(1844680,24); manlo <= conv_std_logic_vector(148858978,28); exponent <= conv_std_logic_vector(1082,11); WHEN "0000101010" => manhi <= conv_std_logic_vector(8532565,24); manlo <= conv_std_logic_vector(136319321,28); exponent <= conv_std_logic_vector(1083,11); WHEN "0000101011" => manhi <= conv_std_logic_vector(422563,24); manlo <= conv_std_logic_vector(211728497,28); exponent <= conv_std_logic_vector(1085,11); WHEN "0000101100" => manhi <= conv_std_logic_vector(6599708,24); manlo <= conv_std_logic_vector(114522162,28); exponent <= conv_std_logic_vector(1086,11); WHEN "0000101101" => manhi <= conv_std_logic_vector(14995318,24); manlo <= conv_std_logic_vector(117328318,28); exponent <= conv_std_logic_vector(1087,11); WHEN "0000101110" => manhi <= conv_std_logic_vector(4814459,24); manlo <= conv_std_logic_vector(201622499,28); exponent <= conv_std_logic_vector(1089,11); WHEN "0000101111" => manhi <= conv_std_logic_vector(12568913,24); manlo <= conv_std_logic_vector(246987638,28); exponent <= conv_std_logic_vector(1090,11); WHEN "0000110000" => manhi <= conv_std_logic_vector(3165546,24); manlo <= conv_std_logic_vector(248128843,28); exponent <= conv_std_logic_vector(1092,11); WHEN "0000110001" => manhi <= conv_std_logic_vector(10327809,24); manlo <= conv_std_logic_vector(8929872,28); exponent <= conv_std_logic_vector(1093,11); WHEN "0000110010" => manhi <= conv_std_logic_vector(1642558,24); manlo <= conv_std_logic_vector(67636037,28); exponent <= conv_std_logic_vector(1095,11); WHEN "0000110011" => manhi <= conv_std_logic_vector(8257852,24); manlo <= conv_std_logic_vector(219235425,28); exponent <= conv_std_logic_vector(1096,11); WHEN "0000110100" => manhi <= conv_std_logic_vector(235877,24); manlo <= conv_std_logic_vector(42862412,28); exponent <= conv_std_logic_vector(1098,11); WHEN "0000110101" => manhi <= conv_std_logic_vector(6345974,24); manlo <= conv_std_logic_vector(265996080,28); exponent <= conv_std_logic_vector(1099,11); WHEN "0000110110" => manhi <= conv_std_logic_vector(14650458,24); manlo <= conv_std_logic_vector(253213243,28); exponent <= conv_std_logic_vector(1100,11); WHEN "0000110111" => manhi <= conv_std_logic_vector(4580103,24); manlo <= conv_std_logic_vector(114693785,28); exponent <= conv_std_logic_vector(1102,11); WHEN "0000111000" => manhi <= conv_std_logic_vector(12250390,24); manlo <= conv_std_logic_vector(174984615,28); exponent <= conv_std_logic_vector(1103,11); WHEN "0000111001" => manhi <= conv_std_logic_vector(2949087,24); manlo <= conv_std_logic_vector(247325089,28); exponent <= conv_std_logic_vector(1105,11); WHEN "0000111010" => manhi <= conv_std_logic_vector(10033610,24); manlo <= conv_std_logic_vector(200264553,28); exponent <= conv_std_logic_vector(1106,11); WHEN "0000111011" => manhi <= conv_std_logic_vector(1442629,24); manlo <= conv_std_logic_vector(211375075,28); exponent <= conv_std_logic_vector(1108,11); WHEN "0000111100" => manhi <= conv_std_logic_vector(7986121,24); manlo <= conv_std_logic_vector(231029862,28); exponent <= conv_std_logic_vector(1109,11); WHEN "0000111101" => manhi <= conv_std_logic_vector(51216,24); manlo <= conv_std_logic_vector(222707863,28); exponent <= conv_std_logic_vector(1111,11); WHEN "0000111110" => manhi <= conv_std_logic_vector(6094995,24); manlo <= conv_std_logic_vector(155999272,28); exponent <= conv_std_logic_vector(1112,11); WHEN "0000111111" => manhi <= conv_std_logic_vector(14309342,24); manlo <= conv_std_logic_vector(150013864,28); exponent <= conv_std_logic_vector(1113,11); WHEN "0001000000" => manhi <= conv_std_logic_vector(4348290,24); manlo <= conv_std_logic_vector(217421773,28); exponent <= conv_std_logic_vector(1115,11); WHEN "0001000001" => manhi <= conv_std_logic_vector(11935324,24); manlo <= conv_std_logic_vector(171597361,28); exponent <= conv_std_logic_vector(1116,11); WHEN "0001000010" => manhi <= conv_std_logic_vector(2734978,24); manlo <= conv_std_logic_vector(98553735,28); exponent <= conv_std_logic_vector(1118,11); WHEN "0001000011" => manhi <= conv_std_logic_vector(9742605,24); manlo <= conv_std_logic_vector(185429986,28); exponent <= conv_std_logic_vector(1119,11); WHEN "0001000100" => manhi <= conv_std_logic_vector(1244871,24); manlo <= conv_std_logic_vector(93685501,28); exponent <= conv_std_logic_vector(1121,11); WHEN "0001000101" => manhi <= conv_std_logic_vector(7717340,24); manlo <= conv_std_logic_vector(74048432,28); exponent <= conv_std_logic_vector(1122,11); WHEN "0001000110" => manhi <= conv_std_logic_vector(16514337,24); manlo <= conv_std_logic_vector(163855108,28); exponent <= conv_std_logic_vector(1123,11); WHEN "0001000111" => manhi <= conv_std_logic_vector(5846740,24); manlo <= conv_std_logic_vector(81895750,28); exponent <= conv_std_logic_vector(1125,11); WHEN "0001001000" => manhi <= conv_std_logic_vector(13971928,24); manlo <= conv_std_logic_vector(176088988,28); exponent <= conv_std_logic_vector(1126,11); WHEN "0001001001" => manhi <= conv_std_logic_vector(4118994,24); manlo <= conv_std_logic_vector(77780251,28); exponent <= conv_std_logic_vector(1128,11); WHEN "0001001010" => manhi <= conv_std_logic_vector(11623678,24); manlo <= conv_std_logic_vector(95871356,28); exponent <= conv_std_logic_vector(1129,11); WHEN "0001001011" => manhi <= conv_std_logic_vector(2523192,24); manlo <= conv_std_logic_vector(204213760,28); exponent <= conv_std_logic_vector(1131,11); WHEN "0001001100" => manhi <= conv_std_logic_vector(9454759,24); manlo <= conv_std_logic_vector(55860552,28); exponent <= conv_std_logic_vector(1132,11); WHEN "0001001101" => manhi <= conv_std_logic_vector(1049259,24); manlo <= conv_std_logic_vector(102861624,28); exponent <= conv_std_logic_vector(1134,11); WHEN "0001001110" => manhi <= conv_std_logic_vector(7451476,24); manlo <= conv_std_logic_vector(13367584,28); exponent <= conv_std_logic_vector(1135,11); WHEN "0001001111" => manhi <= conv_std_logic_vector(16152990,24); manlo <= conv_std_logic_vector(178012490,28); exponent <= conv_std_logic_vector(1136,11); WHEN "0001010000" => manhi <= conv_std_logic_vector(5601179,24); manlo <= conv_std_logic_vector(159708139,28); exponent <= conv_std_logic_vector(1138,11); WHEN "0001010001" => manhi <= conv_std_logic_vector(13638177,24); manlo <= conv_std_logic_vector(12864164,28); exponent <= conv_std_logic_vector(1139,11); WHEN "0001010010" => manhi <= conv_std_logic_vector(3892186,24); manlo <= conv_std_logic_vector(149492240,28); exponent <= conv_std_logic_vector(1141,11); WHEN "0001010011" => manhi <= conv_std_logic_vector(11315414,24); manlo <= conv_std_logic_vector(184620728,28); exponent <= conv_std_logic_vector(1142,11); WHEN "0001010100" => manhi <= conv_std_logic_vector(2313705,24); manlo <= conv_std_logic_vector(235697385,28); exponent <= conv_std_logic_vector(1144,11); WHEN "0001010101" => manhi <= conv_std_logic_vector(9170037,24); manlo <= conv_std_logic_vector(3974263,28); exponent <= conv_std_logic_vector(1145,11); WHEN "0001010110" => manhi <= conv_std_logic_vector(855770,24); manlo <= conv_std_logic_vector(158952336,28); exponent <= conv_std_logic_vector(1147,11); WHEN "0001010111" => manhi <= conv_std_logic_vector(7188497,24); manlo <= conv_std_logic_vector(138900038,28); exponent <= conv_std_logic_vector(1148,11); WHEN "0001011000" => manhi <= conv_std_logic_vector(15795565,24); manlo <= conv_std_logic_vector(209449517,28); exponent <= conv_std_logic_vector(1149,11); WHEN "0001011001" => manhi <= conv_std_logic_vector(5358284,24); manlo <= conv_std_logic_vector(54736896,28); exponent <= conv_std_logic_vector(1151,11); WHEN "0001011010" => manhi <= conv_std_logic_vector(13308047,24); manlo <= conv_std_logic_vector(264159588,28); exponent <= conv_std_logic_vector(1152,11); WHEN "0001011011" => manhi <= conv_std_logic_vector(3667840,24); manlo <= conv_std_logic_vector(160544132,28); exponent <= conv_std_logic_vector(1154,11); WHEN "0001011100" => manhi <= conv_std_logic_vector(11010496,24); manlo <= conv_std_logic_vector(245935181,28); exponent <= conv_std_logic_vector(1155,11); WHEN "0001011101" => manhi <= conv_std_logic_vector(2106492,24); manlo <= conv_std_logic_vector(206325441,28); exponent <= conv_std_logic_vector(1157,11); WHEN "0001011110" => manhi <= conv_std_logic_vector(8888405,24); manlo <= conv_std_logic_vector(53641237,28); exponent <= conv_std_logic_vector(1158,11); WHEN "0001011111" => manhi <= conv_std_logic_vector(664381,24); manlo <= conv_std_logic_vector(249887163,28); exponent <= conv_std_logic_vector(1160,11); WHEN "0001100000" => manhi <= conv_std_logic_vector(6928373,24); manlo <= conv_std_logic_vector(95946938,28); exponent <= conv_std_logic_vector(1161,11); WHEN "0001100001" => manhi <= conv_std_logic_vector(15442020,24); manlo <= conv_std_logic_vector(105121290,28); exponent <= conv_std_logic_vector(1162,11); WHEN "0001100010" => manhi <= conv_std_logic_vector(5118025,24); manlo <= conv_std_logic_vector(54367076,28); exponent <= conv_std_logic_vector(1164,11); WHEN "0001100011" => manhi <= conv_std_logic_vector(12981502,24); manlo <= conv_std_logic_vector(39000129,28); exponent <= conv_std_logic_vector(1165,11); WHEN "0001100100" => manhi <= conv_std_logic_vector(3445929,24); manlo <= conv_std_logic_vector(186063861,28); exponent <= conv_std_logic_vector(1167,11); WHEN "0001100101" => manhi <= conv_std_logic_vector(10708888,24); manlo <= conv_std_logic_vector(194877084,28); exponent <= conv_std_logic_vector(1168,11); WHEN "0001100110" => manhi <= conv_std_logic_vector(1901528,24); manlo <= conv_std_logic_vector(202114223,28); exponent <= conv_std_logic_vector(1170,11); WHEN "0001100111" => manhi <= conv_std_logic_vector(8609830,24); manlo <= conv_std_logic_vector(59099508,28); exponent <= conv_std_logic_vector(1171,11); WHEN "0001101000" => manhi <= conv_std_logic_vector(475070,24); manlo <= conv_std_logic_vector(162304029,28); exponent <= conv_std_logic_vector(1173,11); WHEN "0001101001" => manhi <= conv_std_logic_vector(6671072,24); manlo <= conv_std_logic_vector(157938310,28); exponent <= conv_std_logic_vector(1174,11); WHEN "0001101010" => manhi <= conv_std_logic_vector(15092312,24); manlo <= conv_std_logic_vector(104450792,28); exponent <= conv_std_logic_vector(1175,11); WHEN "0001101011" => manhi <= conv_std_logic_vector(4880373,24); manlo <= conv_std_logic_vector(261837049,28); exponent <= conv_std_logic_vector(1177,11); WHEN "0001101100" => manhi <= conv_std_logic_vector(12658500,24); manlo <= conv_std_logic_vector(171583716,28); exponent <= conv_std_logic_vector(1178,11); WHEN "0001101101" => manhi <= conv_std_logic_vector(3226427,24); manlo <= conv_std_logic_vector(110595717,28); exponent <= conv_std_logic_vector(1180,11); WHEN "0001101110" => manhi <= conv_std_logic_vector(10410554,24); manlo <= conv_std_logic_vector(52320382,28); exponent <= conv_std_logic_vector(1181,11); WHEN "0001101111" => manhi <= conv_std_logic_vector(1698789,24); manlo <= conv_std_logic_vector(112550995,28); exponent <= conv_std_logic_vector(1183,11); WHEN "0001110000" => manhi <= conv_std_logic_vector(8334278,24); manlo <= conv_std_logic_vector(240753534,28); exponent <= conv_std_logic_vector(1184,11); WHEN "0001110001" => manhi <= conv_std_logic_vector(287814,24); manlo <= conv_std_logic_vector(17691391,28); exponent <= conv_std_logic_vector(1186,11); WHEN "0001110010" => manhi <= conv_std_logic_vector(6416564,24); manlo <= conv_std_logic_vector(151700710,28); exponent <= conv_std_logic_vector(1187,11); WHEN "0001110011" => manhi <= conv_std_logic_vector(14746400,24); manlo <= conv_std_logic_vector(32676275,28); exponent <= conv_std_logic_vector(1188,11); WHEN "0001110100" => manhi <= conv_std_logic_vector(4645302,24); manlo <= conv_std_logic_vector(58452725,28); exponent <= conv_std_logic_vector(1190,11); WHEN "0001110101" => manhi <= conv_std_logic_vector(12339004,24); manlo <= conv_std_logic_vector(267247876,28); exponent <= conv_std_logic_vector(1191,11); WHEN "0001110110" => manhi <= conv_std_logic_vector(3009307,24); manlo <= conv_std_logic_vector(164126253,28); exponent <= conv_std_logic_vector(1193,11); WHEN "0001110111" => manhi <= conv_std_logic_vector(10115457,24); manlo <= conv_std_logic_vector(212237584,28); exponent <= conv_std_logic_vector(1194,11); WHEN "0001111000" => manhi <= conv_std_logic_vector(1498250,24); manlo <= conv_std_logic_vector(166684427,28); exponent <= conv_std_logic_vector(1196,11); WHEN "0001111001" => manhi <= conv_std_logic_vector(8061718,24); manlo <= conv_std_logic_vector(110371593,28); exponent <= conv_std_logic_vector(1197,11); WHEN "0001111010" => manhi <= conv_std_logic_vector(102590,24); manlo <= conv_std_logic_vector(3231911,28); exponent <= conv_std_logic_vector(1199,11); WHEN "0001111011" => manhi <= conv_std_logic_vector(6164818,24); manlo <= conv_std_logic_vector(261783833,28); exponent <= conv_std_logic_vector(1200,11); WHEN "0001111100" => manhi <= conv_std_logic_vector(14404242,24); manlo <= conv_std_logic_vector(104825991,28); exponent <= conv_std_logic_vector(1201,11); WHEN "0001111101" => manhi <= conv_std_logic_vector(4412781,24); manlo <= conv_std_logic_vector(250166254,28); exponent <= conv_std_logic_vector(1203,11); WHEN "0001111110" => manhi <= conv_std_logic_vector(12022977,24); manlo <= conv_std_logic_vector(43417082,28); exponent <= conv_std_logic_vector(1204,11); WHEN "0001111111" => manhi <= conv_std_logic_vector(2794544,24); manlo <= conv_std_logic_vector(115942082,28); exponent <= conv_std_logic_vector(1206,11); WHEN "0010000000" => manhi <= conv_std_logic_vector(9823564,24); manlo <= conv_std_logic_vector(98386456,28); exponent <= conv_std_logic_vector(1207,11); WHEN "0010000001" => manhi <= conv_std_logic_vector(1299888,24); manlo <= conv_std_logic_vector(127046227,28); exponent <= conv_std_logic_vector(1209,11); WHEN "0010000010" => manhi <= conv_std_logic_vector(7792116,24); manlo <= conv_std_logic_vector(80649262,28); exponent <= conv_std_logic_vector(1210,11); WHEN "0010000011" => manhi <= conv_std_logic_vector(16615968,24); manlo <= conv_std_logic_vector(205307910,28); exponent <= conv_std_logic_vector(1211,11); WHEN "0010000100" => manhi <= conv_std_logic_vector(5915805,24); manlo <= conv_std_logic_vector(224185017,28); exponent <= conv_std_logic_vector(1213,11); WHEN "0010000101" => manhi <= conv_std_logic_vector(14065798,24); manlo <= conv_std_logic_vector(119094636,28); exponent <= conv_std_logic_vector(1214,11); WHEN "0010000110" => manhi <= conv_std_logic_vector(4182785,24); manlo <= conv_std_logic_vector(113890892,28); exponent <= conv_std_logic_vector(1216,11); WHEN "0010000111" => manhi <= conv_std_logic_vector(11710379,24); manlo <= conv_std_logic_vector(133692518,28); exponent <= conv_std_logic_vector(1217,11); WHEN "0010001000" => manhi <= conv_std_logic_vector(2582112,24); manlo <= conv_std_logic_vector(79109485,28); exponent <= conv_std_logic_vector(1219,11); WHEN "0010001001" => manhi <= conv_std_logic_vector(9534839,24); manlo <= conv_std_logic_vector(42234535,28); exponent <= conv_std_logic_vector(1220,11); WHEN "0010001010" => manhi <= conv_std_logic_vector(1103679,24); manlo <= conv_std_logic_vector(94193887,28); exponent <= conv_std_logic_vector(1222,11); WHEN "0010001011" => manhi <= conv_std_logic_vector(7525440,24); manlo <= conv_std_logic_vector(121994268,28); exponent <= conv_std_logic_vector(1223,11); WHEN "0010001100" => manhi <= conv_std_logic_vector(16253518,24); manlo <= conv_std_logic_vector(191052573,28); exponent <= conv_std_logic_vector(1224,11); WHEN "0010001101" => manhi <= conv_std_logic_vector(5669495,24); manlo <= conv_std_logic_vector(130696997,28); exponent <= conv_std_logic_vector(1226,11); WHEN "0010001110" => manhi <= conv_std_logic_vector(13731027,24); manlo <= conv_std_logic_vector(260846837,28); exponent <= conv_std_logic_vector(1227,11); WHEN "0010001111" => manhi <= conv_std_logic_vector(3955285,24); manlo <= conv_std_logic_vector(80970159,28); exponent <= conv_std_logic_vector(1229,11); WHEN "0010010000" => manhi <= conv_std_logic_vector(11401174,24); manlo <= conv_std_logic_vector(207600506,28); exponent <= conv_std_logic_vector(1230,11); WHEN "0010010001" => manhi <= conv_std_logic_vector(2371985,24); manlo <= conv_std_logic_vector(241221170,28); exponent <= conv_std_logic_vector(1232,11); WHEN "0010010010" => manhi <= conv_std_logic_vector(9249247,24); manlo <= conv_std_logic_vector(208105818,28); exponent <= conv_std_logic_vector(1233,11); WHEN "0010010011" => manhi <= conv_std_logic_vector(909599,24); manlo <= conv_std_logic_vector(237519888,28); exponent <= conv_std_logic_vector(1235,11); WHEN "0010010100" => manhi <= conv_std_logic_vector(7261659,24); manlo <= conv_std_logic_vector(29935335,28); exponent <= conv_std_logic_vector(1236,11); WHEN "0010010101" => manhi <= conv_std_logic_vector(15895002,24); manlo <= conv_std_logic_vector(186862656,28); exponent <= conv_std_logic_vector(1237,11); WHEN "0010010110" => manhi <= conv_std_logic_vector(5425858,24); manlo <= conv_std_logic_vector(159524243,28); exponent <= conv_std_logic_vector(1239,11); WHEN "0010010111" => manhi <= conv_std_logic_vector(13399891,24); manlo <= conv_std_logic_vector(27586577,28); exponent <= conv_std_logic_vector(1240,11); WHEN "0010011000" => manhi <= conv_std_logic_vector(3730254,24); manlo <= conv_std_logic_vector(125689310,28); exponent <= conv_std_logic_vector(1242,11); WHEN "0010011001" => manhi <= conv_std_logic_vector(11095326,24); manlo <= conv_std_logic_vector(43144000,28); exponent <= conv_std_logic_vector(1243,11); WHEN "0010011010" => manhi <= conv_std_logic_vector(2164140,24); manlo <= conv_std_logic_vector(58280992,28); exponent <= conv_std_logic_vector(1245,11); WHEN "0010011011" => manhi <= conv_std_logic_vector(8966756,24); manlo <= conv_std_logic_vector(55210422,28); exponent <= conv_std_logic_vector(1246,11); WHEN "0010011100" => manhi <= conv_std_logic_vector(717626,24); manlo <= conv_std_logic_vector(257633658,28); exponent <= conv_std_logic_vector(1248,11); WHEN "0010011101" => manhi <= conv_std_logic_vector(7000740,24); manlo <= conv_std_logic_vector(229413090,28); exponent <= conv_std_logic_vector(1249,11); WHEN "0010011110" => manhi <= conv_std_logic_vector(15540378,24); manlo <= conv_std_logic_vector(4808337,28); exponent <= conv_std_logic_vector(1250,11); WHEN "0010011111" => manhi <= conv_std_logic_vector(5184866,24); manlo <= conv_std_logic_vector(37474138,28); exponent <= conv_std_logic_vector(1252,11); WHEN "0010100000" => manhi <= conv_std_logic_vector(13072348,24); manlo <= conv_std_logic_vector(106730632,28); exponent <= conv_std_logic_vector(1253,11); WHEN "0010100001" => manhi <= conv_std_logic_vector(3507666,24); manlo <= conv_std_logic_vector(32844500,28); exponent <= conv_std_logic_vector(1255,11); WHEN "0010100010" => manhi <= conv_std_logic_vector(10792797,24); manlo <= conv_std_logic_vector(62496090,28); exponent <= conv_std_logic_vector(1256,11); WHEN "0010100011" => manhi <= conv_std_logic_vector(1958550,24); manlo <= conv_std_logic_vector(132952012,28); exponent <= conv_std_logic_vector(1258,11); WHEN "0010100100" => manhi <= conv_std_logic_vector(8687330,24); manlo <= conv_std_logic_vector(215605290,28); exponent <= conv_std_logic_vector(1259,11); WHEN "0010100101" => manhi <= conv_std_logic_vector(527737,24); manlo <= conv_std_logic_vector(190928911,28); exponent <= conv_std_logic_vector(1261,11); WHEN "0010100110" => manhi <= conv_std_logic_vector(6742654,24); manlo <= conv_std_logic_vector(163162889,28); exponent <= conv_std_logic_vector(1262,11); WHEN "0010100111" => manhi <= conv_std_logic_vector(15189602,24); manlo <= conv_std_logic_vector(118241780,28); exponent <= conv_std_logic_vector(1263,11); WHEN "0010101000" => manhi <= conv_std_logic_vector(4946489,24); manlo <= conv_std_logic_vector(112771062,28); exponent <= conv_std_logic_vector(1265,11); WHEN "0010101001" => manhi <= conv_std_logic_vector(12748360,24); manlo <= conv_std_logic_vector(226864003,28); exponent <= conv_std_logic_vector(1266,11); WHEN "0010101010" => manhi <= conv_std_logic_vector(3287493,24); manlo <= conv_std_logic_vector(202192272,28); exponent <= conv_std_logic_vector(1268,11); WHEN "0010101011" => manhi <= conv_std_logic_vector(10493551,24); manlo <= conv_std_logic_vector(257093553,28); exponent <= conv_std_logic_vector(1269,11); WHEN "0010101100" => manhi <= conv_std_logic_vector(1755192,24); manlo <= conv_std_logic_vector(66281405,28); exponent <= conv_std_logic_vector(1271,11); WHEN "0010101101" => manhi <= conv_std_logic_vector(8410938,24); manlo <= conv_std_logic_vector(77199396,28); exponent <= conv_std_logic_vector(1272,11); WHEN "0010101110" => manhi <= conv_std_logic_vector(339909,24); manlo <= conv_std_logic_vector(140417186,28); exponent <= conv_std_logic_vector(1274,11); WHEN "0010101111" => manhi <= conv_std_logic_vector(6487369,24); manlo <= conv_std_logic_vector(169769464,28); exponent <= conv_std_logic_vector(1275,11); WHEN "0010110000" => manhi <= conv_std_logic_vector(14842634,24); manlo <= conv_std_logic_vector(49834035,28); exponent <= conv_std_logic_vector(1276,11); WHEN "0010110001" => manhi <= conv_std_logic_vector(4710700,24); manlo <= conv_std_logic_vector(11961455,28); exponent <= conv_std_logic_vector(1278,11); WHEN "0010110010" => manhi <= conv_std_logic_vector(12427889,24); manlo <= conv_std_logic_vector(230234502,28); exponent <= conv_std_logic_vector(1279,11); WHEN "0010110011" => manhi <= conv_std_logic_vector(3069711,24); manlo <= conv_std_logic_vector(36989233,28); exponent <= conv_std_logic_vector(1281,11); WHEN "0010110100" => manhi <= conv_std_logic_vector(10197554,24); manlo <= conv_std_logic_vector(186484869,28); exponent <= conv_std_logic_vector(1282,11); WHEN "0010110101" => manhi <= conv_std_logic_vector(1554041,24); manlo <= conv_std_logic_vector(67530342,28); exponent <= conv_std_logic_vector(1284,11); WHEN "0010110110" => manhi <= conv_std_logic_vector(8137545,24); manlo <= conv_std_logic_vector(198608842,28); exponent <= conv_std_logic_vector(1285,11); WHEN "0010110111" => manhi <= conv_std_logic_vector(154120,24); manlo <= conv_std_logic_vector(6569319,28); exponent <= conv_std_logic_vector(1287,11); WHEN "0010111000" => manhi <= conv_std_logic_vector(6234855,24); manlo <= conv_std_logic_vector(140506894,28); exponent <= conv_std_logic_vector(1288,11); WHEN "0010111001" => manhi <= conv_std_logic_vector(14499431,24); manlo <= conv_std_logic_vector(249287529,28); exponent <= conv_std_logic_vector(1289,11); WHEN "0010111010" => manhi <= conv_std_logic_vector(4477469,24); manlo <= conv_std_logic_vector(249618841,28); exponent <= conv_std_logic_vector(1291,11); WHEN "0010111011" => manhi <= conv_std_logic_vector(12110897,24); manlo <= conv_std_logic_vector(71519058,28); exponent <= conv_std_logic_vector(1292,11); WHEN "0010111100" => manhi <= conv_std_logic_vector(2854292,24); manlo <= conv_std_logic_vector(90637320,28); exponent <= conv_std_logic_vector(1294,11); WHEN "0010111101" => manhi <= conv_std_logic_vector(9904770,24); manlo <= conv_std_logic_vector(50932558,28); exponent <= conv_std_logic_vector(1295,11); WHEN "0010111110" => manhi <= conv_std_logic_vector(1355073,24); manlo <= conv_std_logic_vector(148093260,28); exponent <= conv_std_logic_vector(1297,11); WHEN "0010111111" => manhi <= conv_std_logic_vector(7867120,24); manlo <= conv_std_logic_vector(160620741,28); exponent <= conv_std_logic_vector(1298,11); WHEN "0011000000" => manhi <= conv_std_logic_vector(16717910,24); manlo <= conv_std_logic_vector(46942270,28); exponent <= conv_std_logic_vector(1299,11); WHEN "0011000001" => manhi <= conv_std_logic_vector(5985082,24); manlo <= conv_std_logic_vector(55237426,28); exponent <= conv_std_logic_vector(1301,11); WHEN "0011000010" => manhi <= conv_std_logic_vector(14159954,24); manlo <= conv_std_logic_vector(212966668,28); exponent <= conv_std_logic_vector(1302,11); WHEN "0011000011" => manhi <= conv_std_logic_vector(4246771,24); manlo <= conv_std_logic_vector(79962334,28); exponent <= conv_std_logic_vector(1304,11); WHEN "0011000100" => manhi <= conv_std_logic_vector(11797345,24); manlo <= conv_std_logic_vector(85038862,28); exponent <= conv_std_logic_vector(1305,11); WHEN "0011000101" => manhi <= conv_std_logic_vector(2641211,24); manlo <= conv_std_logic_vector(186806322,28); exponent <= conv_std_logic_vector(1307,11); WHEN "0011000110" => manhi <= conv_std_logic_vector(9615163,24); manlo <= conv_std_logic_vector(153415152,28); exponent <= conv_std_logic_vector(1308,11); WHEN "0011000111" => manhi <= conv_std_logic_vector(1158265,24); manlo <= conv_std_logic_vector(120731907,28); exponent <= conv_std_logic_vector(1310,11); WHEN "0011001000" => manhi <= conv_std_logic_vector(7599630,24); manlo <= conv_std_logic_vector(175764921,28); exponent <= conv_std_logic_vector(1311,11); WHEN "0011001001" => manhi <= conv_std_logic_vector(16354353,24); manlo <= conv_std_logic_vector(174054693,28); exponent <= conv_std_logic_vector(1312,11); WHEN "0011001010" => manhi <= conv_std_logic_vector(5738019,24); manlo <= conv_std_logic_vector(249885394,28); exponent <= conv_std_logic_vector(1314,11); WHEN "0011001011" => manhi <= conv_std_logic_vector(13824162,24); manlo <= conv_std_logic_vector(93203713,28); exponent <= conv_std_logic_vector(1315,11); WHEN "0011001100" => manhi <= conv_std_logic_vector(4018576,24); manlo <= conv_std_logic_vector(180323091,28); exponent <= conv_std_logic_vector(1317,11); WHEN "0011001101" => manhi <= conv_std_logic_vector(11487196,24); manlo <= conv_std_logic_vector(178245939,28); exponent <= conv_std_logic_vector(1318,11); WHEN "0011001110" => manhi <= conv_std_logic_vector(2430443,24); manlo <= conv_std_logic_vector(223919964,28); exponent <= conv_std_logic_vector(1320,11); WHEN "0011001111" => manhi <= conv_std_logic_vector(9328700,24); manlo <= conv_std_logic_vector(93205956,28); exponent <= conv_std_logic_vector(1321,11); WHEN "0011010000" => manhi <= conv_std_logic_vector(963593,24); manlo <= conv_std_logic_vector(135688620,28); exponent <= conv_std_logic_vector(1323,11); WHEN "0011010001" => manhi <= conv_std_logic_vector(7335044,24); manlo <= conv_std_logic_vector(13542358,28); exponent <= conv_std_logic_vector(1324,11); WHEN "0011010010" => manhi <= conv_std_logic_vector(15994743,24); manlo <= conv_std_logic_vector(45394459,28); exponent <= conv_std_logic_vector(1325,11); WHEN "0011010011" => manhi <= conv_std_logic_vector(5493639,24); manlo <= conv_std_logic_vector(73308838,28); exponent <= conv_std_logic_vector(1327,11); WHEN "0011010100" => manhi <= conv_std_logic_vector(13492014,24); manlo <= conv_std_logic_vector(160135181,28); exponent <= conv_std_logic_vector(1328,11); WHEN "0011010101" => manhi <= conv_std_logic_vector(3792858,24); manlo <= conv_std_logic_vector(234346738,28); exponent <= conv_std_logic_vector(1330,11); WHEN "0011010110" => manhi <= conv_std_logic_vector(11180414,24); manlo <= conv_std_logic_vector(98964646,28); exponent <= conv_std_logic_vector(1331,11); WHEN "0011010111" => manhi <= conv_std_logic_vector(2221963,24); manlo <= conv_std_logic_vector(174344531,28); exponent <= conv_std_logic_vector(1333,11); WHEN "0011011000" => manhi <= conv_std_logic_vector(9045346,24); manlo <= conv_std_logic_vector(106947534,28); exponent <= conv_std_logic_vector(1334,11); WHEN "0011011001" => manhi <= conv_std_logic_vector(771034,24); manlo <= conv_std_logic_vector(143065990,28); exponent <= conv_std_logic_vector(1336,11); WHEN "0011011010" => manhi <= conv_std_logic_vector(7073329,24); manlo <= conv_std_logic_vector(73148434,28); exponent <= conv_std_logic_vector(1337,11); WHEN "0011011011" => manhi <= conv_std_logic_vector(15639035,24); manlo <= conv_std_logic_vector(243346703,28); exponent <= conv_std_logic_vector(1338,11); WHEN "0011011100" => manhi <= conv_std_logic_vector(5251911,24); manlo <= conv_std_logic_vector(33842377,28); exponent <= conv_std_logic_vector(1340,11); WHEN "0011011101" => manhi <= conv_std_logic_vector(13163471,24); manlo <= conv_std_logic_vector(263552292,28); exponent <= conv_std_logic_vector(1341,11); WHEN "0011011110" => manhi <= conv_std_logic_vector(3569591,24); manlo <= conv_std_logic_vector(4866264,28); exponent <= conv_std_logic_vector(1343,11); WHEN "0011011111" => manhi <= conv_std_logic_vector(10876961,24); manlo <= conv_std_logic_vector(239517036,28); exponent <= conv_std_logic_vector(1344,11); WHEN "0011100000" => manhi <= conv_std_logic_vector(2015746,24); manlo <= conv_std_logic_vector(83586287,28); exponent <= conv_std_logic_vector(1346,11); WHEN "0011100001" => manhi <= conv_std_logic_vector(8765067,24); manlo <= conv_std_logic_vector(262254542,28); exponent <= conv_std_logic_vector(1347,11); WHEN "0011100010" => manhi <= conv_std_logic_vector(580565,24); manlo <= conv_std_logic_vector(160521039,28); exponent <= conv_std_logic_vector(1349,11); WHEN "0011100011" => manhi <= conv_std_logic_vector(6814455,24); manlo <= conv_std_logic_vector(40288155,28); exponent <= conv_std_logic_vector(1350,11); WHEN "0011100100" => manhi <= conv_std_logic_vector(15287189,24); manlo <= conv_std_logic_vector(132910147,28); exponent <= conv_std_logic_vector(1351,11); WHEN "0011100101" => manhi <= conv_std_logic_vector(5012806,24); manlo <= conv_std_logic_vector(187753904,28); exponent <= conv_std_logic_vector(1353,11); WHEN "0011100110" => manhi <= conv_std_logic_vector(12838495,24); manlo <= conv_std_logic_vector(100071648,28); exponent <= conv_std_logic_vector(1354,11); WHEN "0011100111" => manhi <= conv_std_logic_vector(3348746,24); manlo <= conv_std_logic_vector(138348888,28); exponent <= conv_std_logic_vector(1356,11); WHEN "0011101000" => manhi <= conv_std_logic_vector(10576803,24); manlo <= conv_std_logic_vector(24941937,28); exponent <= conv_std_logic_vector(1357,11); WHEN "0011101001" => manhi <= conv_std_logic_vector(1811767,24); manlo <= conv_std_logic_vector(69497619,28); exponent <= conv_std_logic_vector(1359,11); WHEN "0011101010" => manhi <= conv_std_logic_vector(8487831,24); manlo <= conv_std_logic_vector(188199296,28); exponent <= conv_std_logic_vector(1360,11); WHEN "0011101011" => manhi <= conv_std_logic_vector(392164,24); manlo <= conv_std_logic_vector(4096525,28); exponent <= conv_std_logic_vector(1362,11); WHEN "0011101100" => manhi <= conv_std_logic_vector(6558390,24); manlo <= conv_std_logic_vector(228356857,28); exponent <= conv_std_logic_vector(1363,11); WHEN "0011101101" => manhi <= conv_std_logic_vector(14939162,24); manlo <= conv_std_logic_vector(7826265,28); exponent <= conv_std_logic_vector(1364,11); WHEN "0011101110" => manhi <= conv_std_logic_vector(4776297,24); manlo <= conv_std_logic_vector(138324122,28); exponent <= conv_std_logic_vector(1366,11); WHEN "0011101111" => manhi <= conv_std_logic_vector(12517046,24); manlo <= conv_std_logic_vector(17190560,28); exponent <= conv_std_logic_vector(1367,11); WHEN "0011110000" => manhi <= conv_std_logic_vector(3130299,24); manlo <= conv_std_logic_vector(16562242,28); exponent <= conv_std_logic_vector(1369,11); WHEN "0011110001" => manhi <= conv_std_logic_vector(10279902,24); manlo <= conv_std_logic_vector(59323104,28); exponent <= conv_std_logic_vector(1370,11); WHEN "0011110010" => manhi <= conv_std_logic_vector(1610002,24); manlo <= conv_std_logic_vector(53056333,28); exponent <= conv_std_logic_vector(1372,11); WHEN "0011110011" => manhi <= conv_std_logic_vector(8213604,24); manlo <= conv_std_logic_vector(147986337,28); exponent <= conv_std_logic_vector(1373,11); WHEN "0011110100" => manhi <= conv_std_logic_vector(205807,24); manlo <= conv_std_logic_vector(92802035,28); exponent <= conv_std_logic_vector(1375,11); WHEN "0011110101" => manhi <= conv_std_logic_vector(6305105,24); manlo <= conv_std_logic_vector(235277170,28); exponent <= conv_std_logic_vector(1376,11); WHEN "0011110110" => manhi <= conv_std_logic_vector(14594912,24); manlo <= conv_std_logic_vector(15497684,28); exponent <= conv_std_logic_vector(1377,11); WHEN "0011110111" => manhi <= conv_std_logic_vector(4542355,24); manlo <= conv_std_logic_vector(108677892,28); exponent <= conv_std_logic_vector(1379,11); WHEN "0011111000" => manhi <= conv_std_logic_vector(12199085,24); manlo <= conv_std_logic_vector(206743222,28); exponent <= conv_std_logic_vector(1380,11); WHEN "0011111001" => manhi <= conv_std_logic_vector(2914222,24); manlo <= conv_std_logic_vector(171652524,28); exponent <= conv_std_logic_vector(1382,11); WHEN "0011111010" => manhi <= conv_std_logic_vector(9986223,24); manlo <= conv_std_logic_vector(245598061,28); exponent <= conv_std_logic_vector(1383,11); WHEN "0011111011" => manhi <= conv_std_logic_vector(1410427,24); manlo <= conv_std_logic_vector(26024388,28); exponent <= conv_std_logic_vector(1385,11); WHEN "0011111100" => manhi <= conv_std_logic_vector(7942353,24); manlo <= conv_std_logic_vector(232590388,28); exponent <= conv_std_logic_vector(1386,11); WHEN "0011111101" => manhi <= conv_std_logic_vector(21473,24); manlo <= conv_std_logic_vector(105719295,28); exponent <= conv_std_logic_vector(1388,11); WHEN "0011111110" => manhi <= conv_std_logic_vector(6054570,24); manlo <= conv_std_logic_vector(16265786,28); exponent <= conv_std_logic_vector(1389,11); WHEN "0011111111" => manhi <= conv_std_logic_vector(14254398,24); manlo <= conv_std_logic_vector(155662944,28); exponent <= conv_std_logic_vector(1390,11); WHEN "0100000000" => manhi <= conv_std_logic_vector(4310952,24); manlo <= conv_std_logic_vector(135577274,28); exponent <= conv_std_logic_vector(1392,11); WHEN "0100000001" => manhi <= conv_std_logic_vector(11884576,24); manlo <= conv_std_logic_vector(166805756,28); exponent <= conv_std_logic_vector(1393,11); WHEN "0100000010" => manhi <= conv_std_logic_vector(2700491,24); manlo <= conv_std_logic_vector(137829044,28); exponent <= conv_std_logic_vector(1395,11); WHEN "0100000011" => manhi <= conv_std_logic_vector(9695733,24); manlo <= conv_std_logic_vector(52863001,28); exponent <= conv_std_logic_vector(1396,11); WHEN "0100000100" => manhi <= conv_std_logic_vector(1213018,24); manlo <= conv_std_logic_vector(50179603,28); exponent <= conv_std_logic_vector(1398,11); WHEN "0100000101" => manhi <= conv_std_logic_vector(7674047,24); manlo <= conv_std_logic_vector(91276680,28); exponent <= conv_std_logic_vector(1399,11); WHEN "0100000110" => manhi <= conv_std_logic_vector(16455496,24); manlo <= conv_std_logic_vector(110068760,28); exponent <= conv_std_logic_vector(1400,11); WHEN "0100000111" => manhi <= conv_std_logic_vector(5806753,24); manlo <= conv_std_logic_vector(151304445,28); exponent <= conv_std_logic_vector(1402,11); WHEN "0100001000" => manhi <= conv_std_logic_vector(13917581,24); manlo <= conv_std_logic_vector(10650184,28); exponent <= conv_std_logic_vector(1403,11); WHEN "0100001001" => manhi <= conv_std_logic_vector(4082061,24); manlo <= conv_std_logic_vector(68530707,28); exponent <= conv_std_logic_vector(1405,11); WHEN "0100001010" => manhi <= conv_std_logic_vector(11573481,24); manlo <= conv_std_logic_vector(42662756,28); exponent <= conv_std_logic_vector(1406,11); WHEN "0100001011" => manhi <= conv_std_logic_vector(2489080,24); manlo <= conv_std_logic_vector(61154162,28); exponent <= conv_std_logic_vector(1408,11); WHEN "0100001100" => manhi <= conv_std_logic_vector(9408395,24); manlo <= conv_std_logic_vector(125867240,28); exponent <= conv_std_logic_vector(1409,11); WHEN "0100001101" => manhi <= conv_std_logic_vector(1017751,24); manlo <= conv_std_logic_vector(256555705,28); exponent <= conv_std_logic_vector(1411,11); WHEN "0100001110" => manhi <= conv_std_logic_vector(7408653,24); manlo <= conv_std_logic_vector(4309896,28); exponent <= conv_std_logic_vector(1412,11); WHEN "0100001111" => manhi <= conv_std_logic_vector(16094788,24); manlo <= conv_std_logic_vector(33800670,28); exponent <= conv_std_logic_vector(1413,11); WHEN "0100010000" => manhi <= conv_std_logic_vector(5561626,24); manlo <= conv_std_logic_vector(233573192,28); exponent <= conv_std_logic_vector(1415,11); WHEN "0100010001" => manhi <= conv_std_logic_vector(13584419,24); manlo <= conv_std_logic_vector(86257801,28); exponent <= conv_std_logic_vector(1416,11); WHEN "0100010010" => manhi <= conv_std_logic_vector(3855654,24); manlo <= conv_std_logic_vector(105782775,28); exponent <= conv_std_logic_vector(1418,11); WHEN "0100010011" => manhi <= conv_std_logic_vector(11265762,24); manlo <= conv_std_logic_vector(88738762,28); exponent <= conv_std_logic_vector(1419,11); WHEN "0100010100" => manhi <= conv_std_logic_vector(2279963,24); manlo <= conv_std_logic_vector(161858527,28); exponent <= conv_std_logic_vector(1421,11); WHEN "0100010101" => manhi <= conv_std_logic_vector(9124176,24); manlo <= conv_std_logic_vector(136423424,28); exponent <= conv_std_logic_vector(1422,11); WHEN "0100010110" => manhi <= conv_std_logic_vector(824605,24); manlo <= conv_std_logic_vector(39384255,28); exponent <= conv_std_logic_vector(1424,11); WHEN "0100010111" => manhi <= conv_std_logic_vector(7146139,24); manlo <= conv_std_logic_vector(76626123,28); exponent <= conv_std_logic_vector(1425,11); WHEN "0100011000" => manhi <= conv_std_logic_vector(15737994,24); manlo <= conv_std_logic_vector(261485765,28); exponent <= conv_std_logic_vector(1426,11); WHEN "0100011001" => manhi <= conv_std_logic_vector(5319160,24); manlo <= conv_std_logic_vector(210684009,28); exponent <= conv_std_logic_vector(1428,11); WHEN "0100011010" => manhi <= conv_std_logic_vector(13254873,24); manlo <= conv_std_logic_vector(199859160,28); exponent <= conv_std_logic_vector(1429,11); WHEN "0100011011" => manhi <= conv_std_logic_vector(3631704,24); manlo <= conv_std_logic_vector(256571707,28); exponent <= conv_std_logic_vector(1431,11); WHEN "0100011100" => manhi <= conv_std_logic_vector(10961383,24); manlo <= conv_std_logic_vector(130542749,28); exponent <= conv_std_logic_vector(1432,11); WHEN "0100011101" => manhi <= conv_std_logic_vector(2073116,24); manlo <= conv_std_logic_vector(196665136,28); exponent <= conv_std_logic_vector(1434,11); WHEN "0100011110" => manhi <= conv_std_logic_vector(8843042,24); manlo <= conv_std_logic_vector(124490661,28); exponent <= conv_std_logic_vector(1435,11); WHEN "0100011111" => manhi <= conv_std_logic_vector(633554,24); manlo <= conv_std_logic_vector(202834752,28); exponent <= conv_std_logic_vector(1437,11); WHEN "0100100000" => manhi <= conv_std_logic_vector(6886474,24); manlo <= conv_std_logic_vector(236822279,28); exponent <= conv_std_logic_vector(1438,11); WHEN "0100100001" => manhi <= conv_std_logic_vector(15385074,24); manlo <= conv_std_logic_vector(123405487,28); exponent <= conv_std_logic_vector(1439,11); WHEN "0100100010" => manhi <= conv_std_logic_vector(5079326,24); manlo <= conv_std_logic_vector(115311954,28); exponent <= conv_std_logic_vector(1441,11); WHEN "0100100011" => manhi <= conv_std_logic_vector(12928905,24); manlo <= conv_std_logic_vector(16004876,28); exponent <= conv_std_logic_vector(1442,11); WHEN "0100100100" => manhi <= conv_std_logic_vector(3410186,24); manlo <= conv_std_logic_vector(71831800,28); exponent <= conv_std_logic_vector(1444,11); WHEN "0100100101" => manhi <= conv_std_logic_vector(10660308,24); manlo <= conv_std_logic_vector(100367284,28); exponent <= conv_std_logic_vector(1445,11); WHEN "0100100110" => manhi <= conv_std_logic_vector(1868514,24); manlo <= conv_std_logic_vector(263299419,28); exponent <= conv_std_logic_vector(1447,11); WHEN "0100100111" => manhi <= conv_std_logic_vector(8564959,24); manlo <= conv_std_logic_vector(228656810,28); exponent <= conv_std_logic_vector(1448,11); WHEN "0100101000" => manhi <= conv_std_logic_vector(444578,24); manlo <= conv_std_logic_vector(7489141,28); exponent <= conv_std_logic_vector(1450,11); WHEN "0100101001" => manhi <= conv_std_logic_vector(6629628,24); manlo <= conv_std_logic_vector(236156491,28); exponent <= conv_std_logic_vector(1451,11); WHEN "0100101010" => manhi <= conv_std_logic_vector(15035984,24); manlo <= conv_std_logic_vector(147396312,28); exponent <= conv_std_logic_vector(1452,11); WHEN "0100101011" => manhi <= conv_std_logic_vector(4842095,24); manlo <= conv_std_logic_vector(64271882,28); exponent <= conv_std_logic_vector(1454,11); WHEN "0100101100" => manhi <= conv_std_logic_vector(12606474,24); manlo <= conv_std_logic_vector(118909770,28); exponent <= conv_std_logic_vector(1455,11); WHEN "0100101101" => manhi <= conv_std_logic_vector(3191071,24); manlo <= conv_std_logic_vector(253953386,28); exponent <= conv_std_logic_vector(1457,11); WHEN "0100101110" => manhi <= conv_std_logic_vector(10362501,24); manlo <= conv_std_logic_vector(36129498,28); exponent <= conv_std_logic_vector(1458,11); WHEN "0100101111" => manhi <= conv_std_logic_vector(1666133,24); manlo <= conv_std_logic_vector(262830684,28); exponent <= conv_std_logic_vector(1460,11); WHEN "0100110000" => manhi <= conv_std_logic_vector(8289895,24); manlo <= conv_std_logic_vector(148197046,28); exponent <= conv_std_logic_vector(1461,11); WHEN "0100110001" => manhi <= conv_std_logic_vector(257652,24); manlo <= conv_std_logic_vector(122404338,28); exponent <= conv_std_logic_vector(1463,11); WHEN "0100110010" => manhi <= conv_std_logic_vector(6375570,24); manlo <= conv_std_logic_vector(184430245,28); exponent <= conv_std_logic_vector(1464,11); WHEN "0100110011" => manhi <= conv_std_logic_vector(14690683,24); manlo <= conv_std_logic_vector(178457687,28); exponent <= conv_std_logic_vector(1465,11); WHEN "0100110100" => manhi <= conv_std_logic_vector(4607438,24); manlo <= conv_std_logic_vector(257605193,28); exponent <= conv_std_logic_vector(1467,11); WHEN "0100110101" => manhi <= conv_std_logic_vector(12287543,24); manlo <= conv_std_logic_vector(132163446,28); exponent <= conv_std_logic_vector(1468,11); WHEN "0100110110" => manhi <= conv_std_logic_vector(2974335,24); manlo <= conv_std_logic_vector(240020217,28); exponent <= conv_std_logic_vector(1470,11); WHEN "0100110111" => manhi <= conv_std_logic_vector(10067926,24); manlo <= conv_std_logic_vector(80224641,28); exponent <= conv_std_logic_vector(1471,11); WHEN "0100111000" => manhi <= conv_std_logic_vector(1465949,24); manlo <= conv_std_logic_vector(167328478,28); exponent <= conv_std_logic_vector(1473,11); WHEN "0100111001" => manhi <= conv_std_logic_vector(8017816,24); manlo <= conv_std_logic_vector(215756784,28); exponent <= conv_std_logic_vector(1474,11); WHEN "0100111010" => manhi <= conv_std_logic_vector(72755,24); manlo <= conv_std_logic_vector(208473528,28); exponent <= conv_std_logic_vector(1476,11); WHEN "0100111011" => manhi <= conv_std_logic_vector(6124270,24); manlo <= conv_std_logic_vector(12139444,28); exponent <= conv_std_logic_vector(1477,11); WHEN "0100111100" => manhi <= conv_std_logic_vector(14349130,24); manlo <= conv_std_logic_vector(182729110,28); exponent <= conv_std_logic_vector(1478,11); WHEN "0100111101" => manhi <= conv_std_logic_vector(4375329,24); manlo <= conv_std_logic_vector(172370119,28); exponent <= conv_std_logic_vector(1480,11); WHEN "0100111110" => manhi <= conv_std_logic_vector(11972074,24); manlo <= conv_std_logic_vector(59679792,28); exponent <= conv_std_logic_vector(1481,11); WHEN "0100111111" => manhi <= conv_std_logic_vector(2759952,24); manlo <= conv_std_logic_vector(80023302,28); exponent <= conv_std_logic_vector(1483,11); WHEN "0101000000" => manhi <= conv_std_logic_vector(9776548,24); manlo <= conv_std_logic_vector(209956608,28); exponent <= conv_std_logic_vector(1484,11); WHEN "0101000001" => manhi <= conv_std_logic_vector(1267938,24); manlo <= conv_std_logic_vector(19091951,28); exponent <= conv_std_logic_vector(1486,11); WHEN "0101000010" => manhi <= conv_std_logic_vector(7748691,24); manlo <= conv_std_logic_vector(54127000,28); exponent <= conv_std_logic_vector(1487,11); WHEN "0101000011" => manhi <= conv_std_logic_vector(16556947,24); manlo <= conv_std_logic_vector(251347868,28); exponent <= conv_std_logic_vector(1488,11); WHEN "0101000100" => manhi <= conv_std_logic_vector(5875697,24); manlo <= conv_std_logic_vector(6377900,28); exponent <= conv_std_logic_vector(1490,11); WHEN "0101000101" => manhi <= conv_std_logic_vector(14011284,24); manlo <= conv_std_logic_vector(246175281,28); exponent <= conv_std_logic_vector(1491,11); WHEN "0101000110" => manhi <= conv_std_logic_vector(4145739,24); manlo <= conv_std_logic_vector(172360927,28); exponent <= conv_std_logic_vector(1493,11); WHEN "0101000111" => manhi <= conv_std_logic_vector(11660029,24); manlo <= conv_std_logic_vector(16047086,28); exponent <= conv_std_logic_vector(1494,11); WHEN "0101001000" => manhi <= conv_std_logic_vector(2547895,24); manlo <= conv_std_logic_vector(167600151,28); exponent <= conv_std_logic_vector(1496,11); WHEN "0101001001" => manhi <= conv_std_logic_vector(9488333,24); manlo <= conv_std_logic_vector(236416250,28); exponent <= conv_std_logic_vector(1497,11); WHEN "0101001010" => manhi <= conv_std_logic_vector(1072075,24); manlo <= conv_std_logic_vector(198323037,28); exponent <= conv_std_logic_vector(1499,11); WHEN "0101001011" => manhi <= conv_std_logic_vector(7482486,24); manlo <= conv_std_logic_vector(185820926,28); exponent <= conv_std_logic_vector(1500,11); WHEN "0101001100" => manhi <= conv_std_logic_vector(16195138,24); manlo <= conv_std_logic_vector(133160968,28); exponent <= conv_std_logic_vector(1501,11); WHEN "0101001101" => manhi <= conv_std_logic_vector(5629822,24); manlo <= conv_std_logic_vector(4574050,28); exponent <= conv_std_logic_vector(1503,11); WHEN "0101001110" => manhi <= conv_std_logic_vector(13677106,24); manlo <= conv_std_logic_vector(36414601,28); exponent <= conv_std_logic_vector(1504,11); WHEN "0101001111" => manhi <= conv_std_logic_vector(3918641,24); manlo <= conv_std_logic_vector(165046798,28); exponent <= conv_std_logic_vector(1506,11); WHEN "0101010000" => manhi <= conv_std_logic_vector(11351370,24); manlo <= conv_std_logic_vector(225326735,28); exponent <= conv_std_logic_vector(1507,11); WHEN "0101010001" => manhi <= conv_std_logic_vector(2338140,24); manlo <= conv_std_logic_vector(165476611,28); exponent <= conv_std_logic_vector(1509,11); WHEN "0101010010" => manhi <= conv_std_logic_vector(9203247,24); manlo <= conv_std_logic_vector(71807303,28); exponent <= conv_std_logic_vector(1510,11); WHEN "0101010011" => manhi <= conv_std_logic_vector(878339,24); manlo <= conv_std_logic_vector(80195176,28); exponent <= conv_std_logic_vector(1512,11); WHEN "0101010100" => manhi <= conv_std_logic_vector(7219171,24); manlo <= conv_std_logic_vector(153001068,28); exponent <= conv_std_logic_vector(1513,11); WHEN "0101010101" => manhi <= conv_std_logic_vector(15837256,24); manlo <= conv_std_logic_vector(37596960,28); exponent <= conv_std_logic_vector(1514,11); WHEN "0101010110" => manhi <= conv_std_logic_vector(5386615,24); manlo <= conv_std_logic_vector(198850796,28); exponent <= conv_std_logic_vector(1516,11); WHEN "0101010111" => manhi <= conv_std_logic_vector(13346554,24); manlo <= conv_std_logic_vector(143609986,28); exponent <= conv_std_logic_vector(1517,11); WHEN "0101011000" => manhi <= conv_std_logic_vector(3694008,24); manlo <= conv_std_logic_vector(137568494,28); exponent <= conv_std_logic_vector(1519,11); WHEN "0101011001" => manhi <= conv_std_logic_vector(11046062,24); manlo <= conv_std_logic_vector(214558683,28); exponent <= conv_std_logic_vector(1520,11); WHEN "0101011010" => manhi <= conv_std_logic_vector(2130662,24); manlo <= conv_std_logic_vector(78401205,28); exponent <= conv_std_logic_vector(1522,11); WHEN "0101011011" => manhi <= conv_std_logic_vector(8921254,24); manlo <= conv_std_logic_vector(265219821,28); exponent <= conv_std_logic_vector(1523,11); WHEN "0101011100" => manhi <= conv_std_logic_vector(686705,24); manlo <= conv_std_logic_vector(181591149,28); exponent <= conv_std_logic_vector(1525,11); WHEN "0101011101" => manhi <= conv_std_logic_vector(6958714,24); manlo <= conv_std_logic_vector(127078273,28); exponent <= conv_std_logic_vector(1526,11); WHEN "0101011110" => manhi <= conv_std_logic_vector(15483258,24); manlo <= conv_std_logic_vector(65420394,28); exponent <= conv_std_logic_vector(1527,11); WHEN "0101011111" => manhi <= conv_std_logic_vector(5146049,24); manlo <= conv_std_logic_vector(61347424,28); exponent <= conv_std_logic_vector(1529,11); WHEN "0101100000" => manhi <= conv_std_logic_vector(13019590,24); manlo <= conv_std_logic_vector(200148168,28); exponent <= conv_std_logic_vector(1530,11); WHEN "0101100001" => manhi <= conv_std_logic_vector(3471813,24); manlo <= conv_std_logic_vector(155873600,28); exponent <= conv_std_logic_vector(1532,11); WHEN "0101100010" => manhi <= conv_std_logic_vector(10744068,24); manlo <= conv_std_logic_vector(154763366,28); exponent <= conv_std_logic_vector(1533,11); WHEN "0101100011" => manhi <= conv_std_logic_vector(1925435,24); manlo <= conv_std_logic_vector(252346422,28); exponent <= conv_std_logic_vector(1535,11); WHEN "0101100100" => manhi <= conv_std_logic_vector(8642323,24); manlo <= conv_std_logic_vector(122496413,28); exponent <= conv_std_logic_vector(1536,11); WHEN "0101100101" => manhi <= conv_std_logic_vector(497152,24); manlo <= conv_std_logic_vector(12881703,28); exponent <= conv_std_logic_vector(1538,11); WHEN "0101100110" => manhi <= conv_std_logic_vector(6701084,24); manlo <= conv_std_logic_vector(102402698,28); exponent <= conv_std_logic_vector(1539,11); WHEN "0101100111" => manhi <= conv_std_logic_vector(15133102,24); manlo <= conv_std_logic_vector(173151546,28); exponent <= conv_std_logic_vector(1540,11); WHEN "0101101000" => manhi <= conv_std_logic_vector(4908093,24); manlo <= conv_std_logic_vector(222341698,28); exponent <= conv_std_logic_vector(1542,11); WHEN "0101101001" => manhi <= conv_std_logic_vector(12696175,24); manlo <= conv_std_logic_vector(221558290,28); exponent <= conv_std_logic_vector(1543,11); WHEN "0101101010" => manhi <= conv_std_logic_vector(3252030,24); manlo <= conv_std_logic_vector(95425703,28); exponent <= conv_std_logic_vector(1545,11); WHEN "0101101011" => manhi <= conv_std_logic_vector(10445352,24); manlo <= conv_std_logic_vector(54472775,28); exponent <= conv_std_logic_vector(1546,11); WHEN "0101101100" => manhi <= conv_std_logic_vector(1722437,24); manlo <= conv_std_logic_vector(31541381,28); exponent <= conv_std_logic_vector(1548,11); WHEN "0101101101" => manhi <= conv_std_logic_vector(8366419,24); manlo <= conv_std_logic_vector(121077564,28); exponent <= conv_std_logic_vector(1549,11); WHEN "0101101110" => manhi <= conv_std_logic_vector(309655,24); manlo <= conv_std_logic_vector(224679493,28); exponent <= conv_std_logic_vector(1551,11); WHEN "0101101111" => manhi <= conv_std_logic_vector(6446250,24); manlo <= conv_std_logic_vector(163707479,28); exponent <= conv_std_logic_vector(1552,11); WHEN "0101110000" => manhi <= conv_std_logic_vector(14786747,24); manlo <= conv_std_logic_vector(171718440,28); exponent <= conv_std_logic_vector(1553,11); WHEN "0101110001" => manhi <= conv_std_logic_vector(4672721,24); manlo <= conv_std_logic_vector(53414720,28); exponent <= conv_std_logic_vector(1555,11); WHEN "0101110010" => manhi <= conv_std_logic_vector(12376271,24); manlo <= conv_std_logic_vector(68395953,28); exponent <= conv_std_logic_vector(1556,11); WHEN "0101110011" => manhi <= conv_std_logic_vector(3034632,24); manlo <= conv_std_logic_vector(177229210,28); exponent <= conv_std_logic_vector(1558,11); WHEN "0101110100" => manhi <= conv_std_logic_vector(10149878,24); manlo <= conv_std_logic_vector(27015960,28); exponent <= conv_std_logic_vector(1559,11); WHEN "0101110101" => manhi <= conv_std_logic_vector(1521641,24); manlo <= conv_std_logic_vector(173609470,28); exponent <= conv_std_logic_vector(1561,11); WHEN "0101110110" => manhi <= conv_std_logic_vector(8093510,24); manlo <= conv_std_logic_vector(29891310,28); exponent <= conv_std_logic_vector(1562,11); WHEN "0101110111" => manhi <= conv_std_logic_vector(124194,24); manlo <= conv_std_logic_vector(191198183,28); exponent <= conv_std_logic_vector(1564,11); WHEN "0101111000" => manhi <= conv_std_logic_vector(6194182,24); manlo <= conv_std_logic_vector(216692261,28); exponent <= conv_std_logic_vector(1565,11); WHEN "0101111001" => manhi <= conv_std_logic_vector(14444151,24); manlo <= conv_std_logic_vector(261994424,28); exponent <= conv_std_logic_vector(1566,11); WHEN "0101111010" => manhi <= conv_std_logic_vector(4439903,24); manlo <= conv_std_logic_vector(82463931,28); exponent <= conv_std_logic_vector(1568,11); WHEN "0101111011" => manhi <= conv_std_logic_vector(12059838,24); manlo <= conv_std_logic_vector(250318074,28); exponent <= conv_std_logic_vector(1569,11); WHEN "0101111100" => manhi <= conv_std_logic_vector(2819594,24); manlo <= conv_std_logic_vector(161686084,28); exponent <= conv_std_logic_vector(1571,11); WHEN "0101111101" => manhi <= conv_std_logic_vector(9857611,24); manlo <= conv_std_logic_vector(20946108,28); exponent <= conv_std_logic_vector(1572,11); WHEN "0101111110" => manhi <= conv_std_logic_vector(1323025,24); manlo <= conv_std_logic_vector(164440795,28); exponent <= conv_std_logic_vector(1574,11); WHEN "0101111111" => manhi <= conv_std_logic_vector(7823562,24); manlo <= conv_std_logic_vector(250479918,28); exponent <= conv_std_logic_vector(1575,11); WHEN "0110000000" => manhi <= conv_std_logic_vector(16658709,24); manlo <= conv_std_logic_vector(45608811,28); exponent <= conv_std_logic_vector(1576,11); WHEN "0110000001" => manhi <= conv_std_logic_vector(5944850,24); manlo <= conv_std_logic_vector(255488281,28); exponent <= conv_std_logic_vector(1578,11); WHEN "0110000010" => manhi <= conv_std_logic_vector(14105274,24); manlo <= conv_std_logic_vector(228172930,28); exponent <= conv_std_logic_vector(1579,11); WHEN "0110000011" => manhi <= conv_std_logic_vector(4209612,24); manlo <= conv_std_logic_vector(113758652,28); exponent <= conv_std_logic_vector(1581,11); WHEN "0110000100" => manhi <= conv_std_logic_vector(11746841,24); manlo <= conv_std_logic_vector(45816542,28); exponent <= conv_std_logic_vector(1582,11); WHEN "0110000101" => manhi <= conv_std_logic_vector(2606890,24); manlo <= conv_std_logic_vector(153074390,28); exponent <= conv_std_logic_vector(1584,11); WHEN "0110000110" => manhi <= conv_std_logic_vector(9568516,24); manlo <= conv_std_logic_vector(87350878,28); exponent <= conv_std_logic_vector(1585,11); WHEN "0110000111" => manhi <= conv_std_logic_vector(1126565,24); manlo <= conv_std_logic_vector(96475766,28); exponent <= conv_std_logic_vector(1587,11); WHEN "0110001000" => manhi <= conv_std_logic_vector(7556545,24); manlo <= conv_std_logic_vector(205347948,28); exponent <= conv_std_logic_vector(1588,11); WHEN "0110001001" => manhi <= conv_std_logic_vector(16295795,24); manlo <= conv_std_logic_vector(56881285,28); exponent <= conv_std_logic_vector(1589,11); WHEN "0110001010" => manhi <= conv_std_logic_vector(5698225,24); manlo <= conv_std_logic_vector(93263076,28); exponent <= conv_std_logic_vector(1591,11); WHEN "0110001011" => manhi <= conv_std_logic_vector(13770075,24); manlo <= conv_std_logic_vector(241769289,28); exponent <= conv_std_logic_vector(1592,11); WHEN "0110001100" => manhi <= conv_std_logic_vector(3981821,24); manlo <= conv_std_logic_vector(32359920,28); exponent <= conv_std_logic_vector(1594,11); WHEN "0110001101" => manhi <= conv_std_logic_vector(11437240,24); manlo <= conv_std_logic_vector(185367850,28); exponent <= conv_std_logic_vector(1595,11); WHEN "0110001110" => manhi <= conv_std_logic_vector(2396495,24); manlo <= conv_std_logic_vector(61858550,28); exponent <= conv_std_logic_vector(1597,11); WHEN "0110001111" => manhi <= conv_std_logic_vector(9282559,24); manlo <= conv_std_logic_vector(110304027,28); exponent <= conv_std_logic_vector(1598,11); WHEN "0110010000" => manhi <= conv_std_logic_vector(932237,24); manlo <= conv_std_logic_vector(131077892,28); exponent <= conv_std_logic_vector(1600,11); WHEN "0110010001" => manhi <= conv_std_logic_vector(7292426,24); manlo <= conv_std_logic_vector(215982528,28); exponent <= conv_std_logic_vector(1601,11); WHEN "0110010010" => manhi <= conv_std_logic_vector(15936820,24); manlo <= conv_std_logic_vector(87676082,28); exponent <= conv_std_logic_vector(1602,11); WHEN "0110010011" => manhi <= conv_std_logic_vector(5454276,24); manlo <= conv_std_logic_vector(166577430,28); exponent <= conv_std_logic_vector(1604,11); WHEN "0110010100" => manhi <= conv_std_logic_vector(13438515,24); manlo <= conv_std_logic_vector(55023964,28); exponent <= conv_std_logic_vector(1605,11); WHEN "0110010101" => manhi <= conv_std_logic_vector(3756502,24); manlo <= conv_std_logic_vector(71679026,28); exponent <= conv_std_logic_vector(1607,11); WHEN "0110010110" => manhi <= conv_std_logic_vector(11131000,24); manlo <= conv_std_logic_vector(165886683,28); exponent <= conv_std_logic_vector(1608,11); WHEN "0110010111" => manhi <= conv_std_logic_vector(2188383,24); manlo <= conv_std_logic_vector(140750309,28); exponent <= conv_std_logic_vector(1610,11); WHEN "0110011000" => manhi <= conv_std_logic_vector(8999706,24); manlo <= conv_std_logic_vector(74200045,28); exponent <= conv_std_logic_vector(1611,11); WHEN "0110011001" => manhi <= conv_std_logic_vector(740018,24); manlo <= conv_std_logic_vector(229350227,28); exponent <= conv_std_logic_vector(1613,11); WHEN "0110011010" => manhi <= conv_std_logic_vector(7031174,24); manlo <= conv_std_logic_vector(159659309,28); exponent <= conv_std_logic_vector(1614,11); WHEN "0110011011" => manhi <= conv_std_logic_vector(15581741,24); manlo <= conv_std_logic_vector(203828183,28); exponent <= conv_std_logic_vector(1615,11); WHEN "0110011100" => manhi <= conv_std_logic_vector(5212975,24); manlo <= conv_std_logic_vector(192268981,28); exponent <= conv_std_logic_vector(1617,11); WHEN "0110011101" => manhi <= conv_std_logic_vector(13110553,24); manlo <= conv_std_logic_vector(73367990,28); exponent <= conv_std_logic_vector(1618,11); WHEN "0110011110" => manhi <= conv_std_logic_vector(3533629,24); manlo <= conv_std_logic_vector(7303751,28); exponent <= conv_std_logic_vector(1620,11); WHEN "0110011111" => manhi <= conv_std_logic_vector(10828084,24); manlo <= conv_std_logic_vector(128595197,28); exponent <= conv_std_logic_vector(1621,11); WHEN "0110100000" => manhi <= conv_std_logic_vector(1982530,24); manlo <= conv_std_logic_vector(178601213,28); exponent <= conv_std_logic_vector(1623,11); WHEN "0110100001" => manhi <= conv_std_logic_vector(8719923,24); manlo <= conv_std_logic_vector(62665264,28); exponent <= conv_std_logic_vector(1624,11); WHEN "0110100010" => manhi <= conv_std_logic_vector(549886,24); manlo <= conv_std_logic_vector(151395401,28); exponent <= conv_std_logic_vector(1626,11); WHEN "0110100011" => manhi <= conv_std_logic_vector(6772758,24); manlo <= conv_std_logic_vector(5307652,28); exponent <= conv_std_logic_vector(1627,11); WHEN "0110100100" => manhi <= conv_std_logic_vector(15230517,24); manlo <= conv_std_logic_vector(58871965,28); exponent <= conv_std_logic_vector(1628,11); WHEN "0110100101" => manhi <= conv_std_logic_vector(4974293,24); manlo <= conv_std_logic_vector(240265124,28); exponent <= conv_std_logic_vector(1630,11); WHEN "0110100110" => manhi <= conv_std_logic_vector(12786151,24); manlo <= conv_std_logic_vector(11983156,28); exponent <= conv_std_logic_vector(1631,11); WHEN "0110100111" => manhi <= conv_std_logic_vector(3313174,24); manlo <= conv_std_logic_vector(229882212,28); exponent <= conv_std_logic_vector(1633,11); WHEN "0110101000" => manhi <= conv_std_logic_vector(10528456,24); manlo <= conv_std_logic_vector(52550536,28); exponent <= conv_std_logic_vector(1634,11); WHEN "0110101001" => manhi <= conv_std_logic_vector(1778912,24); manlo <= conv_std_logic_vector(36481057,28); exponent <= conv_std_logic_vector(1636,11); WHEN "0110101010" => manhi <= conv_std_logic_vector(8443176,24); manlo <= conv_std_logic_vector(257480801,28); exponent <= conv_std_logic_vector(1637,11); WHEN "0110101011" => manhi <= conv_std_logic_vector(361817,24); manlo <= conv_std_logic_vector(260890045,28); exponent <= conv_std_logic_vector(1639,11); WHEN "0110101100" => manhi <= conv_std_logic_vector(6517146,24); manlo <= conv_std_logic_vector(80951272,28); exponent <= conv_std_logic_vector(1640,11); WHEN "0110101101" => manhi <= conv_std_logic_vector(14883104,24); manlo <= conv_std_logic_vector(234866389,28); exponent <= conv_std_logic_vector(1641,11); WHEN "0110101110" => manhi <= conv_std_logic_vector(4738202,24); manlo <= conv_std_logic_vector(195793257,28); exponent <= conv_std_logic_vector(1643,11); WHEN "0110101111" => manhi <= conv_std_logic_vector(12465269,24); manlo <= conv_std_logic_vector(236730454,28); exponent <= conv_std_logic_vector(1644,11); WHEN "0110110000" => manhi <= conv_std_logic_vector(3095113,24); manlo <= conv_std_logic_vector(133661452,28); exponent <= conv_std_logic_vector(1646,11); WHEN "0110110001" => manhi <= conv_std_logic_vector(10232080,24); manlo <= conv_std_logic_vector(21926822,28); exponent <= conv_std_logic_vector(1647,11); WHEN "0110110010" => manhi <= conv_std_logic_vector(1577503,24); manlo <= conv_std_logic_vector(183764948,28); exponent <= conv_std_logic_vector(1649,11); WHEN "0110110011" => manhi <= conv_std_logic_vector(8169434,24); manlo <= conv_std_logic_vector(132210812,28); exponent <= conv_std_logic_vector(1650,11); WHEN "0110110100" => manhi <= conv_std_logic_vector(175790,24); manlo <= conv_std_logic_vector(182183516,28); exponent <= conv_std_logic_vector(1652,11); WHEN "0110110101" => manhi <= conv_std_logic_vector(6264308,24); manlo <= conv_std_logic_vector(267417858,28); exponent <= conv_std_logic_vector(1653,11); WHEN "0110110110" => manhi <= conv_std_logic_vector(14539463,24); manlo <= conv_std_logic_vector(93573944,28); exponent <= conv_std_logic_vector(1654,11); WHEN "0110110111" => manhi <= conv_std_logic_vector(4504674,24); manlo <= conv_std_logic_vector(26907375,28); exponent <= conv_std_logic_vector(1656,11); WHEN "0110111000" => manhi <= conv_std_logic_vector(12147871,24); manlo <= conv_std_logic_vector(152302066,28); exponent <= conv_std_logic_vector(1657,11); WHEN "0110111001" => manhi <= conv_std_logic_vector(2879418,24); manlo <= conv_std_logic_vector(263131635,28); exponent <= conv_std_logic_vector(1659,11); WHEN "0110111010" => manhi <= conv_std_logic_vector(9938920,24); manlo <= conv_std_logic_vector(224874222,28); exponent <= conv_std_logic_vector(1660,11); WHEN "0110111011" => manhi <= conv_std_logic_vector(1378281,24); manlo <= conv_std_logic_vector(86745210,28); exponent <= conv_std_logic_vector(1662,11); WHEN "0110111100" => manhi <= conv_std_logic_vector(7898663,24); manlo <= conv_std_logic_vector(61761420,28); exponent <= conv_std_logic_vector(1663,11); WHEN "0110111101" => manhi <= conv_std_logic_vector(16760781,24); manlo <= conv_std_logic_vector(15082626,28); exponent <= conv_std_logic_vector(1664,11); WHEN "0110111110" => manhi <= conv_std_logic_vector(6014215,24); manlo <= conv_std_logic_vector(265801199,28); exponent <= conv_std_logic_vector(1666,11); WHEN "0110111111" => manhi <= conv_std_logic_vector(14199551,24); manlo <= conv_std_logic_vector(191056853,28); exponent <= conv_std_logic_vector(1667,11); WHEN "0111000000" => manhi <= conv_std_logic_vector(4273680,24); manlo <= conv_std_logic_vector(52024524,28); exponent <= conv_std_logic_vector(1669,11); WHEN "0111000001" => manhi <= conv_std_logic_vector(11833918,24); manlo <= conv_std_logic_vector(80047690,28); exponent <= conv_std_logic_vector(1670,11); WHEN "0111000010" => manhi <= conv_std_logic_vector(2666065,24); manlo <= conv_std_logic_vector(164712049,28); exponent <= conv_std_logic_vector(1672,11); WHEN "0111000011" => manhi <= conv_std_logic_vector(9648943,24); manlo <= conv_std_logic_vector(147084012,28); exponent <= conv_std_logic_vector(1673,11); WHEN "0111000100" => manhi <= conv_std_logic_vector(1181221,24); manlo <= conv_std_logic_vector(86912647,28); exponent <= conv_std_logic_vector(1675,11); WHEN "0111000101" => manhi <= conv_std_logic_vector(7630830,24); manlo <= conv_std_logic_vector(247596521,28); exponent <= conv_std_logic_vector(1676,11); WHEN "0111000110" => manhi <= conv_std_logic_vector(16396759,24); manlo <= conv_std_logic_vector(56002502,28); exponent <= conv_std_logic_vector(1677,11); WHEN "0111000111" => manhi <= conv_std_logic_vector(5766837,24); manlo <= conv_std_logic_vector(133369322,28); exponent <= conv_std_logic_vector(1679,11); WHEN "0111001000" => manhi <= conv_std_logic_vector(13863329,24); manlo <= conv_std_logic_vector(128884889,28); exponent <= conv_std_logic_vector(1680,11); WHEN "0111001001" => manhi <= conv_std_logic_vector(4045193,24); manlo <= conv_std_logic_vector(133729186,28); exponent <= conv_std_logic_vector(1682,11); WHEN "0111001010" => manhi <= conv_std_logic_vector(11523372,24); manlo <= conv_std_logic_vector(183024104,28); exponent <= conv_std_logic_vector(1683,11); WHEN "0111001011" => manhi <= conv_std_logic_vector(2455027,24); manlo <= conv_std_logic_vector(264977965,28); exponent <= conv_std_logic_vector(1685,11); WHEN "0111001100" => manhi <= conv_std_logic_vector(9362113,24); manlo <= conv_std_logic_vector(181285013,28); exponent <= conv_std_logic_vector(1686,11); WHEN "0111001101" => manhi <= conv_std_logic_vector(986300,24); manlo <= conv_std_logic_vector(58020653,28); exponent <= conv_std_logic_vector(1688,11); WHEN "0111001110" => manhi <= conv_std_logic_vector(7365905,24); manlo <= conv_std_logic_vector(179835810,28); exponent <= conv_std_logic_vector(1689,11); WHEN "0111001111" => manhi <= conv_std_logic_vector(16036688,24); manlo <= conv_std_logic_vector(123168298,28); exponent <= conv_std_logic_vector(1690,11); WHEN "0111010000" => manhi <= conv_std_logic_vector(5522144,24); manlo <= conv_std_logic_vector(14176725,28); exponent <= conv_std_logic_vector(1692,11); WHEN "0111010001" => manhi <= conv_std_logic_vector(13530756,24); manlo <= conv_std_logic_vector(163453775,28); exponent <= conv_std_logic_vector(1693,11); WHEN "0111010010" => manhi <= conv_std_logic_vector(3819186,24); manlo <= conv_std_logic_vector(214764608,28); exponent <= conv_std_logic_vector(1695,11); WHEN "0111010011" => manhi <= conv_std_logic_vector(11216197,24); manlo <= conv_std_logic_vector(196364225,28); exponent <= conv_std_logic_vector(1696,11); WHEN "0111010100" => manhi <= conv_std_logic_vector(2246280,24); manlo <= conv_std_logic_vector(259235483,28); exponent <= conv_std_logic_vector(1698,11); WHEN "0111010101" => manhi <= conv_std_logic_vector(9078397,24); manlo <= conv_std_logic_vector(15526664,28); exponent <= conv_std_logic_vector(1699,11); WHEN "0111010110" => manhi <= conv_std_logic_vector(793494,24); manlo <= conv_std_logic_vector(210641201,28); exponent <= conv_std_logic_vector(1701,11); WHEN "0111010111" => manhi <= conv_std_logic_vector(7103855,24); manlo <= conv_std_logic_vector(246847656,28); exponent <= conv_std_logic_vector(1702,11); WHEN "0111011000" => manhi <= conv_std_logic_vector(15680525,24); manlo <= conv_std_logic_vector(247378795,28); exponent <= conv_std_logic_vector(1703,11); WHEN "0111011001" => manhi <= conv_std_logic_vector(5280106,24); manlo <= conv_std_logic_vector(138122391,28); exponent <= conv_std_logic_vector(1705,11); WHEN "0111011010" => manhi <= conv_std_logic_vector(13201793,24); manlo <= conv_std_logic_vector(130963079,28); exponent <= conv_std_logic_vector(1706,11); WHEN "0111011011" => manhi <= conv_std_logic_vector(3595633,24); manlo <= conv_std_logic_vector(48727293,28); exponent <= conv_std_logic_vector(1708,11); WHEN "0111011100" => manhi <= conv_std_logic_vector(10912356,24); manlo <= conv_std_logic_vector(231400966,28); exponent <= conv_std_logic_vector(1709,11); WHEN "0111011101" => manhi <= conv_std_logic_vector(2039799,24); manlo <= conv_std_logic_vector(184459756,28); exponent <= conv_std_logic_vector(1711,11); WHEN "0111011110" => manhi <= conv_std_logic_vector(8797759,24); manlo <= conv_std_logic_vector(242699544,28); exponent <= conv_std_logic_vector(1712,11); WHEN "0111011111" => manhi <= conv_std_logic_vector(602782,24); manlo <= conv_std_logic_vector(17680793,28); exponent <= conv_std_logic_vector(1714,11); WHEN "0111100000" => manhi <= conv_std_logic_vector(6844650,24); manlo <= conv_std_logic_vector(123627565,28); exponent <= conv_std_logic_vector(1715,11); WHEN "0111100001" => manhi <= conv_std_logic_vector(15328229,24); manlo <= conv_std_logic_vector(47512453,28); exponent <= conv_std_logic_vector(1716,11); WHEN "0111100010" => manhi <= conv_std_logic_vector(5040696,24); manlo <= conv_std_logic_vector(14711664,28); exponent <= conv_std_logic_vector(1718,11); WHEN "0111100011" => manhi <= conv_std_logic_vector(12876400,24); manlo <= conv_std_logic_vector(251456186,28); exponent <= conv_std_logic_vector(1719,11); WHEN "0111100100" => manhi <= conv_std_logic_vector(3374506,24); manlo <= conv_std_logic_vector(4512772,28); exponent <= conv_std_logic_vector(1721,11); WHEN "0111100101" => manhi <= conv_std_logic_vector(10611813,24); manlo <= conv_std_logic_vector(237626642,28); exponent <= conv_std_logic_vector(1722,11); WHEN "0111100110" => manhi <= conv_std_logic_vector(1835559,24); manlo <= conv_std_logic_vector(150064655,28); exponent <= conv_std_logic_vector(1724,11); WHEN "0111100111" => manhi <= conv_std_logic_vector(8520168,24); manlo <= conv_std_logic_vector(211971382,28); exponent <= conv_std_logic_vector(1725,11); WHEN "0111101000" => manhi <= conv_std_logic_vector(414139,24); manlo <= conv_std_logic_vector(92694471,28); exponent <= conv_std_logic_vector(1727,11); WHEN "0111101001" => manhi <= conv_std_logic_vector(6588258,24); manlo <= conv_std_logic_vector(112977613,28); exponent <= conv_std_logic_vector(1728,11); WHEN "0111101010" => manhi <= conv_std_logic_vector(14979756,24); manlo <= conv_std_logic_vector(71348470,28); exponent <= conv_std_logic_vector(1729,11); WHEN "0111101011" => manhi <= conv_std_logic_vector(4803884,24); manlo <= conv_std_logic_vector(42747344,28); exponent <= conv_std_logic_vector(1731,11); WHEN "0111101100" => manhi <= conv_std_logic_vector(12554540,24); manlo <= conv_std_logic_vector(53825836,28); exponent <= conv_std_logic_vector(1732,11); WHEN "0111101101" => manhi <= conv_std_logic_vector(3155778,24); manlo <= conv_std_logic_vector(260157975,28); exponent <= conv_std_logic_vector(1734,11); WHEN "0111101110" => manhi <= conv_std_logic_vector(10314533,24); manlo <= conv_std_logic_vector(1535990,28); exponent <= conv_std_logic_vector(1735,11); WHEN "0111101111" => manhi <= conv_std_logic_vector(1633536,24); manlo <= conv_std_logic_vector(68681060,28); exponent <= conv_std_logic_vector(1737,11); WHEN "0111110000" => manhi <= conv_std_logic_vector(8245590,24); manlo <= conv_std_logic_vector(175202070,28); exponent <= conv_std_logic_vector(1738,11); WHEN "0111110001" => manhi <= conv_std_logic_vector(227544,24); manlo <= conv_std_logic_vector(41675965,28); exponent <= conv_std_logic_vector(1740,11); WHEN "0111110010" => manhi <= conv_std_logic_vector(6334649,24); manlo <= conv_std_logic_vector(70777607,28); exponent <= conv_std_logic_vector(1741,11); WHEN "0111110011" => manhi <= conv_std_logic_vector(14635065,24); manlo <= conv_std_logic_vector(183612561,28); exponent <= conv_std_logic_vector(1742,11); WHEN "0111110100" => manhi <= conv_std_logic_vector(4569642,24); manlo <= conv_std_logic_vector(167240760,28); exponent <= conv_std_logic_vector(1744,11); WHEN "0111110101" => manhi <= conv_std_logic_vector(12236172,24); manlo <= conv_std_logic_vector(253623266,28); exponent <= conv_std_logic_vector(1745,11); WHEN "0111110110" => manhi <= conv_std_logic_vector(2939425,24); manlo <= conv_std_logic_vector(265128301,28); exponent <= conv_std_logic_vector(1747,11); WHEN "0111110111" => manhi <= conv_std_logic_vector(10020478,24); manlo <= conv_std_logic_vector(219223569,28); exponent <= conv_std_logic_vector(1748,11); WHEN "0111111000" => manhi <= conv_std_logic_vector(1433705,24); manlo <= conv_std_logic_vector(192250058,28); exponent <= conv_std_logic_vector(1750,11); WHEN "0111111001" => manhi <= conv_std_logic_vector(7973992,24); manlo <= conv_std_logic_vector(212144821,28); exponent <= conv_std_logic_vector(1751,11); WHEN "0111111010" => manhi <= conv_std_logic_vector(42974,24); manlo <= conv_std_logic_vector(72952107,28); exponent <= conv_std_logic_vector(1753,11); WHEN "0111111011" => manhi <= conv_std_logic_vector(6083792,24); manlo <= conv_std_logic_vector(210315148,28); exponent <= conv_std_logic_vector(1754,11); WHEN "0111111100" => manhi <= conv_std_logic_vector(14294116,24); manlo <= conv_std_logic_vector(101520926,28); exponent <= conv_std_logic_vector(1755,11); WHEN "0111111101" => manhi <= conv_std_logic_vector(4337943,24); manlo <= conv_std_logic_vector(146945490,28); exponent <= conv_std_logic_vector(1757,11); WHEN "0111111110" => manhi <= conv_std_logic_vector(11921261,24); manlo <= conv_std_logic_vector(67478049,28); exponent <= conv_std_logic_vector(1758,11); WHEN "0111111111" => manhi <= conv_std_logic_vector(2725421,24); manlo <= conv_std_logic_vector(81662013,28); exponent <= conv_std_logic_vector(1760,11); WHEN "1000000000" => manhi <= conv_std_logic_vector(9729616,24); manlo <= conv_std_logic_vector(79332654,28); exponent <= conv_std_logic_vector(1761,11); WHEN "1000000001" => manhi <= conv_std_logic_vector(1236044,24); manlo <= conv_std_logic_vector(37511845,28); exponent <= conv_std_logic_vector(1763,11); WHEN "1000000010" => manhi <= conv_std_logic_vector(7705342,24); manlo <= conv_std_logic_vector(229400607,28); exponent <= conv_std_logic_vector(1764,11); WHEN "1000000011" => manhi <= conv_std_logic_vector(16498031,24); manlo <= conv_std_logic_vector(113896411,28); exponent <= conv_std_logic_vector(1765,11); WHEN "1000000100" => manhi <= conv_std_logic_vector(5835659,24); manlo <= conv_std_logic_vector(27578100,28); exponent <= conv_std_logic_vector(1767,11); WHEN "1000000101" => manhi <= conv_std_logic_vector(13956867,24); manlo <= conv_std_logic_vector(198774093,28); exponent <= conv_std_logic_vector(1768,11); WHEN "1000000110" => manhi <= conv_std_logic_vector(4108759,24); manlo <= conv_std_logic_vector(90336304,28); exponent <= conv_std_logic_vector(1770,11); WHEN "1000000111" => manhi <= conv_std_logic_vector(11609767,24); manlo <= conv_std_logic_vector(164675818,28); exponent <= conv_std_logic_vector(1771,11); WHEN "1000001000" => manhi <= conv_std_logic_vector(2513739,24); manlo <= conv_std_logic_vector(115510945,28); exponent <= conv_std_logic_vector(1773,11); WHEN "1000001001" => manhi <= conv_std_logic_vector(9441910,24); manlo <= conv_std_logic_vector(214725537,28); exponent <= conv_std_logic_vector(1774,11); WHEN "1000001010" => manhi <= conv_std_logic_vector(1040527,24); manlo <= conv_std_logic_vector(264292986,28); exponent <= conv_std_logic_vector(1776,11); WHEN "1000001011" => manhi <= conv_std_logic_vector(7439608,24); manlo <= conv_std_logic_vector(227819416,28); exponent <= conv_std_logic_vector(1777,11); WHEN "1000001100" => manhi <= conv_std_logic_vector(16136861,24); manlo <= conv_std_logic_vector(124712281,28); exponent <= conv_std_logic_vector(1778,11); WHEN "1000001101" => manhi <= conv_std_logic_vector(5590218,24); manlo <= conv_std_logic_vector(179347558,28); exponent <= conv_std_logic_vector(1780,11); WHEN "1000001110" => manhi <= conv_std_logic_vector(13623279,24); manlo <= conv_std_logic_vector(162081347,28); exponent <= conv_std_logic_vector(1781,11); WHEN "1000001111" => manhi <= conv_std_logic_vector(3882062,24); manlo <= conv_std_logic_vector(186291443,28); exponent <= conv_std_logic_vector(1783,11); WHEN "1000010000" => manhi <= conv_std_logic_vector(11301654,24); manlo <= conv_std_logic_vector(250040022,28); exponent <= conv_std_logic_vector(1784,11); WHEN "1000010001" => manhi <= conv_std_logic_vector(2304355,24); manlo <= conv_std_logic_vector(41383777,28); exponent <= conv_std_logic_vector(1786,11); WHEN "1000010010" => manhi <= conv_std_logic_vector(9157328,24); manlo <= conv_std_logic_vector(17021400,28); exponent <= conv_std_logic_vector(1787,11); WHEN "1000010011" => manhi <= conv_std_logic_vector(847133,24); manlo <= conv_std_logic_vector(258834653,28); exponent <= conv_std_logic_vector(1789,11); WHEN "1000010100" => manhi <= conv_std_logic_vector(7176759,24); manlo <= conv_std_logic_vector(33041815,28); exponent <= conv_std_logic_vector(1790,11); WHEN "1000010101" => manhi <= conv_std_logic_vector(15779611,24); manlo <= conv_std_logic_vector(174007449,28); exponent <= conv_std_logic_vector(1791,11); WHEN "1000010110" => manhi <= conv_std_logic_vector(5347442,24); manlo <= conv_std_logic_vector(66333886,28); exponent <= conv_std_logic_vector(1793,11); WHEN "1000010111" => manhi <= conv_std_logic_vector(13293312,24); manlo <= conv_std_logic_vector(63618366,28); exponent <= conv_std_logic_vector(1794,11); WHEN "1000011000" => manhi <= conv_std_logic_vector(3657826,24); manlo <= conv_std_logic_vector(166348998,28); exponent <= conv_std_logic_vector(1796,11); WHEN "1000011001" => manhi <= conv_std_logic_vector(10996886,24); manlo <= conv_std_logic_vector(136487624,28); exponent <= conv_std_logic_vector(1797,11); WHEN "1000011010" => manhi <= conv_std_logic_vector(2097243,24); manlo <= conv_std_logic_vector(144317262,28); exponent <= conv_std_logic_vector(1799,11); WHEN "1000011011" => manhi <= conv_std_logic_vector(8875834,24); manlo <= conv_std_logic_vector(51419886,28); exponent <= conv_std_logic_vector(1800,11); WHEN "1000011100" => manhi <= conv_std_logic_vector(655839,24); manlo <= conv_std_logic_vector(12096311,28); exponent <= conv_std_logic_vector(1802,11); WHEN "1000011101" => manhi <= conv_std_logic_vector(6916762,24); manlo <= conv_std_logic_vector(99793437,28); exponent <= conv_std_logic_vector(1803,11); WHEN "1000011110" => manhi <= conv_std_logic_vector(15426239,24); manlo <= conv_std_logic_vector(114334116,28); exponent <= conv_std_logic_vector(1804,11); WHEN "1000011111" => manhi <= conv_std_logic_vector(5107300,24); manlo <= conv_std_logic_vector(248161218,28); exponent <= conv_std_logic_vector(1806,11); WHEN "1000100000" => manhi <= conv_std_logic_vector(12966926,24); manlo <= conv_std_logic_vector(91321506,28); exponent <= conv_std_logic_vector(1807,11); WHEN "1000100001" => manhi <= conv_std_logic_vector(3436024,24); manlo <= conv_std_logic_vector(109150055,28); exponent <= conv_std_logic_vector(1809,11); WHEN "1000100010" => manhi <= conv_std_logic_vector(10695426,24); manlo <= conv_std_logic_vector(12291314,28); exponent <= conv_std_logic_vector(1810,11); WHEN "1000100011" => manhi <= conv_std_logic_vector(1892379,24); manlo <= conv_std_logic_vector(245137096,28); exponent <= conv_std_logic_vector(1812,11); WHEN "1000100100" => manhi <= conv_std_logic_vector(8597395,24); manlo <= conv_std_logic_vector(176569250,28); exponent <= conv_std_logic_vector(1813,11); WHEN "1000100101" => manhi <= conv_std_logic_vector(466620,24); manlo <= conv_std_logic_vector(119019308,28); exponent <= conv_std_logic_vector(1815,11); WHEN "1000100110" => manhi <= conv_std_logic_vector(6659587,24); manlo <= conv_std_logic_vector(168706814,28); exponent <= conv_std_logic_vector(1816,11); WHEN "1000100111" => manhi <= conv_std_logic_vector(15076702,24); manlo <= conv_std_logic_vector(190651618,28); exponent <= conv_std_logic_vector(1817,11); WHEN "1000101000" => manhi <= conv_std_logic_vector(4869766,24); manlo <= conv_std_logic_vector(26523901,28); exponent <= conv_std_logic_vector(1819,11); WHEN "1000101001" => manhi <= conv_std_logic_vector(12644083,24); manlo <= conv_std_logic_vector(10760420,28); exponent <= conv_std_logic_vector(1820,11); WHEN "1000101010" => manhi <= conv_std_logic_vector(3216629,24); manlo <= conv_std_logic_vector(171149379,28); exponent <= conv_std_logic_vector(1822,11); WHEN "1000101011" => manhi <= conv_std_logic_vector(10397237,24); manlo <= conv_std_logic_vector(171483537,28); exponent <= conv_std_logic_vector(1823,11); WHEN "1000101100" => manhi <= conv_std_logic_vector(1689739,24); manlo <= conv_std_logic_vector(236540182,28); exponent <= conv_std_logic_vector(1825,11); WHEN "1000101101" => manhi <= conv_std_logic_vector(8321979,24); manlo <= conv_std_logic_vector(80365386,28); exponent <= conv_std_logic_vector(1826,11); WHEN "1000101110" => manhi <= conv_std_logic_vector(279455,24); manlo <= conv_std_logic_vector(167185714,28); exponent <= conv_std_logic_vector(1828,11); WHEN "1000101111" => manhi <= conv_std_logic_vector(6405204,24); manlo <= conv_std_logic_vector(70637708,28); exponent <= conv_std_logic_vector(1829,11); WHEN "1000110000" => manhi <= conv_std_logic_vector(14730959,24); manlo <= conv_std_logic_vector(233674466,28); exponent <= conv_std_logic_vector(1830,11); WHEN "1000110001" => manhi <= conv_std_logic_vector(4634809,24); manlo <= conv_std_logic_vector(128626627,28); exponent <= conv_std_logic_vector(1832,11); WHEN "1000110010" => manhi <= conv_std_logic_vector(12324743,24); manlo <= conv_std_logic_vector(237637056,28); exponent <= conv_std_logic_vector(1833,11); WHEN "1000110011" => manhi <= conv_std_logic_vector(2999616,24); manlo <= conv_std_logic_vector(48899908,28); exponent <= conv_std_logic_vector(1835,11); WHEN "1000110100" => manhi <= conv_std_logic_vector(10102285,24); manlo <= conv_std_logic_vector(207402206,28); exponent <= conv_std_logic_vector(1836,11); WHEN "1000110101" => manhi <= conv_std_logic_vector(1489299,24); manlo <= conv_std_logic_vector(82314533,28); exponent <= conv_std_logic_vector(1838,11); WHEN "1000110110" => manhi <= conv_std_logic_vector(8049552,24); manlo <= conv_std_logic_vector(84197942,28); exponent <= conv_std_logic_vector(1839,11); WHEN "1000110111" => manhi <= conv_std_logic_vector(94322,24); manlo <= conv_std_logic_vector(78275083,28); exponent <= conv_std_logic_vector(1841,11); WHEN "1000111000" => manhi <= conv_std_logic_vector(6153581,24); manlo <= conv_std_logic_vector(262556746,28); exponent <= conv_std_logic_vector(1842,11); WHEN "1000111001" => manhi <= conv_std_logic_vector(14388969,24); manlo <= conv_std_logic_vector(195412276,28); exponent <= conv_std_logic_vector(1843,11); WHEN "1000111010" => manhi <= conv_std_logic_vector(4402403,24); manlo <= conv_std_logic_vector(21925377,28); exponent <= conv_std_logic_vector(1845,11); WHEN "1000111011" => manhi <= conv_std_logic_vector(12008870,24); manlo <= conv_std_logic_vector(225943576,28); exponent <= conv_std_logic_vector(1846,11); WHEN "1000111100" => manhi <= conv_std_logic_vector(2784958,24); manlo <= conv_std_logic_vector(51959162,28); exponent <= conv_std_logic_vector(1848,11); WHEN "1000111101" => manhi <= conv_std_logic_vector(9810535,24); manlo <= conv_std_logic_vector(85297068,28); exponent <= conv_std_logic_vector(1849,11); WHEN "1000111110" => manhi <= conv_std_logic_vector(1291034,24); manlo <= conv_std_logic_vector(85003113,28); exponent <= conv_std_logic_vector(1851,11); WHEN "1000111111" => manhi <= conv_std_logic_vector(7780082,24); manlo <= conv_std_logic_vector(68159752,28); exponent <= conv_std_logic_vector(1852,11); WHEN "1001000000" => manhi <= conv_std_logic_vector(16599612,24); manlo <= conv_std_logic_vector(214703512,28); exponent <= conv_std_logic_vector(1853,11); WHEN "1001000001" => manhi <= conv_std_logic_vector(5904690,24); manlo <= conv_std_logic_vector(215968023,28); exponent <= conv_std_logic_vector(1855,11); WHEN "1001000010" => manhi <= conv_std_logic_vector(14050691,24); manlo <= conv_std_logic_vector(147853227,28); exponent <= conv_std_logic_vector(1856,11); WHEN "1001000011" => manhi <= conv_std_logic_vector(4172519,24); manlo <= conv_std_logic_vector(60716388,28); exponent <= conv_std_logic_vector(1858,11); WHEN "1001000100" => manhi <= conv_std_logic_vector(11696426,24); manlo <= conv_std_logic_vector(77359100,28); exponent <= conv_std_logic_vector(1859,11); WHEN "1001000101" => manhi <= conv_std_logic_vector(2572630,24); manlo <= conv_std_logic_vector(28321055,28); exponent <= conv_std_logic_vector(1861,11); WHEN "1001000110" => manhi <= conv_std_logic_vector(9521951,24); manlo <= conv_std_logic_vector(141206574,28); exponent <= conv_std_logic_vector(1862,11); WHEN "1001000111" => manhi <= conv_std_logic_vector(1094921,24); manlo <= conv_std_logic_vector(79834212,28); exponent <= conv_std_logic_vector(1864,11); WHEN "1001001000" => manhi <= conv_std_logic_vector(7513537,24); manlo <= conv_std_logic_vector(6880382,28); exponent <= conv_std_logic_vector(1865,11); WHEN "1001001001" => manhi <= conv_std_logic_vector(16237340,24); manlo <= conv_std_logic_vector(73707069,28); exponent <= conv_std_logic_vector(1866,11); WHEN "1001001010" => manhi <= conv_std_logic_vector(5658501,24); manlo <= conv_std_logic_vector(26563701,28); exponent <= conv_std_logic_vector(1868,11); WHEN "1001001011" => manhi <= conv_std_logic_vector(13716085,24); manlo <= conv_std_logic_vector(13226359,28); exponent <= conv_std_logic_vector(1869,11); WHEN "1001001100" => manhi <= conv_std_logic_vector(3945130,24); manlo <= conv_std_logic_vector(143073903,28); exponent <= conv_std_logic_vector(1871,11); WHEN "1001001101" => manhi <= conv_std_logic_vector(11387373,24); manlo <= conv_std_logic_vector(3175990,28); exponent <= conv_std_logic_vector(1872,11); WHEN "1001001110" => manhi <= conv_std_logic_vector(2362606,24); manlo <= conv_std_logic_vector(168904878,28); exponent <= conv_std_logic_vector(1874,11); WHEN "1001001111" => manhi <= conv_std_logic_vector(9236500,24); manlo <= conv_std_logic_vector(7105104,28); exponent <= conv_std_logic_vector(1875,11); WHEN "1001010000" => manhi <= conv_std_logic_vector(900936,24); manlo <= conv_std_logic_vector(239272854,28); exponent <= conv_std_logic_vector(1877,11); WHEN "1001010001" => manhi <= conv_std_logic_vector(7249884,24); manlo <= conv_std_logic_vector(236935482,28); exponent <= conv_std_logic_vector(1878,11); WHEN "1001010010" => manhi <= conv_std_logic_vector(15878999,24); manlo <= conv_std_logic_vector(230836932,28); exponent <= conv_std_logic_vector(1879,11); WHEN "1001010011" => manhi <= conv_std_logic_vector(5414983,24); manlo <= conv_std_logic_vector(144840810,28); exponent <= conv_std_logic_vector(1881,11); WHEN "1001010100" => manhi <= conv_std_logic_vector(13385110,24); manlo <= conv_std_logic_vector(99584369,28); exponent <= conv_std_logic_vector(1882,11); WHEN "1001010101" => manhi <= conv_std_logic_vector(3720209,24); manlo <= conv_std_logic_vector(246845719,28); exponent <= conv_std_logic_vector(1884,11); WHEN "1001010110" => manhi <= conv_std_logic_vector(11081674,24); manlo <= conv_std_logic_vector(54674652,28); exponent <= conv_std_logic_vector(1885,11); WHEN "1001010111" => manhi <= conv_std_logic_vector(2154862,24); manlo <= conv_std_logic_vector(201440422,28); exponent <= conv_std_logic_vector(1887,11); WHEN "1001011000" => manhi <= conv_std_logic_vector(8954146,24); manlo <= conv_std_logic_vector(220416825,28); exponent <= conv_std_logic_vector(1888,11); WHEN "1001011001" => manhi <= conv_std_logic_vector(709057,24); manlo <= conv_std_logic_vector(266967657,28); exponent <= conv_std_logic_vector(1890,11); WHEN "1001011010" => manhi <= conv_std_logic_vector(6989094,24); manlo <= conv_std_logic_vector(113654547,28); exponent <= conv_std_logic_vector(1891,11); WHEN "1001011011" => manhi <= conv_std_logic_vector(15524548,24); manlo <= conv_std_logic_vector(235342013,28); exponent <= conv_std_logic_vector(1892,11); WHEN "1001011100" => manhi <= conv_std_logic_vector(5174109,24); manlo <= conv_std_logic_vector(32986511,28); exponent <= conv_std_logic_vector(1894,11); WHEN "1001011101" => manhi <= conv_std_logic_vector(13057728,24); manlo <= conv_std_logic_vector(25787653,28); exponent <= conv_std_logic_vector(1895,11); WHEN "1001011110" => manhi <= conv_std_logic_vector(3497730,24); manlo <= conv_std_logic_vector(160351868,28); exponent <= conv_std_logic_vector(1897,11); WHEN "1001011111" => manhi <= conv_std_logic_vector(10779293,24); manlo <= conv_std_logic_vector(121946709,28); exponent <= conv_std_logic_vector(1898,11); WHEN "1001100000" => manhi <= conv_std_logic_vector(1949373,24); manlo <= conv_std_logic_vector(194974600,28); exponent <= conv_std_logic_vector(1900,11); WHEN "1001100001" => manhi <= conv_std_logic_vector(8674858,24); manlo <= conv_std_logic_vector(75445083,28); exponent <= conv_std_logic_vector(1901,11); WHEN "1001100010" => manhi <= conv_std_logic_vector(519261,24); manlo <= conv_std_logic_vector(202318540,28); exponent <= conv_std_logic_vector(1903,11); WHEN "1001100011" => manhi <= conv_std_logic_vector(6731134,24); manlo <= conv_std_logic_vector(157600610,28); exponent <= conv_std_logic_vector(1904,11); WHEN "1001100100" => manhi <= conv_std_logic_vector(15173945,24); manlo <= conv_std_logic_vector(29256816,28); exponent <= conv_std_logic_vector(1905,11); WHEN "1001100101" => manhi <= conv_std_logic_vector(4935849,24); manlo <= conv_std_logic_vector(42999013,28); exponent <= conv_std_logic_vector(1907,11); WHEN "1001100110" => manhi <= conv_std_logic_vector(12733899,24); manlo <= conv_std_logic_vector(62421287,28); exponent <= conv_std_logic_vector(1908,11); WHEN "1001100111" => manhi <= conv_std_logic_vector(3277666,24); manlo <= conv_std_logic_vector(18399062,28); exponent <= conv_std_logic_vector(1910,11); WHEN "1001101000" => manhi <= conv_std_logic_vector(10480194,24); manlo <= conv_std_logic_vector(201166396,28); exponent <= conv_std_logic_vector(1911,11); WHEN "1001101001" => manhi <= conv_std_logic_vector(1746115,24); manlo <= conv_std_logic_vector(22209480,28); exponent <= conv_std_logic_vector(1913,11); WHEN "1001101010" => manhi <= conv_std_logic_vector(8398601,24); manlo <= conv_std_logic_vector(38216343,28); exponent <= conv_std_logic_vector(1914,11); WHEN "1001101011" => manhi <= conv_std_logic_vector(331525,24); manlo <= conv_std_logic_vector(151310615,28); exponent <= conv_std_logic_vector(1916,11); WHEN "1001101100" => manhi <= conv_std_logic_vector(6475974,24); manlo <= conv_std_logic_vector(174528998,28); exponent <= conv_std_logic_vector(1917,11); WHEN "1001101101" => manhi <= conv_std_logic_vector(14827146,24); manlo <= conv_std_logic_vector(214487191,28); exponent <= conv_std_logic_vector(1918,11); WHEN "1001101110" => manhi <= conv_std_logic_vector(4700175,24); manlo <= conv_std_logic_vector(73593076,28); exponent <= conv_std_logic_vector(1920,11); WHEN "1001101111" => manhi <= conv_std_logic_vector(12413585,24); manlo <= conv_std_logic_vector(56806573,28); exponent <= conv_std_logic_vector(1921,11); WHEN "1001110000" => manhi <= conv_std_logic_vector(3059990,24); manlo <= conv_std_logic_vector(32998071,28); exponent <= conv_std_logic_vector(1923,11); WHEN "1001110001" => manhi <= conv_std_logic_vector(10184342,24); manlo <= conv_std_logic_vector(125003687,28); exponent <= conv_std_logic_vector(1924,11); WHEN "1001110010" => manhi <= conv_std_logic_vector(1545062,24); manlo <= conv_std_logic_vector(164026180,28); exponent <= conv_std_logic_vector(1926,11); WHEN "1001110011" => manhi <= conv_std_logic_vector(8125342,24); manlo <= conv_std_logic_vector(134803968,28); exponent <= conv_std_logic_vector(1927,11); WHEN "1001110100" => manhi <= conv_std_logic_vector(145827,24); manlo <= conv_std_logic_vector(17356019,28); exponent <= conv_std_logic_vector(1929,11); WHEN "1001110101" => manhi <= conv_std_logic_vector(6223584,24); manlo <= conv_std_logic_vector(59711433,28); exponent <= conv_std_logic_vector(1930,11); WHEN "1001110110" => manhi <= conv_std_logic_vector(14484112,24); manlo <= conv_std_logic_vector(172427100,28); exponent <= conv_std_logic_vector(1931,11); WHEN "1001110111" => manhi <= conv_std_logic_vector(4467059,24); manlo <= conv_std_logic_vector(106163660,28); exponent <= conv_std_logic_vector(1933,11); WHEN "1001111000" => manhi <= conv_std_logic_vector(12096747,24); manlo <= conv_std_logic_vector(237074316,28); exponent <= conv_std_logic_vector(1934,11); WHEN "1001111001" => manhi <= conv_std_logic_vector(2844676,24); manlo <= conv_std_logic_vector(224090291,28); exponent <= conv_std_logic_vector(1936,11); WHEN "1001111010" => manhi <= conv_std_logic_vector(9891701,24); manlo <= conv_std_logic_vector(98356275,28); exponent <= conv_std_logic_vector(1937,11); WHEN "1001111011" => manhi <= conv_std_logic_vector(1346192,24); manlo <= conv_std_logic_vector(98098154,28); exponent <= conv_std_logic_vector(1939,11); WHEN "1001111100" => manhi <= conv_std_logic_vector(7855049,24); manlo <= conv_std_logic_vector(218711727,28); exponent <= conv_std_logic_vector(1940,11); WHEN "1001111101" => manhi <= conv_std_logic_vector(16701504,24); manlo <= conv_std_logic_vector(74899902,28); exponent <= conv_std_logic_vector(1941,11); WHEN "1001111110" => manhi <= conv_std_logic_vector(5973933,24); manlo <= conv_std_logic_vector(65399866,28); exponent <= conv_std_logic_vector(1943,11); WHEN "1001111111" => manhi <= conv_std_logic_vector(14144801,24); manlo <= conv_std_logic_vector(210121699,28); exponent <= conv_std_logic_vector(1944,11); WHEN "1010000000" => manhi <= conv_std_logic_vector(4236473,24); manlo <= conv_std_logic_vector(203888522,28); exponent <= conv_std_logic_vector(1946,11); WHEN "1010000001" => manhi <= conv_std_logic_vector(11783349,24); manlo <= conv_std_logic_vector(137203293,28); exponent <= conv_std_logic_vector(1947,11); WHEN "1010000010" => manhi <= conv_std_logic_vector(2631700,24); manlo <= conv_std_logic_vector(150283410,28); exponent <= conv_std_logic_vector(1949,11); WHEN "1010000011" => manhi <= conv_std_logic_vector(9602236,24); manlo <= conv_std_logic_vector(160352104,28); exponent <= conv_std_logic_vector(1950,11); WHEN "1010000100" => manhi <= conv_std_logic_vector(1149480,24); manlo <= conv_std_logic_vector(177173803,28); exponent <= conv_std_logic_vector(1952,11); WHEN "1010000101" => manhi <= conv_std_logic_vector(7587690,24); manlo <= conv_std_logic_vector(238268718,28); exponent <= conv_std_logic_vector(1953,11); WHEN "1010000110" => manhi <= conv_std_logic_vector(16338125,24); manlo <= conv_std_logic_vector(220749839,28); exponent <= conv_std_logic_vector(1954,11); WHEN "1010000111" => manhi <= conv_std_logic_vector(5726991,24); manlo <= conv_std_logic_vector(262994505,28); exponent <= conv_std_logic_vector(1956,11); WHEN "1010001000" => manhi <= conv_std_logic_vector(13809173,24); manlo <= conv_std_logic_vector(216783842,28); exponent <= conv_std_logic_vector(1957,11); WHEN "1010001001" => manhi <= conv_std_logic_vector(4008390,24); manlo <= conv_std_logic_vector(242405077,28); exponent <= conv_std_logic_vector(1959,11); WHEN "1010001010" => manhi <= conv_std_logic_vector(11473352,24); manlo <= conv_std_logic_vector(206426515,28); exponent <= conv_std_logic_vector(1960,11); WHEN "1010001011" => manhi <= conv_std_logic_vector(2421035,24); manlo <= conv_std_logic_vector(250208807,28); exponent <= conv_std_logic_vector(1962,11); WHEN "1010001100" => manhi <= conv_std_logic_vector(9315913,24); manlo <= conv_std_logic_vector(183235034,28); exponent <= conv_std_logic_vector(1963,11); WHEN "1010001101" => manhi <= conv_std_logic_vector(954904,24); manlo <= conv_std_logic_vector(17706469,28); exponent <= conv_std_logic_vector(1965,11); WHEN "1010001110" => manhi <= conv_std_logic_vector(7323233,24); manlo <= conv_std_logic_vector(235600136,28); exponent <= conv_std_logic_vector(1966,11); WHEN "1010001111" => manhi <= conv_std_logic_vector(15978691,24); manlo <= conv_std_logic_vector(128873524,28); exponent <= conv_std_logic_vector(1967,11); WHEN "1010010000" => manhi <= conv_std_logic_vector(5482731,24); manlo <= conv_std_logic_vector(5222268,28); exponent <= conv_std_logic_vector(1969,11); WHEN "1010010001" => manhi <= conv_std_logic_vector(13477188,24); manlo <= conv_std_logic_vector(199372940,28); exponent <= conv_std_logic_vector(1970,11); WHEN "1010010010" => manhi <= conv_std_logic_vector(3782783,24); manlo <= conv_std_logic_vector(177367827,28); exponent <= conv_std_logic_vector(1972,11); WHEN "1010010011" => manhi <= conv_std_logic_vector(11166720,24); manlo <= conv_std_logic_vector(197425116,28); exponent <= conv_std_logic_vector(1973,11); WHEN "1010010100" => manhi <= conv_std_logic_vector(2212657,24); manlo <= conv_std_logic_vector(231097832,28); exponent <= conv_std_logic_vector(1975,11); WHEN "1010010101" => manhi <= conv_std_logic_vector(9032698,24); manlo <= conv_std_logic_vector(139698050,28); exponent <= conv_std_logic_vector(1976,11); WHEN "1010010110" => manhi <= conv_std_logic_vector(762439,24); manlo <= conv_std_logic_vector(109718127,28); exponent <= conv_std_logic_vector(1978,11); WHEN "1010010111" => manhi <= conv_std_logic_vector(7061647,24); manlo <= conv_std_logic_vector(77173752,28); exponent <= conv_std_logic_vector(1979,11); WHEN "1010011000" => manhi <= conv_std_logic_vector(15623158,24); manlo <= conv_std_logic_vector(118851961,28); exponent <= conv_std_logic_vector(1980,11); WHEN "1010011001" => manhi <= conv_std_logic_vector(5241121,24); manlo <= conv_std_logic_vector(72680114,28); exponent <= conv_std_logic_vector(1982,11); WHEN "1010011010" => manhi <= conv_std_logic_vector(13148807,24); manlo <= conv_std_logic_vector(12881486,28); exponent <= conv_std_logic_vector(1983,11); WHEN "1010011011" => manhi <= conv_std_logic_vector(3559625,24); manlo <= conv_std_logic_vector(43579850,28); exponent <= conv_std_logic_vector(1985,11); WHEN "1010011100" => manhi <= conv_std_logic_vector(10863416,24); manlo <= conv_std_logic_vector(238889758,28); exponent <= conv_std_logic_vector(1986,11); WHEN "1010011101" => manhi <= conv_std_logic_vector(2006541,24); manlo <= conv_std_logic_vector(141721451,28); exponent <= conv_std_logic_vector(1988,11); WHEN "1010011110" => manhi <= conv_std_logic_vector(8752557,24); manlo <= conv_std_logic_vector(101792997,28); exponent <= conv_std_logic_vector(1989,11); WHEN "1010011111" => manhi <= conv_std_logic_vector(572063,24); manlo <= conv_std_logic_vector(205445723,28); exponent <= conv_std_logic_vector(1991,11); WHEN "1010100000" => manhi <= conv_std_logic_vector(6802899,24); manlo <= conv_std_logic_vector(258099270,28); exponent <= conv_std_logic_vector(1992,11); WHEN "1010100001" => manhi <= conv_std_logic_vector(15271484,24); manlo <= conv_std_logic_vector(98124990,28); exponent <= conv_std_logic_vector(1993,11); WHEN "1010100010" => manhi <= conv_std_logic_vector(5002133,24); manlo <= conv_std_logic_vector(256985826,28); exponent <= conv_std_logic_vector(1995,11); WHEN "1010100011" => manhi <= conv_std_logic_vector(12823989,24); manlo <= conv_std_logic_vector(164377270,28); exponent <= conv_std_logic_vector(1996,11); WHEN "1010100100" => manhi <= conv_std_logic_vector(3338888,24); manlo <= conv_std_logic_vector(222569178,28); exponent <= conv_std_logic_vector(1998,11); WHEN "1010100101" => manhi <= conv_std_logic_vector(10563405,24); manlo <= conv_std_logic_vector(29046646,28); exponent <= conv_std_logic_vector(1999,11); WHEN "1010100110" => manhi <= conv_std_logic_vector(1802662,24); manlo <= conv_std_logic_vector(103161316,28); exponent <= conv_std_logic_vector(2001,11); WHEN "1010100111" => manhi <= conv_std_logic_vector(8475456,24); manlo <= conv_std_logic_vector(239852126,28); exponent <= conv_std_logic_vector(2002,11); WHEN "1010101000" => manhi <= conv_std_logic_vector(383754,24); manlo <= conv_std_logic_vector(123914668,28); exponent <= conv_std_logic_vector(2004,11); WHEN "1010101001" => manhi <= conv_std_logic_vector(6546961,24); manlo <= conv_std_logic_vector(22084044,28); exponent <= conv_std_logic_vector(2005,11); WHEN "1010101010" => manhi <= conv_std_logic_vector(14923627,24); manlo <= conv_std_logic_vector(97508377,28); exponent <= conv_std_logic_vector(2006,11); WHEN "1010101011" => manhi <= conv_std_logic_vector(4765740,24); manlo <= conv_std_logic_vector(165164368,28); exponent <= conv_std_logic_vector(2008,11); WHEN "1010101100" => manhi <= conv_std_logic_vector(12502697,24); manlo <= conv_std_logic_vector(201140216,28); exponent <= conv_std_logic_vector(2009,11); WHEN "1010101101" => manhi <= conv_std_logic_vector(3120548,24); manlo <= conv_std_logic_vector(99561759,28); exponent <= conv_std_logic_vector(2011,11); WHEN "1010101110" => manhi <= conv_std_logic_vector(10266649,24); manlo <= conv_std_logic_vector(176679877,28); exponent <= conv_std_logic_vector(2012,11); WHEN "1010101111" => manhi <= conv_std_logic_vector(1600996,24); manlo <= conv_std_logic_vector(39589446,28); exponent <= conv_std_logic_vector(2014,11); WHEN "1010110000" => manhi <= conv_std_logic_vector(8201364,24); manlo <= conv_std_logic_vector(16114999,28); exponent <= conv_std_logic_vector(2015,11); WHEN "1010110001" => manhi <= conv_std_logic_vector(197489,24); manlo <= conv_std_logic_vector(18649371,28); exponent <= conv_std_logic_vector(2017,11); WHEN "1010110010" => manhi <= conv_std_logic_vector(6293800,24); manlo <= conv_std_logic_vector(44802372,28); exponent <= conv_std_logic_vector(2018,11); WHEN "1010110011" => manhi <= conv_std_logic_vector(14579546,24); manlo <= conv_std_logic_vector(1419236,28); exponent <= conv_std_logic_vector(2019,11); WHEN "1010110100" => manhi <= conv_std_logic_vector(4531913,24); manlo <= conv_std_logic_vector(24044223,28); exponent <= conv_std_logic_vector(2021,11); WHEN "1010110101" => manhi <= conv_std_logic_vector(12184893,24); manlo <= conv_std_logic_vector(51602800,28); exponent <= conv_std_logic_vector(2022,11); WHEN "1010110110" => manhi <= conv_std_logic_vector(2904577,24); manlo <= conv_std_logic_vector(210124577,28); exponent <= conv_std_logic_vector(2024,11); WHEN "1010110111" => manhi <= conv_std_logic_vector(9973115,24); manlo <= conv_std_logic_vector(52505388,28); exponent <= conv_std_logic_vector(2025,11); WHEN "1010111000" => manhi <= conv_std_logic_vector(1401518,24); manlo <= conv_std_logic_vector(214362802,28); exponent <= conv_std_logic_vector(2027,11); WHEN "1010111001" => manhi <= conv_std_logic_vector(7930246,24); manlo <= conv_std_logic_vector(62721516,28); exponent <= conv_std_logic_vector(2028,11); WHEN "1010111010" => manhi <= conv_std_logic_vector(13245,24); manlo <= conv_std_logic_vector(108520727,28); exponent <= conv_std_logic_vector(2030,11); WHEN "1010111011" => manhi <= conv_std_logic_vector(6043387,24); manlo <= conv_std_logic_vector(17001813,28); exponent <= conv_std_logic_vector(2031,11); WHEN "1010111100" => manhi <= conv_std_logic_vector(14239199,24); manlo <= conv_std_logic_vector(83422350,28); exponent <= conv_std_logic_vector(2032,11); WHEN "1010111101" => manhi <= conv_std_logic_vector(4300623,24); manlo <= conv_std_logic_vector(142486326,28); exponent <= conv_std_logic_vector(2034,11); WHEN "1010111110" => manhi <= conv_std_logic_vector(11870538,24); manlo <= conv_std_logic_vector(24126621,28); exponent <= conv_std_logic_vector(2035,11); WHEN "1010111111" => manhi <= conv_std_logic_vector(2690951,24); manlo <= conv_std_logic_vector(91850592,28); exponent <= conv_std_logic_vector(2037,11); WHEN "1011000000" => manhi <= conv_std_logic_vector(9682766,24); manlo <= conv_std_logic_vector(203960059,28); exponent <= conv_std_logic_vector(2038,11); WHEN "1011000001" => manhi <= conv_std_logic_vector(1204206,24); manlo <= conv_std_logic_vector(155513539,28); exponent <= conv_std_logic_vector(2040,11); WHEN "1011000010" => manhi <= conv_std_logic_vector(7662071,24); manlo <= conv_std_logic_vector(33184566,28); exponent <= conv_std_logic_vector(2041,11); WHEN "1011000011" => manhi <= conv_std_logic_vector(16439219,24); manlo <= conv_std_logic_vector(11896414,28); exponent <= conv_std_logic_vector(2042,11); WHEN "1011000100" => manhi <= conv_std_logic_vector(5795691,24); manlo <= conv_std_logic_vector(254151921,28); exponent <= conv_std_logic_vector(2044,11); WHEN "1011000101" => manhi <= conv_std_logic_vector(13902546,24); manlo <= conv_std_logic_vector(199613595,28); exponent <= conv_std_logic_vector(2045,11); WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_explutpos IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_explutpos; ARCHITECTURE rtl OF dp_explutpos IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(1023,11); WHEN "0000000001" => manhi <= conv_std_logic_vector(6025384,24); manlo <= conv_std_logic_vector(185882474,28); exponent <= conv_std_logic_vector(1024,11); WHEN "0000000010" => manhi <= conv_std_logic_vector(14214731,24); manlo <= conv_std_logic_vector(148168110,28); exponent <= conv_std_logic_vector(1025,11); WHEN "0000000011" => manhi <= conv_std_logic_vector(4283995,24); manlo <= conv_std_logic_vector(258978054,28); exponent <= conv_std_logic_vector(1027,11); WHEN "0000000100" => manhi <= conv_std_logic_vector(11847938,24); manlo <= conv_std_logic_vector(237451864,28); exponent <= conv_std_logic_vector(1028,11); WHEN "0000000101" => manhi <= conv_std_logic_vector(2675593,24); manlo <= conv_std_logic_vector(158348175,28); exponent <= conv_std_logic_vector(1030,11); WHEN "0000000110" => manhi <= conv_std_logic_vector(9661893,24); manlo <= conv_std_logic_vector(110149775,28); exponent <= conv_std_logic_vector(1031,11); WHEN "0000000111" => manhi <= conv_std_logic_vector(1190021,24); manlo <= conv_std_logic_vector(179232170,28); exponent <= conv_std_logic_vector(1033,11); WHEN "0000001000" => manhi <= conv_std_logic_vector(7642791,24); manlo <= conv_std_logic_vector(222760046,28); exponent <= conv_std_logic_vector(1034,11); WHEN "0000001001" => manhi <= conv_std_logic_vector(16413015,24); manlo <= conv_std_logic_vector(205983618,28); exponent <= conv_std_logic_vector(1035,11); WHEN "0000001010" => manhi <= conv_std_logic_vector(5777884,24); manlo <= conv_std_logic_vector(261424480,28); exponent <= conv_std_logic_vector(1037,11); WHEN "0000001011" => manhi <= conv_std_logic_vector(13878344,24); manlo <= conv_std_logic_vector(149835647,28); exponent <= conv_std_logic_vector(1038,11); WHEN "0000001100" => manhi <= conv_std_logic_vector(4055397,24); manlo <= conv_std_logic_vector(80968858,28); exponent <= conv_std_logic_vector(1040,11); WHEN "0000001101" => manhi <= conv_std_logic_vector(11537241,24); manlo <= conv_std_logic_vector(23775573,28); exponent <= conv_std_logic_vector(1041,11); WHEN "0000001110" => manhi <= conv_std_logic_vector(2464452,24); manlo <= conv_std_logic_vector(146736599,28); exponent <= conv_std_logic_vector(1043,11); WHEN "0000001111" => manhi <= conv_std_logic_vector(9374922,24); manlo <= conv_std_logic_vector(263006855,28); exponent <= conv_std_logic_vector(1044,11); WHEN "0000010000" => manhi <= conv_std_logic_vector(995005,24); manlo <= conv_std_logic_vector(11010080,28); exponent <= conv_std_logic_vector(1046,11); WHEN "0000010001" => manhi <= conv_std_logic_vector(7377736,24); manlo <= conv_std_logic_vector(202286329,28); exponent <= conv_std_logic_vector(1047,11); WHEN "0000010010" => manhi <= conv_std_logic_vector(16052768,24); manlo <= conv_std_logic_vector(152649917,28); exponent <= conv_std_logic_vector(1048,11); WHEN "0000010011" => manhi <= conv_std_logic_vector(5533071,24); manlo <= conv_std_logic_vector(166536930,28); exponent <= conv_std_logic_vector(1050,11); WHEN "0000010100" => manhi <= conv_std_logic_vector(13545608,24); manlo <= conv_std_logic_vector(191424516,28); exponent <= conv_std_logic_vector(1051,11); WHEN "0000010101" => manhi <= conv_std_logic_vector(3829279,24); manlo <= conv_std_logic_vector(228519165,28); exponent <= conv_std_logic_vector(1053,11); WHEN "0000010110" => manhi <= conv_std_logic_vector(11229915,24); manlo <= conv_std_logic_vector(163853824,28); exponent <= conv_std_logic_vector(1054,11); WHEN "0000010111" => manhi <= conv_std_logic_vector(2255603,24); manlo <= conv_std_logic_vector(61996481,28); exponent <= conv_std_logic_vector(1056,11); WHEN "0000011000" => manhi <= conv_std_logic_vector(9091067,24); manlo <= conv_std_logic_vector(88563639,28); exponent <= conv_std_logic_vector(1057,11); WHEN "0000011001" => manhi <= conv_std_logic_vector(802105,24); manlo <= conv_std_logic_vector(34169545,28); exponent <= conv_std_logic_vector(1059,11); WHEN "0000011010" => manhi <= conv_std_logic_vector(7115558,24); manlo <= conv_std_logic_vector(157969244,28); exponent <= conv_std_logic_vector(1060,11); WHEN "0000011011" => manhi <= conv_std_logic_vector(15696431,24); manlo <= conv_std_logic_vector(133591837,28); exponent <= conv_std_logic_vector(1061,11); WHEN "0000011100" => manhi <= conv_std_logic_vector(5290915,24); manlo <= conv_std_logic_vector(127285146,28); exponent <= conv_std_logic_vector(1063,11); WHEN "0000011101" => manhi <= conv_std_logic_vector(13216484,24); manlo <= conv_std_logic_vector(103923798,28); exponent <= conv_std_logic_vector(1064,11); WHEN "0000011110" => manhi <= conv_std_logic_vector(3605616,24); manlo <= conv_std_logic_vector(183249133,28); exponent <= conv_std_logic_vector(1066,11); WHEN "0000011111" => manhi <= conv_std_logic_vector(10925925,24); manlo <= conv_std_logic_vector(227336045,28); exponent <= conv_std_logic_vector(1067,11); WHEN "0000100000" => manhi <= conv_std_logic_vector(2049020,24); manlo <= conv_std_logic_vector(206267948,28); exponent <= conv_std_logic_vector(1069,11); WHEN "0000100001" => manhi <= conv_std_logic_vector(8810292,24); manlo <= conv_std_logic_vector(175265666,28); exponent <= conv_std_logic_vector(1070,11); WHEN "0000100010" => manhi <= conv_std_logic_vector(611298,24); manlo <= conv_std_logic_vector(255467255,28); exponent <= conv_std_logic_vector(1072,11); WHEN "0000100011" => manhi <= conv_std_logic_vector(6856226,24); manlo <= conv_std_logic_vector(29134171,28); exponent <= conv_std_logic_vector(1073,11); WHEN "0000100100" => manhi <= conv_std_logic_vector(15343962,24); manlo <= conv_std_logic_vector(30543222,28); exponent <= conv_std_logic_vector(1074,11); WHEN "0000100101" => manhi <= conv_std_logic_vector(5051387,24); manlo <= conv_std_logic_vector(186253338,28); exponent <= conv_std_logic_vector(1076,11); WHEN "0000100110" => manhi <= conv_std_logic_vector(12890932,24); manlo <= conv_std_logic_vector(102222951,28); exponent <= conv_std_logic_vector(1077,11); WHEN "0000100111" => manhi <= conv_std_logic_vector(3384381,24); manlo <= conv_std_logic_vector(42116377,28); exponent <= conv_std_logic_vector(1079,11); WHEN "0000101000" => manhi <= conv_std_logic_vector(10625235,24); manlo <= conv_std_logic_vector(158954218,28); exponent <= conv_std_logic_vector(1080,11); WHEN "0000101001" => manhi <= conv_std_logic_vector(1844680,24); manlo <= conv_std_logic_vector(148858978,28); exponent <= conv_std_logic_vector(1082,11); WHEN "0000101010" => manhi <= conv_std_logic_vector(8532565,24); manlo <= conv_std_logic_vector(136319321,28); exponent <= conv_std_logic_vector(1083,11); WHEN "0000101011" => manhi <= conv_std_logic_vector(422563,24); manlo <= conv_std_logic_vector(211728497,28); exponent <= conv_std_logic_vector(1085,11); WHEN "0000101100" => manhi <= conv_std_logic_vector(6599708,24); manlo <= conv_std_logic_vector(114522162,28); exponent <= conv_std_logic_vector(1086,11); WHEN "0000101101" => manhi <= conv_std_logic_vector(14995318,24); manlo <= conv_std_logic_vector(117328318,28); exponent <= conv_std_logic_vector(1087,11); WHEN "0000101110" => manhi <= conv_std_logic_vector(4814459,24); manlo <= conv_std_logic_vector(201622499,28); exponent <= conv_std_logic_vector(1089,11); WHEN "0000101111" => manhi <= conv_std_logic_vector(12568913,24); manlo <= conv_std_logic_vector(246987638,28); exponent <= conv_std_logic_vector(1090,11); WHEN "0000110000" => manhi <= conv_std_logic_vector(3165546,24); manlo <= conv_std_logic_vector(248128843,28); exponent <= conv_std_logic_vector(1092,11); WHEN "0000110001" => manhi <= conv_std_logic_vector(10327809,24); manlo <= conv_std_logic_vector(8929872,28); exponent <= conv_std_logic_vector(1093,11); WHEN "0000110010" => manhi <= conv_std_logic_vector(1642558,24); manlo <= conv_std_logic_vector(67636037,28); exponent <= conv_std_logic_vector(1095,11); WHEN "0000110011" => manhi <= conv_std_logic_vector(8257852,24); manlo <= conv_std_logic_vector(219235425,28); exponent <= conv_std_logic_vector(1096,11); WHEN "0000110100" => manhi <= conv_std_logic_vector(235877,24); manlo <= conv_std_logic_vector(42862412,28); exponent <= conv_std_logic_vector(1098,11); WHEN "0000110101" => manhi <= conv_std_logic_vector(6345974,24); manlo <= conv_std_logic_vector(265996080,28); exponent <= conv_std_logic_vector(1099,11); WHEN "0000110110" => manhi <= conv_std_logic_vector(14650458,24); manlo <= conv_std_logic_vector(253213243,28); exponent <= conv_std_logic_vector(1100,11); WHEN "0000110111" => manhi <= conv_std_logic_vector(4580103,24); manlo <= conv_std_logic_vector(114693785,28); exponent <= conv_std_logic_vector(1102,11); WHEN "0000111000" => manhi <= conv_std_logic_vector(12250390,24); manlo <= conv_std_logic_vector(174984615,28); exponent <= conv_std_logic_vector(1103,11); WHEN "0000111001" => manhi <= conv_std_logic_vector(2949087,24); manlo <= conv_std_logic_vector(247325089,28); exponent <= conv_std_logic_vector(1105,11); WHEN "0000111010" => manhi <= conv_std_logic_vector(10033610,24); manlo <= conv_std_logic_vector(200264553,28); exponent <= conv_std_logic_vector(1106,11); WHEN "0000111011" => manhi <= conv_std_logic_vector(1442629,24); manlo <= conv_std_logic_vector(211375075,28); exponent <= conv_std_logic_vector(1108,11); WHEN "0000111100" => manhi <= conv_std_logic_vector(7986121,24); manlo <= conv_std_logic_vector(231029862,28); exponent <= conv_std_logic_vector(1109,11); WHEN "0000111101" => manhi <= conv_std_logic_vector(51216,24); manlo <= conv_std_logic_vector(222707863,28); exponent <= conv_std_logic_vector(1111,11); WHEN "0000111110" => manhi <= conv_std_logic_vector(6094995,24); manlo <= conv_std_logic_vector(155999272,28); exponent <= conv_std_logic_vector(1112,11); WHEN "0000111111" => manhi <= conv_std_logic_vector(14309342,24); manlo <= conv_std_logic_vector(150013864,28); exponent <= conv_std_logic_vector(1113,11); WHEN "0001000000" => manhi <= conv_std_logic_vector(4348290,24); manlo <= conv_std_logic_vector(217421773,28); exponent <= conv_std_logic_vector(1115,11); WHEN "0001000001" => manhi <= conv_std_logic_vector(11935324,24); manlo <= conv_std_logic_vector(171597361,28); exponent <= conv_std_logic_vector(1116,11); WHEN "0001000010" => manhi <= conv_std_logic_vector(2734978,24); manlo <= conv_std_logic_vector(98553735,28); exponent <= conv_std_logic_vector(1118,11); WHEN "0001000011" => manhi <= conv_std_logic_vector(9742605,24); manlo <= conv_std_logic_vector(185429986,28); exponent <= conv_std_logic_vector(1119,11); WHEN "0001000100" => manhi <= conv_std_logic_vector(1244871,24); manlo <= conv_std_logic_vector(93685501,28); exponent <= conv_std_logic_vector(1121,11); WHEN "0001000101" => manhi <= conv_std_logic_vector(7717340,24); manlo <= conv_std_logic_vector(74048432,28); exponent <= conv_std_logic_vector(1122,11); WHEN "0001000110" => manhi <= conv_std_logic_vector(16514337,24); manlo <= conv_std_logic_vector(163855108,28); exponent <= conv_std_logic_vector(1123,11); WHEN "0001000111" => manhi <= conv_std_logic_vector(5846740,24); manlo <= conv_std_logic_vector(81895750,28); exponent <= conv_std_logic_vector(1125,11); WHEN "0001001000" => manhi <= conv_std_logic_vector(13971928,24); manlo <= conv_std_logic_vector(176088988,28); exponent <= conv_std_logic_vector(1126,11); WHEN "0001001001" => manhi <= conv_std_logic_vector(4118994,24); manlo <= conv_std_logic_vector(77780251,28); exponent <= conv_std_logic_vector(1128,11); WHEN "0001001010" => manhi <= conv_std_logic_vector(11623678,24); manlo <= conv_std_logic_vector(95871356,28); exponent <= conv_std_logic_vector(1129,11); WHEN "0001001011" => manhi <= conv_std_logic_vector(2523192,24); manlo <= conv_std_logic_vector(204213760,28); exponent <= conv_std_logic_vector(1131,11); WHEN "0001001100" => manhi <= conv_std_logic_vector(9454759,24); manlo <= conv_std_logic_vector(55860552,28); exponent <= conv_std_logic_vector(1132,11); WHEN "0001001101" => manhi <= conv_std_logic_vector(1049259,24); manlo <= conv_std_logic_vector(102861624,28); exponent <= conv_std_logic_vector(1134,11); WHEN "0001001110" => manhi <= conv_std_logic_vector(7451476,24); manlo <= conv_std_logic_vector(13367584,28); exponent <= conv_std_logic_vector(1135,11); WHEN "0001001111" => manhi <= conv_std_logic_vector(16152990,24); manlo <= conv_std_logic_vector(178012490,28); exponent <= conv_std_logic_vector(1136,11); WHEN "0001010000" => manhi <= conv_std_logic_vector(5601179,24); manlo <= conv_std_logic_vector(159708139,28); exponent <= conv_std_logic_vector(1138,11); WHEN "0001010001" => manhi <= conv_std_logic_vector(13638177,24); manlo <= conv_std_logic_vector(12864164,28); exponent <= conv_std_logic_vector(1139,11); WHEN "0001010010" => manhi <= conv_std_logic_vector(3892186,24); manlo <= conv_std_logic_vector(149492240,28); exponent <= conv_std_logic_vector(1141,11); WHEN "0001010011" => manhi <= conv_std_logic_vector(11315414,24); manlo <= conv_std_logic_vector(184620728,28); exponent <= conv_std_logic_vector(1142,11); WHEN "0001010100" => manhi <= conv_std_logic_vector(2313705,24); manlo <= conv_std_logic_vector(235697385,28); exponent <= conv_std_logic_vector(1144,11); WHEN "0001010101" => manhi <= conv_std_logic_vector(9170037,24); manlo <= conv_std_logic_vector(3974263,28); exponent <= conv_std_logic_vector(1145,11); WHEN "0001010110" => manhi <= conv_std_logic_vector(855770,24); manlo <= conv_std_logic_vector(158952336,28); exponent <= conv_std_logic_vector(1147,11); WHEN "0001010111" => manhi <= conv_std_logic_vector(7188497,24); manlo <= conv_std_logic_vector(138900038,28); exponent <= conv_std_logic_vector(1148,11); WHEN "0001011000" => manhi <= conv_std_logic_vector(15795565,24); manlo <= conv_std_logic_vector(209449517,28); exponent <= conv_std_logic_vector(1149,11); WHEN "0001011001" => manhi <= conv_std_logic_vector(5358284,24); manlo <= conv_std_logic_vector(54736896,28); exponent <= conv_std_logic_vector(1151,11); WHEN "0001011010" => manhi <= conv_std_logic_vector(13308047,24); manlo <= conv_std_logic_vector(264159588,28); exponent <= conv_std_logic_vector(1152,11); WHEN "0001011011" => manhi <= conv_std_logic_vector(3667840,24); manlo <= conv_std_logic_vector(160544132,28); exponent <= conv_std_logic_vector(1154,11); WHEN "0001011100" => manhi <= conv_std_logic_vector(11010496,24); manlo <= conv_std_logic_vector(245935181,28); exponent <= conv_std_logic_vector(1155,11); WHEN "0001011101" => manhi <= conv_std_logic_vector(2106492,24); manlo <= conv_std_logic_vector(206325441,28); exponent <= conv_std_logic_vector(1157,11); WHEN "0001011110" => manhi <= conv_std_logic_vector(8888405,24); manlo <= conv_std_logic_vector(53641237,28); exponent <= conv_std_logic_vector(1158,11); WHEN "0001011111" => manhi <= conv_std_logic_vector(664381,24); manlo <= conv_std_logic_vector(249887163,28); exponent <= conv_std_logic_vector(1160,11); WHEN "0001100000" => manhi <= conv_std_logic_vector(6928373,24); manlo <= conv_std_logic_vector(95946938,28); exponent <= conv_std_logic_vector(1161,11); WHEN "0001100001" => manhi <= conv_std_logic_vector(15442020,24); manlo <= conv_std_logic_vector(105121290,28); exponent <= conv_std_logic_vector(1162,11); WHEN "0001100010" => manhi <= conv_std_logic_vector(5118025,24); manlo <= conv_std_logic_vector(54367076,28); exponent <= conv_std_logic_vector(1164,11); WHEN "0001100011" => manhi <= conv_std_logic_vector(12981502,24); manlo <= conv_std_logic_vector(39000129,28); exponent <= conv_std_logic_vector(1165,11); WHEN "0001100100" => manhi <= conv_std_logic_vector(3445929,24); manlo <= conv_std_logic_vector(186063861,28); exponent <= conv_std_logic_vector(1167,11); WHEN "0001100101" => manhi <= conv_std_logic_vector(10708888,24); manlo <= conv_std_logic_vector(194877084,28); exponent <= conv_std_logic_vector(1168,11); WHEN "0001100110" => manhi <= conv_std_logic_vector(1901528,24); manlo <= conv_std_logic_vector(202114223,28); exponent <= conv_std_logic_vector(1170,11); WHEN "0001100111" => manhi <= conv_std_logic_vector(8609830,24); manlo <= conv_std_logic_vector(59099508,28); exponent <= conv_std_logic_vector(1171,11); WHEN "0001101000" => manhi <= conv_std_logic_vector(475070,24); manlo <= conv_std_logic_vector(162304029,28); exponent <= conv_std_logic_vector(1173,11); WHEN "0001101001" => manhi <= conv_std_logic_vector(6671072,24); manlo <= conv_std_logic_vector(157938310,28); exponent <= conv_std_logic_vector(1174,11); WHEN "0001101010" => manhi <= conv_std_logic_vector(15092312,24); manlo <= conv_std_logic_vector(104450792,28); exponent <= conv_std_logic_vector(1175,11); WHEN "0001101011" => manhi <= conv_std_logic_vector(4880373,24); manlo <= conv_std_logic_vector(261837049,28); exponent <= conv_std_logic_vector(1177,11); WHEN "0001101100" => manhi <= conv_std_logic_vector(12658500,24); manlo <= conv_std_logic_vector(171583716,28); exponent <= conv_std_logic_vector(1178,11); WHEN "0001101101" => manhi <= conv_std_logic_vector(3226427,24); manlo <= conv_std_logic_vector(110595717,28); exponent <= conv_std_logic_vector(1180,11); WHEN "0001101110" => manhi <= conv_std_logic_vector(10410554,24); manlo <= conv_std_logic_vector(52320382,28); exponent <= conv_std_logic_vector(1181,11); WHEN "0001101111" => manhi <= conv_std_logic_vector(1698789,24); manlo <= conv_std_logic_vector(112550995,28); exponent <= conv_std_logic_vector(1183,11); WHEN "0001110000" => manhi <= conv_std_logic_vector(8334278,24); manlo <= conv_std_logic_vector(240753534,28); exponent <= conv_std_logic_vector(1184,11); WHEN "0001110001" => manhi <= conv_std_logic_vector(287814,24); manlo <= conv_std_logic_vector(17691391,28); exponent <= conv_std_logic_vector(1186,11); WHEN "0001110010" => manhi <= conv_std_logic_vector(6416564,24); manlo <= conv_std_logic_vector(151700710,28); exponent <= conv_std_logic_vector(1187,11); WHEN "0001110011" => manhi <= conv_std_logic_vector(14746400,24); manlo <= conv_std_logic_vector(32676275,28); exponent <= conv_std_logic_vector(1188,11); WHEN "0001110100" => manhi <= conv_std_logic_vector(4645302,24); manlo <= conv_std_logic_vector(58452725,28); exponent <= conv_std_logic_vector(1190,11); WHEN "0001110101" => manhi <= conv_std_logic_vector(12339004,24); manlo <= conv_std_logic_vector(267247876,28); exponent <= conv_std_logic_vector(1191,11); WHEN "0001110110" => manhi <= conv_std_logic_vector(3009307,24); manlo <= conv_std_logic_vector(164126253,28); exponent <= conv_std_logic_vector(1193,11); WHEN "0001110111" => manhi <= conv_std_logic_vector(10115457,24); manlo <= conv_std_logic_vector(212237584,28); exponent <= conv_std_logic_vector(1194,11); WHEN "0001111000" => manhi <= conv_std_logic_vector(1498250,24); manlo <= conv_std_logic_vector(166684427,28); exponent <= conv_std_logic_vector(1196,11); WHEN "0001111001" => manhi <= conv_std_logic_vector(8061718,24); manlo <= conv_std_logic_vector(110371593,28); exponent <= conv_std_logic_vector(1197,11); WHEN "0001111010" => manhi <= conv_std_logic_vector(102590,24); manlo <= conv_std_logic_vector(3231911,28); exponent <= conv_std_logic_vector(1199,11); WHEN "0001111011" => manhi <= conv_std_logic_vector(6164818,24); manlo <= conv_std_logic_vector(261783833,28); exponent <= conv_std_logic_vector(1200,11); WHEN "0001111100" => manhi <= conv_std_logic_vector(14404242,24); manlo <= conv_std_logic_vector(104825991,28); exponent <= conv_std_logic_vector(1201,11); WHEN "0001111101" => manhi <= conv_std_logic_vector(4412781,24); manlo <= conv_std_logic_vector(250166254,28); exponent <= conv_std_logic_vector(1203,11); WHEN "0001111110" => manhi <= conv_std_logic_vector(12022977,24); manlo <= conv_std_logic_vector(43417082,28); exponent <= conv_std_logic_vector(1204,11); WHEN "0001111111" => manhi <= conv_std_logic_vector(2794544,24); manlo <= conv_std_logic_vector(115942082,28); exponent <= conv_std_logic_vector(1206,11); WHEN "0010000000" => manhi <= conv_std_logic_vector(9823564,24); manlo <= conv_std_logic_vector(98386456,28); exponent <= conv_std_logic_vector(1207,11); WHEN "0010000001" => manhi <= conv_std_logic_vector(1299888,24); manlo <= conv_std_logic_vector(127046227,28); exponent <= conv_std_logic_vector(1209,11); WHEN "0010000010" => manhi <= conv_std_logic_vector(7792116,24); manlo <= conv_std_logic_vector(80649262,28); exponent <= conv_std_logic_vector(1210,11); WHEN "0010000011" => manhi <= conv_std_logic_vector(16615968,24); manlo <= conv_std_logic_vector(205307910,28); exponent <= conv_std_logic_vector(1211,11); WHEN "0010000100" => manhi <= conv_std_logic_vector(5915805,24); manlo <= conv_std_logic_vector(224185017,28); exponent <= conv_std_logic_vector(1213,11); WHEN "0010000101" => manhi <= conv_std_logic_vector(14065798,24); manlo <= conv_std_logic_vector(119094636,28); exponent <= conv_std_logic_vector(1214,11); WHEN "0010000110" => manhi <= conv_std_logic_vector(4182785,24); manlo <= conv_std_logic_vector(113890892,28); exponent <= conv_std_logic_vector(1216,11); WHEN "0010000111" => manhi <= conv_std_logic_vector(11710379,24); manlo <= conv_std_logic_vector(133692518,28); exponent <= conv_std_logic_vector(1217,11); WHEN "0010001000" => manhi <= conv_std_logic_vector(2582112,24); manlo <= conv_std_logic_vector(79109485,28); exponent <= conv_std_logic_vector(1219,11); WHEN "0010001001" => manhi <= conv_std_logic_vector(9534839,24); manlo <= conv_std_logic_vector(42234535,28); exponent <= conv_std_logic_vector(1220,11); WHEN "0010001010" => manhi <= conv_std_logic_vector(1103679,24); manlo <= conv_std_logic_vector(94193887,28); exponent <= conv_std_logic_vector(1222,11); WHEN "0010001011" => manhi <= conv_std_logic_vector(7525440,24); manlo <= conv_std_logic_vector(121994268,28); exponent <= conv_std_logic_vector(1223,11); WHEN "0010001100" => manhi <= conv_std_logic_vector(16253518,24); manlo <= conv_std_logic_vector(191052573,28); exponent <= conv_std_logic_vector(1224,11); WHEN "0010001101" => manhi <= conv_std_logic_vector(5669495,24); manlo <= conv_std_logic_vector(130696997,28); exponent <= conv_std_logic_vector(1226,11); WHEN "0010001110" => manhi <= conv_std_logic_vector(13731027,24); manlo <= conv_std_logic_vector(260846837,28); exponent <= conv_std_logic_vector(1227,11); WHEN "0010001111" => manhi <= conv_std_logic_vector(3955285,24); manlo <= conv_std_logic_vector(80970159,28); exponent <= conv_std_logic_vector(1229,11); WHEN "0010010000" => manhi <= conv_std_logic_vector(11401174,24); manlo <= conv_std_logic_vector(207600506,28); exponent <= conv_std_logic_vector(1230,11); WHEN "0010010001" => manhi <= conv_std_logic_vector(2371985,24); manlo <= conv_std_logic_vector(241221170,28); exponent <= conv_std_logic_vector(1232,11); WHEN "0010010010" => manhi <= conv_std_logic_vector(9249247,24); manlo <= conv_std_logic_vector(208105818,28); exponent <= conv_std_logic_vector(1233,11); WHEN "0010010011" => manhi <= conv_std_logic_vector(909599,24); manlo <= conv_std_logic_vector(237519888,28); exponent <= conv_std_logic_vector(1235,11); WHEN "0010010100" => manhi <= conv_std_logic_vector(7261659,24); manlo <= conv_std_logic_vector(29935335,28); exponent <= conv_std_logic_vector(1236,11); WHEN "0010010101" => manhi <= conv_std_logic_vector(15895002,24); manlo <= conv_std_logic_vector(186862656,28); exponent <= conv_std_logic_vector(1237,11); WHEN "0010010110" => manhi <= conv_std_logic_vector(5425858,24); manlo <= conv_std_logic_vector(159524243,28); exponent <= conv_std_logic_vector(1239,11); WHEN "0010010111" => manhi <= conv_std_logic_vector(13399891,24); manlo <= conv_std_logic_vector(27586577,28); exponent <= conv_std_logic_vector(1240,11); WHEN "0010011000" => manhi <= conv_std_logic_vector(3730254,24); manlo <= conv_std_logic_vector(125689310,28); exponent <= conv_std_logic_vector(1242,11); WHEN "0010011001" => manhi <= conv_std_logic_vector(11095326,24); manlo <= conv_std_logic_vector(43144000,28); exponent <= conv_std_logic_vector(1243,11); WHEN "0010011010" => manhi <= conv_std_logic_vector(2164140,24); manlo <= conv_std_logic_vector(58280992,28); exponent <= conv_std_logic_vector(1245,11); WHEN "0010011011" => manhi <= conv_std_logic_vector(8966756,24); manlo <= conv_std_logic_vector(55210422,28); exponent <= conv_std_logic_vector(1246,11); WHEN "0010011100" => manhi <= conv_std_logic_vector(717626,24); manlo <= conv_std_logic_vector(257633658,28); exponent <= conv_std_logic_vector(1248,11); WHEN "0010011101" => manhi <= conv_std_logic_vector(7000740,24); manlo <= conv_std_logic_vector(229413090,28); exponent <= conv_std_logic_vector(1249,11); WHEN "0010011110" => manhi <= conv_std_logic_vector(15540378,24); manlo <= conv_std_logic_vector(4808337,28); exponent <= conv_std_logic_vector(1250,11); WHEN "0010011111" => manhi <= conv_std_logic_vector(5184866,24); manlo <= conv_std_logic_vector(37474138,28); exponent <= conv_std_logic_vector(1252,11); WHEN "0010100000" => manhi <= conv_std_logic_vector(13072348,24); manlo <= conv_std_logic_vector(106730632,28); exponent <= conv_std_logic_vector(1253,11); WHEN "0010100001" => manhi <= conv_std_logic_vector(3507666,24); manlo <= conv_std_logic_vector(32844500,28); exponent <= conv_std_logic_vector(1255,11); WHEN "0010100010" => manhi <= conv_std_logic_vector(10792797,24); manlo <= conv_std_logic_vector(62496090,28); exponent <= conv_std_logic_vector(1256,11); WHEN "0010100011" => manhi <= conv_std_logic_vector(1958550,24); manlo <= conv_std_logic_vector(132952012,28); exponent <= conv_std_logic_vector(1258,11); WHEN "0010100100" => manhi <= conv_std_logic_vector(8687330,24); manlo <= conv_std_logic_vector(215605290,28); exponent <= conv_std_logic_vector(1259,11); WHEN "0010100101" => manhi <= conv_std_logic_vector(527737,24); manlo <= conv_std_logic_vector(190928911,28); exponent <= conv_std_logic_vector(1261,11); WHEN "0010100110" => manhi <= conv_std_logic_vector(6742654,24); manlo <= conv_std_logic_vector(163162889,28); exponent <= conv_std_logic_vector(1262,11); WHEN "0010100111" => manhi <= conv_std_logic_vector(15189602,24); manlo <= conv_std_logic_vector(118241780,28); exponent <= conv_std_logic_vector(1263,11); WHEN "0010101000" => manhi <= conv_std_logic_vector(4946489,24); manlo <= conv_std_logic_vector(112771062,28); exponent <= conv_std_logic_vector(1265,11); WHEN "0010101001" => manhi <= conv_std_logic_vector(12748360,24); manlo <= conv_std_logic_vector(226864003,28); exponent <= conv_std_logic_vector(1266,11); WHEN "0010101010" => manhi <= conv_std_logic_vector(3287493,24); manlo <= conv_std_logic_vector(202192272,28); exponent <= conv_std_logic_vector(1268,11); WHEN "0010101011" => manhi <= conv_std_logic_vector(10493551,24); manlo <= conv_std_logic_vector(257093553,28); exponent <= conv_std_logic_vector(1269,11); WHEN "0010101100" => manhi <= conv_std_logic_vector(1755192,24); manlo <= conv_std_logic_vector(66281405,28); exponent <= conv_std_logic_vector(1271,11); WHEN "0010101101" => manhi <= conv_std_logic_vector(8410938,24); manlo <= conv_std_logic_vector(77199396,28); exponent <= conv_std_logic_vector(1272,11); WHEN "0010101110" => manhi <= conv_std_logic_vector(339909,24); manlo <= conv_std_logic_vector(140417186,28); exponent <= conv_std_logic_vector(1274,11); WHEN "0010101111" => manhi <= conv_std_logic_vector(6487369,24); manlo <= conv_std_logic_vector(169769464,28); exponent <= conv_std_logic_vector(1275,11); WHEN "0010110000" => manhi <= conv_std_logic_vector(14842634,24); manlo <= conv_std_logic_vector(49834035,28); exponent <= conv_std_logic_vector(1276,11); WHEN "0010110001" => manhi <= conv_std_logic_vector(4710700,24); manlo <= conv_std_logic_vector(11961455,28); exponent <= conv_std_logic_vector(1278,11); WHEN "0010110010" => manhi <= conv_std_logic_vector(12427889,24); manlo <= conv_std_logic_vector(230234502,28); exponent <= conv_std_logic_vector(1279,11); WHEN "0010110011" => manhi <= conv_std_logic_vector(3069711,24); manlo <= conv_std_logic_vector(36989233,28); exponent <= conv_std_logic_vector(1281,11); WHEN "0010110100" => manhi <= conv_std_logic_vector(10197554,24); manlo <= conv_std_logic_vector(186484869,28); exponent <= conv_std_logic_vector(1282,11); WHEN "0010110101" => manhi <= conv_std_logic_vector(1554041,24); manlo <= conv_std_logic_vector(67530342,28); exponent <= conv_std_logic_vector(1284,11); WHEN "0010110110" => manhi <= conv_std_logic_vector(8137545,24); manlo <= conv_std_logic_vector(198608842,28); exponent <= conv_std_logic_vector(1285,11); WHEN "0010110111" => manhi <= conv_std_logic_vector(154120,24); manlo <= conv_std_logic_vector(6569319,28); exponent <= conv_std_logic_vector(1287,11); WHEN "0010111000" => manhi <= conv_std_logic_vector(6234855,24); manlo <= conv_std_logic_vector(140506894,28); exponent <= conv_std_logic_vector(1288,11); WHEN "0010111001" => manhi <= conv_std_logic_vector(14499431,24); manlo <= conv_std_logic_vector(249287529,28); exponent <= conv_std_logic_vector(1289,11); WHEN "0010111010" => manhi <= conv_std_logic_vector(4477469,24); manlo <= conv_std_logic_vector(249618841,28); exponent <= conv_std_logic_vector(1291,11); WHEN "0010111011" => manhi <= conv_std_logic_vector(12110897,24); manlo <= conv_std_logic_vector(71519058,28); exponent <= conv_std_logic_vector(1292,11); WHEN "0010111100" => manhi <= conv_std_logic_vector(2854292,24); manlo <= conv_std_logic_vector(90637320,28); exponent <= conv_std_logic_vector(1294,11); WHEN "0010111101" => manhi <= conv_std_logic_vector(9904770,24); manlo <= conv_std_logic_vector(50932558,28); exponent <= conv_std_logic_vector(1295,11); WHEN "0010111110" => manhi <= conv_std_logic_vector(1355073,24); manlo <= conv_std_logic_vector(148093260,28); exponent <= conv_std_logic_vector(1297,11); WHEN "0010111111" => manhi <= conv_std_logic_vector(7867120,24); manlo <= conv_std_logic_vector(160620741,28); exponent <= conv_std_logic_vector(1298,11); WHEN "0011000000" => manhi <= conv_std_logic_vector(16717910,24); manlo <= conv_std_logic_vector(46942270,28); exponent <= conv_std_logic_vector(1299,11); WHEN "0011000001" => manhi <= conv_std_logic_vector(5985082,24); manlo <= conv_std_logic_vector(55237426,28); exponent <= conv_std_logic_vector(1301,11); WHEN "0011000010" => manhi <= conv_std_logic_vector(14159954,24); manlo <= conv_std_logic_vector(212966668,28); exponent <= conv_std_logic_vector(1302,11); WHEN "0011000011" => manhi <= conv_std_logic_vector(4246771,24); manlo <= conv_std_logic_vector(79962334,28); exponent <= conv_std_logic_vector(1304,11); WHEN "0011000100" => manhi <= conv_std_logic_vector(11797345,24); manlo <= conv_std_logic_vector(85038862,28); exponent <= conv_std_logic_vector(1305,11); WHEN "0011000101" => manhi <= conv_std_logic_vector(2641211,24); manlo <= conv_std_logic_vector(186806322,28); exponent <= conv_std_logic_vector(1307,11); WHEN "0011000110" => manhi <= conv_std_logic_vector(9615163,24); manlo <= conv_std_logic_vector(153415152,28); exponent <= conv_std_logic_vector(1308,11); WHEN "0011000111" => manhi <= conv_std_logic_vector(1158265,24); manlo <= conv_std_logic_vector(120731907,28); exponent <= conv_std_logic_vector(1310,11); WHEN "0011001000" => manhi <= conv_std_logic_vector(7599630,24); manlo <= conv_std_logic_vector(175764921,28); exponent <= conv_std_logic_vector(1311,11); WHEN "0011001001" => manhi <= conv_std_logic_vector(16354353,24); manlo <= conv_std_logic_vector(174054693,28); exponent <= conv_std_logic_vector(1312,11); WHEN "0011001010" => manhi <= conv_std_logic_vector(5738019,24); manlo <= conv_std_logic_vector(249885394,28); exponent <= conv_std_logic_vector(1314,11); WHEN "0011001011" => manhi <= conv_std_logic_vector(13824162,24); manlo <= conv_std_logic_vector(93203713,28); exponent <= conv_std_logic_vector(1315,11); WHEN "0011001100" => manhi <= conv_std_logic_vector(4018576,24); manlo <= conv_std_logic_vector(180323091,28); exponent <= conv_std_logic_vector(1317,11); WHEN "0011001101" => manhi <= conv_std_logic_vector(11487196,24); manlo <= conv_std_logic_vector(178245939,28); exponent <= conv_std_logic_vector(1318,11); WHEN "0011001110" => manhi <= conv_std_logic_vector(2430443,24); manlo <= conv_std_logic_vector(223919964,28); exponent <= conv_std_logic_vector(1320,11); WHEN "0011001111" => manhi <= conv_std_logic_vector(9328700,24); manlo <= conv_std_logic_vector(93205956,28); exponent <= conv_std_logic_vector(1321,11); WHEN "0011010000" => manhi <= conv_std_logic_vector(963593,24); manlo <= conv_std_logic_vector(135688620,28); exponent <= conv_std_logic_vector(1323,11); WHEN "0011010001" => manhi <= conv_std_logic_vector(7335044,24); manlo <= conv_std_logic_vector(13542358,28); exponent <= conv_std_logic_vector(1324,11); WHEN "0011010010" => manhi <= conv_std_logic_vector(15994743,24); manlo <= conv_std_logic_vector(45394459,28); exponent <= conv_std_logic_vector(1325,11); WHEN "0011010011" => manhi <= conv_std_logic_vector(5493639,24); manlo <= conv_std_logic_vector(73308838,28); exponent <= conv_std_logic_vector(1327,11); WHEN "0011010100" => manhi <= conv_std_logic_vector(13492014,24); manlo <= conv_std_logic_vector(160135181,28); exponent <= conv_std_logic_vector(1328,11); WHEN "0011010101" => manhi <= conv_std_logic_vector(3792858,24); manlo <= conv_std_logic_vector(234346738,28); exponent <= conv_std_logic_vector(1330,11); WHEN "0011010110" => manhi <= conv_std_logic_vector(11180414,24); manlo <= conv_std_logic_vector(98964646,28); exponent <= conv_std_logic_vector(1331,11); WHEN "0011010111" => manhi <= conv_std_logic_vector(2221963,24); manlo <= conv_std_logic_vector(174344531,28); exponent <= conv_std_logic_vector(1333,11); WHEN "0011011000" => manhi <= conv_std_logic_vector(9045346,24); manlo <= conv_std_logic_vector(106947534,28); exponent <= conv_std_logic_vector(1334,11); WHEN "0011011001" => manhi <= conv_std_logic_vector(771034,24); manlo <= conv_std_logic_vector(143065990,28); exponent <= conv_std_logic_vector(1336,11); WHEN "0011011010" => manhi <= conv_std_logic_vector(7073329,24); manlo <= conv_std_logic_vector(73148434,28); exponent <= conv_std_logic_vector(1337,11); WHEN "0011011011" => manhi <= conv_std_logic_vector(15639035,24); manlo <= conv_std_logic_vector(243346703,28); exponent <= conv_std_logic_vector(1338,11); WHEN "0011011100" => manhi <= conv_std_logic_vector(5251911,24); manlo <= conv_std_logic_vector(33842377,28); exponent <= conv_std_logic_vector(1340,11); WHEN "0011011101" => manhi <= conv_std_logic_vector(13163471,24); manlo <= conv_std_logic_vector(263552292,28); exponent <= conv_std_logic_vector(1341,11); WHEN "0011011110" => manhi <= conv_std_logic_vector(3569591,24); manlo <= conv_std_logic_vector(4866264,28); exponent <= conv_std_logic_vector(1343,11); WHEN "0011011111" => manhi <= conv_std_logic_vector(10876961,24); manlo <= conv_std_logic_vector(239517036,28); exponent <= conv_std_logic_vector(1344,11); WHEN "0011100000" => manhi <= conv_std_logic_vector(2015746,24); manlo <= conv_std_logic_vector(83586287,28); exponent <= conv_std_logic_vector(1346,11); WHEN "0011100001" => manhi <= conv_std_logic_vector(8765067,24); manlo <= conv_std_logic_vector(262254542,28); exponent <= conv_std_logic_vector(1347,11); WHEN "0011100010" => manhi <= conv_std_logic_vector(580565,24); manlo <= conv_std_logic_vector(160521039,28); exponent <= conv_std_logic_vector(1349,11); WHEN "0011100011" => manhi <= conv_std_logic_vector(6814455,24); manlo <= conv_std_logic_vector(40288155,28); exponent <= conv_std_logic_vector(1350,11); WHEN "0011100100" => manhi <= conv_std_logic_vector(15287189,24); manlo <= conv_std_logic_vector(132910147,28); exponent <= conv_std_logic_vector(1351,11); WHEN "0011100101" => manhi <= conv_std_logic_vector(5012806,24); manlo <= conv_std_logic_vector(187753904,28); exponent <= conv_std_logic_vector(1353,11); WHEN "0011100110" => manhi <= conv_std_logic_vector(12838495,24); manlo <= conv_std_logic_vector(100071648,28); exponent <= conv_std_logic_vector(1354,11); WHEN "0011100111" => manhi <= conv_std_logic_vector(3348746,24); manlo <= conv_std_logic_vector(138348888,28); exponent <= conv_std_logic_vector(1356,11); WHEN "0011101000" => manhi <= conv_std_logic_vector(10576803,24); manlo <= conv_std_logic_vector(24941937,28); exponent <= conv_std_logic_vector(1357,11); WHEN "0011101001" => manhi <= conv_std_logic_vector(1811767,24); manlo <= conv_std_logic_vector(69497619,28); exponent <= conv_std_logic_vector(1359,11); WHEN "0011101010" => manhi <= conv_std_logic_vector(8487831,24); manlo <= conv_std_logic_vector(188199296,28); exponent <= conv_std_logic_vector(1360,11); WHEN "0011101011" => manhi <= conv_std_logic_vector(392164,24); manlo <= conv_std_logic_vector(4096525,28); exponent <= conv_std_logic_vector(1362,11); WHEN "0011101100" => manhi <= conv_std_logic_vector(6558390,24); manlo <= conv_std_logic_vector(228356857,28); exponent <= conv_std_logic_vector(1363,11); WHEN "0011101101" => manhi <= conv_std_logic_vector(14939162,24); manlo <= conv_std_logic_vector(7826265,28); exponent <= conv_std_logic_vector(1364,11); WHEN "0011101110" => manhi <= conv_std_logic_vector(4776297,24); manlo <= conv_std_logic_vector(138324122,28); exponent <= conv_std_logic_vector(1366,11); WHEN "0011101111" => manhi <= conv_std_logic_vector(12517046,24); manlo <= conv_std_logic_vector(17190560,28); exponent <= conv_std_logic_vector(1367,11); WHEN "0011110000" => manhi <= conv_std_logic_vector(3130299,24); manlo <= conv_std_logic_vector(16562242,28); exponent <= conv_std_logic_vector(1369,11); WHEN "0011110001" => manhi <= conv_std_logic_vector(10279902,24); manlo <= conv_std_logic_vector(59323104,28); exponent <= conv_std_logic_vector(1370,11); WHEN "0011110010" => manhi <= conv_std_logic_vector(1610002,24); manlo <= conv_std_logic_vector(53056333,28); exponent <= conv_std_logic_vector(1372,11); WHEN "0011110011" => manhi <= conv_std_logic_vector(8213604,24); manlo <= conv_std_logic_vector(147986337,28); exponent <= conv_std_logic_vector(1373,11); WHEN "0011110100" => manhi <= conv_std_logic_vector(205807,24); manlo <= conv_std_logic_vector(92802035,28); exponent <= conv_std_logic_vector(1375,11); WHEN "0011110101" => manhi <= conv_std_logic_vector(6305105,24); manlo <= conv_std_logic_vector(235277170,28); exponent <= conv_std_logic_vector(1376,11); WHEN "0011110110" => manhi <= conv_std_logic_vector(14594912,24); manlo <= conv_std_logic_vector(15497684,28); exponent <= conv_std_logic_vector(1377,11); WHEN "0011110111" => manhi <= conv_std_logic_vector(4542355,24); manlo <= conv_std_logic_vector(108677892,28); exponent <= conv_std_logic_vector(1379,11); WHEN "0011111000" => manhi <= conv_std_logic_vector(12199085,24); manlo <= conv_std_logic_vector(206743222,28); exponent <= conv_std_logic_vector(1380,11); WHEN "0011111001" => manhi <= conv_std_logic_vector(2914222,24); manlo <= conv_std_logic_vector(171652524,28); exponent <= conv_std_logic_vector(1382,11); WHEN "0011111010" => manhi <= conv_std_logic_vector(9986223,24); manlo <= conv_std_logic_vector(245598061,28); exponent <= conv_std_logic_vector(1383,11); WHEN "0011111011" => manhi <= conv_std_logic_vector(1410427,24); manlo <= conv_std_logic_vector(26024388,28); exponent <= conv_std_logic_vector(1385,11); WHEN "0011111100" => manhi <= conv_std_logic_vector(7942353,24); manlo <= conv_std_logic_vector(232590388,28); exponent <= conv_std_logic_vector(1386,11); WHEN "0011111101" => manhi <= conv_std_logic_vector(21473,24); manlo <= conv_std_logic_vector(105719295,28); exponent <= conv_std_logic_vector(1388,11); WHEN "0011111110" => manhi <= conv_std_logic_vector(6054570,24); manlo <= conv_std_logic_vector(16265786,28); exponent <= conv_std_logic_vector(1389,11); WHEN "0011111111" => manhi <= conv_std_logic_vector(14254398,24); manlo <= conv_std_logic_vector(155662944,28); exponent <= conv_std_logic_vector(1390,11); WHEN "0100000000" => manhi <= conv_std_logic_vector(4310952,24); manlo <= conv_std_logic_vector(135577274,28); exponent <= conv_std_logic_vector(1392,11); WHEN "0100000001" => manhi <= conv_std_logic_vector(11884576,24); manlo <= conv_std_logic_vector(166805756,28); exponent <= conv_std_logic_vector(1393,11); WHEN "0100000010" => manhi <= conv_std_logic_vector(2700491,24); manlo <= conv_std_logic_vector(137829044,28); exponent <= conv_std_logic_vector(1395,11); WHEN "0100000011" => manhi <= conv_std_logic_vector(9695733,24); manlo <= conv_std_logic_vector(52863001,28); exponent <= conv_std_logic_vector(1396,11); WHEN "0100000100" => manhi <= conv_std_logic_vector(1213018,24); manlo <= conv_std_logic_vector(50179603,28); exponent <= conv_std_logic_vector(1398,11); WHEN "0100000101" => manhi <= conv_std_logic_vector(7674047,24); manlo <= conv_std_logic_vector(91276680,28); exponent <= conv_std_logic_vector(1399,11); WHEN "0100000110" => manhi <= conv_std_logic_vector(16455496,24); manlo <= conv_std_logic_vector(110068760,28); exponent <= conv_std_logic_vector(1400,11); WHEN "0100000111" => manhi <= conv_std_logic_vector(5806753,24); manlo <= conv_std_logic_vector(151304445,28); exponent <= conv_std_logic_vector(1402,11); WHEN "0100001000" => manhi <= conv_std_logic_vector(13917581,24); manlo <= conv_std_logic_vector(10650184,28); exponent <= conv_std_logic_vector(1403,11); WHEN "0100001001" => manhi <= conv_std_logic_vector(4082061,24); manlo <= conv_std_logic_vector(68530707,28); exponent <= conv_std_logic_vector(1405,11); WHEN "0100001010" => manhi <= conv_std_logic_vector(11573481,24); manlo <= conv_std_logic_vector(42662756,28); exponent <= conv_std_logic_vector(1406,11); WHEN "0100001011" => manhi <= conv_std_logic_vector(2489080,24); manlo <= conv_std_logic_vector(61154162,28); exponent <= conv_std_logic_vector(1408,11); WHEN "0100001100" => manhi <= conv_std_logic_vector(9408395,24); manlo <= conv_std_logic_vector(125867240,28); exponent <= conv_std_logic_vector(1409,11); WHEN "0100001101" => manhi <= conv_std_logic_vector(1017751,24); manlo <= conv_std_logic_vector(256555705,28); exponent <= conv_std_logic_vector(1411,11); WHEN "0100001110" => manhi <= conv_std_logic_vector(7408653,24); manlo <= conv_std_logic_vector(4309896,28); exponent <= conv_std_logic_vector(1412,11); WHEN "0100001111" => manhi <= conv_std_logic_vector(16094788,24); manlo <= conv_std_logic_vector(33800670,28); exponent <= conv_std_logic_vector(1413,11); WHEN "0100010000" => manhi <= conv_std_logic_vector(5561626,24); manlo <= conv_std_logic_vector(233573192,28); exponent <= conv_std_logic_vector(1415,11); WHEN "0100010001" => manhi <= conv_std_logic_vector(13584419,24); manlo <= conv_std_logic_vector(86257801,28); exponent <= conv_std_logic_vector(1416,11); WHEN "0100010010" => manhi <= conv_std_logic_vector(3855654,24); manlo <= conv_std_logic_vector(105782775,28); exponent <= conv_std_logic_vector(1418,11); WHEN "0100010011" => manhi <= conv_std_logic_vector(11265762,24); manlo <= conv_std_logic_vector(88738762,28); exponent <= conv_std_logic_vector(1419,11); WHEN "0100010100" => manhi <= conv_std_logic_vector(2279963,24); manlo <= conv_std_logic_vector(161858527,28); exponent <= conv_std_logic_vector(1421,11); WHEN "0100010101" => manhi <= conv_std_logic_vector(9124176,24); manlo <= conv_std_logic_vector(136423424,28); exponent <= conv_std_logic_vector(1422,11); WHEN "0100010110" => manhi <= conv_std_logic_vector(824605,24); manlo <= conv_std_logic_vector(39384255,28); exponent <= conv_std_logic_vector(1424,11); WHEN "0100010111" => manhi <= conv_std_logic_vector(7146139,24); manlo <= conv_std_logic_vector(76626123,28); exponent <= conv_std_logic_vector(1425,11); WHEN "0100011000" => manhi <= conv_std_logic_vector(15737994,24); manlo <= conv_std_logic_vector(261485765,28); exponent <= conv_std_logic_vector(1426,11); WHEN "0100011001" => manhi <= conv_std_logic_vector(5319160,24); manlo <= conv_std_logic_vector(210684009,28); exponent <= conv_std_logic_vector(1428,11); WHEN "0100011010" => manhi <= conv_std_logic_vector(13254873,24); manlo <= conv_std_logic_vector(199859160,28); exponent <= conv_std_logic_vector(1429,11); WHEN "0100011011" => manhi <= conv_std_logic_vector(3631704,24); manlo <= conv_std_logic_vector(256571707,28); exponent <= conv_std_logic_vector(1431,11); WHEN "0100011100" => manhi <= conv_std_logic_vector(10961383,24); manlo <= conv_std_logic_vector(130542749,28); exponent <= conv_std_logic_vector(1432,11); WHEN "0100011101" => manhi <= conv_std_logic_vector(2073116,24); manlo <= conv_std_logic_vector(196665136,28); exponent <= conv_std_logic_vector(1434,11); WHEN "0100011110" => manhi <= conv_std_logic_vector(8843042,24); manlo <= conv_std_logic_vector(124490661,28); exponent <= conv_std_logic_vector(1435,11); WHEN "0100011111" => manhi <= conv_std_logic_vector(633554,24); manlo <= conv_std_logic_vector(202834752,28); exponent <= conv_std_logic_vector(1437,11); WHEN "0100100000" => manhi <= conv_std_logic_vector(6886474,24); manlo <= conv_std_logic_vector(236822279,28); exponent <= conv_std_logic_vector(1438,11); WHEN "0100100001" => manhi <= conv_std_logic_vector(15385074,24); manlo <= conv_std_logic_vector(123405487,28); exponent <= conv_std_logic_vector(1439,11); WHEN "0100100010" => manhi <= conv_std_logic_vector(5079326,24); manlo <= conv_std_logic_vector(115311954,28); exponent <= conv_std_logic_vector(1441,11); WHEN "0100100011" => manhi <= conv_std_logic_vector(12928905,24); manlo <= conv_std_logic_vector(16004876,28); exponent <= conv_std_logic_vector(1442,11); WHEN "0100100100" => manhi <= conv_std_logic_vector(3410186,24); manlo <= conv_std_logic_vector(71831800,28); exponent <= conv_std_logic_vector(1444,11); WHEN "0100100101" => manhi <= conv_std_logic_vector(10660308,24); manlo <= conv_std_logic_vector(100367284,28); exponent <= conv_std_logic_vector(1445,11); WHEN "0100100110" => manhi <= conv_std_logic_vector(1868514,24); manlo <= conv_std_logic_vector(263299419,28); exponent <= conv_std_logic_vector(1447,11); WHEN "0100100111" => manhi <= conv_std_logic_vector(8564959,24); manlo <= conv_std_logic_vector(228656810,28); exponent <= conv_std_logic_vector(1448,11); WHEN "0100101000" => manhi <= conv_std_logic_vector(444578,24); manlo <= conv_std_logic_vector(7489141,28); exponent <= conv_std_logic_vector(1450,11); WHEN "0100101001" => manhi <= conv_std_logic_vector(6629628,24); manlo <= conv_std_logic_vector(236156491,28); exponent <= conv_std_logic_vector(1451,11); WHEN "0100101010" => manhi <= conv_std_logic_vector(15035984,24); manlo <= conv_std_logic_vector(147396312,28); exponent <= conv_std_logic_vector(1452,11); WHEN "0100101011" => manhi <= conv_std_logic_vector(4842095,24); manlo <= conv_std_logic_vector(64271882,28); exponent <= conv_std_logic_vector(1454,11); WHEN "0100101100" => manhi <= conv_std_logic_vector(12606474,24); manlo <= conv_std_logic_vector(118909770,28); exponent <= conv_std_logic_vector(1455,11); WHEN "0100101101" => manhi <= conv_std_logic_vector(3191071,24); manlo <= conv_std_logic_vector(253953386,28); exponent <= conv_std_logic_vector(1457,11); WHEN "0100101110" => manhi <= conv_std_logic_vector(10362501,24); manlo <= conv_std_logic_vector(36129498,28); exponent <= conv_std_logic_vector(1458,11); WHEN "0100101111" => manhi <= conv_std_logic_vector(1666133,24); manlo <= conv_std_logic_vector(262830684,28); exponent <= conv_std_logic_vector(1460,11); WHEN "0100110000" => manhi <= conv_std_logic_vector(8289895,24); manlo <= conv_std_logic_vector(148197046,28); exponent <= conv_std_logic_vector(1461,11); WHEN "0100110001" => manhi <= conv_std_logic_vector(257652,24); manlo <= conv_std_logic_vector(122404338,28); exponent <= conv_std_logic_vector(1463,11); WHEN "0100110010" => manhi <= conv_std_logic_vector(6375570,24); manlo <= conv_std_logic_vector(184430245,28); exponent <= conv_std_logic_vector(1464,11); WHEN "0100110011" => manhi <= conv_std_logic_vector(14690683,24); manlo <= conv_std_logic_vector(178457687,28); exponent <= conv_std_logic_vector(1465,11); WHEN "0100110100" => manhi <= conv_std_logic_vector(4607438,24); manlo <= conv_std_logic_vector(257605193,28); exponent <= conv_std_logic_vector(1467,11); WHEN "0100110101" => manhi <= conv_std_logic_vector(12287543,24); manlo <= conv_std_logic_vector(132163446,28); exponent <= conv_std_logic_vector(1468,11); WHEN "0100110110" => manhi <= conv_std_logic_vector(2974335,24); manlo <= conv_std_logic_vector(240020217,28); exponent <= conv_std_logic_vector(1470,11); WHEN "0100110111" => manhi <= conv_std_logic_vector(10067926,24); manlo <= conv_std_logic_vector(80224641,28); exponent <= conv_std_logic_vector(1471,11); WHEN "0100111000" => manhi <= conv_std_logic_vector(1465949,24); manlo <= conv_std_logic_vector(167328478,28); exponent <= conv_std_logic_vector(1473,11); WHEN "0100111001" => manhi <= conv_std_logic_vector(8017816,24); manlo <= conv_std_logic_vector(215756784,28); exponent <= conv_std_logic_vector(1474,11); WHEN "0100111010" => manhi <= conv_std_logic_vector(72755,24); manlo <= conv_std_logic_vector(208473528,28); exponent <= conv_std_logic_vector(1476,11); WHEN "0100111011" => manhi <= conv_std_logic_vector(6124270,24); manlo <= conv_std_logic_vector(12139444,28); exponent <= conv_std_logic_vector(1477,11); WHEN "0100111100" => manhi <= conv_std_logic_vector(14349130,24); manlo <= conv_std_logic_vector(182729110,28); exponent <= conv_std_logic_vector(1478,11); WHEN "0100111101" => manhi <= conv_std_logic_vector(4375329,24); manlo <= conv_std_logic_vector(172370119,28); exponent <= conv_std_logic_vector(1480,11); WHEN "0100111110" => manhi <= conv_std_logic_vector(11972074,24); manlo <= conv_std_logic_vector(59679792,28); exponent <= conv_std_logic_vector(1481,11); WHEN "0100111111" => manhi <= conv_std_logic_vector(2759952,24); manlo <= conv_std_logic_vector(80023302,28); exponent <= conv_std_logic_vector(1483,11); WHEN "0101000000" => manhi <= conv_std_logic_vector(9776548,24); manlo <= conv_std_logic_vector(209956608,28); exponent <= conv_std_logic_vector(1484,11); WHEN "0101000001" => manhi <= conv_std_logic_vector(1267938,24); manlo <= conv_std_logic_vector(19091951,28); exponent <= conv_std_logic_vector(1486,11); WHEN "0101000010" => manhi <= conv_std_logic_vector(7748691,24); manlo <= conv_std_logic_vector(54127000,28); exponent <= conv_std_logic_vector(1487,11); WHEN "0101000011" => manhi <= conv_std_logic_vector(16556947,24); manlo <= conv_std_logic_vector(251347868,28); exponent <= conv_std_logic_vector(1488,11); WHEN "0101000100" => manhi <= conv_std_logic_vector(5875697,24); manlo <= conv_std_logic_vector(6377900,28); exponent <= conv_std_logic_vector(1490,11); WHEN "0101000101" => manhi <= conv_std_logic_vector(14011284,24); manlo <= conv_std_logic_vector(246175281,28); exponent <= conv_std_logic_vector(1491,11); WHEN "0101000110" => manhi <= conv_std_logic_vector(4145739,24); manlo <= conv_std_logic_vector(172360927,28); exponent <= conv_std_logic_vector(1493,11); WHEN "0101000111" => manhi <= conv_std_logic_vector(11660029,24); manlo <= conv_std_logic_vector(16047086,28); exponent <= conv_std_logic_vector(1494,11); WHEN "0101001000" => manhi <= conv_std_logic_vector(2547895,24); manlo <= conv_std_logic_vector(167600151,28); exponent <= conv_std_logic_vector(1496,11); WHEN "0101001001" => manhi <= conv_std_logic_vector(9488333,24); manlo <= conv_std_logic_vector(236416250,28); exponent <= conv_std_logic_vector(1497,11); WHEN "0101001010" => manhi <= conv_std_logic_vector(1072075,24); manlo <= conv_std_logic_vector(198323037,28); exponent <= conv_std_logic_vector(1499,11); WHEN "0101001011" => manhi <= conv_std_logic_vector(7482486,24); manlo <= conv_std_logic_vector(185820926,28); exponent <= conv_std_logic_vector(1500,11); WHEN "0101001100" => manhi <= conv_std_logic_vector(16195138,24); manlo <= conv_std_logic_vector(133160968,28); exponent <= conv_std_logic_vector(1501,11); WHEN "0101001101" => manhi <= conv_std_logic_vector(5629822,24); manlo <= conv_std_logic_vector(4574050,28); exponent <= conv_std_logic_vector(1503,11); WHEN "0101001110" => manhi <= conv_std_logic_vector(13677106,24); manlo <= conv_std_logic_vector(36414601,28); exponent <= conv_std_logic_vector(1504,11); WHEN "0101001111" => manhi <= conv_std_logic_vector(3918641,24); manlo <= conv_std_logic_vector(165046798,28); exponent <= conv_std_logic_vector(1506,11); WHEN "0101010000" => manhi <= conv_std_logic_vector(11351370,24); manlo <= conv_std_logic_vector(225326735,28); exponent <= conv_std_logic_vector(1507,11); WHEN "0101010001" => manhi <= conv_std_logic_vector(2338140,24); manlo <= conv_std_logic_vector(165476611,28); exponent <= conv_std_logic_vector(1509,11); WHEN "0101010010" => manhi <= conv_std_logic_vector(9203247,24); manlo <= conv_std_logic_vector(71807303,28); exponent <= conv_std_logic_vector(1510,11); WHEN "0101010011" => manhi <= conv_std_logic_vector(878339,24); manlo <= conv_std_logic_vector(80195176,28); exponent <= conv_std_logic_vector(1512,11); WHEN "0101010100" => manhi <= conv_std_logic_vector(7219171,24); manlo <= conv_std_logic_vector(153001068,28); exponent <= conv_std_logic_vector(1513,11); WHEN "0101010101" => manhi <= conv_std_logic_vector(15837256,24); manlo <= conv_std_logic_vector(37596960,28); exponent <= conv_std_logic_vector(1514,11); WHEN "0101010110" => manhi <= conv_std_logic_vector(5386615,24); manlo <= conv_std_logic_vector(198850796,28); exponent <= conv_std_logic_vector(1516,11); WHEN "0101010111" => manhi <= conv_std_logic_vector(13346554,24); manlo <= conv_std_logic_vector(143609986,28); exponent <= conv_std_logic_vector(1517,11); WHEN "0101011000" => manhi <= conv_std_logic_vector(3694008,24); manlo <= conv_std_logic_vector(137568494,28); exponent <= conv_std_logic_vector(1519,11); WHEN "0101011001" => manhi <= conv_std_logic_vector(11046062,24); manlo <= conv_std_logic_vector(214558683,28); exponent <= conv_std_logic_vector(1520,11); WHEN "0101011010" => manhi <= conv_std_logic_vector(2130662,24); manlo <= conv_std_logic_vector(78401205,28); exponent <= conv_std_logic_vector(1522,11); WHEN "0101011011" => manhi <= conv_std_logic_vector(8921254,24); manlo <= conv_std_logic_vector(265219821,28); exponent <= conv_std_logic_vector(1523,11); WHEN "0101011100" => manhi <= conv_std_logic_vector(686705,24); manlo <= conv_std_logic_vector(181591149,28); exponent <= conv_std_logic_vector(1525,11); WHEN "0101011101" => manhi <= conv_std_logic_vector(6958714,24); manlo <= conv_std_logic_vector(127078273,28); exponent <= conv_std_logic_vector(1526,11); WHEN "0101011110" => manhi <= conv_std_logic_vector(15483258,24); manlo <= conv_std_logic_vector(65420394,28); exponent <= conv_std_logic_vector(1527,11); WHEN "0101011111" => manhi <= conv_std_logic_vector(5146049,24); manlo <= conv_std_logic_vector(61347424,28); exponent <= conv_std_logic_vector(1529,11); WHEN "0101100000" => manhi <= conv_std_logic_vector(13019590,24); manlo <= conv_std_logic_vector(200148168,28); exponent <= conv_std_logic_vector(1530,11); WHEN "0101100001" => manhi <= conv_std_logic_vector(3471813,24); manlo <= conv_std_logic_vector(155873600,28); exponent <= conv_std_logic_vector(1532,11); WHEN "0101100010" => manhi <= conv_std_logic_vector(10744068,24); manlo <= conv_std_logic_vector(154763366,28); exponent <= conv_std_logic_vector(1533,11); WHEN "0101100011" => manhi <= conv_std_logic_vector(1925435,24); manlo <= conv_std_logic_vector(252346422,28); exponent <= conv_std_logic_vector(1535,11); WHEN "0101100100" => manhi <= conv_std_logic_vector(8642323,24); manlo <= conv_std_logic_vector(122496413,28); exponent <= conv_std_logic_vector(1536,11); WHEN "0101100101" => manhi <= conv_std_logic_vector(497152,24); manlo <= conv_std_logic_vector(12881703,28); exponent <= conv_std_logic_vector(1538,11); WHEN "0101100110" => manhi <= conv_std_logic_vector(6701084,24); manlo <= conv_std_logic_vector(102402698,28); exponent <= conv_std_logic_vector(1539,11); WHEN "0101100111" => manhi <= conv_std_logic_vector(15133102,24); manlo <= conv_std_logic_vector(173151546,28); exponent <= conv_std_logic_vector(1540,11); WHEN "0101101000" => manhi <= conv_std_logic_vector(4908093,24); manlo <= conv_std_logic_vector(222341698,28); exponent <= conv_std_logic_vector(1542,11); WHEN "0101101001" => manhi <= conv_std_logic_vector(12696175,24); manlo <= conv_std_logic_vector(221558290,28); exponent <= conv_std_logic_vector(1543,11); WHEN "0101101010" => manhi <= conv_std_logic_vector(3252030,24); manlo <= conv_std_logic_vector(95425703,28); exponent <= conv_std_logic_vector(1545,11); WHEN "0101101011" => manhi <= conv_std_logic_vector(10445352,24); manlo <= conv_std_logic_vector(54472775,28); exponent <= conv_std_logic_vector(1546,11); WHEN "0101101100" => manhi <= conv_std_logic_vector(1722437,24); manlo <= conv_std_logic_vector(31541381,28); exponent <= conv_std_logic_vector(1548,11); WHEN "0101101101" => manhi <= conv_std_logic_vector(8366419,24); manlo <= conv_std_logic_vector(121077564,28); exponent <= conv_std_logic_vector(1549,11); WHEN "0101101110" => manhi <= conv_std_logic_vector(309655,24); manlo <= conv_std_logic_vector(224679493,28); exponent <= conv_std_logic_vector(1551,11); WHEN "0101101111" => manhi <= conv_std_logic_vector(6446250,24); manlo <= conv_std_logic_vector(163707479,28); exponent <= conv_std_logic_vector(1552,11); WHEN "0101110000" => manhi <= conv_std_logic_vector(14786747,24); manlo <= conv_std_logic_vector(171718440,28); exponent <= conv_std_logic_vector(1553,11); WHEN "0101110001" => manhi <= conv_std_logic_vector(4672721,24); manlo <= conv_std_logic_vector(53414720,28); exponent <= conv_std_logic_vector(1555,11); WHEN "0101110010" => manhi <= conv_std_logic_vector(12376271,24); manlo <= conv_std_logic_vector(68395953,28); exponent <= conv_std_logic_vector(1556,11); WHEN "0101110011" => manhi <= conv_std_logic_vector(3034632,24); manlo <= conv_std_logic_vector(177229210,28); exponent <= conv_std_logic_vector(1558,11); WHEN "0101110100" => manhi <= conv_std_logic_vector(10149878,24); manlo <= conv_std_logic_vector(27015960,28); exponent <= conv_std_logic_vector(1559,11); WHEN "0101110101" => manhi <= conv_std_logic_vector(1521641,24); manlo <= conv_std_logic_vector(173609470,28); exponent <= conv_std_logic_vector(1561,11); WHEN "0101110110" => manhi <= conv_std_logic_vector(8093510,24); manlo <= conv_std_logic_vector(29891310,28); exponent <= conv_std_logic_vector(1562,11); WHEN "0101110111" => manhi <= conv_std_logic_vector(124194,24); manlo <= conv_std_logic_vector(191198183,28); exponent <= conv_std_logic_vector(1564,11); WHEN "0101111000" => manhi <= conv_std_logic_vector(6194182,24); manlo <= conv_std_logic_vector(216692261,28); exponent <= conv_std_logic_vector(1565,11); WHEN "0101111001" => manhi <= conv_std_logic_vector(14444151,24); manlo <= conv_std_logic_vector(261994424,28); exponent <= conv_std_logic_vector(1566,11); WHEN "0101111010" => manhi <= conv_std_logic_vector(4439903,24); manlo <= conv_std_logic_vector(82463931,28); exponent <= conv_std_logic_vector(1568,11); WHEN "0101111011" => manhi <= conv_std_logic_vector(12059838,24); manlo <= conv_std_logic_vector(250318074,28); exponent <= conv_std_logic_vector(1569,11); WHEN "0101111100" => manhi <= conv_std_logic_vector(2819594,24); manlo <= conv_std_logic_vector(161686084,28); exponent <= conv_std_logic_vector(1571,11); WHEN "0101111101" => manhi <= conv_std_logic_vector(9857611,24); manlo <= conv_std_logic_vector(20946108,28); exponent <= conv_std_logic_vector(1572,11); WHEN "0101111110" => manhi <= conv_std_logic_vector(1323025,24); manlo <= conv_std_logic_vector(164440795,28); exponent <= conv_std_logic_vector(1574,11); WHEN "0101111111" => manhi <= conv_std_logic_vector(7823562,24); manlo <= conv_std_logic_vector(250479918,28); exponent <= conv_std_logic_vector(1575,11); WHEN "0110000000" => manhi <= conv_std_logic_vector(16658709,24); manlo <= conv_std_logic_vector(45608811,28); exponent <= conv_std_logic_vector(1576,11); WHEN "0110000001" => manhi <= conv_std_logic_vector(5944850,24); manlo <= conv_std_logic_vector(255488281,28); exponent <= conv_std_logic_vector(1578,11); WHEN "0110000010" => manhi <= conv_std_logic_vector(14105274,24); manlo <= conv_std_logic_vector(228172930,28); exponent <= conv_std_logic_vector(1579,11); WHEN "0110000011" => manhi <= conv_std_logic_vector(4209612,24); manlo <= conv_std_logic_vector(113758652,28); exponent <= conv_std_logic_vector(1581,11); WHEN "0110000100" => manhi <= conv_std_logic_vector(11746841,24); manlo <= conv_std_logic_vector(45816542,28); exponent <= conv_std_logic_vector(1582,11); WHEN "0110000101" => manhi <= conv_std_logic_vector(2606890,24); manlo <= conv_std_logic_vector(153074390,28); exponent <= conv_std_logic_vector(1584,11); WHEN "0110000110" => manhi <= conv_std_logic_vector(9568516,24); manlo <= conv_std_logic_vector(87350878,28); exponent <= conv_std_logic_vector(1585,11); WHEN "0110000111" => manhi <= conv_std_logic_vector(1126565,24); manlo <= conv_std_logic_vector(96475766,28); exponent <= conv_std_logic_vector(1587,11); WHEN "0110001000" => manhi <= conv_std_logic_vector(7556545,24); manlo <= conv_std_logic_vector(205347948,28); exponent <= conv_std_logic_vector(1588,11); WHEN "0110001001" => manhi <= conv_std_logic_vector(16295795,24); manlo <= conv_std_logic_vector(56881285,28); exponent <= conv_std_logic_vector(1589,11); WHEN "0110001010" => manhi <= conv_std_logic_vector(5698225,24); manlo <= conv_std_logic_vector(93263076,28); exponent <= conv_std_logic_vector(1591,11); WHEN "0110001011" => manhi <= conv_std_logic_vector(13770075,24); manlo <= conv_std_logic_vector(241769289,28); exponent <= conv_std_logic_vector(1592,11); WHEN "0110001100" => manhi <= conv_std_logic_vector(3981821,24); manlo <= conv_std_logic_vector(32359920,28); exponent <= conv_std_logic_vector(1594,11); WHEN "0110001101" => manhi <= conv_std_logic_vector(11437240,24); manlo <= conv_std_logic_vector(185367850,28); exponent <= conv_std_logic_vector(1595,11); WHEN "0110001110" => manhi <= conv_std_logic_vector(2396495,24); manlo <= conv_std_logic_vector(61858550,28); exponent <= conv_std_logic_vector(1597,11); WHEN "0110001111" => manhi <= conv_std_logic_vector(9282559,24); manlo <= conv_std_logic_vector(110304027,28); exponent <= conv_std_logic_vector(1598,11); WHEN "0110010000" => manhi <= conv_std_logic_vector(932237,24); manlo <= conv_std_logic_vector(131077892,28); exponent <= conv_std_logic_vector(1600,11); WHEN "0110010001" => manhi <= conv_std_logic_vector(7292426,24); manlo <= conv_std_logic_vector(215982528,28); exponent <= conv_std_logic_vector(1601,11); WHEN "0110010010" => manhi <= conv_std_logic_vector(15936820,24); manlo <= conv_std_logic_vector(87676082,28); exponent <= conv_std_logic_vector(1602,11); WHEN "0110010011" => manhi <= conv_std_logic_vector(5454276,24); manlo <= conv_std_logic_vector(166577430,28); exponent <= conv_std_logic_vector(1604,11); WHEN "0110010100" => manhi <= conv_std_logic_vector(13438515,24); manlo <= conv_std_logic_vector(55023964,28); exponent <= conv_std_logic_vector(1605,11); WHEN "0110010101" => manhi <= conv_std_logic_vector(3756502,24); manlo <= conv_std_logic_vector(71679026,28); exponent <= conv_std_logic_vector(1607,11); WHEN "0110010110" => manhi <= conv_std_logic_vector(11131000,24); manlo <= conv_std_logic_vector(165886683,28); exponent <= conv_std_logic_vector(1608,11); WHEN "0110010111" => manhi <= conv_std_logic_vector(2188383,24); manlo <= conv_std_logic_vector(140750309,28); exponent <= conv_std_logic_vector(1610,11); WHEN "0110011000" => manhi <= conv_std_logic_vector(8999706,24); manlo <= conv_std_logic_vector(74200045,28); exponent <= conv_std_logic_vector(1611,11); WHEN "0110011001" => manhi <= conv_std_logic_vector(740018,24); manlo <= conv_std_logic_vector(229350227,28); exponent <= conv_std_logic_vector(1613,11); WHEN "0110011010" => manhi <= conv_std_logic_vector(7031174,24); manlo <= conv_std_logic_vector(159659309,28); exponent <= conv_std_logic_vector(1614,11); WHEN "0110011011" => manhi <= conv_std_logic_vector(15581741,24); manlo <= conv_std_logic_vector(203828183,28); exponent <= conv_std_logic_vector(1615,11); WHEN "0110011100" => manhi <= conv_std_logic_vector(5212975,24); manlo <= conv_std_logic_vector(192268981,28); exponent <= conv_std_logic_vector(1617,11); WHEN "0110011101" => manhi <= conv_std_logic_vector(13110553,24); manlo <= conv_std_logic_vector(73367990,28); exponent <= conv_std_logic_vector(1618,11); WHEN "0110011110" => manhi <= conv_std_logic_vector(3533629,24); manlo <= conv_std_logic_vector(7303751,28); exponent <= conv_std_logic_vector(1620,11); WHEN "0110011111" => manhi <= conv_std_logic_vector(10828084,24); manlo <= conv_std_logic_vector(128595197,28); exponent <= conv_std_logic_vector(1621,11); WHEN "0110100000" => manhi <= conv_std_logic_vector(1982530,24); manlo <= conv_std_logic_vector(178601213,28); exponent <= conv_std_logic_vector(1623,11); WHEN "0110100001" => manhi <= conv_std_logic_vector(8719923,24); manlo <= conv_std_logic_vector(62665264,28); exponent <= conv_std_logic_vector(1624,11); WHEN "0110100010" => manhi <= conv_std_logic_vector(549886,24); manlo <= conv_std_logic_vector(151395401,28); exponent <= conv_std_logic_vector(1626,11); WHEN "0110100011" => manhi <= conv_std_logic_vector(6772758,24); manlo <= conv_std_logic_vector(5307652,28); exponent <= conv_std_logic_vector(1627,11); WHEN "0110100100" => manhi <= conv_std_logic_vector(15230517,24); manlo <= conv_std_logic_vector(58871965,28); exponent <= conv_std_logic_vector(1628,11); WHEN "0110100101" => manhi <= conv_std_logic_vector(4974293,24); manlo <= conv_std_logic_vector(240265124,28); exponent <= conv_std_logic_vector(1630,11); WHEN "0110100110" => manhi <= conv_std_logic_vector(12786151,24); manlo <= conv_std_logic_vector(11983156,28); exponent <= conv_std_logic_vector(1631,11); WHEN "0110100111" => manhi <= conv_std_logic_vector(3313174,24); manlo <= conv_std_logic_vector(229882212,28); exponent <= conv_std_logic_vector(1633,11); WHEN "0110101000" => manhi <= conv_std_logic_vector(10528456,24); manlo <= conv_std_logic_vector(52550536,28); exponent <= conv_std_logic_vector(1634,11); WHEN "0110101001" => manhi <= conv_std_logic_vector(1778912,24); manlo <= conv_std_logic_vector(36481057,28); exponent <= conv_std_logic_vector(1636,11); WHEN "0110101010" => manhi <= conv_std_logic_vector(8443176,24); manlo <= conv_std_logic_vector(257480801,28); exponent <= conv_std_logic_vector(1637,11); WHEN "0110101011" => manhi <= conv_std_logic_vector(361817,24); manlo <= conv_std_logic_vector(260890045,28); exponent <= conv_std_logic_vector(1639,11); WHEN "0110101100" => manhi <= conv_std_logic_vector(6517146,24); manlo <= conv_std_logic_vector(80951272,28); exponent <= conv_std_logic_vector(1640,11); WHEN "0110101101" => manhi <= conv_std_logic_vector(14883104,24); manlo <= conv_std_logic_vector(234866389,28); exponent <= conv_std_logic_vector(1641,11); WHEN "0110101110" => manhi <= conv_std_logic_vector(4738202,24); manlo <= conv_std_logic_vector(195793257,28); exponent <= conv_std_logic_vector(1643,11); WHEN "0110101111" => manhi <= conv_std_logic_vector(12465269,24); manlo <= conv_std_logic_vector(236730454,28); exponent <= conv_std_logic_vector(1644,11); WHEN "0110110000" => manhi <= conv_std_logic_vector(3095113,24); manlo <= conv_std_logic_vector(133661452,28); exponent <= conv_std_logic_vector(1646,11); WHEN "0110110001" => manhi <= conv_std_logic_vector(10232080,24); manlo <= conv_std_logic_vector(21926822,28); exponent <= conv_std_logic_vector(1647,11); WHEN "0110110010" => manhi <= conv_std_logic_vector(1577503,24); manlo <= conv_std_logic_vector(183764948,28); exponent <= conv_std_logic_vector(1649,11); WHEN "0110110011" => manhi <= conv_std_logic_vector(8169434,24); manlo <= conv_std_logic_vector(132210812,28); exponent <= conv_std_logic_vector(1650,11); WHEN "0110110100" => manhi <= conv_std_logic_vector(175790,24); manlo <= conv_std_logic_vector(182183516,28); exponent <= conv_std_logic_vector(1652,11); WHEN "0110110101" => manhi <= conv_std_logic_vector(6264308,24); manlo <= conv_std_logic_vector(267417858,28); exponent <= conv_std_logic_vector(1653,11); WHEN "0110110110" => manhi <= conv_std_logic_vector(14539463,24); manlo <= conv_std_logic_vector(93573944,28); exponent <= conv_std_logic_vector(1654,11); WHEN "0110110111" => manhi <= conv_std_logic_vector(4504674,24); manlo <= conv_std_logic_vector(26907375,28); exponent <= conv_std_logic_vector(1656,11); WHEN "0110111000" => manhi <= conv_std_logic_vector(12147871,24); manlo <= conv_std_logic_vector(152302066,28); exponent <= conv_std_logic_vector(1657,11); WHEN "0110111001" => manhi <= conv_std_logic_vector(2879418,24); manlo <= conv_std_logic_vector(263131635,28); exponent <= conv_std_logic_vector(1659,11); WHEN "0110111010" => manhi <= conv_std_logic_vector(9938920,24); manlo <= conv_std_logic_vector(224874222,28); exponent <= conv_std_logic_vector(1660,11); WHEN "0110111011" => manhi <= conv_std_logic_vector(1378281,24); manlo <= conv_std_logic_vector(86745210,28); exponent <= conv_std_logic_vector(1662,11); WHEN "0110111100" => manhi <= conv_std_logic_vector(7898663,24); manlo <= conv_std_logic_vector(61761420,28); exponent <= conv_std_logic_vector(1663,11); WHEN "0110111101" => manhi <= conv_std_logic_vector(16760781,24); manlo <= conv_std_logic_vector(15082626,28); exponent <= conv_std_logic_vector(1664,11); WHEN "0110111110" => manhi <= conv_std_logic_vector(6014215,24); manlo <= conv_std_logic_vector(265801199,28); exponent <= conv_std_logic_vector(1666,11); WHEN "0110111111" => manhi <= conv_std_logic_vector(14199551,24); manlo <= conv_std_logic_vector(191056853,28); exponent <= conv_std_logic_vector(1667,11); WHEN "0111000000" => manhi <= conv_std_logic_vector(4273680,24); manlo <= conv_std_logic_vector(52024524,28); exponent <= conv_std_logic_vector(1669,11); WHEN "0111000001" => manhi <= conv_std_logic_vector(11833918,24); manlo <= conv_std_logic_vector(80047690,28); exponent <= conv_std_logic_vector(1670,11); WHEN "0111000010" => manhi <= conv_std_logic_vector(2666065,24); manlo <= conv_std_logic_vector(164712049,28); exponent <= conv_std_logic_vector(1672,11); WHEN "0111000011" => manhi <= conv_std_logic_vector(9648943,24); manlo <= conv_std_logic_vector(147084012,28); exponent <= conv_std_logic_vector(1673,11); WHEN "0111000100" => manhi <= conv_std_logic_vector(1181221,24); manlo <= conv_std_logic_vector(86912647,28); exponent <= conv_std_logic_vector(1675,11); WHEN "0111000101" => manhi <= conv_std_logic_vector(7630830,24); manlo <= conv_std_logic_vector(247596521,28); exponent <= conv_std_logic_vector(1676,11); WHEN "0111000110" => manhi <= conv_std_logic_vector(16396759,24); manlo <= conv_std_logic_vector(56002502,28); exponent <= conv_std_logic_vector(1677,11); WHEN "0111000111" => manhi <= conv_std_logic_vector(5766837,24); manlo <= conv_std_logic_vector(133369322,28); exponent <= conv_std_logic_vector(1679,11); WHEN "0111001000" => manhi <= conv_std_logic_vector(13863329,24); manlo <= conv_std_logic_vector(128884889,28); exponent <= conv_std_logic_vector(1680,11); WHEN "0111001001" => manhi <= conv_std_logic_vector(4045193,24); manlo <= conv_std_logic_vector(133729186,28); exponent <= conv_std_logic_vector(1682,11); WHEN "0111001010" => manhi <= conv_std_logic_vector(11523372,24); manlo <= conv_std_logic_vector(183024104,28); exponent <= conv_std_logic_vector(1683,11); WHEN "0111001011" => manhi <= conv_std_logic_vector(2455027,24); manlo <= conv_std_logic_vector(264977965,28); exponent <= conv_std_logic_vector(1685,11); WHEN "0111001100" => manhi <= conv_std_logic_vector(9362113,24); manlo <= conv_std_logic_vector(181285013,28); exponent <= conv_std_logic_vector(1686,11); WHEN "0111001101" => manhi <= conv_std_logic_vector(986300,24); manlo <= conv_std_logic_vector(58020653,28); exponent <= conv_std_logic_vector(1688,11); WHEN "0111001110" => manhi <= conv_std_logic_vector(7365905,24); manlo <= conv_std_logic_vector(179835810,28); exponent <= conv_std_logic_vector(1689,11); WHEN "0111001111" => manhi <= conv_std_logic_vector(16036688,24); manlo <= conv_std_logic_vector(123168298,28); exponent <= conv_std_logic_vector(1690,11); WHEN "0111010000" => manhi <= conv_std_logic_vector(5522144,24); manlo <= conv_std_logic_vector(14176725,28); exponent <= conv_std_logic_vector(1692,11); WHEN "0111010001" => manhi <= conv_std_logic_vector(13530756,24); manlo <= conv_std_logic_vector(163453775,28); exponent <= conv_std_logic_vector(1693,11); WHEN "0111010010" => manhi <= conv_std_logic_vector(3819186,24); manlo <= conv_std_logic_vector(214764608,28); exponent <= conv_std_logic_vector(1695,11); WHEN "0111010011" => manhi <= conv_std_logic_vector(11216197,24); manlo <= conv_std_logic_vector(196364225,28); exponent <= conv_std_logic_vector(1696,11); WHEN "0111010100" => manhi <= conv_std_logic_vector(2246280,24); manlo <= conv_std_logic_vector(259235483,28); exponent <= conv_std_logic_vector(1698,11); WHEN "0111010101" => manhi <= conv_std_logic_vector(9078397,24); manlo <= conv_std_logic_vector(15526664,28); exponent <= conv_std_logic_vector(1699,11); WHEN "0111010110" => manhi <= conv_std_logic_vector(793494,24); manlo <= conv_std_logic_vector(210641201,28); exponent <= conv_std_logic_vector(1701,11); WHEN "0111010111" => manhi <= conv_std_logic_vector(7103855,24); manlo <= conv_std_logic_vector(246847656,28); exponent <= conv_std_logic_vector(1702,11); WHEN "0111011000" => manhi <= conv_std_logic_vector(15680525,24); manlo <= conv_std_logic_vector(247378795,28); exponent <= conv_std_logic_vector(1703,11); WHEN "0111011001" => manhi <= conv_std_logic_vector(5280106,24); manlo <= conv_std_logic_vector(138122391,28); exponent <= conv_std_logic_vector(1705,11); WHEN "0111011010" => manhi <= conv_std_logic_vector(13201793,24); manlo <= conv_std_logic_vector(130963079,28); exponent <= conv_std_logic_vector(1706,11); WHEN "0111011011" => manhi <= conv_std_logic_vector(3595633,24); manlo <= conv_std_logic_vector(48727293,28); exponent <= conv_std_logic_vector(1708,11); WHEN "0111011100" => manhi <= conv_std_logic_vector(10912356,24); manlo <= conv_std_logic_vector(231400966,28); exponent <= conv_std_logic_vector(1709,11); WHEN "0111011101" => manhi <= conv_std_logic_vector(2039799,24); manlo <= conv_std_logic_vector(184459756,28); exponent <= conv_std_logic_vector(1711,11); WHEN "0111011110" => manhi <= conv_std_logic_vector(8797759,24); manlo <= conv_std_logic_vector(242699544,28); exponent <= conv_std_logic_vector(1712,11); WHEN "0111011111" => manhi <= conv_std_logic_vector(602782,24); manlo <= conv_std_logic_vector(17680793,28); exponent <= conv_std_logic_vector(1714,11); WHEN "0111100000" => manhi <= conv_std_logic_vector(6844650,24); manlo <= conv_std_logic_vector(123627565,28); exponent <= conv_std_logic_vector(1715,11); WHEN "0111100001" => manhi <= conv_std_logic_vector(15328229,24); manlo <= conv_std_logic_vector(47512453,28); exponent <= conv_std_logic_vector(1716,11); WHEN "0111100010" => manhi <= conv_std_logic_vector(5040696,24); manlo <= conv_std_logic_vector(14711664,28); exponent <= conv_std_logic_vector(1718,11); WHEN "0111100011" => manhi <= conv_std_logic_vector(12876400,24); manlo <= conv_std_logic_vector(251456186,28); exponent <= conv_std_logic_vector(1719,11); WHEN "0111100100" => manhi <= conv_std_logic_vector(3374506,24); manlo <= conv_std_logic_vector(4512772,28); exponent <= conv_std_logic_vector(1721,11); WHEN "0111100101" => manhi <= conv_std_logic_vector(10611813,24); manlo <= conv_std_logic_vector(237626642,28); exponent <= conv_std_logic_vector(1722,11); WHEN "0111100110" => manhi <= conv_std_logic_vector(1835559,24); manlo <= conv_std_logic_vector(150064655,28); exponent <= conv_std_logic_vector(1724,11); WHEN "0111100111" => manhi <= conv_std_logic_vector(8520168,24); manlo <= conv_std_logic_vector(211971382,28); exponent <= conv_std_logic_vector(1725,11); WHEN "0111101000" => manhi <= conv_std_logic_vector(414139,24); manlo <= conv_std_logic_vector(92694471,28); exponent <= conv_std_logic_vector(1727,11); WHEN "0111101001" => manhi <= conv_std_logic_vector(6588258,24); manlo <= conv_std_logic_vector(112977613,28); exponent <= conv_std_logic_vector(1728,11); WHEN "0111101010" => manhi <= conv_std_logic_vector(14979756,24); manlo <= conv_std_logic_vector(71348470,28); exponent <= conv_std_logic_vector(1729,11); WHEN "0111101011" => manhi <= conv_std_logic_vector(4803884,24); manlo <= conv_std_logic_vector(42747344,28); exponent <= conv_std_logic_vector(1731,11); WHEN "0111101100" => manhi <= conv_std_logic_vector(12554540,24); manlo <= conv_std_logic_vector(53825836,28); exponent <= conv_std_logic_vector(1732,11); WHEN "0111101101" => manhi <= conv_std_logic_vector(3155778,24); manlo <= conv_std_logic_vector(260157975,28); exponent <= conv_std_logic_vector(1734,11); WHEN "0111101110" => manhi <= conv_std_logic_vector(10314533,24); manlo <= conv_std_logic_vector(1535990,28); exponent <= conv_std_logic_vector(1735,11); WHEN "0111101111" => manhi <= conv_std_logic_vector(1633536,24); manlo <= conv_std_logic_vector(68681060,28); exponent <= conv_std_logic_vector(1737,11); WHEN "0111110000" => manhi <= conv_std_logic_vector(8245590,24); manlo <= conv_std_logic_vector(175202070,28); exponent <= conv_std_logic_vector(1738,11); WHEN "0111110001" => manhi <= conv_std_logic_vector(227544,24); manlo <= conv_std_logic_vector(41675965,28); exponent <= conv_std_logic_vector(1740,11); WHEN "0111110010" => manhi <= conv_std_logic_vector(6334649,24); manlo <= conv_std_logic_vector(70777607,28); exponent <= conv_std_logic_vector(1741,11); WHEN "0111110011" => manhi <= conv_std_logic_vector(14635065,24); manlo <= conv_std_logic_vector(183612561,28); exponent <= conv_std_logic_vector(1742,11); WHEN "0111110100" => manhi <= conv_std_logic_vector(4569642,24); manlo <= conv_std_logic_vector(167240760,28); exponent <= conv_std_logic_vector(1744,11); WHEN "0111110101" => manhi <= conv_std_logic_vector(12236172,24); manlo <= conv_std_logic_vector(253623266,28); exponent <= conv_std_logic_vector(1745,11); WHEN "0111110110" => manhi <= conv_std_logic_vector(2939425,24); manlo <= conv_std_logic_vector(265128301,28); exponent <= conv_std_logic_vector(1747,11); WHEN "0111110111" => manhi <= conv_std_logic_vector(10020478,24); manlo <= conv_std_logic_vector(219223569,28); exponent <= conv_std_logic_vector(1748,11); WHEN "0111111000" => manhi <= conv_std_logic_vector(1433705,24); manlo <= conv_std_logic_vector(192250058,28); exponent <= conv_std_logic_vector(1750,11); WHEN "0111111001" => manhi <= conv_std_logic_vector(7973992,24); manlo <= conv_std_logic_vector(212144821,28); exponent <= conv_std_logic_vector(1751,11); WHEN "0111111010" => manhi <= conv_std_logic_vector(42974,24); manlo <= conv_std_logic_vector(72952107,28); exponent <= conv_std_logic_vector(1753,11); WHEN "0111111011" => manhi <= conv_std_logic_vector(6083792,24); manlo <= conv_std_logic_vector(210315148,28); exponent <= conv_std_logic_vector(1754,11); WHEN "0111111100" => manhi <= conv_std_logic_vector(14294116,24); manlo <= conv_std_logic_vector(101520926,28); exponent <= conv_std_logic_vector(1755,11); WHEN "0111111101" => manhi <= conv_std_logic_vector(4337943,24); manlo <= conv_std_logic_vector(146945490,28); exponent <= conv_std_logic_vector(1757,11); WHEN "0111111110" => manhi <= conv_std_logic_vector(11921261,24); manlo <= conv_std_logic_vector(67478049,28); exponent <= conv_std_logic_vector(1758,11); WHEN "0111111111" => manhi <= conv_std_logic_vector(2725421,24); manlo <= conv_std_logic_vector(81662013,28); exponent <= conv_std_logic_vector(1760,11); WHEN "1000000000" => manhi <= conv_std_logic_vector(9729616,24); manlo <= conv_std_logic_vector(79332654,28); exponent <= conv_std_logic_vector(1761,11); WHEN "1000000001" => manhi <= conv_std_logic_vector(1236044,24); manlo <= conv_std_logic_vector(37511845,28); exponent <= conv_std_logic_vector(1763,11); WHEN "1000000010" => manhi <= conv_std_logic_vector(7705342,24); manlo <= conv_std_logic_vector(229400607,28); exponent <= conv_std_logic_vector(1764,11); WHEN "1000000011" => manhi <= conv_std_logic_vector(16498031,24); manlo <= conv_std_logic_vector(113896411,28); exponent <= conv_std_logic_vector(1765,11); WHEN "1000000100" => manhi <= conv_std_logic_vector(5835659,24); manlo <= conv_std_logic_vector(27578100,28); exponent <= conv_std_logic_vector(1767,11); WHEN "1000000101" => manhi <= conv_std_logic_vector(13956867,24); manlo <= conv_std_logic_vector(198774093,28); exponent <= conv_std_logic_vector(1768,11); WHEN "1000000110" => manhi <= conv_std_logic_vector(4108759,24); manlo <= conv_std_logic_vector(90336304,28); exponent <= conv_std_logic_vector(1770,11); WHEN "1000000111" => manhi <= conv_std_logic_vector(11609767,24); manlo <= conv_std_logic_vector(164675818,28); exponent <= conv_std_logic_vector(1771,11); WHEN "1000001000" => manhi <= conv_std_logic_vector(2513739,24); manlo <= conv_std_logic_vector(115510945,28); exponent <= conv_std_logic_vector(1773,11); WHEN "1000001001" => manhi <= conv_std_logic_vector(9441910,24); manlo <= conv_std_logic_vector(214725537,28); exponent <= conv_std_logic_vector(1774,11); WHEN "1000001010" => manhi <= conv_std_logic_vector(1040527,24); manlo <= conv_std_logic_vector(264292986,28); exponent <= conv_std_logic_vector(1776,11); WHEN "1000001011" => manhi <= conv_std_logic_vector(7439608,24); manlo <= conv_std_logic_vector(227819416,28); exponent <= conv_std_logic_vector(1777,11); WHEN "1000001100" => manhi <= conv_std_logic_vector(16136861,24); manlo <= conv_std_logic_vector(124712281,28); exponent <= conv_std_logic_vector(1778,11); WHEN "1000001101" => manhi <= conv_std_logic_vector(5590218,24); manlo <= conv_std_logic_vector(179347558,28); exponent <= conv_std_logic_vector(1780,11); WHEN "1000001110" => manhi <= conv_std_logic_vector(13623279,24); manlo <= conv_std_logic_vector(162081347,28); exponent <= conv_std_logic_vector(1781,11); WHEN "1000001111" => manhi <= conv_std_logic_vector(3882062,24); manlo <= conv_std_logic_vector(186291443,28); exponent <= conv_std_logic_vector(1783,11); WHEN "1000010000" => manhi <= conv_std_logic_vector(11301654,24); manlo <= conv_std_logic_vector(250040022,28); exponent <= conv_std_logic_vector(1784,11); WHEN "1000010001" => manhi <= conv_std_logic_vector(2304355,24); manlo <= conv_std_logic_vector(41383777,28); exponent <= conv_std_logic_vector(1786,11); WHEN "1000010010" => manhi <= conv_std_logic_vector(9157328,24); manlo <= conv_std_logic_vector(17021400,28); exponent <= conv_std_logic_vector(1787,11); WHEN "1000010011" => manhi <= conv_std_logic_vector(847133,24); manlo <= conv_std_logic_vector(258834653,28); exponent <= conv_std_logic_vector(1789,11); WHEN "1000010100" => manhi <= conv_std_logic_vector(7176759,24); manlo <= conv_std_logic_vector(33041815,28); exponent <= conv_std_logic_vector(1790,11); WHEN "1000010101" => manhi <= conv_std_logic_vector(15779611,24); manlo <= conv_std_logic_vector(174007449,28); exponent <= conv_std_logic_vector(1791,11); WHEN "1000010110" => manhi <= conv_std_logic_vector(5347442,24); manlo <= conv_std_logic_vector(66333886,28); exponent <= conv_std_logic_vector(1793,11); WHEN "1000010111" => manhi <= conv_std_logic_vector(13293312,24); manlo <= conv_std_logic_vector(63618366,28); exponent <= conv_std_logic_vector(1794,11); WHEN "1000011000" => manhi <= conv_std_logic_vector(3657826,24); manlo <= conv_std_logic_vector(166348998,28); exponent <= conv_std_logic_vector(1796,11); WHEN "1000011001" => manhi <= conv_std_logic_vector(10996886,24); manlo <= conv_std_logic_vector(136487624,28); exponent <= conv_std_logic_vector(1797,11); WHEN "1000011010" => manhi <= conv_std_logic_vector(2097243,24); manlo <= conv_std_logic_vector(144317262,28); exponent <= conv_std_logic_vector(1799,11); WHEN "1000011011" => manhi <= conv_std_logic_vector(8875834,24); manlo <= conv_std_logic_vector(51419886,28); exponent <= conv_std_logic_vector(1800,11); WHEN "1000011100" => manhi <= conv_std_logic_vector(655839,24); manlo <= conv_std_logic_vector(12096311,28); exponent <= conv_std_logic_vector(1802,11); WHEN "1000011101" => manhi <= conv_std_logic_vector(6916762,24); manlo <= conv_std_logic_vector(99793437,28); exponent <= conv_std_logic_vector(1803,11); WHEN "1000011110" => manhi <= conv_std_logic_vector(15426239,24); manlo <= conv_std_logic_vector(114334116,28); exponent <= conv_std_logic_vector(1804,11); WHEN "1000011111" => manhi <= conv_std_logic_vector(5107300,24); manlo <= conv_std_logic_vector(248161218,28); exponent <= conv_std_logic_vector(1806,11); WHEN "1000100000" => manhi <= conv_std_logic_vector(12966926,24); manlo <= conv_std_logic_vector(91321506,28); exponent <= conv_std_logic_vector(1807,11); WHEN "1000100001" => manhi <= conv_std_logic_vector(3436024,24); manlo <= conv_std_logic_vector(109150055,28); exponent <= conv_std_logic_vector(1809,11); WHEN "1000100010" => manhi <= conv_std_logic_vector(10695426,24); manlo <= conv_std_logic_vector(12291314,28); exponent <= conv_std_logic_vector(1810,11); WHEN "1000100011" => manhi <= conv_std_logic_vector(1892379,24); manlo <= conv_std_logic_vector(245137096,28); exponent <= conv_std_logic_vector(1812,11); WHEN "1000100100" => manhi <= conv_std_logic_vector(8597395,24); manlo <= conv_std_logic_vector(176569250,28); exponent <= conv_std_logic_vector(1813,11); WHEN "1000100101" => manhi <= conv_std_logic_vector(466620,24); manlo <= conv_std_logic_vector(119019308,28); exponent <= conv_std_logic_vector(1815,11); WHEN "1000100110" => manhi <= conv_std_logic_vector(6659587,24); manlo <= conv_std_logic_vector(168706814,28); exponent <= conv_std_logic_vector(1816,11); WHEN "1000100111" => manhi <= conv_std_logic_vector(15076702,24); manlo <= conv_std_logic_vector(190651618,28); exponent <= conv_std_logic_vector(1817,11); WHEN "1000101000" => manhi <= conv_std_logic_vector(4869766,24); manlo <= conv_std_logic_vector(26523901,28); exponent <= conv_std_logic_vector(1819,11); WHEN "1000101001" => manhi <= conv_std_logic_vector(12644083,24); manlo <= conv_std_logic_vector(10760420,28); exponent <= conv_std_logic_vector(1820,11); WHEN "1000101010" => manhi <= conv_std_logic_vector(3216629,24); manlo <= conv_std_logic_vector(171149379,28); exponent <= conv_std_logic_vector(1822,11); WHEN "1000101011" => manhi <= conv_std_logic_vector(10397237,24); manlo <= conv_std_logic_vector(171483537,28); exponent <= conv_std_logic_vector(1823,11); WHEN "1000101100" => manhi <= conv_std_logic_vector(1689739,24); manlo <= conv_std_logic_vector(236540182,28); exponent <= conv_std_logic_vector(1825,11); WHEN "1000101101" => manhi <= conv_std_logic_vector(8321979,24); manlo <= conv_std_logic_vector(80365386,28); exponent <= conv_std_logic_vector(1826,11); WHEN "1000101110" => manhi <= conv_std_logic_vector(279455,24); manlo <= conv_std_logic_vector(167185714,28); exponent <= conv_std_logic_vector(1828,11); WHEN "1000101111" => manhi <= conv_std_logic_vector(6405204,24); manlo <= conv_std_logic_vector(70637708,28); exponent <= conv_std_logic_vector(1829,11); WHEN "1000110000" => manhi <= conv_std_logic_vector(14730959,24); manlo <= conv_std_logic_vector(233674466,28); exponent <= conv_std_logic_vector(1830,11); WHEN "1000110001" => manhi <= conv_std_logic_vector(4634809,24); manlo <= conv_std_logic_vector(128626627,28); exponent <= conv_std_logic_vector(1832,11); WHEN "1000110010" => manhi <= conv_std_logic_vector(12324743,24); manlo <= conv_std_logic_vector(237637056,28); exponent <= conv_std_logic_vector(1833,11); WHEN "1000110011" => manhi <= conv_std_logic_vector(2999616,24); manlo <= conv_std_logic_vector(48899908,28); exponent <= conv_std_logic_vector(1835,11); WHEN "1000110100" => manhi <= conv_std_logic_vector(10102285,24); manlo <= conv_std_logic_vector(207402206,28); exponent <= conv_std_logic_vector(1836,11); WHEN "1000110101" => manhi <= conv_std_logic_vector(1489299,24); manlo <= conv_std_logic_vector(82314533,28); exponent <= conv_std_logic_vector(1838,11); WHEN "1000110110" => manhi <= conv_std_logic_vector(8049552,24); manlo <= conv_std_logic_vector(84197942,28); exponent <= conv_std_logic_vector(1839,11); WHEN "1000110111" => manhi <= conv_std_logic_vector(94322,24); manlo <= conv_std_logic_vector(78275083,28); exponent <= conv_std_logic_vector(1841,11); WHEN "1000111000" => manhi <= conv_std_logic_vector(6153581,24); manlo <= conv_std_logic_vector(262556746,28); exponent <= conv_std_logic_vector(1842,11); WHEN "1000111001" => manhi <= conv_std_logic_vector(14388969,24); manlo <= conv_std_logic_vector(195412276,28); exponent <= conv_std_logic_vector(1843,11); WHEN "1000111010" => manhi <= conv_std_logic_vector(4402403,24); manlo <= conv_std_logic_vector(21925377,28); exponent <= conv_std_logic_vector(1845,11); WHEN "1000111011" => manhi <= conv_std_logic_vector(12008870,24); manlo <= conv_std_logic_vector(225943576,28); exponent <= conv_std_logic_vector(1846,11); WHEN "1000111100" => manhi <= conv_std_logic_vector(2784958,24); manlo <= conv_std_logic_vector(51959162,28); exponent <= conv_std_logic_vector(1848,11); WHEN "1000111101" => manhi <= conv_std_logic_vector(9810535,24); manlo <= conv_std_logic_vector(85297068,28); exponent <= conv_std_logic_vector(1849,11); WHEN "1000111110" => manhi <= conv_std_logic_vector(1291034,24); manlo <= conv_std_logic_vector(85003113,28); exponent <= conv_std_logic_vector(1851,11); WHEN "1000111111" => manhi <= conv_std_logic_vector(7780082,24); manlo <= conv_std_logic_vector(68159752,28); exponent <= conv_std_logic_vector(1852,11); WHEN "1001000000" => manhi <= conv_std_logic_vector(16599612,24); manlo <= conv_std_logic_vector(214703512,28); exponent <= conv_std_logic_vector(1853,11); WHEN "1001000001" => manhi <= conv_std_logic_vector(5904690,24); manlo <= conv_std_logic_vector(215968023,28); exponent <= conv_std_logic_vector(1855,11); WHEN "1001000010" => manhi <= conv_std_logic_vector(14050691,24); manlo <= conv_std_logic_vector(147853227,28); exponent <= conv_std_logic_vector(1856,11); WHEN "1001000011" => manhi <= conv_std_logic_vector(4172519,24); manlo <= conv_std_logic_vector(60716388,28); exponent <= conv_std_logic_vector(1858,11); WHEN "1001000100" => manhi <= conv_std_logic_vector(11696426,24); manlo <= conv_std_logic_vector(77359100,28); exponent <= conv_std_logic_vector(1859,11); WHEN "1001000101" => manhi <= conv_std_logic_vector(2572630,24); manlo <= conv_std_logic_vector(28321055,28); exponent <= conv_std_logic_vector(1861,11); WHEN "1001000110" => manhi <= conv_std_logic_vector(9521951,24); manlo <= conv_std_logic_vector(141206574,28); exponent <= conv_std_logic_vector(1862,11); WHEN "1001000111" => manhi <= conv_std_logic_vector(1094921,24); manlo <= conv_std_logic_vector(79834212,28); exponent <= conv_std_logic_vector(1864,11); WHEN "1001001000" => manhi <= conv_std_logic_vector(7513537,24); manlo <= conv_std_logic_vector(6880382,28); exponent <= conv_std_logic_vector(1865,11); WHEN "1001001001" => manhi <= conv_std_logic_vector(16237340,24); manlo <= conv_std_logic_vector(73707069,28); exponent <= conv_std_logic_vector(1866,11); WHEN "1001001010" => manhi <= conv_std_logic_vector(5658501,24); manlo <= conv_std_logic_vector(26563701,28); exponent <= conv_std_logic_vector(1868,11); WHEN "1001001011" => manhi <= conv_std_logic_vector(13716085,24); manlo <= conv_std_logic_vector(13226359,28); exponent <= conv_std_logic_vector(1869,11); WHEN "1001001100" => manhi <= conv_std_logic_vector(3945130,24); manlo <= conv_std_logic_vector(143073903,28); exponent <= conv_std_logic_vector(1871,11); WHEN "1001001101" => manhi <= conv_std_logic_vector(11387373,24); manlo <= conv_std_logic_vector(3175990,28); exponent <= conv_std_logic_vector(1872,11); WHEN "1001001110" => manhi <= conv_std_logic_vector(2362606,24); manlo <= conv_std_logic_vector(168904878,28); exponent <= conv_std_logic_vector(1874,11); WHEN "1001001111" => manhi <= conv_std_logic_vector(9236500,24); manlo <= conv_std_logic_vector(7105104,28); exponent <= conv_std_logic_vector(1875,11); WHEN "1001010000" => manhi <= conv_std_logic_vector(900936,24); manlo <= conv_std_logic_vector(239272854,28); exponent <= conv_std_logic_vector(1877,11); WHEN "1001010001" => manhi <= conv_std_logic_vector(7249884,24); manlo <= conv_std_logic_vector(236935482,28); exponent <= conv_std_logic_vector(1878,11); WHEN "1001010010" => manhi <= conv_std_logic_vector(15878999,24); manlo <= conv_std_logic_vector(230836932,28); exponent <= conv_std_logic_vector(1879,11); WHEN "1001010011" => manhi <= conv_std_logic_vector(5414983,24); manlo <= conv_std_logic_vector(144840810,28); exponent <= conv_std_logic_vector(1881,11); WHEN "1001010100" => manhi <= conv_std_logic_vector(13385110,24); manlo <= conv_std_logic_vector(99584369,28); exponent <= conv_std_logic_vector(1882,11); WHEN "1001010101" => manhi <= conv_std_logic_vector(3720209,24); manlo <= conv_std_logic_vector(246845719,28); exponent <= conv_std_logic_vector(1884,11); WHEN "1001010110" => manhi <= conv_std_logic_vector(11081674,24); manlo <= conv_std_logic_vector(54674652,28); exponent <= conv_std_logic_vector(1885,11); WHEN "1001010111" => manhi <= conv_std_logic_vector(2154862,24); manlo <= conv_std_logic_vector(201440422,28); exponent <= conv_std_logic_vector(1887,11); WHEN "1001011000" => manhi <= conv_std_logic_vector(8954146,24); manlo <= conv_std_logic_vector(220416825,28); exponent <= conv_std_logic_vector(1888,11); WHEN "1001011001" => manhi <= conv_std_logic_vector(709057,24); manlo <= conv_std_logic_vector(266967657,28); exponent <= conv_std_logic_vector(1890,11); WHEN "1001011010" => manhi <= conv_std_logic_vector(6989094,24); manlo <= conv_std_logic_vector(113654547,28); exponent <= conv_std_logic_vector(1891,11); WHEN "1001011011" => manhi <= conv_std_logic_vector(15524548,24); manlo <= conv_std_logic_vector(235342013,28); exponent <= conv_std_logic_vector(1892,11); WHEN "1001011100" => manhi <= conv_std_logic_vector(5174109,24); manlo <= conv_std_logic_vector(32986511,28); exponent <= conv_std_logic_vector(1894,11); WHEN "1001011101" => manhi <= conv_std_logic_vector(13057728,24); manlo <= conv_std_logic_vector(25787653,28); exponent <= conv_std_logic_vector(1895,11); WHEN "1001011110" => manhi <= conv_std_logic_vector(3497730,24); manlo <= conv_std_logic_vector(160351868,28); exponent <= conv_std_logic_vector(1897,11); WHEN "1001011111" => manhi <= conv_std_logic_vector(10779293,24); manlo <= conv_std_logic_vector(121946709,28); exponent <= conv_std_logic_vector(1898,11); WHEN "1001100000" => manhi <= conv_std_logic_vector(1949373,24); manlo <= conv_std_logic_vector(194974600,28); exponent <= conv_std_logic_vector(1900,11); WHEN "1001100001" => manhi <= conv_std_logic_vector(8674858,24); manlo <= conv_std_logic_vector(75445083,28); exponent <= conv_std_logic_vector(1901,11); WHEN "1001100010" => manhi <= conv_std_logic_vector(519261,24); manlo <= conv_std_logic_vector(202318540,28); exponent <= conv_std_logic_vector(1903,11); WHEN "1001100011" => manhi <= conv_std_logic_vector(6731134,24); manlo <= conv_std_logic_vector(157600610,28); exponent <= conv_std_logic_vector(1904,11); WHEN "1001100100" => manhi <= conv_std_logic_vector(15173945,24); manlo <= conv_std_logic_vector(29256816,28); exponent <= conv_std_logic_vector(1905,11); WHEN "1001100101" => manhi <= conv_std_logic_vector(4935849,24); manlo <= conv_std_logic_vector(42999013,28); exponent <= conv_std_logic_vector(1907,11); WHEN "1001100110" => manhi <= conv_std_logic_vector(12733899,24); manlo <= conv_std_logic_vector(62421287,28); exponent <= conv_std_logic_vector(1908,11); WHEN "1001100111" => manhi <= conv_std_logic_vector(3277666,24); manlo <= conv_std_logic_vector(18399062,28); exponent <= conv_std_logic_vector(1910,11); WHEN "1001101000" => manhi <= conv_std_logic_vector(10480194,24); manlo <= conv_std_logic_vector(201166396,28); exponent <= conv_std_logic_vector(1911,11); WHEN "1001101001" => manhi <= conv_std_logic_vector(1746115,24); manlo <= conv_std_logic_vector(22209480,28); exponent <= conv_std_logic_vector(1913,11); WHEN "1001101010" => manhi <= conv_std_logic_vector(8398601,24); manlo <= conv_std_logic_vector(38216343,28); exponent <= conv_std_logic_vector(1914,11); WHEN "1001101011" => manhi <= conv_std_logic_vector(331525,24); manlo <= conv_std_logic_vector(151310615,28); exponent <= conv_std_logic_vector(1916,11); WHEN "1001101100" => manhi <= conv_std_logic_vector(6475974,24); manlo <= conv_std_logic_vector(174528998,28); exponent <= conv_std_logic_vector(1917,11); WHEN "1001101101" => manhi <= conv_std_logic_vector(14827146,24); manlo <= conv_std_logic_vector(214487191,28); exponent <= conv_std_logic_vector(1918,11); WHEN "1001101110" => manhi <= conv_std_logic_vector(4700175,24); manlo <= conv_std_logic_vector(73593076,28); exponent <= conv_std_logic_vector(1920,11); WHEN "1001101111" => manhi <= conv_std_logic_vector(12413585,24); manlo <= conv_std_logic_vector(56806573,28); exponent <= conv_std_logic_vector(1921,11); WHEN "1001110000" => manhi <= conv_std_logic_vector(3059990,24); manlo <= conv_std_logic_vector(32998071,28); exponent <= conv_std_logic_vector(1923,11); WHEN "1001110001" => manhi <= conv_std_logic_vector(10184342,24); manlo <= conv_std_logic_vector(125003687,28); exponent <= conv_std_logic_vector(1924,11); WHEN "1001110010" => manhi <= conv_std_logic_vector(1545062,24); manlo <= conv_std_logic_vector(164026180,28); exponent <= conv_std_logic_vector(1926,11); WHEN "1001110011" => manhi <= conv_std_logic_vector(8125342,24); manlo <= conv_std_logic_vector(134803968,28); exponent <= conv_std_logic_vector(1927,11); WHEN "1001110100" => manhi <= conv_std_logic_vector(145827,24); manlo <= conv_std_logic_vector(17356019,28); exponent <= conv_std_logic_vector(1929,11); WHEN "1001110101" => manhi <= conv_std_logic_vector(6223584,24); manlo <= conv_std_logic_vector(59711433,28); exponent <= conv_std_logic_vector(1930,11); WHEN "1001110110" => manhi <= conv_std_logic_vector(14484112,24); manlo <= conv_std_logic_vector(172427100,28); exponent <= conv_std_logic_vector(1931,11); WHEN "1001110111" => manhi <= conv_std_logic_vector(4467059,24); manlo <= conv_std_logic_vector(106163660,28); exponent <= conv_std_logic_vector(1933,11); WHEN "1001111000" => manhi <= conv_std_logic_vector(12096747,24); manlo <= conv_std_logic_vector(237074316,28); exponent <= conv_std_logic_vector(1934,11); WHEN "1001111001" => manhi <= conv_std_logic_vector(2844676,24); manlo <= conv_std_logic_vector(224090291,28); exponent <= conv_std_logic_vector(1936,11); WHEN "1001111010" => manhi <= conv_std_logic_vector(9891701,24); manlo <= conv_std_logic_vector(98356275,28); exponent <= conv_std_logic_vector(1937,11); WHEN "1001111011" => manhi <= conv_std_logic_vector(1346192,24); manlo <= conv_std_logic_vector(98098154,28); exponent <= conv_std_logic_vector(1939,11); WHEN "1001111100" => manhi <= conv_std_logic_vector(7855049,24); manlo <= conv_std_logic_vector(218711727,28); exponent <= conv_std_logic_vector(1940,11); WHEN "1001111101" => manhi <= conv_std_logic_vector(16701504,24); manlo <= conv_std_logic_vector(74899902,28); exponent <= conv_std_logic_vector(1941,11); WHEN "1001111110" => manhi <= conv_std_logic_vector(5973933,24); manlo <= conv_std_logic_vector(65399866,28); exponent <= conv_std_logic_vector(1943,11); WHEN "1001111111" => manhi <= conv_std_logic_vector(14144801,24); manlo <= conv_std_logic_vector(210121699,28); exponent <= conv_std_logic_vector(1944,11); WHEN "1010000000" => manhi <= conv_std_logic_vector(4236473,24); manlo <= conv_std_logic_vector(203888522,28); exponent <= conv_std_logic_vector(1946,11); WHEN "1010000001" => manhi <= conv_std_logic_vector(11783349,24); manlo <= conv_std_logic_vector(137203293,28); exponent <= conv_std_logic_vector(1947,11); WHEN "1010000010" => manhi <= conv_std_logic_vector(2631700,24); manlo <= conv_std_logic_vector(150283410,28); exponent <= conv_std_logic_vector(1949,11); WHEN "1010000011" => manhi <= conv_std_logic_vector(9602236,24); manlo <= conv_std_logic_vector(160352104,28); exponent <= conv_std_logic_vector(1950,11); WHEN "1010000100" => manhi <= conv_std_logic_vector(1149480,24); manlo <= conv_std_logic_vector(177173803,28); exponent <= conv_std_logic_vector(1952,11); WHEN "1010000101" => manhi <= conv_std_logic_vector(7587690,24); manlo <= conv_std_logic_vector(238268718,28); exponent <= conv_std_logic_vector(1953,11); WHEN "1010000110" => manhi <= conv_std_logic_vector(16338125,24); manlo <= conv_std_logic_vector(220749839,28); exponent <= conv_std_logic_vector(1954,11); WHEN "1010000111" => manhi <= conv_std_logic_vector(5726991,24); manlo <= conv_std_logic_vector(262994505,28); exponent <= conv_std_logic_vector(1956,11); WHEN "1010001000" => manhi <= conv_std_logic_vector(13809173,24); manlo <= conv_std_logic_vector(216783842,28); exponent <= conv_std_logic_vector(1957,11); WHEN "1010001001" => manhi <= conv_std_logic_vector(4008390,24); manlo <= conv_std_logic_vector(242405077,28); exponent <= conv_std_logic_vector(1959,11); WHEN "1010001010" => manhi <= conv_std_logic_vector(11473352,24); manlo <= conv_std_logic_vector(206426515,28); exponent <= conv_std_logic_vector(1960,11); WHEN "1010001011" => manhi <= conv_std_logic_vector(2421035,24); manlo <= conv_std_logic_vector(250208807,28); exponent <= conv_std_logic_vector(1962,11); WHEN "1010001100" => manhi <= conv_std_logic_vector(9315913,24); manlo <= conv_std_logic_vector(183235034,28); exponent <= conv_std_logic_vector(1963,11); WHEN "1010001101" => manhi <= conv_std_logic_vector(954904,24); manlo <= conv_std_logic_vector(17706469,28); exponent <= conv_std_logic_vector(1965,11); WHEN "1010001110" => manhi <= conv_std_logic_vector(7323233,24); manlo <= conv_std_logic_vector(235600136,28); exponent <= conv_std_logic_vector(1966,11); WHEN "1010001111" => manhi <= conv_std_logic_vector(15978691,24); manlo <= conv_std_logic_vector(128873524,28); exponent <= conv_std_logic_vector(1967,11); WHEN "1010010000" => manhi <= conv_std_logic_vector(5482731,24); manlo <= conv_std_logic_vector(5222268,28); exponent <= conv_std_logic_vector(1969,11); WHEN "1010010001" => manhi <= conv_std_logic_vector(13477188,24); manlo <= conv_std_logic_vector(199372940,28); exponent <= conv_std_logic_vector(1970,11); WHEN "1010010010" => manhi <= conv_std_logic_vector(3782783,24); manlo <= conv_std_logic_vector(177367827,28); exponent <= conv_std_logic_vector(1972,11); WHEN "1010010011" => manhi <= conv_std_logic_vector(11166720,24); manlo <= conv_std_logic_vector(197425116,28); exponent <= conv_std_logic_vector(1973,11); WHEN "1010010100" => manhi <= conv_std_logic_vector(2212657,24); manlo <= conv_std_logic_vector(231097832,28); exponent <= conv_std_logic_vector(1975,11); WHEN "1010010101" => manhi <= conv_std_logic_vector(9032698,24); manlo <= conv_std_logic_vector(139698050,28); exponent <= conv_std_logic_vector(1976,11); WHEN "1010010110" => manhi <= conv_std_logic_vector(762439,24); manlo <= conv_std_logic_vector(109718127,28); exponent <= conv_std_logic_vector(1978,11); WHEN "1010010111" => manhi <= conv_std_logic_vector(7061647,24); manlo <= conv_std_logic_vector(77173752,28); exponent <= conv_std_logic_vector(1979,11); WHEN "1010011000" => manhi <= conv_std_logic_vector(15623158,24); manlo <= conv_std_logic_vector(118851961,28); exponent <= conv_std_logic_vector(1980,11); WHEN "1010011001" => manhi <= conv_std_logic_vector(5241121,24); manlo <= conv_std_logic_vector(72680114,28); exponent <= conv_std_logic_vector(1982,11); WHEN "1010011010" => manhi <= conv_std_logic_vector(13148807,24); manlo <= conv_std_logic_vector(12881486,28); exponent <= conv_std_logic_vector(1983,11); WHEN "1010011011" => manhi <= conv_std_logic_vector(3559625,24); manlo <= conv_std_logic_vector(43579850,28); exponent <= conv_std_logic_vector(1985,11); WHEN "1010011100" => manhi <= conv_std_logic_vector(10863416,24); manlo <= conv_std_logic_vector(238889758,28); exponent <= conv_std_logic_vector(1986,11); WHEN "1010011101" => manhi <= conv_std_logic_vector(2006541,24); manlo <= conv_std_logic_vector(141721451,28); exponent <= conv_std_logic_vector(1988,11); WHEN "1010011110" => manhi <= conv_std_logic_vector(8752557,24); manlo <= conv_std_logic_vector(101792997,28); exponent <= conv_std_logic_vector(1989,11); WHEN "1010011111" => manhi <= conv_std_logic_vector(572063,24); manlo <= conv_std_logic_vector(205445723,28); exponent <= conv_std_logic_vector(1991,11); WHEN "1010100000" => manhi <= conv_std_logic_vector(6802899,24); manlo <= conv_std_logic_vector(258099270,28); exponent <= conv_std_logic_vector(1992,11); WHEN "1010100001" => manhi <= conv_std_logic_vector(15271484,24); manlo <= conv_std_logic_vector(98124990,28); exponent <= conv_std_logic_vector(1993,11); WHEN "1010100010" => manhi <= conv_std_logic_vector(5002133,24); manlo <= conv_std_logic_vector(256985826,28); exponent <= conv_std_logic_vector(1995,11); WHEN "1010100011" => manhi <= conv_std_logic_vector(12823989,24); manlo <= conv_std_logic_vector(164377270,28); exponent <= conv_std_logic_vector(1996,11); WHEN "1010100100" => manhi <= conv_std_logic_vector(3338888,24); manlo <= conv_std_logic_vector(222569178,28); exponent <= conv_std_logic_vector(1998,11); WHEN "1010100101" => manhi <= conv_std_logic_vector(10563405,24); manlo <= conv_std_logic_vector(29046646,28); exponent <= conv_std_logic_vector(1999,11); WHEN "1010100110" => manhi <= conv_std_logic_vector(1802662,24); manlo <= conv_std_logic_vector(103161316,28); exponent <= conv_std_logic_vector(2001,11); WHEN "1010100111" => manhi <= conv_std_logic_vector(8475456,24); manlo <= conv_std_logic_vector(239852126,28); exponent <= conv_std_logic_vector(2002,11); WHEN "1010101000" => manhi <= conv_std_logic_vector(383754,24); manlo <= conv_std_logic_vector(123914668,28); exponent <= conv_std_logic_vector(2004,11); WHEN "1010101001" => manhi <= conv_std_logic_vector(6546961,24); manlo <= conv_std_logic_vector(22084044,28); exponent <= conv_std_logic_vector(2005,11); WHEN "1010101010" => manhi <= conv_std_logic_vector(14923627,24); manlo <= conv_std_logic_vector(97508377,28); exponent <= conv_std_logic_vector(2006,11); WHEN "1010101011" => manhi <= conv_std_logic_vector(4765740,24); manlo <= conv_std_logic_vector(165164368,28); exponent <= conv_std_logic_vector(2008,11); WHEN "1010101100" => manhi <= conv_std_logic_vector(12502697,24); manlo <= conv_std_logic_vector(201140216,28); exponent <= conv_std_logic_vector(2009,11); WHEN "1010101101" => manhi <= conv_std_logic_vector(3120548,24); manlo <= conv_std_logic_vector(99561759,28); exponent <= conv_std_logic_vector(2011,11); WHEN "1010101110" => manhi <= conv_std_logic_vector(10266649,24); manlo <= conv_std_logic_vector(176679877,28); exponent <= conv_std_logic_vector(2012,11); WHEN "1010101111" => manhi <= conv_std_logic_vector(1600996,24); manlo <= conv_std_logic_vector(39589446,28); exponent <= conv_std_logic_vector(2014,11); WHEN "1010110000" => manhi <= conv_std_logic_vector(8201364,24); manlo <= conv_std_logic_vector(16114999,28); exponent <= conv_std_logic_vector(2015,11); WHEN "1010110001" => manhi <= conv_std_logic_vector(197489,24); manlo <= conv_std_logic_vector(18649371,28); exponent <= conv_std_logic_vector(2017,11); WHEN "1010110010" => manhi <= conv_std_logic_vector(6293800,24); manlo <= conv_std_logic_vector(44802372,28); exponent <= conv_std_logic_vector(2018,11); WHEN "1010110011" => manhi <= conv_std_logic_vector(14579546,24); manlo <= conv_std_logic_vector(1419236,28); exponent <= conv_std_logic_vector(2019,11); WHEN "1010110100" => manhi <= conv_std_logic_vector(4531913,24); manlo <= conv_std_logic_vector(24044223,28); exponent <= conv_std_logic_vector(2021,11); WHEN "1010110101" => manhi <= conv_std_logic_vector(12184893,24); manlo <= conv_std_logic_vector(51602800,28); exponent <= conv_std_logic_vector(2022,11); WHEN "1010110110" => manhi <= conv_std_logic_vector(2904577,24); manlo <= conv_std_logic_vector(210124577,28); exponent <= conv_std_logic_vector(2024,11); WHEN "1010110111" => manhi <= conv_std_logic_vector(9973115,24); manlo <= conv_std_logic_vector(52505388,28); exponent <= conv_std_logic_vector(2025,11); WHEN "1010111000" => manhi <= conv_std_logic_vector(1401518,24); manlo <= conv_std_logic_vector(214362802,28); exponent <= conv_std_logic_vector(2027,11); WHEN "1010111001" => manhi <= conv_std_logic_vector(7930246,24); manlo <= conv_std_logic_vector(62721516,28); exponent <= conv_std_logic_vector(2028,11); WHEN "1010111010" => manhi <= conv_std_logic_vector(13245,24); manlo <= conv_std_logic_vector(108520727,28); exponent <= conv_std_logic_vector(2030,11); WHEN "1010111011" => manhi <= conv_std_logic_vector(6043387,24); manlo <= conv_std_logic_vector(17001813,28); exponent <= conv_std_logic_vector(2031,11); WHEN "1010111100" => manhi <= conv_std_logic_vector(14239199,24); manlo <= conv_std_logic_vector(83422350,28); exponent <= conv_std_logic_vector(2032,11); WHEN "1010111101" => manhi <= conv_std_logic_vector(4300623,24); manlo <= conv_std_logic_vector(142486326,28); exponent <= conv_std_logic_vector(2034,11); WHEN "1010111110" => manhi <= conv_std_logic_vector(11870538,24); manlo <= conv_std_logic_vector(24126621,28); exponent <= conv_std_logic_vector(2035,11); WHEN "1010111111" => manhi <= conv_std_logic_vector(2690951,24); manlo <= conv_std_logic_vector(91850592,28); exponent <= conv_std_logic_vector(2037,11); WHEN "1011000000" => manhi <= conv_std_logic_vector(9682766,24); manlo <= conv_std_logic_vector(203960059,28); exponent <= conv_std_logic_vector(2038,11); WHEN "1011000001" => manhi <= conv_std_logic_vector(1204206,24); manlo <= conv_std_logic_vector(155513539,28); exponent <= conv_std_logic_vector(2040,11); WHEN "1011000010" => manhi <= conv_std_logic_vector(7662071,24); manlo <= conv_std_logic_vector(33184566,28); exponent <= conv_std_logic_vector(2041,11); WHEN "1011000011" => manhi <= conv_std_logic_vector(16439219,24); manlo <= conv_std_logic_vector(11896414,28); exponent <= conv_std_logic_vector(2042,11); WHEN "1011000100" => manhi <= conv_std_logic_vector(5795691,24); manlo <= conv_std_logic_vector(254151921,28); exponent <= conv_std_logic_vector(2044,11); WHEN "1011000101" => manhi <= conv_std_logic_vector(13902546,24); manlo <= conv_std_logic_vector(199613595,28); exponent <= conv_std_logic_vector(2045,11); WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_explutpos IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_explutpos; ARCHITECTURE rtl OF dp_explutpos IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(1023,11); WHEN "0000000001" => manhi <= conv_std_logic_vector(6025384,24); manlo <= conv_std_logic_vector(185882474,28); exponent <= conv_std_logic_vector(1024,11); WHEN "0000000010" => manhi <= conv_std_logic_vector(14214731,24); manlo <= conv_std_logic_vector(148168110,28); exponent <= conv_std_logic_vector(1025,11); WHEN "0000000011" => manhi <= conv_std_logic_vector(4283995,24); manlo <= conv_std_logic_vector(258978054,28); exponent <= conv_std_logic_vector(1027,11); WHEN "0000000100" => manhi <= conv_std_logic_vector(11847938,24); manlo <= conv_std_logic_vector(237451864,28); exponent <= conv_std_logic_vector(1028,11); WHEN "0000000101" => manhi <= conv_std_logic_vector(2675593,24); manlo <= conv_std_logic_vector(158348175,28); exponent <= conv_std_logic_vector(1030,11); WHEN "0000000110" => manhi <= conv_std_logic_vector(9661893,24); manlo <= conv_std_logic_vector(110149775,28); exponent <= conv_std_logic_vector(1031,11); WHEN "0000000111" => manhi <= conv_std_logic_vector(1190021,24); manlo <= conv_std_logic_vector(179232170,28); exponent <= conv_std_logic_vector(1033,11); WHEN "0000001000" => manhi <= conv_std_logic_vector(7642791,24); manlo <= conv_std_logic_vector(222760046,28); exponent <= conv_std_logic_vector(1034,11); WHEN "0000001001" => manhi <= conv_std_logic_vector(16413015,24); manlo <= conv_std_logic_vector(205983618,28); exponent <= conv_std_logic_vector(1035,11); WHEN "0000001010" => manhi <= conv_std_logic_vector(5777884,24); manlo <= conv_std_logic_vector(261424480,28); exponent <= conv_std_logic_vector(1037,11); WHEN "0000001011" => manhi <= conv_std_logic_vector(13878344,24); manlo <= conv_std_logic_vector(149835647,28); exponent <= conv_std_logic_vector(1038,11); WHEN "0000001100" => manhi <= conv_std_logic_vector(4055397,24); manlo <= conv_std_logic_vector(80968858,28); exponent <= conv_std_logic_vector(1040,11); WHEN "0000001101" => manhi <= conv_std_logic_vector(11537241,24); manlo <= conv_std_logic_vector(23775573,28); exponent <= conv_std_logic_vector(1041,11); WHEN "0000001110" => manhi <= conv_std_logic_vector(2464452,24); manlo <= conv_std_logic_vector(146736599,28); exponent <= conv_std_logic_vector(1043,11); WHEN "0000001111" => manhi <= conv_std_logic_vector(9374922,24); manlo <= conv_std_logic_vector(263006855,28); exponent <= conv_std_logic_vector(1044,11); WHEN "0000010000" => manhi <= conv_std_logic_vector(995005,24); manlo <= conv_std_logic_vector(11010080,28); exponent <= conv_std_logic_vector(1046,11); WHEN "0000010001" => manhi <= conv_std_logic_vector(7377736,24); manlo <= conv_std_logic_vector(202286329,28); exponent <= conv_std_logic_vector(1047,11); WHEN "0000010010" => manhi <= conv_std_logic_vector(16052768,24); manlo <= conv_std_logic_vector(152649917,28); exponent <= conv_std_logic_vector(1048,11); WHEN "0000010011" => manhi <= conv_std_logic_vector(5533071,24); manlo <= conv_std_logic_vector(166536930,28); exponent <= conv_std_logic_vector(1050,11); WHEN "0000010100" => manhi <= conv_std_logic_vector(13545608,24); manlo <= conv_std_logic_vector(191424516,28); exponent <= conv_std_logic_vector(1051,11); WHEN "0000010101" => manhi <= conv_std_logic_vector(3829279,24); manlo <= conv_std_logic_vector(228519165,28); exponent <= conv_std_logic_vector(1053,11); WHEN "0000010110" => manhi <= conv_std_logic_vector(11229915,24); manlo <= conv_std_logic_vector(163853824,28); exponent <= conv_std_logic_vector(1054,11); WHEN "0000010111" => manhi <= conv_std_logic_vector(2255603,24); manlo <= conv_std_logic_vector(61996481,28); exponent <= conv_std_logic_vector(1056,11); WHEN "0000011000" => manhi <= conv_std_logic_vector(9091067,24); manlo <= conv_std_logic_vector(88563639,28); exponent <= conv_std_logic_vector(1057,11); WHEN "0000011001" => manhi <= conv_std_logic_vector(802105,24); manlo <= conv_std_logic_vector(34169545,28); exponent <= conv_std_logic_vector(1059,11); WHEN "0000011010" => manhi <= conv_std_logic_vector(7115558,24); manlo <= conv_std_logic_vector(157969244,28); exponent <= conv_std_logic_vector(1060,11); WHEN "0000011011" => manhi <= conv_std_logic_vector(15696431,24); manlo <= conv_std_logic_vector(133591837,28); exponent <= conv_std_logic_vector(1061,11); WHEN "0000011100" => manhi <= conv_std_logic_vector(5290915,24); manlo <= conv_std_logic_vector(127285146,28); exponent <= conv_std_logic_vector(1063,11); WHEN "0000011101" => manhi <= conv_std_logic_vector(13216484,24); manlo <= conv_std_logic_vector(103923798,28); exponent <= conv_std_logic_vector(1064,11); WHEN "0000011110" => manhi <= conv_std_logic_vector(3605616,24); manlo <= conv_std_logic_vector(183249133,28); exponent <= conv_std_logic_vector(1066,11); WHEN "0000011111" => manhi <= conv_std_logic_vector(10925925,24); manlo <= conv_std_logic_vector(227336045,28); exponent <= conv_std_logic_vector(1067,11); WHEN "0000100000" => manhi <= conv_std_logic_vector(2049020,24); manlo <= conv_std_logic_vector(206267948,28); exponent <= conv_std_logic_vector(1069,11); WHEN "0000100001" => manhi <= conv_std_logic_vector(8810292,24); manlo <= conv_std_logic_vector(175265666,28); exponent <= conv_std_logic_vector(1070,11); WHEN "0000100010" => manhi <= conv_std_logic_vector(611298,24); manlo <= conv_std_logic_vector(255467255,28); exponent <= conv_std_logic_vector(1072,11); WHEN "0000100011" => manhi <= conv_std_logic_vector(6856226,24); manlo <= conv_std_logic_vector(29134171,28); exponent <= conv_std_logic_vector(1073,11); WHEN "0000100100" => manhi <= conv_std_logic_vector(15343962,24); manlo <= conv_std_logic_vector(30543222,28); exponent <= conv_std_logic_vector(1074,11); WHEN "0000100101" => manhi <= conv_std_logic_vector(5051387,24); manlo <= conv_std_logic_vector(186253338,28); exponent <= conv_std_logic_vector(1076,11); WHEN "0000100110" => manhi <= conv_std_logic_vector(12890932,24); manlo <= conv_std_logic_vector(102222951,28); exponent <= conv_std_logic_vector(1077,11); WHEN "0000100111" => manhi <= conv_std_logic_vector(3384381,24); manlo <= conv_std_logic_vector(42116377,28); exponent <= conv_std_logic_vector(1079,11); WHEN "0000101000" => manhi <= conv_std_logic_vector(10625235,24); manlo <= conv_std_logic_vector(158954218,28); exponent <= conv_std_logic_vector(1080,11); WHEN "0000101001" => manhi <= conv_std_logic_vector(1844680,24); manlo <= conv_std_logic_vector(148858978,28); exponent <= conv_std_logic_vector(1082,11); WHEN "0000101010" => manhi <= conv_std_logic_vector(8532565,24); manlo <= conv_std_logic_vector(136319321,28); exponent <= conv_std_logic_vector(1083,11); WHEN "0000101011" => manhi <= conv_std_logic_vector(422563,24); manlo <= conv_std_logic_vector(211728497,28); exponent <= conv_std_logic_vector(1085,11); WHEN "0000101100" => manhi <= conv_std_logic_vector(6599708,24); manlo <= conv_std_logic_vector(114522162,28); exponent <= conv_std_logic_vector(1086,11); WHEN "0000101101" => manhi <= conv_std_logic_vector(14995318,24); manlo <= conv_std_logic_vector(117328318,28); exponent <= conv_std_logic_vector(1087,11); WHEN "0000101110" => manhi <= conv_std_logic_vector(4814459,24); manlo <= conv_std_logic_vector(201622499,28); exponent <= conv_std_logic_vector(1089,11); WHEN "0000101111" => manhi <= conv_std_logic_vector(12568913,24); manlo <= conv_std_logic_vector(246987638,28); exponent <= conv_std_logic_vector(1090,11); WHEN "0000110000" => manhi <= conv_std_logic_vector(3165546,24); manlo <= conv_std_logic_vector(248128843,28); exponent <= conv_std_logic_vector(1092,11); WHEN "0000110001" => manhi <= conv_std_logic_vector(10327809,24); manlo <= conv_std_logic_vector(8929872,28); exponent <= conv_std_logic_vector(1093,11); WHEN "0000110010" => manhi <= conv_std_logic_vector(1642558,24); manlo <= conv_std_logic_vector(67636037,28); exponent <= conv_std_logic_vector(1095,11); WHEN "0000110011" => manhi <= conv_std_logic_vector(8257852,24); manlo <= conv_std_logic_vector(219235425,28); exponent <= conv_std_logic_vector(1096,11); WHEN "0000110100" => manhi <= conv_std_logic_vector(235877,24); manlo <= conv_std_logic_vector(42862412,28); exponent <= conv_std_logic_vector(1098,11); WHEN "0000110101" => manhi <= conv_std_logic_vector(6345974,24); manlo <= conv_std_logic_vector(265996080,28); exponent <= conv_std_logic_vector(1099,11); WHEN "0000110110" => manhi <= conv_std_logic_vector(14650458,24); manlo <= conv_std_logic_vector(253213243,28); exponent <= conv_std_logic_vector(1100,11); WHEN "0000110111" => manhi <= conv_std_logic_vector(4580103,24); manlo <= conv_std_logic_vector(114693785,28); exponent <= conv_std_logic_vector(1102,11); WHEN "0000111000" => manhi <= conv_std_logic_vector(12250390,24); manlo <= conv_std_logic_vector(174984615,28); exponent <= conv_std_logic_vector(1103,11); WHEN "0000111001" => manhi <= conv_std_logic_vector(2949087,24); manlo <= conv_std_logic_vector(247325089,28); exponent <= conv_std_logic_vector(1105,11); WHEN "0000111010" => manhi <= conv_std_logic_vector(10033610,24); manlo <= conv_std_logic_vector(200264553,28); exponent <= conv_std_logic_vector(1106,11); WHEN "0000111011" => manhi <= conv_std_logic_vector(1442629,24); manlo <= conv_std_logic_vector(211375075,28); exponent <= conv_std_logic_vector(1108,11); WHEN "0000111100" => manhi <= conv_std_logic_vector(7986121,24); manlo <= conv_std_logic_vector(231029862,28); exponent <= conv_std_logic_vector(1109,11); WHEN "0000111101" => manhi <= conv_std_logic_vector(51216,24); manlo <= conv_std_logic_vector(222707863,28); exponent <= conv_std_logic_vector(1111,11); WHEN "0000111110" => manhi <= conv_std_logic_vector(6094995,24); manlo <= conv_std_logic_vector(155999272,28); exponent <= conv_std_logic_vector(1112,11); WHEN "0000111111" => manhi <= conv_std_logic_vector(14309342,24); manlo <= conv_std_logic_vector(150013864,28); exponent <= conv_std_logic_vector(1113,11); WHEN "0001000000" => manhi <= conv_std_logic_vector(4348290,24); manlo <= conv_std_logic_vector(217421773,28); exponent <= conv_std_logic_vector(1115,11); WHEN "0001000001" => manhi <= conv_std_logic_vector(11935324,24); manlo <= conv_std_logic_vector(171597361,28); exponent <= conv_std_logic_vector(1116,11); WHEN "0001000010" => manhi <= conv_std_logic_vector(2734978,24); manlo <= conv_std_logic_vector(98553735,28); exponent <= conv_std_logic_vector(1118,11); WHEN "0001000011" => manhi <= conv_std_logic_vector(9742605,24); manlo <= conv_std_logic_vector(185429986,28); exponent <= conv_std_logic_vector(1119,11); WHEN "0001000100" => manhi <= conv_std_logic_vector(1244871,24); manlo <= conv_std_logic_vector(93685501,28); exponent <= conv_std_logic_vector(1121,11); WHEN "0001000101" => manhi <= conv_std_logic_vector(7717340,24); manlo <= conv_std_logic_vector(74048432,28); exponent <= conv_std_logic_vector(1122,11); WHEN "0001000110" => manhi <= conv_std_logic_vector(16514337,24); manlo <= conv_std_logic_vector(163855108,28); exponent <= conv_std_logic_vector(1123,11); WHEN "0001000111" => manhi <= conv_std_logic_vector(5846740,24); manlo <= conv_std_logic_vector(81895750,28); exponent <= conv_std_logic_vector(1125,11); WHEN "0001001000" => manhi <= conv_std_logic_vector(13971928,24); manlo <= conv_std_logic_vector(176088988,28); exponent <= conv_std_logic_vector(1126,11); WHEN "0001001001" => manhi <= conv_std_logic_vector(4118994,24); manlo <= conv_std_logic_vector(77780251,28); exponent <= conv_std_logic_vector(1128,11); WHEN "0001001010" => manhi <= conv_std_logic_vector(11623678,24); manlo <= conv_std_logic_vector(95871356,28); exponent <= conv_std_logic_vector(1129,11); WHEN "0001001011" => manhi <= conv_std_logic_vector(2523192,24); manlo <= conv_std_logic_vector(204213760,28); exponent <= conv_std_logic_vector(1131,11); WHEN "0001001100" => manhi <= conv_std_logic_vector(9454759,24); manlo <= conv_std_logic_vector(55860552,28); exponent <= conv_std_logic_vector(1132,11); WHEN "0001001101" => manhi <= conv_std_logic_vector(1049259,24); manlo <= conv_std_logic_vector(102861624,28); exponent <= conv_std_logic_vector(1134,11); WHEN "0001001110" => manhi <= conv_std_logic_vector(7451476,24); manlo <= conv_std_logic_vector(13367584,28); exponent <= conv_std_logic_vector(1135,11); WHEN "0001001111" => manhi <= conv_std_logic_vector(16152990,24); manlo <= conv_std_logic_vector(178012490,28); exponent <= conv_std_logic_vector(1136,11); WHEN "0001010000" => manhi <= conv_std_logic_vector(5601179,24); manlo <= conv_std_logic_vector(159708139,28); exponent <= conv_std_logic_vector(1138,11); WHEN "0001010001" => manhi <= conv_std_logic_vector(13638177,24); manlo <= conv_std_logic_vector(12864164,28); exponent <= conv_std_logic_vector(1139,11); WHEN "0001010010" => manhi <= conv_std_logic_vector(3892186,24); manlo <= conv_std_logic_vector(149492240,28); exponent <= conv_std_logic_vector(1141,11); WHEN "0001010011" => manhi <= conv_std_logic_vector(11315414,24); manlo <= conv_std_logic_vector(184620728,28); exponent <= conv_std_logic_vector(1142,11); WHEN "0001010100" => manhi <= conv_std_logic_vector(2313705,24); manlo <= conv_std_logic_vector(235697385,28); exponent <= conv_std_logic_vector(1144,11); WHEN "0001010101" => manhi <= conv_std_logic_vector(9170037,24); manlo <= conv_std_logic_vector(3974263,28); exponent <= conv_std_logic_vector(1145,11); WHEN "0001010110" => manhi <= conv_std_logic_vector(855770,24); manlo <= conv_std_logic_vector(158952336,28); exponent <= conv_std_logic_vector(1147,11); WHEN "0001010111" => manhi <= conv_std_logic_vector(7188497,24); manlo <= conv_std_logic_vector(138900038,28); exponent <= conv_std_logic_vector(1148,11); WHEN "0001011000" => manhi <= conv_std_logic_vector(15795565,24); manlo <= conv_std_logic_vector(209449517,28); exponent <= conv_std_logic_vector(1149,11); WHEN "0001011001" => manhi <= conv_std_logic_vector(5358284,24); manlo <= conv_std_logic_vector(54736896,28); exponent <= conv_std_logic_vector(1151,11); WHEN "0001011010" => manhi <= conv_std_logic_vector(13308047,24); manlo <= conv_std_logic_vector(264159588,28); exponent <= conv_std_logic_vector(1152,11); WHEN "0001011011" => manhi <= conv_std_logic_vector(3667840,24); manlo <= conv_std_logic_vector(160544132,28); exponent <= conv_std_logic_vector(1154,11); WHEN "0001011100" => manhi <= conv_std_logic_vector(11010496,24); manlo <= conv_std_logic_vector(245935181,28); exponent <= conv_std_logic_vector(1155,11); WHEN "0001011101" => manhi <= conv_std_logic_vector(2106492,24); manlo <= conv_std_logic_vector(206325441,28); exponent <= conv_std_logic_vector(1157,11); WHEN "0001011110" => manhi <= conv_std_logic_vector(8888405,24); manlo <= conv_std_logic_vector(53641237,28); exponent <= conv_std_logic_vector(1158,11); WHEN "0001011111" => manhi <= conv_std_logic_vector(664381,24); manlo <= conv_std_logic_vector(249887163,28); exponent <= conv_std_logic_vector(1160,11); WHEN "0001100000" => manhi <= conv_std_logic_vector(6928373,24); manlo <= conv_std_logic_vector(95946938,28); exponent <= conv_std_logic_vector(1161,11); WHEN "0001100001" => manhi <= conv_std_logic_vector(15442020,24); manlo <= conv_std_logic_vector(105121290,28); exponent <= conv_std_logic_vector(1162,11); WHEN "0001100010" => manhi <= conv_std_logic_vector(5118025,24); manlo <= conv_std_logic_vector(54367076,28); exponent <= conv_std_logic_vector(1164,11); WHEN "0001100011" => manhi <= conv_std_logic_vector(12981502,24); manlo <= conv_std_logic_vector(39000129,28); exponent <= conv_std_logic_vector(1165,11); WHEN "0001100100" => manhi <= conv_std_logic_vector(3445929,24); manlo <= conv_std_logic_vector(186063861,28); exponent <= conv_std_logic_vector(1167,11); WHEN "0001100101" => manhi <= conv_std_logic_vector(10708888,24); manlo <= conv_std_logic_vector(194877084,28); exponent <= conv_std_logic_vector(1168,11); WHEN "0001100110" => manhi <= conv_std_logic_vector(1901528,24); manlo <= conv_std_logic_vector(202114223,28); exponent <= conv_std_logic_vector(1170,11); WHEN "0001100111" => manhi <= conv_std_logic_vector(8609830,24); manlo <= conv_std_logic_vector(59099508,28); exponent <= conv_std_logic_vector(1171,11); WHEN "0001101000" => manhi <= conv_std_logic_vector(475070,24); manlo <= conv_std_logic_vector(162304029,28); exponent <= conv_std_logic_vector(1173,11); WHEN "0001101001" => manhi <= conv_std_logic_vector(6671072,24); manlo <= conv_std_logic_vector(157938310,28); exponent <= conv_std_logic_vector(1174,11); WHEN "0001101010" => manhi <= conv_std_logic_vector(15092312,24); manlo <= conv_std_logic_vector(104450792,28); exponent <= conv_std_logic_vector(1175,11); WHEN "0001101011" => manhi <= conv_std_logic_vector(4880373,24); manlo <= conv_std_logic_vector(261837049,28); exponent <= conv_std_logic_vector(1177,11); WHEN "0001101100" => manhi <= conv_std_logic_vector(12658500,24); manlo <= conv_std_logic_vector(171583716,28); exponent <= conv_std_logic_vector(1178,11); WHEN "0001101101" => manhi <= conv_std_logic_vector(3226427,24); manlo <= conv_std_logic_vector(110595717,28); exponent <= conv_std_logic_vector(1180,11); WHEN "0001101110" => manhi <= conv_std_logic_vector(10410554,24); manlo <= conv_std_logic_vector(52320382,28); exponent <= conv_std_logic_vector(1181,11); WHEN "0001101111" => manhi <= conv_std_logic_vector(1698789,24); manlo <= conv_std_logic_vector(112550995,28); exponent <= conv_std_logic_vector(1183,11); WHEN "0001110000" => manhi <= conv_std_logic_vector(8334278,24); manlo <= conv_std_logic_vector(240753534,28); exponent <= conv_std_logic_vector(1184,11); WHEN "0001110001" => manhi <= conv_std_logic_vector(287814,24); manlo <= conv_std_logic_vector(17691391,28); exponent <= conv_std_logic_vector(1186,11); WHEN "0001110010" => manhi <= conv_std_logic_vector(6416564,24); manlo <= conv_std_logic_vector(151700710,28); exponent <= conv_std_logic_vector(1187,11); WHEN "0001110011" => manhi <= conv_std_logic_vector(14746400,24); manlo <= conv_std_logic_vector(32676275,28); exponent <= conv_std_logic_vector(1188,11); WHEN "0001110100" => manhi <= conv_std_logic_vector(4645302,24); manlo <= conv_std_logic_vector(58452725,28); exponent <= conv_std_logic_vector(1190,11); WHEN "0001110101" => manhi <= conv_std_logic_vector(12339004,24); manlo <= conv_std_logic_vector(267247876,28); exponent <= conv_std_logic_vector(1191,11); WHEN "0001110110" => manhi <= conv_std_logic_vector(3009307,24); manlo <= conv_std_logic_vector(164126253,28); exponent <= conv_std_logic_vector(1193,11); WHEN "0001110111" => manhi <= conv_std_logic_vector(10115457,24); manlo <= conv_std_logic_vector(212237584,28); exponent <= conv_std_logic_vector(1194,11); WHEN "0001111000" => manhi <= conv_std_logic_vector(1498250,24); manlo <= conv_std_logic_vector(166684427,28); exponent <= conv_std_logic_vector(1196,11); WHEN "0001111001" => manhi <= conv_std_logic_vector(8061718,24); manlo <= conv_std_logic_vector(110371593,28); exponent <= conv_std_logic_vector(1197,11); WHEN "0001111010" => manhi <= conv_std_logic_vector(102590,24); manlo <= conv_std_logic_vector(3231911,28); exponent <= conv_std_logic_vector(1199,11); WHEN "0001111011" => manhi <= conv_std_logic_vector(6164818,24); manlo <= conv_std_logic_vector(261783833,28); exponent <= conv_std_logic_vector(1200,11); WHEN "0001111100" => manhi <= conv_std_logic_vector(14404242,24); manlo <= conv_std_logic_vector(104825991,28); exponent <= conv_std_logic_vector(1201,11); WHEN "0001111101" => manhi <= conv_std_logic_vector(4412781,24); manlo <= conv_std_logic_vector(250166254,28); exponent <= conv_std_logic_vector(1203,11); WHEN "0001111110" => manhi <= conv_std_logic_vector(12022977,24); manlo <= conv_std_logic_vector(43417082,28); exponent <= conv_std_logic_vector(1204,11); WHEN "0001111111" => manhi <= conv_std_logic_vector(2794544,24); manlo <= conv_std_logic_vector(115942082,28); exponent <= conv_std_logic_vector(1206,11); WHEN "0010000000" => manhi <= conv_std_logic_vector(9823564,24); manlo <= conv_std_logic_vector(98386456,28); exponent <= conv_std_logic_vector(1207,11); WHEN "0010000001" => manhi <= conv_std_logic_vector(1299888,24); manlo <= conv_std_logic_vector(127046227,28); exponent <= conv_std_logic_vector(1209,11); WHEN "0010000010" => manhi <= conv_std_logic_vector(7792116,24); manlo <= conv_std_logic_vector(80649262,28); exponent <= conv_std_logic_vector(1210,11); WHEN "0010000011" => manhi <= conv_std_logic_vector(16615968,24); manlo <= conv_std_logic_vector(205307910,28); exponent <= conv_std_logic_vector(1211,11); WHEN "0010000100" => manhi <= conv_std_logic_vector(5915805,24); manlo <= conv_std_logic_vector(224185017,28); exponent <= conv_std_logic_vector(1213,11); WHEN "0010000101" => manhi <= conv_std_logic_vector(14065798,24); manlo <= conv_std_logic_vector(119094636,28); exponent <= conv_std_logic_vector(1214,11); WHEN "0010000110" => manhi <= conv_std_logic_vector(4182785,24); manlo <= conv_std_logic_vector(113890892,28); exponent <= conv_std_logic_vector(1216,11); WHEN "0010000111" => manhi <= conv_std_logic_vector(11710379,24); manlo <= conv_std_logic_vector(133692518,28); exponent <= conv_std_logic_vector(1217,11); WHEN "0010001000" => manhi <= conv_std_logic_vector(2582112,24); manlo <= conv_std_logic_vector(79109485,28); exponent <= conv_std_logic_vector(1219,11); WHEN "0010001001" => manhi <= conv_std_logic_vector(9534839,24); manlo <= conv_std_logic_vector(42234535,28); exponent <= conv_std_logic_vector(1220,11); WHEN "0010001010" => manhi <= conv_std_logic_vector(1103679,24); manlo <= conv_std_logic_vector(94193887,28); exponent <= conv_std_logic_vector(1222,11); WHEN "0010001011" => manhi <= conv_std_logic_vector(7525440,24); manlo <= conv_std_logic_vector(121994268,28); exponent <= conv_std_logic_vector(1223,11); WHEN "0010001100" => manhi <= conv_std_logic_vector(16253518,24); manlo <= conv_std_logic_vector(191052573,28); exponent <= conv_std_logic_vector(1224,11); WHEN "0010001101" => manhi <= conv_std_logic_vector(5669495,24); manlo <= conv_std_logic_vector(130696997,28); exponent <= conv_std_logic_vector(1226,11); WHEN "0010001110" => manhi <= conv_std_logic_vector(13731027,24); manlo <= conv_std_logic_vector(260846837,28); exponent <= conv_std_logic_vector(1227,11); WHEN "0010001111" => manhi <= conv_std_logic_vector(3955285,24); manlo <= conv_std_logic_vector(80970159,28); exponent <= conv_std_logic_vector(1229,11); WHEN "0010010000" => manhi <= conv_std_logic_vector(11401174,24); manlo <= conv_std_logic_vector(207600506,28); exponent <= conv_std_logic_vector(1230,11); WHEN "0010010001" => manhi <= conv_std_logic_vector(2371985,24); manlo <= conv_std_logic_vector(241221170,28); exponent <= conv_std_logic_vector(1232,11); WHEN "0010010010" => manhi <= conv_std_logic_vector(9249247,24); manlo <= conv_std_logic_vector(208105818,28); exponent <= conv_std_logic_vector(1233,11); WHEN "0010010011" => manhi <= conv_std_logic_vector(909599,24); manlo <= conv_std_logic_vector(237519888,28); exponent <= conv_std_logic_vector(1235,11); WHEN "0010010100" => manhi <= conv_std_logic_vector(7261659,24); manlo <= conv_std_logic_vector(29935335,28); exponent <= conv_std_logic_vector(1236,11); WHEN "0010010101" => manhi <= conv_std_logic_vector(15895002,24); manlo <= conv_std_logic_vector(186862656,28); exponent <= conv_std_logic_vector(1237,11); WHEN "0010010110" => manhi <= conv_std_logic_vector(5425858,24); manlo <= conv_std_logic_vector(159524243,28); exponent <= conv_std_logic_vector(1239,11); WHEN "0010010111" => manhi <= conv_std_logic_vector(13399891,24); manlo <= conv_std_logic_vector(27586577,28); exponent <= conv_std_logic_vector(1240,11); WHEN "0010011000" => manhi <= conv_std_logic_vector(3730254,24); manlo <= conv_std_logic_vector(125689310,28); exponent <= conv_std_logic_vector(1242,11); WHEN "0010011001" => manhi <= conv_std_logic_vector(11095326,24); manlo <= conv_std_logic_vector(43144000,28); exponent <= conv_std_logic_vector(1243,11); WHEN "0010011010" => manhi <= conv_std_logic_vector(2164140,24); manlo <= conv_std_logic_vector(58280992,28); exponent <= conv_std_logic_vector(1245,11); WHEN "0010011011" => manhi <= conv_std_logic_vector(8966756,24); manlo <= conv_std_logic_vector(55210422,28); exponent <= conv_std_logic_vector(1246,11); WHEN "0010011100" => manhi <= conv_std_logic_vector(717626,24); manlo <= conv_std_logic_vector(257633658,28); exponent <= conv_std_logic_vector(1248,11); WHEN "0010011101" => manhi <= conv_std_logic_vector(7000740,24); manlo <= conv_std_logic_vector(229413090,28); exponent <= conv_std_logic_vector(1249,11); WHEN "0010011110" => manhi <= conv_std_logic_vector(15540378,24); manlo <= conv_std_logic_vector(4808337,28); exponent <= conv_std_logic_vector(1250,11); WHEN "0010011111" => manhi <= conv_std_logic_vector(5184866,24); manlo <= conv_std_logic_vector(37474138,28); exponent <= conv_std_logic_vector(1252,11); WHEN "0010100000" => manhi <= conv_std_logic_vector(13072348,24); manlo <= conv_std_logic_vector(106730632,28); exponent <= conv_std_logic_vector(1253,11); WHEN "0010100001" => manhi <= conv_std_logic_vector(3507666,24); manlo <= conv_std_logic_vector(32844500,28); exponent <= conv_std_logic_vector(1255,11); WHEN "0010100010" => manhi <= conv_std_logic_vector(10792797,24); manlo <= conv_std_logic_vector(62496090,28); exponent <= conv_std_logic_vector(1256,11); WHEN "0010100011" => manhi <= conv_std_logic_vector(1958550,24); manlo <= conv_std_logic_vector(132952012,28); exponent <= conv_std_logic_vector(1258,11); WHEN "0010100100" => manhi <= conv_std_logic_vector(8687330,24); manlo <= conv_std_logic_vector(215605290,28); exponent <= conv_std_logic_vector(1259,11); WHEN "0010100101" => manhi <= conv_std_logic_vector(527737,24); manlo <= conv_std_logic_vector(190928911,28); exponent <= conv_std_logic_vector(1261,11); WHEN "0010100110" => manhi <= conv_std_logic_vector(6742654,24); manlo <= conv_std_logic_vector(163162889,28); exponent <= conv_std_logic_vector(1262,11); WHEN "0010100111" => manhi <= conv_std_logic_vector(15189602,24); manlo <= conv_std_logic_vector(118241780,28); exponent <= conv_std_logic_vector(1263,11); WHEN "0010101000" => manhi <= conv_std_logic_vector(4946489,24); manlo <= conv_std_logic_vector(112771062,28); exponent <= conv_std_logic_vector(1265,11); WHEN "0010101001" => manhi <= conv_std_logic_vector(12748360,24); manlo <= conv_std_logic_vector(226864003,28); exponent <= conv_std_logic_vector(1266,11); WHEN "0010101010" => manhi <= conv_std_logic_vector(3287493,24); manlo <= conv_std_logic_vector(202192272,28); exponent <= conv_std_logic_vector(1268,11); WHEN "0010101011" => manhi <= conv_std_logic_vector(10493551,24); manlo <= conv_std_logic_vector(257093553,28); exponent <= conv_std_logic_vector(1269,11); WHEN "0010101100" => manhi <= conv_std_logic_vector(1755192,24); manlo <= conv_std_logic_vector(66281405,28); exponent <= conv_std_logic_vector(1271,11); WHEN "0010101101" => manhi <= conv_std_logic_vector(8410938,24); manlo <= conv_std_logic_vector(77199396,28); exponent <= conv_std_logic_vector(1272,11); WHEN "0010101110" => manhi <= conv_std_logic_vector(339909,24); manlo <= conv_std_logic_vector(140417186,28); exponent <= conv_std_logic_vector(1274,11); WHEN "0010101111" => manhi <= conv_std_logic_vector(6487369,24); manlo <= conv_std_logic_vector(169769464,28); exponent <= conv_std_logic_vector(1275,11); WHEN "0010110000" => manhi <= conv_std_logic_vector(14842634,24); manlo <= conv_std_logic_vector(49834035,28); exponent <= conv_std_logic_vector(1276,11); WHEN "0010110001" => manhi <= conv_std_logic_vector(4710700,24); manlo <= conv_std_logic_vector(11961455,28); exponent <= conv_std_logic_vector(1278,11); WHEN "0010110010" => manhi <= conv_std_logic_vector(12427889,24); manlo <= conv_std_logic_vector(230234502,28); exponent <= conv_std_logic_vector(1279,11); WHEN "0010110011" => manhi <= conv_std_logic_vector(3069711,24); manlo <= conv_std_logic_vector(36989233,28); exponent <= conv_std_logic_vector(1281,11); WHEN "0010110100" => manhi <= conv_std_logic_vector(10197554,24); manlo <= conv_std_logic_vector(186484869,28); exponent <= conv_std_logic_vector(1282,11); WHEN "0010110101" => manhi <= conv_std_logic_vector(1554041,24); manlo <= conv_std_logic_vector(67530342,28); exponent <= conv_std_logic_vector(1284,11); WHEN "0010110110" => manhi <= conv_std_logic_vector(8137545,24); manlo <= conv_std_logic_vector(198608842,28); exponent <= conv_std_logic_vector(1285,11); WHEN "0010110111" => manhi <= conv_std_logic_vector(154120,24); manlo <= conv_std_logic_vector(6569319,28); exponent <= conv_std_logic_vector(1287,11); WHEN "0010111000" => manhi <= conv_std_logic_vector(6234855,24); manlo <= conv_std_logic_vector(140506894,28); exponent <= conv_std_logic_vector(1288,11); WHEN "0010111001" => manhi <= conv_std_logic_vector(14499431,24); manlo <= conv_std_logic_vector(249287529,28); exponent <= conv_std_logic_vector(1289,11); WHEN "0010111010" => manhi <= conv_std_logic_vector(4477469,24); manlo <= conv_std_logic_vector(249618841,28); exponent <= conv_std_logic_vector(1291,11); WHEN "0010111011" => manhi <= conv_std_logic_vector(12110897,24); manlo <= conv_std_logic_vector(71519058,28); exponent <= conv_std_logic_vector(1292,11); WHEN "0010111100" => manhi <= conv_std_logic_vector(2854292,24); manlo <= conv_std_logic_vector(90637320,28); exponent <= conv_std_logic_vector(1294,11); WHEN "0010111101" => manhi <= conv_std_logic_vector(9904770,24); manlo <= conv_std_logic_vector(50932558,28); exponent <= conv_std_logic_vector(1295,11); WHEN "0010111110" => manhi <= conv_std_logic_vector(1355073,24); manlo <= conv_std_logic_vector(148093260,28); exponent <= conv_std_logic_vector(1297,11); WHEN "0010111111" => manhi <= conv_std_logic_vector(7867120,24); manlo <= conv_std_logic_vector(160620741,28); exponent <= conv_std_logic_vector(1298,11); WHEN "0011000000" => manhi <= conv_std_logic_vector(16717910,24); manlo <= conv_std_logic_vector(46942270,28); exponent <= conv_std_logic_vector(1299,11); WHEN "0011000001" => manhi <= conv_std_logic_vector(5985082,24); manlo <= conv_std_logic_vector(55237426,28); exponent <= conv_std_logic_vector(1301,11); WHEN "0011000010" => manhi <= conv_std_logic_vector(14159954,24); manlo <= conv_std_logic_vector(212966668,28); exponent <= conv_std_logic_vector(1302,11); WHEN "0011000011" => manhi <= conv_std_logic_vector(4246771,24); manlo <= conv_std_logic_vector(79962334,28); exponent <= conv_std_logic_vector(1304,11); WHEN "0011000100" => manhi <= conv_std_logic_vector(11797345,24); manlo <= conv_std_logic_vector(85038862,28); exponent <= conv_std_logic_vector(1305,11); WHEN "0011000101" => manhi <= conv_std_logic_vector(2641211,24); manlo <= conv_std_logic_vector(186806322,28); exponent <= conv_std_logic_vector(1307,11); WHEN "0011000110" => manhi <= conv_std_logic_vector(9615163,24); manlo <= conv_std_logic_vector(153415152,28); exponent <= conv_std_logic_vector(1308,11); WHEN "0011000111" => manhi <= conv_std_logic_vector(1158265,24); manlo <= conv_std_logic_vector(120731907,28); exponent <= conv_std_logic_vector(1310,11); WHEN "0011001000" => manhi <= conv_std_logic_vector(7599630,24); manlo <= conv_std_logic_vector(175764921,28); exponent <= conv_std_logic_vector(1311,11); WHEN "0011001001" => manhi <= conv_std_logic_vector(16354353,24); manlo <= conv_std_logic_vector(174054693,28); exponent <= conv_std_logic_vector(1312,11); WHEN "0011001010" => manhi <= conv_std_logic_vector(5738019,24); manlo <= conv_std_logic_vector(249885394,28); exponent <= conv_std_logic_vector(1314,11); WHEN "0011001011" => manhi <= conv_std_logic_vector(13824162,24); manlo <= conv_std_logic_vector(93203713,28); exponent <= conv_std_logic_vector(1315,11); WHEN "0011001100" => manhi <= conv_std_logic_vector(4018576,24); manlo <= conv_std_logic_vector(180323091,28); exponent <= conv_std_logic_vector(1317,11); WHEN "0011001101" => manhi <= conv_std_logic_vector(11487196,24); manlo <= conv_std_logic_vector(178245939,28); exponent <= conv_std_logic_vector(1318,11); WHEN "0011001110" => manhi <= conv_std_logic_vector(2430443,24); manlo <= conv_std_logic_vector(223919964,28); exponent <= conv_std_logic_vector(1320,11); WHEN "0011001111" => manhi <= conv_std_logic_vector(9328700,24); manlo <= conv_std_logic_vector(93205956,28); exponent <= conv_std_logic_vector(1321,11); WHEN "0011010000" => manhi <= conv_std_logic_vector(963593,24); manlo <= conv_std_logic_vector(135688620,28); exponent <= conv_std_logic_vector(1323,11); WHEN "0011010001" => manhi <= conv_std_logic_vector(7335044,24); manlo <= conv_std_logic_vector(13542358,28); exponent <= conv_std_logic_vector(1324,11); WHEN "0011010010" => manhi <= conv_std_logic_vector(15994743,24); manlo <= conv_std_logic_vector(45394459,28); exponent <= conv_std_logic_vector(1325,11); WHEN "0011010011" => manhi <= conv_std_logic_vector(5493639,24); manlo <= conv_std_logic_vector(73308838,28); exponent <= conv_std_logic_vector(1327,11); WHEN "0011010100" => manhi <= conv_std_logic_vector(13492014,24); manlo <= conv_std_logic_vector(160135181,28); exponent <= conv_std_logic_vector(1328,11); WHEN "0011010101" => manhi <= conv_std_logic_vector(3792858,24); manlo <= conv_std_logic_vector(234346738,28); exponent <= conv_std_logic_vector(1330,11); WHEN "0011010110" => manhi <= conv_std_logic_vector(11180414,24); manlo <= conv_std_logic_vector(98964646,28); exponent <= conv_std_logic_vector(1331,11); WHEN "0011010111" => manhi <= conv_std_logic_vector(2221963,24); manlo <= conv_std_logic_vector(174344531,28); exponent <= conv_std_logic_vector(1333,11); WHEN "0011011000" => manhi <= conv_std_logic_vector(9045346,24); manlo <= conv_std_logic_vector(106947534,28); exponent <= conv_std_logic_vector(1334,11); WHEN "0011011001" => manhi <= conv_std_logic_vector(771034,24); manlo <= conv_std_logic_vector(143065990,28); exponent <= conv_std_logic_vector(1336,11); WHEN "0011011010" => manhi <= conv_std_logic_vector(7073329,24); manlo <= conv_std_logic_vector(73148434,28); exponent <= conv_std_logic_vector(1337,11); WHEN "0011011011" => manhi <= conv_std_logic_vector(15639035,24); manlo <= conv_std_logic_vector(243346703,28); exponent <= conv_std_logic_vector(1338,11); WHEN "0011011100" => manhi <= conv_std_logic_vector(5251911,24); manlo <= conv_std_logic_vector(33842377,28); exponent <= conv_std_logic_vector(1340,11); WHEN "0011011101" => manhi <= conv_std_logic_vector(13163471,24); manlo <= conv_std_logic_vector(263552292,28); exponent <= conv_std_logic_vector(1341,11); WHEN "0011011110" => manhi <= conv_std_logic_vector(3569591,24); manlo <= conv_std_logic_vector(4866264,28); exponent <= conv_std_logic_vector(1343,11); WHEN "0011011111" => manhi <= conv_std_logic_vector(10876961,24); manlo <= conv_std_logic_vector(239517036,28); exponent <= conv_std_logic_vector(1344,11); WHEN "0011100000" => manhi <= conv_std_logic_vector(2015746,24); manlo <= conv_std_logic_vector(83586287,28); exponent <= conv_std_logic_vector(1346,11); WHEN "0011100001" => manhi <= conv_std_logic_vector(8765067,24); manlo <= conv_std_logic_vector(262254542,28); exponent <= conv_std_logic_vector(1347,11); WHEN "0011100010" => manhi <= conv_std_logic_vector(580565,24); manlo <= conv_std_logic_vector(160521039,28); exponent <= conv_std_logic_vector(1349,11); WHEN "0011100011" => manhi <= conv_std_logic_vector(6814455,24); manlo <= conv_std_logic_vector(40288155,28); exponent <= conv_std_logic_vector(1350,11); WHEN "0011100100" => manhi <= conv_std_logic_vector(15287189,24); manlo <= conv_std_logic_vector(132910147,28); exponent <= conv_std_logic_vector(1351,11); WHEN "0011100101" => manhi <= conv_std_logic_vector(5012806,24); manlo <= conv_std_logic_vector(187753904,28); exponent <= conv_std_logic_vector(1353,11); WHEN "0011100110" => manhi <= conv_std_logic_vector(12838495,24); manlo <= conv_std_logic_vector(100071648,28); exponent <= conv_std_logic_vector(1354,11); WHEN "0011100111" => manhi <= conv_std_logic_vector(3348746,24); manlo <= conv_std_logic_vector(138348888,28); exponent <= conv_std_logic_vector(1356,11); WHEN "0011101000" => manhi <= conv_std_logic_vector(10576803,24); manlo <= conv_std_logic_vector(24941937,28); exponent <= conv_std_logic_vector(1357,11); WHEN "0011101001" => manhi <= conv_std_logic_vector(1811767,24); manlo <= conv_std_logic_vector(69497619,28); exponent <= conv_std_logic_vector(1359,11); WHEN "0011101010" => manhi <= conv_std_logic_vector(8487831,24); manlo <= conv_std_logic_vector(188199296,28); exponent <= conv_std_logic_vector(1360,11); WHEN "0011101011" => manhi <= conv_std_logic_vector(392164,24); manlo <= conv_std_logic_vector(4096525,28); exponent <= conv_std_logic_vector(1362,11); WHEN "0011101100" => manhi <= conv_std_logic_vector(6558390,24); manlo <= conv_std_logic_vector(228356857,28); exponent <= conv_std_logic_vector(1363,11); WHEN "0011101101" => manhi <= conv_std_logic_vector(14939162,24); manlo <= conv_std_logic_vector(7826265,28); exponent <= conv_std_logic_vector(1364,11); WHEN "0011101110" => manhi <= conv_std_logic_vector(4776297,24); manlo <= conv_std_logic_vector(138324122,28); exponent <= conv_std_logic_vector(1366,11); WHEN "0011101111" => manhi <= conv_std_logic_vector(12517046,24); manlo <= conv_std_logic_vector(17190560,28); exponent <= conv_std_logic_vector(1367,11); WHEN "0011110000" => manhi <= conv_std_logic_vector(3130299,24); manlo <= conv_std_logic_vector(16562242,28); exponent <= conv_std_logic_vector(1369,11); WHEN "0011110001" => manhi <= conv_std_logic_vector(10279902,24); manlo <= conv_std_logic_vector(59323104,28); exponent <= conv_std_logic_vector(1370,11); WHEN "0011110010" => manhi <= conv_std_logic_vector(1610002,24); manlo <= conv_std_logic_vector(53056333,28); exponent <= conv_std_logic_vector(1372,11); WHEN "0011110011" => manhi <= conv_std_logic_vector(8213604,24); manlo <= conv_std_logic_vector(147986337,28); exponent <= conv_std_logic_vector(1373,11); WHEN "0011110100" => manhi <= conv_std_logic_vector(205807,24); manlo <= conv_std_logic_vector(92802035,28); exponent <= conv_std_logic_vector(1375,11); WHEN "0011110101" => manhi <= conv_std_logic_vector(6305105,24); manlo <= conv_std_logic_vector(235277170,28); exponent <= conv_std_logic_vector(1376,11); WHEN "0011110110" => manhi <= conv_std_logic_vector(14594912,24); manlo <= conv_std_logic_vector(15497684,28); exponent <= conv_std_logic_vector(1377,11); WHEN "0011110111" => manhi <= conv_std_logic_vector(4542355,24); manlo <= conv_std_logic_vector(108677892,28); exponent <= conv_std_logic_vector(1379,11); WHEN "0011111000" => manhi <= conv_std_logic_vector(12199085,24); manlo <= conv_std_logic_vector(206743222,28); exponent <= conv_std_logic_vector(1380,11); WHEN "0011111001" => manhi <= conv_std_logic_vector(2914222,24); manlo <= conv_std_logic_vector(171652524,28); exponent <= conv_std_logic_vector(1382,11); WHEN "0011111010" => manhi <= conv_std_logic_vector(9986223,24); manlo <= conv_std_logic_vector(245598061,28); exponent <= conv_std_logic_vector(1383,11); WHEN "0011111011" => manhi <= conv_std_logic_vector(1410427,24); manlo <= conv_std_logic_vector(26024388,28); exponent <= conv_std_logic_vector(1385,11); WHEN "0011111100" => manhi <= conv_std_logic_vector(7942353,24); manlo <= conv_std_logic_vector(232590388,28); exponent <= conv_std_logic_vector(1386,11); WHEN "0011111101" => manhi <= conv_std_logic_vector(21473,24); manlo <= conv_std_logic_vector(105719295,28); exponent <= conv_std_logic_vector(1388,11); WHEN "0011111110" => manhi <= conv_std_logic_vector(6054570,24); manlo <= conv_std_logic_vector(16265786,28); exponent <= conv_std_logic_vector(1389,11); WHEN "0011111111" => manhi <= conv_std_logic_vector(14254398,24); manlo <= conv_std_logic_vector(155662944,28); exponent <= conv_std_logic_vector(1390,11); WHEN "0100000000" => manhi <= conv_std_logic_vector(4310952,24); manlo <= conv_std_logic_vector(135577274,28); exponent <= conv_std_logic_vector(1392,11); WHEN "0100000001" => manhi <= conv_std_logic_vector(11884576,24); manlo <= conv_std_logic_vector(166805756,28); exponent <= conv_std_logic_vector(1393,11); WHEN "0100000010" => manhi <= conv_std_logic_vector(2700491,24); manlo <= conv_std_logic_vector(137829044,28); exponent <= conv_std_logic_vector(1395,11); WHEN "0100000011" => manhi <= conv_std_logic_vector(9695733,24); manlo <= conv_std_logic_vector(52863001,28); exponent <= conv_std_logic_vector(1396,11); WHEN "0100000100" => manhi <= conv_std_logic_vector(1213018,24); manlo <= conv_std_logic_vector(50179603,28); exponent <= conv_std_logic_vector(1398,11); WHEN "0100000101" => manhi <= conv_std_logic_vector(7674047,24); manlo <= conv_std_logic_vector(91276680,28); exponent <= conv_std_logic_vector(1399,11); WHEN "0100000110" => manhi <= conv_std_logic_vector(16455496,24); manlo <= conv_std_logic_vector(110068760,28); exponent <= conv_std_logic_vector(1400,11); WHEN "0100000111" => manhi <= conv_std_logic_vector(5806753,24); manlo <= conv_std_logic_vector(151304445,28); exponent <= conv_std_logic_vector(1402,11); WHEN "0100001000" => manhi <= conv_std_logic_vector(13917581,24); manlo <= conv_std_logic_vector(10650184,28); exponent <= conv_std_logic_vector(1403,11); WHEN "0100001001" => manhi <= conv_std_logic_vector(4082061,24); manlo <= conv_std_logic_vector(68530707,28); exponent <= conv_std_logic_vector(1405,11); WHEN "0100001010" => manhi <= conv_std_logic_vector(11573481,24); manlo <= conv_std_logic_vector(42662756,28); exponent <= conv_std_logic_vector(1406,11); WHEN "0100001011" => manhi <= conv_std_logic_vector(2489080,24); manlo <= conv_std_logic_vector(61154162,28); exponent <= conv_std_logic_vector(1408,11); WHEN "0100001100" => manhi <= conv_std_logic_vector(9408395,24); manlo <= conv_std_logic_vector(125867240,28); exponent <= conv_std_logic_vector(1409,11); WHEN "0100001101" => manhi <= conv_std_logic_vector(1017751,24); manlo <= conv_std_logic_vector(256555705,28); exponent <= conv_std_logic_vector(1411,11); WHEN "0100001110" => manhi <= conv_std_logic_vector(7408653,24); manlo <= conv_std_logic_vector(4309896,28); exponent <= conv_std_logic_vector(1412,11); WHEN "0100001111" => manhi <= conv_std_logic_vector(16094788,24); manlo <= conv_std_logic_vector(33800670,28); exponent <= conv_std_logic_vector(1413,11); WHEN "0100010000" => manhi <= conv_std_logic_vector(5561626,24); manlo <= conv_std_logic_vector(233573192,28); exponent <= conv_std_logic_vector(1415,11); WHEN "0100010001" => manhi <= conv_std_logic_vector(13584419,24); manlo <= conv_std_logic_vector(86257801,28); exponent <= conv_std_logic_vector(1416,11); WHEN "0100010010" => manhi <= conv_std_logic_vector(3855654,24); manlo <= conv_std_logic_vector(105782775,28); exponent <= conv_std_logic_vector(1418,11); WHEN "0100010011" => manhi <= conv_std_logic_vector(11265762,24); manlo <= conv_std_logic_vector(88738762,28); exponent <= conv_std_logic_vector(1419,11); WHEN "0100010100" => manhi <= conv_std_logic_vector(2279963,24); manlo <= conv_std_logic_vector(161858527,28); exponent <= conv_std_logic_vector(1421,11); WHEN "0100010101" => manhi <= conv_std_logic_vector(9124176,24); manlo <= conv_std_logic_vector(136423424,28); exponent <= conv_std_logic_vector(1422,11); WHEN "0100010110" => manhi <= conv_std_logic_vector(824605,24); manlo <= conv_std_logic_vector(39384255,28); exponent <= conv_std_logic_vector(1424,11); WHEN "0100010111" => manhi <= conv_std_logic_vector(7146139,24); manlo <= conv_std_logic_vector(76626123,28); exponent <= conv_std_logic_vector(1425,11); WHEN "0100011000" => manhi <= conv_std_logic_vector(15737994,24); manlo <= conv_std_logic_vector(261485765,28); exponent <= conv_std_logic_vector(1426,11); WHEN "0100011001" => manhi <= conv_std_logic_vector(5319160,24); manlo <= conv_std_logic_vector(210684009,28); exponent <= conv_std_logic_vector(1428,11); WHEN "0100011010" => manhi <= conv_std_logic_vector(13254873,24); manlo <= conv_std_logic_vector(199859160,28); exponent <= conv_std_logic_vector(1429,11); WHEN "0100011011" => manhi <= conv_std_logic_vector(3631704,24); manlo <= conv_std_logic_vector(256571707,28); exponent <= conv_std_logic_vector(1431,11); WHEN "0100011100" => manhi <= conv_std_logic_vector(10961383,24); manlo <= conv_std_logic_vector(130542749,28); exponent <= conv_std_logic_vector(1432,11); WHEN "0100011101" => manhi <= conv_std_logic_vector(2073116,24); manlo <= conv_std_logic_vector(196665136,28); exponent <= conv_std_logic_vector(1434,11); WHEN "0100011110" => manhi <= conv_std_logic_vector(8843042,24); manlo <= conv_std_logic_vector(124490661,28); exponent <= conv_std_logic_vector(1435,11); WHEN "0100011111" => manhi <= conv_std_logic_vector(633554,24); manlo <= conv_std_logic_vector(202834752,28); exponent <= conv_std_logic_vector(1437,11); WHEN "0100100000" => manhi <= conv_std_logic_vector(6886474,24); manlo <= conv_std_logic_vector(236822279,28); exponent <= conv_std_logic_vector(1438,11); WHEN "0100100001" => manhi <= conv_std_logic_vector(15385074,24); manlo <= conv_std_logic_vector(123405487,28); exponent <= conv_std_logic_vector(1439,11); WHEN "0100100010" => manhi <= conv_std_logic_vector(5079326,24); manlo <= conv_std_logic_vector(115311954,28); exponent <= conv_std_logic_vector(1441,11); WHEN "0100100011" => manhi <= conv_std_logic_vector(12928905,24); manlo <= conv_std_logic_vector(16004876,28); exponent <= conv_std_logic_vector(1442,11); WHEN "0100100100" => manhi <= conv_std_logic_vector(3410186,24); manlo <= conv_std_logic_vector(71831800,28); exponent <= conv_std_logic_vector(1444,11); WHEN "0100100101" => manhi <= conv_std_logic_vector(10660308,24); manlo <= conv_std_logic_vector(100367284,28); exponent <= conv_std_logic_vector(1445,11); WHEN "0100100110" => manhi <= conv_std_logic_vector(1868514,24); manlo <= conv_std_logic_vector(263299419,28); exponent <= conv_std_logic_vector(1447,11); WHEN "0100100111" => manhi <= conv_std_logic_vector(8564959,24); manlo <= conv_std_logic_vector(228656810,28); exponent <= conv_std_logic_vector(1448,11); WHEN "0100101000" => manhi <= conv_std_logic_vector(444578,24); manlo <= conv_std_logic_vector(7489141,28); exponent <= conv_std_logic_vector(1450,11); WHEN "0100101001" => manhi <= conv_std_logic_vector(6629628,24); manlo <= conv_std_logic_vector(236156491,28); exponent <= conv_std_logic_vector(1451,11); WHEN "0100101010" => manhi <= conv_std_logic_vector(15035984,24); manlo <= conv_std_logic_vector(147396312,28); exponent <= conv_std_logic_vector(1452,11); WHEN "0100101011" => manhi <= conv_std_logic_vector(4842095,24); manlo <= conv_std_logic_vector(64271882,28); exponent <= conv_std_logic_vector(1454,11); WHEN "0100101100" => manhi <= conv_std_logic_vector(12606474,24); manlo <= conv_std_logic_vector(118909770,28); exponent <= conv_std_logic_vector(1455,11); WHEN "0100101101" => manhi <= conv_std_logic_vector(3191071,24); manlo <= conv_std_logic_vector(253953386,28); exponent <= conv_std_logic_vector(1457,11); WHEN "0100101110" => manhi <= conv_std_logic_vector(10362501,24); manlo <= conv_std_logic_vector(36129498,28); exponent <= conv_std_logic_vector(1458,11); WHEN "0100101111" => manhi <= conv_std_logic_vector(1666133,24); manlo <= conv_std_logic_vector(262830684,28); exponent <= conv_std_logic_vector(1460,11); WHEN "0100110000" => manhi <= conv_std_logic_vector(8289895,24); manlo <= conv_std_logic_vector(148197046,28); exponent <= conv_std_logic_vector(1461,11); WHEN "0100110001" => manhi <= conv_std_logic_vector(257652,24); manlo <= conv_std_logic_vector(122404338,28); exponent <= conv_std_logic_vector(1463,11); WHEN "0100110010" => manhi <= conv_std_logic_vector(6375570,24); manlo <= conv_std_logic_vector(184430245,28); exponent <= conv_std_logic_vector(1464,11); WHEN "0100110011" => manhi <= conv_std_logic_vector(14690683,24); manlo <= conv_std_logic_vector(178457687,28); exponent <= conv_std_logic_vector(1465,11); WHEN "0100110100" => manhi <= conv_std_logic_vector(4607438,24); manlo <= conv_std_logic_vector(257605193,28); exponent <= conv_std_logic_vector(1467,11); WHEN "0100110101" => manhi <= conv_std_logic_vector(12287543,24); manlo <= conv_std_logic_vector(132163446,28); exponent <= conv_std_logic_vector(1468,11); WHEN "0100110110" => manhi <= conv_std_logic_vector(2974335,24); manlo <= conv_std_logic_vector(240020217,28); exponent <= conv_std_logic_vector(1470,11); WHEN "0100110111" => manhi <= conv_std_logic_vector(10067926,24); manlo <= conv_std_logic_vector(80224641,28); exponent <= conv_std_logic_vector(1471,11); WHEN "0100111000" => manhi <= conv_std_logic_vector(1465949,24); manlo <= conv_std_logic_vector(167328478,28); exponent <= conv_std_logic_vector(1473,11); WHEN "0100111001" => manhi <= conv_std_logic_vector(8017816,24); manlo <= conv_std_logic_vector(215756784,28); exponent <= conv_std_logic_vector(1474,11); WHEN "0100111010" => manhi <= conv_std_logic_vector(72755,24); manlo <= conv_std_logic_vector(208473528,28); exponent <= conv_std_logic_vector(1476,11); WHEN "0100111011" => manhi <= conv_std_logic_vector(6124270,24); manlo <= conv_std_logic_vector(12139444,28); exponent <= conv_std_logic_vector(1477,11); WHEN "0100111100" => manhi <= conv_std_logic_vector(14349130,24); manlo <= conv_std_logic_vector(182729110,28); exponent <= conv_std_logic_vector(1478,11); WHEN "0100111101" => manhi <= conv_std_logic_vector(4375329,24); manlo <= conv_std_logic_vector(172370119,28); exponent <= conv_std_logic_vector(1480,11); WHEN "0100111110" => manhi <= conv_std_logic_vector(11972074,24); manlo <= conv_std_logic_vector(59679792,28); exponent <= conv_std_logic_vector(1481,11); WHEN "0100111111" => manhi <= conv_std_logic_vector(2759952,24); manlo <= conv_std_logic_vector(80023302,28); exponent <= conv_std_logic_vector(1483,11); WHEN "0101000000" => manhi <= conv_std_logic_vector(9776548,24); manlo <= conv_std_logic_vector(209956608,28); exponent <= conv_std_logic_vector(1484,11); WHEN "0101000001" => manhi <= conv_std_logic_vector(1267938,24); manlo <= conv_std_logic_vector(19091951,28); exponent <= conv_std_logic_vector(1486,11); WHEN "0101000010" => manhi <= conv_std_logic_vector(7748691,24); manlo <= conv_std_logic_vector(54127000,28); exponent <= conv_std_logic_vector(1487,11); WHEN "0101000011" => manhi <= conv_std_logic_vector(16556947,24); manlo <= conv_std_logic_vector(251347868,28); exponent <= conv_std_logic_vector(1488,11); WHEN "0101000100" => manhi <= conv_std_logic_vector(5875697,24); manlo <= conv_std_logic_vector(6377900,28); exponent <= conv_std_logic_vector(1490,11); WHEN "0101000101" => manhi <= conv_std_logic_vector(14011284,24); manlo <= conv_std_logic_vector(246175281,28); exponent <= conv_std_logic_vector(1491,11); WHEN "0101000110" => manhi <= conv_std_logic_vector(4145739,24); manlo <= conv_std_logic_vector(172360927,28); exponent <= conv_std_logic_vector(1493,11); WHEN "0101000111" => manhi <= conv_std_logic_vector(11660029,24); manlo <= conv_std_logic_vector(16047086,28); exponent <= conv_std_logic_vector(1494,11); WHEN "0101001000" => manhi <= conv_std_logic_vector(2547895,24); manlo <= conv_std_logic_vector(167600151,28); exponent <= conv_std_logic_vector(1496,11); WHEN "0101001001" => manhi <= conv_std_logic_vector(9488333,24); manlo <= conv_std_logic_vector(236416250,28); exponent <= conv_std_logic_vector(1497,11); WHEN "0101001010" => manhi <= conv_std_logic_vector(1072075,24); manlo <= conv_std_logic_vector(198323037,28); exponent <= conv_std_logic_vector(1499,11); WHEN "0101001011" => manhi <= conv_std_logic_vector(7482486,24); manlo <= conv_std_logic_vector(185820926,28); exponent <= conv_std_logic_vector(1500,11); WHEN "0101001100" => manhi <= conv_std_logic_vector(16195138,24); manlo <= conv_std_logic_vector(133160968,28); exponent <= conv_std_logic_vector(1501,11); WHEN "0101001101" => manhi <= conv_std_logic_vector(5629822,24); manlo <= conv_std_logic_vector(4574050,28); exponent <= conv_std_logic_vector(1503,11); WHEN "0101001110" => manhi <= conv_std_logic_vector(13677106,24); manlo <= conv_std_logic_vector(36414601,28); exponent <= conv_std_logic_vector(1504,11); WHEN "0101001111" => manhi <= conv_std_logic_vector(3918641,24); manlo <= conv_std_logic_vector(165046798,28); exponent <= conv_std_logic_vector(1506,11); WHEN "0101010000" => manhi <= conv_std_logic_vector(11351370,24); manlo <= conv_std_logic_vector(225326735,28); exponent <= conv_std_logic_vector(1507,11); WHEN "0101010001" => manhi <= conv_std_logic_vector(2338140,24); manlo <= conv_std_logic_vector(165476611,28); exponent <= conv_std_logic_vector(1509,11); WHEN "0101010010" => manhi <= conv_std_logic_vector(9203247,24); manlo <= conv_std_logic_vector(71807303,28); exponent <= conv_std_logic_vector(1510,11); WHEN "0101010011" => manhi <= conv_std_logic_vector(878339,24); manlo <= conv_std_logic_vector(80195176,28); exponent <= conv_std_logic_vector(1512,11); WHEN "0101010100" => manhi <= conv_std_logic_vector(7219171,24); manlo <= conv_std_logic_vector(153001068,28); exponent <= conv_std_logic_vector(1513,11); WHEN "0101010101" => manhi <= conv_std_logic_vector(15837256,24); manlo <= conv_std_logic_vector(37596960,28); exponent <= conv_std_logic_vector(1514,11); WHEN "0101010110" => manhi <= conv_std_logic_vector(5386615,24); manlo <= conv_std_logic_vector(198850796,28); exponent <= conv_std_logic_vector(1516,11); WHEN "0101010111" => manhi <= conv_std_logic_vector(13346554,24); manlo <= conv_std_logic_vector(143609986,28); exponent <= conv_std_logic_vector(1517,11); WHEN "0101011000" => manhi <= conv_std_logic_vector(3694008,24); manlo <= conv_std_logic_vector(137568494,28); exponent <= conv_std_logic_vector(1519,11); WHEN "0101011001" => manhi <= conv_std_logic_vector(11046062,24); manlo <= conv_std_logic_vector(214558683,28); exponent <= conv_std_logic_vector(1520,11); WHEN "0101011010" => manhi <= conv_std_logic_vector(2130662,24); manlo <= conv_std_logic_vector(78401205,28); exponent <= conv_std_logic_vector(1522,11); WHEN "0101011011" => manhi <= conv_std_logic_vector(8921254,24); manlo <= conv_std_logic_vector(265219821,28); exponent <= conv_std_logic_vector(1523,11); WHEN "0101011100" => manhi <= conv_std_logic_vector(686705,24); manlo <= conv_std_logic_vector(181591149,28); exponent <= conv_std_logic_vector(1525,11); WHEN "0101011101" => manhi <= conv_std_logic_vector(6958714,24); manlo <= conv_std_logic_vector(127078273,28); exponent <= conv_std_logic_vector(1526,11); WHEN "0101011110" => manhi <= conv_std_logic_vector(15483258,24); manlo <= conv_std_logic_vector(65420394,28); exponent <= conv_std_logic_vector(1527,11); WHEN "0101011111" => manhi <= conv_std_logic_vector(5146049,24); manlo <= conv_std_logic_vector(61347424,28); exponent <= conv_std_logic_vector(1529,11); WHEN "0101100000" => manhi <= conv_std_logic_vector(13019590,24); manlo <= conv_std_logic_vector(200148168,28); exponent <= conv_std_logic_vector(1530,11); WHEN "0101100001" => manhi <= conv_std_logic_vector(3471813,24); manlo <= conv_std_logic_vector(155873600,28); exponent <= conv_std_logic_vector(1532,11); WHEN "0101100010" => manhi <= conv_std_logic_vector(10744068,24); manlo <= conv_std_logic_vector(154763366,28); exponent <= conv_std_logic_vector(1533,11); WHEN "0101100011" => manhi <= conv_std_logic_vector(1925435,24); manlo <= conv_std_logic_vector(252346422,28); exponent <= conv_std_logic_vector(1535,11); WHEN "0101100100" => manhi <= conv_std_logic_vector(8642323,24); manlo <= conv_std_logic_vector(122496413,28); exponent <= conv_std_logic_vector(1536,11); WHEN "0101100101" => manhi <= conv_std_logic_vector(497152,24); manlo <= conv_std_logic_vector(12881703,28); exponent <= conv_std_logic_vector(1538,11); WHEN "0101100110" => manhi <= conv_std_logic_vector(6701084,24); manlo <= conv_std_logic_vector(102402698,28); exponent <= conv_std_logic_vector(1539,11); WHEN "0101100111" => manhi <= conv_std_logic_vector(15133102,24); manlo <= conv_std_logic_vector(173151546,28); exponent <= conv_std_logic_vector(1540,11); WHEN "0101101000" => manhi <= conv_std_logic_vector(4908093,24); manlo <= conv_std_logic_vector(222341698,28); exponent <= conv_std_logic_vector(1542,11); WHEN "0101101001" => manhi <= conv_std_logic_vector(12696175,24); manlo <= conv_std_logic_vector(221558290,28); exponent <= conv_std_logic_vector(1543,11); WHEN "0101101010" => manhi <= conv_std_logic_vector(3252030,24); manlo <= conv_std_logic_vector(95425703,28); exponent <= conv_std_logic_vector(1545,11); WHEN "0101101011" => manhi <= conv_std_logic_vector(10445352,24); manlo <= conv_std_logic_vector(54472775,28); exponent <= conv_std_logic_vector(1546,11); WHEN "0101101100" => manhi <= conv_std_logic_vector(1722437,24); manlo <= conv_std_logic_vector(31541381,28); exponent <= conv_std_logic_vector(1548,11); WHEN "0101101101" => manhi <= conv_std_logic_vector(8366419,24); manlo <= conv_std_logic_vector(121077564,28); exponent <= conv_std_logic_vector(1549,11); WHEN "0101101110" => manhi <= conv_std_logic_vector(309655,24); manlo <= conv_std_logic_vector(224679493,28); exponent <= conv_std_logic_vector(1551,11); WHEN "0101101111" => manhi <= conv_std_logic_vector(6446250,24); manlo <= conv_std_logic_vector(163707479,28); exponent <= conv_std_logic_vector(1552,11); WHEN "0101110000" => manhi <= conv_std_logic_vector(14786747,24); manlo <= conv_std_logic_vector(171718440,28); exponent <= conv_std_logic_vector(1553,11); WHEN "0101110001" => manhi <= conv_std_logic_vector(4672721,24); manlo <= conv_std_logic_vector(53414720,28); exponent <= conv_std_logic_vector(1555,11); WHEN "0101110010" => manhi <= conv_std_logic_vector(12376271,24); manlo <= conv_std_logic_vector(68395953,28); exponent <= conv_std_logic_vector(1556,11); WHEN "0101110011" => manhi <= conv_std_logic_vector(3034632,24); manlo <= conv_std_logic_vector(177229210,28); exponent <= conv_std_logic_vector(1558,11); WHEN "0101110100" => manhi <= conv_std_logic_vector(10149878,24); manlo <= conv_std_logic_vector(27015960,28); exponent <= conv_std_logic_vector(1559,11); WHEN "0101110101" => manhi <= conv_std_logic_vector(1521641,24); manlo <= conv_std_logic_vector(173609470,28); exponent <= conv_std_logic_vector(1561,11); WHEN "0101110110" => manhi <= conv_std_logic_vector(8093510,24); manlo <= conv_std_logic_vector(29891310,28); exponent <= conv_std_logic_vector(1562,11); WHEN "0101110111" => manhi <= conv_std_logic_vector(124194,24); manlo <= conv_std_logic_vector(191198183,28); exponent <= conv_std_logic_vector(1564,11); WHEN "0101111000" => manhi <= conv_std_logic_vector(6194182,24); manlo <= conv_std_logic_vector(216692261,28); exponent <= conv_std_logic_vector(1565,11); WHEN "0101111001" => manhi <= conv_std_logic_vector(14444151,24); manlo <= conv_std_logic_vector(261994424,28); exponent <= conv_std_logic_vector(1566,11); WHEN "0101111010" => manhi <= conv_std_logic_vector(4439903,24); manlo <= conv_std_logic_vector(82463931,28); exponent <= conv_std_logic_vector(1568,11); WHEN "0101111011" => manhi <= conv_std_logic_vector(12059838,24); manlo <= conv_std_logic_vector(250318074,28); exponent <= conv_std_logic_vector(1569,11); WHEN "0101111100" => manhi <= conv_std_logic_vector(2819594,24); manlo <= conv_std_logic_vector(161686084,28); exponent <= conv_std_logic_vector(1571,11); WHEN "0101111101" => manhi <= conv_std_logic_vector(9857611,24); manlo <= conv_std_logic_vector(20946108,28); exponent <= conv_std_logic_vector(1572,11); WHEN "0101111110" => manhi <= conv_std_logic_vector(1323025,24); manlo <= conv_std_logic_vector(164440795,28); exponent <= conv_std_logic_vector(1574,11); WHEN "0101111111" => manhi <= conv_std_logic_vector(7823562,24); manlo <= conv_std_logic_vector(250479918,28); exponent <= conv_std_logic_vector(1575,11); WHEN "0110000000" => manhi <= conv_std_logic_vector(16658709,24); manlo <= conv_std_logic_vector(45608811,28); exponent <= conv_std_logic_vector(1576,11); WHEN "0110000001" => manhi <= conv_std_logic_vector(5944850,24); manlo <= conv_std_logic_vector(255488281,28); exponent <= conv_std_logic_vector(1578,11); WHEN "0110000010" => manhi <= conv_std_logic_vector(14105274,24); manlo <= conv_std_logic_vector(228172930,28); exponent <= conv_std_logic_vector(1579,11); WHEN "0110000011" => manhi <= conv_std_logic_vector(4209612,24); manlo <= conv_std_logic_vector(113758652,28); exponent <= conv_std_logic_vector(1581,11); WHEN "0110000100" => manhi <= conv_std_logic_vector(11746841,24); manlo <= conv_std_logic_vector(45816542,28); exponent <= conv_std_logic_vector(1582,11); WHEN "0110000101" => manhi <= conv_std_logic_vector(2606890,24); manlo <= conv_std_logic_vector(153074390,28); exponent <= conv_std_logic_vector(1584,11); WHEN "0110000110" => manhi <= conv_std_logic_vector(9568516,24); manlo <= conv_std_logic_vector(87350878,28); exponent <= conv_std_logic_vector(1585,11); WHEN "0110000111" => manhi <= conv_std_logic_vector(1126565,24); manlo <= conv_std_logic_vector(96475766,28); exponent <= conv_std_logic_vector(1587,11); WHEN "0110001000" => manhi <= conv_std_logic_vector(7556545,24); manlo <= conv_std_logic_vector(205347948,28); exponent <= conv_std_logic_vector(1588,11); WHEN "0110001001" => manhi <= conv_std_logic_vector(16295795,24); manlo <= conv_std_logic_vector(56881285,28); exponent <= conv_std_logic_vector(1589,11); WHEN "0110001010" => manhi <= conv_std_logic_vector(5698225,24); manlo <= conv_std_logic_vector(93263076,28); exponent <= conv_std_logic_vector(1591,11); WHEN "0110001011" => manhi <= conv_std_logic_vector(13770075,24); manlo <= conv_std_logic_vector(241769289,28); exponent <= conv_std_logic_vector(1592,11); WHEN "0110001100" => manhi <= conv_std_logic_vector(3981821,24); manlo <= conv_std_logic_vector(32359920,28); exponent <= conv_std_logic_vector(1594,11); WHEN "0110001101" => manhi <= conv_std_logic_vector(11437240,24); manlo <= conv_std_logic_vector(185367850,28); exponent <= conv_std_logic_vector(1595,11); WHEN "0110001110" => manhi <= conv_std_logic_vector(2396495,24); manlo <= conv_std_logic_vector(61858550,28); exponent <= conv_std_logic_vector(1597,11); WHEN "0110001111" => manhi <= conv_std_logic_vector(9282559,24); manlo <= conv_std_logic_vector(110304027,28); exponent <= conv_std_logic_vector(1598,11); WHEN "0110010000" => manhi <= conv_std_logic_vector(932237,24); manlo <= conv_std_logic_vector(131077892,28); exponent <= conv_std_logic_vector(1600,11); WHEN "0110010001" => manhi <= conv_std_logic_vector(7292426,24); manlo <= conv_std_logic_vector(215982528,28); exponent <= conv_std_logic_vector(1601,11); WHEN "0110010010" => manhi <= conv_std_logic_vector(15936820,24); manlo <= conv_std_logic_vector(87676082,28); exponent <= conv_std_logic_vector(1602,11); WHEN "0110010011" => manhi <= conv_std_logic_vector(5454276,24); manlo <= conv_std_logic_vector(166577430,28); exponent <= conv_std_logic_vector(1604,11); WHEN "0110010100" => manhi <= conv_std_logic_vector(13438515,24); manlo <= conv_std_logic_vector(55023964,28); exponent <= conv_std_logic_vector(1605,11); WHEN "0110010101" => manhi <= conv_std_logic_vector(3756502,24); manlo <= conv_std_logic_vector(71679026,28); exponent <= conv_std_logic_vector(1607,11); WHEN "0110010110" => manhi <= conv_std_logic_vector(11131000,24); manlo <= conv_std_logic_vector(165886683,28); exponent <= conv_std_logic_vector(1608,11); WHEN "0110010111" => manhi <= conv_std_logic_vector(2188383,24); manlo <= conv_std_logic_vector(140750309,28); exponent <= conv_std_logic_vector(1610,11); WHEN "0110011000" => manhi <= conv_std_logic_vector(8999706,24); manlo <= conv_std_logic_vector(74200045,28); exponent <= conv_std_logic_vector(1611,11); WHEN "0110011001" => manhi <= conv_std_logic_vector(740018,24); manlo <= conv_std_logic_vector(229350227,28); exponent <= conv_std_logic_vector(1613,11); WHEN "0110011010" => manhi <= conv_std_logic_vector(7031174,24); manlo <= conv_std_logic_vector(159659309,28); exponent <= conv_std_logic_vector(1614,11); WHEN "0110011011" => manhi <= conv_std_logic_vector(15581741,24); manlo <= conv_std_logic_vector(203828183,28); exponent <= conv_std_logic_vector(1615,11); WHEN "0110011100" => manhi <= conv_std_logic_vector(5212975,24); manlo <= conv_std_logic_vector(192268981,28); exponent <= conv_std_logic_vector(1617,11); WHEN "0110011101" => manhi <= conv_std_logic_vector(13110553,24); manlo <= conv_std_logic_vector(73367990,28); exponent <= conv_std_logic_vector(1618,11); WHEN "0110011110" => manhi <= conv_std_logic_vector(3533629,24); manlo <= conv_std_logic_vector(7303751,28); exponent <= conv_std_logic_vector(1620,11); WHEN "0110011111" => manhi <= conv_std_logic_vector(10828084,24); manlo <= conv_std_logic_vector(128595197,28); exponent <= conv_std_logic_vector(1621,11); WHEN "0110100000" => manhi <= conv_std_logic_vector(1982530,24); manlo <= conv_std_logic_vector(178601213,28); exponent <= conv_std_logic_vector(1623,11); WHEN "0110100001" => manhi <= conv_std_logic_vector(8719923,24); manlo <= conv_std_logic_vector(62665264,28); exponent <= conv_std_logic_vector(1624,11); WHEN "0110100010" => manhi <= conv_std_logic_vector(549886,24); manlo <= conv_std_logic_vector(151395401,28); exponent <= conv_std_logic_vector(1626,11); WHEN "0110100011" => manhi <= conv_std_logic_vector(6772758,24); manlo <= conv_std_logic_vector(5307652,28); exponent <= conv_std_logic_vector(1627,11); WHEN "0110100100" => manhi <= conv_std_logic_vector(15230517,24); manlo <= conv_std_logic_vector(58871965,28); exponent <= conv_std_logic_vector(1628,11); WHEN "0110100101" => manhi <= conv_std_logic_vector(4974293,24); manlo <= conv_std_logic_vector(240265124,28); exponent <= conv_std_logic_vector(1630,11); WHEN "0110100110" => manhi <= conv_std_logic_vector(12786151,24); manlo <= conv_std_logic_vector(11983156,28); exponent <= conv_std_logic_vector(1631,11); WHEN "0110100111" => manhi <= conv_std_logic_vector(3313174,24); manlo <= conv_std_logic_vector(229882212,28); exponent <= conv_std_logic_vector(1633,11); WHEN "0110101000" => manhi <= conv_std_logic_vector(10528456,24); manlo <= conv_std_logic_vector(52550536,28); exponent <= conv_std_logic_vector(1634,11); WHEN "0110101001" => manhi <= conv_std_logic_vector(1778912,24); manlo <= conv_std_logic_vector(36481057,28); exponent <= conv_std_logic_vector(1636,11); WHEN "0110101010" => manhi <= conv_std_logic_vector(8443176,24); manlo <= conv_std_logic_vector(257480801,28); exponent <= conv_std_logic_vector(1637,11); WHEN "0110101011" => manhi <= conv_std_logic_vector(361817,24); manlo <= conv_std_logic_vector(260890045,28); exponent <= conv_std_logic_vector(1639,11); WHEN "0110101100" => manhi <= conv_std_logic_vector(6517146,24); manlo <= conv_std_logic_vector(80951272,28); exponent <= conv_std_logic_vector(1640,11); WHEN "0110101101" => manhi <= conv_std_logic_vector(14883104,24); manlo <= conv_std_logic_vector(234866389,28); exponent <= conv_std_logic_vector(1641,11); WHEN "0110101110" => manhi <= conv_std_logic_vector(4738202,24); manlo <= conv_std_logic_vector(195793257,28); exponent <= conv_std_logic_vector(1643,11); WHEN "0110101111" => manhi <= conv_std_logic_vector(12465269,24); manlo <= conv_std_logic_vector(236730454,28); exponent <= conv_std_logic_vector(1644,11); WHEN "0110110000" => manhi <= conv_std_logic_vector(3095113,24); manlo <= conv_std_logic_vector(133661452,28); exponent <= conv_std_logic_vector(1646,11); WHEN "0110110001" => manhi <= conv_std_logic_vector(10232080,24); manlo <= conv_std_logic_vector(21926822,28); exponent <= conv_std_logic_vector(1647,11); WHEN "0110110010" => manhi <= conv_std_logic_vector(1577503,24); manlo <= conv_std_logic_vector(183764948,28); exponent <= conv_std_logic_vector(1649,11); WHEN "0110110011" => manhi <= conv_std_logic_vector(8169434,24); manlo <= conv_std_logic_vector(132210812,28); exponent <= conv_std_logic_vector(1650,11); WHEN "0110110100" => manhi <= conv_std_logic_vector(175790,24); manlo <= conv_std_logic_vector(182183516,28); exponent <= conv_std_logic_vector(1652,11); WHEN "0110110101" => manhi <= conv_std_logic_vector(6264308,24); manlo <= conv_std_logic_vector(267417858,28); exponent <= conv_std_logic_vector(1653,11); WHEN "0110110110" => manhi <= conv_std_logic_vector(14539463,24); manlo <= conv_std_logic_vector(93573944,28); exponent <= conv_std_logic_vector(1654,11); WHEN "0110110111" => manhi <= conv_std_logic_vector(4504674,24); manlo <= conv_std_logic_vector(26907375,28); exponent <= conv_std_logic_vector(1656,11); WHEN "0110111000" => manhi <= conv_std_logic_vector(12147871,24); manlo <= conv_std_logic_vector(152302066,28); exponent <= conv_std_logic_vector(1657,11); WHEN "0110111001" => manhi <= conv_std_logic_vector(2879418,24); manlo <= conv_std_logic_vector(263131635,28); exponent <= conv_std_logic_vector(1659,11); WHEN "0110111010" => manhi <= conv_std_logic_vector(9938920,24); manlo <= conv_std_logic_vector(224874222,28); exponent <= conv_std_logic_vector(1660,11); WHEN "0110111011" => manhi <= conv_std_logic_vector(1378281,24); manlo <= conv_std_logic_vector(86745210,28); exponent <= conv_std_logic_vector(1662,11); WHEN "0110111100" => manhi <= conv_std_logic_vector(7898663,24); manlo <= conv_std_logic_vector(61761420,28); exponent <= conv_std_logic_vector(1663,11); WHEN "0110111101" => manhi <= conv_std_logic_vector(16760781,24); manlo <= conv_std_logic_vector(15082626,28); exponent <= conv_std_logic_vector(1664,11); WHEN "0110111110" => manhi <= conv_std_logic_vector(6014215,24); manlo <= conv_std_logic_vector(265801199,28); exponent <= conv_std_logic_vector(1666,11); WHEN "0110111111" => manhi <= conv_std_logic_vector(14199551,24); manlo <= conv_std_logic_vector(191056853,28); exponent <= conv_std_logic_vector(1667,11); WHEN "0111000000" => manhi <= conv_std_logic_vector(4273680,24); manlo <= conv_std_logic_vector(52024524,28); exponent <= conv_std_logic_vector(1669,11); WHEN "0111000001" => manhi <= conv_std_logic_vector(11833918,24); manlo <= conv_std_logic_vector(80047690,28); exponent <= conv_std_logic_vector(1670,11); WHEN "0111000010" => manhi <= conv_std_logic_vector(2666065,24); manlo <= conv_std_logic_vector(164712049,28); exponent <= conv_std_logic_vector(1672,11); WHEN "0111000011" => manhi <= conv_std_logic_vector(9648943,24); manlo <= conv_std_logic_vector(147084012,28); exponent <= conv_std_logic_vector(1673,11); WHEN "0111000100" => manhi <= conv_std_logic_vector(1181221,24); manlo <= conv_std_logic_vector(86912647,28); exponent <= conv_std_logic_vector(1675,11); WHEN "0111000101" => manhi <= conv_std_logic_vector(7630830,24); manlo <= conv_std_logic_vector(247596521,28); exponent <= conv_std_logic_vector(1676,11); WHEN "0111000110" => manhi <= conv_std_logic_vector(16396759,24); manlo <= conv_std_logic_vector(56002502,28); exponent <= conv_std_logic_vector(1677,11); WHEN "0111000111" => manhi <= conv_std_logic_vector(5766837,24); manlo <= conv_std_logic_vector(133369322,28); exponent <= conv_std_logic_vector(1679,11); WHEN "0111001000" => manhi <= conv_std_logic_vector(13863329,24); manlo <= conv_std_logic_vector(128884889,28); exponent <= conv_std_logic_vector(1680,11); WHEN "0111001001" => manhi <= conv_std_logic_vector(4045193,24); manlo <= conv_std_logic_vector(133729186,28); exponent <= conv_std_logic_vector(1682,11); WHEN "0111001010" => manhi <= conv_std_logic_vector(11523372,24); manlo <= conv_std_logic_vector(183024104,28); exponent <= conv_std_logic_vector(1683,11); WHEN "0111001011" => manhi <= conv_std_logic_vector(2455027,24); manlo <= conv_std_logic_vector(264977965,28); exponent <= conv_std_logic_vector(1685,11); WHEN "0111001100" => manhi <= conv_std_logic_vector(9362113,24); manlo <= conv_std_logic_vector(181285013,28); exponent <= conv_std_logic_vector(1686,11); WHEN "0111001101" => manhi <= conv_std_logic_vector(986300,24); manlo <= conv_std_logic_vector(58020653,28); exponent <= conv_std_logic_vector(1688,11); WHEN "0111001110" => manhi <= conv_std_logic_vector(7365905,24); manlo <= conv_std_logic_vector(179835810,28); exponent <= conv_std_logic_vector(1689,11); WHEN "0111001111" => manhi <= conv_std_logic_vector(16036688,24); manlo <= conv_std_logic_vector(123168298,28); exponent <= conv_std_logic_vector(1690,11); WHEN "0111010000" => manhi <= conv_std_logic_vector(5522144,24); manlo <= conv_std_logic_vector(14176725,28); exponent <= conv_std_logic_vector(1692,11); WHEN "0111010001" => manhi <= conv_std_logic_vector(13530756,24); manlo <= conv_std_logic_vector(163453775,28); exponent <= conv_std_logic_vector(1693,11); WHEN "0111010010" => manhi <= conv_std_logic_vector(3819186,24); manlo <= conv_std_logic_vector(214764608,28); exponent <= conv_std_logic_vector(1695,11); WHEN "0111010011" => manhi <= conv_std_logic_vector(11216197,24); manlo <= conv_std_logic_vector(196364225,28); exponent <= conv_std_logic_vector(1696,11); WHEN "0111010100" => manhi <= conv_std_logic_vector(2246280,24); manlo <= conv_std_logic_vector(259235483,28); exponent <= conv_std_logic_vector(1698,11); WHEN "0111010101" => manhi <= conv_std_logic_vector(9078397,24); manlo <= conv_std_logic_vector(15526664,28); exponent <= conv_std_logic_vector(1699,11); WHEN "0111010110" => manhi <= conv_std_logic_vector(793494,24); manlo <= conv_std_logic_vector(210641201,28); exponent <= conv_std_logic_vector(1701,11); WHEN "0111010111" => manhi <= conv_std_logic_vector(7103855,24); manlo <= conv_std_logic_vector(246847656,28); exponent <= conv_std_logic_vector(1702,11); WHEN "0111011000" => manhi <= conv_std_logic_vector(15680525,24); manlo <= conv_std_logic_vector(247378795,28); exponent <= conv_std_logic_vector(1703,11); WHEN "0111011001" => manhi <= conv_std_logic_vector(5280106,24); manlo <= conv_std_logic_vector(138122391,28); exponent <= conv_std_logic_vector(1705,11); WHEN "0111011010" => manhi <= conv_std_logic_vector(13201793,24); manlo <= conv_std_logic_vector(130963079,28); exponent <= conv_std_logic_vector(1706,11); WHEN "0111011011" => manhi <= conv_std_logic_vector(3595633,24); manlo <= conv_std_logic_vector(48727293,28); exponent <= conv_std_logic_vector(1708,11); WHEN "0111011100" => manhi <= conv_std_logic_vector(10912356,24); manlo <= conv_std_logic_vector(231400966,28); exponent <= conv_std_logic_vector(1709,11); WHEN "0111011101" => manhi <= conv_std_logic_vector(2039799,24); manlo <= conv_std_logic_vector(184459756,28); exponent <= conv_std_logic_vector(1711,11); WHEN "0111011110" => manhi <= conv_std_logic_vector(8797759,24); manlo <= conv_std_logic_vector(242699544,28); exponent <= conv_std_logic_vector(1712,11); WHEN "0111011111" => manhi <= conv_std_logic_vector(602782,24); manlo <= conv_std_logic_vector(17680793,28); exponent <= conv_std_logic_vector(1714,11); WHEN "0111100000" => manhi <= conv_std_logic_vector(6844650,24); manlo <= conv_std_logic_vector(123627565,28); exponent <= conv_std_logic_vector(1715,11); WHEN "0111100001" => manhi <= conv_std_logic_vector(15328229,24); manlo <= conv_std_logic_vector(47512453,28); exponent <= conv_std_logic_vector(1716,11); WHEN "0111100010" => manhi <= conv_std_logic_vector(5040696,24); manlo <= conv_std_logic_vector(14711664,28); exponent <= conv_std_logic_vector(1718,11); WHEN "0111100011" => manhi <= conv_std_logic_vector(12876400,24); manlo <= conv_std_logic_vector(251456186,28); exponent <= conv_std_logic_vector(1719,11); WHEN "0111100100" => manhi <= conv_std_logic_vector(3374506,24); manlo <= conv_std_logic_vector(4512772,28); exponent <= conv_std_logic_vector(1721,11); WHEN "0111100101" => manhi <= conv_std_logic_vector(10611813,24); manlo <= conv_std_logic_vector(237626642,28); exponent <= conv_std_logic_vector(1722,11); WHEN "0111100110" => manhi <= conv_std_logic_vector(1835559,24); manlo <= conv_std_logic_vector(150064655,28); exponent <= conv_std_logic_vector(1724,11); WHEN "0111100111" => manhi <= conv_std_logic_vector(8520168,24); manlo <= conv_std_logic_vector(211971382,28); exponent <= conv_std_logic_vector(1725,11); WHEN "0111101000" => manhi <= conv_std_logic_vector(414139,24); manlo <= conv_std_logic_vector(92694471,28); exponent <= conv_std_logic_vector(1727,11); WHEN "0111101001" => manhi <= conv_std_logic_vector(6588258,24); manlo <= conv_std_logic_vector(112977613,28); exponent <= conv_std_logic_vector(1728,11); WHEN "0111101010" => manhi <= conv_std_logic_vector(14979756,24); manlo <= conv_std_logic_vector(71348470,28); exponent <= conv_std_logic_vector(1729,11); WHEN "0111101011" => manhi <= conv_std_logic_vector(4803884,24); manlo <= conv_std_logic_vector(42747344,28); exponent <= conv_std_logic_vector(1731,11); WHEN "0111101100" => manhi <= conv_std_logic_vector(12554540,24); manlo <= conv_std_logic_vector(53825836,28); exponent <= conv_std_logic_vector(1732,11); WHEN "0111101101" => manhi <= conv_std_logic_vector(3155778,24); manlo <= conv_std_logic_vector(260157975,28); exponent <= conv_std_logic_vector(1734,11); WHEN "0111101110" => manhi <= conv_std_logic_vector(10314533,24); manlo <= conv_std_logic_vector(1535990,28); exponent <= conv_std_logic_vector(1735,11); WHEN "0111101111" => manhi <= conv_std_logic_vector(1633536,24); manlo <= conv_std_logic_vector(68681060,28); exponent <= conv_std_logic_vector(1737,11); WHEN "0111110000" => manhi <= conv_std_logic_vector(8245590,24); manlo <= conv_std_logic_vector(175202070,28); exponent <= conv_std_logic_vector(1738,11); WHEN "0111110001" => manhi <= conv_std_logic_vector(227544,24); manlo <= conv_std_logic_vector(41675965,28); exponent <= conv_std_logic_vector(1740,11); WHEN "0111110010" => manhi <= conv_std_logic_vector(6334649,24); manlo <= conv_std_logic_vector(70777607,28); exponent <= conv_std_logic_vector(1741,11); WHEN "0111110011" => manhi <= conv_std_logic_vector(14635065,24); manlo <= conv_std_logic_vector(183612561,28); exponent <= conv_std_logic_vector(1742,11); WHEN "0111110100" => manhi <= conv_std_logic_vector(4569642,24); manlo <= conv_std_logic_vector(167240760,28); exponent <= conv_std_logic_vector(1744,11); WHEN "0111110101" => manhi <= conv_std_logic_vector(12236172,24); manlo <= conv_std_logic_vector(253623266,28); exponent <= conv_std_logic_vector(1745,11); WHEN "0111110110" => manhi <= conv_std_logic_vector(2939425,24); manlo <= conv_std_logic_vector(265128301,28); exponent <= conv_std_logic_vector(1747,11); WHEN "0111110111" => manhi <= conv_std_logic_vector(10020478,24); manlo <= conv_std_logic_vector(219223569,28); exponent <= conv_std_logic_vector(1748,11); WHEN "0111111000" => manhi <= conv_std_logic_vector(1433705,24); manlo <= conv_std_logic_vector(192250058,28); exponent <= conv_std_logic_vector(1750,11); WHEN "0111111001" => manhi <= conv_std_logic_vector(7973992,24); manlo <= conv_std_logic_vector(212144821,28); exponent <= conv_std_logic_vector(1751,11); WHEN "0111111010" => manhi <= conv_std_logic_vector(42974,24); manlo <= conv_std_logic_vector(72952107,28); exponent <= conv_std_logic_vector(1753,11); WHEN "0111111011" => manhi <= conv_std_logic_vector(6083792,24); manlo <= conv_std_logic_vector(210315148,28); exponent <= conv_std_logic_vector(1754,11); WHEN "0111111100" => manhi <= conv_std_logic_vector(14294116,24); manlo <= conv_std_logic_vector(101520926,28); exponent <= conv_std_logic_vector(1755,11); WHEN "0111111101" => manhi <= conv_std_logic_vector(4337943,24); manlo <= conv_std_logic_vector(146945490,28); exponent <= conv_std_logic_vector(1757,11); WHEN "0111111110" => manhi <= conv_std_logic_vector(11921261,24); manlo <= conv_std_logic_vector(67478049,28); exponent <= conv_std_logic_vector(1758,11); WHEN "0111111111" => manhi <= conv_std_logic_vector(2725421,24); manlo <= conv_std_logic_vector(81662013,28); exponent <= conv_std_logic_vector(1760,11); WHEN "1000000000" => manhi <= conv_std_logic_vector(9729616,24); manlo <= conv_std_logic_vector(79332654,28); exponent <= conv_std_logic_vector(1761,11); WHEN "1000000001" => manhi <= conv_std_logic_vector(1236044,24); manlo <= conv_std_logic_vector(37511845,28); exponent <= conv_std_logic_vector(1763,11); WHEN "1000000010" => manhi <= conv_std_logic_vector(7705342,24); manlo <= conv_std_logic_vector(229400607,28); exponent <= conv_std_logic_vector(1764,11); WHEN "1000000011" => manhi <= conv_std_logic_vector(16498031,24); manlo <= conv_std_logic_vector(113896411,28); exponent <= conv_std_logic_vector(1765,11); WHEN "1000000100" => manhi <= conv_std_logic_vector(5835659,24); manlo <= conv_std_logic_vector(27578100,28); exponent <= conv_std_logic_vector(1767,11); WHEN "1000000101" => manhi <= conv_std_logic_vector(13956867,24); manlo <= conv_std_logic_vector(198774093,28); exponent <= conv_std_logic_vector(1768,11); WHEN "1000000110" => manhi <= conv_std_logic_vector(4108759,24); manlo <= conv_std_logic_vector(90336304,28); exponent <= conv_std_logic_vector(1770,11); WHEN "1000000111" => manhi <= conv_std_logic_vector(11609767,24); manlo <= conv_std_logic_vector(164675818,28); exponent <= conv_std_logic_vector(1771,11); WHEN "1000001000" => manhi <= conv_std_logic_vector(2513739,24); manlo <= conv_std_logic_vector(115510945,28); exponent <= conv_std_logic_vector(1773,11); WHEN "1000001001" => manhi <= conv_std_logic_vector(9441910,24); manlo <= conv_std_logic_vector(214725537,28); exponent <= conv_std_logic_vector(1774,11); WHEN "1000001010" => manhi <= conv_std_logic_vector(1040527,24); manlo <= conv_std_logic_vector(264292986,28); exponent <= conv_std_logic_vector(1776,11); WHEN "1000001011" => manhi <= conv_std_logic_vector(7439608,24); manlo <= conv_std_logic_vector(227819416,28); exponent <= conv_std_logic_vector(1777,11); WHEN "1000001100" => manhi <= conv_std_logic_vector(16136861,24); manlo <= conv_std_logic_vector(124712281,28); exponent <= conv_std_logic_vector(1778,11); WHEN "1000001101" => manhi <= conv_std_logic_vector(5590218,24); manlo <= conv_std_logic_vector(179347558,28); exponent <= conv_std_logic_vector(1780,11); WHEN "1000001110" => manhi <= conv_std_logic_vector(13623279,24); manlo <= conv_std_logic_vector(162081347,28); exponent <= conv_std_logic_vector(1781,11); WHEN "1000001111" => manhi <= conv_std_logic_vector(3882062,24); manlo <= conv_std_logic_vector(186291443,28); exponent <= conv_std_logic_vector(1783,11); WHEN "1000010000" => manhi <= conv_std_logic_vector(11301654,24); manlo <= conv_std_logic_vector(250040022,28); exponent <= conv_std_logic_vector(1784,11); WHEN "1000010001" => manhi <= conv_std_logic_vector(2304355,24); manlo <= conv_std_logic_vector(41383777,28); exponent <= conv_std_logic_vector(1786,11); WHEN "1000010010" => manhi <= conv_std_logic_vector(9157328,24); manlo <= conv_std_logic_vector(17021400,28); exponent <= conv_std_logic_vector(1787,11); WHEN "1000010011" => manhi <= conv_std_logic_vector(847133,24); manlo <= conv_std_logic_vector(258834653,28); exponent <= conv_std_logic_vector(1789,11); WHEN "1000010100" => manhi <= conv_std_logic_vector(7176759,24); manlo <= conv_std_logic_vector(33041815,28); exponent <= conv_std_logic_vector(1790,11); WHEN "1000010101" => manhi <= conv_std_logic_vector(15779611,24); manlo <= conv_std_logic_vector(174007449,28); exponent <= conv_std_logic_vector(1791,11); WHEN "1000010110" => manhi <= conv_std_logic_vector(5347442,24); manlo <= conv_std_logic_vector(66333886,28); exponent <= conv_std_logic_vector(1793,11); WHEN "1000010111" => manhi <= conv_std_logic_vector(13293312,24); manlo <= conv_std_logic_vector(63618366,28); exponent <= conv_std_logic_vector(1794,11); WHEN "1000011000" => manhi <= conv_std_logic_vector(3657826,24); manlo <= conv_std_logic_vector(166348998,28); exponent <= conv_std_logic_vector(1796,11); WHEN "1000011001" => manhi <= conv_std_logic_vector(10996886,24); manlo <= conv_std_logic_vector(136487624,28); exponent <= conv_std_logic_vector(1797,11); WHEN "1000011010" => manhi <= conv_std_logic_vector(2097243,24); manlo <= conv_std_logic_vector(144317262,28); exponent <= conv_std_logic_vector(1799,11); WHEN "1000011011" => manhi <= conv_std_logic_vector(8875834,24); manlo <= conv_std_logic_vector(51419886,28); exponent <= conv_std_logic_vector(1800,11); WHEN "1000011100" => manhi <= conv_std_logic_vector(655839,24); manlo <= conv_std_logic_vector(12096311,28); exponent <= conv_std_logic_vector(1802,11); WHEN "1000011101" => manhi <= conv_std_logic_vector(6916762,24); manlo <= conv_std_logic_vector(99793437,28); exponent <= conv_std_logic_vector(1803,11); WHEN "1000011110" => manhi <= conv_std_logic_vector(15426239,24); manlo <= conv_std_logic_vector(114334116,28); exponent <= conv_std_logic_vector(1804,11); WHEN "1000011111" => manhi <= conv_std_logic_vector(5107300,24); manlo <= conv_std_logic_vector(248161218,28); exponent <= conv_std_logic_vector(1806,11); WHEN "1000100000" => manhi <= conv_std_logic_vector(12966926,24); manlo <= conv_std_logic_vector(91321506,28); exponent <= conv_std_logic_vector(1807,11); WHEN "1000100001" => manhi <= conv_std_logic_vector(3436024,24); manlo <= conv_std_logic_vector(109150055,28); exponent <= conv_std_logic_vector(1809,11); WHEN "1000100010" => manhi <= conv_std_logic_vector(10695426,24); manlo <= conv_std_logic_vector(12291314,28); exponent <= conv_std_logic_vector(1810,11); WHEN "1000100011" => manhi <= conv_std_logic_vector(1892379,24); manlo <= conv_std_logic_vector(245137096,28); exponent <= conv_std_logic_vector(1812,11); WHEN "1000100100" => manhi <= conv_std_logic_vector(8597395,24); manlo <= conv_std_logic_vector(176569250,28); exponent <= conv_std_logic_vector(1813,11); WHEN "1000100101" => manhi <= conv_std_logic_vector(466620,24); manlo <= conv_std_logic_vector(119019308,28); exponent <= conv_std_logic_vector(1815,11); WHEN "1000100110" => manhi <= conv_std_logic_vector(6659587,24); manlo <= conv_std_logic_vector(168706814,28); exponent <= conv_std_logic_vector(1816,11); WHEN "1000100111" => manhi <= conv_std_logic_vector(15076702,24); manlo <= conv_std_logic_vector(190651618,28); exponent <= conv_std_logic_vector(1817,11); WHEN "1000101000" => manhi <= conv_std_logic_vector(4869766,24); manlo <= conv_std_logic_vector(26523901,28); exponent <= conv_std_logic_vector(1819,11); WHEN "1000101001" => manhi <= conv_std_logic_vector(12644083,24); manlo <= conv_std_logic_vector(10760420,28); exponent <= conv_std_logic_vector(1820,11); WHEN "1000101010" => manhi <= conv_std_logic_vector(3216629,24); manlo <= conv_std_logic_vector(171149379,28); exponent <= conv_std_logic_vector(1822,11); WHEN "1000101011" => manhi <= conv_std_logic_vector(10397237,24); manlo <= conv_std_logic_vector(171483537,28); exponent <= conv_std_logic_vector(1823,11); WHEN "1000101100" => manhi <= conv_std_logic_vector(1689739,24); manlo <= conv_std_logic_vector(236540182,28); exponent <= conv_std_logic_vector(1825,11); WHEN "1000101101" => manhi <= conv_std_logic_vector(8321979,24); manlo <= conv_std_logic_vector(80365386,28); exponent <= conv_std_logic_vector(1826,11); WHEN "1000101110" => manhi <= conv_std_logic_vector(279455,24); manlo <= conv_std_logic_vector(167185714,28); exponent <= conv_std_logic_vector(1828,11); WHEN "1000101111" => manhi <= conv_std_logic_vector(6405204,24); manlo <= conv_std_logic_vector(70637708,28); exponent <= conv_std_logic_vector(1829,11); WHEN "1000110000" => manhi <= conv_std_logic_vector(14730959,24); manlo <= conv_std_logic_vector(233674466,28); exponent <= conv_std_logic_vector(1830,11); WHEN "1000110001" => manhi <= conv_std_logic_vector(4634809,24); manlo <= conv_std_logic_vector(128626627,28); exponent <= conv_std_logic_vector(1832,11); WHEN "1000110010" => manhi <= conv_std_logic_vector(12324743,24); manlo <= conv_std_logic_vector(237637056,28); exponent <= conv_std_logic_vector(1833,11); WHEN "1000110011" => manhi <= conv_std_logic_vector(2999616,24); manlo <= conv_std_logic_vector(48899908,28); exponent <= conv_std_logic_vector(1835,11); WHEN "1000110100" => manhi <= conv_std_logic_vector(10102285,24); manlo <= conv_std_logic_vector(207402206,28); exponent <= conv_std_logic_vector(1836,11); WHEN "1000110101" => manhi <= conv_std_logic_vector(1489299,24); manlo <= conv_std_logic_vector(82314533,28); exponent <= conv_std_logic_vector(1838,11); WHEN "1000110110" => manhi <= conv_std_logic_vector(8049552,24); manlo <= conv_std_logic_vector(84197942,28); exponent <= conv_std_logic_vector(1839,11); WHEN "1000110111" => manhi <= conv_std_logic_vector(94322,24); manlo <= conv_std_logic_vector(78275083,28); exponent <= conv_std_logic_vector(1841,11); WHEN "1000111000" => manhi <= conv_std_logic_vector(6153581,24); manlo <= conv_std_logic_vector(262556746,28); exponent <= conv_std_logic_vector(1842,11); WHEN "1000111001" => manhi <= conv_std_logic_vector(14388969,24); manlo <= conv_std_logic_vector(195412276,28); exponent <= conv_std_logic_vector(1843,11); WHEN "1000111010" => manhi <= conv_std_logic_vector(4402403,24); manlo <= conv_std_logic_vector(21925377,28); exponent <= conv_std_logic_vector(1845,11); WHEN "1000111011" => manhi <= conv_std_logic_vector(12008870,24); manlo <= conv_std_logic_vector(225943576,28); exponent <= conv_std_logic_vector(1846,11); WHEN "1000111100" => manhi <= conv_std_logic_vector(2784958,24); manlo <= conv_std_logic_vector(51959162,28); exponent <= conv_std_logic_vector(1848,11); WHEN "1000111101" => manhi <= conv_std_logic_vector(9810535,24); manlo <= conv_std_logic_vector(85297068,28); exponent <= conv_std_logic_vector(1849,11); WHEN "1000111110" => manhi <= conv_std_logic_vector(1291034,24); manlo <= conv_std_logic_vector(85003113,28); exponent <= conv_std_logic_vector(1851,11); WHEN "1000111111" => manhi <= conv_std_logic_vector(7780082,24); manlo <= conv_std_logic_vector(68159752,28); exponent <= conv_std_logic_vector(1852,11); WHEN "1001000000" => manhi <= conv_std_logic_vector(16599612,24); manlo <= conv_std_logic_vector(214703512,28); exponent <= conv_std_logic_vector(1853,11); WHEN "1001000001" => manhi <= conv_std_logic_vector(5904690,24); manlo <= conv_std_logic_vector(215968023,28); exponent <= conv_std_logic_vector(1855,11); WHEN "1001000010" => manhi <= conv_std_logic_vector(14050691,24); manlo <= conv_std_logic_vector(147853227,28); exponent <= conv_std_logic_vector(1856,11); WHEN "1001000011" => manhi <= conv_std_logic_vector(4172519,24); manlo <= conv_std_logic_vector(60716388,28); exponent <= conv_std_logic_vector(1858,11); WHEN "1001000100" => manhi <= conv_std_logic_vector(11696426,24); manlo <= conv_std_logic_vector(77359100,28); exponent <= conv_std_logic_vector(1859,11); WHEN "1001000101" => manhi <= conv_std_logic_vector(2572630,24); manlo <= conv_std_logic_vector(28321055,28); exponent <= conv_std_logic_vector(1861,11); WHEN "1001000110" => manhi <= conv_std_logic_vector(9521951,24); manlo <= conv_std_logic_vector(141206574,28); exponent <= conv_std_logic_vector(1862,11); WHEN "1001000111" => manhi <= conv_std_logic_vector(1094921,24); manlo <= conv_std_logic_vector(79834212,28); exponent <= conv_std_logic_vector(1864,11); WHEN "1001001000" => manhi <= conv_std_logic_vector(7513537,24); manlo <= conv_std_logic_vector(6880382,28); exponent <= conv_std_logic_vector(1865,11); WHEN "1001001001" => manhi <= conv_std_logic_vector(16237340,24); manlo <= conv_std_logic_vector(73707069,28); exponent <= conv_std_logic_vector(1866,11); WHEN "1001001010" => manhi <= conv_std_logic_vector(5658501,24); manlo <= conv_std_logic_vector(26563701,28); exponent <= conv_std_logic_vector(1868,11); WHEN "1001001011" => manhi <= conv_std_logic_vector(13716085,24); manlo <= conv_std_logic_vector(13226359,28); exponent <= conv_std_logic_vector(1869,11); WHEN "1001001100" => manhi <= conv_std_logic_vector(3945130,24); manlo <= conv_std_logic_vector(143073903,28); exponent <= conv_std_logic_vector(1871,11); WHEN "1001001101" => manhi <= conv_std_logic_vector(11387373,24); manlo <= conv_std_logic_vector(3175990,28); exponent <= conv_std_logic_vector(1872,11); WHEN "1001001110" => manhi <= conv_std_logic_vector(2362606,24); manlo <= conv_std_logic_vector(168904878,28); exponent <= conv_std_logic_vector(1874,11); WHEN "1001001111" => manhi <= conv_std_logic_vector(9236500,24); manlo <= conv_std_logic_vector(7105104,28); exponent <= conv_std_logic_vector(1875,11); WHEN "1001010000" => manhi <= conv_std_logic_vector(900936,24); manlo <= conv_std_logic_vector(239272854,28); exponent <= conv_std_logic_vector(1877,11); WHEN "1001010001" => manhi <= conv_std_logic_vector(7249884,24); manlo <= conv_std_logic_vector(236935482,28); exponent <= conv_std_logic_vector(1878,11); WHEN "1001010010" => manhi <= conv_std_logic_vector(15878999,24); manlo <= conv_std_logic_vector(230836932,28); exponent <= conv_std_logic_vector(1879,11); WHEN "1001010011" => manhi <= conv_std_logic_vector(5414983,24); manlo <= conv_std_logic_vector(144840810,28); exponent <= conv_std_logic_vector(1881,11); WHEN "1001010100" => manhi <= conv_std_logic_vector(13385110,24); manlo <= conv_std_logic_vector(99584369,28); exponent <= conv_std_logic_vector(1882,11); WHEN "1001010101" => manhi <= conv_std_logic_vector(3720209,24); manlo <= conv_std_logic_vector(246845719,28); exponent <= conv_std_logic_vector(1884,11); WHEN "1001010110" => manhi <= conv_std_logic_vector(11081674,24); manlo <= conv_std_logic_vector(54674652,28); exponent <= conv_std_logic_vector(1885,11); WHEN "1001010111" => manhi <= conv_std_logic_vector(2154862,24); manlo <= conv_std_logic_vector(201440422,28); exponent <= conv_std_logic_vector(1887,11); WHEN "1001011000" => manhi <= conv_std_logic_vector(8954146,24); manlo <= conv_std_logic_vector(220416825,28); exponent <= conv_std_logic_vector(1888,11); WHEN "1001011001" => manhi <= conv_std_logic_vector(709057,24); manlo <= conv_std_logic_vector(266967657,28); exponent <= conv_std_logic_vector(1890,11); WHEN "1001011010" => manhi <= conv_std_logic_vector(6989094,24); manlo <= conv_std_logic_vector(113654547,28); exponent <= conv_std_logic_vector(1891,11); WHEN "1001011011" => manhi <= conv_std_logic_vector(15524548,24); manlo <= conv_std_logic_vector(235342013,28); exponent <= conv_std_logic_vector(1892,11); WHEN "1001011100" => manhi <= conv_std_logic_vector(5174109,24); manlo <= conv_std_logic_vector(32986511,28); exponent <= conv_std_logic_vector(1894,11); WHEN "1001011101" => manhi <= conv_std_logic_vector(13057728,24); manlo <= conv_std_logic_vector(25787653,28); exponent <= conv_std_logic_vector(1895,11); WHEN "1001011110" => manhi <= conv_std_logic_vector(3497730,24); manlo <= conv_std_logic_vector(160351868,28); exponent <= conv_std_logic_vector(1897,11); WHEN "1001011111" => manhi <= conv_std_logic_vector(10779293,24); manlo <= conv_std_logic_vector(121946709,28); exponent <= conv_std_logic_vector(1898,11); WHEN "1001100000" => manhi <= conv_std_logic_vector(1949373,24); manlo <= conv_std_logic_vector(194974600,28); exponent <= conv_std_logic_vector(1900,11); WHEN "1001100001" => manhi <= conv_std_logic_vector(8674858,24); manlo <= conv_std_logic_vector(75445083,28); exponent <= conv_std_logic_vector(1901,11); WHEN "1001100010" => manhi <= conv_std_logic_vector(519261,24); manlo <= conv_std_logic_vector(202318540,28); exponent <= conv_std_logic_vector(1903,11); WHEN "1001100011" => manhi <= conv_std_logic_vector(6731134,24); manlo <= conv_std_logic_vector(157600610,28); exponent <= conv_std_logic_vector(1904,11); WHEN "1001100100" => manhi <= conv_std_logic_vector(15173945,24); manlo <= conv_std_logic_vector(29256816,28); exponent <= conv_std_logic_vector(1905,11); WHEN "1001100101" => manhi <= conv_std_logic_vector(4935849,24); manlo <= conv_std_logic_vector(42999013,28); exponent <= conv_std_logic_vector(1907,11); WHEN "1001100110" => manhi <= conv_std_logic_vector(12733899,24); manlo <= conv_std_logic_vector(62421287,28); exponent <= conv_std_logic_vector(1908,11); WHEN "1001100111" => manhi <= conv_std_logic_vector(3277666,24); manlo <= conv_std_logic_vector(18399062,28); exponent <= conv_std_logic_vector(1910,11); WHEN "1001101000" => manhi <= conv_std_logic_vector(10480194,24); manlo <= conv_std_logic_vector(201166396,28); exponent <= conv_std_logic_vector(1911,11); WHEN "1001101001" => manhi <= conv_std_logic_vector(1746115,24); manlo <= conv_std_logic_vector(22209480,28); exponent <= conv_std_logic_vector(1913,11); WHEN "1001101010" => manhi <= conv_std_logic_vector(8398601,24); manlo <= conv_std_logic_vector(38216343,28); exponent <= conv_std_logic_vector(1914,11); WHEN "1001101011" => manhi <= conv_std_logic_vector(331525,24); manlo <= conv_std_logic_vector(151310615,28); exponent <= conv_std_logic_vector(1916,11); WHEN "1001101100" => manhi <= conv_std_logic_vector(6475974,24); manlo <= conv_std_logic_vector(174528998,28); exponent <= conv_std_logic_vector(1917,11); WHEN "1001101101" => manhi <= conv_std_logic_vector(14827146,24); manlo <= conv_std_logic_vector(214487191,28); exponent <= conv_std_logic_vector(1918,11); WHEN "1001101110" => manhi <= conv_std_logic_vector(4700175,24); manlo <= conv_std_logic_vector(73593076,28); exponent <= conv_std_logic_vector(1920,11); WHEN "1001101111" => manhi <= conv_std_logic_vector(12413585,24); manlo <= conv_std_logic_vector(56806573,28); exponent <= conv_std_logic_vector(1921,11); WHEN "1001110000" => manhi <= conv_std_logic_vector(3059990,24); manlo <= conv_std_logic_vector(32998071,28); exponent <= conv_std_logic_vector(1923,11); WHEN "1001110001" => manhi <= conv_std_logic_vector(10184342,24); manlo <= conv_std_logic_vector(125003687,28); exponent <= conv_std_logic_vector(1924,11); WHEN "1001110010" => manhi <= conv_std_logic_vector(1545062,24); manlo <= conv_std_logic_vector(164026180,28); exponent <= conv_std_logic_vector(1926,11); WHEN "1001110011" => manhi <= conv_std_logic_vector(8125342,24); manlo <= conv_std_logic_vector(134803968,28); exponent <= conv_std_logic_vector(1927,11); WHEN "1001110100" => manhi <= conv_std_logic_vector(145827,24); manlo <= conv_std_logic_vector(17356019,28); exponent <= conv_std_logic_vector(1929,11); WHEN "1001110101" => manhi <= conv_std_logic_vector(6223584,24); manlo <= conv_std_logic_vector(59711433,28); exponent <= conv_std_logic_vector(1930,11); WHEN "1001110110" => manhi <= conv_std_logic_vector(14484112,24); manlo <= conv_std_logic_vector(172427100,28); exponent <= conv_std_logic_vector(1931,11); WHEN "1001110111" => manhi <= conv_std_logic_vector(4467059,24); manlo <= conv_std_logic_vector(106163660,28); exponent <= conv_std_logic_vector(1933,11); WHEN "1001111000" => manhi <= conv_std_logic_vector(12096747,24); manlo <= conv_std_logic_vector(237074316,28); exponent <= conv_std_logic_vector(1934,11); WHEN "1001111001" => manhi <= conv_std_logic_vector(2844676,24); manlo <= conv_std_logic_vector(224090291,28); exponent <= conv_std_logic_vector(1936,11); WHEN "1001111010" => manhi <= conv_std_logic_vector(9891701,24); manlo <= conv_std_logic_vector(98356275,28); exponent <= conv_std_logic_vector(1937,11); WHEN "1001111011" => manhi <= conv_std_logic_vector(1346192,24); manlo <= conv_std_logic_vector(98098154,28); exponent <= conv_std_logic_vector(1939,11); WHEN "1001111100" => manhi <= conv_std_logic_vector(7855049,24); manlo <= conv_std_logic_vector(218711727,28); exponent <= conv_std_logic_vector(1940,11); WHEN "1001111101" => manhi <= conv_std_logic_vector(16701504,24); manlo <= conv_std_logic_vector(74899902,28); exponent <= conv_std_logic_vector(1941,11); WHEN "1001111110" => manhi <= conv_std_logic_vector(5973933,24); manlo <= conv_std_logic_vector(65399866,28); exponent <= conv_std_logic_vector(1943,11); WHEN "1001111111" => manhi <= conv_std_logic_vector(14144801,24); manlo <= conv_std_logic_vector(210121699,28); exponent <= conv_std_logic_vector(1944,11); WHEN "1010000000" => manhi <= conv_std_logic_vector(4236473,24); manlo <= conv_std_logic_vector(203888522,28); exponent <= conv_std_logic_vector(1946,11); WHEN "1010000001" => manhi <= conv_std_logic_vector(11783349,24); manlo <= conv_std_logic_vector(137203293,28); exponent <= conv_std_logic_vector(1947,11); WHEN "1010000010" => manhi <= conv_std_logic_vector(2631700,24); manlo <= conv_std_logic_vector(150283410,28); exponent <= conv_std_logic_vector(1949,11); WHEN "1010000011" => manhi <= conv_std_logic_vector(9602236,24); manlo <= conv_std_logic_vector(160352104,28); exponent <= conv_std_logic_vector(1950,11); WHEN "1010000100" => manhi <= conv_std_logic_vector(1149480,24); manlo <= conv_std_logic_vector(177173803,28); exponent <= conv_std_logic_vector(1952,11); WHEN "1010000101" => manhi <= conv_std_logic_vector(7587690,24); manlo <= conv_std_logic_vector(238268718,28); exponent <= conv_std_logic_vector(1953,11); WHEN "1010000110" => manhi <= conv_std_logic_vector(16338125,24); manlo <= conv_std_logic_vector(220749839,28); exponent <= conv_std_logic_vector(1954,11); WHEN "1010000111" => manhi <= conv_std_logic_vector(5726991,24); manlo <= conv_std_logic_vector(262994505,28); exponent <= conv_std_logic_vector(1956,11); WHEN "1010001000" => manhi <= conv_std_logic_vector(13809173,24); manlo <= conv_std_logic_vector(216783842,28); exponent <= conv_std_logic_vector(1957,11); WHEN "1010001001" => manhi <= conv_std_logic_vector(4008390,24); manlo <= conv_std_logic_vector(242405077,28); exponent <= conv_std_logic_vector(1959,11); WHEN "1010001010" => manhi <= conv_std_logic_vector(11473352,24); manlo <= conv_std_logic_vector(206426515,28); exponent <= conv_std_logic_vector(1960,11); WHEN "1010001011" => manhi <= conv_std_logic_vector(2421035,24); manlo <= conv_std_logic_vector(250208807,28); exponent <= conv_std_logic_vector(1962,11); WHEN "1010001100" => manhi <= conv_std_logic_vector(9315913,24); manlo <= conv_std_logic_vector(183235034,28); exponent <= conv_std_logic_vector(1963,11); WHEN "1010001101" => manhi <= conv_std_logic_vector(954904,24); manlo <= conv_std_logic_vector(17706469,28); exponent <= conv_std_logic_vector(1965,11); WHEN "1010001110" => manhi <= conv_std_logic_vector(7323233,24); manlo <= conv_std_logic_vector(235600136,28); exponent <= conv_std_logic_vector(1966,11); WHEN "1010001111" => manhi <= conv_std_logic_vector(15978691,24); manlo <= conv_std_logic_vector(128873524,28); exponent <= conv_std_logic_vector(1967,11); WHEN "1010010000" => manhi <= conv_std_logic_vector(5482731,24); manlo <= conv_std_logic_vector(5222268,28); exponent <= conv_std_logic_vector(1969,11); WHEN "1010010001" => manhi <= conv_std_logic_vector(13477188,24); manlo <= conv_std_logic_vector(199372940,28); exponent <= conv_std_logic_vector(1970,11); WHEN "1010010010" => manhi <= conv_std_logic_vector(3782783,24); manlo <= conv_std_logic_vector(177367827,28); exponent <= conv_std_logic_vector(1972,11); WHEN "1010010011" => manhi <= conv_std_logic_vector(11166720,24); manlo <= conv_std_logic_vector(197425116,28); exponent <= conv_std_logic_vector(1973,11); WHEN "1010010100" => manhi <= conv_std_logic_vector(2212657,24); manlo <= conv_std_logic_vector(231097832,28); exponent <= conv_std_logic_vector(1975,11); WHEN "1010010101" => manhi <= conv_std_logic_vector(9032698,24); manlo <= conv_std_logic_vector(139698050,28); exponent <= conv_std_logic_vector(1976,11); WHEN "1010010110" => manhi <= conv_std_logic_vector(762439,24); manlo <= conv_std_logic_vector(109718127,28); exponent <= conv_std_logic_vector(1978,11); WHEN "1010010111" => manhi <= conv_std_logic_vector(7061647,24); manlo <= conv_std_logic_vector(77173752,28); exponent <= conv_std_logic_vector(1979,11); WHEN "1010011000" => manhi <= conv_std_logic_vector(15623158,24); manlo <= conv_std_logic_vector(118851961,28); exponent <= conv_std_logic_vector(1980,11); WHEN "1010011001" => manhi <= conv_std_logic_vector(5241121,24); manlo <= conv_std_logic_vector(72680114,28); exponent <= conv_std_logic_vector(1982,11); WHEN "1010011010" => manhi <= conv_std_logic_vector(13148807,24); manlo <= conv_std_logic_vector(12881486,28); exponent <= conv_std_logic_vector(1983,11); WHEN "1010011011" => manhi <= conv_std_logic_vector(3559625,24); manlo <= conv_std_logic_vector(43579850,28); exponent <= conv_std_logic_vector(1985,11); WHEN "1010011100" => manhi <= conv_std_logic_vector(10863416,24); manlo <= conv_std_logic_vector(238889758,28); exponent <= conv_std_logic_vector(1986,11); WHEN "1010011101" => manhi <= conv_std_logic_vector(2006541,24); manlo <= conv_std_logic_vector(141721451,28); exponent <= conv_std_logic_vector(1988,11); WHEN "1010011110" => manhi <= conv_std_logic_vector(8752557,24); manlo <= conv_std_logic_vector(101792997,28); exponent <= conv_std_logic_vector(1989,11); WHEN "1010011111" => manhi <= conv_std_logic_vector(572063,24); manlo <= conv_std_logic_vector(205445723,28); exponent <= conv_std_logic_vector(1991,11); WHEN "1010100000" => manhi <= conv_std_logic_vector(6802899,24); manlo <= conv_std_logic_vector(258099270,28); exponent <= conv_std_logic_vector(1992,11); WHEN "1010100001" => manhi <= conv_std_logic_vector(15271484,24); manlo <= conv_std_logic_vector(98124990,28); exponent <= conv_std_logic_vector(1993,11); WHEN "1010100010" => manhi <= conv_std_logic_vector(5002133,24); manlo <= conv_std_logic_vector(256985826,28); exponent <= conv_std_logic_vector(1995,11); WHEN "1010100011" => manhi <= conv_std_logic_vector(12823989,24); manlo <= conv_std_logic_vector(164377270,28); exponent <= conv_std_logic_vector(1996,11); WHEN "1010100100" => manhi <= conv_std_logic_vector(3338888,24); manlo <= conv_std_logic_vector(222569178,28); exponent <= conv_std_logic_vector(1998,11); WHEN "1010100101" => manhi <= conv_std_logic_vector(10563405,24); manlo <= conv_std_logic_vector(29046646,28); exponent <= conv_std_logic_vector(1999,11); WHEN "1010100110" => manhi <= conv_std_logic_vector(1802662,24); manlo <= conv_std_logic_vector(103161316,28); exponent <= conv_std_logic_vector(2001,11); WHEN "1010100111" => manhi <= conv_std_logic_vector(8475456,24); manlo <= conv_std_logic_vector(239852126,28); exponent <= conv_std_logic_vector(2002,11); WHEN "1010101000" => manhi <= conv_std_logic_vector(383754,24); manlo <= conv_std_logic_vector(123914668,28); exponent <= conv_std_logic_vector(2004,11); WHEN "1010101001" => manhi <= conv_std_logic_vector(6546961,24); manlo <= conv_std_logic_vector(22084044,28); exponent <= conv_std_logic_vector(2005,11); WHEN "1010101010" => manhi <= conv_std_logic_vector(14923627,24); manlo <= conv_std_logic_vector(97508377,28); exponent <= conv_std_logic_vector(2006,11); WHEN "1010101011" => manhi <= conv_std_logic_vector(4765740,24); manlo <= conv_std_logic_vector(165164368,28); exponent <= conv_std_logic_vector(2008,11); WHEN "1010101100" => manhi <= conv_std_logic_vector(12502697,24); manlo <= conv_std_logic_vector(201140216,28); exponent <= conv_std_logic_vector(2009,11); WHEN "1010101101" => manhi <= conv_std_logic_vector(3120548,24); manlo <= conv_std_logic_vector(99561759,28); exponent <= conv_std_logic_vector(2011,11); WHEN "1010101110" => manhi <= conv_std_logic_vector(10266649,24); manlo <= conv_std_logic_vector(176679877,28); exponent <= conv_std_logic_vector(2012,11); WHEN "1010101111" => manhi <= conv_std_logic_vector(1600996,24); manlo <= conv_std_logic_vector(39589446,28); exponent <= conv_std_logic_vector(2014,11); WHEN "1010110000" => manhi <= conv_std_logic_vector(8201364,24); manlo <= conv_std_logic_vector(16114999,28); exponent <= conv_std_logic_vector(2015,11); WHEN "1010110001" => manhi <= conv_std_logic_vector(197489,24); manlo <= conv_std_logic_vector(18649371,28); exponent <= conv_std_logic_vector(2017,11); WHEN "1010110010" => manhi <= conv_std_logic_vector(6293800,24); manlo <= conv_std_logic_vector(44802372,28); exponent <= conv_std_logic_vector(2018,11); WHEN "1010110011" => manhi <= conv_std_logic_vector(14579546,24); manlo <= conv_std_logic_vector(1419236,28); exponent <= conv_std_logic_vector(2019,11); WHEN "1010110100" => manhi <= conv_std_logic_vector(4531913,24); manlo <= conv_std_logic_vector(24044223,28); exponent <= conv_std_logic_vector(2021,11); WHEN "1010110101" => manhi <= conv_std_logic_vector(12184893,24); manlo <= conv_std_logic_vector(51602800,28); exponent <= conv_std_logic_vector(2022,11); WHEN "1010110110" => manhi <= conv_std_logic_vector(2904577,24); manlo <= conv_std_logic_vector(210124577,28); exponent <= conv_std_logic_vector(2024,11); WHEN "1010110111" => manhi <= conv_std_logic_vector(9973115,24); manlo <= conv_std_logic_vector(52505388,28); exponent <= conv_std_logic_vector(2025,11); WHEN "1010111000" => manhi <= conv_std_logic_vector(1401518,24); manlo <= conv_std_logic_vector(214362802,28); exponent <= conv_std_logic_vector(2027,11); WHEN "1010111001" => manhi <= conv_std_logic_vector(7930246,24); manlo <= conv_std_logic_vector(62721516,28); exponent <= conv_std_logic_vector(2028,11); WHEN "1010111010" => manhi <= conv_std_logic_vector(13245,24); manlo <= conv_std_logic_vector(108520727,28); exponent <= conv_std_logic_vector(2030,11); WHEN "1010111011" => manhi <= conv_std_logic_vector(6043387,24); manlo <= conv_std_logic_vector(17001813,28); exponent <= conv_std_logic_vector(2031,11); WHEN "1010111100" => manhi <= conv_std_logic_vector(14239199,24); manlo <= conv_std_logic_vector(83422350,28); exponent <= conv_std_logic_vector(2032,11); WHEN "1010111101" => manhi <= conv_std_logic_vector(4300623,24); manlo <= conv_std_logic_vector(142486326,28); exponent <= conv_std_logic_vector(2034,11); WHEN "1010111110" => manhi <= conv_std_logic_vector(11870538,24); manlo <= conv_std_logic_vector(24126621,28); exponent <= conv_std_logic_vector(2035,11); WHEN "1010111111" => manhi <= conv_std_logic_vector(2690951,24); manlo <= conv_std_logic_vector(91850592,28); exponent <= conv_std_logic_vector(2037,11); WHEN "1011000000" => manhi <= conv_std_logic_vector(9682766,24); manlo <= conv_std_logic_vector(203960059,28); exponent <= conv_std_logic_vector(2038,11); WHEN "1011000001" => manhi <= conv_std_logic_vector(1204206,24); manlo <= conv_std_logic_vector(155513539,28); exponent <= conv_std_logic_vector(2040,11); WHEN "1011000010" => manhi <= conv_std_logic_vector(7662071,24); manlo <= conv_std_logic_vector(33184566,28); exponent <= conv_std_logic_vector(2041,11); WHEN "1011000011" => manhi <= conv_std_logic_vector(16439219,24); manlo <= conv_std_logic_vector(11896414,28); exponent <= conv_std_logic_vector(2042,11); WHEN "1011000100" => manhi <= conv_std_logic_vector(5795691,24); manlo <= conv_std_logic_vector(254151921,28); exponent <= conv_std_logic_vector(2044,11); WHEN "1011000101" => manhi <= conv_std_logic_vector(13902546,24); manlo <= conv_std_logic_vector(199613595,28); exponent <= conv_std_logic_vector(2045,11); WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_explutpos IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_explutpos; ARCHITECTURE rtl OF dp_explutpos IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(1023,11); WHEN "0000000001" => manhi <= conv_std_logic_vector(6025384,24); manlo <= conv_std_logic_vector(185882474,28); exponent <= conv_std_logic_vector(1024,11); WHEN "0000000010" => manhi <= conv_std_logic_vector(14214731,24); manlo <= conv_std_logic_vector(148168110,28); exponent <= conv_std_logic_vector(1025,11); WHEN "0000000011" => manhi <= conv_std_logic_vector(4283995,24); manlo <= conv_std_logic_vector(258978054,28); exponent <= conv_std_logic_vector(1027,11); WHEN "0000000100" => manhi <= conv_std_logic_vector(11847938,24); manlo <= conv_std_logic_vector(237451864,28); exponent <= conv_std_logic_vector(1028,11); WHEN "0000000101" => manhi <= conv_std_logic_vector(2675593,24); manlo <= conv_std_logic_vector(158348175,28); exponent <= conv_std_logic_vector(1030,11); WHEN "0000000110" => manhi <= conv_std_logic_vector(9661893,24); manlo <= conv_std_logic_vector(110149775,28); exponent <= conv_std_logic_vector(1031,11); WHEN "0000000111" => manhi <= conv_std_logic_vector(1190021,24); manlo <= conv_std_logic_vector(179232170,28); exponent <= conv_std_logic_vector(1033,11); WHEN "0000001000" => manhi <= conv_std_logic_vector(7642791,24); manlo <= conv_std_logic_vector(222760046,28); exponent <= conv_std_logic_vector(1034,11); WHEN "0000001001" => manhi <= conv_std_logic_vector(16413015,24); manlo <= conv_std_logic_vector(205983618,28); exponent <= conv_std_logic_vector(1035,11); WHEN "0000001010" => manhi <= conv_std_logic_vector(5777884,24); manlo <= conv_std_logic_vector(261424480,28); exponent <= conv_std_logic_vector(1037,11); WHEN "0000001011" => manhi <= conv_std_logic_vector(13878344,24); manlo <= conv_std_logic_vector(149835647,28); exponent <= conv_std_logic_vector(1038,11); WHEN "0000001100" => manhi <= conv_std_logic_vector(4055397,24); manlo <= conv_std_logic_vector(80968858,28); exponent <= conv_std_logic_vector(1040,11); WHEN "0000001101" => manhi <= conv_std_logic_vector(11537241,24); manlo <= conv_std_logic_vector(23775573,28); exponent <= conv_std_logic_vector(1041,11); WHEN "0000001110" => manhi <= conv_std_logic_vector(2464452,24); manlo <= conv_std_logic_vector(146736599,28); exponent <= conv_std_logic_vector(1043,11); WHEN "0000001111" => manhi <= conv_std_logic_vector(9374922,24); manlo <= conv_std_logic_vector(263006855,28); exponent <= conv_std_logic_vector(1044,11); WHEN "0000010000" => manhi <= conv_std_logic_vector(995005,24); manlo <= conv_std_logic_vector(11010080,28); exponent <= conv_std_logic_vector(1046,11); WHEN "0000010001" => manhi <= conv_std_logic_vector(7377736,24); manlo <= conv_std_logic_vector(202286329,28); exponent <= conv_std_logic_vector(1047,11); WHEN "0000010010" => manhi <= conv_std_logic_vector(16052768,24); manlo <= conv_std_logic_vector(152649917,28); exponent <= conv_std_logic_vector(1048,11); WHEN "0000010011" => manhi <= conv_std_logic_vector(5533071,24); manlo <= conv_std_logic_vector(166536930,28); exponent <= conv_std_logic_vector(1050,11); WHEN "0000010100" => manhi <= conv_std_logic_vector(13545608,24); manlo <= conv_std_logic_vector(191424516,28); exponent <= conv_std_logic_vector(1051,11); WHEN "0000010101" => manhi <= conv_std_logic_vector(3829279,24); manlo <= conv_std_logic_vector(228519165,28); exponent <= conv_std_logic_vector(1053,11); WHEN "0000010110" => manhi <= conv_std_logic_vector(11229915,24); manlo <= conv_std_logic_vector(163853824,28); exponent <= conv_std_logic_vector(1054,11); WHEN "0000010111" => manhi <= conv_std_logic_vector(2255603,24); manlo <= conv_std_logic_vector(61996481,28); exponent <= conv_std_logic_vector(1056,11); WHEN "0000011000" => manhi <= conv_std_logic_vector(9091067,24); manlo <= conv_std_logic_vector(88563639,28); exponent <= conv_std_logic_vector(1057,11); WHEN "0000011001" => manhi <= conv_std_logic_vector(802105,24); manlo <= conv_std_logic_vector(34169545,28); exponent <= conv_std_logic_vector(1059,11); WHEN "0000011010" => manhi <= conv_std_logic_vector(7115558,24); manlo <= conv_std_logic_vector(157969244,28); exponent <= conv_std_logic_vector(1060,11); WHEN "0000011011" => manhi <= conv_std_logic_vector(15696431,24); manlo <= conv_std_logic_vector(133591837,28); exponent <= conv_std_logic_vector(1061,11); WHEN "0000011100" => manhi <= conv_std_logic_vector(5290915,24); manlo <= conv_std_logic_vector(127285146,28); exponent <= conv_std_logic_vector(1063,11); WHEN "0000011101" => manhi <= conv_std_logic_vector(13216484,24); manlo <= conv_std_logic_vector(103923798,28); exponent <= conv_std_logic_vector(1064,11); WHEN "0000011110" => manhi <= conv_std_logic_vector(3605616,24); manlo <= conv_std_logic_vector(183249133,28); exponent <= conv_std_logic_vector(1066,11); WHEN "0000011111" => manhi <= conv_std_logic_vector(10925925,24); manlo <= conv_std_logic_vector(227336045,28); exponent <= conv_std_logic_vector(1067,11); WHEN "0000100000" => manhi <= conv_std_logic_vector(2049020,24); manlo <= conv_std_logic_vector(206267948,28); exponent <= conv_std_logic_vector(1069,11); WHEN "0000100001" => manhi <= conv_std_logic_vector(8810292,24); manlo <= conv_std_logic_vector(175265666,28); exponent <= conv_std_logic_vector(1070,11); WHEN "0000100010" => manhi <= conv_std_logic_vector(611298,24); manlo <= conv_std_logic_vector(255467255,28); exponent <= conv_std_logic_vector(1072,11); WHEN "0000100011" => manhi <= conv_std_logic_vector(6856226,24); manlo <= conv_std_logic_vector(29134171,28); exponent <= conv_std_logic_vector(1073,11); WHEN "0000100100" => manhi <= conv_std_logic_vector(15343962,24); manlo <= conv_std_logic_vector(30543222,28); exponent <= conv_std_logic_vector(1074,11); WHEN "0000100101" => manhi <= conv_std_logic_vector(5051387,24); manlo <= conv_std_logic_vector(186253338,28); exponent <= conv_std_logic_vector(1076,11); WHEN "0000100110" => manhi <= conv_std_logic_vector(12890932,24); manlo <= conv_std_logic_vector(102222951,28); exponent <= conv_std_logic_vector(1077,11); WHEN "0000100111" => manhi <= conv_std_logic_vector(3384381,24); manlo <= conv_std_logic_vector(42116377,28); exponent <= conv_std_logic_vector(1079,11); WHEN "0000101000" => manhi <= conv_std_logic_vector(10625235,24); manlo <= conv_std_logic_vector(158954218,28); exponent <= conv_std_logic_vector(1080,11); WHEN "0000101001" => manhi <= conv_std_logic_vector(1844680,24); manlo <= conv_std_logic_vector(148858978,28); exponent <= conv_std_logic_vector(1082,11); WHEN "0000101010" => manhi <= conv_std_logic_vector(8532565,24); manlo <= conv_std_logic_vector(136319321,28); exponent <= conv_std_logic_vector(1083,11); WHEN "0000101011" => manhi <= conv_std_logic_vector(422563,24); manlo <= conv_std_logic_vector(211728497,28); exponent <= conv_std_logic_vector(1085,11); WHEN "0000101100" => manhi <= conv_std_logic_vector(6599708,24); manlo <= conv_std_logic_vector(114522162,28); exponent <= conv_std_logic_vector(1086,11); WHEN "0000101101" => manhi <= conv_std_logic_vector(14995318,24); manlo <= conv_std_logic_vector(117328318,28); exponent <= conv_std_logic_vector(1087,11); WHEN "0000101110" => manhi <= conv_std_logic_vector(4814459,24); manlo <= conv_std_logic_vector(201622499,28); exponent <= conv_std_logic_vector(1089,11); WHEN "0000101111" => manhi <= conv_std_logic_vector(12568913,24); manlo <= conv_std_logic_vector(246987638,28); exponent <= conv_std_logic_vector(1090,11); WHEN "0000110000" => manhi <= conv_std_logic_vector(3165546,24); manlo <= conv_std_logic_vector(248128843,28); exponent <= conv_std_logic_vector(1092,11); WHEN "0000110001" => manhi <= conv_std_logic_vector(10327809,24); manlo <= conv_std_logic_vector(8929872,28); exponent <= conv_std_logic_vector(1093,11); WHEN "0000110010" => manhi <= conv_std_logic_vector(1642558,24); manlo <= conv_std_logic_vector(67636037,28); exponent <= conv_std_logic_vector(1095,11); WHEN "0000110011" => manhi <= conv_std_logic_vector(8257852,24); manlo <= conv_std_logic_vector(219235425,28); exponent <= conv_std_logic_vector(1096,11); WHEN "0000110100" => manhi <= conv_std_logic_vector(235877,24); manlo <= conv_std_logic_vector(42862412,28); exponent <= conv_std_logic_vector(1098,11); WHEN "0000110101" => manhi <= conv_std_logic_vector(6345974,24); manlo <= conv_std_logic_vector(265996080,28); exponent <= conv_std_logic_vector(1099,11); WHEN "0000110110" => manhi <= conv_std_logic_vector(14650458,24); manlo <= conv_std_logic_vector(253213243,28); exponent <= conv_std_logic_vector(1100,11); WHEN "0000110111" => manhi <= conv_std_logic_vector(4580103,24); manlo <= conv_std_logic_vector(114693785,28); exponent <= conv_std_logic_vector(1102,11); WHEN "0000111000" => manhi <= conv_std_logic_vector(12250390,24); manlo <= conv_std_logic_vector(174984615,28); exponent <= conv_std_logic_vector(1103,11); WHEN "0000111001" => manhi <= conv_std_logic_vector(2949087,24); manlo <= conv_std_logic_vector(247325089,28); exponent <= conv_std_logic_vector(1105,11); WHEN "0000111010" => manhi <= conv_std_logic_vector(10033610,24); manlo <= conv_std_logic_vector(200264553,28); exponent <= conv_std_logic_vector(1106,11); WHEN "0000111011" => manhi <= conv_std_logic_vector(1442629,24); manlo <= conv_std_logic_vector(211375075,28); exponent <= conv_std_logic_vector(1108,11); WHEN "0000111100" => manhi <= conv_std_logic_vector(7986121,24); manlo <= conv_std_logic_vector(231029862,28); exponent <= conv_std_logic_vector(1109,11); WHEN "0000111101" => manhi <= conv_std_logic_vector(51216,24); manlo <= conv_std_logic_vector(222707863,28); exponent <= conv_std_logic_vector(1111,11); WHEN "0000111110" => manhi <= conv_std_logic_vector(6094995,24); manlo <= conv_std_logic_vector(155999272,28); exponent <= conv_std_logic_vector(1112,11); WHEN "0000111111" => manhi <= conv_std_logic_vector(14309342,24); manlo <= conv_std_logic_vector(150013864,28); exponent <= conv_std_logic_vector(1113,11); WHEN "0001000000" => manhi <= conv_std_logic_vector(4348290,24); manlo <= conv_std_logic_vector(217421773,28); exponent <= conv_std_logic_vector(1115,11); WHEN "0001000001" => manhi <= conv_std_logic_vector(11935324,24); manlo <= conv_std_logic_vector(171597361,28); exponent <= conv_std_logic_vector(1116,11); WHEN "0001000010" => manhi <= conv_std_logic_vector(2734978,24); manlo <= conv_std_logic_vector(98553735,28); exponent <= conv_std_logic_vector(1118,11); WHEN "0001000011" => manhi <= conv_std_logic_vector(9742605,24); manlo <= conv_std_logic_vector(185429986,28); exponent <= conv_std_logic_vector(1119,11); WHEN "0001000100" => manhi <= conv_std_logic_vector(1244871,24); manlo <= conv_std_logic_vector(93685501,28); exponent <= conv_std_logic_vector(1121,11); WHEN "0001000101" => manhi <= conv_std_logic_vector(7717340,24); manlo <= conv_std_logic_vector(74048432,28); exponent <= conv_std_logic_vector(1122,11); WHEN "0001000110" => manhi <= conv_std_logic_vector(16514337,24); manlo <= conv_std_logic_vector(163855108,28); exponent <= conv_std_logic_vector(1123,11); WHEN "0001000111" => manhi <= conv_std_logic_vector(5846740,24); manlo <= conv_std_logic_vector(81895750,28); exponent <= conv_std_logic_vector(1125,11); WHEN "0001001000" => manhi <= conv_std_logic_vector(13971928,24); manlo <= conv_std_logic_vector(176088988,28); exponent <= conv_std_logic_vector(1126,11); WHEN "0001001001" => manhi <= conv_std_logic_vector(4118994,24); manlo <= conv_std_logic_vector(77780251,28); exponent <= conv_std_logic_vector(1128,11); WHEN "0001001010" => manhi <= conv_std_logic_vector(11623678,24); manlo <= conv_std_logic_vector(95871356,28); exponent <= conv_std_logic_vector(1129,11); WHEN "0001001011" => manhi <= conv_std_logic_vector(2523192,24); manlo <= conv_std_logic_vector(204213760,28); exponent <= conv_std_logic_vector(1131,11); WHEN "0001001100" => manhi <= conv_std_logic_vector(9454759,24); manlo <= conv_std_logic_vector(55860552,28); exponent <= conv_std_logic_vector(1132,11); WHEN "0001001101" => manhi <= conv_std_logic_vector(1049259,24); manlo <= conv_std_logic_vector(102861624,28); exponent <= conv_std_logic_vector(1134,11); WHEN "0001001110" => manhi <= conv_std_logic_vector(7451476,24); manlo <= conv_std_logic_vector(13367584,28); exponent <= conv_std_logic_vector(1135,11); WHEN "0001001111" => manhi <= conv_std_logic_vector(16152990,24); manlo <= conv_std_logic_vector(178012490,28); exponent <= conv_std_logic_vector(1136,11); WHEN "0001010000" => manhi <= conv_std_logic_vector(5601179,24); manlo <= conv_std_logic_vector(159708139,28); exponent <= conv_std_logic_vector(1138,11); WHEN "0001010001" => manhi <= conv_std_logic_vector(13638177,24); manlo <= conv_std_logic_vector(12864164,28); exponent <= conv_std_logic_vector(1139,11); WHEN "0001010010" => manhi <= conv_std_logic_vector(3892186,24); manlo <= conv_std_logic_vector(149492240,28); exponent <= conv_std_logic_vector(1141,11); WHEN "0001010011" => manhi <= conv_std_logic_vector(11315414,24); manlo <= conv_std_logic_vector(184620728,28); exponent <= conv_std_logic_vector(1142,11); WHEN "0001010100" => manhi <= conv_std_logic_vector(2313705,24); manlo <= conv_std_logic_vector(235697385,28); exponent <= conv_std_logic_vector(1144,11); WHEN "0001010101" => manhi <= conv_std_logic_vector(9170037,24); manlo <= conv_std_logic_vector(3974263,28); exponent <= conv_std_logic_vector(1145,11); WHEN "0001010110" => manhi <= conv_std_logic_vector(855770,24); manlo <= conv_std_logic_vector(158952336,28); exponent <= conv_std_logic_vector(1147,11); WHEN "0001010111" => manhi <= conv_std_logic_vector(7188497,24); manlo <= conv_std_logic_vector(138900038,28); exponent <= conv_std_logic_vector(1148,11); WHEN "0001011000" => manhi <= conv_std_logic_vector(15795565,24); manlo <= conv_std_logic_vector(209449517,28); exponent <= conv_std_logic_vector(1149,11); WHEN "0001011001" => manhi <= conv_std_logic_vector(5358284,24); manlo <= conv_std_logic_vector(54736896,28); exponent <= conv_std_logic_vector(1151,11); WHEN "0001011010" => manhi <= conv_std_logic_vector(13308047,24); manlo <= conv_std_logic_vector(264159588,28); exponent <= conv_std_logic_vector(1152,11); WHEN "0001011011" => manhi <= conv_std_logic_vector(3667840,24); manlo <= conv_std_logic_vector(160544132,28); exponent <= conv_std_logic_vector(1154,11); WHEN "0001011100" => manhi <= conv_std_logic_vector(11010496,24); manlo <= conv_std_logic_vector(245935181,28); exponent <= conv_std_logic_vector(1155,11); WHEN "0001011101" => manhi <= conv_std_logic_vector(2106492,24); manlo <= conv_std_logic_vector(206325441,28); exponent <= conv_std_logic_vector(1157,11); WHEN "0001011110" => manhi <= conv_std_logic_vector(8888405,24); manlo <= conv_std_logic_vector(53641237,28); exponent <= conv_std_logic_vector(1158,11); WHEN "0001011111" => manhi <= conv_std_logic_vector(664381,24); manlo <= conv_std_logic_vector(249887163,28); exponent <= conv_std_logic_vector(1160,11); WHEN "0001100000" => manhi <= conv_std_logic_vector(6928373,24); manlo <= conv_std_logic_vector(95946938,28); exponent <= conv_std_logic_vector(1161,11); WHEN "0001100001" => manhi <= conv_std_logic_vector(15442020,24); manlo <= conv_std_logic_vector(105121290,28); exponent <= conv_std_logic_vector(1162,11); WHEN "0001100010" => manhi <= conv_std_logic_vector(5118025,24); manlo <= conv_std_logic_vector(54367076,28); exponent <= conv_std_logic_vector(1164,11); WHEN "0001100011" => manhi <= conv_std_logic_vector(12981502,24); manlo <= conv_std_logic_vector(39000129,28); exponent <= conv_std_logic_vector(1165,11); WHEN "0001100100" => manhi <= conv_std_logic_vector(3445929,24); manlo <= conv_std_logic_vector(186063861,28); exponent <= conv_std_logic_vector(1167,11); WHEN "0001100101" => manhi <= conv_std_logic_vector(10708888,24); manlo <= conv_std_logic_vector(194877084,28); exponent <= conv_std_logic_vector(1168,11); WHEN "0001100110" => manhi <= conv_std_logic_vector(1901528,24); manlo <= conv_std_logic_vector(202114223,28); exponent <= conv_std_logic_vector(1170,11); WHEN "0001100111" => manhi <= conv_std_logic_vector(8609830,24); manlo <= conv_std_logic_vector(59099508,28); exponent <= conv_std_logic_vector(1171,11); WHEN "0001101000" => manhi <= conv_std_logic_vector(475070,24); manlo <= conv_std_logic_vector(162304029,28); exponent <= conv_std_logic_vector(1173,11); WHEN "0001101001" => manhi <= conv_std_logic_vector(6671072,24); manlo <= conv_std_logic_vector(157938310,28); exponent <= conv_std_logic_vector(1174,11); WHEN "0001101010" => manhi <= conv_std_logic_vector(15092312,24); manlo <= conv_std_logic_vector(104450792,28); exponent <= conv_std_logic_vector(1175,11); WHEN "0001101011" => manhi <= conv_std_logic_vector(4880373,24); manlo <= conv_std_logic_vector(261837049,28); exponent <= conv_std_logic_vector(1177,11); WHEN "0001101100" => manhi <= conv_std_logic_vector(12658500,24); manlo <= conv_std_logic_vector(171583716,28); exponent <= conv_std_logic_vector(1178,11); WHEN "0001101101" => manhi <= conv_std_logic_vector(3226427,24); manlo <= conv_std_logic_vector(110595717,28); exponent <= conv_std_logic_vector(1180,11); WHEN "0001101110" => manhi <= conv_std_logic_vector(10410554,24); manlo <= conv_std_logic_vector(52320382,28); exponent <= conv_std_logic_vector(1181,11); WHEN "0001101111" => manhi <= conv_std_logic_vector(1698789,24); manlo <= conv_std_logic_vector(112550995,28); exponent <= conv_std_logic_vector(1183,11); WHEN "0001110000" => manhi <= conv_std_logic_vector(8334278,24); manlo <= conv_std_logic_vector(240753534,28); exponent <= conv_std_logic_vector(1184,11); WHEN "0001110001" => manhi <= conv_std_logic_vector(287814,24); manlo <= conv_std_logic_vector(17691391,28); exponent <= conv_std_logic_vector(1186,11); WHEN "0001110010" => manhi <= conv_std_logic_vector(6416564,24); manlo <= conv_std_logic_vector(151700710,28); exponent <= conv_std_logic_vector(1187,11); WHEN "0001110011" => manhi <= conv_std_logic_vector(14746400,24); manlo <= conv_std_logic_vector(32676275,28); exponent <= conv_std_logic_vector(1188,11); WHEN "0001110100" => manhi <= conv_std_logic_vector(4645302,24); manlo <= conv_std_logic_vector(58452725,28); exponent <= conv_std_logic_vector(1190,11); WHEN "0001110101" => manhi <= conv_std_logic_vector(12339004,24); manlo <= conv_std_logic_vector(267247876,28); exponent <= conv_std_logic_vector(1191,11); WHEN "0001110110" => manhi <= conv_std_logic_vector(3009307,24); manlo <= conv_std_logic_vector(164126253,28); exponent <= conv_std_logic_vector(1193,11); WHEN "0001110111" => manhi <= conv_std_logic_vector(10115457,24); manlo <= conv_std_logic_vector(212237584,28); exponent <= conv_std_logic_vector(1194,11); WHEN "0001111000" => manhi <= conv_std_logic_vector(1498250,24); manlo <= conv_std_logic_vector(166684427,28); exponent <= conv_std_logic_vector(1196,11); WHEN "0001111001" => manhi <= conv_std_logic_vector(8061718,24); manlo <= conv_std_logic_vector(110371593,28); exponent <= conv_std_logic_vector(1197,11); WHEN "0001111010" => manhi <= conv_std_logic_vector(102590,24); manlo <= conv_std_logic_vector(3231911,28); exponent <= conv_std_logic_vector(1199,11); WHEN "0001111011" => manhi <= conv_std_logic_vector(6164818,24); manlo <= conv_std_logic_vector(261783833,28); exponent <= conv_std_logic_vector(1200,11); WHEN "0001111100" => manhi <= conv_std_logic_vector(14404242,24); manlo <= conv_std_logic_vector(104825991,28); exponent <= conv_std_logic_vector(1201,11); WHEN "0001111101" => manhi <= conv_std_logic_vector(4412781,24); manlo <= conv_std_logic_vector(250166254,28); exponent <= conv_std_logic_vector(1203,11); WHEN "0001111110" => manhi <= conv_std_logic_vector(12022977,24); manlo <= conv_std_logic_vector(43417082,28); exponent <= conv_std_logic_vector(1204,11); WHEN "0001111111" => manhi <= conv_std_logic_vector(2794544,24); manlo <= conv_std_logic_vector(115942082,28); exponent <= conv_std_logic_vector(1206,11); WHEN "0010000000" => manhi <= conv_std_logic_vector(9823564,24); manlo <= conv_std_logic_vector(98386456,28); exponent <= conv_std_logic_vector(1207,11); WHEN "0010000001" => manhi <= conv_std_logic_vector(1299888,24); manlo <= conv_std_logic_vector(127046227,28); exponent <= conv_std_logic_vector(1209,11); WHEN "0010000010" => manhi <= conv_std_logic_vector(7792116,24); manlo <= conv_std_logic_vector(80649262,28); exponent <= conv_std_logic_vector(1210,11); WHEN "0010000011" => manhi <= conv_std_logic_vector(16615968,24); manlo <= conv_std_logic_vector(205307910,28); exponent <= conv_std_logic_vector(1211,11); WHEN "0010000100" => manhi <= conv_std_logic_vector(5915805,24); manlo <= conv_std_logic_vector(224185017,28); exponent <= conv_std_logic_vector(1213,11); WHEN "0010000101" => manhi <= conv_std_logic_vector(14065798,24); manlo <= conv_std_logic_vector(119094636,28); exponent <= conv_std_logic_vector(1214,11); WHEN "0010000110" => manhi <= conv_std_logic_vector(4182785,24); manlo <= conv_std_logic_vector(113890892,28); exponent <= conv_std_logic_vector(1216,11); WHEN "0010000111" => manhi <= conv_std_logic_vector(11710379,24); manlo <= conv_std_logic_vector(133692518,28); exponent <= conv_std_logic_vector(1217,11); WHEN "0010001000" => manhi <= conv_std_logic_vector(2582112,24); manlo <= conv_std_logic_vector(79109485,28); exponent <= conv_std_logic_vector(1219,11); WHEN "0010001001" => manhi <= conv_std_logic_vector(9534839,24); manlo <= conv_std_logic_vector(42234535,28); exponent <= conv_std_logic_vector(1220,11); WHEN "0010001010" => manhi <= conv_std_logic_vector(1103679,24); manlo <= conv_std_logic_vector(94193887,28); exponent <= conv_std_logic_vector(1222,11); WHEN "0010001011" => manhi <= conv_std_logic_vector(7525440,24); manlo <= conv_std_logic_vector(121994268,28); exponent <= conv_std_logic_vector(1223,11); WHEN "0010001100" => manhi <= conv_std_logic_vector(16253518,24); manlo <= conv_std_logic_vector(191052573,28); exponent <= conv_std_logic_vector(1224,11); WHEN "0010001101" => manhi <= conv_std_logic_vector(5669495,24); manlo <= conv_std_logic_vector(130696997,28); exponent <= conv_std_logic_vector(1226,11); WHEN "0010001110" => manhi <= conv_std_logic_vector(13731027,24); manlo <= conv_std_logic_vector(260846837,28); exponent <= conv_std_logic_vector(1227,11); WHEN "0010001111" => manhi <= conv_std_logic_vector(3955285,24); manlo <= conv_std_logic_vector(80970159,28); exponent <= conv_std_logic_vector(1229,11); WHEN "0010010000" => manhi <= conv_std_logic_vector(11401174,24); manlo <= conv_std_logic_vector(207600506,28); exponent <= conv_std_logic_vector(1230,11); WHEN "0010010001" => manhi <= conv_std_logic_vector(2371985,24); manlo <= conv_std_logic_vector(241221170,28); exponent <= conv_std_logic_vector(1232,11); WHEN "0010010010" => manhi <= conv_std_logic_vector(9249247,24); manlo <= conv_std_logic_vector(208105818,28); exponent <= conv_std_logic_vector(1233,11); WHEN "0010010011" => manhi <= conv_std_logic_vector(909599,24); manlo <= conv_std_logic_vector(237519888,28); exponent <= conv_std_logic_vector(1235,11); WHEN "0010010100" => manhi <= conv_std_logic_vector(7261659,24); manlo <= conv_std_logic_vector(29935335,28); exponent <= conv_std_logic_vector(1236,11); WHEN "0010010101" => manhi <= conv_std_logic_vector(15895002,24); manlo <= conv_std_logic_vector(186862656,28); exponent <= conv_std_logic_vector(1237,11); WHEN "0010010110" => manhi <= conv_std_logic_vector(5425858,24); manlo <= conv_std_logic_vector(159524243,28); exponent <= conv_std_logic_vector(1239,11); WHEN "0010010111" => manhi <= conv_std_logic_vector(13399891,24); manlo <= conv_std_logic_vector(27586577,28); exponent <= conv_std_logic_vector(1240,11); WHEN "0010011000" => manhi <= conv_std_logic_vector(3730254,24); manlo <= conv_std_logic_vector(125689310,28); exponent <= conv_std_logic_vector(1242,11); WHEN "0010011001" => manhi <= conv_std_logic_vector(11095326,24); manlo <= conv_std_logic_vector(43144000,28); exponent <= conv_std_logic_vector(1243,11); WHEN "0010011010" => manhi <= conv_std_logic_vector(2164140,24); manlo <= conv_std_logic_vector(58280992,28); exponent <= conv_std_logic_vector(1245,11); WHEN "0010011011" => manhi <= conv_std_logic_vector(8966756,24); manlo <= conv_std_logic_vector(55210422,28); exponent <= conv_std_logic_vector(1246,11); WHEN "0010011100" => manhi <= conv_std_logic_vector(717626,24); manlo <= conv_std_logic_vector(257633658,28); exponent <= conv_std_logic_vector(1248,11); WHEN "0010011101" => manhi <= conv_std_logic_vector(7000740,24); manlo <= conv_std_logic_vector(229413090,28); exponent <= conv_std_logic_vector(1249,11); WHEN "0010011110" => manhi <= conv_std_logic_vector(15540378,24); manlo <= conv_std_logic_vector(4808337,28); exponent <= conv_std_logic_vector(1250,11); WHEN "0010011111" => manhi <= conv_std_logic_vector(5184866,24); manlo <= conv_std_logic_vector(37474138,28); exponent <= conv_std_logic_vector(1252,11); WHEN "0010100000" => manhi <= conv_std_logic_vector(13072348,24); manlo <= conv_std_logic_vector(106730632,28); exponent <= conv_std_logic_vector(1253,11); WHEN "0010100001" => manhi <= conv_std_logic_vector(3507666,24); manlo <= conv_std_logic_vector(32844500,28); exponent <= conv_std_logic_vector(1255,11); WHEN "0010100010" => manhi <= conv_std_logic_vector(10792797,24); manlo <= conv_std_logic_vector(62496090,28); exponent <= conv_std_logic_vector(1256,11); WHEN "0010100011" => manhi <= conv_std_logic_vector(1958550,24); manlo <= conv_std_logic_vector(132952012,28); exponent <= conv_std_logic_vector(1258,11); WHEN "0010100100" => manhi <= conv_std_logic_vector(8687330,24); manlo <= conv_std_logic_vector(215605290,28); exponent <= conv_std_logic_vector(1259,11); WHEN "0010100101" => manhi <= conv_std_logic_vector(527737,24); manlo <= conv_std_logic_vector(190928911,28); exponent <= conv_std_logic_vector(1261,11); WHEN "0010100110" => manhi <= conv_std_logic_vector(6742654,24); manlo <= conv_std_logic_vector(163162889,28); exponent <= conv_std_logic_vector(1262,11); WHEN "0010100111" => manhi <= conv_std_logic_vector(15189602,24); manlo <= conv_std_logic_vector(118241780,28); exponent <= conv_std_logic_vector(1263,11); WHEN "0010101000" => manhi <= conv_std_logic_vector(4946489,24); manlo <= conv_std_logic_vector(112771062,28); exponent <= conv_std_logic_vector(1265,11); WHEN "0010101001" => manhi <= conv_std_logic_vector(12748360,24); manlo <= conv_std_logic_vector(226864003,28); exponent <= conv_std_logic_vector(1266,11); WHEN "0010101010" => manhi <= conv_std_logic_vector(3287493,24); manlo <= conv_std_logic_vector(202192272,28); exponent <= conv_std_logic_vector(1268,11); WHEN "0010101011" => manhi <= conv_std_logic_vector(10493551,24); manlo <= conv_std_logic_vector(257093553,28); exponent <= conv_std_logic_vector(1269,11); WHEN "0010101100" => manhi <= conv_std_logic_vector(1755192,24); manlo <= conv_std_logic_vector(66281405,28); exponent <= conv_std_logic_vector(1271,11); WHEN "0010101101" => manhi <= conv_std_logic_vector(8410938,24); manlo <= conv_std_logic_vector(77199396,28); exponent <= conv_std_logic_vector(1272,11); WHEN "0010101110" => manhi <= conv_std_logic_vector(339909,24); manlo <= conv_std_logic_vector(140417186,28); exponent <= conv_std_logic_vector(1274,11); WHEN "0010101111" => manhi <= conv_std_logic_vector(6487369,24); manlo <= conv_std_logic_vector(169769464,28); exponent <= conv_std_logic_vector(1275,11); WHEN "0010110000" => manhi <= conv_std_logic_vector(14842634,24); manlo <= conv_std_logic_vector(49834035,28); exponent <= conv_std_logic_vector(1276,11); WHEN "0010110001" => manhi <= conv_std_logic_vector(4710700,24); manlo <= conv_std_logic_vector(11961455,28); exponent <= conv_std_logic_vector(1278,11); WHEN "0010110010" => manhi <= conv_std_logic_vector(12427889,24); manlo <= conv_std_logic_vector(230234502,28); exponent <= conv_std_logic_vector(1279,11); WHEN "0010110011" => manhi <= conv_std_logic_vector(3069711,24); manlo <= conv_std_logic_vector(36989233,28); exponent <= conv_std_logic_vector(1281,11); WHEN "0010110100" => manhi <= conv_std_logic_vector(10197554,24); manlo <= conv_std_logic_vector(186484869,28); exponent <= conv_std_logic_vector(1282,11); WHEN "0010110101" => manhi <= conv_std_logic_vector(1554041,24); manlo <= conv_std_logic_vector(67530342,28); exponent <= conv_std_logic_vector(1284,11); WHEN "0010110110" => manhi <= conv_std_logic_vector(8137545,24); manlo <= conv_std_logic_vector(198608842,28); exponent <= conv_std_logic_vector(1285,11); WHEN "0010110111" => manhi <= conv_std_logic_vector(154120,24); manlo <= conv_std_logic_vector(6569319,28); exponent <= conv_std_logic_vector(1287,11); WHEN "0010111000" => manhi <= conv_std_logic_vector(6234855,24); manlo <= conv_std_logic_vector(140506894,28); exponent <= conv_std_logic_vector(1288,11); WHEN "0010111001" => manhi <= conv_std_logic_vector(14499431,24); manlo <= conv_std_logic_vector(249287529,28); exponent <= conv_std_logic_vector(1289,11); WHEN "0010111010" => manhi <= conv_std_logic_vector(4477469,24); manlo <= conv_std_logic_vector(249618841,28); exponent <= conv_std_logic_vector(1291,11); WHEN "0010111011" => manhi <= conv_std_logic_vector(12110897,24); manlo <= conv_std_logic_vector(71519058,28); exponent <= conv_std_logic_vector(1292,11); WHEN "0010111100" => manhi <= conv_std_logic_vector(2854292,24); manlo <= conv_std_logic_vector(90637320,28); exponent <= conv_std_logic_vector(1294,11); WHEN "0010111101" => manhi <= conv_std_logic_vector(9904770,24); manlo <= conv_std_logic_vector(50932558,28); exponent <= conv_std_logic_vector(1295,11); WHEN "0010111110" => manhi <= conv_std_logic_vector(1355073,24); manlo <= conv_std_logic_vector(148093260,28); exponent <= conv_std_logic_vector(1297,11); WHEN "0010111111" => manhi <= conv_std_logic_vector(7867120,24); manlo <= conv_std_logic_vector(160620741,28); exponent <= conv_std_logic_vector(1298,11); WHEN "0011000000" => manhi <= conv_std_logic_vector(16717910,24); manlo <= conv_std_logic_vector(46942270,28); exponent <= conv_std_logic_vector(1299,11); WHEN "0011000001" => manhi <= conv_std_logic_vector(5985082,24); manlo <= conv_std_logic_vector(55237426,28); exponent <= conv_std_logic_vector(1301,11); WHEN "0011000010" => manhi <= conv_std_logic_vector(14159954,24); manlo <= conv_std_logic_vector(212966668,28); exponent <= conv_std_logic_vector(1302,11); WHEN "0011000011" => manhi <= conv_std_logic_vector(4246771,24); manlo <= conv_std_logic_vector(79962334,28); exponent <= conv_std_logic_vector(1304,11); WHEN "0011000100" => manhi <= conv_std_logic_vector(11797345,24); manlo <= conv_std_logic_vector(85038862,28); exponent <= conv_std_logic_vector(1305,11); WHEN "0011000101" => manhi <= conv_std_logic_vector(2641211,24); manlo <= conv_std_logic_vector(186806322,28); exponent <= conv_std_logic_vector(1307,11); WHEN "0011000110" => manhi <= conv_std_logic_vector(9615163,24); manlo <= conv_std_logic_vector(153415152,28); exponent <= conv_std_logic_vector(1308,11); WHEN "0011000111" => manhi <= conv_std_logic_vector(1158265,24); manlo <= conv_std_logic_vector(120731907,28); exponent <= conv_std_logic_vector(1310,11); WHEN "0011001000" => manhi <= conv_std_logic_vector(7599630,24); manlo <= conv_std_logic_vector(175764921,28); exponent <= conv_std_logic_vector(1311,11); WHEN "0011001001" => manhi <= conv_std_logic_vector(16354353,24); manlo <= conv_std_logic_vector(174054693,28); exponent <= conv_std_logic_vector(1312,11); WHEN "0011001010" => manhi <= conv_std_logic_vector(5738019,24); manlo <= conv_std_logic_vector(249885394,28); exponent <= conv_std_logic_vector(1314,11); WHEN "0011001011" => manhi <= conv_std_logic_vector(13824162,24); manlo <= conv_std_logic_vector(93203713,28); exponent <= conv_std_logic_vector(1315,11); WHEN "0011001100" => manhi <= conv_std_logic_vector(4018576,24); manlo <= conv_std_logic_vector(180323091,28); exponent <= conv_std_logic_vector(1317,11); WHEN "0011001101" => manhi <= conv_std_logic_vector(11487196,24); manlo <= conv_std_logic_vector(178245939,28); exponent <= conv_std_logic_vector(1318,11); WHEN "0011001110" => manhi <= conv_std_logic_vector(2430443,24); manlo <= conv_std_logic_vector(223919964,28); exponent <= conv_std_logic_vector(1320,11); WHEN "0011001111" => manhi <= conv_std_logic_vector(9328700,24); manlo <= conv_std_logic_vector(93205956,28); exponent <= conv_std_logic_vector(1321,11); WHEN "0011010000" => manhi <= conv_std_logic_vector(963593,24); manlo <= conv_std_logic_vector(135688620,28); exponent <= conv_std_logic_vector(1323,11); WHEN "0011010001" => manhi <= conv_std_logic_vector(7335044,24); manlo <= conv_std_logic_vector(13542358,28); exponent <= conv_std_logic_vector(1324,11); WHEN "0011010010" => manhi <= conv_std_logic_vector(15994743,24); manlo <= conv_std_logic_vector(45394459,28); exponent <= conv_std_logic_vector(1325,11); WHEN "0011010011" => manhi <= conv_std_logic_vector(5493639,24); manlo <= conv_std_logic_vector(73308838,28); exponent <= conv_std_logic_vector(1327,11); WHEN "0011010100" => manhi <= conv_std_logic_vector(13492014,24); manlo <= conv_std_logic_vector(160135181,28); exponent <= conv_std_logic_vector(1328,11); WHEN "0011010101" => manhi <= conv_std_logic_vector(3792858,24); manlo <= conv_std_logic_vector(234346738,28); exponent <= conv_std_logic_vector(1330,11); WHEN "0011010110" => manhi <= conv_std_logic_vector(11180414,24); manlo <= conv_std_logic_vector(98964646,28); exponent <= conv_std_logic_vector(1331,11); WHEN "0011010111" => manhi <= conv_std_logic_vector(2221963,24); manlo <= conv_std_logic_vector(174344531,28); exponent <= conv_std_logic_vector(1333,11); WHEN "0011011000" => manhi <= conv_std_logic_vector(9045346,24); manlo <= conv_std_logic_vector(106947534,28); exponent <= conv_std_logic_vector(1334,11); WHEN "0011011001" => manhi <= conv_std_logic_vector(771034,24); manlo <= conv_std_logic_vector(143065990,28); exponent <= conv_std_logic_vector(1336,11); WHEN "0011011010" => manhi <= conv_std_logic_vector(7073329,24); manlo <= conv_std_logic_vector(73148434,28); exponent <= conv_std_logic_vector(1337,11); WHEN "0011011011" => manhi <= conv_std_logic_vector(15639035,24); manlo <= conv_std_logic_vector(243346703,28); exponent <= conv_std_logic_vector(1338,11); WHEN "0011011100" => manhi <= conv_std_logic_vector(5251911,24); manlo <= conv_std_logic_vector(33842377,28); exponent <= conv_std_logic_vector(1340,11); WHEN "0011011101" => manhi <= conv_std_logic_vector(13163471,24); manlo <= conv_std_logic_vector(263552292,28); exponent <= conv_std_logic_vector(1341,11); WHEN "0011011110" => manhi <= conv_std_logic_vector(3569591,24); manlo <= conv_std_logic_vector(4866264,28); exponent <= conv_std_logic_vector(1343,11); WHEN "0011011111" => manhi <= conv_std_logic_vector(10876961,24); manlo <= conv_std_logic_vector(239517036,28); exponent <= conv_std_logic_vector(1344,11); WHEN "0011100000" => manhi <= conv_std_logic_vector(2015746,24); manlo <= conv_std_logic_vector(83586287,28); exponent <= conv_std_logic_vector(1346,11); WHEN "0011100001" => manhi <= conv_std_logic_vector(8765067,24); manlo <= conv_std_logic_vector(262254542,28); exponent <= conv_std_logic_vector(1347,11); WHEN "0011100010" => manhi <= conv_std_logic_vector(580565,24); manlo <= conv_std_logic_vector(160521039,28); exponent <= conv_std_logic_vector(1349,11); WHEN "0011100011" => manhi <= conv_std_logic_vector(6814455,24); manlo <= conv_std_logic_vector(40288155,28); exponent <= conv_std_logic_vector(1350,11); WHEN "0011100100" => manhi <= conv_std_logic_vector(15287189,24); manlo <= conv_std_logic_vector(132910147,28); exponent <= conv_std_logic_vector(1351,11); WHEN "0011100101" => manhi <= conv_std_logic_vector(5012806,24); manlo <= conv_std_logic_vector(187753904,28); exponent <= conv_std_logic_vector(1353,11); WHEN "0011100110" => manhi <= conv_std_logic_vector(12838495,24); manlo <= conv_std_logic_vector(100071648,28); exponent <= conv_std_logic_vector(1354,11); WHEN "0011100111" => manhi <= conv_std_logic_vector(3348746,24); manlo <= conv_std_logic_vector(138348888,28); exponent <= conv_std_logic_vector(1356,11); WHEN "0011101000" => manhi <= conv_std_logic_vector(10576803,24); manlo <= conv_std_logic_vector(24941937,28); exponent <= conv_std_logic_vector(1357,11); WHEN "0011101001" => manhi <= conv_std_logic_vector(1811767,24); manlo <= conv_std_logic_vector(69497619,28); exponent <= conv_std_logic_vector(1359,11); WHEN "0011101010" => manhi <= conv_std_logic_vector(8487831,24); manlo <= conv_std_logic_vector(188199296,28); exponent <= conv_std_logic_vector(1360,11); WHEN "0011101011" => manhi <= conv_std_logic_vector(392164,24); manlo <= conv_std_logic_vector(4096525,28); exponent <= conv_std_logic_vector(1362,11); WHEN "0011101100" => manhi <= conv_std_logic_vector(6558390,24); manlo <= conv_std_logic_vector(228356857,28); exponent <= conv_std_logic_vector(1363,11); WHEN "0011101101" => manhi <= conv_std_logic_vector(14939162,24); manlo <= conv_std_logic_vector(7826265,28); exponent <= conv_std_logic_vector(1364,11); WHEN "0011101110" => manhi <= conv_std_logic_vector(4776297,24); manlo <= conv_std_logic_vector(138324122,28); exponent <= conv_std_logic_vector(1366,11); WHEN "0011101111" => manhi <= conv_std_logic_vector(12517046,24); manlo <= conv_std_logic_vector(17190560,28); exponent <= conv_std_logic_vector(1367,11); WHEN "0011110000" => manhi <= conv_std_logic_vector(3130299,24); manlo <= conv_std_logic_vector(16562242,28); exponent <= conv_std_logic_vector(1369,11); WHEN "0011110001" => manhi <= conv_std_logic_vector(10279902,24); manlo <= conv_std_logic_vector(59323104,28); exponent <= conv_std_logic_vector(1370,11); WHEN "0011110010" => manhi <= conv_std_logic_vector(1610002,24); manlo <= conv_std_logic_vector(53056333,28); exponent <= conv_std_logic_vector(1372,11); WHEN "0011110011" => manhi <= conv_std_logic_vector(8213604,24); manlo <= conv_std_logic_vector(147986337,28); exponent <= conv_std_logic_vector(1373,11); WHEN "0011110100" => manhi <= conv_std_logic_vector(205807,24); manlo <= conv_std_logic_vector(92802035,28); exponent <= conv_std_logic_vector(1375,11); WHEN "0011110101" => manhi <= conv_std_logic_vector(6305105,24); manlo <= conv_std_logic_vector(235277170,28); exponent <= conv_std_logic_vector(1376,11); WHEN "0011110110" => manhi <= conv_std_logic_vector(14594912,24); manlo <= conv_std_logic_vector(15497684,28); exponent <= conv_std_logic_vector(1377,11); WHEN "0011110111" => manhi <= conv_std_logic_vector(4542355,24); manlo <= conv_std_logic_vector(108677892,28); exponent <= conv_std_logic_vector(1379,11); WHEN "0011111000" => manhi <= conv_std_logic_vector(12199085,24); manlo <= conv_std_logic_vector(206743222,28); exponent <= conv_std_logic_vector(1380,11); WHEN "0011111001" => manhi <= conv_std_logic_vector(2914222,24); manlo <= conv_std_logic_vector(171652524,28); exponent <= conv_std_logic_vector(1382,11); WHEN "0011111010" => manhi <= conv_std_logic_vector(9986223,24); manlo <= conv_std_logic_vector(245598061,28); exponent <= conv_std_logic_vector(1383,11); WHEN "0011111011" => manhi <= conv_std_logic_vector(1410427,24); manlo <= conv_std_logic_vector(26024388,28); exponent <= conv_std_logic_vector(1385,11); WHEN "0011111100" => manhi <= conv_std_logic_vector(7942353,24); manlo <= conv_std_logic_vector(232590388,28); exponent <= conv_std_logic_vector(1386,11); WHEN "0011111101" => manhi <= conv_std_logic_vector(21473,24); manlo <= conv_std_logic_vector(105719295,28); exponent <= conv_std_logic_vector(1388,11); WHEN "0011111110" => manhi <= conv_std_logic_vector(6054570,24); manlo <= conv_std_logic_vector(16265786,28); exponent <= conv_std_logic_vector(1389,11); WHEN "0011111111" => manhi <= conv_std_logic_vector(14254398,24); manlo <= conv_std_logic_vector(155662944,28); exponent <= conv_std_logic_vector(1390,11); WHEN "0100000000" => manhi <= conv_std_logic_vector(4310952,24); manlo <= conv_std_logic_vector(135577274,28); exponent <= conv_std_logic_vector(1392,11); WHEN "0100000001" => manhi <= conv_std_logic_vector(11884576,24); manlo <= conv_std_logic_vector(166805756,28); exponent <= conv_std_logic_vector(1393,11); WHEN "0100000010" => manhi <= conv_std_logic_vector(2700491,24); manlo <= conv_std_logic_vector(137829044,28); exponent <= conv_std_logic_vector(1395,11); WHEN "0100000011" => manhi <= conv_std_logic_vector(9695733,24); manlo <= conv_std_logic_vector(52863001,28); exponent <= conv_std_logic_vector(1396,11); WHEN "0100000100" => manhi <= conv_std_logic_vector(1213018,24); manlo <= conv_std_logic_vector(50179603,28); exponent <= conv_std_logic_vector(1398,11); WHEN "0100000101" => manhi <= conv_std_logic_vector(7674047,24); manlo <= conv_std_logic_vector(91276680,28); exponent <= conv_std_logic_vector(1399,11); WHEN "0100000110" => manhi <= conv_std_logic_vector(16455496,24); manlo <= conv_std_logic_vector(110068760,28); exponent <= conv_std_logic_vector(1400,11); WHEN "0100000111" => manhi <= conv_std_logic_vector(5806753,24); manlo <= conv_std_logic_vector(151304445,28); exponent <= conv_std_logic_vector(1402,11); WHEN "0100001000" => manhi <= conv_std_logic_vector(13917581,24); manlo <= conv_std_logic_vector(10650184,28); exponent <= conv_std_logic_vector(1403,11); WHEN "0100001001" => manhi <= conv_std_logic_vector(4082061,24); manlo <= conv_std_logic_vector(68530707,28); exponent <= conv_std_logic_vector(1405,11); WHEN "0100001010" => manhi <= conv_std_logic_vector(11573481,24); manlo <= conv_std_logic_vector(42662756,28); exponent <= conv_std_logic_vector(1406,11); WHEN "0100001011" => manhi <= conv_std_logic_vector(2489080,24); manlo <= conv_std_logic_vector(61154162,28); exponent <= conv_std_logic_vector(1408,11); WHEN "0100001100" => manhi <= conv_std_logic_vector(9408395,24); manlo <= conv_std_logic_vector(125867240,28); exponent <= conv_std_logic_vector(1409,11); WHEN "0100001101" => manhi <= conv_std_logic_vector(1017751,24); manlo <= conv_std_logic_vector(256555705,28); exponent <= conv_std_logic_vector(1411,11); WHEN "0100001110" => manhi <= conv_std_logic_vector(7408653,24); manlo <= conv_std_logic_vector(4309896,28); exponent <= conv_std_logic_vector(1412,11); WHEN "0100001111" => manhi <= conv_std_logic_vector(16094788,24); manlo <= conv_std_logic_vector(33800670,28); exponent <= conv_std_logic_vector(1413,11); WHEN "0100010000" => manhi <= conv_std_logic_vector(5561626,24); manlo <= conv_std_logic_vector(233573192,28); exponent <= conv_std_logic_vector(1415,11); WHEN "0100010001" => manhi <= conv_std_logic_vector(13584419,24); manlo <= conv_std_logic_vector(86257801,28); exponent <= conv_std_logic_vector(1416,11); WHEN "0100010010" => manhi <= conv_std_logic_vector(3855654,24); manlo <= conv_std_logic_vector(105782775,28); exponent <= conv_std_logic_vector(1418,11); WHEN "0100010011" => manhi <= conv_std_logic_vector(11265762,24); manlo <= conv_std_logic_vector(88738762,28); exponent <= conv_std_logic_vector(1419,11); WHEN "0100010100" => manhi <= conv_std_logic_vector(2279963,24); manlo <= conv_std_logic_vector(161858527,28); exponent <= conv_std_logic_vector(1421,11); WHEN "0100010101" => manhi <= conv_std_logic_vector(9124176,24); manlo <= conv_std_logic_vector(136423424,28); exponent <= conv_std_logic_vector(1422,11); WHEN "0100010110" => manhi <= conv_std_logic_vector(824605,24); manlo <= conv_std_logic_vector(39384255,28); exponent <= conv_std_logic_vector(1424,11); WHEN "0100010111" => manhi <= conv_std_logic_vector(7146139,24); manlo <= conv_std_logic_vector(76626123,28); exponent <= conv_std_logic_vector(1425,11); WHEN "0100011000" => manhi <= conv_std_logic_vector(15737994,24); manlo <= conv_std_logic_vector(261485765,28); exponent <= conv_std_logic_vector(1426,11); WHEN "0100011001" => manhi <= conv_std_logic_vector(5319160,24); manlo <= conv_std_logic_vector(210684009,28); exponent <= conv_std_logic_vector(1428,11); WHEN "0100011010" => manhi <= conv_std_logic_vector(13254873,24); manlo <= conv_std_logic_vector(199859160,28); exponent <= conv_std_logic_vector(1429,11); WHEN "0100011011" => manhi <= conv_std_logic_vector(3631704,24); manlo <= conv_std_logic_vector(256571707,28); exponent <= conv_std_logic_vector(1431,11); WHEN "0100011100" => manhi <= conv_std_logic_vector(10961383,24); manlo <= conv_std_logic_vector(130542749,28); exponent <= conv_std_logic_vector(1432,11); WHEN "0100011101" => manhi <= conv_std_logic_vector(2073116,24); manlo <= conv_std_logic_vector(196665136,28); exponent <= conv_std_logic_vector(1434,11); WHEN "0100011110" => manhi <= conv_std_logic_vector(8843042,24); manlo <= conv_std_logic_vector(124490661,28); exponent <= conv_std_logic_vector(1435,11); WHEN "0100011111" => manhi <= conv_std_logic_vector(633554,24); manlo <= conv_std_logic_vector(202834752,28); exponent <= conv_std_logic_vector(1437,11); WHEN "0100100000" => manhi <= conv_std_logic_vector(6886474,24); manlo <= conv_std_logic_vector(236822279,28); exponent <= conv_std_logic_vector(1438,11); WHEN "0100100001" => manhi <= conv_std_logic_vector(15385074,24); manlo <= conv_std_logic_vector(123405487,28); exponent <= conv_std_logic_vector(1439,11); WHEN "0100100010" => manhi <= conv_std_logic_vector(5079326,24); manlo <= conv_std_logic_vector(115311954,28); exponent <= conv_std_logic_vector(1441,11); WHEN "0100100011" => manhi <= conv_std_logic_vector(12928905,24); manlo <= conv_std_logic_vector(16004876,28); exponent <= conv_std_logic_vector(1442,11); WHEN "0100100100" => manhi <= conv_std_logic_vector(3410186,24); manlo <= conv_std_logic_vector(71831800,28); exponent <= conv_std_logic_vector(1444,11); WHEN "0100100101" => manhi <= conv_std_logic_vector(10660308,24); manlo <= conv_std_logic_vector(100367284,28); exponent <= conv_std_logic_vector(1445,11); WHEN "0100100110" => manhi <= conv_std_logic_vector(1868514,24); manlo <= conv_std_logic_vector(263299419,28); exponent <= conv_std_logic_vector(1447,11); WHEN "0100100111" => manhi <= conv_std_logic_vector(8564959,24); manlo <= conv_std_logic_vector(228656810,28); exponent <= conv_std_logic_vector(1448,11); WHEN "0100101000" => manhi <= conv_std_logic_vector(444578,24); manlo <= conv_std_logic_vector(7489141,28); exponent <= conv_std_logic_vector(1450,11); WHEN "0100101001" => manhi <= conv_std_logic_vector(6629628,24); manlo <= conv_std_logic_vector(236156491,28); exponent <= conv_std_logic_vector(1451,11); WHEN "0100101010" => manhi <= conv_std_logic_vector(15035984,24); manlo <= conv_std_logic_vector(147396312,28); exponent <= conv_std_logic_vector(1452,11); WHEN "0100101011" => manhi <= conv_std_logic_vector(4842095,24); manlo <= conv_std_logic_vector(64271882,28); exponent <= conv_std_logic_vector(1454,11); WHEN "0100101100" => manhi <= conv_std_logic_vector(12606474,24); manlo <= conv_std_logic_vector(118909770,28); exponent <= conv_std_logic_vector(1455,11); WHEN "0100101101" => manhi <= conv_std_logic_vector(3191071,24); manlo <= conv_std_logic_vector(253953386,28); exponent <= conv_std_logic_vector(1457,11); WHEN "0100101110" => manhi <= conv_std_logic_vector(10362501,24); manlo <= conv_std_logic_vector(36129498,28); exponent <= conv_std_logic_vector(1458,11); WHEN "0100101111" => manhi <= conv_std_logic_vector(1666133,24); manlo <= conv_std_logic_vector(262830684,28); exponent <= conv_std_logic_vector(1460,11); WHEN "0100110000" => manhi <= conv_std_logic_vector(8289895,24); manlo <= conv_std_logic_vector(148197046,28); exponent <= conv_std_logic_vector(1461,11); WHEN "0100110001" => manhi <= conv_std_logic_vector(257652,24); manlo <= conv_std_logic_vector(122404338,28); exponent <= conv_std_logic_vector(1463,11); WHEN "0100110010" => manhi <= conv_std_logic_vector(6375570,24); manlo <= conv_std_logic_vector(184430245,28); exponent <= conv_std_logic_vector(1464,11); WHEN "0100110011" => manhi <= conv_std_logic_vector(14690683,24); manlo <= conv_std_logic_vector(178457687,28); exponent <= conv_std_logic_vector(1465,11); WHEN "0100110100" => manhi <= conv_std_logic_vector(4607438,24); manlo <= conv_std_logic_vector(257605193,28); exponent <= conv_std_logic_vector(1467,11); WHEN "0100110101" => manhi <= conv_std_logic_vector(12287543,24); manlo <= conv_std_logic_vector(132163446,28); exponent <= conv_std_logic_vector(1468,11); WHEN "0100110110" => manhi <= conv_std_logic_vector(2974335,24); manlo <= conv_std_logic_vector(240020217,28); exponent <= conv_std_logic_vector(1470,11); WHEN "0100110111" => manhi <= conv_std_logic_vector(10067926,24); manlo <= conv_std_logic_vector(80224641,28); exponent <= conv_std_logic_vector(1471,11); WHEN "0100111000" => manhi <= conv_std_logic_vector(1465949,24); manlo <= conv_std_logic_vector(167328478,28); exponent <= conv_std_logic_vector(1473,11); WHEN "0100111001" => manhi <= conv_std_logic_vector(8017816,24); manlo <= conv_std_logic_vector(215756784,28); exponent <= conv_std_logic_vector(1474,11); WHEN "0100111010" => manhi <= conv_std_logic_vector(72755,24); manlo <= conv_std_logic_vector(208473528,28); exponent <= conv_std_logic_vector(1476,11); WHEN "0100111011" => manhi <= conv_std_logic_vector(6124270,24); manlo <= conv_std_logic_vector(12139444,28); exponent <= conv_std_logic_vector(1477,11); WHEN "0100111100" => manhi <= conv_std_logic_vector(14349130,24); manlo <= conv_std_logic_vector(182729110,28); exponent <= conv_std_logic_vector(1478,11); WHEN "0100111101" => manhi <= conv_std_logic_vector(4375329,24); manlo <= conv_std_logic_vector(172370119,28); exponent <= conv_std_logic_vector(1480,11); WHEN "0100111110" => manhi <= conv_std_logic_vector(11972074,24); manlo <= conv_std_logic_vector(59679792,28); exponent <= conv_std_logic_vector(1481,11); WHEN "0100111111" => manhi <= conv_std_logic_vector(2759952,24); manlo <= conv_std_logic_vector(80023302,28); exponent <= conv_std_logic_vector(1483,11); WHEN "0101000000" => manhi <= conv_std_logic_vector(9776548,24); manlo <= conv_std_logic_vector(209956608,28); exponent <= conv_std_logic_vector(1484,11); WHEN "0101000001" => manhi <= conv_std_logic_vector(1267938,24); manlo <= conv_std_logic_vector(19091951,28); exponent <= conv_std_logic_vector(1486,11); WHEN "0101000010" => manhi <= conv_std_logic_vector(7748691,24); manlo <= conv_std_logic_vector(54127000,28); exponent <= conv_std_logic_vector(1487,11); WHEN "0101000011" => manhi <= conv_std_logic_vector(16556947,24); manlo <= conv_std_logic_vector(251347868,28); exponent <= conv_std_logic_vector(1488,11); WHEN "0101000100" => manhi <= conv_std_logic_vector(5875697,24); manlo <= conv_std_logic_vector(6377900,28); exponent <= conv_std_logic_vector(1490,11); WHEN "0101000101" => manhi <= conv_std_logic_vector(14011284,24); manlo <= conv_std_logic_vector(246175281,28); exponent <= conv_std_logic_vector(1491,11); WHEN "0101000110" => manhi <= conv_std_logic_vector(4145739,24); manlo <= conv_std_logic_vector(172360927,28); exponent <= conv_std_logic_vector(1493,11); WHEN "0101000111" => manhi <= conv_std_logic_vector(11660029,24); manlo <= conv_std_logic_vector(16047086,28); exponent <= conv_std_logic_vector(1494,11); WHEN "0101001000" => manhi <= conv_std_logic_vector(2547895,24); manlo <= conv_std_logic_vector(167600151,28); exponent <= conv_std_logic_vector(1496,11); WHEN "0101001001" => manhi <= conv_std_logic_vector(9488333,24); manlo <= conv_std_logic_vector(236416250,28); exponent <= conv_std_logic_vector(1497,11); WHEN "0101001010" => manhi <= conv_std_logic_vector(1072075,24); manlo <= conv_std_logic_vector(198323037,28); exponent <= conv_std_logic_vector(1499,11); WHEN "0101001011" => manhi <= conv_std_logic_vector(7482486,24); manlo <= conv_std_logic_vector(185820926,28); exponent <= conv_std_logic_vector(1500,11); WHEN "0101001100" => manhi <= conv_std_logic_vector(16195138,24); manlo <= conv_std_logic_vector(133160968,28); exponent <= conv_std_logic_vector(1501,11); WHEN "0101001101" => manhi <= conv_std_logic_vector(5629822,24); manlo <= conv_std_logic_vector(4574050,28); exponent <= conv_std_logic_vector(1503,11); WHEN "0101001110" => manhi <= conv_std_logic_vector(13677106,24); manlo <= conv_std_logic_vector(36414601,28); exponent <= conv_std_logic_vector(1504,11); WHEN "0101001111" => manhi <= conv_std_logic_vector(3918641,24); manlo <= conv_std_logic_vector(165046798,28); exponent <= conv_std_logic_vector(1506,11); WHEN "0101010000" => manhi <= conv_std_logic_vector(11351370,24); manlo <= conv_std_logic_vector(225326735,28); exponent <= conv_std_logic_vector(1507,11); WHEN "0101010001" => manhi <= conv_std_logic_vector(2338140,24); manlo <= conv_std_logic_vector(165476611,28); exponent <= conv_std_logic_vector(1509,11); WHEN "0101010010" => manhi <= conv_std_logic_vector(9203247,24); manlo <= conv_std_logic_vector(71807303,28); exponent <= conv_std_logic_vector(1510,11); WHEN "0101010011" => manhi <= conv_std_logic_vector(878339,24); manlo <= conv_std_logic_vector(80195176,28); exponent <= conv_std_logic_vector(1512,11); WHEN "0101010100" => manhi <= conv_std_logic_vector(7219171,24); manlo <= conv_std_logic_vector(153001068,28); exponent <= conv_std_logic_vector(1513,11); WHEN "0101010101" => manhi <= conv_std_logic_vector(15837256,24); manlo <= conv_std_logic_vector(37596960,28); exponent <= conv_std_logic_vector(1514,11); WHEN "0101010110" => manhi <= conv_std_logic_vector(5386615,24); manlo <= conv_std_logic_vector(198850796,28); exponent <= conv_std_logic_vector(1516,11); WHEN "0101010111" => manhi <= conv_std_logic_vector(13346554,24); manlo <= conv_std_logic_vector(143609986,28); exponent <= conv_std_logic_vector(1517,11); WHEN "0101011000" => manhi <= conv_std_logic_vector(3694008,24); manlo <= conv_std_logic_vector(137568494,28); exponent <= conv_std_logic_vector(1519,11); WHEN "0101011001" => manhi <= conv_std_logic_vector(11046062,24); manlo <= conv_std_logic_vector(214558683,28); exponent <= conv_std_logic_vector(1520,11); WHEN "0101011010" => manhi <= conv_std_logic_vector(2130662,24); manlo <= conv_std_logic_vector(78401205,28); exponent <= conv_std_logic_vector(1522,11); WHEN "0101011011" => manhi <= conv_std_logic_vector(8921254,24); manlo <= conv_std_logic_vector(265219821,28); exponent <= conv_std_logic_vector(1523,11); WHEN "0101011100" => manhi <= conv_std_logic_vector(686705,24); manlo <= conv_std_logic_vector(181591149,28); exponent <= conv_std_logic_vector(1525,11); WHEN "0101011101" => manhi <= conv_std_logic_vector(6958714,24); manlo <= conv_std_logic_vector(127078273,28); exponent <= conv_std_logic_vector(1526,11); WHEN "0101011110" => manhi <= conv_std_logic_vector(15483258,24); manlo <= conv_std_logic_vector(65420394,28); exponent <= conv_std_logic_vector(1527,11); WHEN "0101011111" => manhi <= conv_std_logic_vector(5146049,24); manlo <= conv_std_logic_vector(61347424,28); exponent <= conv_std_logic_vector(1529,11); WHEN "0101100000" => manhi <= conv_std_logic_vector(13019590,24); manlo <= conv_std_logic_vector(200148168,28); exponent <= conv_std_logic_vector(1530,11); WHEN "0101100001" => manhi <= conv_std_logic_vector(3471813,24); manlo <= conv_std_logic_vector(155873600,28); exponent <= conv_std_logic_vector(1532,11); WHEN "0101100010" => manhi <= conv_std_logic_vector(10744068,24); manlo <= conv_std_logic_vector(154763366,28); exponent <= conv_std_logic_vector(1533,11); WHEN "0101100011" => manhi <= conv_std_logic_vector(1925435,24); manlo <= conv_std_logic_vector(252346422,28); exponent <= conv_std_logic_vector(1535,11); WHEN "0101100100" => manhi <= conv_std_logic_vector(8642323,24); manlo <= conv_std_logic_vector(122496413,28); exponent <= conv_std_logic_vector(1536,11); WHEN "0101100101" => manhi <= conv_std_logic_vector(497152,24); manlo <= conv_std_logic_vector(12881703,28); exponent <= conv_std_logic_vector(1538,11); WHEN "0101100110" => manhi <= conv_std_logic_vector(6701084,24); manlo <= conv_std_logic_vector(102402698,28); exponent <= conv_std_logic_vector(1539,11); WHEN "0101100111" => manhi <= conv_std_logic_vector(15133102,24); manlo <= conv_std_logic_vector(173151546,28); exponent <= conv_std_logic_vector(1540,11); WHEN "0101101000" => manhi <= conv_std_logic_vector(4908093,24); manlo <= conv_std_logic_vector(222341698,28); exponent <= conv_std_logic_vector(1542,11); WHEN "0101101001" => manhi <= conv_std_logic_vector(12696175,24); manlo <= conv_std_logic_vector(221558290,28); exponent <= conv_std_logic_vector(1543,11); WHEN "0101101010" => manhi <= conv_std_logic_vector(3252030,24); manlo <= conv_std_logic_vector(95425703,28); exponent <= conv_std_logic_vector(1545,11); WHEN "0101101011" => manhi <= conv_std_logic_vector(10445352,24); manlo <= conv_std_logic_vector(54472775,28); exponent <= conv_std_logic_vector(1546,11); WHEN "0101101100" => manhi <= conv_std_logic_vector(1722437,24); manlo <= conv_std_logic_vector(31541381,28); exponent <= conv_std_logic_vector(1548,11); WHEN "0101101101" => manhi <= conv_std_logic_vector(8366419,24); manlo <= conv_std_logic_vector(121077564,28); exponent <= conv_std_logic_vector(1549,11); WHEN "0101101110" => manhi <= conv_std_logic_vector(309655,24); manlo <= conv_std_logic_vector(224679493,28); exponent <= conv_std_logic_vector(1551,11); WHEN "0101101111" => manhi <= conv_std_logic_vector(6446250,24); manlo <= conv_std_logic_vector(163707479,28); exponent <= conv_std_logic_vector(1552,11); WHEN "0101110000" => manhi <= conv_std_logic_vector(14786747,24); manlo <= conv_std_logic_vector(171718440,28); exponent <= conv_std_logic_vector(1553,11); WHEN "0101110001" => manhi <= conv_std_logic_vector(4672721,24); manlo <= conv_std_logic_vector(53414720,28); exponent <= conv_std_logic_vector(1555,11); WHEN "0101110010" => manhi <= conv_std_logic_vector(12376271,24); manlo <= conv_std_logic_vector(68395953,28); exponent <= conv_std_logic_vector(1556,11); WHEN "0101110011" => manhi <= conv_std_logic_vector(3034632,24); manlo <= conv_std_logic_vector(177229210,28); exponent <= conv_std_logic_vector(1558,11); WHEN "0101110100" => manhi <= conv_std_logic_vector(10149878,24); manlo <= conv_std_logic_vector(27015960,28); exponent <= conv_std_logic_vector(1559,11); WHEN "0101110101" => manhi <= conv_std_logic_vector(1521641,24); manlo <= conv_std_logic_vector(173609470,28); exponent <= conv_std_logic_vector(1561,11); WHEN "0101110110" => manhi <= conv_std_logic_vector(8093510,24); manlo <= conv_std_logic_vector(29891310,28); exponent <= conv_std_logic_vector(1562,11); WHEN "0101110111" => manhi <= conv_std_logic_vector(124194,24); manlo <= conv_std_logic_vector(191198183,28); exponent <= conv_std_logic_vector(1564,11); WHEN "0101111000" => manhi <= conv_std_logic_vector(6194182,24); manlo <= conv_std_logic_vector(216692261,28); exponent <= conv_std_logic_vector(1565,11); WHEN "0101111001" => manhi <= conv_std_logic_vector(14444151,24); manlo <= conv_std_logic_vector(261994424,28); exponent <= conv_std_logic_vector(1566,11); WHEN "0101111010" => manhi <= conv_std_logic_vector(4439903,24); manlo <= conv_std_logic_vector(82463931,28); exponent <= conv_std_logic_vector(1568,11); WHEN "0101111011" => manhi <= conv_std_logic_vector(12059838,24); manlo <= conv_std_logic_vector(250318074,28); exponent <= conv_std_logic_vector(1569,11); WHEN "0101111100" => manhi <= conv_std_logic_vector(2819594,24); manlo <= conv_std_logic_vector(161686084,28); exponent <= conv_std_logic_vector(1571,11); WHEN "0101111101" => manhi <= conv_std_logic_vector(9857611,24); manlo <= conv_std_logic_vector(20946108,28); exponent <= conv_std_logic_vector(1572,11); WHEN "0101111110" => manhi <= conv_std_logic_vector(1323025,24); manlo <= conv_std_logic_vector(164440795,28); exponent <= conv_std_logic_vector(1574,11); WHEN "0101111111" => manhi <= conv_std_logic_vector(7823562,24); manlo <= conv_std_logic_vector(250479918,28); exponent <= conv_std_logic_vector(1575,11); WHEN "0110000000" => manhi <= conv_std_logic_vector(16658709,24); manlo <= conv_std_logic_vector(45608811,28); exponent <= conv_std_logic_vector(1576,11); WHEN "0110000001" => manhi <= conv_std_logic_vector(5944850,24); manlo <= conv_std_logic_vector(255488281,28); exponent <= conv_std_logic_vector(1578,11); WHEN "0110000010" => manhi <= conv_std_logic_vector(14105274,24); manlo <= conv_std_logic_vector(228172930,28); exponent <= conv_std_logic_vector(1579,11); WHEN "0110000011" => manhi <= conv_std_logic_vector(4209612,24); manlo <= conv_std_logic_vector(113758652,28); exponent <= conv_std_logic_vector(1581,11); WHEN "0110000100" => manhi <= conv_std_logic_vector(11746841,24); manlo <= conv_std_logic_vector(45816542,28); exponent <= conv_std_logic_vector(1582,11); WHEN "0110000101" => manhi <= conv_std_logic_vector(2606890,24); manlo <= conv_std_logic_vector(153074390,28); exponent <= conv_std_logic_vector(1584,11); WHEN "0110000110" => manhi <= conv_std_logic_vector(9568516,24); manlo <= conv_std_logic_vector(87350878,28); exponent <= conv_std_logic_vector(1585,11); WHEN "0110000111" => manhi <= conv_std_logic_vector(1126565,24); manlo <= conv_std_logic_vector(96475766,28); exponent <= conv_std_logic_vector(1587,11); WHEN "0110001000" => manhi <= conv_std_logic_vector(7556545,24); manlo <= conv_std_logic_vector(205347948,28); exponent <= conv_std_logic_vector(1588,11); WHEN "0110001001" => manhi <= conv_std_logic_vector(16295795,24); manlo <= conv_std_logic_vector(56881285,28); exponent <= conv_std_logic_vector(1589,11); WHEN "0110001010" => manhi <= conv_std_logic_vector(5698225,24); manlo <= conv_std_logic_vector(93263076,28); exponent <= conv_std_logic_vector(1591,11); WHEN "0110001011" => manhi <= conv_std_logic_vector(13770075,24); manlo <= conv_std_logic_vector(241769289,28); exponent <= conv_std_logic_vector(1592,11); WHEN "0110001100" => manhi <= conv_std_logic_vector(3981821,24); manlo <= conv_std_logic_vector(32359920,28); exponent <= conv_std_logic_vector(1594,11); WHEN "0110001101" => manhi <= conv_std_logic_vector(11437240,24); manlo <= conv_std_logic_vector(185367850,28); exponent <= conv_std_logic_vector(1595,11); WHEN "0110001110" => manhi <= conv_std_logic_vector(2396495,24); manlo <= conv_std_logic_vector(61858550,28); exponent <= conv_std_logic_vector(1597,11); WHEN "0110001111" => manhi <= conv_std_logic_vector(9282559,24); manlo <= conv_std_logic_vector(110304027,28); exponent <= conv_std_logic_vector(1598,11); WHEN "0110010000" => manhi <= conv_std_logic_vector(932237,24); manlo <= conv_std_logic_vector(131077892,28); exponent <= conv_std_logic_vector(1600,11); WHEN "0110010001" => manhi <= conv_std_logic_vector(7292426,24); manlo <= conv_std_logic_vector(215982528,28); exponent <= conv_std_logic_vector(1601,11); WHEN "0110010010" => manhi <= conv_std_logic_vector(15936820,24); manlo <= conv_std_logic_vector(87676082,28); exponent <= conv_std_logic_vector(1602,11); WHEN "0110010011" => manhi <= conv_std_logic_vector(5454276,24); manlo <= conv_std_logic_vector(166577430,28); exponent <= conv_std_logic_vector(1604,11); WHEN "0110010100" => manhi <= conv_std_logic_vector(13438515,24); manlo <= conv_std_logic_vector(55023964,28); exponent <= conv_std_logic_vector(1605,11); WHEN "0110010101" => manhi <= conv_std_logic_vector(3756502,24); manlo <= conv_std_logic_vector(71679026,28); exponent <= conv_std_logic_vector(1607,11); WHEN "0110010110" => manhi <= conv_std_logic_vector(11131000,24); manlo <= conv_std_logic_vector(165886683,28); exponent <= conv_std_logic_vector(1608,11); WHEN "0110010111" => manhi <= conv_std_logic_vector(2188383,24); manlo <= conv_std_logic_vector(140750309,28); exponent <= conv_std_logic_vector(1610,11); WHEN "0110011000" => manhi <= conv_std_logic_vector(8999706,24); manlo <= conv_std_logic_vector(74200045,28); exponent <= conv_std_logic_vector(1611,11); WHEN "0110011001" => manhi <= conv_std_logic_vector(740018,24); manlo <= conv_std_logic_vector(229350227,28); exponent <= conv_std_logic_vector(1613,11); WHEN "0110011010" => manhi <= conv_std_logic_vector(7031174,24); manlo <= conv_std_logic_vector(159659309,28); exponent <= conv_std_logic_vector(1614,11); WHEN "0110011011" => manhi <= conv_std_logic_vector(15581741,24); manlo <= conv_std_logic_vector(203828183,28); exponent <= conv_std_logic_vector(1615,11); WHEN "0110011100" => manhi <= conv_std_logic_vector(5212975,24); manlo <= conv_std_logic_vector(192268981,28); exponent <= conv_std_logic_vector(1617,11); WHEN "0110011101" => manhi <= conv_std_logic_vector(13110553,24); manlo <= conv_std_logic_vector(73367990,28); exponent <= conv_std_logic_vector(1618,11); WHEN "0110011110" => manhi <= conv_std_logic_vector(3533629,24); manlo <= conv_std_logic_vector(7303751,28); exponent <= conv_std_logic_vector(1620,11); WHEN "0110011111" => manhi <= conv_std_logic_vector(10828084,24); manlo <= conv_std_logic_vector(128595197,28); exponent <= conv_std_logic_vector(1621,11); WHEN "0110100000" => manhi <= conv_std_logic_vector(1982530,24); manlo <= conv_std_logic_vector(178601213,28); exponent <= conv_std_logic_vector(1623,11); WHEN "0110100001" => manhi <= conv_std_logic_vector(8719923,24); manlo <= conv_std_logic_vector(62665264,28); exponent <= conv_std_logic_vector(1624,11); WHEN "0110100010" => manhi <= conv_std_logic_vector(549886,24); manlo <= conv_std_logic_vector(151395401,28); exponent <= conv_std_logic_vector(1626,11); WHEN "0110100011" => manhi <= conv_std_logic_vector(6772758,24); manlo <= conv_std_logic_vector(5307652,28); exponent <= conv_std_logic_vector(1627,11); WHEN "0110100100" => manhi <= conv_std_logic_vector(15230517,24); manlo <= conv_std_logic_vector(58871965,28); exponent <= conv_std_logic_vector(1628,11); WHEN "0110100101" => manhi <= conv_std_logic_vector(4974293,24); manlo <= conv_std_logic_vector(240265124,28); exponent <= conv_std_logic_vector(1630,11); WHEN "0110100110" => manhi <= conv_std_logic_vector(12786151,24); manlo <= conv_std_logic_vector(11983156,28); exponent <= conv_std_logic_vector(1631,11); WHEN "0110100111" => manhi <= conv_std_logic_vector(3313174,24); manlo <= conv_std_logic_vector(229882212,28); exponent <= conv_std_logic_vector(1633,11); WHEN "0110101000" => manhi <= conv_std_logic_vector(10528456,24); manlo <= conv_std_logic_vector(52550536,28); exponent <= conv_std_logic_vector(1634,11); WHEN "0110101001" => manhi <= conv_std_logic_vector(1778912,24); manlo <= conv_std_logic_vector(36481057,28); exponent <= conv_std_logic_vector(1636,11); WHEN "0110101010" => manhi <= conv_std_logic_vector(8443176,24); manlo <= conv_std_logic_vector(257480801,28); exponent <= conv_std_logic_vector(1637,11); WHEN "0110101011" => manhi <= conv_std_logic_vector(361817,24); manlo <= conv_std_logic_vector(260890045,28); exponent <= conv_std_logic_vector(1639,11); WHEN "0110101100" => manhi <= conv_std_logic_vector(6517146,24); manlo <= conv_std_logic_vector(80951272,28); exponent <= conv_std_logic_vector(1640,11); WHEN "0110101101" => manhi <= conv_std_logic_vector(14883104,24); manlo <= conv_std_logic_vector(234866389,28); exponent <= conv_std_logic_vector(1641,11); WHEN "0110101110" => manhi <= conv_std_logic_vector(4738202,24); manlo <= conv_std_logic_vector(195793257,28); exponent <= conv_std_logic_vector(1643,11); WHEN "0110101111" => manhi <= conv_std_logic_vector(12465269,24); manlo <= conv_std_logic_vector(236730454,28); exponent <= conv_std_logic_vector(1644,11); WHEN "0110110000" => manhi <= conv_std_logic_vector(3095113,24); manlo <= conv_std_logic_vector(133661452,28); exponent <= conv_std_logic_vector(1646,11); WHEN "0110110001" => manhi <= conv_std_logic_vector(10232080,24); manlo <= conv_std_logic_vector(21926822,28); exponent <= conv_std_logic_vector(1647,11); WHEN "0110110010" => manhi <= conv_std_logic_vector(1577503,24); manlo <= conv_std_logic_vector(183764948,28); exponent <= conv_std_logic_vector(1649,11); WHEN "0110110011" => manhi <= conv_std_logic_vector(8169434,24); manlo <= conv_std_logic_vector(132210812,28); exponent <= conv_std_logic_vector(1650,11); WHEN "0110110100" => manhi <= conv_std_logic_vector(175790,24); manlo <= conv_std_logic_vector(182183516,28); exponent <= conv_std_logic_vector(1652,11); WHEN "0110110101" => manhi <= conv_std_logic_vector(6264308,24); manlo <= conv_std_logic_vector(267417858,28); exponent <= conv_std_logic_vector(1653,11); WHEN "0110110110" => manhi <= conv_std_logic_vector(14539463,24); manlo <= conv_std_logic_vector(93573944,28); exponent <= conv_std_logic_vector(1654,11); WHEN "0110110111" => manhi <= conv_std_logic_vector(4504674,24); manlo <= conv_std_logic_vector(26907375,28); exponent <= conv_std_logic_vector(1656,11); WHEN "0110111000" => manhi <= conv_std_logic_vector(12147871,24); manlo <= conv_std_logic_vector(152302066,28); exponent <= conv_std_logic_vector(1657,11); WHEN "0110111001" => manhi <= conv_std_logic_vector(2879418,24); manlo <= conv_std_logic_vector(263131635,28); exponent <= conv_std_logic_vector(1659,11); WHEN "0110111010" => manhi <= conv_std_logic_vector(9938920,24); manlo <= conv_std_logic_vector(224874222,28); exponent <= conv_std_logic_vector(1660,11); WHEN "0110111011" => manhi <= conv_std_logic_vector(1378281,24); manlo <= conv_std_logic_vector(86745210,28); exponent <= conv_std_logic_vector(1662,11); WHEN "0110111100" => manhi <= conv_std_logic_vector(7898663,24); manlo <= conv_std_logic_vector(61761420,28); exponent <= conv_std_logic_vector(1663,11); WHEN "0110111101" => manhi <= conv_std_logic_vector(16760781,24); manlo <= conv_std_logic_vector(15082626,28); exponent <= conv_std_logic_vector(1664,11); WHEN "0110111110" => manhi <= conv_std_logic_vector(6014215,24); manlo <= conv_std_logic_vector(265801199,28); exponent <= conv_std_logic_vector(1666,11); WHEN "0110111111" => manhi <= conv_std_logic_vector(14199551,24); manlo <= conv_std_logic_vector(191056853,28); exponent <= conv_std_logic_vector(1667,11); WHEN "0111000000" => manhi <= conv_std_logic_vector(4273680,24); manlo <= conv_std_logic_vector(52024524,28); exponent <= conv_std_logic_vector(1669,11); WHEN "0111000001" => manhi <= conv_std_logic_vector(11833918,24); manlo <= conv_std_logic_vector(80047690,28); exponent <= conv_std_logic_vector(1670,11); WHEN "0111000010" => manhi <= conv_std_logic_vector(2666065,24); manlo <= conv_std_logic_vector(164712049,28); exponent <= conv_std_logic_vector(1672,11); WHEN "0111000011" => manhi <= conv_std_logic_vector(9648943,24); manlo <= conv_std_logic_vector(147084012,28); exponent <= conv_std_logic_vector(1673,11); WHEN "0111000100" => manhi <= conv_std_logic_vector(1181221,24); manlo <= conv_std_logic_vector(86912647,28); exponent <= conv_std_logic_vector(1675,11); WHEN "0111000101" => manhi <= conv_std_logic_vector(7630830,24); manlo <= conv_std_logic_vector(247596521,28); exponent <= conv_std_logic_vector(1676,11); WHEN "0111000110" => manhi <= conv_std_logic_vector(16396759,24); manlo <= conv_std_logic_vector(56002502,28); exponent <= conv_std_logic_vector(1677,11); WHEN "0111000111" => manhi <= conv_std_logic_vector(5766837,24); manlo <= conv_std_logic_vector(133369322,28); exponent <= conv_std_logic_vector(1679,11); WHEN "0111001000" => manhi <= conv_std_logic_vector(13863329,24); manlo <= conv_std_logic_vector(128884889,28); exponent <= conv_std_logic_vector(1680,11); WHEN "0111001001" => manhi <= conv_std_logic_vector(4045193,24); manlo <= conv_std_logic_vector(133729186,28); exponent <= conv_std_logic_vector(1682,11); WHEN "0111001010" => manhi <= conv_std_logic_vector(11523372,24); manlo <= conv_std_logic_vector(183024104,28); exponent <= conv_std_logic_vector(1683,11); WHEN "0111001011" => manhi <= conv_std_logic_vector(2455027,24); manlo <= conv_std_logic_vector(264977965,28); exponent <= conv_std_logic_vector(1685,11); WHEN "0111001100" => manhi <= conv_std_logic_vector(9362113,24); manlo <= conv_std_logic_vector(181285013,28); exponent <= conv_std_logic_vector(1686,11); WHEN "0111001101" => manhi <= conv_std_logic_vector(986300,24); manlo <= conv_std_logic_vector(58020653,28); exponent <= conv_std_logic_vector(1688,11); WHEN "0111001110" => manhi <= conv_std_logic_vector(7365905,24); manlo <= conv_std_logic_vector(179835810,28); exponent <= conv_std_logic_vector(1689,11); WHEN "0111001111" => manhi <= conv_std_logic_vector(16036688,24); manlo <= conv_std_logic_vector(123168298,28); exponent <= conv_std_logic_vector(1690,11); WHEN "0111010000" => manhi <= conv_std_logic_vector(5522144,24); manlo <= conv_std_logic_vector(14176725,28); exponent <= conv_std_logic_vector(1692,11); WHEN "0111010001" => manhi <= conv_std_logic_vector(13530756,24); manlo <= conv_std_logic_vector(163453775,28); exponent <= conv_std_logic_vector(1693,11); WHEN "0111010010" => manhi <= conv_std_logic_vector(3819186,24); manlo <= conv_std_logic_vector(214764608,28); exponent <= conv_std_logic_vector(1695,11); WHEN "0111010011" => manhi <= conv_std_logic_vector(11216197,24); manlo <= conv_std_logic_vector(196364225,28); exponent <= conv_std_logic_vector(1696,11); WHEN "0111010100" => manhi <= conv_std_logic_vector(2246280,24); manlo <= conv_std_logic_vector(259235483,28); exponent <= conv_std_logic_vector(1698,11); WHEN "0111010101" => manhi <= conv_std_logic_vector(9078397,24); manlo <= conv_std_logic_vector(15526664,28); exponent <= conv_std_logic_vector(1699,11); WHEN "0111010110" => manhi <= conv_std_logic_vector(793494,24); manlo <= conv_std_logic_vector(210641201,28); exponent <= conv_std_logic_vector(1701,11); WHEN "0111010111" => manhi <= conv_std_logic_vector(7103855,24); manlo <= conv_std_logic_vector(246847656,28); exponent <= conv_std_logic_vector(1702,11); WHEN "0111011000" => manhi <= conv_std_logic_vector(15680525,24); manlo <= conv_std_logic_vector(247378795,28); exponent <= conv_std_logic_vector(1703,11); WHEN "0111011001" => manhi <= conv_std_logic_vector(5280106,24); manlo <= conv_std_logic_vector(138122391,28); exponent <= conv_std_logic_vector(1705,11); WHEN "0111011010" => manhi <= conv_std_logic_vector(13201793,24); manlo <= conv_std_logic_vector(130963079,28); exponent <= conv_std_logic_vector(1706,11); WHEN "0111011011" => manhi <= conv_std_logic_vector(3595633,24); manlo <= conv_std_logic_vector(48727293,28); exponent <= conv_std_logic_vector(1708,11); WHEN "0111011100" => manhi <= conv_std_logic_vector(10912356,24); manlo <= conv_std_logic_vector(231400966,28); exponent <= conv_std_logic_vector(1709,11); WHEN "0111011101" => manhi <= conv_std_logic_vector(2039799,24); manlo <= conv_std_logic_vector(184459756,28); exponent <= conv_std_logic_vector(1711,11); WHEN "0111011110" => manhi <= conv_std_logic_vector(8797759,24); manlo <= conv_std_logic_vector(242699544,28); exponent <= conv_std_logic_vector(1712,11); WHEN "0111011111" => manhi <= conv_std_logic_vector(602782,24); manlo <= conv_std_logic_vector(17680793,28); exponent <= conv_std_logic_vector(1714,11); WHEN "0111100000" => manhi <= conv_std_logic_vector(6844650,24); manlo <= conv_std_logic_vector(123627565,28); exponent <= conv_std_logic_vector(1715,11); WHEN "0111100001" => manhi <= conv_std_logic_vector(15328229,24); manlo <= conv_std_logic_vector(47512453,28); exponent <= conv_std_logic_vector(1716,11); WHEN "0111100010" => manhi <= conv_std_logic_vector(5040696,24); manlo <= conv_std_logic_vector(14711664,28); exponent <= conv_std_logic_vector(1718,11); WHEN "0111100011" => manhi <= conv_std_logic_vector(12876400,24); manlo <= conv_std_logic_vector(251456186,28); exponent <= conv_std_logic_vector(1719,11); WHEN "0111100100" => manhi <= conv_std_logic_vector(3374506,24); manlo <= conv_std_logic_vector(4512772,28); exponent <= conv_std_logic_vector(1721,11); WHEN "0111100101" => manhi <= conv_std_logic_vector(10611813,24); manlo <= conv_std_logic_vector(237626642,28); exponent <= conv_std_logic_vector(1722,11); WHEN "0111100110" => manhi <= conv_std_logic_vector(1835559,24); manlo <= conv_std_logic_vector(150064655,28); exponent <= conv_std_logic_vector(1724,11); WHEN "0111100111" => manhi <= conv_std_logic_vector(8520168,24); manlo <= conv_std_logic_vector(211971382,28); exponent <= conv_std_logic_vector(1725,11); WHEN "0111101000" => manhi <= conv_std_logic_vector(414139,24); manlo <= conv_std_logic_vector(92694471,28); exponent <= conv_std_logic_vector(1727,11); WHEN "0111101001" => manhi <= conv_std_logic_vector(6588258,24); manlo <= conv_std_logic_vector(112977613,28); exponent <= conv_std_logic_vector(1728,11); WHEN "0111101010" => manhi <= conv_std_logic_vector(14979756,24); manlo <= conv_std_logic_vector(71348470,28); exponent <= conv_std_logic_vector(1729,11); WHEN "0111101011" => manhi <= conv_std_logic_vector(4803884,24); manlo <= conv_std_logic_vector(42747344,28); exponent <= conv_std_logic_vector(1731,11); WHEN "0111101100" => manhi <= conv_std_logic_vector(12554540,24); manlo <= conv_std_logic_vector(53825836,28); exponent <= conv_std_logic_vector(1732,11); WHEN "0111101101" => manhi <= conv_std_logic_vector(3155778,24); manlo <= conv_std_logic_vector(260157975,28); exponent <= conv_std_logic_vector(1734,11); WHEN "0111101110" => manhi <= conv_std_logic_vector(10314533,24); manlo <= conv_std_logic_vector(1535990,28); exponent <= conv_std_logic_vector(1735,11); WHEN "0111101111" => manhi <= conv_std_logic_vector(1633536,24); manlo <= conv_std_logic_vector(68681060,28); exponent <= conv_std_logic_vector(1737,11); WHEN "0111110000" => manhi <= conv_std_logic_vector(8245590,24); manlo <= conv_std_logic_vector(175202070,28); exponent <= conv_std_logic_vector(1738,11); WHEN "0111110001" => manhi <= conv_std_logic_vector(227544,24); manlo <= conv_std_logic_vector(41675965,28); exponent <= conv_std_logic_vector(1740,11); WHEN "0111110010" => manhi <= conv_std_logic_vector(6334649,24); manlo <= conv_std_logic_vector(70777607,28); exponent <= conv_std_logic_vector(1741,11); WHEN "0111110011" => manhi <= conv_std_logic_vector(14635065,24); manlo <= conv_std_logic_vector(183612561,28); exponent <= conv_std_logic_vector(1742,11); WHEN "0111110100" => manhi <= conv_std_logic_vector(4569642,24); manlo <= conv_std_logic_vector(167240760,28); exponent <= conv_std_logic_vector(1744,11); WHEN "0111110101" => manhi <= conv_std_logic_vector(12236172,24); manlo <= conv_std_logic_vector(253623266,28); exponent <= conv_std_logic_vector(1745,11); WHEN "0111110110" => manhi <= conv_std_logic_vector(2939425,24); manlo <= conv_std_logic_vector(265128301,28); exponent <= conv_std_logic_vector(1747,11); WHEN "0111110111" => manhi <= conv_std_logic_vector(10020478,24); manlo <= conv_std_logic_vector(219223569,28); exponent <= conv_std_logic_vector(1748,11); WHEN "0111111000" => manhi <= conv_std_logic_vector(1433705,24); manlo <= conv_std_logic_vector(192250058,28); exponent <= conv_std_logic_vector(1750,11); WHEN "0111111001" => manhi <= conv_std_logic_vector(7973992,24); manlo <= conv_std_logic_vector(212144821,28); exponent <= conv_std_logic_vector(1751,11); WHEN "0111111010" => manhi <= conv_std_logic_vector(42974,24); manlo <= conv_std_logic_vector(72952107,28); exponent <= conv_std_logic_vector(1753,11); WHEN "0111111011" => manhi <= conv_std_logic_vector(6083792,24); manlo <= conv_std_logic_vector(210315148,28); exponent <= conv_std_logic_vector(1754,11); WHEN "0111111100" => manhi <= conv_std_logic_vector(14294116,24); manlo <= conv_std_logic_vector(101520926,28); exponent <= conv_std_logic_vector(1755,11); WHEN "0111111101" => manhi <= conv_std_logic_vector(4337943,24); manlo <= conv_std_logic_vector(146945490,28); exponent <= conv_std_logic_vector(1757,11); WHEN "0111111110" => manhi <= conv_std_logic_vector(11921261,24); manlo <= conv_std_logic_vector(67478049,28); exponent <= conv_std_logic_vector(1758,11); WHEN "0111111111" => manhi <= conv_std_logic_vector(2725421,24); manlo <= conv_std_logic_vector(81662013,28); exponent <= conv_std_logic_vector(1760,11); WHEN "1000000000" => manhi <= conv_std_logic_vector(9729616,24); manlo <= conv_std_logic_vector(79332654,28); exponent <= conv_std_logic_vector(1761,11); WHEN "1000000001" => manhi <= conv_std_logic_vector(1236044,24); manlo <= conv_std_logic_vector(37511845,28); exponent <= conv_std_logic_vector(1763,11); WHEN "1000000010" => manhi <= conv_std_logic_vector(7705342,24); manlo <= conv_std_logic_vector(229400607,28); exponent <= conv_std_logic_vector(1764,11); WHEN "1000000011" => manhi <= conv_std_logic_vector(16498031,24); manlo <= conv_std_logic_vector(113896411,28); exponent <= conv_std_logic_vector(1765,11); WHEN "1000000100" => manhi <= conv_std_logic_vector(5835659,24); manlo <= conv_std_logic_vector(27578100,28); exponent <= conv_std_logic_vector(1767,11); WHEN "1000000101" => manhi <= conv_std_logic_vector(13956867,24); manlo <= conv_std_logic_vector(198774093,28); exponent <= conv_std_logic_vector(1768,11); WHEN "1000000110" => manhi <= conv_std_logic_vector(4108759,24); manlo <= conv_std_logic_vector(90336304,28); exponent <= conv_std_logic_vector(1770,11); WHEN "1000000111" => manhi <= conv_std_logic_vector(11609767,24); manlo <= conv_std_logic_vector(164675818,28); exponent <= conv_std_logic_vector(1771,11); WHEN "1000001000" => manhi <= conv_std_logic_vector(2513739,24); manlo <= conv_std_logic_vector(115510945,28); exponent <= conv_std_logic_vector(1773,11); WHEN "1000001001" => manhi <= conv_std_logic_vector(9441910,24); manlo <= conv_std_logic_vector(214725537,28); exponent <= conv_std_logic_vector(1774,11); WHEN "1000001010" => manhi <= conv_std_logic_vector(1040527,24); manlo <= conv_std_logic_vector(264292986,28); exponent <= conv_std_logic_vector(1776,11); WHEN "1000001011" => manhi <= conv_std_logic_vector(7439608,24); manlo <= conv_std_logic_vector(227819416,28); exponent <= conv_std_logic_vector(1777,11); WHEN "1000001100" => manhi <= conv_std_logic_vector(16136861,24); manlo <= conv_std_logic_vector(124712281,28); exponent <= conv_std_logic_vector(1778,11); WHEN "1000001101" => manhi <= conv_std_logic_vector(5590218,24); manlo <= conv_std_logic_vector(179347558,28); exponent <= conv_std_logic_vector(1780,11); WHEN "1000001110" => manhi <= conv_std_logic_vector(13623279,24); manlo <= conv_std_logic_vector(162081347,28); exponent <= conv_std_logic_vector(1781,11); WHEN "1000001111" => manhi <= conv_std_logic_vector(3882062,24); manlo <= conv_std_logic_vector(186291443,28); exponent <= conv_std_logic_vector(1783,11); WHEN "1000010000" => manhi <= conv_std_logic_vector(11301654,24); manlo <= conv_std_logic_vector(250040022,28); exponent <= conv_std_logic_vector(1784,11); WHEN "1000010001" => manhi <= conv_std_logic_vector(2304355,24); manlo <= conv_std_logic_vector(41383777,28); exponent <= conv_std_logic_vector(1786,11); WHEN "1000010010" => manhi <= conv_std_logic_vector(9157328,24); manlo <= conv_std_logic_vector(17021400,28); exponent <= conv_std_logic_vector(1787,11); WHEN "1000010011" => manhi <= conv_std_logic_vector(847133,24); manlo <= conv_std_logic_vector(258834653,28); exponent <= conv_std_logic_vector(1789,11); WHEN "1000010100" => manhi <= conv_std_logic_vector(7176759,24); manlo <= conv_std_logic_vector(33041815,28); exponent <= conv_std_logic_vector(1790,11); WHEN "1000010101" => manhi <= conv_std_logic_vector(15779611,24); manlo <= conv_std_logic_vector(174007449,28); exponent <= conv_std_logic_vector(1791,11); WHEN "1000010110" => manhi <= conv_std_logic_vector(5347442,24); manlo <= conv_std_logic_vector(66333886,28); exponent <= conv_std_logic_vector(1793,11); WHEN "1000010111" => manhi <= conv_std_logic_vector(13293312,24); manlo <= conv_std_logic_vector(63618366,28); exponent <= conv_std_logic_vector(1794,11); WHEN "1000011000" => manhi <= conv_std_logic_vector(3657826,24); manlo <= conv_std_logic_vector(166348998,28); exponent <= conv_std_logic_vector(1796,11); WHEN "1000011001" => manhi <= conv_std_logic_vector(10996886,24); manlo <= conv_std_logic_vector(136487624,28); exponent <= conv_std_logic_vector(1797,11); WHEN "1000011010" => manhi <= conv_std_logic_vector(2097243,24); manlo <= conv_std_logic_vector(144317262,28); exponent <= conv_std_logic_vector(1799,11); WHEN "1000011011" => manhi <= conv_std_logic_vector(8875834,24); manlo <= conv_std_logic_vector(51419886,28); exponent <= conv_std_logic_vector(1800,11); WHEN "1000011100" => manhi <= conv_std_logic_vector(655839,24); manlo <= conv_std_logic_vector(12096311,28); exponent <= conv_std_logic_vector(1802,11); WHEN "1000011101" => manhi <= conv_std_logic_vector(6916762,24); manlo <= conv_std_logic_vector(99793437,28); exponent <= conv_std_logic_vector(1803,11); WHEN "1000011110" => manhi <= conv_std_logic_vector(15426239,24); manlo <= conv_std_logic_vector(114334116,28); exponent <= conv_std_logic_vector(1804,11); WHEN "1000011111" => manhi <= conv_std_logic_vector(5107300,24); manlo <= conv_std_logic_vector(248161218,28); exponent <= conv_std_logic_vector(1806,11); WHEN "1000100000" => manhi <= conv_std_logic_vector(12966926,24); manlo <= conv_std_logic_vector(91321506,28); exponent <= conv_std_logic_vector(1807,11); WHEN "1000100001" => manhi <= conv_std_logic_vector(3436024,24); manlo <= conv_std_logic_vector(109150055,28); exponent <= conv_std_logic_vector(1809,11); WHEN "1000100010" => manhi <= conv_std_logic_vector(10695426,24); manlo <= conv_std_logic_vector(12291314,28); exponent <= conv_std_logic_vector(1810,11); WHEN "1000100011" => manhi <= conv_std_logic_vector(1892379,24); manlo <= conv_std_logic_vector(245137096,28); exponent <= conv_std_logic_vector(1812,11); WHEN "1000100100" => manhi <= conv_std_logic_vector(8597395,24); manlo <= conv_std_logic_vector(176569250,28); exponent <= conv_std_logic_vector(1813,11); WHEN "1000100101" => manhi <= conv_std_logic_vector(466620,24); manlo <= conv_std_logic_vector(119019308,28); exponent <= conv_std_logic_vector(1815,11); WHEN "1000100110" => manhi <= conv_std_logic_vector(6659587,24); manlo <= conv_std_logic_vector(168706814,28); exponent <= conv_std_logic_vector(1816,11); WHEN "1000100111" => manhi <= conv_std_logic_vector(15076702,24); manlo <= conv_std_logic_vector(190651618,28); exponent <= conv_std_logic_vector(1817,11); WHEN "1000101000" => manhi <= conv_std_logic_vector(4869766,24); manlo <= conv_std_logic_vector(26523901,28); exponent <= conv_std_logic_vector(1819,11); WHEN "1000101001" => manhi <= conv_std_logic_vector(12644083,24); manlo <= conv_std_logic_vector(10760420,28); exponent <= conv_std_logic_vector(1820,11); WHEN "1000101010" => manhi <= conv_std_logic_vector(3216629,24); manlo <= conv_std_logic_vector(171149379,28); exponent <= conv_std_logic_vector(1822,11); WHEN "1000101011" => manhi <= conv_std_logic_vector(10397237,24); manlo <= conv_std_logic_vector(171483537,28); exponent <= conv_std_logic_vector(1823,11); WHEN "1000101100" => manhi <= conv_std_logic_vector(1689739,24); manlo <= conv_std_logic_vector(236540182,28); exponent <= conv_std_logic_vector(1825,11); WHEN "1000101101" => manhi <= conv_std_logic_vector(8321979,24); manlo <= conv_std_logic_vector(80365386,28); exponent <= conv_std_logic_vector(1826,11); WHEN "1000101110" => manhi <= conv_std_logic_vector(279455,24); manlo <= conv_std_logic_vector(167185714,28); exponent <= conv_std_logic_vector(1828,11); WHEN "1000101111" => manhi <= conv_std_logic_vector(6405204,24); manlo <= conv_std_logic_vector(70637708,28); exponent <= conv_std_logic_vector(1829,11); WHEN "1000110000" => manhi <= conv_std_logic_vector(14730959,24); manlo <= conv_std_logic_vector(233674466,28); exponent <= conv_std_logic_vector(1830,11); WHEN "1000110001" => manhi <= conv_std_logic_vector(4634809,24); manlo <= conv_std_logic_vector(128626627,28); exponent <= conv_std_logic_vector(1832,11); WHEN "1000110010" => manhi <= conv_std_logic_vector(12324743,24); manlo <= conv_std_logic_vector(237637056,28); exponent <= conv_std_logic_vector(1833,11); WHEN "1000110011" => manhi <= conv_std_logic_vector(2999616,24); manlo <= conv_std_logic_vector(48899908,28); exponent <= conv_std_logic_vector(1835,11); WHEN "1000110100" => manhi <= conv_std_logic_vector(10102285,24); manlo <= conv_std_logic_vector(207402206,28); exponent <= conv_std_logic_vector(1836,11); WHEN "1000110101" => manhi <= conv_std_logic_vector(1489299,24); manlo <= conv_std_logic_vector(82314533,28); exponent <= conv_std_logic_vector(1838,11); WHEN "1000110110" => manhi <= conv_std_logic_vector(8049552,24); manlo <= conv_std_logic_vector(84197942,28); exponent <= conv_std_logic_vector(1839,11); WHEN "1000110111" => manhi <= conv_std_logic_vector(94322,24); manlo <= conv_std_logic_vector(78275083,28); exponent <= conv_std_logic_vector(1841,11); WHEN "1000111000" => manhi <= conv_std_logic_vector(6153581,24); manlo <= conv_std_logic_vector(262556746,28); exponent <= conv_std_logic_vector(1842,11); WHEN "1000111001" => manhi <= conv_std_logic_vector(14388969,24); manlo <= conv_std_logic_vector(195412276,28); exponent <= conv_std_logic_vector(1843,11); WHEN "1000111010" => manhi <= conv_std_logic_vector(4402403,24); manlo <= conv_std_logic_vector(21925377,28); exponent <= conv_std_logic_vector(1845,11); WHEN "1000111011" => manhi <= conv_std_logic_vector(12008870,24); manlo <= conv_std_logic_vector(225943576,28); exponent <= conv_std_logic_vector(1846,11); WHEN "1000111100" => manhi <= conv_std_logic_vector(2784958,24); manlo <= conv_std_logic_vector(51959162,28); exponent <= conv_std_logic_vector(1848,11); WHEN "1000111101" => manhi <= conv_std_logic_vector(9810535,24); manlo <= conv_std_logic_vector(85297068,28); exponent <= conv_std_logic_vector(1849,11); WHEN "1000111110" => manhi <= conv_std_logic_vector(1291034,24); manlo <= conv_std_logic_vector(85003113,28); exponent <= conv_std_logic_vector(1851,11); WHEN "1000111111" => manhi <= conv_std_logic_vector(7780082,24); manlo <= conv_std_logic_vector(68159752,28); exponent <= conv_std_logic_vector(1852,11); WHEN "1001000000" => manhi <= conv_std_logic_vector(16599612,24); manlo <= conv_std_logic_vector(214703512,28); exponent <= conv_std_logic_vector(1853,11); WHEN "1001000001" => manhi <= conv_std_logic_vector(5904690,24); manlo <= conv_std_logic_vector(215968023,28); exponent <= conv_std_logic_vector(1855,11); WHEN "1001000010" => manhi <= conv_std_logic_vector(14050691,24); manlo <= conv_std_logic_vector(147853227,28); exponent <= conv_std_logic_vector(1856,11); WHEN "1001000011" => manhi <= conv_std_logic_vector(4172519,24); manlo <= conv_std_logic_vector(60716388,28); exponent <= conv_std_logic_vector(1858,11); WHEN "1001000100" => manhi <= conv_std_logic_vector(11696426,24); manlo <= conv_std_logic_vector(77359100,28); exponent <= conv_std_logic_vector(1859,11); WHEN "1001000101" => manhi <= conv_std_logic_vector(2572630,24); manlo <= conv_std_logic_vector(28321055,28); exponent <= conv_std_logic_vector(1861,11); WHEN "1001000110" => manhi <= conv_std_logic_vector(9521951,24); manlo <= conv_std_logic_vector(141206574,28); exponent <= conv_std_logic_vector(1862,11); WHEN "1001000111" => manhi <= conv_std_logic_vector(1094921,24); manlo <= conv_std_logic_vector(79834212,28); exponent <= conv_std_logic_vector(1864,11); WHEN "1001001000" => manhi <= conv_std_logic_vector(7513537,24); manlo <= conv_std_logic_vector(6880382,28); exponent <= conv_std_logic_vector(1865,11); WHEN "1001001001" => manhi <= conv_std_logic_vector(16237340,24); manlo <= conv_std_logic_vector(73707069,28); exponent <= conv_std_logic_vector(1866,11); WHEN "1001001010" => manhi <= conv_std_logic_vector(5658501,24); manlo <= conv_std_logic_vector(26563701,28); exponent <= conv_std_logic_vector(1868,11); WHEN "1001001011" => manhi <= conv_std_logic_vector(13716085,24); manlo <= conv_std_logic_vector(13226359,28); exponent <= conv_std_logic_vector(1869,11); WHEN "1001001100" => manhi <= conv_std_logic_vector(3945130,24); manlo <= conv_std_logic_vector(143073903,28); exponent <= conv_std_logic_vector(1871,11); WHEN "1001001101" => manhi <= conv_std_logic_vector(11387373,24); manlo <= conv_std_logic_vector(3175990,28); exponent <= conv_std_logic_vector(1872,11); WHEN "1001001110" => manhi <= conv_std_logic_vector(2362606,24); manlo <= conv_std_logic_vector(168904878,28); exponent <= conv_std_logic_vector(1874,11); WHEN "1001001111" => manhi <= conv_std_logic_vector(9236500,24); manlo <= conv_std_logic_vector(7105104,28); exponent <= conv_std_logic_vector(1875,11); WHEN "1001010000" => manhi <= conv_std_logic_vector(900936,24); manlo <= conv_std_logic_vector(239272854,28); exponent <= conv_std_logic_vector(1877,11); WHEN "1001010001" => manhi <= conv_std_logic_vector(7249884,24); manlo <= conv_std_logic_vector(236935482,28); exponent <= conv_std_logic_vector(1878,11); WHEN "1001010010" => manhi <= conv_std_logic_vector(15878999,24); manlo <= conv_std_logic_vector(230836932,28); exponent <= conv_std_logic_vector(1879,11); WHEN "1001010011" => manhi <= conv_std_logic_vector(5414983,24); manlo <= conv_std_logic_vector(144840810,28); exponent <= conv_std_logic_vector(1881,11); WHEN "1001010100" => manhi <= conv_std_logic_vector(13385110,24); manlo <= conv_std_logic_vector(99584369,28); exponent <= conv_std_logic_vector(1882,11); WHEN "1001010101" => manhi <= conv_std_logic_vector(3720209,24); manlo <= conv_std_logic_vector(246845719,28); exponent <= conv_std_logic_vector(1884,11); WHEN "1001010110" => manhi <= conv_std_logic_vector(11081674,24); manlo <= conv_std_logic_vector(54674652,28); exponent <= conv_std_logic_vector(1885,11); WHEN "1001010111" => manhi <= conv_std_logic_vector(2154862,24); manlo <= conv_std_logic_vector(201440422,28); exponent <= conv_std_logic_vector(1887,11); WHEN "1001011000" => manhi <= conv_std_logic_vector(8954146,24); manlo <= conv_std_logic_vector(220416825,28); exponent <= conv_std_logic_vector(1888,11); WHEN "1001011001" => manhi <= conv_std_logic_vector(709057,24); manlo <= conv_std_logic_vector(266967657,28); exponent <= conv_std_logic_vector(1890,11); WHEN "1001011010" => manhi <= conv_std_logic_vector(6989094,24); manlo <= conv_std_logic_vector(113654547,28); exponent <= conv_std_logic_vector(1891,11); WHEN "1001011011" => manhi <= conv_std_logic_vector(15524548,24); manlo <= conv_std_logic_vector(235342013,28); exponent <= conv_std_logic_vector(1892,11); WHEN "1001011100" => manhi <= conv_std_logic_vector(5174109,24); manlo <= conv_std_logic_vector(32986511,28); exponent <= conv_std_logic_vector(1894,11); WHEN "1001011101" => manhi <= conv_std_logic_vector(13057728,24); manlo <= conv_std_logic_vector(25787653,28); exponent <= conv_std_logic_vector(1895,11); WHEN "1001011110" => manhi <= conv_std_logic_vector(3497730,24); manlo <= conv_std_logic_vector(160351868,28); exponent <= conv_std_logic_vector(1897,11); WHEN "1001011111" => manhi <= conv_std_logic_vector(10779293,24); manlo <= conv_std_logic_vector(121946709,28); exponent <= conv_std_logic_vector(1898,11); WHEN "1001100000" => manhi <= conv_std_logic_vector(1949373,24); manlo <= conv_std_logic_vector(194974600,28); exponent <= conv_std_logic_vector(1900,11); WHEN "1001100001" => manhi <= conv_std_logic_vector(8674858,24); manlo <= conv_std_logic_vector(75445083,28); exponent <= conv_std_logic_vector(1901,11); WHEN "1001100010" => manhi <= conv_std_logic_vector(519261,24); manlo <= conv_std_logic_vector(202318540,28); exponent <= conv_std_logic_vector(1903,11); WHEN "1001100011" => manhi <= conv_std_logic_vector(6731134,24); manlo <= conv_std_logic_vector(157600610,28); exponent <= conv_std_logic_vector(1904,11); WHEN "1001100100" => manhi <= conv_std_logic_vector(15173945,24); manlo <= conv_std_logic_vector(29256816,28); exponent <= conv_std_logic_vector(1905,11); WHEN "1001100101" => manhi <= conv_std_logic_vector(4935849,24); manlo <= conv_std_logic_vector(42999013,28); exponent <= conv_std_logic_vector(1907,11); WHEN "1001100110" => manhi <= conv_std_logic_vector(12733899,24); manlo <= conv_std_logic_vector(62421287,28); exponent <= conv_std_logic_vector(1908,11); WHEN "1001100111" => manhi <= conv_std_logic_vector(3277666,24); manlo <= conv_std_logic_vector(18399062,28); exponent <= conv_std_logic_vector(1910,11); WHEN "1001101000" => manhi <= conv_std_logic_vector(10480194,24); manlo <= conv_std_logic_vector(201166396,28); exponent <= conv_std_logic_vector(1911,11); WHEN "1001101001" => manhi <= conv_std_logic_vector(1746115,24); manlo <= conv_std_logic_vector(22209480,28); exponent <= conv_std_logic_vector(1913,11); WHEN "1001101010" => manhi <= conv_std_logic_vector(8398601,24); manlo <= conv_std_logic_vector(38216343,28); exponent <= conv_std_logic_vector(1914,11); WHEN "1001101011" => manhi <= conv_std_logic_vector(331525,24); manlo <= conv_std_logic_vector(151310615,28); exponent <= conv_std_logic_vector(1916,11); WHEN "1001101100" => manhi <= conv_std_logic_vector(6475974,24); manlo <= conv_std_logic_vector(174528998,28); exponent <= conv_std_logic_vector(1917,11); WHEN "1001101101" => manhi <= conv_std_logic_vector(14827146,24); manlo <= conv_std_logic_vector(214487191,28); exponent <= conv_std_logic_vector(1918,11); WHEN "1001101110" => manhi <= conv_std_logic_vector(4700175,24); manlo <= conv_std_logic_vector(73593076,28); exponent <= conv_std_logic_vector(1920,11); WHEN "1001101111" => manhi <= conv_std_logic_vector(12413585,24); manlo <= conv_std_logic_vector(56806573,28); exponent <= conv_std_logic_vector(1921,11); WHEN "1001110000" => manhi <= conv_std_logic_vector(3059990,24); manlo <= conv_std_logic_vector(32998071,28); exponent <= conv_std_logic_vector(1923,11); WHEN "1001110001" => manhi <= conv_std_logic_vector(10184342,24); manlo <= conv_std_logic_vector(125003687,28); exponent <= conv_std_logic_vector(1924,11); WHEN "1001110010" => manhi <= conv_std_logic_vector(1545062,24); manlo <= conv_std_logic_vector(164026180,28); exponent <= conv_std_logic_vector(1926,11); WHEN "1001110011" => manhi <= conv_std_logic_vector(8125342,24); manlo <= conv_std_logic_vector(134803968,28); exponent <= conv_std_logic_vector(1927,11); WHEN "1001110100" => manhi <= conv_std_logic_vector(145827,24); manlo <= conv_std_logic_vector(17356019,28); exponent <= conv_std_logic_vector(1929,11); WHEN "1001110101" => manhi <= conv_std_logic_vector(6223584,24); manlo <= conv_std_logic_vector(59711433,28); exponent <= conv_std_logic_vector(1930,11); WHEN "1001110110" => manhi <= conv_std_logic_vector(14484112,24); manlo <= conv_std_logic_vector(172427100,28); exponent <= conv_std_logic_vector(1931,11); WHEN "1001110111" => manhi <= conv_std_logic_vector(4467059,24); manlo <= conv_std_logic_vector(106163660,28); exponent <= conv_std_logic_vector(1933,11); WHEN "1001111000" => manhi <= conv_std_logic_vector(12096747,24); manlo <= conv_std_logic_vector(237074316,28); exponent <= conv_std_logic_vector(1934,11); WHEN "1001111001" => manhi <= conv_std_logic_vector(2844676,24); manlo <= conv_std_logic_vector(224090291,28); exponent <= conv_std_logic_vector(1936,11); WHEN "1001111010" => manhi <= conv_std_logic_vector(9891701,24); manlo <= conv_std_logic_vector(98356275,28); exponent <= conv_std_logic_vector(1937,11); WHEN "1001111011" => manhi <= conv_std_logic_vector(1346192,24); manlo <= conv_std_logic_vector(98098154,28); exponent <= conv_std_logic_vector(1939,11); WHEN "1001111100" => manhi <= conv_std_logic_vector(7855049,24); manlo <= conv_std_logic_vector(218711727,28); exponent <= conv_std_logic_vector(1940,11); WHEN "1001111101" => manhi <= conv_std_logic_vector(16701504,24); manlo <= conv_std_logic_vector(74899902,28); exponent <= conv_std_logic_vector(1941,11); WHEN "1001111110" => manhi <= conv_std_logic_vector(5973933,24); manlo <= conv_std_logic_vector(65399866,28); exponent <= conv_std_logic_vector(1943,11); WHEN "1001111111" => manhi <= conv_std_logic_vector(14144801,24); manlo <= conv_std_logic_vector(210121699,28); exponent <= conv_std_logic_vector(1944,11); WHEN "1010000000" => manhi <= conv_std_logic_vector(4236473,24); manlo <= conv_std_logic_vector(203888522,28); exponent <= conv_std_logic_vector(1946,11); WHEN "1010000001" => manhi <= conv_std_logic_vector(11783349,24); manlo <= conv_std_logic_vector(137203293,28); exponent <= conv_std_logic_vector(1947,11); WHEN "1010000010" => manhi <= conv_std_logic_vector(2631700,24); manlo <= conv_std_logic_vector(150283410,28); exponent <= conv_std_logic_vector(1949,11); WHEN "1010000011" => manhi <= conv_std_logic_vector(9602236,24); manlo <= conv_std_logic_vector(160352104,28); exponent <= conv_std_logic_vector(1950,11); WHEN "1010000100" => manhi <= conv_std_logic_vector(1149480,24); manlo <= conv_std_logic_vector(177173803,28); exponent <= conv_std_logic_vector(1952,11); WHEN "1010000101" => manhi <= conv_std_logic_vector(7587690,24); manlo <= conv_std_logic_vector(238268718,28); exponent <= conv_std_logic_vector(1953,11); WHEN "1010000110" => manhi <= conv_std_logic_vector(16338125,24); manlo <= conv_std_logic_vector(220749839,28); exponent <= conv_std_logic_vector(1954,11); WHEN "1010000111" => manhi <= conv_std_logic_vector(5726991,24); manlo <= conv_std_logic_vector(262994505,28); exponent <= conv_std_logic_vector(1956,11); WHEN "1010001000" => manhi <= conv_std_logic_vector(13809173,24); manlo <= conv_std_logic_vector(216783842,28); exponent <= conv_std_logic_vector(1957,11); WHEN "1010001001" => manhi <= conv_std_logic_vector(4008390,24); manlo <= conv_std_logic_vector(242405077,28); exponent <= conv_std_logic_vector(1959,11); WHEN "1010001010" => manhi <= conv_std_logic_vector(11473352,24); manlo <= conv_std_logic_vector(206426515,28); exponent <= conv_std_logic_vector(1960,11); WHEN "1010001011" => manhi <= conv_std_logic_vector(2421035,24); manlo <= conv_std_logic_vector(250208807,28); exponent <= conv_std_logic_vector(1962,11); WHEN "1010001100" => manhi <= conv_std_logic_vector(9315913,24); manlo <= conv_std_logic_vector(183235034,28); exponent <= conv_std_logic_vector(1963,11); WHEN "1010001101" => manhi <= conv_std_logic_vector(954904,24); manlo <= conv_std_logic_vector(17706469,28); exponent <= conv_std_logic_vector(1965,11); WHEN "1010001110" => manhi <= conv_std_logic_vector(7323233,24); manlo <= conv_std_logic_vector(235600136,28); exponent <= conv_std_logic_vector(1966,11); WHEN "1010001111" => manhi <= conv_std_logic_vector(15978691,24); manlo <= conv_std_logic_vector(128873524,28); exponent <= conv_std_logic_vector(1967,11); WHEN "1010010000" => manhi <= conv_std_logic_vector(5482731,24); manlo <= conv_std_logic_vector(5222268,28); exponent <= conv_std_logic_vector(1969,11); WHEN "1010010001" => manhi <= conv_std_logic_vector(13477188,24); manlo <= conv_std_logic_vector(199372940,28); exponent <= conv_std_logic_vector(1970,11); WHEN "1010010010" => manhi <= conv_std_logic_vector(3782783,24); manlo <= conv_std_logic_vector(177367827,28); exponent <= conv_std_logic_vector(1972,11); WHEN "1010010011" => manhi <= conv_std_logic_vector(11166720,24); manlo <= conv_std_logic_vector(197425116,28); exponent <= conv_std_logic_vector(1973,11); WHEN "1010010100" => manhi <= conv_std_logic_vector(2212657,24); manlo <= conv_std_logic_vector(231097832,28); exponent <= conv_std_logic_vector(1975,11); WHEN "1010010101" => manhi <= conv_std_logic_vector(9032698,24); manlo <= conv_std_logic_vector(139698050,28); exponent <= conv_std_logic_vector(1976,11); WHEN "1010010110" => manhi <= conv_std_logic_vector(762439,24); manlo <= conv_std_logic_vector(109718127,28); exponent <= conv_std_logic_vector(1978,11); WHEN "1010010111" => manhi <= conv_std_logic_vector(7061647,24); manlo <= conv_std_logic_vector(77173752,28); exponent <= conv_std_logic_vector(1979,11); WHEN "1010011000" => manhi <= conv_std_logic_vector(15623158,24); manlo <= conv_std_logic_vector(118851961,28); exponent <= conv_std_logic_vector(1980,11); WHEN "1010011001" => manhi <= conv_std_logic_vector(5241121,24); manlo <= conv_std_logic_vector(72680114,28); exponent <= conv_std_logic_vector(1982,11); WHEN "1010011010" => manhi <= conv_std_logic_vector(13148807,24); manlo <= conv_std_logic_vector(12881486,28); exponent <= conv_std_logic_vector(1983,11); WHEN "1010011011" => manhi <= conv_std_logic_vector(3559625,24); manlo <= conv_std_logic_vector(43579850,28); exponent <= conv_std_logic_vector(1985,11); WHEN "1010011100" => manhi <= conv_std_logic_vector(10863416,24); manlo <= conv_std_logic_vector(238889758,28); exponent <= conv_std_logic_vector(1986,11); WHEN "1010011101" => manhi <= conv_std_logic_vector(2006541,24); manlo <= conv_std_logic_vector(141721451,28); exponent <= conv_std_logic_vector(1988,11); WHEN "1010011110" => manhi <= conv_std_logic_vector(8752557,24); manlo <= conv_std_logic_vector(101792997,28); exponent <= conv_std_logic_vector(1989,11); WHEN "1010011111" => manhi <= conv_std_logic_vector(572063,24); manlo <= conv_std_logic_vector(205445723,28); exponent <= conv_std_logic_vector(1991,11); WHEN "1010100000" => manhi <= conv_std_logic_vector(6802899,24); manlo <= conv_std_logic_vector(258099270,28); exponent <= conv_std_logic_vector(1992,11); WHEN "1010100001" => manhi <= conv_std_logic_vector(15271484,24); manlo <= conv_std_logic_vector(98124990,28); exponent <= conv_std_logic_vector(1993,11); WHEN "1010100010" => manhi <= conv_std_logic_vector(5002133,24); manlo <= conv_std_logic_vector(256985826,28); exponent <= conv_std_logic_vector(1995,11); WHEN "1010100011" => manhi <= conv_std_logic_vector(12823989,24); manlo <= conv_std_logic_vector(164377270,28); exponent <= conv_std_logic_vector(1996,11); WHEN "1010100100" => manhi <= conv_std_logic_vector(3338888,24); manlo <= conv_std_logic_vector(222569178,28); exponent <= conv_std_logic_vector(1998,11); WHEN "1010100101" => manhi <= conv_std_logic_vector(10563405,24); manlo <= conv_std_logic_vector(29046646,28); exponent <= conv_std_logic_vector(1999,11); WHEN "1010100110" => manhi <= conv_std_logic_vector(1802662,24); manlo <= conv_std_logic_vector(103161316,28); exponent <= conv_std_logic_vector(2001,11); WHEN "1010100111" => manhi <= conv_std_logic_vector(8475456,24); manlo <= conv_std_logic_vector(239852126,28); exponent <= conv_std_logic_vector(2002,11); WHEN "1010101000" => manhi <= conv_std_logic_vector(383754,24); manlo <= conv_std_logic_vector(123914668,28); exponent <= conv_std_logic_vector(2004,11); WHEN "1010101001" => manhi <= conv_std_logic_vector(6546961,24); manlo <= conv_std_logic_vector(22084044,28); exponent <= conv_std_logic_vector(2005,11); WHEN "1010101010" => manhi <= conv_std_logic_vector(14923627,24); manlo <= conv_std_logic_vector(97508377,28); exponent <= conv_std_logic_vector(2006,11); WHEN "1010101011" => manhi <= conv_std_logic_vector(4765740,24); manlo <= conv_std_logic_vector(165164368,28); exponent <= conv_std_logic_vector(2008,11); WHEN "1010101100" => manhi <= conv_std_logic_vector(12502697,24); manlo <= conv_std_logic_vector(201140216,28); exponent <= conv_std_logic_vector(2009,11); WHEN "1010101101" => manhi <= conv_std_logic_vector(3120548,24); manlo <= conv_std_logic_vector(99561759,28); exponent <= conv_std_logic_vector(2011,11); WHEN "1010101110" => manhi <= conv_std_logic_vector(10266649,24); manlo <= conv_std_logic_vector(176679877,28); exponent <= conv_std_logic_vector(2012,11); WHEN "1010101111" => manhi <= conv_std_logic_vector(1600996,24); manlo <= conv_std_logic_vector(39589446,28); exponent <= conv_std_logic_vector(2014,11); WHEN "1010110000" => manhi <= conv_std_logic_vector(8201364,24); manlo <= conv_std_logic_vector(16114999,28); exponent <= conv_std_logic_vector(2015,11); WHEN "1010110001" => manhi <= conv_std_logic_vector(197489,24); manlo <= conv_std_logic_vector(18649371,28); exponent <= conv_std_logic_vector(2017,11); WHEN "1010110010" => manhi <= conv_std_logic_vector(6293800,24); manlo <= conv_std_logic_vector(44802372,28); exponent <= conv_std_logic_vector(2018,11); WHEN "1010110011" => manhi <= conv_std_logic_vector(14579546,24); manlo <= conv_std_logic_vector(1419236,28); exponent <= conv_std_logic_vector(2019,11); WHEN "1010110100" => manhi <= conv_std_logic_vector(4531913,24); manlo <= conv_std_logic_vector(24044223,28); exponent <= conv_std_logic_vector(2021,11); WHEN "1010110101" => manhi <= conv_std_logic_vector(12184893,24); manlo <= conv_std_logic_vector(51602800,28); exponent <= conv_std_logic_vector(2022,11); WHEN "1010110110" => manhi <= conv_std_logic_vector(2904577,24); manlo <= conv_std_logic_vector(210124577,28); exponent <= conv_std_logic_vector(2024,11); WHEN "1010110111" => manhi <= conv_std_logic_vector(9973115,24); manlo <= conv_std_logic_vector(52505388,28); exponent <= conv_std_logic_vector(2025,11); WHEN "1010111000" => manhi <= conv_std_logic_vector(1401518,24); manlo <= conv_std_logic_vector(214362802,28); exponent <= conv_std_logic_vector(2027,11); WHEN "1010111001" => manhi <= conv_std_logic_vector(7930246,24); manlo <= conv_std_logic_vector(62721516,28); exponent <= conv_std_logic_vector(2028,11); WHEN "1010111010" => manhi <= conv_std_logic_vector(13245,24); manlo <= conv_std_logic_vector(108520727,28); exponent <= conv_std_logic_vector(2030,11); WHEN "1010111011" => manhi <= conv_std_logic_vector(6043387,24); manlo <= conv_std_logic_vector(17001813,28); exponent <= conv_std_logic_vector(2031,11); WHEN "1010111100" => manhi <= conv_std_logic_vector(14239199,24); manlo <= conv_std_logic_vector(83422350,28); exponent <= conv_std_logic_vector(2032,11); WHEN "1010111101" => manhi <= conv_std_logic_vector(4300623,24); manlo <= conv_std_logic_vector(142486326,28); exponent <= conv_std_logic_vector(2034,11); WHEN "1010111110" => manhi <= conv_std_logic_vector(11870538,24); manlo <= conv_std_logic_vector(24126621,28); exponent <= conv_std_logic_vector(2035,11); WHEN "1010111111" => manhi <= conv_std_logic_vector(2690951,24); manlo <= conv_std_logic_vector(91850592,28); exponent <= conv_std_logic_vector(2037,11); WHEN "1011000000" => manhi <= conv_std_logic_vector(9682766,24); manlo <= conv_std_logic_vector(203960059,28); exponent <= conv_std_logic_vector(2038,11); WHEN "1011000001" => manhi <= conv_std_logic_vector(1204206,24); manlo <= conv_std_logic_vector(155513539,28); exponent <= conv_std_logic_vector(2040,11); WHEN "1011000010" => manhi <= conv_std_logic_vector(7662071,24); manlo <= conv_std_logic_vector(33184566,28); exponent <= conv_std_logic_vector(2041,11); WHEN "1011000011" => manhi <= conv_std_logic_vector(16439219,24); manlo <= conv_std_logic_vector(11896414,28); exponent <= conv_std_logic_vector(2042,11); WHEN "1011000100" => manhi <= conv_std_logic_vector(5795691,24); manlo <= conv_std_logic_vector(254151921,28); exponent <= conv_std_logic_vector(2044,11); WHEN "1011000101" => manhi <= conv_std_logic_vector(13902546,24); manlo <= conv_std_logic_vector(199613595,28); exponent <= conv_std_logic_vector(2045,11); WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_explutpos IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_explutpos; ARCHITECTURE rtl OF dp_explutpos IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(1023,11); WHEN "0000000001" => manhi <= conv_std_logic_vector(6025384,24); manlo <= conv_std_logic_vector(185882474,28); exponent <= conv_std_logic_vector(1024,11); WHEN "0000000010" => manhi <= conv_std_logic_vector(14214731,24); manlo <= conv_std_logic_vector(148168110,28); exponent <= conv_std_logic_vector(1025,11); WHEN "0000000011" => manhi <= conv_std_logic_vector(4283995,24); manlo <= conv_std_logic_vector(258978054,28); exponent <= conv_std_logic_vector(1027,11); WHEN "0000000100" => manhi <= conv_std_logic_vector(11847938,24); manlo <= conv_std_logic_vector(237451864,28); exponent <= conv_std_logic_vector(1028,11); WHEN "0000000101" => manhi <= conv_std_logic_vector(2675593,24); manlo <= conv_std_logic_vector(158348175,28); exponent <= conv_std_logic_vector(1030,11); WHEN "0000000110" => manhi <= conv_std_logic_vector(9661893,24); manlo <= conv_std_logic_vector(110149775,28); exponent <= conv_std_logic_vector(1031,11); WHEN "0000000111" => manhi <= conv_std_logic_vector(1190021,24); manlo <= conv_std_logic_vector(179232170,28); exponent <= conv_std_logic_vector(1033,11); WHEN "0000001000" => manhi <= conv_std_logic_vector(7642791,24); manlo <= conv_std_logic_vector(222760046,28); exponent <= conv_std_logic_vector(1034,11); WHEN "0000001001" => manhi <= conv_std_logic_vector(16413015,24); manlo <= conv_std_logic_vector(205983618,28); exponent <= conv_std_logic_vector(1035,11); WHEN "0000001010" => manhi <= conv_std_logic_vector(5777884,24); manlo <= conv_std_logic_vector(261424480,28); exponent <= conv_std_logic_vector(1037,11); WHEN "0000001011" => manhi <= conv_std_logic_vector(13878344,24); manlo <= conv_std_logic_vector(149835647,28); exponent <= conv_std_logic_vector(1038,11); WHEN "0000001100" => manhi <= conv_std_logic_vector(4055397,24); manlo <= conv_std_logic_vector(80968858,28); exponent <= conv_std_logic_vector(1040,11); WHEN "0000001101" => manhi <= conv_std_logic_vector(11537241,24); manlo <= conv_std_logic_vector(23775573,28); exponent <= conv_std_logic_vector(1041,11); WHEN "0000001110" => manhi <= conv_std_logic_vector(2464452,24); manlo <= conv_std_logic_vector(146736599,28); exponent <= conv_std_logic_vector(1043,11); WHEN "0000001111" => manhi <= conv_std_logic_vector(9374922,24); manlo <= conv_std_logic_vector(263006855,28); exponent <= conv_std_logic_vector(1044,11); WHEN "0000010000" => manhi <= conv_std_logic_vector(995005,24); manlo <= conv_std_logic_vector(11010080,28); exponent <= conv_std_logic_vector(1046,11); WHEN "0000010001" => manhi <= conv_std_logic_vector(7377736,24); manlo <= conv_std_logic_vector(202286329,28); exponent <= conv_std_logic_vector(1047,11); WHEN "0000010010" => manhi <= conv_std_logic_vector(16052768,24); manlo <= conv_std_logic_vector(152649917,28); exponent <= conv_std_logic_vector(1048,11); WHEN "0000010011" => manhi <= conv_std_logic_vector(5533071,24); manlo <= conv_std_logic_vector(166536930,28); exponent <= conv_std_logic_vector(1050,11); WHEN "0000010100" => manhi <= conv_std_logic_vector(13545608,24); manlo <= conv_std_logic_vector(191424516,28); exponent <= conv_std_logic_vector(1051,11); WHEN "0000010101" => manhi <= conv_std_logic_vector(3829279,24); manlo <= conv_std_logic_vector(228519165,28); exponent <= conv_std_logic_vector(1053,11); WHEN "0000010110" => manhi <= conv_std_logic_vector(11229915,24); manlo <= conv_std_logic_vector(163853824,28); exponent <= conv_std_logic_vector(1054,11); WHEN "0000010111" => manhi <= conv_std_logic_vector(2255603,24); manlo <= conv_std_logic_vector(61996481,28); exponent <= conv_std_logic_vector(1056,11); WHEN "0000011000" => manhi <= conv_std_logic_vector(9091067,24); manlo <= conv_std_logic_vector(88563639,28); exponent <= conv_std_logic_vector(1057,11); WHEN "0000011001" => manhi <= conv_std_logic_vector(802105,24); manlo <= conv_std_logic_vector(34169545,28); exponent <= conv_std_logic_vector(1059,11); WHEN "0000011010" => manhi <= conv_std_logic_vector(7115558,24); manlo <= conv_std_logic_vector(157969244,28); exponent <= conv_std_logic_vector(1060,11); WHEN "0000011011" => manhi <= conv_std_logic_vector(15696431,24); manlo <= conv_std_logic_vector(133591837,28); exponent <= conv_std_logic_vector(1061,11); WHEN "0000011100" => manhi <= conv_std_logic_vector(5290915,24); manlo <= conv_std_logic_vector(127285146,28); exponent <= conv_std_logic_vector(1063,11); WHEN "0000011101" => manhi <= conv_std_logic_vector(13216484,24); manlo <= conv_std_logic_vector(103923798,28); exponent <= conv_std_logic_vector(1064,11); WHEN "0000011110" => manhi <= conv_std_logic_vector(3605616,24); manlo <= conv_std_logic_vector(183249133,28); exponent <= conv_std_logic_vector(1066,11); WHEN "0000011111" => manhi <= conv_std_logic_vector(10925925,24); manlo <= conv_std_logic_vector(227336045,28); exponent <= conv_std_logic_vector(1067,11); WHEN "0000100000" => manhi <= conv_std_logic_vector(2049020,24); manlo <= conv_std_logic_vector(206267948,28); exponent <= conv_std_logic_vector(1069,11); WHEN "0000100001" => manhi <= conv_std_logic_vector(8810292,24); manlo <= conv_std_logic_vector(175265666,28); exponent <= conv_std_logic_vector(1070,11); WHEN "0000100010" => manhi <= conv_std_logic_vector(611298,24); manlo <= conv_std_logic_vector(255467255,28); exponent <= conv_std_logic_vector(1072,11); WHEN "0000100011" => manhi <= conv_std_logic_vector(6856226,24); manlo <= conv_std_logic_vector(29134171,28); exponent <= conv_std_logic_vector(1073,11); WHEN "0000100100" => manhi <= conv_std_logic_vector(15343962,24); manlo <= conv_std_logic_vector(30543222,28); exponent <= conv_std_logic_vector(1074,11); WHEN "0000100101" => manhi <= conv_std_logic_vector(5051387,24); manlo <= conv_std_logic_vector(186253338,28); exponent <= conv_std_logic_vector(1076,11); WHEN "0000100110" => manhi <= conv_std_logic_vector(12890932,24); manlo <= conv_std_logic_vector(102222951,28); exponent <= conv_std_logic_vector(1077,11); WHEN "0000100111" => manhi <= conv_std_logic_vector(3384381,24); manlo <= conv_std_logic_vector(42116377,28); exponent <= conv_std_logic_vector(1079,11); WHEN "0000101000" => manhi <= conv_std_logic_vector(10625235,24); manlo <= conv_std_logic_vector(158954218,28); exponent <= conv_std_logic_vector(1080,11); WHEN "0000101001" => manhi <= conv_std_logic_vector(1844680,24); manlo <= conv_std_logic_vector(148858978,28); exponent <= conv_std_logic_vector(1082,11); WHEN "0000101010" => manhi <= conv_std_logic_vector(8532565,24); manlo <= conv_std_logic_vector(136319321,28); exponent <= conv_std_logic_vector(1083,11); WHEN "0000101011" => manhi <= conv_std_logic_vector(422563,24); manlo <= conv_std_logic_vector(211728497,28); exponent <= conv_std_logic_vector(1085,11); WHEN "0000101100" => manhi <= conv_std_logic_vector(6599708,24); manlo <= conv_std_logic_vector(114522162,28); exponent <= conv_std_logic_vector(1086,11); WHEN "0000101101" => manhi <= conv_std_logic_vector(14995318,24); manlo <= conv_std_logic_vector(117328318,28); exponent <= conv_std_logic_vector(1087,11); WHEN "0000101110" => manhi <= conv_std_logic_vector(4814459,24); manlo <= conv_std_logic_vector(201622499,28); exponent <= conv_std_logic_vector(1089,11); WHEN "0000101111" => manhi <= conv_std_logic_vector(12568913,24); manlo <= conv_std_logic_vector(246987638,28); exponent <= conv_std_logic_vector(1090,11); WHEN "0000110000" => manhi <= conv_std_logic_vector(3165546,24); manlo <= conv_std_logic_vector(248128843,28); exponent <= conv_std_logic_vector(1092,11); WHEN "0000110001" => manhi <= conv_std_logic_vector(10327809,24); manlo <= conv_std_logic_vector(8929872,28); exponent <= conv_std_logic_vector(1093,11); WHEN "0000110010" => manhi <= conv_std_logic_vector(1642558,24); manlo <= conv_std_logic_vector(67636037,28); exponent <= conv_std_logic_vector(1095,11); WHEN "0000110011" => manhi <= conv_std_logic_vector(8257852,24); manlo <= conv_std_logic_vector(219235425,28); exponent <= conv_std_logic_vector(1096,11); WHEN "0000110100" => manhi <= conv_std_logic_vector(235877,24); manlo <= conv_std_logic_vector(42862412,28); exponent <= conv_std_logic_vector(1098,11); WHEN "0000110101" => manhi <= conv_std_logic_vector(6345974,24); manlo <= conv_std_logic_vector(265996080,28); exponent <= conv_std_logic_vector(1099,11); WHEN "0000110110" => manhi <= conv_std_logic_vector(14650458,24); manlo <= conv_std_logic_vector(253213243,28); exponent <= conv_std_logic_vector(1100,11); WHEN "0000110111" => manhi <= conv_std_logic_vector(4580103,24); manlo <= conv_std_logic_vector(114693785,28); exponent <= conv_std_logic_vector(1102,11); WHEN "0000111000" => manhi <= conv_std_logic_vector(12250390,24); manlo <= conv_std_logic_vector(174984615,28); exponent <= conv_std_logic_vector(1103,11); WHEN "0000111001" => manhi <= conv_std_logic_vector(2949087,24); manlo <= conv_std_logic_vector(247325089,28); exponent <= conv_std_logic_vector(1105,11); WHEN "0000111010" => manhi <= conv_std_logic_vector(10033610,24); manlo <= conv_std_logic_vector(200264553,28); exponent <= conv_std_logic_vector(1106,11); WHEN "0000111011" => manhi <= conv_std_logic_vector(1442629,24); manlo <= conv_std_logic_vector(211375075,28); exponent <= conv_std_logic_vector(1108,11); WHEN "0000111100" => manhi <= conv_std_logic_vector(7986121,24); manlo <= conv_std_logic_vector(231029862,28); exponent <= conv_std_logic_vector(1109,11); WHEN "0000111101" => manhi <= conv_std_logic_vector(51216,24); manlo <= conv_std_logic_vector(222707863,28); exponent <= conv_std_logic_vector(1111,11); WHEN "0000111110" => manhi <= conv_std_logic_vector(6094995,24); manlo <= conv_std_logic_vector(155999272,28); exponent <= conv_std_logic_vector(1112,11); WHEN "0000111111" => manhi <= conv_std_logic_vector(14309342,24); manlo <= conv_std_logic_vector(150013864,28); exponent <= conv_std_logic_vector(1113,11); WHEN "0001000000" => manhi <= conv_std_logic_vector(4348290,24); manlo <= conv_std_logic_vector(217421773,28); exponent <= conv_std_logic_vector(1115,11); WHEN "0001000001" => manhi <= conv_std_logic_vector(11935324,24); manlo <= conv_std_logic_vector(171597361,28); exponent <= conv_std_logic_vector(1116,11); WHEN "0001000010" => manhi <= conv_std_logic_vector(2734978,24); manlo <= conv_std_logic_vector(98553735,28); exponent <= conv_std_logic_vector(1118,11); WHEN "0001000011" => manhi <= conv_std_logic_vector(9742605,24); manlo <= conv_std_logic_vector(185429986,28); exponent <= conv_std_logic_vector(1119,11); WHEN "0001000100" => manhi <= conv_std_logic_vector(1244871,24); manlo <= conv_std_logic_vector(93685501,28); exponent <= conv_std_logic_vector(1121,11); WHEN "0001000101" => manhi <= conv_std_logic_vector(7717340,24); manlo <= conv_std_logic_vector(74048432,28); exponent <= conv_std_logic_vector(1122,11); WHEN "0001000110" => manhi <= conv_std_logic_vector(16514337,24); manlo <= conv_std_logic_vector(163855108,28); exponent <= conv_std_logic_vector(1123,11); WHEN "0001000111" => manhi <= conv_std_logic_vector(5846740,24); manlo <= conv_std_logic_vector(81895750,28); exponent <= conv_std_logic_vector(1125,11); WHEN "0001001000" => manhi <= conv_std_logic_vector(13971928,24); manlo <= conv_std_logic_vector(176088988,28); exponent <= conv_std_logic_vector(1126,11); WHEN "0001001001" => manhi <= conv_std_logic_vector(4118994,24); manlo <= conv_std_logic_vector(77780251,28); exponent <= conv_std_logic_vector(1128,11); WHEN "0001001010" => manhi <= conv_std_logic_vector(11623678,24); manlo <= conv_std_logic_vector(95871356,28); exponent <= conv_std_logic_vector(1129,11); WHEN "0001001011" => manhi <= conv_std_logic_vector(2523192,24); manlo <= conv_std_logic_vector(204213760,28); exponent <= conv_std_logic_vector(1131,11); WHEN "0001001100" => manhi <= conv_std_logic_vector(9454759,24); manlo <= conv_std_logic_vector(55860552,28); exponent <= conv_std_logic_vector(1132,11); WHEN "0001001101" => manhi <= conv_std_logic_vector(1049259,24); manlo <= conv_std_logic_vector(102861624,28); exponent <= conv_std_logic_vector(1134,11); WHEN "0001001110" => manhi <= conv_std_logic_vector(7451476,24); manlo <= conv_std_logic_vector(13367584,28); exponent <= conv_std_logic_vector(1135,11); WHEN "0001001111" => manhi <= conv_std_logic_vector(16152990,24); manlo <= conv_std_logic_vector(178012490,28); exponent <= conv_std_logic_vector(1136,11); WHEN "0001010000" => manhi <= conv_std_logic_vector(5601179,24); manlo <= conv_std_logic_vector(159708139,28); exponent <= conv_std_logic_vector(1138,11); WHEN "0001010001" => manhi <= conv_std_logic_vector(13638177,24); manlo <= conv_std_logic_vector(12864164,28); exponent <= conv_std_logic_vector(1139,11); WHEN "0001010010" => manhi <= conv_std_logic_vector(3892186,24); manlo <= conv_std_logic_vector(149492240,28); exponent <= conv_std_logic_vector(1141,11); WHEN "0001010011" => manhi <= conv_std_logic_vector(11315414,24); manlo <= conv_std_logic_vector(184620728,28); exponent <= conv_std_logic_vector(1142,11); WHEN "0001010100" => manhi <= conv_std_logic_vector(2313705,24); manlo <= conv_std_logic_vector(235697385,28); exponent <= conv_std_logic_vector(1144,11); WHEN "0001010101" => manhi <= conv_std_logic_vector(9170037,24); manlo <= conv_std_logic_vector(3974263,28); exponent <= conv_std_logic_vector(1145,11); WHEN "0001010110" => manhi <= conv_std_logic_vector(855770,24); manlo <= conv_std_logic_vector(158952336,28); exponent <= conv_std_logic_vector(1147,11); WHEN "0001010111" => manhi <= conv_std_logic_vector(7188497,24); manlo <= conv_std_logic_vector(138900038,28); exponent <= conv_std_logic_vector(1148,11); WHEN "0001011000" => manhi <= conv_std_logic_vector(15795565,24); manlo <= conv_std_logic_vector(209449517,28); exponent <= conv_std_logic_vector(1149,11); WHEN "0001011001" => manhi <= conv_std_logic_vector(5358284,24); manlo <= conv_std_logic_vector(54736896,28); exponent <= conv_std_logic_vector(1151,11); WHEN "0001011010" => manhi <= conv_std_logic_vector(13308047,24); manlo <= conv_std_logic_vector(264159588,28); exponent <= conv_std_logic_vector(1152,11); WHEN "0001011011" => manhi <= conv_std_logic_vector(3667840,24); manlo <= conv_std_logic_vector(160544132,28); exponent <= conv_std_logic_vector(1154,11); WHEN "0001011100" => manhi <= conv_std_logic_vector(11010496,24); manlo <= conv_std_logic_vector(245935181,28); exponent <= conv_std_logic_vector(1155,11); WHEN "0001011101" => manhi <= conv_std_logic_vector(2106492,24); manlo <= conv_std_logic_vector(206325441,28); exponent <= conv_std_logic_vector(1157,11); WHEN "0001011110" => manhi <= conv_std_logic_vector(8888405,24); manlo <= conv_std_logic_vector(53641237,28); exponent <= conv_std_logic_vector(1158,11); WHEN "0001011111" => manhi <= conv_std_logic_vector(664381,24); manlo <= conv_std_logic_vector(249887163,28); exponent <= conv_std_logic_vector(1160,11); WHEN "0001100000" => manhi <= conv_std_logic_vector(6928373,24); manlo <= conv_std_logic_vector(95946938,28); exponent <= conv_std_logic_vector(1161,11); WHEN "0001100001" => manhi <= conv_std_logic_vector(15442020,24); manlo <= conv_std_logic_vector(105121290,28); exponent <= conv_std_logic_vector(1162,11); WHEN "0001100010" => manhi <= conv_std_logic_vector(5118025,24); manlo <= conv_std_logic_vector(54367076,28); exponent <= conv_std_logic_vector(1164,11); WHEN "0001100011" => manhi <= conv_std_logic_vector(12981502,24); manlo <= conv_std_logic_vector(39000129,28); exponent <= conv_std_logic_vector(1165,11); WHEN "0001100100" => manhi <= conv_std_logic_vector(3445929,24); manlo <= conv_std_logic_vector(186063861,28); exponent <= conv_std_logic_vector(1167,11); WHEN "0001100101" => manhi <= conv_std_logic_vector(10708888,24); manlo <= conv_std_logic_vector(194877084,28); exponent <= conv_std_logic_vector(1168,11); WHEN "0001100110" => manhi <= conv_std_logic_vector(1901528,24); manlo <= conv_std_logic_vector(202114223,28); exponent <= conv_std_logic_vector(1170,11); WHEN "0001100111" => manhi <= conv_std_logic_vector(8609830,24); manlo <= conv_std_logic_vector(59099508,28); exponent <= conv_std_logic_vector(1171,11); WHEN "0001101000" => manhi <= conv_std_logic_vector(475070,24); manlo <= conv_std_logic_vector(162304029,28); exponent <= conv_std_logic_vector(1173,11); WHEN "0001101001" => manhi <= conv_std_logic_vector(6671072,24); manlo <= conv_std_logic_vector(157938310,28); exponent <= conv_std_logic_vector(1174,11); WHEN "0001101010" => manhi <= conv_std_logic_vector(15092312,24); manlo <= conv_std_logic_vector(104450792,28); exponent <= conv_std_logic_vector(1175,11); WHEN "0001101011" => manhi <= conv_std_logic_vector(4880373,24); manlo <= conv_std_logic_vector(261837049,28); exponent <= conv_std_logic_vector(1177,11); WHEN "0001101100" => manhi <= conv_std_logic_vector(12658500,24); manlo <= conv_std_logic_vector(171583716,28); exponent <= conv_std_logic_vector(1178,11); WHEN "0001101101" => manhi <= conv_std_logic_vector(3226427,24); manlo <= conv_std_logic_vector(110595717,28); exponent <= conv_std_logic_vector(1180,11); WHEN "0001101110" => manhi <= conv_std_logic_vector(10410554,24); manlo <= conv_std_logic_vector(52320382,28); exponent <= conv_std_logic_vector(1181,11); WHEN "0001101111" => manhi <= conv_std_logic_vector(1698789,24); manlo <= conv_std_logic_vector(112550995,28); exponent <= conv_std_logic_vector(1183,11); WHEN "0001110000" => manhi <= conv_std_logic_vector(8334278,24); manlo <= conv_std_logic_vector(240753534,28); exponent <= conv_std_logic_vector(1184,11); WHEN "0001110001" => manhi <= conv_std_logic_vector(287814,24); manlo <= conv_std_logic_vector(17691391,28); exponent <= conv_std_logic_vector(1186,11); WHEN "0001110010" => manhi <= conv_std_logic_vector(6416564,24); manlo <= conv_std_logic_vector(151700710,28); exponent <= conv_std_logic_vector(1187,11); WHEN "0001110011" => manhi <= conv_std_logic_vector(14746400,24); manlo <= conv_std_logic_vector(32676275,28); exponent <= conv_std_logic_vector(1188,11); WHEN "0001110100" => manhi <= conv_std_logic_vector(4645302,24); manlo <= conv_std_logic_vector(58452725,28); exponent <= conv_std_logic_vector(1190,11); WHEN "0001110101" => manhi <= conv_std_logic_vector(12339004,24); manlo <= conv_std_logic_vector(267247876,28); exponent <= conv_std_logic_vector(1191,11); WHEN "0001110110" => manhi <= conv_std_logic_vector(3009307,24); manlo <= conv_std_logic_vector(164126253,28); exponent <= conv_std_logic_vector(1193,11); WHEN "0001110111" => manhi <= conv_std_logic_vector(10115457,24); manlo <= conv_std_logic_vector(212237584,28); exponent <= conv_std_logic_vector(1194,11); WHEN "0001111000" => manhi <= conv_std_logic_vector(1498250,24); manlo <= conv_std_logic_vector(166684427,28); exponent <= conv_std_logic_vector(1196,11); WHEN "0001111001" => manhi <= conv_std_logic_vector(8061718,24); manlo <= conv_std_logic_vector(110371593,28); exponent <= conv_std_logic_vector(1197,11); WHEN "0001111010" => manhi <= conv_std_logic_vector(102590,24); manlo <= conv_std_logic_vector(3231911,28); exponent <= conv_std_logic_vector(1199,11); WHEN "0001111011" => manhi <= conv_std_logic_vector(6164818,24); manlo <= conv_std_logic_vector(261783833,28); exponent <= conv_std_logic_vector(1200,11); WHEN "0001111100" => manhi <= conv_std_logic_vector(14404242,24); manlo <= conv_std_logic_vector(104825991,28); exponent <= conv_std_logic_vector(1201,11); WHEN "0001111101" => manhi <= conv_std_logic_vector(4412781,24); manlo <= conv_std_logic_vector(250166254,28); exponent <= conv_std_logic_vector(1203,11); WHEN "0001111110" => manhi <= conv_std_logic_vector(12022977,24); manlo <= conv_std_logic_vector(43417082,28); exponent <= conv_std_logic_vector(1204,11); WHEN "0001111111" => manhi <= conv_std_logic_vector(2794544,24); manlo <= conv_std_logic_vector(115942082,28); exponent <= conv_std_logic_vector(1206,11); WHEN "0010000000" => manhi <= conv_std_logic_vector(9823564,24); manlo <= conv_std_logic_vector(98386456,28); exponent <= conv_std_logic_vector(1207,11); WHEN "0010000001" => manhi <= conv_std_logic_vector(1299888,24); manlo <= conv_std_logic_vector(127046227,28); exponent <= conv_std_logic_vector(1209,11); WHEN "0010000010" => manhi <= conv_std_logic_vector(7792116,24); manlo <= conv_std_logic_vector(80649262,28); exponent <= conv_std_logic_vector(1210,11); WHEN "0010000011" => manhi <= conv_std_logic_vector(16615968,24); manlo <= conv_std_logic_vector(205307910,28); exponent <= conv_std_logic_vector(1211,11); WHEN "0010000100" => manhi <= conv_std_logic_vector(5915805,24); manlo <= conv_std_logic_vector(224185017,28); exponent <= conv_std_logic_vector(1213,11); WHEN "0010000101" => manhi <= conv_std_logic_vector(14065798,24); manlo <= conv_std_logic_vector(119094636,28); exponent <= conv_std_logic_vector(1214,11); WHEN "0010000110" => manhi <= conv_std_logic_vector(4182785,24); manlo <= conv_std_logic_vector(113890892,28); exponent <= conv_std_logic_vector(1216,11); WHEN "0010000111" => manhi <= conv_std_logic_vector(11710379,24); manlo <= conv_std_logic_vector(133692518,28); exponent <= conv_std_logic_vector(1217,11); WHEN "0010001000" => manhi <= conv_std_logic_vector(2582112,24); manlo <= conv_std_logic_vector(79109485,28); exponent <= conv_std_logic_vector(1219,11); WHEN "0010001001" => manhi <= conv_std_logic_vector(9534839,24); manlo <= conv_std_logic_vector(42234535,28); exponent <= conv_std_logic_vector(1220,11); WHEN "0010001010" => manhi <= conv_std_logic_vector(1103679,24); manlo <= conv_std_logic_vector(94193887,28); exponent <= conv_std_logic_vector(1222,11); WHEN "0010001011" => manhi <= conv_std_logic_vector(7525440,24); manlo <= conv_std_logic_vector(121994268,28); exponent <= conv_std_logic_vector(1223,11); WHEN "0010001100" => manhi <= conv_std_logic_vector(16253518,24); manlo <= conv_std_logic_vector(191052573,28); exponent <= conv_std_logic_vector(1224,11); WHEN "0010001101" => manhi <= conv_std_logic_vector(5669495,24); manlo <= conv_std_logic_vector(130696997,28); exponent <= conv_std_logic_vector(1226,11); WHEN "0010001110" => manhi <= conv_std_logic_vector(13731027,24); manlo <= conv_std_logic_vector(260846837,28); exponent <= conv_std_logic_vector(1227,11); WHEN "0010001111" => manhi <= conv_std_logic_vector(3955285,24); manlo <= conv_std_logic_vector(80970159,28); exponent <= conv_std_logic_vector(1229,11); WHEN "0010010000" => manhi <= conv_std_logic_vector(11401174,24); manlo <= conv_std_logic_vector(207600506,28); exponent <= conv_std_logic_vector(1230,11); WHEN "0010010001" => manhi <= conv_std_logic_vector(2371985,24); manlo <= conv_std_logic_vector(241221170,28); exponent <= conv_std_logic_vector(1232,11); WHEN "0010010010" => manhi <= conv_std_logic_vector(9249247,24); manlo <= conv_std_logic_vector(208105818,28); exponent <= conv_std_logic_vector(1233,11); WHEN "0010010011" => manhi <= conv_std_logic_vector(909599,24); manlo <= conv_std_logic_vector(237519888,28); exponent <= conv_std_logic_vector(1235,11); WHEN "0010010100" => manhi <= conv_std_logic_vector(7261659,24); manlo <= conv_std_logic_vector(29935335,28); exponent <= conv_std_logic_vector(1236,11); WHEN "0010010101" => manhi <= conv_std_logic_vector(15895002,24); manlo <= conv_std_logic_vector(186862656,28); exponent <= conv_std_logic_vector(1237,11); WHEN "0010010110" => manhi <= conv_std_logic_vector(5425858,24); manlo <= conv_std_logic_vector(159524243,28); exponent <= conv_std_logic_vector(1239,11); WHEN "0010010111" => manhi <= conv_std_logic_vector(13399891,24); manlo <= conv_std_logic_vector(27586577,28); exponent <= conv_std_logic_vector(1240,11); WHEN "0010011000" => manhi <= conv_std_logic_vector(3730254,24); manlo <= conv_std_logic_vector(125689310,28); exponent <= conv_std_logic_vector(1242,11); WHEN "0010011001" => manhi <= conv_std_logic_vector(11095326,24); manlo <= conv_std_logic_vector(43144000,28); exponent <= conv_std_logic_vector(1243,11); WHEN "0010011010" => manhi <= conv_std_logic_vector(2164140,24); manlo <= conv_std_logic_vector(58280992,28); exponent <= conv_std_logic_vector(1245,11); WHEN "0010011011" => manhi <= conv_std_logic_vector(8966756,24); manlo <= conv_std_logic_vector(55210422,28); exponent <= conv_std_logic_vector(1246,11); WHEN "0010011100" => manhi <= conv_std_logic_vector(717626,24); manlo <= conv_std_logic_vector(257633658,28); exponent <= conv_std_logic_vector(1248,11); WHEN "0010011101" => manhi <= conv_std_logic_vector(7000740,24); manlo <= conv_std_logic_vector(229413090,28); exponent <= conv_std_logic_vector(1249,11); WHEN "0010011110" => manhi <= conv_std_logic_vector(15540378,24); manlo <= conv_std_logic_vector(4808337,28); exponent <= conv_std_logic_vector(1250,11); WHEN "0010011111" => manhi <= conv_std_logic_vector(5184866,24); manlo <= conv_std_logic_vector(37474138,28); exponent <= conv_std_logic_vector(1252,11); WHEN "0010100000" => manhi <= conv_std_logic_vector(13072348,24); manlo <= conv_std_logic_vector(106730632,28); exponent <= conv_std_logic_vector(1253,11); WHEN "0010100001" => manhi <= conv_std_logic_vector(3507666,24); manlo <= conv_std_logic_vector(32844500,28); exponent <= conv_std_logic_vector(1255,11); WHEN "0010100010" => manhi <= conv_std_logic_vector(10792797,24); manlo <= conv_std_logic_vector(62496090,28); exponent <= conv_std_logic_vector(1256,11); WHEN "0010100011" => manhi <= conv_std_logic_vector(1958550,24); manlo <= conv_std_logic_vector(132952012,28); exponent <= conv_std_logic_vector(1258,11); WHEN "0010100100" => manhi <= conv_std_logic_vector(8687330,24); manlo <= conv_std_logic_vector(215605290,28); exponent <= conv_std_logic_vector(1259,11); WHEN "0010100101" => manhi <= conv_std_logic_vector(527737,24); manlo <= conv_std_logic_vector(190928911,28); exponent <= conv_std_logic_vector(1261,11); WHEN "0010100110" => manhi <= conv_std_logic_vector(6742654,24); manlo <= conv_std_logic_vector(163162889,28); exponent <= conv_std_logic_vector(1262,11); WHEN "0010100111" => manhi <= conv_std_logic_vector(15189602,24); manlo <= conv_std_logic_vector(118241780,28); exponent <= conv_std_logic_vector(1263,11); WHEN "0010101000" => manhi <= conv_std_logic_vector(4946489,24); manlo <= conv_std_logic_vector(112771062,28); exponent <= conv_std_logic_vector(1265,11); WHEN "0010101001" => manhi <= conv_std_logic_vector(12748360,24); manlo <= conv_std_logic_vector(226864003,28); exponent <= conv_std_logic_vector(1266,11); WHEN "0010101010" => manhi <= conv_std_logic_vector(3287493,24); manlo <= conv_std_logic_vector(202192272,28); exponent <= conv_std_logic_vector(1268,11); WHEN "0010101011" => manhi <= conv_std_logic_vector(10493551,24); manlo <= conv_std_logic_vector(257093553,28); exponent <= conv_std_logic_vector(1269,11); WHEN "0010101100" => manhi <= conv_std_logic_vector(1755192,24); manlo <= conv_std_logic_vector(66281405,28); exponent <= conv_std_logic_vector(1271,11); WHEN "0010101101" => manhi <= conv_std_logic_vector(8410938,24); manlo <= conv_std_logic_vector(77199396,28); exponent <= conv_std_logic_vector(1272,11); WHEN "0010101110" => manhi <= conv_std_logic_vector(339909,24); manlo <= conv_std_logic_vector(140417186,28); exponent <= conv_std_logic_vector(1274,11); WHEN "0010101111" => manhi <= conv_std_logic_vector(6487369,24); manlo <= conv_std_logic_vector(169769464,28); exponent <= conv_std_logic_vector(1275,11); WHEN "0010110000" => manhi <= conv_std_logic_vector(14842634,24); manlo <= conv_std_logic_vector(49834035,28); exponent <= conv_std_logic_vector(1276,11); WHEN "0010110001" => manhi <= conv_std_logic_vector(4710700,24); manlo <= conv_std_logic_vector(11961455,28); exponent <= conv_std_logic_vector(1278,11); WHEN "0010110010" => manhi <= conv_std_logic_vector(12427889,24); manlo <= conv_std_logic_vector(230234502,28); exponent <= conv_std_logic_vector(1279,11); WHEN "0010110011" => manhi <= conv_std_logic_vector(3069711,24); manlo <= conv_std_logic_vector(36989233,28); exponent <= conv_std_logic_vector(1281,11); WHEN "0010110100" => manhi <= conv_std_logic_vector(10197554,24); manlo <= conv_std_logic_vector(186484869,28); exponent <= conv_std_logic_vector(1282,11); WHEN "0010110101" => manhi <= conv_std_logic_vector(1554041,24); manlo <= conv_std_logic_vector(67530342,28); exponent <= conv_std_logic_vector(1284,11); WHEN "0010110110" => manhi <= conv_std_logic_vector(8137545,24); manlo <= conv_std_logic_vector(198608842,28); exponent <= conv_std_logic_vector(1285,11); WHEN "0010110111" => manhi <= conv_std_logic_vector(154120,24); manlo <= conv_std_logic_vector(6569319,28); exponent <= conv_std_logic_vector(1287,11); WHEN "0010111000" => manhi <= conv_std_logic_vector(6234855,24); manlo <= conv_std_logic_vector(140506894,28); exponent <= conv_std_logic_vector(1288,11); WHEN "0010111001" => manhi <= conv_std_logic_vector(14499431,24); manlo <= conv_std_logic_vector(249287529,28); exponent <= conv_std_logic_vector(1289,11); WHEN "0010111010" => manhi <= conv_std_logic_vector(4477469,24); manlo <= conv_std_logic_vector(249618841,28); exponent <= conv_std_logic_vector(1291,11); WHEN "0010111011" => manhi <= conv_std_logic_vector(12110897,24); manlo <= conv_std_logic_vector(71519058,28); exponent <= conv_std_logic_vector(1292,11); WHEN "0010111100" => manhi <= conv_std_logic_vector(2854292,24); manlo <= conv_std_logic_vector(90637320,28); exponent <= conv_std_logic_vector(1294,11); WHEN "0010111101" => manhi <= conv_std_logic_vector(9904770,24); manlo <= conv_std_logic_vector(50932558,28); exponent <= conv_std_logic_vector(1295,11); WHEN "0010111110" => manhi <= conv_std_logic_vector(1355073,24); manlo <= conv_std_logic_vector(148093260,28); exponent <= conv_std_logic_vector(1297,11); WHEN "0010111111" => manhi <= conv_std_logic_vector(7867120,24); manlo <= conv_std_logic_vector(160620741,28); exponent <= conv_std_logic_vector(1298,11); WHEN "0011000000" => manhi <= conv_std_logic_vector(16717910,24); manlo <= conv_std_logic_vector(46942270,28); exponent <= conv_std_logic_vector(1299,11); WHEN "0011000001" => manhi <= conv_std_logic_vector(5985082,24); manlo <= conv_std_logic_vector(55237426,28); exponent <= conv_std_logic_vector(1301,11); WHEN "0011000010" => manhi <= conv_std_logic_vector(14159954,24); manlo <= conv_std_logic_vector(212966668,28); exponent <= conv_std_logic_vector(1302,11); WHEN "0011000011" => manhi <= conv_std_logic_vector(4246771,24); manlo <= conv_std_logic_vector(79962334,28); exponent <= conv_std_logic_vector(1304,11); WHEN "0011000100" => manhi <= conv_std_logic_vector(11797345,24); manlo <= conv_std_logic_vector(85038862,28); exponent <= conv_std_logic_vector(1305,11); WHEN "0011000101" => manhi <= conv_std_logic_vector(2641211,24); manlo <= conv_std_logic_vector(186806322,28); exponent <= conv_std_logic_vector(1307,11); WHEN "0011000110" => manhi <= conv_std_logic_vector(9615163,24); manlo <= conv_std_logic_vector(153415152,28); exponent <= conv_std_logic_vector(1308,11); WHEN "0011000111" => manhi <= conv_std_logic_vector(1158265,24); manlo <= conv_std_logic_vector(120731907,28); exponent <= conv_std_logic_vector(1310,11); WHEN "0011001000" => manhi <= conv_std_logic_vector(7599630,24); manlo <= conv_std_logic_vector(175764921,28); exponent <= conv_std_logic_vector(1311,11); WHEN "0011001001" => manhi <= conv_std_logic_vector(16354353,24); manlo <= conv_std_logic_vector(174054693,28); exponent <= conv_std_logic_vector(1312,11); WHEN "0011001010" => manhi <= conv_std_logic_vector(5738019,24); manlo <= conv_std_logic_vector(249885394,28); exponent <= conv_std_logic_vector(1314,11); WHEN "0011001011" => manhi <= conv_std_logic_vector(13824162,24); manlo <= conv_std_logic_vector(93203713,28); exponent <= conv_std_logic_vector(1315,11); WHEN "0011001100" => manhi <= conv_std_logic_vector(4018576,24); manlo <= conv_std_logic_vector(180323091,28); exponent <= conv_std_logic_vector(1317,11); WHEN "0011001101" => manhi <= conv_std_logic_vector(11487196,24); manlo <= conv_std_logic_vector(178245939,28); exponent <= conv_std_logic_vector(1318,11); WHEN "0011001110" => manhi <= conv_std_logic_vector(2430443,24); manlo <= conv_std_logic_vector(223919964,28); exponent <= conv_std_logic_vector(1320,11); WHEN "0011001111" => manhi <= conv_std_logic_vector(9328700,24); manlo <= conv_std_logic_vector(93205956,28); exponent <= conv_std_logic_vector(1321,11); WHEN "0011010000" => manhi <= conv_std_logic_vector(963593,24); manlo <= conv_std_logic_vector(135688620,28); exponent <= conv_std_logic_vector(1323,11); WHEN "0011010001" => manhi <= conv_std_logic_vector(7335044,24); manlo <= conv_std_logic_vector(13542358,28); exponent <= conv_std_logic_vector(1324,11); WHEN "0011010010" => manhi <= conv_std_logic_vector(15994743,24); manlo <= conv_std_logic_vector(45394459,28); exponent <= conv_std_logic_vector(1325,11); WHEN "0011010011" => manhi <= conv_std_logic_vector(5493639,24); manlo <= conv_std_logic_vector(73308838,28); exponent <= conv_std_logic_vector(1327,11); WHEN "0011010100" => manhi <= conv_std_logic_vector(13492014,24); manlo <= conv_std_logic_vector(160135181,28); exponent <= conv_std_logic_vector(1328,11); WHEN "0011010101" => manhi <= conv_std_logic_vector(3792858,24); manlo <= conv_std_logic_vector(234346738,28); exponent <= conv_std_logic_vector(1330,11); WHEN "0011010110" => manhi <= conv_std_logic_vector(11180414,24); manlo <= conv_std_logic_vector(98964646,28); exponent <= conv_std_logic_vector(1331,11); WHEN "0011010111" => manhi <= conv_std_logic_vector(2221963,24); manlo <= conv_std_logic_vector(174344531,28); exponent <= conv_std_logic_vector(1333,11); WHEN "0011011000" => manhi <= conv_std_logic_vector(9045346,24); manlo <= conv_std_logic_vector(106947534,28); exponent <= conv_std_logic_vector(1334,11); WHEN "0011011001" => manhi <= conv_std_logic_vector(771034,24); manlo <= conv_std_logic_vector(143065990,28); exponent <= conv_std_logic_vector(1336,11); WHEN "0011011010" => manhi <= conv_std_logic_vector(7073329,24); manlo <= conv_std_logic_vector(73148434,28); exponent <= conv_std_logic_vector(1337,11); WHEN "0011011011" => manhi <= conv_std_logic_vector(15639035,24); manlo <= conv_std_logic_vector(243346703,28); exponent <= conv_std_logic_vector(1338,11); WHEN "0011011100" => manhi <= conv_std_logic_vector(5251911,24); manlo <= conv_std_logic_vector(33842377,28); exponent <= conv_std_logic_vector(1340,11); WHEN "0011011101" => manhi <= conv_std_logic_vector(13163471,24); manlo <= conv_std_logic_vector(263552292,28); exponent <= conv_std_logic_vector(1341,11); WHEN "0011011110" => manhi <= conv_std_logic_vector(3569591,24); manlo <= conv_std_logic_vector(4866264,28); exponent <= conv_std_logic_vector(1343,11); WHEN "0011011111" => manhi <= conv_std_logic_vector(10876961,24); manlo <= conv_std_logic_vector(239517036,28); exponent <= conv_std_logic_vector(1344,11); WHEN "0011100000" => manhi <= conv_std_logic_vector(2015746,24); manlo <= conv_std_logic_vector(83586287,28); exponent <= conv_std_logic_vector(1346,11); WHEN "0011100001" => manhi <= conv_std_logic_vector(8765067,24); manlo <= conv_std_logic_vector(262254542,28); exponent <= conv_std_logic_vector(1347,11); WHEN "0011100010" => manhi <= conv_std_logic_vector(580565,24); manlo <= conv_std_logic_vector(160521039,28); exponent <= conv_std_logic_vector(1349,11); WHEN "0011100011" => manhi <= conv_std_logic_vector(6814455,24); manlo <= conv_std_logic_vector(40288155,28); exponent <= conv_std_logic_vector(1350,11); WHEN "0011100100" => manhi <= conv_std_logic_vector(15287189,24); manlo <= conv_std_logic_vector(132910147,28); exponent <= conv_std_logic_vector(1351,11); WHEN "0011100101" => manhi <= conv_std_logic_vector(5012806,24); manlo <= conv_std_logic_vector(187753904,28); exponent <= conv_std_logic_vector(1353,11); WHEN "0011100110" => manhi <= conv_std_logic_vector(12838495,24); manlo <= conv_std_logic_vector(100071648,28); exponent <= conv_std_logic_vector(1354,11); WHEN "0011100111" => manhi <= conv_std_logic_vector(3348746,24); manlo <= conv_std_logic_vector(138348888,28); exponent <= conv_std_logic_vector(1356,11); WHEN "0011101000" => manhi <= conv_std_logic_vector(10576803,24); manlo <= conv_std_logic_vector(24941937,28); exponent <= conv_std_logic_vector(1357,11); WHEN "0011101001" => manhi <= conv_std_logic_vector(1811767,24); manlo <= conv_std_logic_vector(69497619,28); exponent <= conv_std_logic_vector(1359,11); WHEN "0011101010" => manhi <= conv_std_logic_vector(8487831,24); manlo <= conv_std_logic_vector(188199296,28); exponent <= conv_std_logic_vector(1360,11); WHEN "0011101011" => manhi <= conv_std_logic_vector(392164,24); manlo <= conv_std_logic_vector(4096525,28); exponent <= conv_std_logic_vector(1362,11); WHEN "0011101100" => manhi <= conv_std_logic_vector(6558390,24); manlo <= conv_std_logic_vector(228356857,28); exponent <= conv_std_logic_vector(1363,11); WHEN "0011101101" => manhi <= conv_std_logic_vector(14939162,24); manlo <= conv_std_logic_vector(7826265,28); exponent <= conv_std_logic_vector(1364,11); WHEN "0011101110" => manhi <= conv_std_logic_vector(4776297,24); manlo <= conv_std_logic_vector(138324122,28); exponent <= conv_std_logic_vector(1366,11); WHEN "0011101111" => manhi <= conv_std_logic_vector(12517046,24); manlo <= conv_std_logic_vector(17190560,28); exponent <= conv_std_logic_vector(1367,11); WHEN "0011110000" => manhi <= conv_std_logic_vector(3130299,24); manlo <= conv_std_logic_vector(16562242,28); exponent <= conv_std_logic_vector(1369,11); WHEN "0011110001" => manhi <= conv_std_logic_vector(10279902,24); manlo <= conv_std_logic_vector(59323104,28); exponent <= conv_std_logic_vector(1370,11); WHEN "0011110010" => manhi <= conv_std_logic_vector(1610002,24); manlo <= conv_std_logic_vector(53056333,28); exponent <= conv_std_logic_vector(1372,11); WHEN "0011110011" => manhi <= conv_std_logic_vector(8213604,24); manlo <= conv_std_logic_vector(147986337,28); exponent <= conv_std_logic_vector(1373,11); WHEN "0011110100" => manhi <= conv_std_logic_vector(205807,24); manlo <= conv_std_logic_vector(92802035,28); exponent <= conv_std_logic_vector(1375,11); WHEN "0011110101" => manhi <= conv_std_logic_vector(6305105,24); manlo <= conv_std_logic_vector(235277170,28); exponent <= conv_std_logic_vector(1376,11); WHEN "0011110110" => manhi <= conv_std_logic_vector(14594912,24); manlo <= conv_std_logic_vector(15497684,28); exponent <= conv_std_logic_vector(1377,11); WHEN "0011110111" => manhi <= conv_std_logic_vector(4542355,24); manlo <= conv_std_logic_vector(108677892,28); exponent <= conv_std_logic_vector(1379,11); WHEN "0011111000" => manhi <= conv_std_logic_vector(12199085,24); manlo <= conv_std_logic_vector(206743222,28); exponent <= conv_std_logic_vector(1380,11); WHEN "0011111001" => manhi <= conv_std_logic_vector(2914222,24); manlo <= conv_std_logic_vector(171652524,28); exponent <= conv_std_logic_vector(1382,11); WHEN "0011111010" => manhi <= conv_std_logic_vector(9986223,24); manlo <= conv_std_logic_vector(245598061,28); exponent <= conv_std_logic_vector(1383,11); WHEN "0011111011" => manhi <= conv_std_logic_vector(1410427,24); manlo <= conv_std_logic_vector(26024388,28); exponent <= conv_std_logic_vector(1385,11); WHEN "0011111100" => manhi <= conv_std_logic_vector(7942353,24); manlo <= conv_std_logic_vector(232590388,28); exponent <= conv_std_logic_vector(1386,11); WHEN "0011111101" => manhi <= conv_std_logic_vector(21473,24); manlo <= conv_std_logic_vector(105719295,28); exponent <= conv_std_logic_vector(1388,11); WHEN "0011111110" => manhi <= conv_std_logic_vector(6054570,24); manlo <= conv_std_logic_vector(16265786,28); exponent <= conv_std_logic_vector(1389,11); WHEN "0011111111" => manhi <= conv_std_logic_vector(14254398,24); manlo <= conv_std_logic_vector(155662944,28); exponent <= conv_std_logic_vector(1390,11); WHEN "0100000000" => manhi <= conv_std_logic_vector(4310952,24); manlo <= conv_std_logic_vector(135577274,28); exponent <= conv_std_logic_vector(1392,11); WHEN "0100000001" => manhi <= conv_std_logic_vector(11884576,24); manlo <= conv_std_logic_vector(166805756,28); exponent <= conv_std_logic_vector(1393,11); WHEN "0100000010" => manhi <= conv_std_logic_vector(2700491,24); manlo <= conv_std_logic_vector(137829044,28); exponent <= conv_std_logic_vector(1395,11); WHEN "0100000011" => manhi <= conv_std_logic_vector(9695733,24); manlo <= conv_std_logic_vector(52863001,28); exponent <= conv_std_logic_vector(1396,11); WHEN "0100000100" => manhi <= conv_std_logic_vector(1213018,24); manlo <= conv_std_logic_vector(50179603,28); exponent <= conv_std_logic_vector(1398,11); WHEN "0100000101" => manhi <= conv_std_logic_vector(7674047,24); manlo <= conv_std_logic_vector(91276680,28); exponent <= conv_std_logic_vector(1399,11); WHEN "0100000110" => manhi <= conv_std_logic_vector(16455496,24); manlo <= conv_std_logic_vector(110068760,28); exponent <= conv_std_logic_vector(1400,11); WHEN "0100000111" => manhi <= conv_std_logic_vector(5806753,24); manlo <= conv_std_logic_vector(151304445,28); exponent <= conv_std_logic_vector(1402,11); WHEN "0100001000" => manhi <= conv_std_logic_vector(13917581,24); manlo <= conv_std_logic_vector(10650184,28); exponent <= conv_std_logic_vector(1403,11); WHEN "0100001001" => manhi <= conv_std_logic_vector(4082061,24); manlo <= conv_std_logic_vector(68530707,28); exponent <= conv_std_logic_vector(1405,11); WHEN "0100001010" => manhi <= conv_std_logic_vector(11573481,24); manlo <= conv_std_logic_vector(42662756,28); exponent <= conv_std_logic_vector(1406,11); WHEN "0100001011" => manhi <= conv_std_logic_vector(2489080,24); manlo <= conv_std_logic_vector(61154162,28); exponent <= conv_std_logic_vector(1408,11); WHEN "0100001100" => manhi <= conv_std_logic_vector(9408395,24); manlo <= conv_std_logic_vector(125867240,28); exponent <= conv_std_logic_vector(1409,11); WHEN "0100001101" => manhi <= conv_std_logic_vector(1017751,24); manlo <= conv_std_logic_vector(256555705,28); exponent <= conv_std_logic_vector(1411,11); WHEN "0100001110" => manhi <= conv_std_logic_vector(7408653,24); manlo <= conv_std_logic_vector(4309896,28); exponent <= conv_std_logic_vector(1412,11); WHEN "0100001111" => manhi <= conv_std_logic_vector(16094788,24); manlo <= conv_std_logic_vector(33800670,28); exponent <= conv_std_logic_vector(1413,11); WHEN "0100010000" => manhi <= conv_std_logic_vector(5561626,24); manlo <= conv_std_logic_vector(233573192,28); exponent <= conv_std_logic_vector(1415,11); WHEN "0100010001" => manhi <= conv_std_logic_vector(13584419,24); manlo <= conv_std_logic_vector(86257801,28); exponent <= conv_std_logic_vector(1416,11); WHEN "0100010010" => manhi <= conv_std_logic_vector(3855654,24); manlo <= conv_std_logic_vector(105782775,28); exponent <= conv_std_logic_vector(1418,11); WHEN "0100010011" => manhi <= conv_std_logic_vector(11265762,24); manlo <= conv_std_logic_vector(88738762,28); exponent <= conv_std_logic_vector(1419,11); WHEN "0100010100" => manhi <= conv_std_logic_vector(2279963,24); manlo <= conv_std_logic_vector(161858527,28); exponent <= conv_std_logic_vector(1421,11); WHEN "0100010101" => manhi <= conv_std_logic_vector(9124176,24); manlo <= conv_std_logic_vector(136423424,28); exponent <= conv_std_logic_vector(1422,11); WHEN "0100010110" => manhi <= conv_std_logic_vector(824605,24); manlo <= conv_std_logic_vector(39384255,28); exponent <= conv_std_logic_vector(1424,11); WHEN "0100010111" => manhi <= conv_std_logic_vector(7146139,24); manlo <= conv_std_logic_vector(76626123,28); exponent <= conv_std_logic_vector(1425,11); WHEN "0100011000" => manhi <= conv_std_logic_vector(15737994,24); manlo <= conv_std_logic_vector(261485765,28); exponent <= conv_std_logic_vector(1426,11); WHEN "0100011001" => manhi <= conv_std_logic_vector(5319160,24); manlo <= conv_std_logic_vector(210684009,28); exponent <= conv_std_logic_vector(1428,11); WHEN "0100011010" => manhi <= conv_std_logic_vector(13254873,24); manlo <= conv_std_logic_vector(199859160,28); exponent <= conv_std_logic_vector(1429,11); WHEN "0100011011" => manhi <= conv_std_logic_vector(3631704,24); manlo <= conv_std_logic_vector(256571707,28); exponent <= conv_std_logic_vector(1431,11); WHEN "0100011100" => manhi <= conv_std_logic_vector(10961383,24); manlo <= conv_std_logic_vector(130542749,28); exponent <= conv_std_logic_vector(1432,11); WHEN "0100011101" => manhi <= conv_std_logic_vector(2073116,24); manlo <= conv_std_logic_vector(196665136,28); exponent <= conv_std_logic_vector(1434,11); WHEN "0100011110" => manhi <= conv_std_logic_vector(8843042,24); manlo <= conv_std_logic_vector(124490661,28); exponent <= conv_std_logic_vector(1435,11); WHEN "0100011111" => manhi <= conv_std_logic_vector(633554,24); manlo <= conv_std_logic_vector(202834752,28); exponent <= conv_std_logic_vector(1437,11); WHEN "0100100000" => manhi <= conv_std_logic_vector(6886474,24); manlo <= conv_std_logic_vector(236822279,28); exponent <= conv_std_logic_vector(1438,11); WHEN "0100100001" => manhi <= conv_std_logic_vector(15385074,24); manlo <= conv_std_logic_vector(123405487,28); exponent <= conv_std_logic_vector(1439,11); WHEN "0100100010" => manhi <= conv_std_logic_vector(5079326,24); manlo <= conv_std_logic_vector(115311954,28); exponent <= conv_std_logic_vector(1441,11); WHEN "0100100011" => manhi <= conv_std_logic_vector(12928905,24); manlo <= conv_std_logic_vector(16004876,28); exponent <= conv_std_logic_vector(1442,11); WHEN "0100100100" => manhi <= conv_std_logic_vector(3410186,24); manlo <= conv_std_logic_vector(71831800,28); exponent <= conv_std_logic_vector(1444,11); WHEN "0100100101" => manhi <= conv_std_logic_vector(10660308,24); manlo <= conv_std_logic_vector(100367284,28); exponent <= conv_std_logic_vector(1445,11); WHEN "0100100110" => manhi <= conv_std_logic_vector(1868514,24); manlo <= conv_std_logic_vector(263299419,28); exponent <= conv_std_logic_vector(1447,11); WHEN "0100100111" => manhi <= conv_std_logic_vector(8564959,24); manlo <= conv_std_logic_vector(228656810,28); exponent <= conv_std_logic_vector(1448,11); WHEN "0100101000" => manhi <= conv_std_logic_vector(444578,24); manlo <= conv_std_logic_vector(7489141,28); exponent <= conv_std_logic_vector(1450,11); WHEN "0100101001" => manhi <= conv_std_logic_vector(6629628,24); manlo <= conv_std_logic_vector(236156491,28); exponent <= conv_std_logic_vector(1451,11); WHEN "0100101010" => manhi <= conv_std_logic_vector(15035984,24); manlo <= conv_std_logic_vector(147396312,28); exponent <= conv_std_logic_vector(1452,11); WHEN "0100101011" => manhi <= conv_std_logic_vector(4842095,24); manlo <= conv_std_logic_vector(64271882,28); exponent <= conv_std_logic_vector(1454,11); WHEN "0100101100" => manhi <= conv_std_logic_vector(12606474,24); manlo <= conv_std_logic_vector(118909770,28); exponent <= conv_std_logic_vector(1455,11); WHEN "0100101101" => manhi <= conv_std_logic_vector(3191071,24); manlo <= conv_std_logic_vector(253953386,28); exponent <= conv_std_logic_vector(1457,11); WHEN "0100101110" => manhi <= conv_std_logic_vector(10362501,24); manlo <= conv_std_logic_vector(36129498,28); exponent <= conv_std_logic_vector(1458,11); WHEN "0100101111" => manhi <= conv_std_logic_vector(1666133,24); manlo <= conv_std_logic_vector(262830684,28); exponent <= conv_std_logic_vector(1460,11); WHEN "0100110000" => manhi <= conv_std_logic_vector(8289895,24); manlo <= conv_std_logic_vector(148197046,28); exponent <= conv_std_logic_vector(1461,11); WHEN "0100110001" => manhi <= conv_std_logic_vector(257652,24); manlo <= conv_std_logic_vector(122404338,28); exponent <= conv_std_logic_vector(1463,11); WHEN "0100110010" => manhi <= conv_std_logic_vector(6375570,24); manlo <= conv_std_logic_vector(184430245,28); exponent <= conv_std_logic_vector(1464,11); WHEN "0100110011" => manhi <= conv_std_logic_vector(14690683,24); manlo <= conv_std_logic_vector(178457687,28); exponent <= conv_std_logic_vector(1465,11); WHEN "0100110100" => manhi <= conv_std_logic_vector(4607438,24); manlo <= conv_std_logic_vector(257605193,28); exponent <= conv_std_logic_vector(1467,11); WHEN "0100110101" => manhi <= conv_std_logic_vector(12287543,24); manlo <= conv_std_logic_vector(132163446,28); exponent <= conv_std_logic_vector(1468,11); WHEN "0100110110" => manhi <= conv_std_logic_vector(2974335,24); manlo <= conv_std_logic_vector(240020217,28); exponent <= conv_std_logic_vector(1470,11); WHEN "0100110111" => manhi <= conv_std_logic_vector(10067926,24); manlo <= conv_std_logic_vector(80224641,28); exponent <= conv_std_logic_vector(1471,11); WHEN "0100111000" => manhi <= conv_std_logic_vector(1465949,24); manlo <= conv_std_logic_vector(167328478,28); exponent <= conv_std_logic_vector(1473,11); WHEN "0100111001" => manhi <= conv_std_logic_vector(8017816,24); manlo <= conv_std_logic_vector(215756784,28); exponent <= conv_std_logic_vector(1474,11); WHEN "0100111010" => manhi <= conv_std_logic_vector(72755,24); manlo <= conv_std_logic_vector(208473528,28); exponent <= conv_std_logic_vector(1476,11); WHEN "0100111011" => manhi <= conv_std_logic_vector(6124270,24); manlo <= conv_std_logic_vector(12139444,28); exponent <= conv_std_logic_vector(1477,11); WHEN "0100111100" => manhi <= conv_std_logic_vector(14349130,24); manlo <= conv_std_logic_vector(182729110,28); exponent <= conv_std_logic_vector(1478,11); WHEN "0100111101" => manhi <= conv_std_logic_vector(4375329,24); manlo <= conv_std_logic_vector(172370119,28); exponent <= conv_std_logic_vector(1480,11); WHEN "0100111110" => manhi <= conv_std_logic_vector(11972074,24); manlo <= conv_std_logic_vector(59679792,28); exponent <= conv_std_logic_vector(1481,11); WHEN "0100111111" => manhi <= conv_std_logic_vector(2759952,24); manlo <= conv_std_logic_vector(80023302,28); exponent <= conv_std_logic_vector(1483,11); WHEN "0101000000" => manhi <= conv_std_logic_vector(9776548,24); manlo <= conv_std_logic_vector(209956608,28); exponent <= conv_std_logic_vector(1484,11); WHEN "0101000001" => manhi <= conv_std_logic_vector(1267938,24); manlo <= conv_std_logic_vector(19091951,28); exponent <= conv_std_logic_vector(1486,11); WHEN "0101000010" => manhi <= conv_std_logic_vector(7748691,24); manlo <= conv_std_logic_vector(54127000,28); exponent <= conv_std_logic_vector(1487,11); WHEN "0101000011" => manhi <= conv_std_logic_vector(16556947,24); manlo <= conv_std_logic_vector(251347868,28); exponent <= conv_std_logic_vector(1488,11); WHEN "0101000100" => manhi <= conv_std_logic_vector(5875697,24); manlo <= conv_std_logic_vector(6377900,28); exponent <= conv_std_logic_vector(1490,11); WHEN "0101000101" => manhi <= conv_std_logic_vector(14011284,24); manlo <= conv_std_logic_vector(246175281,28); exponent <= conv_std_logic_vector(1491,11); WHEN "0101000110" => manhi <= conv_std_logic_vector(4145739,24); manlo <= conv_std_logic_vector(172360927,28); exponent <= conv_std_logic_vector(1493,11); WHEN "0101000111" => manhi <= conv_std_logic_vector(11660029,24); manlo <= conv_std_logic_vector(16047086,28); exponent <= conv_std_logic_vector(1494,11); WHEN "0101001000" => manhi <= conv_std_logic_vector(2547895,24); manlo <= conv_std_logic_vector(167600151,28); exponent <= conv_std_logic_vector(1496,11); WHEN "0101001001" => manhi <= conv_std_logic_vector(9488333,24); manlo <= conv_std_logic_vector(236416250,28); exponent <= conv_std_logic_vector(1497,11); WHEN "0101001010" => manhi <= conv_std_logic_vector(1072075,24); manlo <= conv_std_logic_vector(198323037,28); exponent <= conv_std_logic_vector(1499,11); WHEN "0101001011" => manhi <= conv_std_logic_vector(7482486,24); manlo <= conv_std_logic_vector(185820926,28); exponent <= conv_std_logic_vector(1500,11); WHEN "0101001100" => manhi <= conv_std_logic_vector(16195138,24); manlo <= conv_std_logic_vector(133160968,28); exponent <= conv_std_logic_vector(1501,11); WHEN "0101001101" => manhi <= conv_std_logic_vector(5629822,24); manlo <= conv_std_logic_vector(4574050,28); exponent <= conv_std_logic_vector(1503,11); WHEN "0101001110" => manhi <= conv_std_logic_vector(13677106,24); manlo <= conv_std_logic_vector(36414601,28); exponent <= conv_std_logic_vector(1504,11); WHEN "0101001111" => manhi <= conv_std_logic_vector(3918641,24); manlo <= conv_std_logic_vector(165046798,28); exponent <= conv_std_logic_vector(1506,11); WHEN "0101010000" => manhi <= conv_std_logic_vector(11351370,24); manlo <= conv_std_logic_vector(225326735,28); exponent <= conv_std_logic_vector(1507,11); WHEN "0101010001" => manhi <= conv_std_logic_vector(2338140,24); manlo <= conv_std_logic_vector(165476611,28); exponent <= conv_std_logic_vector(1509,11); WHEN "0101010010" => manhi <= conv_std_logic_vector(9203247,24); manlo <= conv_std_logic_vector(71807303,28); exponent <= conv_std_logic_vector(1510,11); WHEN "0101010011" => manhi <= conv_std_logic_vector(878339,24); manlo <= conv_std_logic_vector(80195176,28); exponent <= conv_std_logic_vector(1512,11); WHEN "0101010100" => manhi <= conv_std_logic_vector(7219171,24); manlo <= conv_std_logic_vector(153001068,28); exponent <= conv_std_logic_vector(1513,11); WHEN "0101010101" => manhi <= conv_std_logic_vector(15837256,24); manlo <= conv_std_logic_vector(37596960,28); exponent <= conv_std_logic_vector(1514,11); WHEN "0101010110" => manhi <= conv_std_logic_vector(5386615,24); manlo <= conv_std_logic_vector(198850796,28); exponent <= conv_std_logic_vector(1516,11); WHEN "0101010111" => manhi <= conv_std_logic_vector(13346554,24); manlo <= conv_std_logic_vector(143609986,28); exponent <= conv_std_logic_vector(1517,11); WHEN "0101011000" => manhi <= conv_std_logic_vector(3694008,24); manlo <= conv_std_logic_vector(137568494,28); exponent <= conv_std_logic_vector(1519,11); WHEN "0101011001" => manhi <= conv_std_logic_vector(11046062,24); manlo <= conv_std_logic_vector(214558683,28); exponent <= conv_std_logic_vector(1520,11); WHEN "0101011010" => manhi <= conv_std_logic_vector(2130662,24); manlo <= conv_std_logic_vector(78401205,28); exponent <= conv_std_logic_vector(1522,11); WHEN "0101011011" => manhi <= conv_std_logic_vector(8921254,24); manlo <= conv_std_logic_vector(265219821,28); exponent <= conv_std_logic_vector(1523,11); WHEN "0101011100" => manhi <= conv_std_logic_vector(686705,24); manlo <= conv_std_logic_vector(181591149,28); exponent <= conv_std_logic_vector(1525,11); WHEN "0101011101" => manhi <= conv_std_logic_vector(6958714,24); manlo <= conv_std_logic_vector(127078273,28); exponent <= conv_std_logic_vector(1526,11); WHEN "0101011110" => manhi <= conv_std_logic_vector(15483258,24); manlo <= conv_std_logic_vector(65420394,28); exponent <= conv_std_logic_vector(1527,11); WHEN "0101011111" => manhi <= conv_std_logic_vector(5146049,24); manlo <= conv_std_logic_vector(61347424,28); exponent <= conv_std_logic_vector(1529,11); WHEN "0101100000" => manhi <= conv_std_logic_vector(13019590,24); manlo <= conv_std_logic_vector(200148168,28); exponent <= conv_std_logic_vector(1530,11); WHEN "0101100001" => manhi <= conv_std_logic_vector(3471813,24); manlo <= conv_std_logic_vector(155873600,28); exponent <= conv_std_logic_vector(1532,11); WHEN "0101100010" => manhi <= conv_std_logic_vector(10744068,24); manlo <= conv_std_logic_vector(154763366,28); exponent <= conv_std_logic_vector(1533,11); WHEN "0101100011" => manhi <= conv_std_logic_vector(1925435,24); manlo <= conv_std_logic_vector(252346422,28); exponent <= conv_std_logic_vector(1535,11); WHEN "0101100100" => manhi <= conv_std_logic_vector(8642323,24); manlo <= conv_std_logic_vector(122496413,28); exponent <= conv_std_logic_vector(1536,11); WHEN "0101100101" => manhi <= conv_std_logic_vector(497152,24); manlo <= conv_std_logic_vector(12881703,28); exponent <= conv_std_logic_vector(1538,11); WHEN "0101100110" => manhi <= conv_std_logic_vector(6701084,24); manlo <= conv_std_logic_vector(102402698,28); exponent <= conv_std_logic_vector(1539,11); WHEN "0101100111" => manhi <= conv_std_logic_vector(15133102,24); manlo <= conv_std_logic_vector(173151546,28); exponent <= conv_std_logic_vector(1540,11); WHEN "0101101000" => manhi <= conv_std_logic_vector(4908093,24); manlo <= conv_std_logic_vector(222341698,28); exponent <= conv_std_logic_vector(1542,11); WHEN "0101101001" => manhi <= conv_std_logic_vector(12696175,24); manlo <= conv_std_logic_vector(221558290,28); exponent <= conv_std_logic_vector(1543,11); WHEN "0101101010" => manhi <= conv_std_logic_vector(3252030,24); manlo <= conv_std_logic_vector(95425703,28); exponent <= conv_std_logic_vector(1545,11); WHEN "0101101011" => manhi <= conv_std_logic_vector(10445352,24); manlo <= conv_std_logic_vector(54472775,28); exponent <= conv_std_logic_vector(1546,11); WHEN "0101101100" => manhi <= conv_std_logic_vector(1722437,24); manlo <= conv_std_logic_vector(31541381,28); exponent <= conv_std_logic_vector(1548,11); WHEN "0101101101" => manhi <= conv_std_logic_vector(8366419,24); manlo <= conv_std_logic_vector(121077564,28); exponent <= conv_std_logic_vector(1549,11); WHEN "0101101110" => manhi <= conv_std_logic_vector(309655,24); manlo <= conv_std_logic_vector(224679493,28); exponent <= conv_std_logic_vector(1551,11); WHEN "0101101111" => manhi <= conv_std_logic_vector(6446250,24); manlo <= conv_std_logic_vector(163707479,28); exponent <= conv_std_logic_vector(1552,11); WHEN "0101110000" => manhi <= conv_std_logic_vector(14786747,24); manlo <= conv_std_logic_vector(171718440,28); exponent <= conv_std_logic_vector(1553,11); WHEN "0101110001" => manhi <= conv_std_logic_vector(4672721,24); manlo <= conv_std_logic_vector(53414720,28); exponent <= conv_std_logic_vector(1555,11); WHEN "0101110010" => manhi <= conv_std_logic_vector(12376271,24); manlo <= conv_std_logic_vector(68395953,28); exponent <= conv_std_logic_vector(1556,11); WHEN "0101110011" => manhi <= conv_std_logic_vector(3034632,24); manlo <= conv_std_logic_vector(177229210,28); exponent <= conv_std_logic_vector(1558,11); WHEN "0101110100" => manhi <= conv_std_logic_vector(10149878,24); manlo <= conv_std_logic_vector(27015960,28); exponent <= conv_std_logic_vector(1559,11); WHEN "0101110101" => manhi <= conv_std_logic_vector(1521641,24); manlo <= conv_std_logic_vector(173609470,28); exponent <= conv_std_logic_vector(1561,11); WHEN "0101110110" => manhi <= conv_std_logic_vector(8093510,24); manlo <= conv_std_logic_vector(29891310,28); exponent <= conv_std_logic_vector(1562,11); WHEN "0101110111" => manhi <= conv_std_logic_vector(124194,24); manlo <= conv_std_logic_vector(191198183,28); exponent <= conv_std_logic_vector(1564,11); WHEN "0101111000" => manhi <= conv_std_logic_vector(6194182,24); manlo <= conv_std_logic_vector(216692261,28); exponent <= conv_std_logic_vector(1565,11); WHEN "0101111001" => manhi <= conv_std_logic_vector(14444151,24); manlo <= conv_std_logic_vector(261994424,28); exponent <= conv_std_logic_vector(1566,11); WHEN "0101111010" => manhi <= conv_std_logic_vector(4439903,24); manlo <= conv_std_logic_vector(82463931,28); exponent <= conv_std_logic_vector(1568,11); WHEN "0101111011" => manhi <= conv_std_logic_vector(12059838,24); manlo <= conv_std_logic_vector(250318074,28); exponent <= conv_std_logic_vector(1569,11); WHEN "0101111100" => manhi <= conv_std_logic_vector(2819594,24); manlo <= conv_std_logic_vector(161686084,28); exponent <= conv_std_logic_vector(1571,11); WHEN "0101111101" => manhi <= conv_std_logic_vector(9857611,24); manlo <= conv_std_logic_vector(20946108,28); exponent <= conv_std_logic_vector(1572,11); WHEN "0101111110" => manhi <= conv_std_logic_vector(1323025,24); manlo <= conv_std_logic_vector(164440795,28); exponent <= conv_std_logic_vector(1574,11); WHEN "0101111111" => manhi <= conv_std_logic_vector(7823562,24); manlo <= conv_std_logic_vector(250479918,28); exponent <= conv_std_logic_vector(1575,11); WHEN "0110000000" => manhi <= conv_std_logic_vector(16658709,24); manlo <= conv_std_logic_vector(45608811,28); exponent <= conv_std_logic_vector(1576,11); WHEN "0110000001" => manhi <= conv_std_logic_vector(5944850,24); manlo <= conv_std_logic_vector(255488281,28); exponent <= conv_std_logic_vector(1578,11); WHEN "0110000010" => manhi <= conv_std_logic_vector(14105274,24); manlo <= conv_std_logic_vector(228172930,28); exponent <= conv_std_logic_vector(1579,11); WHEN "0110000011" => manhi <= conv_std_logic_vector(4209612,24); manlo <= conv_std_logic_vector(113758652,28); exponent <= conv_std_logic_vector(1581,11); WHEN "0110000100" => manhi <= conv_std_logic_vector(11746841,24); manlo <= conv_std_logic_vector(45816542,28); exponent <= conv_std_logic_vector(1582,11); WHEN "0110000101" => manhi <= conv_std_logic_vector(2606890,24); manlo <= conv_std_logic_vector(153074390,28); exponent <= conv_std_logic_vector(1584,11); WHEN "0110000110" => manhi <= conv_std_logic_vector(9568516,24); manlo <= conv_std_logic_vector(87350878,28); exponent <= conv_std_logic_vector(1585,11); WHEN "0110000111" => manhi <= conv_std_logic_vector(1126565,24); manlo <= conv_std_logic_vector(96475766,28); exponent <= conv_std_logic_vector(1587,11); WHEN "0110001000" => manhi <= conv_std_logic_vector(7556545,24); manlo <= conv_std_logic_vector(205347948,28); exponent <= conv_std_logic_vector(1588,11); WHEN "0110001001" => manhi <= conv_std_logic_vector(16295795,24); manlo <= conv_std_logic_vector(56881285,28); exponent <= conv_std_logic_vector(1589,11); WHEN "0110001010" => manhi <= conv_std_logic_vector(5698225,24); manlo <= conv_std_logic_vector(93263076,28); exponent <= conv_std_logic_vector(1591,11); WHEN "0110001011" => manhi <= conv_std_logic_vector(13770075,24); manlo <= conv_std_logic_vector(241769289,28); exponent <= conv_std_logic_vector(1592,11); WHEN "0110001100" => manhi <= conv_std_logic_vector(3981821,24); manlo <= conv_std_logic_vector(32359920,28); exponent <= conv_std_logic_vector(1594,11); WHEN "0110001101" => manhi <= conv_std_logic_vector(11437240,24); manlo <= conv_std_logic_vector(185367850,28); exponent <= conv_std_logic_vector(1595,11); WHEN "0110001110" => manhi <= conv_std_logic_vector(2396495,24); manlo <= conv_std_logic_vector(61858550,28); exponent <= conv_std_logic_vector(1597,11); WHEN "0110001111" => manhi <= conv_std_logic_vector(9282559,24); manlo <= conv_std_logic_vector(110304027,28); exponent <= conv_std_logic_vector(1598,11); WHEN "0110010000" => manhi <= conv_std_logic_vector(932237,24); manlo <= conv_std_logic_vector(131077892,28); exponent <= conv_std_logic_vector(1600,11); WHEN "0110010001" => manhi <= conv_std_logic_vector(7292426,24); manlo <= conv_std_logic_vector(215982528,28); exponent <= conv_std_logic_vector(1601,11); WHEN "0110010010" => manhi <= conv_std_logic_vector(15936820,24); manlo <= conv_std_logic_vector(87676082,28); exponent <= conv_std_logic_vector(1602,11); WHEN "0110010011" => manhi <= conv_std_logic_vector(5454276,24); manlo <= conv_std_logic_vector(166577430,28); exponent <= conv_std_logic_vector(1604,11); WHEN "0110010100" => manhi <= conv_std_logic_vector(13438515,24); manlo <= conv_std_logic_vector(55023964,28); exponent <= conv_std_logic_vector(1605,11); WHEN "0110010101" => manhi <= conv_std_logic_vector(3756502,24); manlo <= conv_std_logic_vector(71679026,28); exponent <= conv_std_logic_vector(1607,11); WHEN "0110010110" => manhi <= conv_std_logic_vector(11131000,24); manlo <= conv_std_logic_vector(165886683,28); exponent <= conv_std_logic_vector(1608,11); WHEN "0110010111" => manhi <= conv_std_logic_vector(2188383,24); manlo <= conv_std_logic_vector(140750309,28); exponent <= conv_std_logic_vector(1610,11); WHEN "0110011000" => manhi <= conv_std_logic_vector(8999706,24); manlo <= conv_std_logic_vector(74200045,28); exponent <= conv_std_logic_vector(1611,11); WHEN "0110011001" => manhi <= conv_std_logic_vector(740018,24); manlo <= conv_std_logic_vector(229350227,28); exponent <= conv_std_logic_vector(1613,11); WHEN "0110011010" => manhi <= conv_std_logic_vector(7031174,24); manlo <= conv_std_logic_vector(159659309,28); exponent <= conv_std_logic_vector(1614,11); WHEN "0110011011" => manhi <= conv_std_logic_vector(15581741,24); manlo <= conv_std_logic_vector(203828183,28); exponent <= conv_std_logic_vector(1615,11); WHEN "0110011100" => manhi <= conv_std_logic_vector(5212975,24); manlo <= conv_std_logic_vector(192268981,28); exponent <= conv_std_logic_vector(1617,11); WHEN "0110011101" => manhi <= conv_std_logic_vector(13110553,24); manlo <= conv_std_logic_vector(73367990,28); exponent <= conv_std_logic_vector(1618,11); WHEN "0110011110" => manhi <= conv_std_logic_vector(3533629,24); manlo <= conv_std_logic_vector(7303751,28); exponent <= conv_std_logic_vector(1620,11); WHEN "0110011111" => manhi <= conv_std_logic_vector(10828084,24); manlo <= conv_std_logic_vector(128595197,28); exponent <= conv_std_logic_vector(1621,11); WHEN "0110100000" => manhi <= conv_std_logic_vector(1982530,24); manlo <= conv_std_logic_vector(178601213,28); exponent <= conv_std_logic_vector(1623,11); WHEN "0110100001" => manhi <= conv_std_logic_vector(8719923,24); manlo <= conv_std_logic_vector(62665264,28); exponent <= conv_std_logic_vector(1624,11); WHEN "0110100010" => manhi <= conv_std_logic_vector(549886,24); manlo <= conv_std_logic_vector(151395401,28); exponent <= conv_std_logic_vector(1626,11); WHEN "0110100011" => manhi <= conv_std_logic_vector(6772758,24); manlo <= conv_std_logic_vector(5307652,28); exponent <= conv_std_logic_vector(1627,11); WHEN "0110100100" => manhi <= conv_std_logic_vector(15230517,24); manlo <= conv_std_logic_vector(58871965,28); exponent <= conv_std_logic_vector(1628,11); WHEN "0110100101" => manhi <= conv_std_logic_vector(4974293,24); manlo <= conv_std_logic_vector(240265124,28); exponent <= conv_std_logic_vector(1630,11); WHEN "0110100110" => manhi <= conv_std_logic_vector(12786151,24); manlo <= conv_std_logic_vector(11983156,28); exponent <= conv_std_logic_vector(1631,11); WHEN "0110100111" => manhi <= conv_std_logic_vector(3313174,24); manlo <= conv_std_logic_vector(229882212,28); exponent <= conv_std_logic_vector(1633,11); WHEN "0110101000" => manhi <= conv_std_logic_vector(10528456,24); manlo <= conv_std_logic_vector(52550536,28); exponent <= conv_std_logic_vector(1634,11); WHEN "0110101001" => manhi <= conv_std_logic_vector(1778912,24); manlo <= conv_std_logic_vector(36481057,28); exponent <= conv_std_logic_vector(1636,11); WHEN "0110101010" => manhi <= conv_std_logic_vector(8443176,24); manlo <= conv_std_logic_vector(257480801,28); exponent <= conv_std_logic_vector(1637,11); WHEN "0110101011" => manhi <= conv_std_logic_vector(361817,24); manlo <= conv_std_logic_vector(260890045,28); exponent <= conv_std_logic_vector(1639,11); WHEN "0110101100" => manhi <= conv_std_logic_vector(6517146,24); manlo <= conv_std_logic_vector(80951272,28); exponent <= conv_std_logic_vector(1640,11); WHEN "0110101101" => manhi <= conv_std_logic_vector(14883104,24); manlo <= conv_std_logic_vector(234866389,28); exponent <= conv_std_logic_vector(1641,11); WHEN "0110101110" => manhi <= conv_std_logic_vector(4738202,24); manlo <= conv_std_logic_vector(195793257,28); exponent <= conv_std_logic_vector(1643,11); WHEN "0110101111" => manhi <= conv_std_logic_vector(12465269,24); manlo <= conv_std_logic_vector(236730454,28); exponent <= conv_std_logic_vector(1644,11); WHEN "0110110000" => manhi <= conv_std_logic_vector(3095113,24); manlo <= conv_std_logic_vector(133661452,28); exponent <= conv_std_logic_vector(1646,11); WHEN "0110110001" => manhi <= conv_std_logic_vector(10232080,24); manlo <= conv_std_logic_vector(21926822,28); exponent <= conv_std_logic_vector(1647,11); WHEN "0110110010" => manhi <= conv_std_logic_vector(1577503,24); manlo <= conv_std_logic_vector(183764948,28); exponent <= conv_std_logic_vector(1649,11); WHEN "0110110011" => manhi <= conv_std_logic_vector(8169434,24); manlo <= conv_std_logic_vector(132210812,28); exponent <= conv_std_logic_vector(1650,11); WHEN "0110110100" => manhi <= conv_std_logic_vector(175790,24); manlo <= conv_std_logic_vector(182183516,28); exponent <= conv_std_logic_vector(1652,11); WHEN "0110110101" => manhi <= conv_std_logic_vector(6264308,24); manlo <= conv_std_logic_vector(267417858,28); exponent <= conv_std_logic_vector(1653,11); WHEN "0110110110" => manhi <= conv_std_logic_vector(14539463,24); manlo <= conv_std_logic_vector(93573944,28); exponent <= conv_std_logic_vector(1654,11); WHEN "0110110111" => manhi <= conv_std_logic_vector(4504674,24); manlo <= conv_std_logic_vector(26907375,28); exponent <= conv_std_logic_vector(1656,11); WHEN "0110111000" => manhi <= conv_std_logic_vector(12147871,24); manlo <= conv_std_logic_vector(152302066,28); exponent <= conv_std_logic_vector(1657,11); WHEN "0110111001" => manhi <= conv_std_logic_vector(2879418,24); manlo <= conv_std_logic_vector(263131635,28); exponent <= conv_std_logic_vector(1659,11); WHEN "0110111010" => manhi <= conv_std_logic_vector(9938920,24); manlo <= conv_std_logic_vector(224874222,28); exponent <= conv_std_logic_vector(1660,11); WHEN "0110111011" => manhi <= conv_std_logic_vector(1378281,24); manlo <= conv_std_logic_vector(86745210,28); exponent <= conv_std_logic_vector(1662,11); WHEN "0110111100" => manhi <= conv_std_logic_vector(7898663,24); manlo <= conv_std_logic_vector(61761420,28); exponent <= conv_std_logic_vector(1663,11); WHEN "0110111101" => manhi <= conv_std_logic_vector(16760781,24); manlo <= conv_std_logic_vector(15082626,28); exponent <= conv_std_logic_vector(1664,11); WHEN "0110111110" => manhi <= conv_std_logic_vector(6014215,24); manlo <= conv_std_logic_vector(265801199,28); exponent <= conv_std_logic_vector(1666,11); WHEN "0110111111" => manhi <= conv_std_logic_vector(14199551,24); manlo <= conv_std_logic_vector(191056853,28); exponent <= conv_std_logic_vector(1667,11); WHEN "0111000000" => manhi <= conv_std_logic_vector(4273680,24); manlo <= conv_std_logic_vector(52024524,28); exponent <= conv_std_logic_vector(1669,11); WHEN "0111000001" => manhi <= conv_std_logic_vector(11833918,24); manlo <= conv_std_logic_vector(80047690,28); exponent <= conv_std_logic_vector(1670,11); WHEN "0111000010" => manhi <= conv_std_logic_vector(2666065,24); manlo <= conv_std_logic_vector(164712049,28); exponent <= conv_std_logic_vector(1672,11); WHEN "0111000011" => manhi <= conv_std_logic_vector(9648943,24); manlo <= conv_std_logic_vector(147084012,28); exponent <= conv_std_logic_vector(1673,11); WHEN "0111000100" => manhi <= conv_std_logic_vector(1181221,24); manlo <= conv_std_logic_vector(86912647,28); exponent <= conv_std_logic_vector(1675,11); WHEN "0111000101" => manhi <= conv_std_logic_vector(7630830,24); manlo <= conv_std_logic_vector(247596521,28); exponent <= conv_std_logic_vector(1676,11); WHEN "0111000110" => manhi <= conv_std_logic_vector(16396759,24); manlo <= conv_std_logic_vector(56002502,28); exponent <= conv_std_logic_vector(1677,11); WHEN "0111000111" => manhi <= conv_std_logic_vector(5766837,24); manlo <= conv_std_logic_vector(133369322,28); exponent <= conv_std_logic_vector(1679,11); WHEN "0111001000" => manhi <= conv_std_logic_vector(13863329,24); manlo <= conv_std_logic_vector(128884889,28); exponent <= conv_std_logic_vector(1680,11); WHEN "0111001001" => manhi <= conv_std_logic_vector(4045193,24); manlo <= conv_std_logic_vector(133729186,28); exponent <= conv_std_logic_vector(1682,11); WHEN "0111001010" => manhi <= conv_std_logic_vector(11523372,24); manlo <= conv_std_logic_vector(183024104,28); exponent <= conv_std_logic_vector(1683,11); WHEN "0111001011" => manhi <= conv_std_logic_vector(2455027,24); manlo <= conv_std_logic_vector(264977965,28); exponent <= conv_std_logic_vector(1685,11); WHEN "0111001100" => manhi <= conv_std_logic_vector(9362113,24); manlo <= conv_std_logic_vector(181285013,28); exponent <= conv_std_logic_vector(1686,11); WHEN "0111001101" => manhi <= conv_std_logic_vector(986300,24); manlo <= conv_std_logic_vector(58020653,28); exponent <= conv_std_logic_vector(1688,11); WHEN "0111001110" => manhi <= conv_std_logic_vector(7365905,24); manlo <= conv_std_logic_vector(179835810,28); exponent <= conv_std_logic_vector(1689,11); WHEN "0111001111" => manhi <= conv_std_logic_vector(16036688,24); manlo <= conv_std_logic_vector(123168298,28); exponent <= conv_std_logic_vector(1690,11); WHEN "0111010000" => manhi <= conv_std_logic_vector(5522144,24); manlo <= conv_std_logic_vector(14176725,28); exponent <= conv_std_logic_vector(1692,11); WHEN "0111010001" => manhi <= conv_std_logic_vector(13530756,24); manlo <= conv_std_logic_vector(163453775,28); exponent <= conv_std_logic_vector(1693,11); WHEN "0111010010" => manhi <= conv_std_logic_vector(3819186,24); manlo <= conv_std_logic_vector(214764608,28); exponent <= conv_std_logic_vector(1695,11); WHEN "0111010011" => manhi <= conv_std_logic_vector(11216197,24); manlo <= conv_std_logic_vector(196364225,28); exponent <= conv_std_logic_vector(1696,11); WHEN "0111010100" => manhi <= conv_std_logic_vector(2246280,24); manlo <= conv_std_logic_vector(259235483,28); exponent <= conv_std_logic_vector(1698,11); WHEN "0111010101" => manhi <= conv_std_logic_vector(9078397,24); manlo <= conv_std_logic_vector(15526664,28); exponent <= conv_std_logic_vector(1699,11); WHEN "0111010110" => manhi <= conv_std_logic_vector(793494,24); manlo <= conv_std_logic_vector(210641201,28); exponent <= conv_std_logic_vector(1701,11); WHEN "0111010111" => manhi <= conv_std_logic_vector(7103855,24); manlo <= conv_std_logic_vector(246847656,28); exponent <= conv_std_logic_vector(1702,11); WHEN "0111011000" => manhi <= conv_std_logic_vector(15680525,24); manlo <= conv_std_logic_vector(247378795,28); exponent <= conv_std_logic_vector(1703,11); WHEN "0111011001" => manhi <= conv_std_logic_vector(5280106,24); manlo <= conv_std_logic_vector(138122391,28); exponent <= conv_std_logic_vector(1705,11); WHEN "0111011010" => manhi <= conv_std_logic_vector(13201793,24); manlo <= conv_std_logic_vector(130963079,28); exponent <= conv_std_logic_vector(1706,11); WHEN "0111011011" => manhi <= conv_std_logic_vector(3595633,24); manlo <= conv_std_logic_vector(48727293,28); exponent <= conv_std_logic_vector(1708,11); WHEN "0111011100" => manhi <= conv_std_logic_vector(10912356,24); manlo <= conv_std_logic_vector(231400966,28); exponent <= conv_std_logic_vector(1709,11); WHEN "0111011101" => manhi <= conv_std_logic_vector(2039799,24); manlo <= conv_std_logic_vector(184459756,28); exponent <= conv_std_logic_vector(1711,11); WHEN "0111011110" => manhi <= conv_std_logic_vector(8797759,24); manlo <= conv_std_logic_vector(242699544,28); exponent <= conv_std_logic_vector(1712,11); WHEN "0111011111" => manhi <= conv_std_logic_vector(602782,24); manlo <= conv_std_logic_vector(17680793,28); exponent <= conv_std_logic_vector(1714,11); WHEN "0111100000" => manhi <= conv_std_logic_vector(6844650,24); manlo <= conv_std_logic_vector(123627565,28); exponent <= conv_std_logic_vector(1715,11); WHEN "0111100001" => manhi <= conv_std_logic_vector(15328229,24); manlo <= conv_std_logic_vector(47512453,28); exponent <= conv_std_logic_vector(1716,11); WHEN "0111100010" => manhi <= conv_std_logic_vector(5040696,24); manlo <= conv_std_logic_vector(14711664,28); exponent <= conv_std_logic_vector(1718,11); WHEN "0111100011" => manhi <= conv_std_logic_vector(12876400,24); manlo <= conv_std_logic_vector(251456186,28); exponent <= conv_std_logic_vector(1719,11); WHEN "0111100100" => manhi <= conv_std_logic_vector(3374506,24); manlo <= conv_std_logic_vector(4512772,28); exponent <= conv_std_logic_vector(1721,11); WHEN "0111100101" => manhi <= conv_std_logic_vector(10611813,24); manlo <= conv_std_logic_vector(237626642,28); exponent <= conv_std_logic_vector(1722,11); WHEN "0111100110" => manhi <= conv_std_logic_vector(1835559,24); manlo <= conv_std_logic_vector(150064655,28); exponent <= conv_std_logic_vector(1724,11); WHEN "0111100111" => manhi <= conv_std_logic_vector(8520168,24); manlo <= conv_std_logic_vector(211971382,28); exponent <= conv_std_logic_vector(1725,11); WHEN "0111101000" => manhi <= conv_std_logic_vector(414139,24); manlo <= conv_std_logic_vector(92694471,28); exponent <= conv_std_logic_vector(1727,11); WHEN "0111101001" => manhi <= conv_std_logic_vector(6588258,24); manlo <= conv_std_logic_vector(112977613,28); exponent <= conv_std_logic_vector(1728,11); WHEN "0111101010" => manhi <= conv_std_logic_vector(14979756,24); manlo <= conv_std_logic_vector(71348470,28); exponent <= conv_std_logic_vector(1729,11); WHEN "0111101011" => manhi <= conv_std_logic_vector(4803884,24); manlo <= conv_std_logic_vector(42747344,28); exponent <= conv_std_logic_vector(1731,11); WHEN "0111101100" => manhi <= conv_std_logic_vector(12554540,24); manlo <= conv_std_logic_vector(53825836,28); exponent <= conv_std_logic_vector(1732,11); WHEN "0111101101" => manhi <= conv_std_logic_vector(3155778,24); manlo <= conv_std_logic_vector(260157975,28); exponent <= conv_std_logic_vector(1734,11); WHEN "0111101110" => manhi <= conv_std_logic_vector(10314533,24); manlo <= conv_std_logic_vector(1535990,28); exponent <= conv_std_logic_vector(1735,11); WHEN "0111101111" => manhi <= conv_std_logic_vector(1633536,24); manlo <= conv_std_logic_vector(68681060,28); exponent <= conv_std_logic_vector(1737,11); WHEN "0111110000" => manhi <= conv_std_logic_vector(8245590,24); manlo <= conv_std_logic_vector(175202070,28); exponent <= conv_std_logic_vector(1738,11); WHEN "0111110001" => manhi <= conv_std_logic_vector(227544,24); manlo <= conv_std_logic_vector(41675965,28); exponent <= conv_std_logic_vector(1740,11); WHEN "0111110010" => manhi <= conv_std_logic_vector(6334649,24); manlo <= conv_std_logic_vector(70777607,28); exponent <= conv_std_logic_vector(1741,11); WHEN "0111110011" => manhi <= conv_std_logic_vector(14635065,24); manlo <= conv_std_logic_vector(183612561,28); exponent <= conv_std_logic_vector(1742,11); WHEN "0111110100" => manhi <= conv_std_logic_vector(4569642,24); manlo <= conv_std_logic_vector(167240760,28); exponent <= conv_std_logic_vector(1744,11); WHEN "0111110101" => manhi <= conv_std_logic_vector(12236172,24); manlo <= conv_std_logic_vector(253623266,28); exponent <= conv_std_logic_vector(1745,11); WHEN "0111110110" => manhi <= conv_std_logic_vector(2939425,24); manlo <= conv_std_logic_vector(265128301,28); exponent <= conv_std_logic_vector(1747,11); WHEN "0111110111" => manhi <= conv_std_logic_vector(10020478,24); manlo <= conv_std_logic_vector(219223569,28); exponent <= conv_std_logic_vector(1748,11); WHEN "0111111000" => manhi <= conv_std_logic_vector(1433705,24); manlo <= conv_std_logic_vector(192250058,28); exponent <= conv_std_logic_vector(1750,11); WHEN "0111111001" => manhi <= conv_std_logic_vector(7973992,24); manlo <= conv_std_logic_vector(212144821,28); exponent <= conv_std_logic_vector(1751,11); WHEN "0111111010" => manhi <= conv_std_logic_vector(42974,24); manlo <= conv_std_logic_vector(72952107,28); exponent <= conv_std_logic_vector(1753,11); WHEN "0111111011" => manhi <= conv_std_logic_vector(6083792,24); manlo <= conv_std_logic_vector(210315148,28); exponent <= conv_std_logic_vector(1754,11); WHEN "0111111100" => manhi <= conv_std_logic_vector(14294116,24); manlo <= conv_std_logic_vector(101520926,28); exponent <= conv_std_logic_vector(1755,11); WHEN "0111111101" => manhi <= conv_std_logic_vector(4337943,24); manlo <= conv_std_logic_vector(146945490,28); exponent <= conv_std_logic_vector(1757,11); WHEN "0111111110" => manhi <= conv_std_logic_vector(11921261,24); manlo <= conv_std_logic_vector(67478049,28); exponent <= conv_std_logic_vector(1758,11); WHEN "0111111111" => manhi <= conv_std_logic_vector(2725421,24); manlo <= conv_std_logic_vector(81662013,28); exponent <= conv_std_logic_vector(1760,11); WHEN "1000000000" => manhi <= conv_std_logic_vector(9729616,24); manlo <= conv_std_logic_vector(79332654,28); exponent <= conv_std_logic_vector(1761,11); WHEN "1000000001" => manhi <= conv_std_logic_vector(1236044,24); manlo <= conv_std_logic_vector(37511845,28); exponent <= conv_std_logic_vector(1763,11); WHEN "1000000010" => manhi <= conv_std_logic_vector(7705342,24); manlo <= conv_std_logic_vector(229400607,28); exponent <= conv_std_logic_vector(1764,11); WHEN "1000000011" => manhi <= conv_std_logic_vector(16498031,24); manlo <= conv_std_logic_vector(113896411,28); exponent <= conv_std_logic_vector(1765,11); WHEN "1000000100" => manhi <= conv_std_logic_vector(5835659,24); manlo <= conv_std_logic_vector(27578100,28); exponent <= conv_std_logic_vector(1767,11); WHEN "1000000101" => manhi <= conv_std_logic_vector(13956867,24); manlo <= conv_std_logic_vector(198774093,28); exponent <= conv_std_logic_vector(1768,11); WHEN "1000000110" => manhi <= conv_std_logic_vector(4108759,24); manlo <= conv_std_logic_vector(90336304,28); exponent <= conv_std_logic_vector(1770,11); WHEN "1000000111" => manhi <= conv_std_logic_vector(11609767,24); manlo <= conv_std_logic_vector(164675818,28); exponent <= conv_std_logic_vector(1771,11); WHEN "1000001000" => manhi <= conv_std_logic_vector(2513739,24); manlo <= conv_std_logic_vector(115510945,28); exponent <= conv_std_logic_vector(1773,11); WHEN "1000001001" => manhi <= conv_std_logic_vector(9441910,24); manlo <= conv_std_logic_vector(214725537,28); exponent <= conv_std_logic_vector(1774,11); WHEN "1000001010" => manhi <= conv_std_logic_vector(1040527,24); manlo <= conv_std_logic_vector(264292986,28); exponent <= conv_std_logic_vector(1776,11); WHEN "1000001011" => manhi <= conv_std_logic_vector(7439608,24); manlo <= conv_std_logic_vector(227819416,28); exponent <= conv_std_logic_vector(1777,11); WHEN "1000001100" => manhi <= conv_std_logic_vector(16136861,24); manlo <= conv_std_logic_vector(124712281,28); exponent <= conv_std_logic_vector(1778,11); WHEN "1000001101" => manhi <= conv_std_logic_vector(5590218,24); manlo <= conv_std_logic_vector(179347558,28); exponent <= conv_std_logic_vector(1780,11); WHEN "1000001110" => manhi <= conv_std_logic_vector(13623279,24); manlo <= conv_std_logic_vector(162081347,28); exponent <= conv_std_logic_vector(1781,11); WHEN "1000001111" => manhi <= conv_std_logic_vector(3882062,24); manlo <= conv_std_logic_vector(186291443,28); exponent <= conv_std_logic_vector(1783,11); WHEN "1000010000" => manhi <= conv_std_logic_vector(11301654,24); manlo <= conv_std_logic_vector(250040022,28); exponent <= conv_std_logic_vector(1784,11); WHEN "1000010001" => manhi <= conv_std_logic_vector(2304355,24); manlo <= conv_std_logic_vector(41383777,28); exponent <= conv_std_logic_vector(1786,11); WHEN "1000010010" => manhi <= conv_std_logic_vector(9157328,24); manlo <= conv_std_logic_vector(17021400,28); exponent <= conv_std_logic_vector(1787,11); WHEN "1000010011" => manhi <= conv_std_logic_vector(847133,24); manlo <= conv_std_logic_vector(258834653,28); exponent <= conv_std_logic_vector(1789,11); WHEN "1000010100" => manhi <= conv_std_logic_vector(7176759,24); manlo <= conv_std_logic_vector(33041815,28); exponent <= conv_std_logic_vector(1790,11); WHEN "1000010101" => manhi <= conv_std_logic_vector(15779611,24); manlo <= conv_std_logic_vector(174007449,28); exponent <= conv_std_logic_vector(1791,11); WHEN "1000010110" => manhi <= conv_std_logic_vector(5347442,24); manlo <= conv_std_logic_vector(66333886,28); exponent <= conv_std_logic_vector(1793,11); WHEN "1000010111" => manhi <= conv_std_logic_vector(13293312,24); manlo <= conv_std_logic_vector(63618366,28); exponent <= conv_std_logic_vector(1794,11); WHEN "1000011000" => manhi <= conv_std_logic_vector(3657826,24); manlo <= conv_std_logic_vector(166348998,28); exponent <= conv_std_logic_vector(1796,11); WHEN "1000011001" => manhi <= conv_std_logic_vector(10996886,24); manlo <= conv_std_logic_vector(136487624,28); exponent <= conv_std_logic_vector(1797,11); WHEN "1000011010" => manhi <= conv_std_logic_vector(2097243,24); manlo <= conv_std_logic_vector(144317262,28); exponent <= conv_std_logic_vector(1799,11); WHEN "1000011011" => manhi <= conv_std_logic_vector(8875834,24); manlo <= conv_std_logic_vector(51419886,28); exponent <= conv_std_logic_vector(1800,11); WHEN "1000011100" => manhi <= conv_std_logic_vector(655839,24); manlo <= conv_std_logic_vector(12096311,28); exponent <= conv_std_logic_vector(1802,11); WHEN "1000011101" => manhi <= conv_std_logic_vector(6916762,24); manlo <= conv_std_logic_vector(99793437,28); exponent <= conv_std_logic_vector(1803,11); WHEN "1000011110" => manhi <= conv_std_logic_vector(15426239,24); manlo <= conv_std_logic_vector(114334116,28); exponent <= conv_std_logic_vector(1804,11); WHEN "1000011111" => manhi <= conv_std_logic_vector(5107300,24); manlo <= conv_std_logic_vector(248161218,28); exponent <= conv_std_logic_vector(1806,11); WHEN "1000100000" => manhi <= conv_std_logic_vector(12966926,24); manlo <= conv_std_logic_vector(91321506,28); exponent <= conv_std_logic_vector(1807,11); WHEN "1000100001" => manhi <= conv_std_logic_vector(3436024,24); manlo <= conv_std_logic_vector(109150055,28); exponent <= conv_std_logic_vector(1809,11); WHEN "1000100010" => manhi <= conv_std_logic_vector(10695426,24); manlo <= conv_std_logic_vector(12291314,28); exponent <= conv_std_logic_vector(1810,11); WHEN "1000100011" => manhi <= conv_std_logic_vector(1892379,24); manlo <= conv_std_logic_vector(245137096,28); exponent <= conv_std_logic_vector(1812,11); WHEN "1000100100" => manhi <= conv_std_logic_vector(8597395,24); manlo <= conv_std_logic_vector(176569250,28); exponent <= conv_std_logic_vector(1813,11); WHEN "1000100101" => manhi <= conv_std_logic_vector(466620,24); manlo <= conv_std_logic_vector(119019308,28); exponent <= conv_std_logic_vector(1815,11); WHEN "1000100110" => manhi <= conv_std_logic_vector(6659587,24); manlo <= conv_std_logic_vector(168706814,28); exponent <= conv_std_logic_vector(1816,11); WHEN "1000100111" => manhi <= conv_std_logic_vector(15076702,24); manlo <= conv_std_logic_vector(190651618,28); exponent <= conv_std_logic_vector(1817,11); WHEN "1000101000" => manhi <= conv_std_logic_vector(4869766,24); manlo <= conv_std_logic_vector(26523901,28); exponent <= conv_std_logic_vector(1819,11); WHEN "1000101001" => manhi <= conv_std_logic_vector(12644083,24); manlo <= conv_std_logic_vector(10760420,28); exponent <= conv_std_logic_vector(1820,11); WHEN "1000101010" => manhi <= conv_std_logic_vector(3216629,24); manlo <= conv_std_logic_vector(171149379,28); exponent <= conv_std_logic_vector(1822,11); WHEN "1000101011" => manhi <= conv_std_logic_vector(10397237,24); manlo <= conv_std_logic_vector(171483537,28); exponent <= conv_std_logic_vector(1823,11); WHEN "1000101100" => manhi <= conv_std_logic_vector(1689739,24); manlo <= conv_std_logic_vector(236540182,28); exponent <= conv_std_logic_vector(1825,11); WHEN "1000101101" => manhi <= conv_std_logic_vector(8321979,24); manlo <= conv_std_logic_vector(80365386,28); exponent <= conv_std_logic_vector(1826,11); WHEN "1000101110" => manhi <= conv_std_logic_vector(279455,24); manlo <= conv_std_logic_vector(167185714,28); exponent <= conv_std_logic_vector(1828,11); WHEN "1000101111" => manhi <= conv_std_logic_vector(6405204,24); manlo <= conv_std_logic_vector(70637708,28); exponent <= conv_std_logic_vector(1829,11); WHEN "1000110000" => manhi <= conv_std_logic_vector(14730959,24); manlo <= conv_std_logic_vector(233674466,28); exponent <= conv_std_logic_vector(1830,11); WHEN "1000110001" => manhi <= conv_std_logic_vector(4634809,24); manlo <= conv_std_logic_vector(128626627,28); exponent <= conv_std_logic_vector(1832,11); WHEN "1000110010" => manhi <= conv_std_logic_vector(12324743,24); manlo <= conv_std_logic_vector(237637056,28); exponent <= conv_std_logic_vector(1833,11); WHEN "1000110011" => manhi <= conv_std_logic_vector(2999616,24); manlo <= conv_std_logic_vector(48899908,28); exponent <= conv_std_logic_vector(1835,11); WHEN "1000110100" => manhi <= conv_std_logic_vector(10102285,24); manlo <= conv_std_logic_vector(207402206,28); exponent <= conv_std_logic_vector(1836,11); WHEN "1000110101" => manhi <= conv_std_logic_vector(1489299,24); manlo <= conv_std_logic_vector(82314533,28); exponent <= conv_std_logic_vector(1838,11); WHEN "1000110110" => manhi <= conv_std_logic_vector(8049552,24); manlo <= conv_std_logic_vector(84197942,28); exponent <= conv_std_logic_vector(1839,11); WHEN "1000110111" => manhi <= conv_std_logic_vector(94322,24); manlo <= conv_std_logic_vector(78275083,28); exponent <= conv_std_logic_vector(1841,11); WHEN "1000111000" => manhi <= conv_std_logic_vector(6153581,24); manlo <= conv_std_logic_vector(262556746,28); exponent <= conv_std_logic_vector(1842,11); WHEN "1000111001" => manhi <= conv_std_logic_vector(14388969,24); manlo <= conv_std_logic_vector(195412276,28); exponent <= conv_std_logic_vector(1843,11); WHEN "1000111010" => manhi <= conv_std_logic_vector(4402403,24); manlo <= conv_std_logic_vector(21925377,28); exponent <= conv_std_logic_vector(1845,11); WHEN "1000111011" => manhi <= conv_std_logic_vector(12008870,24); manlo <= conv_std_logic_vector(225943576,28); exponent <= conv_std_logic_vector(1846,11); WHEN "1000111100" => manhi <= conv_std_logic_vector(2784958,24); manlo <= conv_std_logic_vector(51959162,28); exponent <= conv_std_logic_vector(1848,11); WHEN "1000111101" => manhi <= conv_std_logic_vector(9810535,24); manlo <= conv_std_logic_vector(85297068,28); exponent <= conv_std_logic_vector(1849,11); WHEN "1000111110" => manhi <= conv_std_logic_vector(1291034,24); manlo <= conv_std_logic_vector(85003113,28); exponent <= conv_std_logic_vector(1851,11); WHEN "1000111111" => manhi <= conv_std_logic_vector(7780082,24); manlo <= conv_std_logic_vector(68159752,28); exponent <= conv_std_logic_vector(1852,11); WHEN "1001000000" => manhi <= conv_std_logic_vector(16599612,24); manlo <= conv_std_logic_vector(214703512,28); exponent <= conv_std_logic_vector(1853,11); WHEN "1001000001" => manhi <= conv_std_logic_vector(5904690,24); manlo <= conv_std_logic_vector(215968023,28); exponent <= conv_std_logic_vector(1855,11); WHEN "1001000010" => manhi <= conv_std_logic_vector(14050691,24); manlo <= conv_std_logic_vector(147853227,28); exponent <= conv_std_logic_vector(1856,11); WHEN "1001000011" => manhi <= conv_std_logic_vector(4172519,24); manlo <= conv_std_logic_vector(60716388,28); exponent <= conv_std_logic_vector(1858,11); WHEN "1001000100" => manhi <= conv_std_logic_vector(11696426,24); manlo <= conv_std_logic_vector(77359100,28); exponent <= conv_std_logic_vector(1859,11); WHEN "1001000101" => manhi <= conv_std_logic_vector(2572630,24); manlo <= conv_std_logic_vector(28321055,28); exponent <= conv_std_logic_vector(1861,11); WHEN "1001000110" => manhi <= conv_std_logic_vector(9521951,24); manlo <= conv_std_logic_vector(141206574,28); exponent <= conv_std_logic_vector(1862,11); WHEN "1001000111" => manhi <= conv_std_logic_vector(1094921,24); manlo <= conv_std_logic_vector(79834212,28); exponent <= conv_std_logic_vector(1864,11); WHEN "1001001000" => manhi <= conv_std_logic_vector(7513537,24); manlo <= conv_std_logic_vector(6880382,28); exponent <= conv_std_logic_vector(1865,11); WHEN "1001001001" => manhi <= conv_std_logic_vector(16237340,24); manlo <= conv_std_logic_vector(73707069,28); exponent <= conv_std_logic_vector(1866,11); WHEN "1001001010" => manhi <= conv_std_logic_vector(5658501,24); manlo <= conv_std_logic_vector(26563701,28); exponent <= conv_std_logic_vector(1868,11); WHEN "1001001011" => manhi <= conv_std_logic_vector(13716085,24); manlo <= conv_std_logic_vector(13226359,28); exponent <= conv_std_logic_vector(1869,11); WHEN "1001001100" => manhi <= conv_std_logic_vector(3945130,24); manlo <= conv_std_logic_vector(143073903,28); exponent <= conv_std_logic_vector(1871,11); WHEN "1001001101" => manhi <= conv_std_logic_vector(11387373,24); manlo <= conv_std_logic_vector(3175990,28); exponent <= conv_std_logic_vector(1872,11); WHEN "1001001110" => manhi <= conv_std_logic_vector(2362606,24); manlo <= conv_std_logic_vector(168904878,28); exponent <= conv_std_logic_vector(1874,11); WHEN "1001001111" => manhi <= conv_std_logic_vector(9236500,24); manlo <= conv_std_logic_vector(7105104,28); exponent <= conv_std_logic_vector(1875,11); WHEN "1001010000" => manhi <= conv_std_logic_vector(900936,24); manlo <= conv_std_logic_vector(239272854,28); exponent <= conv_std_logic_vector(1877,11); WHEN "1001010001" => manhi <= conv_std_logic_vector(7249884,24); manlo <= conv_std_logic_vector(236935482,28); exponent <= conv_std_logic_vector(1878,11); WHEN "1001010010" => manhi <= conv_std_logic_vector(15878999,24); manlo <= conv_std_logic_vector(230836932,28); exponent <= conv_std_logic_vector(1879,11); WHEN "1001010011" => manhi <= conv_std_logic_vector(5414983,24); manlo <= conv_std_logic_vector(144840810,28); exponent <= conv_std_logic_vector(1881,11); WHEN "1001010100" => manhi <= conv_std_logic_vector(13385110,24); manlo <= conv_std_logic_vector(99584369,28); exponent <= conv_std_logic_vector(1882,11); WHEN "1001010101" => manhi <= conv_std_logic_vector(3720209,24); manlo <= conv_std_logic_vector(246845719,28); exponent <= conv_std_logic_vector(1884,11); WHEN "1001010110" => manhi <= conv_std_logic_vector(11081674,24); manlo <= conv_std_logic_vector(54674652,28); exponent <= conv_std_logic_vector(1885,11); WHEN "1001010111" => manhi <= conv_std_logic_vector(2154862,24); manlo <= conv_std_logic_vector(201440422,28); exponent <= conv_std_logic_vector(1887,11); WHEN "1001011000" => manhi <= conv_std_logic_vector(8954146,24); manlo <= conv_std_logic_vector(220416825,28); exponent <= conv_std_logic_vector(1888,11); WHEN "1001011001" => manhi <= conv_std_logic_vector(709057,24); manlo <= conv_std_logic_vector(266967657,28); exponent <= conv_std_logic_vector(1890,11); WHEN "1001011010" => manhi <= conv_std_logic_vector(6989094,24); manlo <= conv_std_logic_vector(113654547,28); exponent <= conv_std_logic_vector(1891,11); WHEN "1001011011" => manhi <= conv_std_logic_vector(15524548,24); manlo <= conv_std_logic_vector(235342013,28); exponent <= conv_std_logic_vector(1892,11); WHEN "1001011100" => manhi <= conv_std_logic_vector(5174109,24); manlo <= conv_std_logic_vector(32986511,28); exponent <= conv_std_logic_vector(1894,11); WHEN "1001011101" => manhi <= conv_std_logic_vector(13057728,24); manlo <= conv_std_logic_vector(25787653,28); exponent <= conv_std_logic_vector(1895,11); WHEN "1001011110" => manhi <= conv_std_logic_vector(3497730,24); manlo <= conv_std_logic_vector(160351868,28); exponent <= conv_std_logic_vector(1897,11); WHEN "1001011111" => manhi <= conv_std_logic_vector(10779293,24); manlo <= conv_std_logic_vector(121946709,28); exponent <= conv_std_logic_vector(1898,11); WHEN "1001100000" => manhi <= conv_std_logic_vector(1949373,24); manlo <= conv_std_logic_vector(194974600,28); exponent <= conv_std_logic_vector(1900,11); WHEN "1001100001" => manhi <= conv_std_logic_vector(8674858,24); manlo <= conv_std_logic_vector(75445083,28); exponent <= conv_std_logic_vector(1901,11); WHEN "1001100010" => manhi <= conv_std_logic_vector(519261,24); manlo <= conv_std_logic_vector(202318540,28); exponent <= conv_std_logic_vector(1903,11); WHEN "1001100011" => manhi <= conv_std_logic_vector(6731134,24); manlo <= conv_std_logic_vector(157600610,28); exponent <= conv_std_logic_vector(1904,11); WHEN "1001100100" => manhi <= conv_std_logic_vector(15173945,24); manlo <= conv_std_logic_vector(29256816,28); exponent <= conv_std_logic_vector(1905,11); WHEN "1001100101" => manhi <= conv_std_logic_vector(4935849,24); manlo <= conv_std_logic_vector(42999013,28); exponent <= conv_std_logic_vector(1907,11); WHEN "1001100110" => manhi <= conv_std_logic_vector(12733899,24); manlo <= conv_std_logic_vector(62421287,28); exponent <= conv_std_logic_vector(1908,11); WHEN "1001100111" => manhi <= conv_std_logic_vector(3277666,24); manlo <= conv_std_logic_vector(18399062,28); exponent <= conv_std_logic_vector(1910,11); WHEN "1001101000" => manhi <= conv_std_logic_vector(10480194,24); manlo <= conv_std_logic_vector(201166396,28); exponent <= conv_std_logic_vector(1911,11); WHEN "1001101001" => manhi <= conv_std_logic_vector(1746115,24); manlo <= conv_std_logic_vector(22209480,28); exponent <= conv_std_logic_vector(1913,11); WHEN "1001101010" => manhi <= conv_std_logic_vector(8398601,24); manlo <= conv_std_logic_vector(38216343,28); exponent <= conv_std_logic_vector(1914,11); WHEN "1001101011" => manhi <= conv_std_logic_vector(331525,24); manlo <= conv_std_logic_vector(151310615,28); exponent <= conv_std_logic_vector(1916,11); WHEN "1001101100" => manhi <= conv_std_logic_vector(6475974,24); manlo <= conv_std_logic_vector(174528998,28); exponent <= conv_std_logic_vector(1917,11); WHEN "1001101101" => manhi <= conv_std_logic_vector(14827146,24); manlo <= conv_std_logic_vector(214487191,28); exponent <= conv_std_logic_vector(1918,11); WHEN "1001101110" => manhi <= conv_std_logic_vector(4700175,24); manlo <= conv_std_logic_vector(73593076,28); exponent <= conv_std_logic_vector(1920,11); WHEN "1001101111" => manhi <= conv_std_logic_vector(12413585,24); manlo <= conv_std_logic_vector(56806573,28); exponent <= conv_std_logic_vector(1921,11); WHEN "1001110000" => manhi <= conv_std_logic_vector(3059990,24); manlo <= conv_std_logic_vector(32998071,28); exponent <= conv_std_logic_vector(1923,11); WHEN "1001110001" => manhi <= conv_std_logic_vector(10184342,24); manlo <= conv_std_logic_vector(125003687,28); exponent <= conv_std_logic_vector(1924,11); WHEN "1001110010" => manhi <= conv_std_logic_vector(1545062,24); manlo <= conv_std_logic_vector(164026180,28); exponent <= conv_std_logic_vector(1926,11); WHEN "1001110011" => manhi <= conv_std_logic_vector(8125342,24); manlo <= conv_std_logic_vector(134803968,28); exponent <= conv_std_logic_vector(1927,11); WHEN "1001110100" => manhi <= conv_std_logic_vector(145827,24); manlo <= conv_std_logic_vector(17356019,28); exponent <= conv_std_logic_vector(1929,11); WHEN "1001110101" => manhi <= conv_std_logic_vector(6223584,24); manlo <= conv_std_logic_vector(59711433,28); exponent <= conv_std_logic_vector(1930,11); WHEN "1001110110" => manhi <= conv_std_logic_vector(14484112,24); manlo <= conv_std_logic_vector(172427100,28); exponent <= conv_std_logic_vector(1931,11); WHEN "1001110111" => manhi <= conv_std_logic_vector(4467059,24); manlo <= conv_std_logic_vector(106163660,28); exponent <= conv_std_logic_vector(1933,11); WHEN "1001111000" => manhi <= conv_std_logic_vector(12096747,24); manlo <= conv_std_logic_vector(237074316,28); exponent <= conv_std_logic_vector(1934,11); WHEN "1001111001" => manhi <= conv_std_logic_vector(2844676,24); manlo <= conv_std_logic_vector(224090291,28); exponent <= conv_std_logic_vector(1936,11); WHEN "1001111010" => manhi <= conv_std_logic_vector(9891701,24); manlo <= conv_std_logic_vector(98356275,28); exponent <= conv_std_logic_vector(1937,11); WHEN "1001111011" => manhi <= conv_std_logic_vector(1346192,24); manlo <= conv_std_logic_vector(98098154,28); exponent <= conv_std_logic_vector(1939,11); WHEN "1001111100" => manhi <= conv_std_logic_vector(7855049,24); manlo <= conv_std_logic_vector(218711727,28); exponent <= conv_std_logic_vector(1940,11); WHEN "1001111101" => manhi <= conv_std_logic_vector(16701504,24); manlo <= conv_std_logic_vector(74899902,28); exponent <= conv_std_logic_vector(1941,11); WHEN "1001111110" => manhi <= conv_std_logic_vector(5973933,24); manlo <= conv_std_logic_vector(65399866,28); exponent <= conv_std_logic_vector(1943,11); WHEN "1001111111" => manhi <= conv_std_logic_vector(14144801,24); manlo <= conv_std_logic_vector(210121699,28); exponent <= conv_std_logic_vector(1944,11); WHEN "1010000000" => manhi <= conv_std_logic_vector(4236473,24); manlo <= conv_std_logic_vector(203888522,28); exponent <= conv_std_logic_vector(1946,11); WHEN "1010000001" => manhi <= conv_std_logic_vector(11783349,24); manlo <= conv_std_logic_vector(137203293,28); exponent <= conv_std_logic_vector(1947,11); WHEN "1010000010" => manhi <= conv_std_logic_vector(2631700,24); manlo <= conv_std_logic_vector(150283410,28); exponent <= conv_std_logic_vector(1949,11); WHEN "1010000011" => manhi <= conv_std_logic_vector(9602236,24); manlo <= conv_std_logic_vector(160352104,28); exponent <= conv_std_logic_vector(1950,11); WHEN "1010000100" => manhi <= conv_std_logic_vector(1149480,24); manlo <= conv_std_logic_vector(177173803,28); exponent <= conv_std_logic_vector(1952,11); WHEN "1010000101" => manhi <= conv_std_logic_vector(7587690,24); manlo <= conv_std_logic_vector(238268718,28); exponent <= conv_std_logic_vector(1953,11); WHEN "1010000110" => manhi <= conv_std_logic_vector(16338125,24); manlo <= conv_std_logic_vector(220749839,28); exponent <= conv_std_logic_vector(1954,11); WHEN "1010000111" => manhi <= conv_std_logic_vector(5726991,24); manlo <= conv_std_logic_vector(262994505,28); exponent <= conv_std_logic_vector(1956,11); WHEN "1010001000" => manhi <= conv_std_logic_vector(13809173,24); manlo <= conv_std_logic_vector(216783842,28); exponent <= conv_std_logic_vector(1957,11); WHEN "1010001001" => manhi <= conv_std_logic_vector(4008390,24); manlo <= conv_std_logic_vector(242405077,28); exponent <= conv_std_logic_vector(1959,11); WHEN "1010001010" => manhi <= conv_std_logic_vector(11473352,24); manlo <= conv_std_logic_vector(206426515,28); exponent <= conv_std_logic_vector(1960,11); WHEN "1010001011" => manhi <= conv_std_logic_vector(2421035,24); manlo <= conv_std_logic_vector(250208807,28); exponent <= conv_std_logic_vector(1962,11); WHEN "1010001100" => manhi <= conv_std_logic_vector(9315913,24); manlo <= conv_std_logic_vector(183235034,28); exponent <= conv_std_logic_vector(1963,11); WHEN "1010001101" => manhi <= conv_std_logic_vector(954904,24); manlo <= conv_std_logic_vector(17706469,28); exponent <= conv_std_logic_vector(1965,11); WHEN "1010001110" => manhi <= conv_std_logic_vector(7323233,24); manlo <= conv_std_logic_vector(235600136,28); exponent <= conv_std_logic_vector(1966,11); WHEN "1010001111" => manhi <= conv_std_logic_vector(15978691,24); manlo <= conv_std_logic_vector(128873524,28); exponent <= conv_std_logic_vector(1967,11); WHEN "1010010000" => manhi <= conv_std_logic_vector(5482731,24); manlo <= conv_std_logic_vector(5222268,28); exponent <= conv_std_logic_vector(1969,11); WHEN "1010010001" => manhi <= conv_std_logic_vector(13477188,24); manlo <= conv_std_logic_vector(199372940,28); exponent <= conv_std_logic_vector(1970,11); WHEN "1010010010" => manhi <= conv_std_logic_vector(3782783,24); manlo <= conv_std_logic_vector(177367827,28); exponent <= conv_std_logic_vector(1972,11); WHEN "1010010011" => manhi <= conv_std_logic_vector(11166720,24); manlo <= conv_std_logic_vector(197425116,28); exponent <= conv_std_logic_vector(1973,11); WHEN "1010010100" => manhi <= conv_std_logic_vector(2212657,24); manlo <= conv_std_logic_vector(231097832,28); exponent <= conv_std_logic_vector(1975,11); WHEN "1010010101" => manhi <= conv_std_logic_vector(9032698,24); manlo <= conv_std_logic_vector(139698050,28); exponent <= conv_std_logic_vector(1976,11); WHEN "1010010110" => manhi <= conv_std_logic_vector(762439,24); manlo <= conv_std_logic_vector(109718127,28); exponent <= conv_std_logic_vector(1978,11); WHEN "1010010111" => manhi <= conv_std_logic_vector(7061647,24); manlo <= conv_std_logic_vector(77173752,28); exponent <= conv_std_logic_vector(1979,11); WHEN "1010011000" => manhi <= conv_std_logic_vector(15623158,24); manlo <= conv_std_logic_vector(118851961,28); exponent <= conv_std_logic_vector(1980,11); WHEN "1010011001" => manhi <= conv_std_logic_vector(5241121,24); manlo <= conv_std_logic_vector(72680114,28); exponent <= conv_std_logic_vector(1982,11); WHEN "1010011010" => manhi <= conv_std_logic_vector(13148807,24); manlo <= conv_std_logic_vector(12881486,28); exponent <= conv_std_logic_vector(1983,11); WHEN "1010011011" => manhi <= conv_std_logic_vector(3559625,24); manlo <= conv_std_logic_vector(43579850,28); exponent <= conv_std_logic_vector(1985,11); WHEN "1010011100" => manhi <= conv_std_logic_vector(10863416,24); manlo <= conv_std_logic_vector(238889758,28); exponent <= conv_std_logic_vector(1986,11); WHEN "1010011101" => manhi <= conv_std_logic_vector(2006541,24); manlo <= conv_std_logic_vector(141721451,28); exponent <= conv_std_logic_vector(1988,11); WHEN "1010011110" => manhi <= conv_std_logic_vector(8752557,24); manlo <= conv_std_logic_vector(101792997,28); exponent <= conv_std_logic_vector(1989,11); WHEN "1010011111" => manhi <= conv_std_logic_vector(572063,24); manlo <= conv_std_logic_vector(205445723,28); exponent <= conv_std_logic_vector(1991,11); WHEN "1010100000" => manhi <= conv_std_logic_vector(6802899,24); manlo <= conv_std_logic_vector(258099270,28); exponent <= conv_std_logic_vector(1992,11); WHEN "1010100001" => manhi <= conv_std_logic_vector(15271484,24); manlo <= conv_std_logic_vector(98124990,28); exponent <= conv_std_logic_vector(1993,11); WHEN "1010100010" => manhi <= conv_std_logic_vector(5002133,24); manlo <= conv_std_logic_vector(256985826,28); exponent <= conv_std_logic_vector(1995,11); WHEN "1010100011" => manhi <= conv_std_logic_vector(12823989,24); manlo <= conv_std_logic_vector(164377270,28); exponent <= conv_std_logic_vector(1996,11); WHEN "1010100100" => manhi <= conv_std_logic_vector(3338888,24); manlo <= conv_std_logic_vector(222569178,28); exponent <= conv_std_logic_vector(1998,11); WHEN "1010100101" => manhi <= conv_std_logic_vector(10563405,24); manlo <= conv_std_logic_vector(29046646,28); exponent <= conv_std_logic_vector(1999,11); WHEN "1010100110" => manhi <= conv_std_logic_vector(1802662,24); manlo <= conv_std_logic_vector(103161316,28); exponent <= conv_std_logic_vector(2001,11); WHEN "1010100111" => manhi <= conv_std_logic_vector(8475456,24); manlo <= conv_std_logic_vector(239852126,28); exponent <= conv_std_logic_vector(2002,11); WHEN "1010101000" => manhi <= conv_std_logic_vector(383754,24); manlo <= conv_std_logic_vector(123914668,28); exponent <= conv_std_logic_vector(2004,11); WHEN "1010101001" => manhi <= conv_std_logic_vector(6546961,24); manlo <= conv_std_logic_vector(22084044,28); exponent <= conv_std_logic_vector(2005,11); WHEN "1010101010" => manhi <= conv_std_logic_vector(14923627,24); manlo <= conv_std_logic_vector(97508377,28); exponent <= conv_std_logic_vector(2006,11); WHEN "1010101011" => manhi <= conv_std_logic_vector(4765740,24); manlo <= conv_std_logic_vector(165164368,28); exponent <= conv_std_logic_vector(2008,11); WHEN "1010101100" => manhi <= conv_std_logic_vector(12502697,24); manlo <= conv_std_logic_vector(201140216,28); exponent <= conv_std_logic_vector(2009,11); WHEN "1010101101" => manhi <= conv_std_logic_vector(3120548,24); manlo <= conv_std_logic_vector(99561759,28); exponent <= conv_std_logic_vector(2011,11); WHEN "1010101110" => manhi <= conv_std_logic_vector(10266649,24); manlo <= conv_std_logic_vector(176679877,28); exponent <= conv_std_logic_vector(2012,11); WHEN "1010101111" => manhi <= conv_std_logic_vector(1600996,24); manlo <= conv_std_logic_vector(39589446,28); exponent <= conv_std_logic_vector(2014,11); WHEN "1010110000" => manhi <= conv_std_logic_vector(8201364,24); manlo <= conv_std_logic_vector(16114999,28); exponent <= conv_std_logic_vector(2015,11); WHEN "1010110001" => manhi <= conv_std_logic_vector(197489,24); manlo <= conv_std_logic_vector(18649371,28); exponent <= conv_std_logic_vector(2017,11); WHEN "1010110010" => manhi <= conv_std_logic_vector(6293800,24); manlo <= conv_std_logic_vector(44802372,28); exponent <= conv_std_logic_vector(2018,11); WHEN "1010110011" => manhi <= conv_std_logic_vector(14579546,24); manlo <= conv_std_logic_vector(1419236,28); exponent <= conv_std_logic_vector(2019,11); WHEN "1010110100" => manhi <= conv_std_logic_vector(4531913,24); manlo <= conv_std_logic_vector(24044223,28); exponent <= conv_std_logic_vector(2021,11); WHEN "1010110101" => manhi <= conv_std_logic_vector(12184893,24); manlo <= conv_std_logic_vector(51602800,28); exponent <= conv_std_logic_vector(2022,11); WHEN "1010110110" => manhi <= conv_std_logic_vector(2904577,24); manlo <= conv_std_logic_vector(210124577,28); exponent <= conv_std_logic_vector(2024,11); WHEN "1010110111" => manhi <= conv_std_logic_vector(9973115,24); manlo <= conv_std_logic_vector(52505388,28); exponent <= conv_std_logic_vector(2025,11); WHEN "1010111000" => manhi <= conv_std_logic_vector(1401518,24); manlo <= conv_std_logic_vector(214362802,28); exponent <= conv_std_logic_vector(2027,11); WHEN "1010111001" => manhi <= conv_std_logic_vector(7930246,24); manlo <= conv_std_logic_vector(62721516,28); exponent <= conv_std_logic_vector(2028,11); WHEN "1010111010" => manhi <= conv_std_logic_vector(13245,24); manlo <= conv_std_logic_vector(108520727,28); exponent <= conv_std_logic_vector(2030,11); WHEN "1010111011" => manhi <= conv_std_logic_vector(6043387,24); manlo <= conv_std_logic_vector(17001813,28); exponent <= conv_std_logic_vector(2031,11); WHEN "1010111100" => manhi <= conv_std_logic_vector(14239199,24); manlo <= conv_std_logic_vector(83422350,28); exponent <= conv_std_logic_vector(2032,11); WHEN "1010111101" => manhi <= conv_std_logic_vector(4300623,24); manlo <= conv_std_logic_vector(142486326,28); exponent <= conv_std_logic_vector(2034,11); WHEN "1010111110" => manhi <= conv_std_logic_vector(11870538,24); manlo <= conv_std_logic_vector(24126621,28); exponent <= conv_std_logic_vector(2035,11); WHEN "1010111111" => manhi <= conv_std_logic_vector(2690951,24); manlo <= conv_std_logic_vector(91850592,28); exponent <= conv_std_logic_vector(2037,11); WHEN "1011000000" => manhi <= conv_std_logic_vector(9682766,24); manlo <= conv_std_logic_vector(203960059,28); exponent <= conv_std_logic_vector(2038,11); WHEN "1011000001" => manhi <= conv_std_logic_vector(1204206,24); manlo <= conv_std_logic_vector(155513539,28); exponent <= conv_std_logic_vector(2040,11); WHEN "1011000010" => manhi <= conv_std_logic_vector(7662071,24); manlo <= conv_std_logic_vector(33184566,28); exponent <= conv_std_logic_vector(2041,11); WHEN "1011000011" => manhi <= conv_std_logic_vector(16439219,24); manlo <= conv_std_logic_vector(11896414,28); exponent <= conv_std_logic_vector(2042,11); WHEN "1011000100" => manhi <= conv_std_logic_vector(5795691,24); manlo <= conv_std_logic_vector(254151921,28); exponent <= conv_std_logic_vector(2044,11); WHEN "1011000101" => manhi <= conv_std_logic_vector(13902546,24); manlo <= conv_std_logic_vector(199613595,28); exponent <= conv_std_logic_vector(2045,11); WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_explutpos IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_explutpos; ARCHITECTURE rtl OF dp_explutpos IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(1023,11); WHEN "0000000001" => manhi <= conv_std_logic_vector(6025384,24); manlo <= conv_std_logic_vector(185882474,28); exponent <= conv_std_logic_vector(1024,11); WHEN "0000000010" => manhi <= conv_std_logic_vector(14214731,24); manlo <= conv_std_logic_vector(148168110,28); exponent <= conv_std_logic_vector(1025,11); WHEN "0000000011" => manhi <= conv_std_logic_vector(4283995,24); manlo <= conv_std_logic_vector(258978054,28); exponent <= conv_std_logic_vector(1027,11); WHEN "0000000100" => manhi <= conv_std_logic_vector(11847938,24); manlo <= conv_std_logic_vector(237451864,28); exponent <= conv_std_logic_vector(1028,11); WHEN "0000000101" => manhi <= conv_std_logic_vector(2675593,24); manlo <= conv_std_logic_vector(158348175,28); exponent <= conv_std_logic_vector(1030,11); WHEN "0000000110" => manhi <= conv_std_logic_vector(9661893,24); manlo <= conv_std_logic_vector(110149775,28); exponent <= conv_std_logic_vector(1031,11); WHEN "0000000111" => manhi <= conv_std_logic_vector(1190021,24); manlo <= conv_std_logic_vector(179232170,28); exponent <= conv_std_logic_vector(1033,11); WHEN "0000001000" => manhi <= conv_std_logic_vector(7642791,24); manlo <= conv_std_logic_vector(222760046,28); exponent <= conv_std_logic_vector(1034,11); WHEN "0000001001" => manhi <= conv_std_logic_vector(16413015,24); manlo <= conv_std_logic_vector(205983618,28); exponent <= conv_std_logic_vector(1035,11); WHEN "0000001010" => manhi <= conv_std_logic_vector(5777884,24); manlo <= conv_std_logic_vector(261424480,28); exponent <= conv_std_logic_vector(1037,11); WHEN "0000001011" => manhi <= conv_std_logic_vector(13878344,24); manlo <= conv_std_logic_vector(149835647,28); exponent <= conv_std_logic_vector(1038,11); WHEN "0000001100" => manhi <= conv_std_logic_vector(4055397,24); manlo <= conv_std_logic_vector(80968858,28); exponent <= conv_std_logic_vector(1040,11); WHEN "0000001101" => manhi <= conv_std_logic_vector(11537241,24); manlo <= conv_std_logic_vector(23775573,28); exponent <= conv_std_logic_vector(1041,11); WHEN "0000001110" => manhi <= conv_std_logic_vector(2464452,24); manlo <= conv_std_logic_vector(146736599,28); exponent <= conv_std_logic_vector(1043,11); WHEN "0000001111" => manhi <= conv_std_logic_vector(9374922,24); manlo <= conv_std_logic_vector(263006855,28); exponent <= conv_std_logic_vector(1044,11); WHEN "0000010000" => manhi <= conv_std_logic_vector(995005,24); manlo <= conv_std_logic_vector(11010080,28); exponent <= conv_std_logic_vector(1046,11); WHEN "0000010001" => manhi <= conv_std_logic_vector(7377736,24); manlo <= conv_std_logic_vector(202286329,28); exponent <= conv_std_logic_vector(1047,11); WHEN "0000010010" => manhi <= conv_std_logic_vector(16052768,24); manlo <= conv_std_logic_vector(152649917,28); exponent <= conv_std_logic_vector(1048,11); WHEN "0000010011" => manhi <= conv_std_logic_vector(5533071,24); manlo <= conv_std_logic_vector(166536930,28); exponent <= conv_std_logic_vector(1050,11); WHEN "0000010100" => manhi <= conv_std_logic_vector(13545608,24); manlo <= conv_std_logic_vector(191424516,28); exponent <= conv_std_logic_vector(1051,11); WHEN "0000010101" => manhi <= conv_std_logic_vector(3829279,24); manlo <= conv_std_logic_vector(228519165,28); exponent <= conv_std_logic_vector(1053,11); WHEN "0000010110" => manhi <= conv_std_logic_vector(11229915,24); manlo <= conv_std_logic_vector(163853824,28); exponent <= conv_std_logic_vector(1054,11); WHEN "0000010111" => manhi <= conv_std_logic_vector(2255603,24); manlo <= conv_std_logic_vector(61996481,28); exponent <= conv_std_logic_vector(1056,11); WHEN "0000011000" => manhi <= conv_std_logic_vector(9091067,24); manlo <= conv_std_logic_vector(88563639,28); exponent <= conv_std_logic_vector(1057,11); WHEN "0000011001" => manhi <= conv_std_logic_vector(802105,24); manlo <= conv_std_logic_vector(34169545,28); exponent <= conv_std_logic_vector(1059,11); WHEN "0000011010" => manhi <= conv_std_logic_vector(7115558,24); manlo <= conv_std_logic_vector(157969244,28); exponent <= conv_std_logic_vector(1060,11); WHEN "0000011011" => manhi <= conv_std_logic_vector(15696431,24); manlo <= conv_std_logic_vector(133591837,28); exponent <= conv_std_logic_vector(1061,11); WHEN "0000011100" => manhi <= conv_std_logic_vector(5290915,24); manlo <= conv_std_logic_vector(127285146,28); exponent <= conv_std_logic_vector(1063,11); WHEN "0000011101" => manhi <= conv_std_logic_vector(13216484,24); manlo <= conv_std_logic_vector(103923798,28); exponent <= conv_std_logic_vector(1064,11); WHEN "0000011110" => manhi <= conv_std_logic_vector(3605616,24); manlo <= conv_std_logic_vector(183249133,28); exponent <= conv_std_logic_vector(1066,11); WHEN "0000011111" => manhi <= conv_std_logic_vector(10925925,24); manlo <= conv_std_logic_vector(227336045,28); exponent <= conv_std_logic_vector(1067,11); WHEN "0000100000" => manhi <= conv_std_logic_vector(2049020,24); manlo <= conv_std_logic_vector(206267948,28); exponent <= conv_std_logic_vector(1069,11); WHEN "0000100001" => manhi <= conv_std_logic_vector(8810292,24); manlo <= conv_std_logic_vector(175265666,28); exponent <= conv_std_logic_vector(1070,11); WHEN "0000100010" => manhi <= conv_std_logic_vector(611298,24); manlo <= conv_std_logic_vector(255467255,28); exponent <= conv_std_logic_vector(1072,11); WHEN "0000100011" => manhi <= conv_std_logic_vector(6856226,24); manlo <= conv_std_logic_vector(29134171,28); exponent <= conv_std_logic_vector(1073,11); WHEN "0000100100" => manhi <= conv_std_logic_vector(15343962,24); manlo <= conv_std_logic_vector(30543222,28); exponent <= conv_std_logic_vector(1074,11); WHEN "0000100101" => manhi <= conv_std_logic_vector(5051387,24); manlo <= conv_std_logic_vector(186253338,28); exponent <= conv_std_logic_vector(1076,11); WHEN "0000100110" => manhi <= conv_std_logic_vector(12890932,24); manlo <= conv_std_logic_vector(102222951,28); exponent <= conv_std_logic_vector(1077,11); WHEN "0000100111" => manhi <= conv_std_logic_vector(3384381,24); manlo <= conv_std_logic_vector(42116377,28); exponent <= conv_std_logic_vector(1079,11); WHEN "0000101000" => manhi <= conv_std_logic_vector(10625235,24); manlo <= conv_std_logic_vector(158954218,28); exponent <= conv_std_logic_vector(1080,11); WHEN "0000101001" => manhi <= conv_std_logic_vector(1844680,24); manlo <= conv_std_logic_vector(148858978,28); exponent <= conv_std_logic_vector(1082,11); WHEN "0000101010" => manhi <= conv_std_logic_vector(8532565,24); manlo <= conv_std_logic_vector(136319321,28); exponent <= conv_std_logic_vector(1083,11); WHEN "0000101011" => manhi <= conv_std_logic_vector(422563,24); manlo <= conv_std_logic_vector(211728497,28); exponent <= conv_std_logic_vector(1085,11); WHEN "0000101100" => manhi <= conv_std_logic_vector(6599708,24); manlo <= conv_std_logic_vector(114522162,28); exponent <= conv_std_logic_vector(1086,11); WHEN "0000101101" => manhi <= conv_std_logic_vector(14995318,24); manlo <= conv_std_logic_vector(117328318,28); exponent <= conv_std_logic_vector(1087,11); WHEN "0000101110" => manhi <= conv_std_logic_vector(4814459,24); manlo <= conv_std_logic_vector(201622499,28); exponent <= conv_std_logic_vector(1089,11); WHEN "0000101111" => manhi <= conv_std_logic_vector(12568913,24); manlo <= conv_std_logic_vector(246987638,28); exponent <= conv_std_logic_vector(1090,11); WHEN "0000110000" => manhi <= conv_std_logic_vector(3165546,24); manlo <= conv_std_logic_vector(248128843,28); exponent <= conv_std_logic_vector(1092,11); WHEN "0000110001" => manhi <= conv_std_logic_vector(10327809,24); manlo <= conv_std_logic_vector(8929872,28); exponent <= conv_std_logic_vector(1093,11); WHEN "0000110010" => manhi <= conv_std_logic_vector(1642558,24); manlo <= conv_std_logic_vector(67636037,28); exponent <= conv_std_logic_vector(1095,11); WHEN "0000110011" => manhi <= conv_std_logic_vector(8257852,24); manlo <= conv_std_logic_vector(219235425,28); exponent <= conv_std_logic_vector(1096,11); WHEN "0000110100" => manhi <= conv_std_logic_vector(235877,24); manlo <= conv_std_logic_vector(42862412,28); exponent <= conv_std_logic_vector(1098,11); WHEN "0000110101" => manhi <= conv_std_logic_vector(6345974,24); manlo <= conv_std_logic_vector(265996080,28); exponent <= conv_std_logic_vector(1099,11); WHEN "0000110110" => manhi <= conv_std_logic_vector(14650458,24); manlo <= conv_std_logic_vector(253213243,28); exponent <= conv_std_logic_vector(1100,11); WHEN "0000110111" => manhi <= conv_std_logic_vector(4580103,24); manlo <= conv_std_logic_vector(114693785,28); exponent <= conv_std_logic_vector(1102,11); WHEN "0000111000" => manhi <= conv_std_logic_vector(12250390,24); manlo <= conv_std_logic_vector(174984615,28); exponent <= conv_std_logic_vector(1103,11); WHEN "0000111001" => manhi <= conv_std_logic_vector(2949087,24); manlo <= conv_std_logic_vector(247325089,28); exponent <= conv_std_logic_vector(1105,11); WHEN "0000111010" => manhi <= conv_std_logic_vector(10033610,24); manlo <= conv_std_logic_vector(200264553,28); exponent <= conv_std_logic_vector(1106,11); WHEN "0000111011" => manhi <= conv_std_logic_vector(1442629,24); manlo <= conv_std_logic_vector(211375075,28); exponent <= conv_std_logic_vector(1108,11); WHEN "0000111100" => manhi <= conv_std_logic_vector(7986121,24); manlo <= conv_std_logic_vector(231029862,28); exponent <= conv_std_logic_vector(1109,11); WHEN "0000111101" => manhi <= conv_std_logic_vector(51216,24); manlo <= conv_std_logic_vector(222707863,28); exponent <= conv_std_logic_vector(1111,11); WHEN "0000111110" => manhi <= conv_std_logic_vector(6094995,24); manlo <= conv_std_logic_vector(155999272,28); exponent <= conv_std_logic_vector(1112,11); WHEN "0000111111" => manhi <= conv_std_logic_vector(14309342,24); manlo <= conv_std_logic_vector(150013864,28); exponent <= conv_std_logic_vector(1113,11); WHEN "0001000000" => manhi <= conv_std_logic_vector(4348290,24); manlo <= conv_std_logic_vector(217421773,28); exponent <= conv_std_logic_vector(1115,11); WHEN "0001000001" => manhi <= conv_std_logic_vector(11935324,24); manlo <= conv_std_logic_vector(171597361,28); exponent <= conv_std_logic_vector(1116,11); WHEN "0001000010" => manhi <= conv_std_logic_vector(2734978,24); manlo <= conv_std_logic_vector(98553735,28); exponent <= conv_std_logic_vector(1118,11); WHEN "0001000011" => manhi <= conv_std_logic_vector(9742605,24); manlo <= conv_std_logic_vector(185429986,28); exponent <= conv_std_logic_vector(1119,11); WHEN "0001000100" => manhi <= conv_std_logic_vector(1244871,24); manlo <= conv_std_logic_vector(93685501,28); exponent <= conv_std_logic_vector(1121,11); WHEN "0001000101" => manhi <= conv_std_logic_vector(7717340,24); manlo <= conv_std_logic_vector(74048432,28); exponent <= conv_std_logic_vector(1122,11); WHEN "0001000110" => manhi <= conv_std_logic_vector(16514337,24); manlo <= conv_std_logic_vector(163855108,28); exponent <= conv_std_logic_vector(1123,11); WHEN "0001000111" => manhi <= conv_std_logic_vector(5846740,24); manlo <= conv_std_logic_vector(81895750,28); exponent <= conv_std_logic_vector(1125,11); WHEN "0001001000" => manhi <= conv_std_logic_vector(13971928,24); manlo <= conv_std_logic_vector(176088988,28); exponent <= conv_std_logic_vector(1126,11); WHEN "0001001001" => manhi <= conv_std_logic_vector(4118994,24); manlo <= conv_std_logic_vector(77780251,28); exponent <= conv_std_logic_vector(1128,11); WHEN "0001001010" => manhi <= conv_std_logic_vector(11623678,24); manlo <= conv_std_logic_vector(95871356,28); exponent <= conv_std_logic_vector(1129,11); WHEN "0001001011" => manhi <= conv_std_logic_vector(2523192,24); manlo <= conv_std_logic_vector(204213760,28); exponent <= conv_std_logic_vector(1131,11); WHEN "0001001100" => manhi <= conv_std_logic_vector(9454759,24); manlo <= conv_std_logic_vector(55860552,28); exponent <= conv_std_logic_vector(1132,11); WHEN "0001001101" => manhi <= conv_std_logic_vector(1049259,24); manlo <= conv_std_logic_vector(102861624,28); exponent <= conv_std_logic_vector(1134,11); WHEN "0001001110" => manhi <= conv_std_logic_vector(7451476,24); manlo <= conv_std_logic_vector(13367584,28); exponent <= conv_std_logic_vector(1135,11); WHEN "0001001111" => manhi <= conv_std_logic_vector(16152990,24); manlo <= conv_std_logic_vector(178012490,28); exponent <= conv_std_logic_vector(1136,11); WHEN "0001010000" => manhi <= conv_std_logic_vector(5601179,24); manlo <= conv_std_logic_vector(159708139,28); exponent <= conv_std_logic_vector(1138,11); WHEN "0001010001" => manhi <= conv_std_logic_vector(13638177,24); manlo <= conv_std_logic_vector(12864164,28); exponent <= conv_std_logic_vector(1139,11); WHEN "0001010010" => manhi <= conv_std_logic_vector(3892186,24); manlo <= conv_std_logic_vector(149492240,28); exponent <= conv_std_logic_vector(1141,11); WHEN "0001010011" => manhi <= conv_std_logic_vector(11315414,24); manlo <= conv_std_logic_vector(184620728,28); exponent <= conv_std_logic_vector(1142,11); WHEN "0001010100" => manhi <= conv_std_logic_vector(2313705,24); manlo <= conv_std_logic_vector(235697385,28); exponent <= conv_std_logic_vector(1144,11); WHEN "0001010101" => manhi <= conv_std_logic_vector(9170037,24); manlo <= conv_std_logic_vector(3974263,28); exponent <= conv_std_logic_vector(1145,11); WHEN "0001010110" => manhi <= conv_std_logic_vector(855770,24); manlo <= conv_std_logic_vector(158952336,28); exponent <= conv_std_logic_vector(1147,11); WHEN "0001010111" => manhi <= conv_std_logic_vector(7188497,24); manlo <= conv_std_logic_vector(138900038,28); exponent <= conv_std_logic_vector(1148,11); WHEN "0001011000" => manhi <= conv_std_logic_vector(15795565,24); manlo <= conv_std_logic_vector(209449517,28); exponent <= conv_std_logic_vector(1149,11); WHEN "0001011001" => manhi <= conv_std_logic_vector(5358284,24); manlo <= conv_std_logic_vector(54736896,28); exponent <= conv_std_logic_vector(1151,11); WHEN "0001011010" => manhi <= conv_std_logic_vector(13308047,24); manlo <= conv_std_logic_vector(264159588,28); exponent <= conv_std_logic_vector(1152,11); WHEN "0001011011" => manhi <= conv_std_logic_vector(3667840,24); manlo <= conv_std_logic_vector(160544132,28); exponent <= conv_std_logic_vector(1154,11); WHEN "0001011100" => manhi <= conv_std_logic_vector(11010496,24); manlo <= conv_std_logic_vector(245935181,28); exponent <= conv_std_logic_vector(1155,11); WHEN "0001011101" => manhi <= conv_std_logic_vector(2106492,24); manlo <= conv_std_logic_vector(206325441,28); exponent <= conv_std_logic_vector(1157,11); WHEN "0001011110" => manhi <= conv_std_logic_vector(8888405,24); manlo <= conv_std_logic_vector(53641237,28); exponent <= conv_std_logic_vector(1158,11); WHEN "0001011111" => manhi <= conv_std_logic_vector(664381,24); manlo <= conv_std_logic_vector(249887163,28); exponent <= conv_std_logic_vector(1160,11); WHEN "0001100000" => manhi <= conv_std_logic_vector(6928373,24); manlo <= conv_std_logic_vector(95946938,28); exponent <= conv_std_logic_vector(1161,11); WHEN "0001100001" => manhi <= conv_std_logic_vector(15442020,24); manlo <= conv_std_logic_vector(105121290,28); exponent <= conv_std_logic_vector(1162,11); WHEN "0001100010" => manhi <= conv_std_logic_vector(5118025,24); manlo <= conv_std_logic_vector(54367076,28); exponent <= conv_std_logic_vector(1164,11); WHEN "0001100011" => manhi <= conv_std_logic_vector(12981502,24); manlo <= conv_std_logic_vector(39000129,28); exponent <= conv_std_logic_vector(1165,11); WHEN "0001100100" => manhi <= conv_std_logic_vector(3445929,24); manlo <= conv_std_logic_vector(186063861,28); exponent <= conv_std_logic_vector(1167,11); WHEN "0001100101" => manhi <= conv_std_logic_vector(10708888,24); manlo <= conv_std_logic_vector(194877084,28); exponent <= conv_std_logic_vector(1168,11); WHEN "0001100110" => manhi <= conv_std_logic_vector(1901528,24); manlo <= conv_std_logic_vector(202114223,28); exponent <= conv_std_logic_vector(1170,11); WHEN "0001100111" => manhi <= conv_std_logic_vector(8609830,24); manlo <= conv_std_logic_vector(59099508,28); exponent <= conv_std_logic_vector(1171,11); WHEN "0001101000" => manhi <= conv_std_logic_vector(475070,24); manlo <= conv_std_logic_vector(162304029,28); exponent <= conv_std_logic_vector(1173,11); WHEN "0001101001" => manhi <= conv_std_logic_vector(6671072,24); manlo <= conv_std_logic_vector(157938310,28); exponent <= conv_std_logic_vector(1174,11); WHEN "0001101010" => manhi <= conv_std_logic_vector(15092312,24); manlo <= conv_std_logic_vector(104450792,28); exponent <= conv_std_logic_vector(1175,11); WHEN "0001101011" => manhi <= conv_std_logic_vector(4880373,24); manlo <= conv_std_logic_vector(261837049,28); exponent <= conv_std_logic_vector(1177,11); WHEN "0001101100" => manhi <= conv_std_logic_vector(12658500,24); manlo <= conv_std_logic_vector(171583716,28); exponent <= conv_std_logic_vector(1178,11); WHEN "0001101101" => manhi <= conv_std_logic_vector(3226427,24); manlo <= conv_std_logic_vector(110595717,28); exponent <= conv_std_logic_vector(1180,11); WHEN "0001101110" => manhi <= conv_std_logic_vector(10410554,24); manlo <= conv_std_logic_vector(52320382,28); exponent <= conv_std_logic_vector(1181,11); WHEN "0001101111" => manhi <= conv_std_logic_vector(1698789,24); manlo <= conv_std_logic_vector(112550995,28); exponent <= conv_std_logic_vector(1183,11); WHEN "0001110000" => manhi <= conv_std_logic_vector(8334278,24); manlo <= conv_std_logic_vector(240753534,28); exponent <= conv_std_logic_vector(1184,11); WHEN "0001110001" => manhi <= conv_std_logic_vector(287814,24); manlo <= conv_std_logic_vector(17691391,28); exponent <= conv_std_logic_vector(1186,11); WHEN "0001110010" => manhi <= conv_std_logic_vector(6416564,24); manlo <= conv_std_logic_vector(151700710,28); exponent <= conv_std_logic_vector(1187,11); WHEN "0001110011" => manhi <= conv_std_logic_vector(14746400,24); manlo <= conv_std_logic_vector(32676275,28); exponent <= conv_std_logic_vector(1188,11); WHEN "0001110100" => manhi <= conv_std_logic_vector(4645302,24); manlo <= conv_std_logic_vector(58452725,28); exponent <= conv_std_logic_vector(1190,11); WHEN "0001110101" => manhi <= conv_std_logic_vector(12339004,24); manlo <= conv_std_logic_vector(267247876,28); exponent <= conv_std_logic_vector(1191,11); WHEN "0001110110" => manhi <= conv_std_logic_vector(3009307,24); manlo <= conv_std_logic_vector(164126253,28); exponent <= conv_std_logic_vector(1193,11); WHEN "0001110111" => manhi <= conv_std_logic_vector(10115457,24); manlo <= conv_std_logic_vector(212237584,28); exponent <= conv_std_logic_vector(1194,11); WHEN "0001111000" => manhi <= conv_std_logic_vector(1498250,24); manlo <= conv_std_logic_vector(166684427,28); exponent <= conv_std_logic_vector(1196,11); WHEN "0001111001" => manhi <= conv_std_logic_vector(8061718,24); manlo <= conv_std_logic_vector(110371593,28); exponent <= conv_std_logic_vector(1197,11); WHEN "0001111010" => manhi <= conv_std_logic_vector(102590,24); manlo <= conv_std_logic_vector(3231911,28); exponent <= conv_std_logic_vector(1199,11); WHEN "0001111011" => manhi <= conv_std_logic_vector(6164818,24); manlo <= conv_std_logic_vector(261783833,28); exponent <= conv_std_logic_vector(1200,11); WHEN "0001111100" => manhi <= conv_std_logic_vector(14404242,24); manlo <= conv_std_logic_vector(104825991,28); exponent <= conv_std_logic_vector(1201,11); WHEN "0001111101" => manhi <= conv_std_logic_vector(4412781,24); manlo <= conv_std_logic_vector(250166254,28); exponent <= conv_std_logic_vector(1203,11); WHEN "0001111110" => manhi <= conv_std_logic_vector(12022977,24); manlo <= conv_std_logic_vector(43417082,28); exponent <= conv_std_logic_vector(1204,11); WHEN "0001111111" => manhi <= conv_std_logic_vector(2794544,24); manlo <= conv_std_logic_vector(115942082,28); exponent <= conv_std_logic_vector(1206,11); WHEN "0010000000" => manhi <= conv_std_logic_vector(9823564,24); manlo <= conv_std_logic_vector(98386456,28); exponent <= conv_std_logic_vector(1207,11); WHEN "0010000001" => manhi <= conv_std_logic_vector(1299888,24); manlo <= conv_std_logic_vector(127046227,28); exponent <= conv_std_logic_vector(1209,11); WHEN "0010000010" => manhi <= conv_std_logic_vector(7792116,24); manlo <= conv_std_logic_vector(80649262,28); exponent <= conv_std_logic_vector(1210,11); WHEN "0010000011" => manhi <= conv_std_logic_vector(16615968,24); manlo <= conv_std_logic_vector(205307910,28); exponent <= conv_std_logic_vector(1211,11); WHEN "0010000100" => manhi <= conv_std_logic_vector(5915805,24); manlo <= conv_std_logic_vector(224185017,28); exponent <= conv_std_logic_vector(1213,11); WHEN "0010000101" => manhi <= conv_std_logic_vector(14065798,24); manlo <= conv_std_logic_vector(119094636,28); exponent <= conv_std_logic_vector(1214,11); WHEN "0010000110" => manhi <= conv_std_logic_vector(4182785,24); manlo <= conv_std_logic_vector(113890892,28); exponent <= conv_std_logic_vector(1216,11); WHEN "0010000111" => manhi <= conv_std_logic_vector(11710379,24); manlo <= conv_std_logic_vector(133692518,28); exponent <= conv_std_logic_vector(1217,11); WHEN "0010001000" => manhi <= conv_std_logic_vector(2582112,24); manlo <= conv_std_logic_vector(79109485,28); exponent <= conv_std_logic_vector(1219,11); WHEN "0010001001" => manhi <= conv_std_logic_vector(9534839,24); manlo <= conv_std_logic_vector(42234535,28); exponent <= conv_std_logic_vector(1220,11); WHEN "0010001010" => manhi <= conv_std_logic_vector(1103679,24); manlo <= conv_std_logic_vector(94193887,28); exponent <= conv_std_logic_vector(1222,11); WHEN "0010001011" => manhi <= conv_std_logic_vector(7525440,24); manlo <= conv_std_logic_vector(121994268,28); exponent <= conv_std_logic_vector(1223,11); WHEN "0010001100" => manhi <= conv_std_logic_vector(16253518,24); manlo <= conv_std_logic_vector(191052573,28); exponent <= conv_std_logic_vector(1224,11); WHEN "0010001101" => manhi <= conv_std_logic_vector(5669495,24); manlo <= conv_std_logic_vector(130696997,28); exponent <= conv_std_logic_vector(1226,11); WHEN "0010001110" => manhi <= conv_std_logic_vector(13731027,24); manlo <= conv_std_logic_vector(260846837,28); exponent <= conv_std_logic_vector(1227,11); WHEN "0010001111" => manhi <= conv_std_logic_vector(3955285,24); manlo <= conv_std_logic_vector(80970159,28); exponent <= conv_std_logic_vector(1229,11); WHEN "0010010000" => manhi <= conv_std_logic_vector(11401174,24); manlo <= conv_std_logic_vector(207600506,28); exponent <= conv_std_logic_vector(1230,11); WHEN "0010010001" => manhi <= conv_std_logic_vector(2371985,24); manlo <= conv_std_logic_vector(241221170,28); exponent <= conv_std_logic_vector(1232,11); WHEN "0010010010" => manhi <= conv_std_logic_vector(9249247,24); manlo <= conv_std_logic_vector(208105818,28); exponent <= conv_std_logic_vector(1233,11); WHEN "0010010011" => manhi <= conv_std_logic_vector(909599,24); manlo <= conv_std_logic_vector(237519888,28); exponent <= conv_std_logic_vector(1235,11); WHEN "0010010100" => manhi <= conv_std_logic_vector(7261659,24); manlo <= conv_std_logic_vector(29935335,28); exponent <= conv_std_logic_vector(1236,11); WHEN "0010010101" => manhi <= conv_std_logic_vector(15895002,24); manlo <= conv_std_logic_vector(186862656,28); exponent <= conv_std_logic_vector(1237,11); WHEN "0010010110" => manhi <= conv_std_logic_vector(5425858,24); manlo <= conv_std_logic_vector(159524243,28); exponent <= conv_std_logic_vector(1239,11); WHEN "0010010111" => manhi <= conv_std_logic_vector(13399891,24); manlo <= conv_std_logic_vector(27586577,28); exponent <= conv_std_logic_vector(1240,11); WHEN "0010011000" => manhi <= conv_std_logic_vector(3730254,24); manlo <= conv_std_logic_vector(125689310,28); exponent <= conv_std_logic_vector(1242,11); WHEN "0010011001" => manhi <= conv_std_logic_vector(11095326,24); manlo <= conv_std_logic_vector(43144000,28); exponent <= conv_std_logic_vector(1243,11); WHEN "0010011010" => manhi <= conv_std_logic_vector(2164140,24); manlo <= conv_std_logic_vector(58280992,28); exponent <= conv_std_logic_vector(1245,11); WHEN "0010011011" => manhi <= conv_std_logic_vector(8966756,24); manlo <= conv_std_logic_vector(55210422,28); exponent <= conv_std_logic_vector(1246,11); WHEN "0010011100" => manhi <= conv_std_logic_vector(717626,24); manlo <= conv_std_logic_vector(257633658,28); exponent <= conv_std_logic_vector(1248,11); WHEN "0010011101" => manhi <= conv_std_logic_vector(7000740,24); manlo <= conv_std_logic_vector(229413090,28); exponent <= conv_std_logic_vector(1249,11); WHEN "0010011110" => manhi <= conv_std_logic_vector(15540378,24); manlo <= conv_std_logic_vector(4808337,28); exponent <= conv_std_logic_vector(1250,11); WHEN "0010011111" => manhi <= conv_std_logic_vector(5184866,24); manlo <= conv_std_logic_vector(37474138,28); exponent <= conv_std_logic_vector(1252,11); WHEN "0010100000" => manhi <= conv_std_logic_vector(13072348,24); manlo <= conv_std_logic_vector(106730632,28); exponent <= conv_std_logic_vector(1253,11); WHEN "0010100001" => manhi <= conv_std_logic_vector(3507666,24); manlo <= conv_std_logic_vector(32844500,28); exponent <= conv_std_logic_vector(1255,11); WHEN "0010100010" => manhi <= conv_std_logic_vector(10792797,24); manlo <= conv_std_logic_vector(62496090,28); exponent <= conv_std_logic_vector(1256,11); WHEN "0010100011" => manhi <= conv_std_logic_vector(1958550,24); manlo <= conv_std_logic_vector(132952012,28); exponent <= conv_std_logic_vector(1258,11); WHEN "0010100100" => manhi <= conv_std_logic_vector(8687330,24); manlo <= conv_std_logic_vector(215605290,28); exponent <= conv_std_logic_vector(1259,11); WHEN "0010100101" => manhi <= conv_std_logic_vector(527737,24); manlo <= conv_std_logic_vector(190928911,28); exponent <= conv_std_logic_vector(1261,11); WHEN "0010100110" => manhi <= conv_std_logic_vector(6742654,24); manlo <= conv_std_logic_vector(163162889,28); exponent <= conv_std_logic_vector(1262,11); WHEN "0010100111" => manhi <= conv_std_logic_vector(15189602,24); manlo <= conv_std_logic_vector(118241780,28); exponent <= conv_std_logic_vector(1263,11); WHEN "0010101000" => manhi <= conv_std_logic_vector(4946489,24); manlo <= conv_std_logic_vector(112771062,28); exponent <= conv_std_logic_vector(1265,11); WHEN "0010101001" => manhi <= conv_std_logic_vector(12748360,24); manlo <= conv_std_logic_vector(226864003,28); exponent <= conv_std_logic_vector(1266,11); WHEN "0010101010" => manhi <= conv_std_logic_vector(3287493,24); manlo <= conv_std_logic_vector(202192272,28); exponent <= conv_std_logic_vector(1268,11); WHEN "0010101011" => manhi <= conv_std_logic_vector(10493551,24); manlo <= conv_std_logic_vector(257093553,28); exponent <= conv_std_logic_vector(1269,11); WHEN "0010101100" => manhi <= conv_std_logic_vector(1755192,24); manlo <= conv_std_logic_vector(66281405,28); exponent <= conv_std_logic_vector(1271,11); WHEN "0010101101" => manhi <= conv_std_logic_vector(8410938,24); manlo <= conv_std_logic_vector(77199396,28); exponent <= conv_std_logic_vector(1272,11); WHEN "0010101110" => manhi <= conv_std_logic_vector(339909,24); manlo <= conv_std_logic_vector(140417186,28); exponent <= conv_std_logic_vector(1274,11); WHEN "0010101111" => manhi <= conv_std_logic_vector(6487369,24); manlo <= conv_std_logic_vector(169769464,28); exponent <= conv_std_logic_vector(1275,11); WHEN "0010110000" => manhi <= conv_std_logic_vector(14842634,24); manlo <= conv_std_logic_vector(49834035,28); exponent <= conv_std_logic_vector(1276,11); WHEN "0010110001" => manhi <= conv_std_logic_vector(4710700,24); manlo <= conv_std_logic_vector(11961455,28); exponent <= conv_std_logic_vector(1278,11); WHEN "0010110010" => manhi <= conv_std_logic_vector(12427889,24); manlo <= conv_std_logic_vector(230234502,28); exponent <= conv_std_logic_vector(1279,11); WHEN "0010110011" => manhi <= conv_std_logic_vector(3069711,24); manlo <= conv_std_logic_vector(36989233,28); exponent <= conv_std_logic_vector(1281,11); WHEN "0010110100" => manhi <= conv_std_logic_vector(10197554,24); manlo <= conv_std_logic_vector(186484869,28); exponent <= conv_std_logic_vector(1282,11); WHEN "0010110101" => manhi <= conv_std_logic_vector(1554041,24); manlo <= conv_std_logic_vector(67530342,28); exponent <= conv_std_logic_vector(1284,11); WHEN "0010110110" => manhi <= conv_std_logic_vector(8137545,24); manlo <= conv_std_logic_vector(198608842,28); exponent <= conv_std_logic_vector(1285,11); WHEN "0010110111" => manhi <= conv_std_logic_vector(154120,24); manlo <= conv_std_logic_vector(6569319,28); exponent <= conv_std_logic_vector(1287,11); WHEN "0010111000" => manhi <= conv_std_logic_vector(6234855,24); manlo <= conv_std_logic_vector(140506894,28); exponent <= conv_std_logic_vector(1288,11); WHEN "0010111001" => manhi <= conv_std_logic_vector(14499431,24); manlo <= conv_std_logic_vector(249287529,28); exponent <= conv_std_logic_vector(1289,11); WHEN "0010111010" => manhi <= conv_std_logic_vector(4477469,24); manlo <= conv_std_logic_vector(249618841,28); exponent <= conv_std_logic_vector(1291,11); WHEN "0010111011" => manhi <= conv_std_logic_vector(12110897,24); manlo <= conv_std_logic_vector(71519058,28); exponent <= conv_std_logic_vector(1292,11); WHEN "0010111100" => manhi <= conv_std_logic_vector(2854292,24); manlo <= conv_std_logic_vector(90637320,28); exponent <= conv_std_logic_vector(1294,11); WHEN "0010111101" => manhi <= conv_std_logic_vector(9904770,24); manlo <= conv_std_logic_vector(50932558,28); exponent <= conv_std_logic_vector(1295,11); WHEN "0010111110" => manhi <= conv_std_logic_vector(1355073,24); manlo <= conv_std_logic_vector(148093260,28); exponent <= conv_std_logic_vector(1297,11); WHEN "0010111111" => manhi <= conv_std_logic_vector(7867120,24); manlo <= conv_std_logic_vector(160620741,28); exponent <= conv_std_logic_vector(1298,11); WHEN "0011000000" => manhi <= conv_std_logic_vector(16717910,24); manlo <= conv_std_logic_vector(46942270,28); exponent <= conv_std_logic_vector(1299,11); WHEN "0011000001" => manhi <= conv_std_logic_vector(5985082,24); manlo <= conv_std_logic_vector(55237426,28); exponent <= conv_std_logic_vector(1301,11); WHEN "0011000010" => manhi <= conv_std_logic_vector(14159954,24); manlo <= conv_std_logic_vector(212966668,28); exponent <= conv_std_logic_vector(1302,11); WHEN "0011000011" => manhi <= conv_std_logic_vector(4246771,24); manlo <= conv_std_logic_vector(79962334,28); exponent <= conv_std_logic_vector(1304,11); WHEN "0011000100" => manhi <= conv_std_logic_vector(11797345,24); manlo <= conv_std_logic_vector(85038862,28); exponent <= conv_std_logic_vector(1305,11); WHEN "0011000101" => manhi <= conv_std_logic_vector(2641211,24); manlo <= conv_std_logic_vector(186806322,28); exponent <= conv_std_logic_vector(1307,11); WHEN "0011000110" => manhi <= conv_std_logic_vector(9615163,24); manlo <= conv_std_logic_vector(153415152,28); exponent <= conv_std_logic_vector(1308,11); WHEN "0011000111" => manhi <= conv_std_logic_vector(1158265,24); manlo <= conv_std_logic_vector(120731907,28); exponent <= conv_std_logic_vector(1310,11); WHEN "0011001000" => manhi <= conv_std_logic_vector(7599630,24); manlo <= conv_std_logic_vector(175764921,28); exponent <= conv_std_logic_vector(1311,11); WHEN "0011001001" => manhi <= conv_std_logic_vector(16354353,24); manlo <= conv_std_logic_vector(174054693,28); exponent <= conv_std_logic_vector(1312,11); WHEN "0011001010" => manhi <= conv_std_logic_vector(5738019,24); manlo <= conv_std_logic_vector(249885394,28); exponent <= conv_std_logic_vector(1314,11); WHEN "0011001011" => manhi <= conv_std_logic_vector(13824162,24); manlo <= conv_std_logic_vector(93203713,28); exponent <= conv_std_logic_vector(1315,11); WHEN "0011001100" => manhi <= conv_std_logic_vector(4018576,24); manlo <= conv_std_logic_vector(180323091,28); exponent <= conv_std_logic_vector(1317,11); WHEN "0011001101" => manhi <= conv_std_logic_vector(11487196,24); manlo <= conv_std_logic_vector(178245939,28); exponent <= conv_std_logic_vector(1318,11); WHEN "0011001110" => manhi <= conv_std_logic_vector(2430443,24); manlo <= conv_std_logic_vector(223919964,28); exponent <= conv_std_logic_vector(1320,11); WHEN "0011001111" => manhi <= conv_std_logic_vector(9328700,24); manlo <= conv_std_logic_vector(93205956,28); exponent <= conv_std_logic_vector(1321,11); WHEN "0011010000" => manhi <= conv_std_logic_vector(963593,24); manlo <= conv_std_logic_vector(135688620,28); exponent <= conv_std_logic_vector(1323,11); WHEN "0011010001" => manhi <= conv_std_logic_vector(7335044,24); manlo <= conv_std_logic_vector(13542358,28); exponent <= conv_std_logic_vector(1324,11); WHEN "0011010010" => manhi <= conv_std_logic_vector(15994743,24); manlo <= conv_std_logic_vector(45394459,28); exponent <= conv_std_logic_vector(1325,11); WHEN "0011010011" => manhi <= conv_std_logic_vector(5493639,24); manlo <= conv_std_logic_vector(73308838,28); exponent <= conv_std_logic_vector(1327,11); WHEN "0011010100" => manhi <= conv_std_logic_vector(13492014,24); manlo <= conv_std_logic_vector(160135181,28); exponent <= conv_std_logic_vector(1328,11); WHEN "0011010101" => manhi <= conv_std_logic_vector(3792858,24); manlo <= conv_std_logic_vector(234346738,28); exponent <= conv_std_logic_vector(1330,11); WHEN "0011010110" => manhi <= conv_std_logic_vector(11180414,24); manlo <= conv_std_logic_vector(98964646,28); exponent <= conv_std_logic_vector(1331,11); WHEN "0011010111" => manhi <= conv_std_logic_vector(2221963,24); manlo <= conv_std_logic_vector(174344531,28); exponent <= conv_std_logic_vector(1333,11); WHEN "0011011000" => manhi <= conv_std_logic_vector(9045346,24); manlo <= conv_std_logic_vector(106947534,28); exponent <= conv_std_logic_vector(1334,11); WHEN "0011011001" => manhi <= conv_std_logic_vector(771034,24); manlo <= conv_std_logic_vector(143065990,28); exponent <= conv_std_logic_vector(1336,11); WHEN "0011011010" => manhi <= conv_std_logic_vector(7073329,24); manlo <= conv_std_logic_vector(73148434,28); exponent <= conv_std_logic_vector(1337,11); WHEN "0011011011" => manhi <= conv_std_logic_vector(15639035,24); manlo <= conv_std_logic_vector(243346703,28); exponent <= conv_std_logic_vector(1338,11); WHEN "0011011100" => manhi <= conv_std_logic_vector(5251911,24); manlo <= conv_std_logic_vector(33842377,28); exponent <= conv_std_logic_vector(1340,11); WHEN "0011011101" => manhi <= conv_std_logic_vector(13163471,24); manlo <= conv_std_logic_vector(263552292,28); exponent <= conv_std_logic_vector(1341,11); WHEN "0011011110" => manhi <= conv_std_logic_vector(3569591,24); manlo <= conv_std_logic_vector(4866264,28); exponent <= conv_std_logic_vector(1343,11); WHEN "0011011111" => manhi <= conv_std_logic_vector(10876961,24); manlo <= conv_std_logic_vector(239517036,28); exponent <= conv_std_logic_vector(1344,11); WHEN "0011100000" => manhi <= conv_std_logic_vector(2015746,24); manlo <= conv_std_logic_vector(83586287,28); exponent <= conv_std_logic_vector(1346,11); WHEN "0011100001" => manhi <= conv_std_logic_vector(8765067,24); manlo <= conv_std_logic_vector(262254542,28); exponent <= conv_std_logic_vector(1347,11); WHEN "0011100010" => manhi <= conv_std_logic_vector(580565,24); manlo <= conv_std_logic_vector(160521039,28); exponent <= conv_std_logic_vector(1349,11); WHEN "0011100011" => manhi <= conv_std_logic_vector(6814455,24); manlo <= conv_std_logic_vector(40288155,28); exponent <= conv_std_logic_vector(1350,11); WHEN "0011100100" => manhi <= conv_std_logic_vector(15287189,24); manlo <= conv_std_logic_vector(132910147,28); exponent <= conv_std_logic_vector(1351,11); WHEN "0011100101" => manhi <= conv_std_logic_vector(5012806,24); manlo <= conv_std_logic_vector(187753904,28); exponent <= conv_std_logic_vector(1353,11); WHEN "0011100110" => manhi <= conv_std_logic_vector(12838495,24); manlo <= conv_std_logic_vector(100071648,28); exponent <= conv_std_logic_vector(1354,11); WHEN "0011100111" => manhi <= conv_std_logic_vector(3348746,24); manlo <= conv_std_logic_vector(138348888,28); exponent <= conv_std_logic_vector(1356,11); WHEN "0011101000" => manhi <= conv_std_logic_vector(10576803,24); manlo <= conv_std_logic_vector(24941937,28); exponent <= conv_std_logic_vector(1357,11); WHEN "0011101001" => manhi <= conv_std_logic_vector(1811767,24); manlo <= conv_std_logic_vector(69497619,28); exponent <= conv_std_logic_vector(1359,11); WHEN "0011101010" => manhi <= conv_std_logic_vector(8487831,24); manlo <= conv_std_logic_vector(188199296,28); exponent <= conv_std_logic_vector(1360,11); WHEN "0011101011" => manhi <= conv_std_logic_vector(392164,24); manlo <= conv_std_logic_vector(4096525,28); exponent <= conv_std_logic_vector(1362,11); WHEN "0011101100" => manhi <= conv_std_logic_vector(6558390,24); manlo <= conv_std_logic_vector(228356857,28); exponent <= conv_std_logic_vector(1363,11); WHEN "0011101101" => manhi <= conv_std_logic_vector(14939162,24); manlo <= conv_std_logic_vector(7826265,28); exponent <= conv_std_logic_vector(1364,11); WHEN "0011101110" => manhi <= conv_std_logic_vector(4776297,24); manlo <= conv_std_logic_vector(138324122,28); exponent <= conv_std_logic_vector(1366,11); WHEN "0011101111" => manhi <= conv_std_logic_vector(12517046,24); manlo <= conv_std_logic_vector(17190560,28); exponent <= conv_std_logic_vector(1367,11); WHEN "0011110000" => manhi <= conv_std_logic_vector(3130299,24); manlo <= conv_std_logic_vector(16562242,28); exponent <= conv_std_logic_vector(1369,11); WHEN "0011110001" => manhi <= conv_std_logic_vector(10279902,24); manlo <= conv_std_logic_vector(59323104,28); exponent <= conv_std_logic_vector(1370,11); WHEN "0011110010" => manhi <= conv_std_logic_vector(1610002,24); manlo <= conv_std_logic_vector(53056333,28); exponent <= conv_std_logic_vector(1372,11); WHEN "0011110011" => manhi <= conv_std_logic_vector(8213604,24); manlo <= conv_std_logic_vector(147986337,28); exponent <= conv_std_logic_vector(1373,11); WHEN "0011110100" => manhi <= conv_std_logic_vector(205807,24); manlo <= conv_std_logic_vector(92802035,28); exponent <= conv_std_logic_vector(1375,11); WHEN "0011110101" => manhi <= conv_std_logic_vector(6305105,24); manlo <= conv_std_logic_vector(235277170,28); exponent <= conv_std_logic_vector(1376,11); WHEN "0011110110" => manhi <= conv_std_logic_vector(14594912,24); manlo <= conv_std_logic_vector(15497684,28); exponent <= conv_std_logic_vector(1377,11); WHEN "0011110111" => manhi <= conv_std_logic_vector(4542355,24); manlo <= conv_std_logic_vector(108677892,28); exponent <= conv_std_logic_vector(1379,11); WHEN "0011111000" => manhi <= conv_std_logic_vector(12199085,24); manlo <= conv_std_logic_vector(206743222,28); exponent <= conv_std_logic_vector(1380,11); WHEN "0011111001" => manhi <= conv_std_logic_vector(2914222,24); manlo <= conv_std_logic_vector(171652524,28); exponent <= conv_std_logic_vector(1382,11); WHEN "0011111010" => manhi <= conv_std_logic_vector(9986223,24); manlo <= conv_std_logic_vector(245598061,28); exponent <= conv_std_logic_vector(1383,11); WHEN "0011111011" => manhi <= conv_std_logic_vector(1410427,24); manlo <= conv_std_logic_vector(26024388,28); exponent <= conv_std_logic_vector(1385,11); WHEN "0011111100" => manhi <= conv_std_logic_vector(7942353,24); manlo <= conv_std_logic_vector(232590388,28); exponent <= conv_std_logic_vector(1386,11); WHEN "0011111101" => manhi <= conv_std_logic_vector(21473,24); manlo <= conv_std_logic_vector(105719295,28); exponent <= conv_std_logic_vector(1388,11); WHEN "0011111110" => manhi <= conv_std_logic_vector(6054570,24); manlo <= conv_std_logic_vector(16265786,28); exponent <= conv_std_logic_vector(1389,11); WHEN "0011111111" => manhi <= conv_std_logic_vector(14254398,24); manlo <= conv_std_logic_vector(155662944,28); exponent <= conv_std_logic_vector(1390,11); WHEN "0100000000" => manhi <= conv_std_logic_vector(4310952,24); manlo <= conv_std_logic_vector(135577274,28); exponent <= conv_std_logic_vector(1392,11); WHEN "0100000001" => manhi <= conv_std_logic_vector(11884576,24); manlo <= conv_std_logic_vector(166805756,28); exponent <= conv_std_logic_vector(1393,11); WHEN "0100000010" => manhi <= conv_std_logic_vector(2700491,24); manlo <= conv_std_logic_vector(137829044,28); exponent <= conv_std_logic_vector(1395,11); WHEN "0100000011" => manhi <= conv_std_logic_vector(9695733,24); manlo <= conv_std_logic_vector(52863001,28); exponent <= conv_std_logic_vector(1396,11); WHEN "0100000100" => manhi <= conv_std_logic_vector(1213018,24); manlo <= conv_std_logic_vector(50179603,28); exponent <= conv_std_logic_vector(1398,11); WHEN "0100000101" => manhi <= conv_std_logic_vector(7674047,24); manlo <= conv_std_logic_vector(91276680,28); exponent <= conv_std_logic_vector(1399,11); WHEN "0100000110" => manhi <= conv_std_logic_vector(16455496,24); manlo <= conv_std_logic_vector(110068760,28); exponent <= conv_std_logic_vector(1400,11); WHEN "0100000111" => manhi <= conv_std_logic_vector(5806753,24); manlo <= conv_std_logic_vector(151304445,28); exponent <= conv_std_logic_vector(1402,11); WHEN "0100001000" => manhi <= conv_std_logic_vector(13917581,24); manlo <= conv_std_logic_vector(10650184,28); exponent <= conv_std_logic_vector(1403,11); WHEN "0100001001" => manhi <= conv_std_logic_vector(4082061,24); manlo <= conv_std_logic_vector(68530707,28); exponent <= conv_std_logic_vector(1405,11); WHEN "0100001010" => manhi <= conv_std_logic_vector(11573481,24); manlo <= conv_std_logic_vector(42662756,28); exponent <= conv_std_logic_vector(1406,11); WHEN "0100001011" => manhi <= conv_std_logic_vector(2489080,24); manlo <= conv_std_logic_vector(61154162,28); exponent <= conv_std_logic_vector(1408,11); WHEN "0100001100" => manhi <= conv_std_logic_vector(9408395,24); manlo <= conv_std_logic_vector(125867240,28); exponent <= conv_std_logic_vector(1409,11); WHEN "0100001101" => manhi <= conv_std_logic_vector(1017751,24); manlo <= conv_std_logic_vector(256555705,28); exponent <= conv_std_logic_vector(1411,11); WHEN "0100001110" => manhi <= conv_std_logic_vector(7408653,24); manlo <= conv_std_logic_vector(4309896,28); exponent <= conv_std_logic_vector(1412,11); WHEN "0100001111" => manhi <= conv_std_logic_vector(16094788,24); manlo <= conv_std_logic_vector(33800670,28); exponent <= conv_std_logic_vector(1413,11); WHEN "0100010000" => manhi <= conv_std_logic_vector(5561626,24); manlo <= conv_std_logic_vector(233573192,28); exponent <= conv_std_logic_vector(1415,11); WHEN "0100010001" => manhi <= conv_std_logic_vector(13584419,24); manlo <= conv_std_logic_vector(86257801,28); exponent <= conv_std_logic_vector(1416,11); WHEN "0100010010" => manhi <= conv_std_logic_vector(3855654,24); manlo <= conv_std_logic_vector(105782775,28); exponent <= conv_std_logic_vector(1418,11); WHEN "0100010011" => manhi <= conv_std_logic_vector(11265762,24); manlo <= conv_std_logic_vector(88738762,28); exponent <= conv_std_logic_vector(1419,11); WHEN "0100010100" => manhi <= conv_std_logic_vector(2279963,24); manlo <= conv_std_logic_vector(161858527,28); exponent <= conv_std_logic_vector(1421,11); WHEN "0100010101" => manhi <= conv_std_logic_vector(9124176,24); manlo <= conv_std_logic_vector(136423424,28); exponent <= conv_std_logic_vector(1422,11); WHEN "0100010110" => manhi <= conv_std_logic_vector(824605,24); manlo <= conv_std_logic_vector(39384255,28); exponent <= conv_std_logic_vector(1424,11); WHEN "0100010111" => manhi <= conv_std_logic_vector(7146139,24); manlo <= conv_std_logic_vector(76626123,28); exponent <= conv_std_logic_vector(1425,11); WHEN "0100011000" => manhi <= conv_std_logic_vector(15737994,24); manlo <= conv_std_logic_vector(261485765,28); exponent <= conv_std_logic_vector(1426,11); WHEN "0100011001" => manhi <= conv_std_logic_vector(5319160,24); manlo <= conv_std_logic_vector(210684009,28); exponent <= conv_std_logic_vector(1428,11); WHEN "0100011010" => manhi <= conv_std_logic_vector(13254873,24); manlo <= conv_std_logic_vector(199859160,28); exponent <= conv_std_logic_vector(1429,11); WHEN "0100011011" => manhi <= conv_std_logic_vector(3631704,24); manlo <= conv_std_logic_vector(256571707,28); exponent <= conv_std_logic_vector(1431,11); WHEN "0100011100" => manhi <= conv_std_logic_vector(10961383,24); manlo <= conv_std_logic_vector(130542749,28); exponent <= conv_std_logic_vector(1432,11); WHEN "0100011101" => manhi <= conv_std_logic_vector(2073116,24); manlo <= conv_std_logic_vector(196665136,28); exponent <= conv_std_logic_vector(1434,11); WHEN "0100011110" => manhi <= conv_std_logic_vector(8843042,24); manlo <= conv_std_logic_vector(124490661,28); exponent <= conv_std_logic_vector(1435,11); WHEN "0100011111" => manhi <= conv_std_logic_vector(633554,24); manlo <= conv_std_logic_vector(202834752,28); exponent <= conv_std_logic_vector(1437,11); WHEN "0100100000" => manhi <= conv_std_logic_vector(6886474,24); manlo <= conv_std_logic_vector(236822279,28); exponent <= conv_std_logic_vector(1438,11); WHEN "0100100001" => manhi <= conv_std_logic_vector(15385074,24); manlo <= conv_std_logic_vector(123405487,28); exponent <= conv_std_logic_vector(1439,11); WHEN "0100100010" => manhi <= conv_std_logic_vector(5079326,24); manlo <= conv_std_logic_vector(115311954,28); exponent <= conv_std_logic_vector(1441,11); WHEN "0100100011" => manhi <= conv_std_logic_vector(12928905,24); manlo <= conv_std_logic_vector(16004876,28); exponent <= conv_std_logic_vector(1442,11); WHEN "0100100100" => manhi <= conv_std_logic_vector(3410186,24); manlo <= conv_std_logic_vector(71831800,28); exponent <= conv_std_logic_vector(1444,11); WHEN "0100100101" => manhi <= conv_std_logic_vector(10660308,24); manlo <= conv_std_logic_vector(100367284,28); exponent <= conv_std_logic_vector(1445,11); WHEN "0100100110" => manhi <= conv_std_logic_vector(1868514,24); manlo <= conv_std_logic_vector(263299419,28); exponent <= conv_std_logic_vector(1447,11); WHEN "0100100111" => manhi <= conv_std_logic_vector(8564959,24); manlo <= conv_std_logic_vector(228656810,28); exponent <= conv_std_logic_vector(1448,11); WHEN "0100101000" => manhi <= conv_std_logic_vector(444578,24); manlo <= conv_std_logic_vector(7489141,28); exponent <= conv_std_logic_vector(1450,11); WHEN "0100101001" => manhi <= conv_std_logic_vector(6629628,24); manlo <= conv_std_logic_vector(236156491,28); exponent <= conv_std_logic_vector(1451,11); WHEN "0100101010" => manhi <= conv_std_logic_vector(15035984,24); manlo <= conv_std_logic_vector(147396312,28); exponent <= conv_std_logic_vector(1452,11); WHEN "0100101011" => manhi <= conv_std_logic_vector(4842095,24); manlo <= conv_std_logic_vector(64271882,28); exponent <= conv_std_logic_vector(1454,11); WHEN "0100101100" => manhi <= conv_std_logic_vector(12606474,24); manlo <= conv_std_logic_vector(118909770,28); exponent <= conv_std_logic_vector(1455,11); WHEN "0100101101" => manhi <= conv_std_logic_vector(3191071,24); manlo <= conv_std_logic_vector(253953386,28); exponent <= conv_std_logic_vector(1457,11); WHEN "0100101110" => manhi <= conv_std_logic_vector(10362501,24); manlo <= conv_std_logic_vector(36129498,28); exponent <= conv_std_logic_vector(1458,11); WHEN "0100101111" => manhi <= conv_std_logic_vector(1666133,24); manlo <= conv_std_logic_vector(262830684,28); exponent <= conv_std_logic_vector(1460,11); WHEN "0100110000" => manhi <= conv_std_logic_vector(8289895,24); manlo <= conv_std_logic_vector(148197046,28); exponent <= conv_std_logic_vector(1461,11); WHEN "0100110001" => manhi <= conv_std_logic_vector(257652,24); manlo <= conv_std_logic_vector(122404338,28); exponent <= conv_std_logic_vector(1463,11); WHEN "0100110010" => manhi <= conv_std_logic_vector(6375570,24); manlo <= conv_std_logic_vector(184430245,28); exponent <= conv_std_logic_vector(1464,11); WHEN "0100110011" => manhi <= conv_std_logic_vector(14690683,24); manlo <= conv_std_logic_vector(178457687,28); exponent <= conv_std_logic_vector(1465,11); WHEN "0100110100" => manhi <= conv_std_logic_vector(4607438,24); manlo <= conv_std_logic_vector(257605193,28); exponent <= conv_std_logic_vector(1467,11); WHEN "0100110101" => manhi <= conv_std_logic_vector(12287543,24); manlo <= conv_std_logic_vector(132163446,28); exponent <= conv_std_logic_vector(1468,11); WHEN "0100110110" => manhi <= conv_std_logic_vector(2974335,24); manlo <= conv_std_logic_vector(240020217,28); exponent <= conv_std_logic_vector(1470,11); WHEN "0100110111" => manhi <= conv_std_logic_vector(10067926,24); manlo <= conv_std_logic_vector(80224641,28); exponent <= conv_std_logic_vector(1471,11); WHEN "0100111000" => manhi <= conv_std_logic_vector(1465949,24); manlo <= conv_std_logic_vector(167328478,28); exponent <= conv_std_logic_vector(1473,11); WHEN "0100111001" => manhi <= conv_std_logic_vector(8017816,24); manlo <= conv_std_logic_vector(215756784,28); exponent <= conv_std_logic_vector(1474,11); WHEN "0100111010" => manhi <= conv_std_logic_vector(72755,24); manlo <= conv_std_logic_vector(208473528,28); exponent <= conv_std_logic_vector(1476,11); WHEN "0100111011" => manhi <= conv_std_logic_vector(6124270,24); manlo <= conv_std_logic_vector(12139444,28); exponent <= conv_std_logic_vector(1477,11); WHEN "0100111100" => manhi <= conv_std_logic_vector(14349130,24); manlo <= conv_std_logic_vector(182729110,28); exponent <= conv_std_logic_vector(1478,11); WHEN "0100111101" => manhi <= conv_std_logic_vector(4375329,24); manlo <= conv_std_logic_vector(172370119,28); exponent <= conv_std_logic_vector(1480,11); WHEN "0100111110" => manhi <= conv_std_logic_vector(11972074,24); manlo <= conv_std_logic_vector(59679792,28); exponent <= conv_std_logic_vector(1481,11); WHEN "0100111111" => manhi <= conv_std_logic_vector(2759952,24); manlo <= conv_std_logic_vector(80023302,28); exponent <= conv_std_logic_vector(1483,11); WHEN "0101000000" => manhi <= conv_std_logic_vector(9776548,24); manlo <= conv_std_logic_vector(209956608,28); exponent <= conv_std_logic_vector(1484,11); WHEN "0101000001" => manhi <= conv_std_logic_vector(1267938,24); manlo <= conv_std_logic_vector(19091951,28); exponent <= conv_std_logic_vector(1486,11); WHEN "0101000010" => manhi <= conv_std_logic_vector(7748691,24); manlo <= conv_std_logic_vector(54127000,28); exponent <= conv_std_logic_vector(1487,11); WHEN "0101000011" => manhi <= conv_std_logic_vector(16556947,24); manlo <= conv_std_logic_vector(251347868,28); exponent <= conv_std_logic_vector(1488,11); WHEN "0101000100" => manhi <= conv_std_logic_vector(5875697,24); manlo <= conv_std_logic_vector(6377900,28); exponent <= conv_std_logic_vector(1490,11); WHEN "0101000101" => manhi <= conv_std_logic_vector(14011284,24); manlo <= conv_std_logic_vector(246175281,28); exponent <= conv_std_logic_vector(1491,11); WHEN "0101000110" => manhi <= conv_std_logic_vector(4145739,24); manlo <= conv_std_logic_vector(172360927,28); exponent <= conv_std_logic_vector(1493,11); WHEN "0101000111" => manhi <= conv_std_logic_vector(11660029,24); manlo <= conv_std_logic_vector(16047086,28); exponent <= conv_std_logic_vector(1494,11); WHEN "0101001000" => manhi <= conv_std_logic_vector(2547895,24); manlo <= conv_std_logic_vector(167600151,28); exponent <= conv_std_logic_vector(1496,11); WHEN "0101001001" => manhi <= conv_std_logic_vector(9488333,24); manlo <= conv_std_logic_vector(236416250,28); exponent <= conv_std_logic_vector(1497,11); WHEN "0101001010" => manhi <= conv_std_logic_vector(1072075,24); manlo <= conv_std_logic_vector(198323037,28); exponent <= conv_std_logic_vector(1499,11); WHEN "0101001011" => manhi <= conv_std_logic_vector(7482486,24); manlo <= conv_std_logic_vector(185820926,28); exponent <= conv_std_logic_vector(1500,11); WHEN "0101001100" => manhi <= conv_std_logic_vector(16195138,24); manlo <= conv_std_logic_vector(133160968,28); exponent <= conv_std_logic_vector(1501,11); WHEN "0101001101" => manhi <= conv_std_logic_vector(5629822,24); manlo <= conv_std_logic_vector(4574050,28); exponent <= conv_std_logic_vector(1503,11); WHEN "0101001110" => manhi <= conv_std_logic_vector(13677106,24); manlo <= conv_std_logic_vector(36414601,28); exponent <= conv_std_logic_vector(1504,11); WHEN "0101001111" => manhi <= conv_std_logic_vector(3918641,24); manlo <= conv_std_logic_vector(165046798,28); exponent <= conv_std_logic_vector(1506,11); WHEN "0101010000" => manhi <= conv_std_logic_vector(11351370,24); manlo <= conv_std_logic_vector(225326735,28); exponent <= conv_std_logic_vector(1507,11); WHEN "0101010001" => manhi <= conv_std_logic_vector(2338140,24); manlo <= conv_std_logic_vector(165476611,28); exponent <= conv_std_logic_vector(1509,11); WHEN "0101010010" => manhi <= conv_std_logic_vector(9203247,24); manlo <= conv_std_logic_vector(71807303,28); exponent <= conv_std_logic_vector(1510,11); WHEN "0101010011" => manhi <= conv_std_logic_vector(878339,24); manlo <= conv_std_logic_vector(80195176,28); exponent <= conv_std_logic_vector(1512,11); WHEN "0101010100" => manhi <= conv_std_logic_vector(7219171,24); manlo <= conv_std_logic_vector(153001068,28); exponent <= conv_std_logic_vector(1513,11); WHEN "0101010101" => manhi <= conv_std_logic_vector(15837256,24); manlo <= conv_std_logic_vector(37596960,28); exponent <= conv_std_logic_vector(1514,11); WHEN "0101010110" => manhi <= conv_std_logic_vector(5386615,24); manlo <= conv_std_logic_vector(198850796,28); exponent <= conv_std_logic_vector(1516,11); WHEN "0101010111" => manhi <= conv_std_logic_vector(13346554,24); manlo <= conv_std_logic_vector(143609986,28); exponent <= conv_std_logic_vector(1517,11); WHEN "0101011000" => manhi <= conv_std_logic_vector(3694008,24); manlo <= conv_std_logic_vector(137568494,28); exponent <= conv_std_logic_vector(1519,11); WHEN "0101011001" => manhi <= conv_std_logic_vector(11046062,24); manlo <= conv_std_logic_vector(214558683,28); exponent <= conv_std_logic_vector(1520,11); WHEN "0101011010" => manhi <= conv_std_logic_vector(2130662,24); manlo <= conv_std_logic_vector(78401205,28); exponent <= conv_std_logic_vector(1522,11); WHEN "0101011011" => manhi <= conv_std_logic_vector(8921254,24); manlo <= conv_std_logic_vector(265219821,28); exponent <= conv_std_logic_vector(1523,11); WHEN "0101011100" => manhi <= conv_std_logic_vector(686705,24); manlo <= conv_std_logic_vector(181591149,28); exponent <= conv_std_logic_vector(1525,11); WHEN "0101011101" => manhi <= conv_std_logic_vector(6958714,24); manlo <= conv_std_logic_vector(127078273,28); exponent <= conv_std_logic_vector(1526,11); WHEN "0101011110" => manhi <= conv_std_logic_vector(15483258,24); manlo <= conv_std_logic_vector(65420394,28); exponent <= conv_std_logic_vector(1527,11); WHEN "0101011111" => manhi <= conv_std_logic_vector(5146049,24); manlo <= conv_std_logic_vector(61347424,28); exponent <= conv_std_logic_vector(1529,11); WHEN "0101100000" => manhi <= conv_std_logic_vector(13019590,24); manlo <= conv_std_logic_vector(200148168,28); exponent <= conv_std_logic_vector(1530,11); WHEN "0101100001" => manhi <= conv_std_logic_vector(3471813,24); manlo <= conv_std_logic_vector(155873600,28); exponent <= conv_std_logic_vector(1532,11); WHEN "0101100010" => manhi <= conv_std_logic_vector(10744068,24); manlo <= conv_std_logic_vector(154763366,28); exponent <= conv_std_logic_vector(1533,11); WHEN "0101100011" => manhi <= conv_std_logic_vector(1925435,24); manlo <= conv_std_logic_vector(252346422,28); exponent <= conv_std_logic_vector(1535,11); WHEN "0101100100" => manhi <= conv_std_logic_vector(8642323,24); manlo <= conv_std_logic_vector(122496413,28); exponent <= conv_std_logic_vector(1536,11); WHEN "0101100101" => manhi <= conv_std_logic_vector(497152,24); manlo <= conv_std_logic_vector(12881703,28); exponent <= conv_std_logic_vector(1538,11); WHEN "0101100110" => manhi <= conv_std_logic_vector(6701084,24); manlo <= conv_std_logic_vector(102402698,28); exponent <= conv_std_logic_vector(1539,11); WHEN "0101100111" => manhi <= conv_std_logic_vector(15133102,24); manlo <= conv_std_logic_vector(173151546,28); exponent <= conv_std_logic_vector(1540,11); WHEN "0101101000" => manhi <= conv_std_logic_vector(4908093,24); manlo <= conv_std_logic_vector(222341698,28); exponent <= conv_std_logic_vector(1542,11); WHEN "0101101001" => manhi <= conv_std_logic_vector(12696175,24); manlo <= conv_std_logic_vector(221558290,28); exponent <= conv_std_logic_vector(1543,11); WHEN "0101101010" => manhi <= conv_std_logic_vector(3252030,24); manlo <= conv_std_logic_vector(95425703,28); exponent <= conv_std_logic_vector(1545,11); WHEN "0101101011" => manhi <= conv_std_logic_vector(10445352,24); manlo <= conv_std_logic_vector(54472775,28); exponent <= conv_std_logic_vector(1546,11); WHEN "0101101100" => manhi <= conv_std_logic_vector(1722437,24); manlo <= conv_std_logic_vector(31541381,28); exponent <= conv_std_logic_vector(1548,11); WHEN "0101101101" => manhi <= conv_std_logic_vector(8366419,24); manlo <= conv_std_logic_vector(121077564,28); exponent <= conv_std_logic_vector(1549,11); WHEN "0101101110" => manhi <= conv_std_logic_vector(309655,24); manlo <= conv_std_logic_vector(224679493,28); exponent <= conv_std_logic_vector(1551,11); WHEN "0101101111" => manhi <= conv_std_logic_vector(6446250,24); manlo <= conv_std_logic_vector(163707479,28); exponent <= conv_std_logic_vector(1552,11); WHEN "0101110000" => manhi <= conv_std_logic_vector(14786747,24); manlo <= conv_std_logic_vector(171718440,28); exponent <= conv_std_logic_vector(1553,11); WHEN "0101110001" => manhi <= conv_std_logic_vector(4672721,24); manlo <= conv_std_logic_vector(53414720,28); exponent <= conv_std_logic_vector(1555,11); WHEN "0101110010" => manhi <= conv_std_logic_vector(12376271,24); manlo <= conv_std_logic_vector(68395953,28); exponent <= conv_std_logic_vector(1556,11); WHEN "0101110011" => manhi <= conv_std_logic_vector(3034632,24); manlo <= conv_std_logic_vector(177229210,28); exponent <= conv_std_logic_vector(1558,11); WHEN "0101110100" => manhi <= conv_std_logic_vector(10149878,24); manlo <= conv_std_logic_vector(27015960,28); exponent <= conv_std_logic_vector(1559,11); WHEN "0101110101" => manhi <= conv_std_logic_vector(1521641,24); manlo <= conv_std_logic_vector(173609470,28); exponent <= conv_std_logic_vector(1561,11); WHEN "0101110110" => manhi <= conv_std_logic_vector(8093510,24); manlo <= conv_std_logic_vector(29891310,28); exponent <= conv_std_logic_vector(1562,11); WHEN "0101110111" => manhi <= conv_std_logic_vector(124194,24); manlo <= conv_std_logic_vector(191198183,28); exponent <= conv_std_logic_vector(1564,11); WHEN "0101111000" => manhi <= conv_std_logic_vector(6194182,24); manlo <= conv_std_logic_vector(216692261,28); exponent <= conv_std_logic_vector(1565,11); WHEN "0101111001" => manhi <= conv_std_logic_vector(14444151,24); manlo <= conv_std_logic_vector(261994424,28); exponent <= conv_std_logic_vector(1566,11); WHEN "0101111010" => manhi <= conv_std_logic_vector(4439903,24); manlo <= conv_std_logic_vector(82463931,28); exponent <= conv_std_logic_vector(1568,11); WHEN "0101111011" => manhi <= conv_std_logic_vector(12059838,24); manlo <= conv_std_logic_vector(250318074,28); exponent <= conv_std_logic_vector(1569,11); WHEN "0101111100" => manhi <= conv_std_logic_vector(2819594,24); manlo <= conv_std_logic_vector(161686084,28); exponent <= conv_std_logic_vector(1571,11); WHEN "0101111101" => manhi <= conv_std_logic_vector(9857611,24); manlo <= conv_std_logic_vector(20946108,28); exponent <= conv_std_logic_vector(1572,11); WHEN "0101111110" => manhi <= conv_std_logic_vector(1323025,24); manlo <= conv_std_logic_vector(164440795,28); exponent <= conv_std_logic_vector(1574,11); WHEN "0101111111" => manhi <= conv_std_logic_vector(7823562,24); manlo <= conv_std_logic_vector(250479918,28); exponent <= conv_std_logic_vector(1575,11); WHEN "0110000000" => manhi <= conv_std_logic_vector(16658709,24); manlo <= conv_std_logic_vector(45608811,28); exponent <= conv_std_logic_vector(1576,11); WHEN "0110000001" => manhi <= conv_std_logic_vector(5944850,24); manlo <= conv_std_logic_vector(255488281,28); exponent <= conv_std_logic_vector(1578,11); WHEN "0110000010" => manhi <= conv_std_logic_vector(14105274,24); manlo <= conv_std_logic_vector(228172930,28); exponent <= conv_std_logic_vector(1579,11); WHEN "0110000011" => manhi <= conv_std_logic_vector(4209612,24); manlo <= conv_std_logic_vector(113758652,28); exponent <= conv_std_logic_vector(1581,11); WHEN "0110000100" => manhi <= conv_std_logic_vector(11746841,24); manlo <= conv_std_logic_vector(45816542,28); exponent <= conv_std_logic_vector(1582,11); WHEN "0110000101" => manhi <= conv_std_logic_vector(2606890,24); manlo <= conv_std_logic_vector(153074390,28); exponent <= conv_std_logic_vector(1584,11); WHEN "0110000110" => manhi <= conv_std_logic_vector(9568516,24); manlo <= conv_std_logic_vector(87350878,28); exponent <= conv_std_logic_vector(1585,11); WHEN "0110000111" => manhi <= conv_std_logic_vector(1126565,24); manlo <= conv_std_logic_vector(96475766,28); exponent <= conv_std_logic_vector(1587,11); WHEN "0110001000" => manhi <= conv_std_logic_vector(7556545,24); manlo <= conv_std_logic_vector(205347948,28); exponent <= conv_std_logic_vector(1588,11); WHEN "0110001001" => manhi <= conv_std_logic_vector(16295795,24); manlo <= conv_std_logic_vector(56881285,28); exponent <= conv_std_logic_vector(1589,11); WHEN "0110001010" => manhi <= conv_std_logic_vector(5698225,24); manlo <= conv_std_logic_vector(93263076,28); exponent <= conv_std_logic_vector(1591,11); WHEN "0110001011" => manhi <= conv_std_logic_vector(13770075,24); manlo <= conv_std_logic_vector(241769289,28); exponent <= conv_std_logic_vector(1592,11); WHEN "0110001100" => manhi <= conv_std_logic_vector(3981821,24); manlo <= conv_std_logic_vector(32359920,28); exponent <= conv_std_logic_vector(1594,11); WHEN "0110001101" => manhi <= conv_std_logic_vector(11437240,24); manlo <= conv_std_logic_vector(185367850,28); exponent <= conv_std_logic_vector(1595,11); WHEN "0110001110" => manhi <= conv_std_logic_vector(2396495,24); manlo <= conv_std_logic_vector(61858550,28); exponent <= conv_std_logic_vector(1597,11); WHEN "0110001111" => manhi <= conv_std_logic_vector(9282559,24); manlo <= conv_std_logic_vector(110304027,28); exponent <= conv_std_logic_vector(1598,11); WHEN "0110010000" => manhi <= conv_std_logic_vector(932237,24); manlo <= conv_std_logic_vector(131077892,28); exponent <= conv_std_logic_vector(1600,11); WHEN "0110010001" => manhi <= conv_std_logic_vector(7292426,24); manlo <= conv_std_logic_vector(215982528,28); exponent <= conv_std_logic_vector(1601,11); WHEN "0110010010" => manhi <= conv_std_logic_vector(15936820,24); manlo <= conv_std_logic_vector(87676082,28); exponent <= conv_std_logic_vector(1602,11); WHEN "0110010011" => manhi <= conv_std_logic_vector(5454276,24); manlo <= conv_std_logic_vector(166577430,28); exponent <= conv_std_logic_vector(1604,11); WHEN "0110010100" => manhi <= conv_std_logic_vector(13438515,24); manlo <= conv_std_logic_vector(55023964,28); exponent <= conv_std_logic_vector(1605,11); WHEN "0110010101" => manhi <= conv_std_logic_vector(3756502,24); manlo <= conv_std_logic_vector(71679026,28); exponent <= conv_std_logic_vector(1607,11); WHEN "0110010110" => manhi <= conv_std_logic_vector(11131000,24); manlo <= conv_std_logic_vector(165886683,28); exponent <= conv_std_logic_vector(1608,11); WHEN "0110010111" => manhi <= conv_std_logic_vector(2188383,24); manlo <= conv_std_logic_vector(140750309,28); exponent <= conv_std_logic_vector(1610,11); WHEN "0110011000" => manhi <= conv_std_logic_vector(8999706,24); manlo <= conv_std_logic_vector(74200045,28); exponent <= conv_std_logic_vector(1611,11); WHEN "0110011001" => manhi <= conv_std_logic_vector(740018,24); manlo <= conv_std_logic_vector(229350227,28); exponent <= conv_std_logic_vector(1613,11); WHEN "0110011010" => manhi <= conv_std_logic_vector(7031174,24); manlo <= conv_std_logic_vector(159659309,28); exponent <= conv_std_logic_vector(1614,11); WHEN "0110011011" => manhi <= conv_std_logic_vector(15581741,24); manlo <= conv_std_logic_vector(203828183,28); exponent <= conv_std_logic_vector(1615,11); WHEN "0110011100" => manhi <= conv_std_logic_vector(5212975,24); manlo <= conv_std_logic_vector(192268981,28); exponent <= conv_std_logic_vector(1617,11); WHEN "0110011101" => manhi <= conv_std_logic_vector(13110553,24); manlo <= conv_std_logic_vector(73367990,28); exponent <= conv_std_logic_vector(1618,11); WHEN "0110011110" => manhi <= conv_std_logic_vector(3533629,24); manlo <= conv_std_logic_vector(7303751,28); exponent <= conv_std_logic_vector(1620,11); WHEN "0110011111" => manhi <= conv_std_logic_vector(10828084,24); manlo <= conv_std_logic_vector(128595197,28); exponent <= conv_std_logic_vector(1621,11); WHEN "0110100000" => manhi <= conv_std_logic_vector(1982530,24); manlo <= conv_std_logic_vector(178601213,28); exponent <= conv_std_logic_vector(1623,11); WHEN "0110100001" => manhi <= conv_std_logic_vector(8719923,24); manlo <= conv_std_logic_vector(62665264,28); exponent <= conv_std_logic_vector(1624,11); WHEN "0110100010" => manhi <= conv_std_logic_vector(549886,24); manlo <= conv_std_logic_vector(151395401,28); exponent <= conv_std_logic_vector(1626,11); WHEN "0110100011" => manhi <= conv_std_logic_vector(6772758,24); manlo <= conv_std_logic_vector(5307652,28); exponent <= conv_std_logic_vector(1627,11); WHEN "0110100100" => manhi <= conv_std_logic_vector(15230517,24); manlo <= conv_std_logic_vector(58871965,28); exponent <= conv_std_logic_vector(1628,11); WHEN "0110100101" => manhi <= conv_std_logic_vector(4974293,24); manlo <= conv_std_logic_vector(240265124,28); exponent <= conv_std_logic_vector(1630,11); WHEN "0110100110" => manhi <= conv_std_logic_vector(12786151,24); manlo <= conv_std_logic_vector(11983156,28); exponent <= conv_std_logic_vector(1631,11); WHEN "0110100111" => manhi <= conv_std_logic_vector(3313174,24); manlo <= conv_std_logic_vector(229882212,28); exponent <= conv_std_logic_vector(1633,11); WHEN "0110101000" => manhi <= conv_std_logic_vector(10528456,24); manlo <= conv_std_logic_vector(52550536,28); exponent <= conv_std_logic_vector(1634,11); WHEN "0110101001" => manhi <= conv_std_logic_vector(1778912,24); manlo <= conv_std_logic_vector(36481057,28); exponent <= conv_std_logic_vector(1636,11); WHEN "0110101010" => manhi <= conv_std_logic_vector(8443176,24); manlo <= conv_std_logic_vector(257480801,28); exponent <= conv_std_logic_vector(1637,11); WHEN "0110101011" => manhi <= conv_std_logic_vector(361817,24); manlo <= conv_std_logic_vector(260890045,28); exponent <= conv_std_logic_vector(1639,11); WHEN "0110101100" => manhi <= conv_std_logic_vector(6517146,24); manlo <= conv_std_logic_vector(80951272,28); exponent <= conv_std_logic_vector(1640,11); WHEN "0110101101" => manhi <= conv_std_logic_vector(14883104,24); manlo <= conv_std_logic_vector(234866389,28); exponent <= conv_std_logic_vector(1641,11); WHEN "0110101110" => manhi <= conv_std_logic_vector(4738202,24); manlo <= conv_std_logic_vector(195793257,28); exponent <= conv_std_logic_vector(1643,11); WHEN "0110101111" => manhi <= conv_std_logic_vector(12465269,24); manlo <= conv_std_logic_vector(236730454,28); exponent <= conv_std_logic_vector(1644,11); WHEN "0110110000" => manhi <= conv_std_logic_vector(3095113,24); manlo <= conv_std_logic_vector(133661452,28); exponent <= conv_std_logic_vector(1646,11); WHEN "0110110001" => manhi <= conv_std_logic_vector(10232080,24); manlo <= conv_std_logic_vector(21926822,28); exponent <= conv_std_logic_vector(1647,11); WHEN "0110110010" => manhi <= conv_std_logic_vector(1577503,24); manlo <= conv_std_logic_vector(183764948,28); exponent <= conv_std_logic_vector(1649,11); WHEN "0110110011" => manhi <= conv_std_logic_vector(8169434,24); manlo <= conv_std_logic_vector(132210812,28); exponent <= conv_std_logic_vector(1650,11); WHEN "0110110100" => manhi <= conv_std_logic_vector(175790,24); manlo <= conv_std_logic_vector(182183516,28); exponent <= conv_std_logic_vector(1652,11); WHEN "0110110101" => manhi <= conv_std_logic_vector(6264308,24); manlo <= conv_std_logic_vector(267417858,28); exponent <= conv_std_logic_vector(1653,11); WHEN "0110110110" => manhi <= conv_std_logic_vector(14539463,24); manlo <= conv_std_logic_vector(93573944,28); exponent <= conv_std_logic_vector(1654,11); WHEN "0110110111" => manhi <= conv_std_logic_vector(4504674,24); manlo <= conv_std_logic_vector(26907375,28); exponent <= conv_std_logic_vector(1656,11); WHEN "0110111000" => manhi <= conv_std_logic_vector(12147871,24); manlo <= conv_std_logic_vector(152302066,28); exponent <= conv_std_logic_vector(1657,11); WHEN "0110111001" => manhi <= conv_std_logic_vector(2879418,24); manlo <= conv_std_logic_vector(263131635,28); exponent <= conv_std_logic_vector(1659,11); WHEN "0110111010" => manhi <= conv_std_logic_vector(9938920,24); manlo <= conv_std_logic_vector(224874222,28); exponent <= conv_std_logic_vector(1660,11); WHEN "0110111011" => manhi <= conv_std_logic_vector(1378281,24); manlo <= conv_std_logic_vector(86745210,28); exponent <= conv_std_logic_vector(1662,11); WHEN "0110111100" => manhi <= conv_std_logic_vector(7898663,24); manlo <= conv_std_logic_vector(61761420,28); exponent <= conv_std_logic_vector(1663,11); WHEN "0110111101" => manhi <= conv_std_logic_vector(16760781,24); manlo <= conv_std_logic_vector(15082626,28); exponent <= conv_std_logic_vector(1664,11); WHEN "0110111110" => manhi <= conv_std_logic_vector(6014215,24); manlo <= conv_std_logic_vector(265801199,28); exponent <= conv_std_logic_vector(1666,11); WHEN "0110111111" => manhi <= conv_std_logic_vector(14199551,24); manlo <= conv_std_logic_vector(191056853,28); exponent <= conv_std_logic_vector(1667,11); WHEN "0111000000" => manhi <= conv_std_logic_vector(4273680,24); manlo <= conv_std_logic_vector(52024524,28); exponent <= conv_std_logic_vector(1669,11); WHEN "0111000001" => manhi <= conv_std_logic_vector(11833918,24); manlo <= conv_std_logic_vector(80047690,28); exponent <= conv_std_logic_vector(1670,11); WHEN "0111000010" => manhi <= conv_std_logic_vector(2666065,24); manlo <= conv_std_logic_vector(164712049,28); exponent <= conv_std_logic_vector(1672,11); WHEN "0111000011" => manhi <= conv_std_logic_vector(9648943,24); manlo <= conv_std_logic_vector(147084012,28); exponent <= conv_std_logic_vector(1673,11); WHEN "0111000100" => manhi <= conv_std_logic_vector(1181221,24); manlo <= conv_std_logic_vector(86912647,28); exponent <= conv_std_logic_vector(1675,11); WHEN "0111000101" => manhi <= conv_std_logic_vector(7630830,24); manlo <= conv_std_logic_vector(247596521,28); exponent <= conv_std_logic_vector(1676,11); WHEN "0111000110" => manhi <= conv_std_logic_vector(16396759,24); manlo <= conv_std_logic_vector(56002502,28); exponent <= conv_std_logic_vector(1677,11); WHEN "0111000111" => manhi <= conv_std_logic_vector(5766837,24); manlo <= conv_std_logic_vector(133369322,28); exponent <= conv_std_logic_vector(1679,11); WHEN "0111001000" => manhi <= conv_std_logic_vector(13863329,24); manlo <= conv_std_logic_vector(128884889,28); exponent <= conv_std_logic_vector(1680,11); WHEN "0111001001" => manhi <= conv_std_logic_vector(4045193,24); manlo <= conv_std_logic_vector(133729186,28); exponent <= conv_std_logic_vector(1682,11); WHEN "0111001010" => manhi <= conv_std_logic_vector(11523372,24); manlo <= conv_std_logic_vector(183024104,28); exponent <= conv_std_logic_vector(1683,11); WHEN "0111001011" => manhi <= conv_std_logic_vector(2455027,24); manlo <= conv_std_logic_vector(264977965,28); exponent <= conv_std_logic_vector(1685,11); WHEN "0111001100" => manhi <= conv_std_logic_vector(9362113,24); manlo <= conv_std_logic_vector(181285013,28); exponent <= conv_std_logic_vector(1686,11); WHEN "0111001101" => manhi <= conv_std_logic_vector(986300,24); manlo <= conv_std_logic_vector(58020653,28); exponent <= conv_std_logic_vector(1688,11); WHEN "0111001110" => manhi <= conv_std_logic_vector(7365905,24); manlo <= conv_std_logic_vector(179835810,28); exponent <= conv_std_logic_vector(1689,11); WHEN "0111001111" => manhi <= conv_std_logic_vector(16036688,24); manlo <= conv_std_logic_vector(123168298,28); exponent <= conv_std_logic_vector(1690,11); WHEN "0111010000" => manhi <= conv_std_logic_vector(5522144,24); manlo <= conv_std_logic_vector(14176725,28); exponent <= conv_std_logic_vector(1692,11); WHEN "0111010001" => manhi <= conv_std_logic_vector(13530756,24); manlo <= conv_std_logic_vector(163453775,28); exponent <= conv_std_logic_vector(1693,11); WHEN "0111010010" => manhi <= conv_std_logic_vector(3819186,24); manlo <= conv_std_logic_vector(214764608,28); exponent <= conv_std_logic_vector(1695,11); WHEN "0111010011" => manhi <= conv_std_logic_vector(11216197,24); manlo <= conv_std_logic_vector(196364225,28); exponent <= conv_std_logic_vector(1696,11); WHEN "0111010100" => manhi <= conv_std_logic_vector(2246280,24); manlo <= conv_std_logic_vector(259235483,28); exponent <= conv_std_logic_vector(1698,11); WHEN "0111010101" => manhi <= conv_std_logic_vector(9078397,24); manlo <= conv_std_logic_vector(15526664,28); exponent <= conv_std_logic_vector(1699,11); WHEN "0111010110" => manhi <= conv_std_logic_vector(793494,24); manlo <= conv_std_logic_vector(210641201,28); exponent <= conv_std_logic_vector(1701,11); WHEN "0111010111" => manhi <= conv_std_logic_vector(7103855,24); manlo <= conv_std_logic_vector(246847656,28); exponent <= conv_std_logic_vector(1702,11); WHEN "0111011000" => manhi <= conv_std_logic_vector(15680525,24); manlo <= conv_std_logic_vector(247378795,28); exponent <= conv_std_logic_vector(1703,11); WHEN "0111011001" => manhi <= conv_std_logic_vector(5280106,24); manlo <= conv_std_logic_vector(138122391,28); exponent <= conv_std_logic_vector(1705,11); WHEN "0111011010" => manhi <= conv_std_logic_vector(13201793,24); manlo <= conv_std_logic_vector(130963079,28); exponent <= conv_std_logic_vector(1706,11); WHEN "0111011011" => manhi <= conv_std_logic_vector(3595633,24); manlo <= conv_std_logic_vector(48727293,28); exponent <= conv_std_logic_vector(1708,11); WHEN "0111011100" => manhi <= conv_std_logic_vector(10912356,24); manlo <= conv_std_logic_vector(231400966,28); exponent <= conv_std_logic_vector(1709,11); WHEN "0111011101" => manhi <= conv_std_logic_vector(2039799,24); manlo <= conv_std_logic_vector(184459756,28); exponent <= conv_std_logic_vector(1711,11); WHEN "0111011110" => manhi <= conv_std_logic_vector(8797759,24); manlo <= conv_std_logic_vector(242699544,28); exponent <= conv_std_logic_vector(1712,11); WHEN "0111011111" => manhi <= conv_std_logic_vector(602782,24); manlo <= conv_std_logic_vector(17680793,28); exponent <= conv_std_logic_vector(1714,11); WHEN "0111100000" => manhi <= conv_std_logic_vector(6844650,24); manlo <= conv_std_logic_vector(123627565,28); exponent <= conv_std_logic_vector(1715,11); WHEN "0111100001" => manhi <= conv_std_logic_vector(15328229,24); manlo <= conv_std_logic_vector(47512453,28); exponent <= conv_std_logic_vector(1716,11); WHEN "0111100010" => manhi <= conv_std_logic_vector(5040696,24); manlo <= conv_std_logic_vector(14711664,28); exponent <= conv_std_logic_vector(1718,11); WHEN "0111100011" => manhi <= conv_std_logic_vector(12876400,24); manlo <= conv_std_logic_vector(251456186,28); exponent <= conv_std_logic_vector(1719,11); WHEN "0111100100" => manhi <= conv_std_logic_vector(3374506,24); manlo <= conv_std_logic_vector(4512772,28); exponent <= conv_std_logic_vector(1721,11); WHEN "0111100101" => manhi <= conv_std_logic_vector(10611813,24); manlo <= conv_std_logic_vector(237626642,28); exponent <= conv_std_logic_vector(1722,11); WHEN "0111100110" => manhi <= conv_std_logic_vector(1835559,24); manlo <= conv_std_logic_vector(150064655,28); exponent <= conv_std_logic_vector(1724,11); WHEN "0111100111" => manhi <= conv_std_logic_vector(8520168,24); manlo <= conv_std_logic_vector(211971382,28); exponent <= conv_std_logic_vector(1725,11); WHEN "0111101000" => manhi <= conv_std_logic_vector(414139,24); manlo <= conv_std_logic_vector(92694471,28); exponent <= conv_std_logic_vector(1727,11); WHEN "0111101001" => manhi <= conv_std_logic_vector(6588258,24); manlo <= conv_std_logic_vector(112977613,28); exponent <= conv_std_logic_vector(1728,11); WHEN "0111101010" => manhi <= conv_std_logic_vector(14979756,24); manlo <= conv_std_logic_vector(71348470,28); exponent <= conv_std_logic_vector(1729,11); WHEN "0111101011" => manhi <= conv_std_logic_vector(4803884,24); manlo <= conv_std_logic_vector(42747344,28); exponent <= conv_std_logic_vector(1731,11); WHEN "0111101100" => manhi <= conv_std_logic_vector(12554540,24); manlo <= conv_std_logic_vector(53825836,28); exponent <= conv_std_logic_vector(1732,11); WHEN "0111101101" => manhi <= conv_std_logic_vector(3155778,24); manlo <= conv_std_logic_vector(260157975,28); exponent <= conv_std_logic_vector(1734,11); WHEN "0111101110" => manhi <= conv_std_logic_vector(10314533,24); manlo <= conv_std_logic_vector(1535990,28); exponent <= conv_std_logic_vector(1735,11); WHEN "0111101111" => manhi <= conv_std_logic_vector(1633536,24); manlo <= conv_std_logic_vector(68681060,28); exponent <= conv_std_logic_vector(1737,11); WHEN "0111110000" => manhi <= conv_std_logic_vector(8245590,24); manlo <= conv_std_logic_vector(175202070,28); exponent <= conv_std_logic_vector(1738,11); WHEN "0111110001" => manhi <= conv_std_logic_vector(227544,24); manlo <= conv_std_logic_vector(41675965,28); exponent <= conv_std_logic_vector(1740,11); WHEN "0111110010" => manhi <= conv_std_logic_vector(6334649,24); manlo <= conv_std_logic_vector(70777607,28); exponent <= conv_std_logic_vector(1741,11); WHEN "0111110011" => manhi <= conv_std_logic_vector(14635065,24); manlo <= conv_std_logic_vector(183612561,28); exponent <= conv_std_logic_vector(1742,11); WHEN "0111110100" => manhi <= conv_std_logic_vector(4569642,24); manlo <= conv_std_logic_vector(167240760,28); exponent <= conv_std_logic_vector(1744,11); WHEN "0111110101" => manhi <= conv_std_logic_vector(12236172,24); manlo <= conv_std_logic_vector(253623266,28); exponent <= conv_std_logic_vector(1745,11); WHEN "0111110110" => manhi <= conv_std_logic_vector(2939425,24); manlo <= conv_std_logic_vector(265128301,28); exponent <= conv_std_logic_vector(1747,11); WHEN "0111110111" => manhi <= conv_std_logic_vector(10020478,24); manlo <= conv_std_logic_vector(219223569,28); exponent <= conv_std_logic_vector(1748,11); WHEN "0111111000" => manhi <= conv_std_logic_vector(1433705,24); manlo <= conv_std_logic_vector(192250058,28); exponent <= conv_std_logic_vector(1750,11); WHEN "0111111001" => manhi <= conv_std_logic_vector(7973992,24); manlo <= conv_std_logic_vector(212144821,28); exponent <= conv_std_logic_vector(1751,11); WHEN "0111111010" => manhi <= conv_std_logic_vector(42974,24); manlo <= conv_std_logic_vector(72952107,28); exponent <= conv_std_logic_vector(1753,11); WHEN "0111111011" => manhi <= conv_std_logic_vector(6083792,24); manlo <= conv_std_logic_vector(210315148,28); exponent <= conv_std_logic_vector(1754,11); WHEN "0111111100" => manhi <= conv_std_logic_vector(14294116,24); manlo <= conv_std_logic_vector(101520926,28); exponent <= conv_std_logic_vector(1755,11); WHEN "0111111101" => manhi <= conv_std_logic_vector(4337943,24); manlo <= conv_std_logic_vector(146945490,28); exponent <= conv_std_logic_vector(1757,11); WHEN "0111111110" => manhi <= conv_std_logic_vector(11921261,24); manlo <= conv_std_logic_vector(67478049,28); exponent <= conv_std_logic_vector(1758,11); WHEN "0111111111" => manhi <= conv_std_logic_vector(2725421,24); manlo <= conv_std_logic_vector(81662013,28); exponent <= conv_std_logic_vector(1760,11); WHEN "1000000000" => manhi <= conv_std_logic_vector(9729616,24); manlo <= conv_std_logic_vector(79332654,28); exponent <= conv_std_logic_vector(1761,11); WHEN "1000000001" => manhi <= conv_std_logic_vector(1236044,24); manlo <= conv_std_logic_vector(37511845,28); exponent <= conv_std_logic_vector(1763,11); WHEN "1000000010" => manhi <= conv_std_logic_vector(7705342,24); manlo <= conv_std_logic_vector(229400607,28); exponent <= conv_std_logic_vector(1764,11); WHEN "1000000011" => manhi <= conv_std_logic_vector(16498031,24); manlo <= conv_std_logic_vector(113896411,28); exponent <= conv_std_logic_vector(1765,11); WHEN "1000000100" => manhi <= conv_std_logic_vector(5835659,24); manlo <= conv_std_logic_vector(27578100,28); exponent <= conv_std_logic_vector(1767,11); WHEN "1000000101" => manhi <= conv_std_logic_vector(13956867,24); manlo <= conv_std_logic_vector(198774093,28); exponent <= conv_std_logic_vector(1768,11); WHEN "1000000110" => manhi <= conv_std_logic_vector(4108759,24); manlo <= conv_std_logic_vector(90336304,28); exponent <= conv_std_logic_vector(1770,11); WHEN "1000000111" => manhi <= conv_std_logic_vector(11609767,24); manlo <= conv_std_logic_vector(164675818,28); exponent <= conv_std_logic_vector(1771,11); WHEN "1000001000" => manhi <= conv_std_logic_vector(2513739,24); manlo <= conv_std_logic_vector(115510945,28); exponent <= conv_std_logic_vector(1773,11); WHEN "1000001001" => manhi <= conv_std_logic_vector(9441910,24); manlo <= conv_std_logic_vector(214725537,28); exponent <= conv_std_logic_vector(1774,11); WHEN "1000001010" => manhi <= conv_std_logic_vector(1040527,24); manlo <= conv_std_logic_vector(264292986,28); exponent <= conv_std_logic_vector(1776,11); WHEN "1000001011" => manhi <= conv_std_logic_vector(7439608,24); manlo <= conv_std_logic_vector(227819416,28); exponent <= conv_std_logic_vector(1777,11); WHEN "1000001100" => manhi <= conv_std_logic_vector(16136861,24); manlo <= conv_std_logic_vector(124712281,28); exponent <= conv_std_logic_vector(1778,11); WHEN "1000001101" => manhi <= conv_std_logic_vector(5590218,24); manlo <= conv_std_logic_vector(179347558,28); exponent <= conv_std_logic_vector(1780,11); WHEN "1000001110" => manhi <= conv_std_logic_vector(13623279,24); manlo <= conv_std_logic_vector(162081347,28); exponent <= conv_std_logic_vector(1781,11); WHEN "1000001111" => manhi <= conv_std_logic_vector(3882062,24); manlo <= conv_std_logic_vector(186291443,28); exponent <= conv_std_logic_vector(1783,11); WHEN "1000010000" => manhi <= conv_std_logic_vector(11301654,24); manlo <= conv_std_logic_vector(250040022,28); exponent <= conv_std_logic_vector(1784,11); WHEN "1000010001" => manhi <= conv_std_logic_vector(2304355,24); manlo <= conv_std_logic_vector(41383777,28); exponent <= conv_std_logic_vector(1786,11); WHEN "1000010010" => manhi <= conv_std_logic_vector(9157328,24); manlo <= conv_std_logic_vector(17021400,28); exponent <= conv_std_logic_vector(1787,11); WHEN "1000010011" => manhi <= conv_std_logic_vector(847133,24); manlo <= conv_std_logic_vector(258834653,28); exponent <= conv_std_logic_vector(1789,11); WHEN "1000010100" => manhi <= conv_std_logic_vector(7176759,24); manlo <= conv_std_logic_vector(33041815,28); exponent <= conv_std_logic_vector(1790,11); WHEN "1000010101" => manhi <= conv_std_logic_vector(15779611,24); manlo <= conv_std_logic_vector(174007449,28); exponent <= conv_std_logic_vector(1791,11); WHEN "1000010110" => manhi <= conv_std_logic_vector(5347442,24); manlo <= conv_std_logic_vector(66333886,28); exponent <= conv_std_logic_vector(1793,11); WHEN "1000010111" => manhi <= conv_std_logic_vector(13293312,24); manlo <= conv_std_logic_vector(63618366,28); exponent <= conv_std_logic_vector(1794,11); WHEN "1000011000" => manhi <= conv_std_logic_vector(3657826,24); manlo <= conv_std_logic_vector(166348998,28); exponent <= conv_std_logic_vector(1796,11); WHEN "1000011001" => manhi <= conv_std_logic_vector(10996886,24); manlo <= conv_std_logic_vector(136487624,28); exponent <= conv_std_logic_vector(1797,11); WHEN "1000011010" => manhi <= conv_std_logic_vector(2097243,24); manlo <= conv_std_logic_vector(144317262,28); exponent <= conv_std_logic_vector(1799,11); WHEN "1000011011" => manhi <= conv_std_logic_vector(8875834,24); manlo <= conv_std_logic_vector(51419886,28); exponent <= conv_std_logic_vector(1800,11); WHEN "1000011100" => manhi <= conv_std_logic_vector(655839,24); manlo <= conv_std_logic_vector(12096311,28); exponent <= conv_std_logic_vector(1802,11); WHEN "1000011101" => manhi <= conv_std_logic_vector(6916762,24); manlo <= conv_std_logic_vector(99793437,28); exponent <= conv_std_logic_vector(1803,11); WHEN "1000011110" => manhi <= conv_std_logic_vector(15426239,24); manlo <= conv_std_logic_vector(114334116,28); exponent <= conv_std_logic_vector(1804,11); WHEN "1000011111" => manhi <= conv_std_logic_vector(5107300,24); manlo <= conv_std_logic_vector(248161218,28); exponent <= conv_std_logic_vector(1806,11); WHEN "1000100000" => manhi <= conv_std_logic_vector(12966926,24); manlo <= conv_std_logic_vector(91321506,28); exponent <= conv_std_logic_vector(1807,11); WHEN "1000100001" => manhi <= conv_std_logic_vector(3436024,24); manlo <= conv_std_logic_vector(109150055,28); exponent <= conv_std_logic_vector(1809,11); WHEN "1000100010" => manhi <= conv_std_logic_vector(10695426,24); manlo <= conv_std_logic_vector(12291314,28); exponent <= conv_std_logic_vector(1810,11); WHEN "1000100011" => manhi <= conv_std_logic_vector(1892379,24); manlo <= conv_std_logic_vector(245137096,28); exponent <= conv_std_logic_vector(1812,11); WHEN "1000100100" => manhi <= conv_std_logic_vector(8597395,24); manlo <= conv_std_logic_vector(176569250,28); exponent <= conv_std_logic_vector(1813,11); WHEN "1000100101" => manhi <= conv_std_logic_vector(466620,24); manlo <= conv_std_logic_vector(119019308,28); exponent <= conv_std_logic_vector(1815,11); WHEN "1000100110" => manhi <= conv_std_logic_vector(6659587,24); manlo <= conv_std_logic_vector(168706814,28); exponent <= conv_std_logic_vector(1816,11); WHEN "1000100111" => manhi <= conv_std_logic_vector(15076702,24); manlo <= conv_std_logic_vector(190651618,28); exponent <= conv_std_logic_vector(1817,11); WHEN "1000101000" => manhi <= conv_std_logic_vector(4869766,24); manlo <= conv_std_logic_vector(26523901,28); exponent <= conv_std_logic_vector(1819,11); WHEN "1000101001" => manhi <= conv_std_logic_vector(12644083,24); manlo <= conv_std_logic_vector(10760420,28); exponent <= conv_std_logic_vector(1820,11); WHEN "1000101010" => manhi <= conv_std_logic_vector(3216629,24); manlo <= conv_std_logic_vector(171149379,28); exponent <= conv_std_logic_vector(1822,11); WHEN "1000101011" => manhi <= conv_std_logic_vector(10397237,24); manlo <= conv_std_logic_vector(171483537,28); exponent <= conv_std_logic_vector(1823,11); WHEN "1000101100" => manhi <= conv_std_logic_vector(1689739,24); manlo <= conv_std_logic_vector(236540182,28); exponent <= conv_std_logic_vector(1825,11); WHEN "1000101101" => manhi <= conv_std_logic_vector(8321979,24); manlo <= conv_std_logic_vector(80365386,28); exponent <= conv_std_logic_vector(1826,11); WHEN "1000101110" => manhi <= conv_std_logic_vector(279455,24); manlo <= conv_std_logic_vector(167185714,28); exponent <= conv_std_logic_vector(1828,11); WHEN "1000101111" => manhi <= conv_std_logic_vector(6405204,24); manlo <= conv_std_logic_vector(70637708,28); exponent <= conv_std_logic_vector(1829,11); WHEN "1000110000" => manhi <= conv_std_logic_vector(14730959,24); manlo <= conv_std_logic_vector(233674466,28); exponent <= conv_std_logic_vector(1830,11); WHEN "1000110001" => manhi <= conv_std_logic_vector(4634809,24); manlo <= conv_std_logic_vector(128626627,28); exponent <= conv_std_logic_vector(1832,11); WHEN "1000110010" => manhi <= conv_std_logic_vector(12324743,24); manlo <= conv_std_logic_vector(237637056,28); exponent <= conv_std_logic_vector(1833,11); WHEN "1000110011" => manhi <= conv_std_logic_vector(2999616,24); manlo <= conv_std_logic_vector(48899908,28); exponent <= conv_std_logic_vector(1835,11); WHEN "1000110100" => manhi <= conv_std_logic_vector(10102285,24); manlo <= conv_std_logic_vector(207402206,28); exponent <= conv_std_logic_vector(1836,11); WHEN "1000110101" => manhi <= conv_std_logic_vector(1489299,24); manlo <= conv_std_logic_vector(82314533,28); exponent <= conv_std_logic_vector(1838,11); WHEN "1000110110" => manhi <= conv_std_logic_vector(8049552,24); manlo <= conv_std_logic_vector(84197942,28); exponent <= conv_std_logic_vector(1839,11); WHEN "1000110111" => manhi <= conv_std_logic_vector(94322,24); manlo <= conv_std_logic_vector(78275083,28); exponent <= conv_std_logic_vector(1841,11); WHEN "1000111000" => manhi <= conv_std_logic_vector(6153581,24); manlo <= conv_std_logic_vector(262556746,28); exponent <= conv_std_logic_vector(1842,11); WHEN "1000111001" => manhi <= conv_std_logic_vector(14388969,24); manlo <= conv_std_logic_vector(195412276,28); exponent <= conv_std_logic_vector(1843,11); WHEN "1000111010" => manhi <= conv_std_logic_vector(4402403,24); manlo <= conv_std_logic_vector(21925377,28); exponent <= conv_std_logic_vector(1845,11); WHEN "1000111011" => manhi <= conv_std_logic_vector(12008870,24); manlo <= conv_std_logic_vector(225943576,28); exponent <= conv_std_logic_vector(1846,11); WHEN "1000111100" => manhi <= conv_std_logic_vector(2784958,24); manlo <= conv_std_logic_vector(51959162,28); exponent <= conv_std_logic_vector(1848,11); WHEN "1000111101" => manhi <= conv_std_logic_vector(9810535,24); manlo <= conv_std_logic_vector(85297068,28); exponent <= conv_std_logic_vector(1849,11); WHEN "1000111110" => manhi <= conv_std_logic_vector(1291034,24); manlo <= conv_std_logic_vector(85003113,28); exponent <= conv_std_logic_vector(1851,11); WHEN "1000111111" => manhi <= conv_std_logic_vector(7780082,24); manlo <= conv_std_logic_vector(68159752,28); exponent <= conv_std_logic_vector(1852,11); WHEN "1001000000" => manhi <= conv_std_logic_vector(16599612,24); manlo <= conv_std_logic_vector(214703512,28); exponent <= conv_std_logic_vector(1853,11); WHEN "1001000001" => manhi <= conv_std_logic_vector(5904690,24); manlo <= conv_std_logic_vector(215968023,28); exponent <= conv_std_logic_vector(1855,11); WHEN "1001000010" => manhi <= conv_std_logic_vector(14050691,24); manlo <= conv_std_logic_vector(147853227,28); exponent <= conv_std_logic_vector(1856,11); WHEN "1001000011" => manhi <= conv_std_logic_vector(4172519,24); manlo <= conv_std_logic_vector(60716388,28); exponent <= conv_std_logic_vector(1858,11); WHEN "1001000100" => manhi <= conv_std_logic_vector(11696426,24); manlo <= conv_std_logic_vector(77359100,28); exponent <= conv_std_logic_vector(1859,11); WHEN "1001000101" => manhi <= conv_std_logic_vector(2572630,24); manlo <= conv_std_logic_vector(28321055,28); exponent <= conv_std_logic_vector(1861,11); WHEN "1001000110" => manhi <= conv_std_logic_vector(9521951,24); manlo <= conv_std_logic_vector(141206574,28); exponent <= conv_std_logic_vector(1862,11); WHEN "1001000111" => manhi <= conv_std_logic_vector(1094921,24); manlo <= conv_std_logic_vector(79834212,28); exponent <= conv_std_logic_vector(1864,11); WHEN "1001001000" => manhi <= conv_std_logic_vector(7513537,24); manlo <= conv_std_logic_vector(6880382,28); exponent <= conv_std_logic_vector(1865,11); WHEN "1001001001" => manhi <= conv_std_logic_vector(16237340,24); manlo <= conv_std_logic_vector(73707069,28); exponent <= conv_std_logic_vector(1866,11); WHEN "1001001010" => manhi <= conv_std_logic_vector(5658501,24); manlo <= conv_std_logic_vector(26563701,28); exponent <= conv_std_logic_vector(1868,11); WHEN "1001001011" => manhi <= conv_std_logic_vector(13716085,24); manlo <= conv_std_logic_vector(13226359,28); exponent <= conv_std_logic_vector(1869,11); WHEN "1001001100" => manhi <= conv_std_logic_vector(3945130,24); manlo <= conv_std_logic_vector(143073903,28); exponent <= conv_std_logic_vector(1871,11); WHEN "1001001101" => manhi <= conv_std_logic_vector(11387373,24); manlo <= conv_std_logic_vector(3175990,28); exponent <= conv_std_logic_vector(1872,11); WHEN "1001001110" => manhi <= conv_std_logic_vector(2362606,24); manlo <= conv_std_logic_vector(168904878,28); exponent <= conv_std_logic_vector(1874,11); WHEN "1001001111" => manhi <= conv_std_logic_vector(9236500,24); manlo <= conv_std_logic_vector(7105104,28); exponent <= conv_std_logic_vector(1875,11); WHEN "1001010000" => manhi <= conv_std_logic_vector(900936,24); manlo <= conv_std_logic_vector(239272854,28); exponent <= conv_std_logic_vector(1877,11); WHEN "1001010001" => manhi <= conv_std_logic_vector(7249884,24); manlo <= conv_std_logic_vector(236935482,28); exponent <= conv_std_logic_vector(1878,11); WHEN "1001010010" => manhi <= conv_std_logic_vector(15878999,24); manlo <= conv_std_logic_vector(230836932,28); exponent <= conv_std_logic_vector(1879,11); WHEN "1001010011" => manhi <= conv_std_logic_vector(5414983,24); manlo <= conv_std_logic_vector(144840810,28); exponent <= conv_std_logic_vector(1881,11); WHEN "1001010100" => manhi <= conv_std_logic_vector(13385110,24); manlo <= conv_std_logic_vector(99584369,28); exponent <= conv_std_logic_vector(1882,11); WHEN "1001010101" => manhi <= conv_std_logic_vector(3720209,24); manlo <= conv_std_logic_vector(246845719,28); exponent <= conv_std_logic_vector(1884,11); WHEN "1001010110" => manhi <= conv_std_logic_vector(11081674,24); manlo <= conv_std_logic_vector(54674652,28); exponent <= conv_std_logic_vector(1885,11); WHEN "1001010111" => manhi <= conv_std_logic_vector(2154862,24); manlo <= conv_std_logic_vector(201440422,28); exponent <= conv_std_logic_vector(1887,11); WHEN "1001011000" => manhi <= conv_std_logic_vector(8954146,24); manlo <= conv_std_logic_vector(220416825,28); exponent <= conv_std_logic_vector(1888,11); WHEN "1001011001" => manhi <= conv_std_logic_vector(709057,24); manlo <= conv_std_logic_vector(266967657,28); exponent <= conv_std_logic_vector(1890,11); WHEN "1001011010" => manhi <= conv_std_logic_vector(6989094,24); manlo <= conv_std_logic_vector(113654547,28); exponent <= conv_std_logic_vector(1891,11); WHEN "1001011011" => manhi <= conv_std_logic_vector(15524548,24); manlo <= conv_std_logic_vector(235342013,28); exponent <= conv_std_logic_vector(1892,11); WHEN "1001011100" => manhi <= conv_std_logic_vector(5174109,24); manlo <= conv_std_logic_vector(32986511,28); exponent <= conv_std_logic_vector(1894,11); WHEN "1001011101" => manhi <= conv_std_logic_vector(13057728,24); manlo <= conv_std_logic_vector(25787653,28); exponent <= conv_std_logic_vector(1895,11); WHEN "1001011110" => manhi <= conv_std_logic_vector(3497730,24); manlo <= conv_std_logic_vector(160351868,28); exponent <= conv_std_logic_vector(1897,11); WHEN "1001011111" => manhi <= conv_std_logic_vector(10779293,24); manlo <= conv_std_logic_vector(121946709,28); exponent <= conv_std_logic_vector(1898,11); WHEN "1001100000" => manhi <= conv_std_logic_vector(1949373,24); manlo <= conv_std_logic_vector(194974600,28); exponent <= conv_std_logic_vector(1900,11); WHEN "1001100001" => manhi <= conv_std_logic_vector(8674858,24); manlo <= conv_std_logic_vector(75445083,28); exponent <= conv_std_logic_vector(1901,11); WHEN "1001100010" => manhi <= conv_std_logic_vector(519261,24); manlo <= conv_std_logic_vector(202318540,28); exponent <= conv_std_logic_vector(1903,11); WHEN "1001100011" => manhi <= conv_std_logic_vector(6731134,24); manlo <= conv_std_logic_vector(157600610,28); exponent <= conv_std_logic_vector(1904,11); WHEN "1001100100" => manhi <= conv_std_logic_vector(15173945,24); manlo <= conv_std_logic_vector(29256816,28); exponent <= conv_std_logic_vector(1905,11); WHEN "1001100101" => manhi <= conv_std_logic_vector(4935849,24); manlo <= conv_std_logic_vector(42999013,28); exponent <= conv_std_logic_vector(1907,11); WHEN "1001100110" => manhi <= conv_std_logic_vector(12733899,24); manlo <= conv_std_logic_vector(62421287,28); exponent <= conv_std_logic_vector(1908,11); WHEN "1001100111" => manhi <= conv_std_logic_vector(3277666,24); manlo <= conv_std_logic_vector(18399062,28); exponent <= conv_std_logic_vector(1910,11); WHEN "1001101000" => manhi <= conv_std_logic_vector(10480194,24); manlo <= conv_std_logic_vector(201166396,28); exponent <= conv_std_logic_vector(1911,11); WHEN "1001101001" => manhi <= conv_std_logic_vector(1746115,24); manlo <= conv_std_logic_vector(22209480,28); exponent <= conv_std_logic_vector(1913,11); WHEN "1001101010" => manhi <= conv_std_logic_vector(8398601,24); manlo <= conv_std_logic_vector(38216343,28); exponent <= conv_std_logic_vector(1914,11); WHEN "1001101011" => manhi <= conv_std_logic_vector(331525,24); manlo <= conv_std_logic_vector(151310615,28); exponent <= conv_std_logic_vector(1916,11); WHEN "1001101100" => manhi <= conv_std_logic_vector(6475974,24); manlo <= conv_std_logic_vector(174528998,28); exponent <= conv_std_logic_vector(1917,11); WHEN "1001101101" => manhi <= conv_std_logic_vector(14827146,24); manlo <= conv_std_logic_vector(214487191,28); exponent <= conv_std_logic_vector(1918,11); WHEN "1001101110" => manhi <= conv_std_logic_vector(4700175,24); manlo <= conv_std_logic_vector(73593076,28); exponent <= conv_std_logic_vector(1920,11); WHEN "1001101111" => manhi <= conv_std_logic_vector(12413585,24); manlo <= conv_std_logic_vector(56806573,28); exponent <= conv_std_logic_vector(1921,11); WHEN "1001110000" => manhi <= conv_std_logic_vector(3059990,24); manlo <= conv_std_logic_vector(32998071,28); exponent <= conv_std_logic_vector(1923,11); WHEN "1001110001" => manhi <= conv_std_logic_vector(10184342,24); manlo <= conv_std_logic_vector(125003687,28); exponent <= conv_std_logic_vector(1924,11); WHEN "1001110010" => manhi <= conv_std_logic_vector(1545062,24); manlo <= conv_std_logic_vector(164026180,28); exponent <= conv_std_logic_vector(1926,11); WHEN "1001110011" => manhi <= conv_std_logic_vector(8125342,24); manlo <= conv_std_logic_vector(134803968,28); exponent <= conv_std_logic_vector(1927,11); WHEN "1001110100" => manhi <= conv_std_logic_vector(145827,24); manlo <= conv_std_logic_vector(17356019,28); exponent <= conv_std_logic_vector(1929,11); WHEN "1001110101" => manhi <= conv_std_logic_vector(6223584,24); manlo <= conv_std_logic_vector(59711433,28); exponent <= conv_std_logic_vector(1930,11); WHEN "1001110110" => manhi <= conv_std_logic_vector(14484112,24); manlo <= conv_std_logic_vector(172427100,28); exponent <= conv_std_logic_vector(1931,11); WHEN "1001110111" => manhi <= conv_std_logic_vector(4467059,24); manlo <= conv_std_logic_vector(106163660,28); exponent <= conv_std_logic_vector(1933,11); WHEN "1001111000" => manhi <= conv_std_logic_vector(12096747,24); manlo <= conv_std_logic_vector(237074316,28); exponent <= conv_std_logic_vector(1934,11); WHEN "1001111001" => manhi <= conv_std_logic_vector(2844676,24); manlo <= conv_std_logic_vector(224090291,28); exponent <= conv_std_logic_vector(1936,11); WHEN "1001111010" => manhi <= conv_std_logic_vector(9891701,24); manlo <= conv_std_logic_vector(98356275,28); exponent <= conv_std_logic_vector(1937,11); WHEN "1001111011" => manhi <= conv_std_logic_vector(1346192,24); manlo <= conv_std_logic_vector(98098154,28); exponent <= conv_std_logic_vector(1939,11); WHEN "1001111100" => manhi <= conv_std_logic_vector(7855049,24); manlo <= conv_std_logic_vector(218711727,28); exponent <= conv_std_logic_vector(1940,11); WHEN "1001111101" => manhi <= conv_std_logic_vector(16701504,24); manlo <= conv_std_logic_vector(74899902,28); exponent <= conv_std_logic_vector(1941,11); WHEN "1001111110" => manhi <= conv_std_logic_vector(5973933,24); manlo <= conv_std_logic_vector(65399866,28); exponent <= conv_std_logic_vector(1943,11); WHEN "1001111111" => manhi <= conv_std_logic_vector(14144801,24); manlo <= conv_std_logic_vector(210121699,28); exponent <= conv_std_logic_vector(1944,11); WHEN "1010000000" => manhi <= conv_std_logic_vector(4236473,24); manlo <= conv_std_logic_vector(203888522,28); exponent <= conv_std_logic_vector(1946,11); WHEN "1010000001" => manhi <= conv_std_logic_vector(11783349,24); manlo <= conv_std_logic_vector(137203293,28); exponent <= conv_std_logic_vector(1947,11); WHEN "1010000010" => manhi <= conv_std_logic_vector(2631700,24); manlo <= conv_std_logic_vector(150283410,28); exponent <= conv_std_logic_vector(1949,11); WHEN "1010000011" => manhi <= conv_std_logic_vector(9602236,24); manlo <= conv_std_logic_vector(160352104,28); exponent <= conv_std_logic_vector(1950,11); WHEN "1010000100" => manhi <= conv_std_logic_vector(1149480,24); manlo <= conv_std_logic_vector(177173803,28); exponent <= conv_std_logic_vector(1952,11); WHEN "1010000101" => manhi <= conv_std_logic_vector(7587690,24); manlo <= conv_std_logic_vector(238268718,28); exponent <= conv_std_logic_vector(1953,11); WHEN "1010000110" => manhi <= conv_std_logic_vector(16338125,24); manlo <= conv_std_logic_vector(220749839,28); exponent <= conv_std_logic_vector(1954,11); WHEN "1010000111" => manhi <= conv_std_logic_vector(5726991,24); manlo <= conv_std_logic_vector(262994505,28); exponent <= conv_std_logic_vector(1956,11); WHEN "1010001000" => manhi <= conv_std_logic_vector(13809173,24); manlo <= conv_std_logic_vector(216783842,28); exponent <= conv_std_logic_vector(1957,11); WHEN "1010001001" => manhi <= conv_std_logic_vector(4008390,24); manlo <= conv_std_logic_vector(242405077,28); exponent <= conv_std_logic_vector(1959,11); WHEN "1010001010" => manhi <= conv_std_logic_vector(11473352,24); manlo <= conv_std_logic_vector(206426515,28); exponent <= conv_std_logic_vector(1960,11); WHEN "1010001011" => manhi <= conv_std_logic_vector(2421035,24); manlo <= conv_std_logic_vector(250208807,28); exponent <= conv_std_logic_vector(1962,11); WHEN "1010001100" => manhi <= conv_std_logic_vector(9315913,24); manlo <= conv_std_logic_vector(183235034,28); exponent <= conv_std_logic_vector(1963,11); WHEN "1010001101" => manhi <= conv_std_logic_vector(954904,24); manlo <= conv_std_logic_vector(17706469,28); exponent <= conv_std_logic_vector(1965,11); WHEN "1010001110" => manhi <= conv_std_logic_vector(7323233,24); manlo <= conv_std_logic_vector(235600136,28); exponent <= conv_std_logic_vector(1966,11); WHEN "1010001111" => manhi <= conv_std_logic_vector(15978691,24); manlo <= conv_std_logic_vector(128873524,28); exponent <= conv_std_logic_vector(1967,11); WHEN "1010010000" => manhi <= conv_std_logic_vector(5482731,24); manlo <= conv_std_logic_vector(5222268,28); exponent <= conv_std_logic_vector(1969,11); WHEN "1010010001" => manhi <= conv_std_logic_vector(13477188,24); manlo <= conv_std_logic_vector(199372940,28); exponent <= conv_std_logic_vector(1970,11); WHEN "1010010010" => manhi <= conv_std_logic_vector(3782783,24); manlo <= conv_std_logic_vector(177367827,28); exponent <= conv_std_logic_vector(1972,11); WHEN "1010010011" => manhi <= conv_std_logic_vector(11166720,24); manlo <= conv_std_logic_vector(197425116,28); exponent <= conv_std_logic_vector(1973,11); WHEN "1010010100" => manhi <= conv_std_logic_vector(2212657,24); manlo <= conv_std_logic_vector(231097832,28); exponent <= conv_std_logic_vector(1975,11); WHEN "1010010101" => manhi <= conv_std_logic_vector(9032698,24); manlo <= conv_std_logic_vector(139698050,28); exponent <= conv_std_logic_vector(1976,11); WHEN "1010010110" => manhi <= conv_std_logic_vector(762439,24); manlo <= conv_std_logic_vector(109718127,28); exponent <= conv_std_logic_vector(1978,11); WHEN "1010010111" => manhi <= conv_std_logic_vector(7061647,24); manlo <= conv_std_logic_vector(77173752,28); exponent <= conv_std_logic_vector(1979,11); WHEN "1010011000" => manhi <= conv_std_logic_vector(15623158,24); manlo <= conv_std_logic_vector(118851961,28); exponent <= conv_std_logic_vector(1980,11); WHEN "1010011001" => manhi <= conv_std_logic_vector(5241121,24); manlo <= conv_std_logic_vector(72680114,28); exponent <= conv_std_logic_vector(1982,11); WHEN "1010011010" => manhi <= conv_std_logic_vector(13148807,24); manlo <= conv_std_logic_vector(12881486,28); exponent <= conv_std_logic_vector(1983,11); WHEN "1010011011" => manhi <= conv_std_logic_vector(3559625,24); manlo <= conv_std_logic_vector(43579850,28); exponent <= conv_std_logic_vector(1985,11); WHEN "1010011100" => manhi <= conv_std_logic_vector(10863416,24); manlo <= conv_std_logic_vector(238889758,28); exponent <= conv_std_logic_vector(1986,11); WHEN "1010011101" => manhi <= conv_std_logic_vector(2006541,24); manlo <= conv_std_logic_vector(141721451,28); exponent <= conv_std_logic_vector(1988,11); WHEN "1010011110" => manhi <= conv_std_logic_vector(8752557,24); manlo <= conv_std_logic_vector(101792997,28); exponent <= conv_std_logic_vector(1989,11); WHEN "1010011111" => manhi <= conv_std_logic_vector(572063,24); manlo <= conv_std_logic_vector(205445723,28); exponent <= conv_std_logic_vector(1991,11); WHEN "1010100000" => manhi <= conv_std_logic_vector(6802899,24); manlo <= conv_std_logic_vector(258099270,28); exponent <= conv_std_logic_vector(1992,11); WHEN "1010100001" => manhi <= conv_std_logic_vector(15271484,24); manlo <= conv_std_logic_vector(98124990,28); exponent <= conv_std_logic_vector(1993,11); WHEN "1010100010" => manhi <= conv_std_logic_vector(5002133,24); manlo <= conv_std_logic_vector(256985826,28); exponent <= conv_std_logic_vector(1995,11); WHEN "1010100011" => manhi <= conv_std_logic_vector(12823989,24); manlo <= conv_std_logic_vector(164377270,28); exponent <= conv_std_logic_vector(1996,11); WHEN "1010100100" => manhi <= conv_std_logic_vector(3338888,24); manlo <= conv_std_logic_vector(222569178,28); exponent <= conv_std_logic_vector(1998,11); WHEN "1010100101" => manhi <= conv_std_logic_vector(10563405,24); manlo <= conv_std_logic_vector(29046646,28); exponent <= conv_std_logic_vector(1999,11); WHEN "1010100110" => manhi <= conv_std_logic_vector(1802662,24); manlo <= conv_std_logic_vector(103161316,28); exponent <= conv_std_logic_vector(2001,11); WHEN "1010100111" => manhi <= conv_std_logic_vector(8475456,24); manlo <= conv_std_logic_vector(239852126,28); exponent <= conv_std_logic_vector(2002,11); WHEN "1010101000" => manhi <= conv_std_logic_vector(383754,24); manlo <= conv_std_logic_vector(123914668,28); exponent <= conv_std_logic_vector(2004,11); WHEN "1010101001" => manhi <= conv_std_logic_vector(6546961,24); manlo <= conv_std_logic_vector(22084044,28); exponent <= conv_std_logic_vector(2005,11); WHEN "1010101010" => manhi <= conv_std_logic_vector(14923627,24); manlo <= conv_std_logic_vector(97508377,28); exponent <= conv_std_logic_vector(2006,11); WHEN "1010101011" => manhi <= conv_std_logic_vector(4765740,24); manlo <= conv_std_logic_vector(165164368,28); exponent <= conv_std_logic_vector(2008,11); WHEN "1010101100" => manhi <= conv_std_logic_vector(12502697,24); manlo <= conv_std_logic_vector(201140216,28); exponent <= conv_std_logic_vector(2009,11); WHEN "1010101101" => manhi <= conv_std_logic_vector(3120548,24); manlo <= conv_std_logic_vector(99561759,28); exponent <= conv_std_logic_vector(2011,11); WHEN "1010101110" => manhi <= conv_std_logic_vector(10266649,24); manlo <= conv_std_logic_vector(176679877,28); exponent <= conv_std_logic_vector(2012,11); WHEN "1010101111" => manhi <= conv_std_logic_vector(1600996,24); manlo <= conv_std_logic_vector(39589446,28); exponent <= conv_std_logic_vector(2014,11); WHEN "1010110000" => manhi <= conv_std_logic_vector(8201364,24); manlo <= conv_std_logic_vector(16114999,28); exponent <= conv_std_logic_vector(2015,11); WHEN "1010110001" => manhi <= conv_std_logic_vector(197489,24); manlo <= conv_std_logic_vector(18649371,28); exponent <= conv_std_logic_vector(2017,11); WHEN "1010110010" => manhi <= conv_std_logic_vector(6293800,24); manlo <= conv_std_logic_vector(44802372,28); exponent <= conv_std_logic_vector(2018,11); WHEN "1010110011" => manhi <= conv_std_logic_vector(14579546,24); manlo <= conv_std_logic_vector(1419236,28); exponent <= conv_std_logic_vector(2019,11); WHEN "1010110100" => manhi <= conv_std_logic_vector(4531913,24); manlo <= conv_std_logic_vector(24044223,28); exponent <= conv_std_logic_vector(2021,11); WHEN "1010110101" => manhi <= conv_std_logic_vector(12184893,24); manlo <= conv_std_logic_vector(51602800,28); exponent <= conv_std_logic_vector(2022,11); WHEN "1010110110" => manhi <= conv_std_logic_vector(2904577,24); manlo <= conv_std_logic_vector(210124577,28); exponent <= conv_std_logic_vector(2024,11); WHEN "1010110111" => manhi <= conv_std_logic_vector(9973115,24); manlo <= conv_std_logic_vector(52505388,28); exponent <= conv_std_logic_vector(2025,11); WHEN "1010111000" => manhi <= conv_std_logic_vector(1401518,24); manlo <= conv_std_logic_vector(214362802,28); exponent <= conv_std_logic_vector(2027,11); WHEN "1010111001" => manhi <= conv_std_logic_vector(7930246,24); manlo <= conv_std_logic_vector(62721516,28); exponent <= conv_std_logic_vector(2028,11); WHEN "1010111010" => manhi <= conv_std_logic_vector(13245,24); manlo <= conv_std_logic_vector(108520727,28); exponent <= conv_std_logic_vector(2030,11); WHEN "1010111011" => manhi <= conv_std_logic_vector(6043387,24); manlo <= conv_std_logic_vector(17001813,28); exponent <= conv_std_logic_vector(2031,11); WHEN "1010111100" => manhi <= conv_std_logic_vector(14239199,24); manlo <= conv_std_logic_vector(83422350,28); exponent <= conv_std_logic_vector(2032,11); WHEN "1010111101" => manhi <= conv_std_logic_vector(4300623,24); manlo <= conv_std_logic_vector(142486326,28); exponent <= conv_std_logic_vector(2034,11); WHEN "1010111110" => manhi <= conv_std_logic_vector(11870538,24); manlo <= conv_std_logic_vector(24126621,28); exponent <= conv_std_logic_vector(2035,11); WHEN "1010111111" => manhi <= conv_std_logic_vector(2690951,24); manlo <= conv_std_logic_vector(91850592,28); exponent <= conv_std_logic_vector(2037,11); WHEN "1011000000" => manhi <= conv_std_logic_vector(9682766,24); manlo <= conv_std_logic_vector(203960059,28); exponent <= conv_std_logic_vector(2038,11); WHEN "1011000001" => manhi <= conv_std_logic_vector(1204206,24); manlo <= conv_std_logic_vector(155513539,28); exponent <= conv_std_logic_vector(2040,11); WHEN "1011000010" => manhi <= conv_std_logic_vector(7662071,24); manlo <= conv_std_logic_vector(33184566,28); exponent <= conv_std_logic_vector(2041,11); WHEN "1011000011" => manhi <= conv_std_logic_vector(16439219,24); manlo <= conv_std_logic_vector(11896414,28); exponent <= conv_std_logic_vector(2042,11); WHEN "1011000100" => manhi <= conv_std_logic_vector(5795691,24); manlo <= conv_std_logic_vector(254151921,28); exponent <= conv_std_logic_vector(2044,11); WHEN "1011000101" => manhi <= conv_std_logic_vector(13902546,24); manlo <= conv_std_logic_vector(199613595,28); exponent <= conv_std_logic_vector(2045,11); WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_explutpos IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_explutpos; ARCHITECTURE rtl OF dp_explutpos IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(1023,11); WHEN "0000000001" => manhi <= conv_std_logic_vector(6025384,24); manlo <= conv_std_logic_vector(185882474,28); exponent <= conv_std_logic_vector(1024,11); WHEN "0000000010" => manhi <= conv_std_logic_vector(14214731,24); manlo <= conv_std_logic_vector(148168110,28); exponent <= conv_std_logic_vector(1025,11); WHEN "0000000011" => manhi <= conv_std_logic_vector(4283995,24); manlo <= conv_std_logic_vector(258978054,28); exponent <= conv_std_logic_vector(1027,11); WHEN "0000000100" => manhi <= conv_std_logic_vector(11847938,24); manlo <= conv_std_logic_vector(237451864,28); exponent <= conv_std_logic_vector(1028,11); WHEN "0000000101" => manhi <= conv_std_logic_vector(2675593,24); manlo <= conv_std_logic_vector(158348175,28); exponent <= conv_std_logic_vector(1030,11); WHEN "0000000110" => manhi <= conv_std_logic_vector(9661893,24); manlo <= conv_std_logic_vector(110149775,28); exponent <= conv_std_logic_vector(1031,11); WHEN "0000000111" => manhi <= conv_std_logic_vector(1190021,24); manlo <= conv_std_logic_vector(179232170,28); exponent <= conv_std_logic_vector(1033,11); WHEN "0000001000" => manhi <= conv_std_logic_vector(7642791,24); manlo <= conv_std_logic_vector(222760046,28); exponent <= conv_std_logic_vector(1034,11); WHEN "0000001001" => manhi <= conv_std_logic_vector(16413015,24); manlo <= conv_std_logic_vector(205983618,28); exponent <= conv_std_logic_vector(1035,11); WHEN "0000001010" => manhi <= conv_std_logic_vector(5777884,24); manlo <= conv_std_logic_vector(261424480,28); exponent <= conv_std_logic_vector(1037,11); WHEN "0000001011" => manhi <= conv_std_logic_vector(13878344,24); manlo <= conv_std_logic_vector(149835647,28); exponent <= conv_std_logic_vector(1038,11); WHEN "0000001100" => manhi <= conv_std_logic_vector(4055397,24); manlo <= conv_std_logic_vector(80968858,28); exponent <= conv_std_logic_vector(1040,11); WHEN "0000001101" => manhi <= conv_std_logic_vector(11537241,24); manlo <= conv_std_logic_vector(23775573,28); exponent <= conv_std_logic_vector(1041,11); WHEN "0000001110" => manhi <= conv_std_logic_vector(2464452,24); manlo <= conv_std_logic_vector(146736599,28); exponent <= conv_std_logic_vector(1043,11); WHEN "0000001111" => manhi <= conv_std_logic_vector(9374922,24); manlo <= conv_std_logic_vector(263006855,28); exponent <= conv_std_logic_vector(1044,11); WHEN "0000010000" => manhi <= conv_std_logic_vector(995005,24); manlo <= conv_std_logic_vector(11010080,28); exponent <= conv_std_logic_vector(1046,11); WHEN "0000010001" => manhi <= conv_std_logic_vector(7377736,24); manlo <= conv_std_logic_vector(202286329,28); exponent <= conv_std_logic_vector(1047,11); WHEN "0000010010" => manhi <= conv_std_logic_vector(16052768,24); manlo <= conv_std_logic_vector(152649917,28); exponent <= conv_std_logic_vector(1048,11); WHEN "0000010011" => manhi <= conv_std_logic_vector(5533071,24); manlo <= conv_std_logic_vector(166536930,28); exponent <= conv_std_logic_vector(1050,11); WHEN "0000010100" => manhi <= conv_std_logic_vector(13545608,24); manlo <= conv_std_logic_vector(191424516,28); exponent <= conv_std_logic_vector(1051,11); WHEN "0000010101" => manhi <= conv_std_logic_vector(3829279,24); manlo <= conv_std_logic_vector(228519165,28); exponent <= conv_std_logic_vector(1053,11); WHEN "0000010110" => manhi <= conv_std_logic_vector(11229915,24); manlo <= conv_std_logic_vector(163853824,28); exponent <= conv_std_logic_vector(1054,11); WHEN "0000010111" => manhi <= conv_std_logic_vector(2255603,24); manlo <= conv_std_logic_vector(61996481,28); exponent <= conv_std_logic_vector(1056,11); WHEN "0000011000" => manhi <= conv_std_logic_vector(9091067,24); manlo <= conv_std_logic_vector(88563639,28); exponent <= conv_std_logic_vector(1057,11); WHEN "0000011001" => manhi <= conv_std_logic_vector(802105,24); manlo <= conv_std_logic_vector(34169545,28); exponent <= conv_std_logic_vector(1059,11); WHEN "0000011010" => manhi <= conv_std_logic_vector(7115558,24); manlo <= conv_std_logic_vector(157969244,28); exponent <= conv_std_logic_vector(1060,11); WHEN "0000011011" => manhi <= conv_std_logic_vector(15696431,24); manlo <= conv_std_logic_vector(133591837,28); exponent <= conv_std_logic_vector(1061,11); WHEN "0000011100" => manhi <= conv_std_logic_vector(5290915,24); manlo <= conv_std_logic_vector(127285146,28); exponent <= conv_std_logic_vector(1063,11); WHEN "0000011101" => manhi <= conv_std_logic_vector(13216484,24); manlo <= conv_std_logic_vector(103923798,28); exponent <= conv_std_logic_vector(1064,11); WHEN "0000011110" => manhi <= conv_std_logic_vector(3605616,24); manlo <= conv_std_logic_vector(183249133,28); exponent <= conv_std_logic_vector(1066,11); WHEN "0000011111" => manhi <= conv_std_logic_vector(10925925,24); manlo <= conv_std_logic_vector(227336045,28); exponent <= conv_std_logic_vector(1067,11); WHEN "0000100000" => manhi <= conv_std_logic_vector(2049020,24); manlo <= conv_std_logic_vector(206267948,28); exponent <= conv_std_logic_vector(1069,11); WHEN "0000100001" => manhi <= conv_std_logic_vector(8810292,24); manlo <= conv_std_logic_vector(175265666,28); exponent <= conv_std_logic_vector(1070,11); WHEN "0000100010" => manhi <= conv_std_logic_vector(611298,24); manlo <= conv_std_logic_vector(255467255,28); exponent <= conv_std_logic_vector(1072,11); WHEN "0000100011" => manhi <= conv_std_logic_vector(6856226,24); manlo <= conv_std_logic_vector(29134171,28); exponent <= conv_std_logic_vector(1073,11); WHEN "0000100100" => manhi <= conv_std_logic_vector(15343962,24); manlo <= conv_std_logic_vector(30543222,28); exponent <= conv_std_logic_vector(1074,11); WHEN "0000100101" => manhi <= conv_std_logic_vector(5051387,24); manlo <= conv_std_logic_vector(186253338,28); exponent <= conv_std_logic_vector(1076,11); WHEN "0000100110" => manhi <= conv_std_logic_vector(12890932,24); manlo <= conv_std_logic_vector(102222951,28); exponent <= conv_std_logic_vector(1077,11); WHEN "0000100111" => manhi <= conv_std_logic_vector(3384381,24); manlo <= conv_std_logic_vector(42116377,28); exponent <= conv_std_logic_vector(1079,11); WHEN "0000101000" => manhi <= conv_std_logic_vector(10625235,24); manlo <= conv_std_logic_vector(158954218,28); exponent <= conv_std_logic_vector(1080,11); WHEN "0000101001" => manhi <= conv_std_logic_vector(1844680,24); manlo <= conv_std_logic_vector(148858978,28); exponent <= conv_std_logic_vector(1082,11); WHEN "0000101010" => manhi <= conv_std_logic_vector(8532565,24); manlo <= conv_std_logic_vector(136319321,28); exponent <= conv_std_logic_vector(1083,11); WHEN "0000101011" => manhi <= conv_std_logic_vector(422563,24); manlo <= conv_std_logic_vector(211728497,28); exponent <= conv_std_logic_vector(1085,11); WHEN "0000101100" => manhi <= conv_std_logic_vector(6599708,24); manlo <= conv_std_logic_vector(114522162,28); exponent <= conv_std_logic_vector(1086,11); WHEN "0000101101" => manhi <= conv_std_logic_vector(14995318,24); manlo <= conv_std_logic_vector(117328318,28); exponent <= conv_std_logic_vector(1087,11); WHEN "0000101110" => manhi <= conv_std_logic_vector(4814459,24); manlo <= conv_std_logic_vector(201622499,28); exponent <= conv_std_logic_vector(1089,11); WHEN "0000101111" => manhi <= conv_std_logic_vector(12568913,24); manlo <= conv_std_logic_vector(246987638,28); exponent <= conv_std_logic_vector(1090,11); WHEN "0000110000" => manhi <= conv_std_logic_vector(3165546,24); manlo <= conv_std_logic_vector(248128843,28); exponent <= conv_std_logic_vector(1092,11); WHEN "0000110001" => manhi <= conv_std_logic_vector(10327809,24); manlo <= conv_std_logic_vector(8929872,28); exponent <= conv_std_logic_vector(1093,11); WHEN "0000110010" => manhi <= conv_std_logic_vector(1642558,24); manlo <= conv_std_logic_vector(67636037,28); exponent <= conv_std_logic_vector(1095,11); WHEN "0000110011" => manhi <= conv_std_logic_vector(8257852,24); manlo <= conv_std_logic_vector(219235425,28); exponent <= conv_std_logic_vector(1096,11); WHEN "0000110100" => manhi <= conv_std_logic_vector(235877,24); manlo <= conv_std_logic_vector(42862412,28); exponent <= conv_std_logic_vector(1098,11); WHEN "0000110101" => manhi <= conv_std_logic_vector(6345974,24); manlo <= conv_std_logic_vector(265996080,28); exponent <= conv_std_logic_vector(1099,11); WHEN "0000110110" => manhi <= conv_std_logic_vector(14650458,24); manlo <= conv_std_logic_vector(253213243,28); exponent <= conv_std_logic_vector(1100,11); WHEN "0000110111" => manhi <= conv_std_logic_vector(4580103,24); manlo <= conv_std_logic_vector(114693785,28); exponent <= conv_std_logic_vector(1102,11); WHEN "0000111000" => manhi <= conv_std_logic_vector(12250390,24); manlo <= conv_std_logic_vector(174984615,28); exponent <= conv_std_logic_vector(1103,11); WHEN "0000111001" => manhi <= conv_std_logic_vector(2949087,24); manlo <= conv_std_logic_vector(247325089,28); exponent <= conv_std_logic_vector(1105,11); WHEN "0000111010" => manhi <= conv_std_logic_vector(10033610,24); manlo <= conv_std_logic_vector(200264553,28); exponent <= conv_std_logic_vector(1106,11); WHEN "0000111011" => manhi <= conv_std_logic_vector(1442629,24); manlo <= conv_std_logic_vector(211375075,28); exponent <= conv_std_logic_vector(1108,11); WHEN "0000111100" => manhi <= conv_std_logic_vector(7986121,24); manlo <= conv_std_logic_vector(231029862,28); exponent <= conv_std_logic_vector(1109,11); WHEN "0000111101" => manhi <= conv_std_logic_vector(51216,24); manlo <= conv_std_logic_vector(222707863,28); exponent <= conv_std_logic_vector(1111,11); WHEN "0000111110" => manhi <= conv_std_logic_vector(6094995,24); manlo <= conv_std_logic_vector(155999272,28); exponent <= conv_std_logic_vector(1112,11); WHEN "0000111111" => manhi <= conv_std_logic_vector(14309342,24); manlo <= conv_std_logic_vector(150013864,28); exponent <= conv_std_logic_vector(1113,11); WHEN "0001000000" => manhi <= conv_std_logic_vector(4348290,24); manlo <= conv_std_logic_vector(217421773,28); exponent <= conv_std_logic_vector(1115,11); WHEN "0001000001" => manhi <= conv_std_logic_vector(11935324,24); manlo <= conv_std_logic_vector(171597361,28); exponent <= conv_std_logic_vector(1116,11); WHEN "0001000010" => manhi <= conv_std_logic_vector(2734978,24); manlo <= conv_std_logic_vector(98553735,28); exponent <= conv_std_logic_vector(1118,11); WHEN "0001000011" => manhi <= conv_std_logic_vector(9742605,24); manlo <= conv_std_logic_vector(185429986,28); exponent <= conv_std_logic_vector(1119,11); WHEN "0001000100" => manhi <= conv_std_logic_vector(1244871,24); manlo <= conv_std_logic_vector(93685501,28); exponent <= conv_std_logic_vector(1121,11); WHEN "0001000101" => manhi <= conv_std_logic_vector(7717340,24); manlo <= conv_std_logic_vector(74048432,28); exponent <= conv_std_logic_vector(1122,11); WHEN "0001000110" => manhi <= conv_std_logic_vector(16514337,24); manlo <= conv_std_logic_vector(163855108,28); exponent <= conv_std_logic_vector(1123,11); WHEN "0001000111" => manhi <= conv_std_logic_vector(5846740,24); manlo <= conv_std_logic_vector(81895750,28); exponent <= conv_std_logic_vector(1125,11); WHEN "0001001000" => manhi <= conv_std_logic_vector(13971928,24); manlo <= conv_std_logic_vector(176088988,28); exponent <= conv_std_logic_vector(1126,11); WHEN "0001001001" => manhi <= conv_std_logic_vector(4118994,24); manlo <= conv_std_logic_vector(77780251,28); exponent <= conv_std_logic_vector(1128,11); WHEN "0001001010" => manhi <= conv_std_logic_vector(11623678,24); manlo <= conv_std_logic_vector(95871356,28); exponent <= conv_std_logic_vector(1129,11); WHEN "0001001011" => manhi <= conv_std_logic_vector(2523192,24); manlo <= conv_std_logic_vector(204213760,28); exponent <= conv_std_logic_vector(1131,11); WHEN "0001001100" => manhi <= conv_std_logic_vector(9454759,24); manlo <= conv_std_logic_vector(55860552,28); exponent <= conv_std_logic_vector(1132,11); WHEN "0001001101" => manhi <= conv_std_logic_vector(1049259,24); manlo <= conv_std_logic_vector(102861624,28); exponent <= conv_std_logic_vector(1134,11); WHEN "0001001110" => manhi <= conv_std_logic_vector(7451476,24); manlo <= conv_std_logic_vector(13367584,28); exponent <= conv_std_logic_vector(1135,11); WHEN "0001001111" => manhi <= conv_std_logic_vector(16152990,24); manlo <= conv_std_logic_vector(178012490,28); exponent <= conv_std_logic_vector(1136,11); WHEN "0001010000" => manhi <= conv_std_logic_vector(5601179,24); manlo <= conv_std_logic_vector(159708139,28); exponent <= conv_std_logic_vector(1138,11); WHEN "0001010001" => manhi <= conv_std_logic_vector(13638177,24); manlo <= conv_std_logic_vector(12864164,28); exponent <= conv_std_logic_vector(1139,11); WHEN "0001010010" => manhi <= conv_std_logic_vector(3892186,24); manlo <= conv_std_logic_vector(149492240,28); exponent <= conv_std_logic_vector(1141,11); WHEN "0001010011" => manhi <= conv_std_logic_vector(11315414,24); manlo <= conv_std_logic_vector(184620728,28); exponent <= conv_std_logic_vector(1142,11); WHEN "0001010100" => manhi <= conv_std_logic_vector(2313705,24); manlo <= conv_std_logic_vector(235697385,28); exponent <= conv_std_logic_vector(1144,11); WHEN "0001010101" => manhi <= conv_std_logic_vector(9170037,24); manlo <= conv_std_logic_vector(3974263,28); exponent <= conv_std_logic_vector(1145,11); WHEN "0001010110" => manhi <= conv_std_logic_vector(855770,24); manlo <= conv_std_logic_vector(158952336,28); exponent <= conv_std_logic_vector(1147,11); WHEN "0001010111" => manhi <= conv_std_logic_vector(7188497,24); manlo <= conv_std_logic_vector(138900038,28); exponent <= conv_std_logic_vector(1148,11); WHEN "0001011000" => manhi <= conv_std_logic_vector(15795565,24); manlo <= conv_std_logic_vector(209449517,28); exponent <= conv_std_logic_vector(1149,11); WHEN "0001011001" => manhi <= conv_std_logic_vector(5358284,24); manlo <= conv_std_logic_vector(54736896,28); exponent <= conv_std_logic_vector(1151,11); WHEN "0001011010" => manhi <= conv_std_logic_vector(13308047,24); manlo <= conv_std_logic_vector(264159588,28); exponent <= conv_std_logic_vector(1152,11); WHEN "0001011011" => manhi <= conv_std_logic_vector(3667840,24); manlo <= conv_std_logic_vector(160544132,28); exponent <= conv_std_logic_vector(1154,11); WHEN "0001011100" => manhi <= conv_std_logic_vector(11010496,24); manlo <= conv_std_logic_vector(245935181,28); exponent <= conv_std_logic_vector(1155,11); WHEN "0001011101" => manhi <= conv_std_logic_vector(2106492,24); manlo <= conv_std_logic_vector(206325441,28); exponent <= conv_std_logic_vector(1157,11); WHEN "0001011110" => manhi <= conv_std_logic_vector(8888405,24); manlo <= conv_std_logic_vector(53641237,28); exponent <= conv_std_logic_vector(1158,11); WHEN "0001011111" => manhi <= conv_std_logic_vector(664381,24); manlo <= conv_std_logic_vector(249887163,28); exponent <= conv_std_logic_vector(1160,11); WHEN "0001100000" => manhi <= conv_std_logic_vector(6928373,24); manlo <= conv_std_logic_vector(95946938,28); exponent <= conv_std_logic_vector(1161,11); WHEN "0001100001" => manhi <= conv_std_logic_vector(15442020,24); manlo <= conv_std_logic_vector(105121290,28); exponent <= conv_std_logic_vector(1162,11); WHEN "0001100010" => manhi <= conv_std_logic_vector(5118025,24); manlo <= conv_std_logic_vector(54367076,28); exponent <= conv_std_logic_vector(1164,11); WHEN "0001100011" => manhi <= conv_std_logic_vector(12981502,24); manlo <= conv_std_logic_vector(39000129,28); exponent <= conv_std_logic_vector(1165,11); WHEN "0001100100" => manhi <= conv_std_logic_vector(3445929,24); manlo <= conv_std_logic_vector(186063861,28); exponent <= conv_std_logic_vector(1167,11); WHEN "0001100101" => manhi <= conv_std_logic_vector(10708888,24); manlo <= conv_std_logic_vector(194877084,28); exponent <= conv_std_logic_vector(1168,11); WHEN "0001100110" => manhi <= conv_std_logic_vector(1901528,24); manlo <= conv_std_logic_vector(202114223,28); exponent <= conv_std_logic_vector(1170,11); WHEN "0001100111" => manhi <= conv_std_logic_vector(8609830,24); manlo <= conv_std_logic_vector(59099508,28); exponent <= conv_std_logic_vector(1171,11); WHEN "0001101000" => manhi <= conv_std_logic_vector(475070,24); manlo <= conv_std_logic_vector(162304029,28); exponent <= conv_std_logic_vector(1173,11); WHEN "0001101001" => manhi <= conv_std_logic_vector(6671072,24); manlo <= conv_std_logic_vector(157938310,28); exponent <= conv_std_logic_vector(1174,11); WHEN "0001101010" => manhi <= conv_std_logic_vector(15092312,24); manlo <= conv_std_logic_vector(104450792,28); exponent <= conv_std_logic_vector(1175,11); WHEN "0001101011" => manhi <= conv_std_logic_vector(4880373,24); manlo <= conv_std_logic_vector(261837049,28); exponent <= conv_std_logic_vector(1177,11); WHEN "0001101100" => manhi <= conv_std_logic_vector(12658500,24); manlo <= conv_std_logic_vector(171583716,28); exponent <= conv_std_logic_vector(1178,11); WHEN "0001101101" => manhi <= conv_std_logic_vector(3226427,24); manlo <= conv_std_logic_vector(110595717,28); exponent <= conv_std_logic_vector(1180,11); WHEN "0001101110" => manhi <= conv_std_logic_vector(10410554,24); manlo <= conv_std_logic_vector(52320382,28); exponent <= conv_std_logic_vector(1181,11); WHEN "0001101111" => manhi <= conv_std_logic_vector(1698789,24); manlo <= conv_std_logic_vector(112550995,28); exponent <= conv_std_logic_vector(1183,11); WHEN "0001110000" => manhi <= conv_std_logic_vector(8334278,24); manlo <= conv_std_logic_vector(240753534,28); exponent <= conv_std_logic_vector(1184,11); WHEN "0001110001" => manhi <= conv_std_logic_vector(287814,24); manlo <= conv_std_logic_vector(17691391,28); exponent <= conv_std_logic_vector(1186,11); WHEN "0001110010" => manhi <= conv_std_logic_vector(6416564,24); manlo <= conv_std_logic_vector(151700710,28); exponent <= conv_std_logic_vector(1187,11); WHEN "0001110011" => manhi <= conv_std_logic_vector(14746400,24); manlo <= conv_std_logic_vector(32676275,28); exponent <= conv_std_logic_vector(1188,11); WHEN "0001110100" => manhi <= conv_std_logic_vector(4645302,24); manlo <= conv_std_logic_vector(58452725,28); exponent <= conv_std_logic_vector(1190,11); WHEN "0001110101" => manhi <= conv_std_logic_vector(12339004,24); manlo <= conv_std_logic_vector(267247876,28); exponent <= conv_std_logic_vector(1191,11); WHEN "0001110110" => manhi <= conv_std_logic_vector(3009307,24); manlo <= conv_std_logic_vector(164126253,28); exponent <= conv_std_logic_vector(1193,11); WHEN "0001110111" => manhi <= conv_std_logic_vector(10115457,24); manlo <= conv_std_logic_vector(212237584,28); exponent <= conv_std_logic_vector(1194,11); WHEN "0001111000" => manhi <= conv_std_logic_vector(1498250,24); manlo <= conv_std_logic_vector(166684427,28); exponent <= conv_std_logic_vector(1196,11); WHEN "0001111001" => manhi <= conv_std_logic_vector(8061718,24); manlo <= conv_std_logic_vector(110371593,28); exponent <= conv_std_logic_vector(1197,11); WHEN "0001111010" => manhi <= conv_std_logic_vector(102590,24); manlo <= conv_std_logic_vector(3231911,28); exponent <= conv_std_logic_vector(1199,11); WHEN "0001111011" => manhi <= conv_std_logic_vector(6164818,24); manlo <= conv_std_logic_vector(261783833,28); exponent <= conv_std_logic_vector(1200,11); WHEN "0001111100" => manhi <= conv_std_logic_vector(14404242,24); manlo <= conv_std_logic_vector(104825991,28); exponent <= conv_std_logic_vector(1201,11); WHEN "0001111101" => manhi <= conv_std_logic_vector(4412781,24); manlo <= conv_std_logic_vector(250166254,28); exponent <= conv_std_logic_vector(1203,11); WHEN "0001111110" => manhi <= conv_std_logic_vector(12022977,24); manlo <= conv_std_logic_vector(43417082,28); exponent <= conv_std_logic_vector(1204,11); WHEN "0001111111" => manhi <= conv_std_logic_vector(2794544,24); manlo <= conv_std_logic_vector(115942082,28); exponent <= conv_std_logic_vector(1206,11); WHEN "0010000000" => manhi <= conv_std_logic_vector(9823564,24); manlo <= conv_std_logic_vector(98386456,28); exponent <= conv_std_logic_vector(1207,11); WHEN "0010000001" => manhi <= conv_std_logic_vector(1299888,24); manlo <= conv_std_logic_vector(127046227,28); exponent <= conv_std_logic_vector(1209,11); WHEN "0010000010" => manhi <= conv_std_logic_vector(7792116,24); manlo <= conv_std_logic_vector(80649262,28); exponent <= conv_std_logic_vector(1210,11); WHEN "0010000011" => manhi <= conv_std_logic_vector(16615968,24); manlo <= conv_std_logic_vector(205307910,28); exponent <= conv_std_logic_vector(1211,11); WHEN "0010000100" => manhi <= conv_std_logic_vector(5915805,24); manlo <= conv_std_logic_vector(224185017,28); exponent <= conv_std_logic_vector(1213,11); WHEN "0010000101" => manhi <= conv_std_logic_vector(14065798,24); manlo <= conv_std_logic_vector(119094636,28); exponent <= conv_std_logic_vector(1214,11); WHEN "0010000110" => manhi <= conv_std_logic_vector(4182785,24); manlo <= conv_std_logic_vector(113890892,28); exponent <= conv_std_logic_vector(1216,11); WHEN "0010000111" => manhi <= conv_std_logic_vector(11710379,24); manlo <= conv_std_logic_vector(133692518,28); exponent <= conv_std_logic_vector(1217,11); WHEN "0010001000" => manhi <= conv_std_logic_vector(2582112,24); manlo <= conv_std_logic_vector(79109485,28); exponent <= conv_std_logic_vector(1219,11); WHEN "0010001001" => manhi <= conv_std_logic_vector(9534839,24); manlo <= conv_std_logic_vector(42234535,28); exponent <= conv_std_logic_vector(1220,11); WHEN "0010001010" => manhi <= conv_std_logic_vector(1103679,24); manlo <= conv_std_logic_vector(94193887,28); exponent <= conv_std_logic_vector(1222,11); WHEN "0010001011" => manhi <= conv_std_logic_vector(7525440,24); manlo <= conv_std_logic_vector(121994268,28); exponent <= conv_std_logic_vector(1223,11); WHEN "0010001100" => manhi <= conv_std_logic_vector(16253518,24); manlo <= conv_std_logic_vector(191052573,28); exponent <= conv_std_logic_vector(1224,11); WHEN "0010001101" => manhi <= conv_std_logic_vector(5669495,24); manlo <= conv_std_logic_vector(130696997,28); exponent <= conv_std_logic_vector(1226,11); WHEN "0010001110" => manhi <= conv_std_logic_vector(13731027,24); manlo <= conv_std_logic_vector(260846837,28); exponent <= conv_std_logic_vector(1227,11); WHEN "0010001111" => manhi <= conv_std_logic_vector(3955285,24); manlo <= conv_std_logic_vector(80970159,28); exponent <= conv_std_logic_vector(1229,11); WHEN "0010010000" => manhi <= conv_std_logic_vector(11401174,24); manlo <= conv_std_logic_vector(207600506,28); exponent <= conv_std_logic_vector(1230,11); WHEN "0010010001" => manhi <= conv_std_logic_vector(2371985,24); manlo <= conv_std_logic_vector(241221170,28); exponent <= conv_std_logic_vector(1232,11); WHEN "0010010010" => manhi <= conv_std_logic_vector(9249247,24); manlo <= conv_std_logic_vector(208105818,28); exponent <= conv_std_logic_vector(1233,11); WHEN "0010010011" => manhi <= conv_std_logic_vector(909599,24); manlo <= conv_std_logic_vector(237519888,28); exponent <= conv_std_logic_vector(1235,11); WHEN "0010010100" => manhi <= conv_std_logic_vector(7261659,24); manlo <= conv_std_logic_vector(29935335,28); exponent <= conv_std_logic_vector(1236,11); WHEN "0010010101" => manhi <= conv_std_logic_vector(15895002,24); manlo <= conv_std_logic_vector(186862656,28); exponent <= conv_std_logic_vector(1237,11); WHEN "0010010110" => manhi <= conv_std_logic_vector(5425858,24); manlo <= conv_std_logic_vector(159524243,28); exponent <= conv_std_logic_vector(1239,11); WHEN "0010010111" => manhi <= conv_std_logic_vector(13399891,24); manlo <= conv_std_logic_vector(27586577,28); exponent <= conv_std_logic_vector(1240,11); WHEN "0010011000" => manhi <= conv_std_logic_vector(3730254,24); manlo <= conv_std_logic_vector(125689310,28); exponent <= conv_std_logic_vector(1242,11); WHEN "0010011001" => manhi <= conv_std_logic_vector(11095326,24); manlo <= conv_std_logic_vector(43144000,28); exponent <= conv_std_logic_vector(1243,11); WHEN "0010011010" => manhi <= conv_std_logic_vector(2164140,24); manlo <= conv_std_logic_vector(58280992,28); exponent <= conv_std_logic_vector(1245,11); WHEN "0010011011" => manhi <= conv_std_logic_vector(8966756,24); manlo <= conv_std_logic_vector(55210422,28); exponent <= conv_std_logic_vector(1246,11); WHEN "0010011100" => manhi <= conv_std_logic_vector(717626,24); manlo <= conv_std_logic_vector(257633658,28); exponent <= conv_std_logic_vector(1248,11); WHEN "0010011101" => manhi <= conv_std_logic_vector(7000740,24); manlo <= conv_std_logic_vector(229413090,28); exponent <= conv_std_logic_vector(1249,11); WHEN "0010011110" => manhi <= conv_std_logic_vector(15540378,24); manlo <= conv_std_logic_vector(4808337,28); exponent <= conv_std_logic_vector(1250,11); WHEN "0010011111" => manhi <= conv_std_logic_vector(5184866,24); manlo <= conv_std_logic_vector(37474138,28); exponent <= conv_std_logic_vector(1252,11); WHEN "0010100000" => manhi <= conv_std_logic_vector(13072348,24); manlo <= conv_std_logic_vector(106730632,28); exponent <= conv_std_logic_vector(1253,11); WHEN "0010100001" => manhi <= conv_std_logic_vector(3507666,24); manlo <= conv_std_logic_vector(32844500,28); exponent <= conv_std_logic_vector(1255,11); WHEN "0010100010" => manhi <= conv_std_logic_vector(10792797,24); manlo <= conv_std_logic_vector(62496090,28); exponent <= conv_std_logic_vector(1256,11); WHEN "0010100011" => manhi <= conv_std_logic_vector(1958550,24); manlo <= conv_std_logic_vector(132952012,28); exponent <= conv_std_logic_vector(1258,11); WHEN "0010100100" => manhi <= conv_std_logic_vector(8687330,24); manlo <= conv_std_logic_vector(215605290,28); exponent <= conv_std_logic_vector(1259,11); WHEN "0010100101" => manhi <= conv_std_logic_vector(527737,24); manlo <= conv_std_logic_vector(190928911,28); exponent <= conv_std_logic_vector(1261,11); WHEN "0010100110" => manhi <= conv_std_logic_vector(6742654,24); manlo <= conv_std_logic_vector(163162889,28); exponent <= conv_std_logic_vector(1262,11); WHEN "0010100111" => manhi <= conv_std_logic_vector(15189602,24); manlo <= conv_std_logic_vector(118241780,28); exponent <= conv_std_logic_vector(1263,11); WHEN "0010101000" => manhi <= conv_std_logic_vector(4946489,24); manlo <= conv_std_logic_vector(112771062,28); exponent <= conv_std_logic_vector(1265,11); WHEN "0010101001" => manhi <= conv_std_logic_vector(12748360,24); manlo <= conv_std_logic_vector(226864003,28); exponent <= conv_std_logic_vector(1266,11); WHEN "0010101010" => manhi <= conv_std_logic_vector(3287493,24); manlo <= conv_std_logic_vector(202192272,28); exponent <= conv_std_logic_vector(1268,11); WHEN "0010101011" => manhi <= conv_std_logic_vector(10493551,24); manlo <= conv_std_logic_vector(257093553,28); exponent <= conv_std_logic_vector(1269,11); WHEN "0010101100" => manhi <= conv_std_logic_vector(1755192,24); manlo <= conv_std_logic_vector(66281405,28); exponent <= conv_std_logic_vector(1271,11); WHEN "0010101101" => manhi <= conv_std_logic_vector(8410938,24); manlo <= conv_std_logic_vector(77199396,28); exponent <= conv_std_logic_vector(1272,11); WHEN "0010101110" => manhi <= conv_std_logic_vector(339909,24); manlo <= conv_std_logic_vector(140417186,28); exponent <= conv_std_logic_vector(1274,11); WHEN "0010101111" => manhi <= conv_std_logic_vector(6487369,24); manlo <= conv_std_logic_vector(169769464,28); exponent <= conv_std_logic_vector(1275,11); WHEN "0010110000" => manhi <= conv_std_logic_vector(14842634,24); manlo <= conv_std_logic_vector(49834035,28); exponent <= conv_std_logic_vector(1276,11); WHEN "0010110001" => manhi <= conv_std_logic_vector(4710700,24); manlo <= conv_std_logic_vector(11961455,28); exponent <= conv_std_logic_vector(1278,11); WHEN "0010110010" => manhi <= conv_std_logic_vector(12427889,24); manlo <= conv_std_logic_vector(230234502,28); exponent <= conv_std_logic_vector(1279,11); WHEN "0010110011" => manhi <= conv_std_logic_vector(3069711,24); manlo <= conv_std_logic_vector(36989233,28); exponent <= conv_std_logic_vector(1281,11); WHEN "0010110100" => manhi <= conv_std_logic_vector(10197554,24); manlo <= conv_std_logic_vector(186484869,28); exponent <= conv_std_logic_vector(1282,11); WHEN "0010110101" => manhi <= conv_std_logic_vector(1554041,24); manlo <= conv_std_logic_vector(67530342,28); exponent <= conv_std_logic_vector(1284,11); WHEN "0010110110" => manhi <= conv_std_logic_vector(8137545,24); manlo <= conv_std_logic_vector(198608842,28); exponent <= conv_std_logic_vector(1285,11); WHEN "0010110111" => manhi <= conv_std_logic_vector(154120,24); manlo <= conv_std_logic_vector(6569319,28); exponent <= conv_std_logic_vector(1287,11); WHEN "0010111000" => manhi <= conv_std_logic_vector(6234855,24); manlo <= conv_std_logic_vector(140506894,28); exponent <= conv_std_logic_vector(1288,11); WHEN "0010111001" => manhi <= conv_std_logic_vector(14499431,24); manlo <= conv_std_logic_vector(249287529,28); exponent <= conv_std_logic_vector(1289,11); WHEN "0010111010" => manhi <= conv_std_logic_vector(4477469,24); manlo <= conv_std_logic_vector(249618841,28); exponent <= conv_std_logic_vector(1291,11); WHEN "0010111011" => manhi <= conv_std_logic_vector(12110897,24); manlo <= conv_std_logic_vector(71519058,28); exponent <= conv_std_logic_vector(1292,11); WHEN "0010111100" => manhi <= conv_std_logic_vector(2854292,24); manlo <= conv_std_logic_vector(90637320,28); exponent <= conv_std_logic_vector(1294,11); WHEN "0010111101" => manhi <= conv_std_logic_vector(9904770,24); manlo <= conv_std_logic_vector(50932558,28); exponent <= conv_std_logic_vector(1295,11); WHEN "0010111110" => manhi <= conv_std_logic_vector(1355073,24); manlo <= conv_std_logic_vector(148093260,28); exponent <= conv_std_logic_vector(1297,11); WHEN "0010111111" => manhi <= conv_std_logic_vector(7867120,24); manlo <= conv_std_logic_vector(160620741,28); exponent <= conv_std_logic_vector(1298,11); WHEN "0011000000" => manhi <= conv_std_logic_vector(16717910,24); manlo <= conv_std_logic_vector(46942270,28); exponent <= conv_std_logic_vector(1299,11); WHEN "0011000001" => manhi <= conv_std_logic_vector(5985082,24); manlo <= conv_std_logic_vector(55237426,28); exponent <= conv_std_logic_vector(1301,11); WHEN "0011000010" => manhi <= conv_std_logic_vector(14159954,24); manlo <= conv_std_logic_vector(212966668,28); exponent <= conv_std_logic_vector(1302,11); WHEN "0011000011" => manhi <= conv_std_logic_vector(4246771,24); manlo <= conv_std_logic_vector(79962334,28); exponent <= conv_std_logic_vector(1304,11); WHEN "0011000100" => manhi <= conv_std_logic_vector(11797345,24); manlo <= conv_std_logic_vector(85038862,28); exponent <= conv_std_logic_vector(1305,11); WHEN "0011000101" => manhi <= conv_std_logic_vector(2641211,24); manlo <= conv_std_logic_vector(186806322,28); exponent <= conv_std_logic_vector(1307,11); WHEN "0011000110" => manhi <= conv_std_logic_vector(9615163,24); manlo <= conv_std_logic_vector(153415152,28); exponent <= conv_std_logic_vector(1308,11); WHEN "0011000111" => manhi <= conv_std_logic_vector(1158265,24); manlo <= conv_std_logic_vector(120731907,28); exponent <= conv_std_logic_vector(1310,11); WHEN "0011001000" => manhi <= conv_std_logic_vector(7599630,24); manlo <= conv_std_logic_vector(175764921,28); exponent <= conv_std_logic_vector(1311,11); WHEN "0011001001" => manhi <= conv_std_logic_vector(16354353,24); manlo <= conv_std_logic_vector(174054693,28); exponent <= conv_std_logic_vector(1312,11); WHEN "0011001010" => manhi <= conv_std_logic_vector(5738019,24); manlo <= conv_std_logic_vector(249885394,28); exponent <= conv_std_logic_vector(1314,11); WHEN "0011001011" => manhi <= conv_std_logic_vector(13824162,24); manlo <= conv_std_logic_vector(93203713,28); exponent <= conv_std_logic_vector(1315,11); WHEN "0011001100" => manhi <= conv_std_logic_vector(4018576,24); manlo <= conv_std_logic_vector(180323091,28); exponent <= conv_std_logic_vector(1317,11); WHEN "0011001101" => manhi <= conv_std_logic_vector(11487196,24); manlo <= conv_std_logic_vector(178245939,28); exponent <= conv_std_logic_vector(1318,11); WHEN "0011001110" => manhi <= conv_std_logic_vector(2430443,24); manlo <= conv_std_logic_vector(223919964,28); exponent <= conv_std_logic_vector(1320,11); WHEN "0011001111" => manhi <= conv_std_logic_vector(9328700,24); manlo <= conv_std_logic_vector(93205956,28); exponent <= conv_std_logic_vector(1321,11); WHEN "0011010000" => manhi <= conv_std_logic_vector(963593,24); manlo <= conv_std_logic_vector(135688620,28); exponent <= conv_std_logic_vector(1323,11); WHEN "0011010001" => manhi <= conv_std_logic_vector(7335044,24); manlo <= conv_std_logic_vector(13542358,28); exponent <= conv_std_logic_vector(1324,11); WHEN "0011010010" => manhi <= conv_std_logic_vector(15994743,24); manlo <= conv_std_logic_vector(45394459,28); exponent <= conv_std_logic_vector(1325,11); WHEN "0011010011" => manhi <= conv_std_logic_vector(5493639,24); manlo <= conv_std_logic_vector(73308838,28); exponent <= conv_std_logic_vector(1327,11); WHEN "0011010100" => manhi <= conv_std_logic_vector(13492014,24); manlo <= conv_std_logic_vector(160135181,28); exponent <= conv_std_logic_vector(1328,11); WHEN "0011010101" => manhi <= conv_std_logic_vector(3792858,24); manlo <= conv_std_logic_vector(234346738,28); exponent <= conv_std_logic_vector(1330,11); WHEN "0011010110" => manhi <= conv_std_logic_vector(11180414,24); manlo <= conv_std_logic_vector(98964646,28); exponent <= conv_std_logic_vector(1331,11); WHEN "0011010111" => manhi <= conv_std_logic_vector(2221963,24); manlo <= conv_std_logic_vector(174344531,28); exponent <= conv_std_logic_vector(1333,11); WHEN "0011011000" => manhi <= conv_std_logic_vector(9045346,24); manlo <= conv_std_logic_vector(106947534,28); exponent <= conv_std_logic_vector(1334,11); WHEN "0011011001" => manhi <= conv_std_logic_vector(771034,24); manlo <= conv_std_logic_vector(143065990,28); exponent <= conv_std_logic_vector(1336,11); WHEN "0011011010" => manhi <= conv_std_logic_vector(7073329,24); manlo <= conv_std_logic_vector(73148434,28); exponent <= conv_std_logic_vector(1337,11); WHEN "0011011011" => manhi <= conv_std_logic_vector(15639035,24); manlo <= conv_std_logic_vector(243346703,28); exponent <= conv_std_logic_vector(1338,11); WHEN "0011011100" => manhi <= conv_std_logic_vector(5251911,24); manlo <= conv_std_logic_vector(33842377,28); exponent <= conv_std_logic_vector(1340,11); WHEN "0011011101" => manhi <= conv_std_logic_vector(13163471,24); manlo <= conv_std_logic_vector(263552292,28); exponent <= conv_std_logic_vector(1341,11); WHEN "0011011110" => manhi <= conv_std_logic_vector(3569591,24); manlo <= conv_std_logic_vector(4866264,28); exponent <= conv_std_logic_vector(1343,11); WHEN "0011011111" => manhi <= conv_std_logic_vector(10876961,24); manlo <= conv_std_logic_vector(239517036,28); exponent <= conv_std_logic_vector(1344,11); WHEN "0011100000" => manhi <= conv_std_logic_vector(2015746,24); manlo <= conv_std_logic_vector(83586287,28); exponent <= conv_std_logic_vector(1346,11); WHEN "0011100001" => manhi <= conv_std_logic_vector(8765067,24); manlo <= conv_std_logic_vector(262254542,28); exponent <= conv_std_logic_vector(1347,11); WHEN "0011100010" => manhi <= conv_std_logic_vector(580565,24); manlo <= conv_std_logic_vector(160521039,28); exponent <= conv_std_logic_vector(1349,11); WHEN "0011100011" => manhi <= conv_std_logic_vector(6814455,24); manlo <= conv_std_logic_vector(40288155,28); exponent <= conv_std_logic_vector(1350,11); WHEN "0011100100" => manhi <= conv_std_logic_vector(15287189,24); manlo <= conv_std_logic_vector(132910147,28); exponent <= conv_std_logic_vector(1351,11); WHEN "0011100101" => manhi <= conv_std_logic_vector(5012806,24); manlo <= conv_std_logic_vector(187753904,28); exponent <= conv_std_logic_vector(1353,11); WHEN "0011100110" => manhi <= conv_std_logic_vector(12838495,24); manlo <= conv_std_logic_vector(100071648,28); exponent <= conv_std_logic_vector(1354,11); WHEN "0011100111" => manhi <= conv_std_logic_vector(3348746,24); manlo <= conv_std_logic_vector(138348888,28); exponent <= conv_std_logic_vector(1356,11); WHEN "0011101000" => manhi <= conv_std_logic_vector(10576803,24); manlo <= conv_std_logic_vector(24941937,28); exponent <= conv_std_logic_vector(1357,11); WHEN "0011101001" => manhi <= conv_std_logic_vector(1811767,24); manlo <= conv_std_logic_vector(69497619,28); exponent <= conv_std_logic_vector(1359,11); WHEN "0011101010" => manhi <= conv_std_logic_vector(8487831,24); manlo <= conv_std_logic_vector(188199296,28); exponent <= conv_std_logic_vector(1360,11); WHEN "0011101011" => manhi <= conv_std_logic_vector(392164,24); manlo <= conv_std_logic_vector(4096525,28); exponent <= conv_std_logic_vector(1362,11); WHEN "0011101100" => manhi <= conv_std_logic_vector(6558390,24); manlo <= conv_std_logic_vector(228356857,28); exponent <= conv_std_logic_vector(1363,11); WHEN "0011101101" => manhi <= conv_std_logic_vector(14939162,24); manlo <= conv_std_logic_vector(7826265,28); exponent <= conv_std_logic_vector(1364,11); WHEN "0011101110" => manhi <= conv_std_logic_vector(4776297,24); manlo <= conv_std_logic_vector(138324122,28); exponent <= conv_std_logic_vector(1366,11); WHEN "0011101111" => manhi <= conv_std_logic_vector(12517046,24); manlo <= conv_std_logic_vector(17190560,28); exponent <= conv_std_logic_vector(1367,11); WHEN "0011110000" => manhi <= conv_std_logic_vector(3130299,24); manlo <= conv_std_logic_vector(16562242,28); exponent <= conv_std_logic_vector(1369,11); WHEN "0011110001" => manhi <= conv_std_logic_vector(10279902,24); manlo <= conv_std_logic_vector(59323104,28); exponent <= conv_std_logic_vector(1370,11); WHEN "0011110010" => manhi <= conv_std_logic_vector(1610002,24); manlo <= conv_std_logic_vector(53056333,28); exponent <= conv_std_logic_vector(1372,11); WHEN "0011110011" => manhi <= conv_std_logic_vector(8213604,24); manlo <= conv_std_logic_vector(147986337,28); exponent <= conv_std_logic_vector(1373,11); WHEN "0011110100" => manhi <= conv_std_logic_vector(205807,24); manlo <= conv_std_logic_vector(92802035,28); exponent <= conv_std_logic_vector(1375,11); WHEN "0011110101" => manhi <= conv_std_logic_vector(6305105,24); manlo <= conv_std_logic_vector(235277170,28); exponent <= conv_std_logic_vector(1376,11); WHEN "0011110110" => manhi <= conv_std_logic_vector(14594912,24); manlo <= conv_std_logic_vector(15497684,28); exponent <= conv_std_logic_vector(1377,11); WHEN "0011110111" => manhi <= conv_std_logic_vector(4542355,24); manlo <= conv_std_logic_vector(108677892,28); exponent <= conv_std_logic_vector(1379,11); WHEN "0011111000" => manhi <= conv_std_logic_vector(12199085,24); manlo <= conv_std_logic_vector(206743222,28); exponent <= conv_std_logic_vector(1380,11); WHEN "0011111001" => manhi <= conv_std_logic_vector(2914222,24); manlo <= conv_std_logic_vector(171652524,28); exponent <= conv_std_logic_vector(1382,11); WHEN "0011111010" => manhi <= conv_std_logic_vector(9986223,24); manlo <= conv_std_logic_vector(245598061,28); exponent <= conv_std_logic_vector(1383,11); WHEN "0011111011" => manhi <= conv_std_logic_vector(1410427,24); manlo <= conv_std_logic_vector(26024388,28); exponent <= conv_std_logic_vector(1385,11); WHEN "0011111100" => manhi <= conv_std_logic_vector(7942353,24); manlo <= conv_std_logic_vector(232590388,28); exponent <= conv_std_logic_vector(1386,11); WHEN "0011111101" => manhi <= conv_std_logic_vector(21473,24); manlo <= conv_std_logic_vector(105719295,28); exponent <= conv_std_logic_vector(1388,11); WHEN "0011111110" => manhi <= conv_std_logic_vector(6054570,24); manlo <= conv_std_logic_vector(16265786,28); exponent <= conv_std_logic_vector(1389,11); WHEN "0011111111" => manhi <= conv_std_logic_vector(14254398,24); manlo <= conv_std_logic_vector(155662944,28); exponent <= conv_std_logic_vector(1390,11); WHEN "0100000000" => manhi <= conv_std_logic_vector(4310952,24); manlo <= conv_std_logic_vector(135577274,28); exponent <= conv_std_logic_vector(1392,11); WHEN "0100000001" => manhi <= conv_std_logic_vector(11884576,24); manlo <= conv_std_logic_vector(166805756,28); exponent <= conv_std_logic_vector(1393,11); WHEN "0100000010" => manhi <= conv_std_logic_vector(2700491,24); manlo <= conv_std_logic_vector(137829044,28); exponent <= conv_std_logic_vector(1395,11); WHEN "0100000011" => manhi <= conv_std_logic_vector(9695733,24); manlo <= conv_std_logic_vector(52863001,28); exponent <= conv_std_logic_vector(1396,11); WHEN "0100000100" => manhi <= conv_std_logic_vector(1213018,24); manlo <= conv_std_logic_vector(50179603,28); exponent <= conv_std_logic_vector(1398,11); WHEN "0100000101" => manhi <= conv_std_logic_vector(7674047,24); manlo <= conv_std_logic_vector(91276680,28); exponent <= conv_std_logic_vector(1399,11); WHEN "0100000110" => manhi <= conv_std_logic_vector(16455496,24); manlo <= conv_std_logic_vector(110068760,28); exponent <= conv_std_logic_vector(1400,11); WHEN "0100000111" => manhi <= conv_std_logic_vector(5806753,24); manlo <= conv_std_logic_vector(151304445,28); exponent <= conv_std_logic_vector(1402,11); WHEN "0100001000" => manhi <= conv_std_logic_vector(13917581,24); manlo <= conv_std_logic_vector(10650184,28); exponent <= conv_std_logic_vector(1403,11); WHEN "0100001001" => manhi <= conv_std_logic_vector(4082061,24); manlo <= conv_std_logic_vector(68530707,28); exponent <= conv_std_logic_vector(1405,11); WHEN "0100001010" => manhi <= conv_std_logic_vector(11573481,24); manlo <= conv_std_logic_vector(42662756,28); exponent <= conv_std_logic_vector(1406,11); WHEN "0100001011" => manhi <= conv_std_logic_vector(2489080,24); manlo <= conv_std_logic_vector(61154162,28); exponent <= conv_std_logic_vector(1408,11); WHEN "0100001100" => manhi <= conv_std_logic_vector(9408395,24); manlo <= conv_std_logic_vector(125867240,28); exponent <= conv_std_logic_vector(1409,11); WHEN "0100001101" => manhi <= conv_std_logic_vector(1017751,24); manlo <= conv_std_logic_vector(256555705,28); exponent <= conv_std_logic_vector(1411,11); WHEN "0100001110" => manhi <= conv_std_logic_vector(7408653,24); manlo <= conv_std_logic_vector(4309896,28); exponent <= conv_std_logic_vector(1412,11); WHEN "0100001111" => manhi <= conv_std_logic_vector(16094788,24); manlo <= conv_std_logic_vector(33800670,28); exponent <= conv_std_logic_vector(1413,11); WHEN "0100010000" => manhi <= conv_std_logic_vector(5561626,24); manlo <= conv_std_logic_vector(233573192,28); exponent <= conv_std_logic_vector(1415,11); WHEN "0100010001" => manhi <= conv_std_logic_vector(13584419,24); manlo <= conv_std_logic_vector(86257801,28); exponent <= conv_std_logic_vector(1416,11); WHEN "0100010010" => manhi <= conv_std_logic_vector(3855654,24); manlo <= conv_std_logic_vector(105782775,28); exponent <= conv_std_logic_vector(1418,11); WHEN "0100010011" => manhi <= conv_std_logic_vector(11265762,24); manlo <= conv_std_logic_vector(88738762,28); exponent <= conv_std_logic_vector(1419,11); WHEN "0100010100" => manhi <= conv_std_logic_vector(2279963,24); manlo <= conv_std_logic_vector(161858527,28); exponent <= conv_std_logic_vector(1421,11); WHEN "0100010101" => manhi <= conv_std_logic_vector(9124176,24); manlo <= conv_std_logic_vector(136423424,28); exponent <= conv_std_logic_vector(1422,11); WHEN "0100010110" => manhi <= conv_std_logic_vector(824605,24); manlo <= conv_std_logic_vector(39384255,28); exponent <= conv_std_logic_vector(1424,11); WHEN "0100010111" => manhi <= conv_std_logic_vector(7146139,24); manlo <= conv_std_logic_vector(76626123,28); exponent <= conv_std_logic_vector(1425,11); WHEN "0100011000" => manhi <= conv_std_logic_vector(15737994,24); manlo <= conv_std_logic_vector(261485765,28); exponent <= conv_std_logic_vector(1426,11); WHEN "0100011001" => manhi <= conv_std_logic_vector(5319160,24); manlo <= conv_std_logic_vector(210684009,28); exponent <= conv_std_logic_vector(1428,11); WHEN "0100011010" => manhi <= conv_std_logic_vector(13254873,24); manlo <= conv_std_logic_vector(199859160,28); exponent <= conv_std_logic_vector(1429,11); WHEN "0100011011" => manhi <= conv_std_logic_vector(3631704,24); manlo <= conv_std_logic_vector(256571707,28); exponent <= conv_std_logic_vector(1431,11); WHEN "0100011100" => manhi <= conv_std_logic_vector(10961383,24); manlo <= conv_std_logic_vector(130542749,28); exponent <= conv_std_logic_vector(1432,11); WHEN "0100011101" => manhi <= conv_std_logic_vector(2073116,24); manlo <= conv_std_logic_vector(196665136,28); exponent <= conv_std_logic_vector(1434,11); WHEN "0100011110" => manhi <= conv_std_logic_vector(8843042,24); manlo <= conv_std_logic_vector(124490661,28); exponent <= conv_std_logic_vector(1435,11); WHEN "0100011111" => manhi <= conv_std_logic_vector(633554,24); manlo <= conv_std_logic_vector(202834752,28); exponent <= conv_std_logic_vector(1437,11); WHEN "0100100000" => manhi <= conv_std_logic_vector(6886474,24); manlo <= conv_std_logic_vector(236822279,28); exponent <= conv_std_logic_vector(1438,11); WHEN "0100100001" => manhi <= conv_std_logic_vector(15385074,24); manlo <= conv_std_logic_vector(123405487,28); exponent <= conv_std_logic_vector(1439,11); WHEN "0100100010" => manhi <= conv_std_logic_vector(5079326,24); manlo <= conv_std_logic_vector(115311954,28); exponent <= conv_std_logic_vector(1441,11); WHEN "0100100011" => manhi <= conv_std_logic_vector(12928905,24); manlo <= conv_std_logic_vector(16004876,28); exponent <= conv_std_logic_vector(1442,11); WHEN "0100100100" => manhi <= conv_std_logic_vector(3410186,24); manlo <= conv_std_logic_vector(71831800,28); exponent <= conv_std_logic_vector(1444,11); WHEN "0100100101" => manhi <= conv_std_logic_vector(10660308,24); manlo <= conv_std_logic_vector(100367284,28); exponent <= conv_std_logic_vector(1445,11); WHEN "0100100110" => manhi <= conv_std_logic_vector(1868514,24); manlo <= conv_std_logic_vector(263299419,28); exponent <= conv_std_logic_vector(1447,11); WHEN "0100100111" => manhi <= conv_std_logic_vector(8564959,24); manlo <= conv_std_logic_vector(228656810,28); exponent <= conv_std_logic_vector(1448,11); WHEN "0100101000" => manhi <= conv_std_logic_vector(444578,24); manlo <= conv_std_logic_vector(7489141,28); exponent <= conv_std_logic_vector(1450,11); WHEN "0100101001" => manhi <= conv_std_logic_vector(6629628,24); manlo <= conv_std_logic_vector(236156491,28); exponent <= conv_std_logic_vector(1451,11); WHEN "0100101010" => manhi <= conv_std_logic_vector(15035984,24); manlo <= conv_std_logic_vector(147396312,28); exponent <= conv_std_logic_vector(1452,11); WHEN "0100101011" => manhi <= conv_std_logic_vector(4842095,24); manlo <= conv_std_logic_vector(64271882,28); exponent <= conv_std_logic_vector(1454,11); WHEN "0100101100" => manhi <= conv_std_logic_vector(12606474,24); manlo <= conv_std_logic_vector(118909770,28); exponent <= conv_std_logic_vector(1455,11); WHEN "0100101101" => manhi <= conv_std_logic_vector(3191071,24); manlo <= conv_std_logic_vector(253953386,28); exponent <= conv_std_logic_vector(1457,11); WHEN "0100101110" => manhi <= conv_std_logic_vector(10362501,24); manlo <= conv_std_logic_vector(36129498,28); exponent <= conv_std_logic_vector(1458,11); WHEN "0100101111" => manhi <= conv_std_logic_vector(1666133,24); manlo <= conv_std_logic_vector(262830684,28); exponent <= conv_std_logic_vector(1460,11); WHEN "0100110000" => manhi <= conv_std_logic_vector(8289895,24); manlo <= conv_std_logic_vector(148197046,28); exponent <= conv_std_logic_vector(1461,11); WHEN "0100110001" => manhi <= conv_std_logic_vector(257652,24); manlo <= conv_std_logic_vector(122404338,28); exponent <= conv_std_logic_vector(1463,11); WHEN "0100110010" => manhi <= conv_std_logic_vector(6375570,24); manlo <= conv_std_logic_vector(184430245,28); exponent <= conv_std_logic_vector(1464,11); WHEN "0100110011" => manhi <= conv_std_logic_vector(14690683,24); manlo <= conv_std_logic_vector(178457687,28); exponent <= conv_std_logic_vector(1465,11); WHEN "0100110100" => manhi <= conv_std_logic_vector(4607438,24); manlo <= conv_std_logic_vector(257605193,28); exponent <= conv_std_logic_vector(1467,11); WHEN "0100110101" => manhi <= conv_std_logic_vector(12287543,24); manlo <= conv_std_logic_vector(132163446,28); exponent <= conv_std_logic_vector(1468,11); WHEN "0100110110" => manhi <= conv_std_logic_vector(2974335,24); manlo <= conv_std_logic_vector(240020217,28); exponent <= conv_std_logic_vector(1470,11); WHEN "0100110111" => manhi <= conv_std_logic_vector(10067926,24); manlo <= conv_std_logic_vector(80224641,28); exponent <= conv_std_logic_vector(1471,11); WHEN "0100111000" => manhi <= conv_std_logic_vector(1465949,24); manlo <= conv_std_logic_vector(167328478,28); exponent <= conv_std_logic_vector(1473,11); WHEN "0100111001" => manhi <= conv_std_logic_vector(8017816,24); manlo <= conv_std_logic_vector(215756784,28); exponent <= conv_std_logic_vector(1474,11); WHEN "0100111010" => manhi <= conv_std_logic_vector(72755,24); manlo <= conv_std_logic_vector(208473528,28); exponent <= conv_std_logic_vector(1476,11); WHEN "0100111011" => manhi <= conv_std_logic_vector(6124270,24); manlo <= conv_std_logic_vector(12139444,28); exponent <= conv_std_logic_vector(1477,11); WHEN "0100111100" => manhi <= conv_std_logic_vector(14349130,24); manlo <= conv_std_logic_vector(182729110,28); exponent <= conv_std_logic_vector(1478,11); WHEN "0100111101" => manhi <= conv_std_logic_vector(4375329,24); manlo <= conv_std_logic_vector(172370119,28); exponent <= conv_std_logic_vector(1480,11); WHEN "0100111110" => manhi <= conv_std_logic_vector(11972074,24); manlo <= conv_std_logic_vector(59679792,28); exponent <= conv_std_logic_vector(1481,11); WHEN "0100111111" => manhi <= conv_std_logic_vector(2759952,24); manlo <= conv_std_logic_vector(80023302,28); exponent <= conv_std_logic_vector(1483,11); WHEN "0101000000" => manhi <= conv_std_logic_vector(9776548,24); manlo <= conv_std_logic_vector(209956608,28); exponent <= conv_std_logic_vector(1484,11); WHEN "0101000001" => manhi <= conv_std_logic_vector(1267938,24); manlo <= conv_std_logic_vector(19091951,28); exponent <= conv_std_logic_vector(1486,11); WHEN "0101000010" => manhi <= conv_std_logic_vector(7748691,24); manlo <= conv_std_logic_vector(54127000,28); exponent <= conv_std_logic_vector(1487,11); WHEN "0101000011" => manhi <= conv_std_logic_vector(16556947,24); manlo <= conv_std_logic_vector(251347868,28); exponent <= conv_std_logic_vector(1488,11); WHEN "0101000100" => manhi <= conv_std_logic_vector(5875697,24); manlo <= conv_std_logic_vector(6377900,28); exponent <= conv_std_logic_vector(1490,11); WHEN "0101000101" => manhi <= conv_std_logic_vector(14011284,24); manlo <= conv_std_logic_vector(246175281,28); exponent <= conv_std_logic_vector(1491,11); WHEN "0101000110" => manhi <= conv_std_logic_vector(4145739,24); manlo <= conv_std_logic_vector(172360927,28); exponent <= conv_std_logic_vector(1493,11); WHEN "0101000111" => manhi <= conv_std_logic_vector(11660029,24); manlo <= conv_std_logic_vector(16047086,28); exponent <= conv_std_logic_vector(1494,11); WHEN "0101001000" => manhi <= conv_std_logic_vector(2547895,24); manlo <= conv_std_logic_vector(167600151,28); exponent <= conv_std_logic_vector(1496,11); WHEN "0101001001" => manhi <= conv_std_logic_vector(9488333,24); manlo <= conv_std_logic_vector(236416250,28); exponent <= conv_std_logic_vector(1497,11); WHEN "0101001010" => manhi <= conv_std_logic_vector(1072075,24); manlo <= conv_std_logic_vector(198323037,28); exponent <= conv_std_logic_vector(1499,11); WHEN "0101001011" => manhi <= conv_std_logic_vector(7482486,24); manlo <= conv_std_logic_vector(185820926,28); exponent <= conv_std_logic_vector(1500,11); WHEN "0101001100" => manhi <= conv_std_logic_vector(16195138,24); manlo <= conv_std_logic_vector(133160968,28); exponent <= conv_std_logic_vector(1501,11); WHEN "0101001101" => manhi <= conv_std_logic_vector(5629822,24); manlo <= conv_std_logic_vector(4574050,28); exponent <= conv_std_logic_vector(1503,11); WHEN "0101001110" => manhi <= conv_std_logic_vector(13677106,24); manlo <= conv_std_logic_vector(36414601,28); exponent <= conv_std_logic_vector(1504,11); WHEN "0101001111" => manhi <= conv_std_logic_vector(3918641,24); manlo <= conv_std_logic_vector(165046798,28); exponent <= conv_std_logic_vector(1506,11); WHEN "0101010000" => manhi <= conv_std_logic_vector(11351370,24); manlo <= conv_std_logic_vector(225326735,28); exponent <= conv_std_logic_vector(1507,11); WHEN "0101010001" => manhi <= conv_std_logic_vector(2338140,24); manlo <= conv_std_logic_vector(165476611,28); exponent <= conv_std_logic_vector(1509,11); WHEN "0101010010" => manhi <= conv_std_logic_vector(9203247,24); manlo <= conv_std_logic_vector(71807303,28); exponent <= conv_std_logic_vector(1510,11); WHEN "0101010011" => manhi <= conv_std_logic_vector(878339,24); manlo <= conv_std_logic_vector(80195176,28); exponent <= conv_std_logic_vector(1512,11); WHEN "0101010100" => manhi <= conv_std_logic_vector(7219171,24); manlo <= conv_std_logic_vector(153001068,28); exponent <= conv_std_logic_vector(1513,11); WHEN "0101010101" => manhi <= conv_std_logic_vector(15837256,24); manlo <= conv_std_logic_vector(37596960,28); exponent <= conv_std_logic_vector(1514,11); WHEN "0101010110" => manhi <= conv_std_logic_vector(5386615,24); manlo <= conv_std_logic_vector(198850796,28); exponent <= conv_std_logic_vector(1516,11); WHEN "0101010111" => manhi <= conv_std_logic_vector(13346554,24); manlo <= conv_std_logic_vector(143609986,28); exponent <= conv_std_logic_vector(1517,11); WHEN "0101011000" => manhi <= conv_std_logic_vector(3694008,24); manlo <= conv_std_logic_vector(137568494,28); exponent <= conv_std_logic_vector(1519,11); WHEN "0101011001" => manhi <= conv_std_logic_vector(11046062,24); manlo <= conv_std_logic_vector(214558683,28); exponent <= conv_std_logic_vector(1520,11); WHEN "0101011010" => manhi <= conv_std_logic_vector(2130662,24); manlo <= conv_std_logic_vector(78401205,28); exponent <= conv_std_logic_vector(1522,11); WHEN "0101011011" => manhi <= conv_std_logic_vector(8921254,24); manlo <= conv_std_logic_vector(265219821,28); exponent <= conv_std_logic_vector(1523,11); WHEN "0101011100" => manhi <= conv_std_logic_vector(686705,24); manlo <= conv_std_logic_vector(181591149,28); exponent <= conv_std_logic_vector(1525,11); WHEN "0101011101" => manhi <= conv_std_logic_vector(6958714,24); manlo <= conv_std_logic_vector(127078273,28); exponent <= conv_std_logic_vector(1526,11); WHEN "0101011110" => manhi <= conv_std_logic_vector(15483258,24); manlo <= conv_std_logic_vector(65420394,28); exponent <= conv_std_logic_vector(1527,11); WHEN "0101011111" => manhi <= conv_std_logic_vector(5146049,24); manlo <= conv_std_logic_vector(61347424,28); exponent <= conv_std_logic_vector(1529,11); WHEN "0101100000" => manhi <= conv_std_logic_vector(13019590,24); manlo <= conv_std_logic_vector(200148168,28); exponent <= conv_std_logic_vector(1530,11); WHEN "0101100001" => manhi <= conv_std_logic_vector(3471813,24); manlo <= conv_std_logic_vector(155873600,28); exponent <= conv_std_logic_vector(1532,11); WHEN "0101100010" => manhi <= conv_std_logic_vector(10744068,24); manlo <= conv_std_logic_vector(154763366,28); exponent <= conv_std_logic_vector(1533,11); WHEN "0101100011" => manhi <= conv_std_logic_vector(1925435,24); manlo <= conv_std_logic_vector(252346422,28); exponent <= conv_std_logic_vector(1535,11); WHEN "0101100100" => manhi <= conv_std_logic_vector(8642323,24); manlo <= conv_std_logic_vector(122496413,28); exponent <= conv_std_logic_vector(1536,11); WHEN "0101100101" => manhi <= conv_std_logic_vector(497152,24); manlo <= conv_std_logic_vector(12881703,28); exponent <= conv_std_logic_vector(1538,11); WHEN "0101100110" => manhi <= conv_std_logic_vector(6701084,24); manlo <= conv_std_logic_vector(102402698,28); exponent <= conv_std_logic_vector(1539,11); WHEN "0101100111" => manhi <= conv_std_logic_vector(15133102,24); manlo <= conv_std_logic_vector(173151546,28); exponent <= conv_std_logic_vector(1540,11); WHEN "0101101000" => manhi <= conv_std_logic_vector(4908093,24); manlo <= conv_std_logic_vector(222341698,28); exponent <= conv_std_logic_vector(1542,11); WHEN "0101101001" => manhi <= conv_std_logic_vector(12696175,24); manlo <= conv_std_logic_vector(221558290,28); exponent <= conv_std_logic_vector(1543,11); WHEN "0101101010" => manhi <= conv_std_logic_vector(3252030,24); manlo <= conv_std_logic_vector(95425703,28); exponent <= conv_std_logic_vector(1545,11); WHEN "0101101011" => manhi <= conv_std_logic_vector(10445352,24); manlo <= conv_std_logic_vector(54472775,28); exponent <= conv_std_logic_vector(1546,11); WHEN "0101101100" => manhi <= conv_std_logic_vector(1722437,24); manlo <= conv_std_logic_vector(31541381,28); exponent <= conv_std_logic_vector(1548,11); WHEN "0101101101" => manhi <= conv_std_logic_vector(8366419,24); manlo <= conv_std_logic_vector(121077564,28); exponent <= conv_std_logic_vector(1549,11); WHEN "0101101110" => manhi <= conv_std_logic_vector(309655,24); manlo <= conv_std_logic_vector(224679493,28); exponent <= conv_std_logic_vector(1551,11); WHEN "0101101111" => manhi <= conv_std_logic_vector(6446250,24); manlo <= conv_std_logic_vector(163707479,28); exponent <= conv_std_logic_vector(1552,11); WHEN "0101110000" => manhi <= conv_std_logic_vector(14786747,24); manlo <= conv_std_logic_vector(171718440,28); exponent <= conv_std_logic_vector(1553,11); WHEN "0101110001" => manhi <= conv_std_logic_vector(4672721,24); manlo <= conv_std_logic_vector(53414720,28); exponent <= conv_std_logic_vector(1555,11); WHEN "0101110010" => manhi <= conv_std_logic_vector(12376271,24); manlo <= conv_std_logic_vector(68395953,28); exponent <= conv_std_logic_vector(1556,11); WHEN "0101110011" => manhi <= conv_std_logic_vector(3034632,24); manlo <= conv_std_logic_vector(177229210,28); exponent <= conv_std_logic_vector(1558,11); WHEN "0101110100" => manhi <= conv_std_logic_vector(10149878,24); manlo <= conv_std_logic_vector(27015960,28); exponent <= conv_std_logic_vector(1559,11); WHEN "0101110101" => manhi <= conv_std_logic_vector(1521641,24); manlo <= conv_std_logic_vector(173609470,28); exponent <= conv_std_logic_vector(1561,11); WHEN "0101110110" => manhi <= conv_std_logic_vector(8093510,24); manlo <= conv_std_logic_vector(29891310,28); exponent <= conv_std_logic_vector(1562,11); WHEN "0101110111" => manhi <= conv_std_logic_vector(124194,24); manlo <= conv_std_logic_vector(191198183,28); exponent <= conv_std_logic_vector(1564,11); WHEN "0101111000" => manhi <= conv_std_logic_vector(6194182,24); manlo <= conv_std_logic_vector(216692261,28); exponent <= conv_std_logic_vector(1565,11); WHEN "0101111001" => manhi <= conv_std_logic_vector(14444151,24); manlo <= conv_std_logic_vector(261994424,28); exponent <= conv_std_logic_vector(1566,11); WHEN "0101111010" => manhi <= conv_std_logic_vector(4439903,24); manlo <= conv_std_logic_vector(82463931,28); exponent <= conv_std_logic_vector(1568,11); WHEN "0101111011" => manhi <= conv_std_logic_vector(12059838,24); manlo <= conv_std_logic_vector(250318074,28); exponent <= conv_std_logic_vector(1569,11); WHEN "0101111100" => manhi <= conv_std_logic_vector(2819594,24); manlo <= conv_std_logic_vector(161686084,28); exponent <= conv_std_logic_vector(1571,11); WHEN "0101111101" => manhi <= conv_std_logic_vector(9857611,24); manlo <= conv_std_logic_vector(20946108,28); exponent <= conv_std_logic_vector(1572,11); WHEN "0101111110" => manhi <= conv_std_logic_vector(1323025,24); manlo <= conv_std_logic_vector(164440795,28); exponent <= conv_std_logic_vector(1574,11); WHEN "0101111111" => manhi <= conv_std_logic_vector(7823562,24); manlo <= conv_std_logic_vector(250479918,28); exponent <= conv_std_logic_vector(1575,11); WHEN "0110000000" => manhi <= conv_std_logic_vector(16658709,24); manlo <= conv_std_logic_vector(45608811,28); exponent <= conv_std_logic_vector(1576,11); WHEN "0110000001" => manhi <= conv_std_logic_vector(5944850,24); manlo <= conv_std_logic_vector(255488281,28); exponent <= conv_std_logic_vector(1578,11); WHEN "0110000010" => manhi <= conv_std_logic_vector(14105274,24); manlo <= conv_std_logic_vector(228172930,28); exponent <= conv_std_logic_vector(1579,11); WHEN "0110000011" => manhi <= conv_std_logic_vector(4209612,24); manlo <= conv_std_logic_vector(113758652,28); exponent <= conv_std_logic_vector(1581,11); WHEN "0110000100" => manhi <= conv_std_logic_vector(11746841,24); manlo <= conv_std_logic_vector(45816542,28); exponent <= conv_std_logic_vector(1582,11); WHEN "0110000101" => manhi <= conv_std_logic_vector(2606890,24); manlo <= conv_std_logic_vector(153074390,28); exponent <= conv_std_logic_vector(1584,11); WHEN "0110000110" => manhi <= conv_std_logic_vector(9568516,24); manlo <= conv_std_logic_vector(87350878,28); exponent <= conv_std_logic_vector(1585,11); WHEN "0110000111" => manhi <= conv_std_logic_vector(1126565,24); manlo <= conv_std_logic_vector(96475766,28); exponent <= conv_std_logic_vector(1587,11); WHEN "0110001000" => manhi <= conv_std_logic_vector(7556545,24); manlo <= conv_std_logic_vector(205347948,28); exponent <= conv_std_logic_vector(1588,11); WHEN "0110001001" => manhi <= conv_std_logic_vector(16295795,24); manlo <= conv_std_logic_vector(56881285,28); exponent <= conv_std_logic_vector(1589,11); WHEN "0110001010" => manhi <= conv_std_logic_vector(5698225,24); manlo <= conv_std_logic_vector(93263076,28); exponent <= conv_std_logic_vector(1591,11); WHEN "0110001011" => manhi <= conv_std_logic_vector(13770075,24); manlo <= conv_std_logic_vector(241769289,28); exponent <= conv_std_logic_vector(1592,11); WHEN "0110001100" => manhi <= conv_std_logic_vector(3981821,24); manlo <= conv_std_logic_vector(32359920,28); exponent <= conv_std_logic_vector(1594,11); WHEN "0110001101" => manhi <= conv_std_logic_vector(11437240,24); manlo <= conv_std_logic_vector(185367850,28); exponent <= conv_std_logic_vector(1595,11); WHEN "0110001110" => manhi <= conv_std_logic_vector(2396495,24); manlo <= conv_std_logic_vector(61858550,28); exponent <= conv_std_logic_vector(1597,11); WHEN "0110001111" => manhi <= conv_std_logic_vector(9282559,24); manlo <= conv_std_logic_vector(110304027,28); exponent <= conv_std_logic_vector(1598,11); WHEN "0110010000" => manhi <= conv_std_logic_vector(932237,24); manlo <= conv_std_logic_vector(131077892,28); exponent <= conv_std_logic_vector(1600,11); WHEN "0110010001" => manhi <= conv_std_logic_vector(7292426,24); manlo <= conv_std_logic_vector(215982528,28); exponent <= conv_std_logic_vector(1601,11); WHEN "0110010010" => manhi <= conv_std_logic_vector(15936820,24); manlo <= conv_std_logic_vector(87676082,28); exponent <= conv_std_logic_vector(1602,11); WHEN "0110010011" => manhi <= conv_std_logic_vector(5454276,24); manlo <= conv_std_logic_vector(166577430,28); exponent <= conv_std_logic_vector(1604,11); WHEN "0110010100" => manhi <= conv_std_logic_vector(13438515,24); manlo <= conv_std_logic_vector(55023964,28); exponent <= conv_std_logic_vector(1605,11); WHEN "0110010101" => manhi <= conv_std_logic_vector(3756502,24); manlo <= conv_std_logic_vector(71679026,28); exponent <= conv_std_logic_vector(1607,11); WHEN "0110010110" => manhi <= conv_std_logic_vector(11131000,24); manlo <= conv_std_logic_vector(165886683,28); exponent <= conv_std_logic_vector(1608,11); WHEN "0110010111" => manhi <= conv_std_logic_vector(2188383,24); manlo <= conv_std_logic_vector(140750309,28); exponent <= conv_std_logic_vector(1610,11); WHEN "0110011000" => manhi <= conv_std_logic_vector(8999706,24); manlo <= conv_std_logic_vector(74200045,28); exponent <= conv_std_logic_vector(1611,11); WHEN "0110011001" => manhi <= conv_std_logic_vector(740018,24); manlo <= conv_std_logic_vector(229350227,28); exponent <= conv_std_logic_vector(1613,11); WHEN "0110011010" => manhi <= conv_std_logic_vector(7031174,24); manlo <= conv_std_logic_vector(159659309,28); exponent <= conv_std_logic_vector(1614,11); WHEN "0110011011" => manhi <= conv_std_logic_vector(15581741,24); manlo <= conv_std_logic_vector(203828183,28); exponent <= conv_std_logic_vector(1615,11); WHEN "0110011100" => manhi <= conv_std_logic_vector(5212975,24); manlo <= conv_std_logic_vector(192268981,28); exponent <= conv_std_logic_vector(1617,11); WHEN "0110011101" => manhi <= conv_std_logic_vector(13110553,24); manlo <= conv_std_logic_vector(73367990,28); exponent <= conv_std_logic_vector(1618,11); WHEN "0110011110" => manhi <= conv_std_logic_vector(3533629,24); manlo <= conv_std_logic_vector(7303751,28); exponent <= conv_std_logic_vector(1620,11); WHEN "0110011111" => manhi <= conv_std_logic_vector(10828084,24); manlo <= conv_std_logic_vector(128595197,28); exponent <= conv_std_logic_vector(1621,11); WHEN "0110100000" => manhi <= conv_std_logic_vector(1982530,24); manlo <= conv_std_logic_vector(178601213,28); exponent <= conv_std_logic_vector(1623,11); WHEN "0110100001" => manhi <= conv_std_logic_vector(8719923,24); manlo <= conv_std_logic_vector(62665264,28); exponent <= conv_std_logic_vector(1624,11); WHEN "0110100010" => manhi <= conv_std_logic_vector(549886,24); manlo <= conv_std_logic_vector(151395401,28); exponent <= conv_std_logic_vector(1626,11); WHEN "0110100011" => manhi <= conv_std_logic_vector(6772758,24); manlo <= conv_std_logic_vector(5307652,28); exponent <= conv_std_logic_vector(1627,11); WHEN "0110100100" => manhi <= conv_std_logic_vector(15230517,24); manlo <= conv_std_logic_vector(58871965,28); exponent <= conv_std_logic_vector(1628,11); WHEN "0110100101" => manhi <= conv_std_logic_vector(4974293,24); manlo <= conv_std_logic_vector(240265124,28); exponent <= conv_std_logic_vector(1630,11); WHEN "0110100110" => manhi <= conv_std_logic_vector(12786151,24); manlo <= conv_std_logic_vector(11983156,28); exponent <= conv_std_logic_vector(1631,11); WHEN "0110100111" => manhi <= conv_std_logic_vector(3313174,24); manlo <= conv_std_logic_vector(229882212,28); exponent <= conv_std_logic_vector(1633,11); WHEN "0110101000" => manhi <= conv_std_logic_vector(10528456,24); manlo <= conv_std_logic_vector(52550536,28); exponent <= conv_std_logic_vector(1634,11); WHEN "0110101001" => manhi <= conv_std_logic_vector(1778912,24); manlo <= conv_std_logic_vector(36481057,28); exponent <= conv_std_logic_vector(1636,11); WHEN "0110101010" => manhi <= conv_std_logic_vector(8443176,24); manlo <= conv_std_logic_vector(257480801,28); exponent <= conv_std_logic_vector(1637,11); WHEN "0110101011" => manhi <= conv_std_logic_vector(361817,24); manlo <= conv_std_logic_vector(260890045,28); exponent <= conv_std_logic_vector(1639,11); WHEN "0110101100" => manhi <= conv_std_logic_vector(6517146,24); manlo <= conv_std_logic_vector(80951272,28); exponent <= conv_std_logic_vector(1640,11); WHEN "0110101101" => manhi <= conv_std_logic_vector(14883104,24); manlo <= conv_std_logic_vector(234866389,28); exponent <= conv_std_logic_vector(1641,11); WHEN "0110101110" => manhi <= conv_std_logic_vector(4738202,24); manlo <= conv_std_logic_vector(195793257,28); exponent <= conv_std_logic_vector(1643,11); WHEN "0110101111" => manhi <= conv_std_logic_vector(12465269,24); manlo <= conv_std_logic_vector(236730454,28); exponent <= conv_std_logic_vector(1644,11); WHEN "0110110000" => manhi <= conv_std_logic_vector(3095113,24); manlo <= conv_std_logic_vector(133661452,28); exponent <= conv_std_logic_vector(1646,11); WHEN "0110110001" => manhi <= conv_std_logic_vector(10232080,24); manlo <= conv_std_logic_vector(21926822,28); exponent <= conv_std_logic_vector(1647,11); WHEN "0110110010" => manhi <= conv_std_logic_vector(1577503,24); manlo <= conv_std_logic_vector(183764948,28); exponent <= conv_std_logic_vector(1649,11); WHEN "0110110011" => manhi <= conv_std_logic_vector(8169434,24); manlo <= conv_std_logic_vector(132210812,28); exponent <= conv_std_logic_vector(1650,11); WHEN "0110110100" => manhi <= conv_std_logic_vector(175790,24); manlo <= conv_std_logic_vector(182183516,28); exponent <= conv_std_logic_vector(1652,11); WHEN "0110110101" => manhi <= conv_std_logic_vector(6264308,24); manlo <= conv_std_logic_vector(267417858,28); exponent <= conv_std_logic_vector(1653,11); WHEN "0110110110" => manhi <= conv_std_logic_vector(14539463,24); manlo <= conv_std_logic_vector(93573944,28); exponent <= conv_std_logic_vector(1654,11); WHEN "0110110111" => manhi <= conv_std_logic_vector(4504674,24); manlo <= conv_std_logic_vector(26907375,28); exponent <= conv_std_logic_vector(1656,11); WHEN "0110111000" => manhi <= conv_std_logic_vector(12147871,24); manlo <= conv_std_logic_vector(152302066,28); exponent <= conv_std_logic_vector(1657,11); WHEN "0110111001" => manhi <= conv_std_logic_vector(2879418,24); manlo <= conv_std_logic_vector(263131635,28); exponent <= conv_std_logic_vector(1659,11); WHEN "0110111010" => manhi <= conv_std_logic_vector(9938920,24); manlo <= conv_std_logic_vector(224874222,28); exponent <= conv_std_logic_vector(1660,11); WHEN "0110111011" => manhi <= conv_std_logic_vector(1378281,24); manlo <= conv_std_logic_vector(86745210,28); exponent <= conv_std_logic_vector(1662,11); WHEN "0110111100" => manhi <= conv_std_logic_vector(7898663,24); manlo <= conv_std_logic_vector(61761420,28); exponent <= conv_std_logic_vector(1663,11); WHEN "0110111101" => manhi <= conv_std_logic_vector(16760781,24); manlo <= conv_std_logic_vector(15082626,28); exponent <= conv_std_logic_vector(1664,11); WHEN "0110111110" => manhi <= conv_std_logic_vector(6014215,24); manlo <= conv_std_logic_vector(265801199,28); exponent <= conv_std_logic_vector(1666,11); WHEN "0110111111" => manhi <= conv_std_logic_vector(14199551,24); manlo <= conv_std_logic_vector(191056853,28); exponent <= conv_std_logic_vector(1667,11); WHEN "0111000000" => manhi <= conv_std_logic_vector(4273680,24); manlo <= conv_std_logic_vector(52024524,28); exponent <= conv_std_logic_vector(1669,11); WHEN "0111000001" => manhi <= conv_std_logic_vector(11833918,24); manlo <= conv_std_logic_vector(80047690,28); exponent <= conv_std_logic_vector(1670,11); WHEN "0111000010" => manhi <= conv_std_logic_vector(2666065,24); manlo <= conv_std_logic_vector(164712049,28); exponent <= conv_std_logic_vector(1672,11); WHEN "0111000011" => manhi <= conv_std_logic_vector(9648943,24); manlo <= conv_std_logic_vector(147084012,28); exponent <= conv_std_logic_vector(1673,11); WHEN "0111000100" => manhi <= conv_std_logic_vector(1181221,24); manlo <= conv_std_logic_vector(86912647,28); exponent <= conv_std_logic_vector(1675,11); WHEN "0111000101" => manhi <= conv_std_logic_vector(7630830,24); manlo <= conv_std_logic_vector(247596521,28); exponent <= conv_std_logic_vector(1676,11); WHEN "0111000110" => manhi <= conv_std_logic_vector(16396759,24); manlo <= conv_std_logic_vector(56002502,28); exponent <= conv_std_logic_vector(1677,11); WHEN "0111000111" => manhi <= conv_std_logic_vector(5766837,24); manlo <= conv_std_logic_vector(133369322,28); exponent <= conv_std_logic_vector(1679,11); WHEN "0111001000" => manhi <= conv_std_logic_vector(13863329,24); manlo <= conv_std_logic_vector(128884889,28); exponent <= conv_std_logic_vector(1680,11); WHEN "0111001001" => manhi <= conv_std_logic_vector(4045193,24); manlo <= conv_std_logic_vector(133729186,28); exponent <= conv_std_logic_vector(1682,11); WHEN "0111001010" => manhi <= conv_std_logic_vector(11523372,24); manlo <= conv_std_logic_vector(183024104,28); exponent <= conv_std_logic_vector(1683,11); WHEN "0111001011" => manhi <= conv_std_logic_vector(2455027,24); manlo <= conv_std_logic_vector(264977965,28); exponent <= conv_std_logic_vector(1685,11); WHEN "0111001100" => manhi <= conv_std_logic_vector(9362113,24); manlo <= conv_std_logic_vector(181285013,28); exponent <= conv_std_logic_vector(1686,11); WHEN "0111001101" => manhi <= conv_std_logic_vector(986300,24); manlo <= conv_std_logic_vector(58020653,28); exponent <= conv_std_logic_vector(1688,11); WHEN "0111001110" => manhi <= conv_std_logic_vector(7365905,24); manlo <= conv_std_logic_vector(179835810,28); exponent <= conv_std_logic_vector(1689,11); WHEN "0111001111" => manhi <= conv_std_logic_vector(16036688,24); manlo <= conv_std_logic_vector(123168298,28); exponent <= conv_std_logic_vector(1690,11); WHEN "0111010000" => manhi <= conv_std_logic_vector(5522144,24); manlo <= conv_std_logic_vector(14176725,28); exponent <= conv_std_logic_vector(1692,11); WHEN "0111010001" => manhi <= conv_std_logic_vector(13530756,24); manlo <= conv_std_logic_vector(163453775,28); exponent <= conv_std_logic_vector(1693,11); WHEN "0111010010" => manhi <= conv_std_logic_vector(3819186,24); manlo <= conv_std_logic_vector(214764608,28); exponent <= conv_std_logic_vector(1695,11); WHEN "0111010011" => manhi <= conv_std_logic_vector(11216197,24); manlo <= conv_std_logic_vector(196364225,28); exponent <= conv_std_logic_vector(1696,11); WHEN "0111010100" => manhi <= conv_std_logic_vector(2246280,24); manlo <= conv_std_logic_vector(259235483,28); exponent <= conv_std_logic_vector(1698,11); WHEN "0111010101" => manhi <= conv_std_logic_vector(9078397,24); manlo <= conv_std_logic_vector(15526664,28); exponent <= conv_std_logic_vector(1699,11); WHEN "0111010110" => manhi <= conv_std_logic_vector(793494,24); manlo <= conv_std_logic_vector(210641201,28); exponent <= conv_std_logic_vector(1701,11); WHEN "0111010111" => manhi <= conv_std_logic_vector(7103855,24); manlo <= conv_std_logic_vector(246847656,28); exponent <= conv_std_logic_vector(1702,11); WHEN "0111011000" => manhi <= conv_std_logic_vector(15680525,24); manlo <= conv_std_logic_vector(247378795,28); exponent <= conv_std_logic_vector(1703,11); WHEN "0111011001" => manhi <= conv_std_logic_vector(5280106,24); manlo <= conv_std_logic_vector(138122391,28); exponent <= conv_std_logic_vector(1705,11); WHEN "0111011010" => manhi <= conv_std_logic_vector(13201793,24); manlo <= conv_std_logic_vector(130963079,28); exponent <= conv_std_logic_vector(1706,11); WHEN "0111011011" => manhi <= conv_std_logic_vector(3595633,24); manlo <= conv_std_logic_vector(48727293,28); exponent <= conv_std_logic_vector(1708,11); WHEN "0111011100" => manhi <= conv_std_logic_vector(10912356,24); manlo <= conv_std_logic_vector(231400966,28); exponent <= conv_std_logic_vector(1709,11); WHEN "0111011101" => manhi <= conv_std_logic_vector(2039799,24); manlo <= conv_std_logic_vector(184459756,28); exponent <= conv_std_logic_vector(1711,11); WHEN "0111011110" => manhi <= conv_std_logic_vector(8797759,24); manlo <= conv_std_logic_vector(242699544,28); exponent <= conv_std_logic_vector(1712,11); WHEN "0111011111" => manhi <= conv_std_logic_vector(602782,24); manlo <= conv_std_logic_vector(17680793,28); exponent <= conv_std_logic_vector(1714,11); WHEN "0111100000" => manhi <= conv_std_logic_vector(6844650,24); manlo <= conv_std_logic_vector(123627565,28); exponent <= conv_std_logic_vector(1715,11); WHEN "0111100001" => manhi <= conv_std_logic_vector(15328229,24); manlo <= conv_std_logic_vector(47512453,28); exponent <= conv_std_logic_vector(1716,11); WHEN "0111100010" => manhi <= conv_std_logic_vector(5040696,24); manlo <= conv_std_logic_vector(14711664,28); exponent <= conv_std_logic_vector(1718,11); WHEN "0111100011" => manhi <= conv_std_logic_vector(12876400,24); manlo <= conv_std_logic_vector(251456186,28); exponent <= conv_std_logic_vector(1719,11); WHEN "0111100100" => manhi <= conv_std_logic_vector(3374506,24); manlo <= conv_std_logic_vector(4512772,28); exponent <= conv_std_logic_vector(1721,11); WHEN "0111100101" => manhi <= conv_std_logic_vector(10611813,24); manlo <= conv_std_logic_vector(237626642,28); exponent <= conv_std_logic_vector(1722,11); WHEN "0111100110" => manhi <= conv_std_logic_vector(1835559,24); manlo <= conv_std_logic_vector(150064655,28); exponent <= conv_std_logic_vector(1724,11); WHEN "0111100111" => manhi <= conv_std_logic_vector(8520168,24); manlo <= conv_std_logic_vector(211971382,28); exponent <= conv_std_logic_vector(1725,11); WHEN "0111101000" => manhi <= conv_std_logic_vector(414139,24); manlo <= conv_std_logic_vector(92694471,28); exponent <= conv_std_logic_vector(1727,11); WHEN "0111101001" => manhi <= conv_std_logic_vector(6588258,24); manlo <= conv_std_logic_vector(112977613,28); exponent <= conv_std_logic_vector(1728,11); WHEN "0111101010" => manhi <= conv_std_logic_vector(14979756,24); manlo <= conv_std_logic_vector(71348470,28); exponent <= conv_std_logic_vector(1729,11); WHEN "0111101011" => manhi <= conv_std_logic_vector(4803884,24); manlo <= conv_std_logic_vector(42747344,28); exponent <= conv_std_logic_vector(1731,11); WHEN "0111101100" => manhi <= conv_std_logic_vector(12554540,24); manlo <= conv_std_logic_vector(53825836,28); exponent <= conv_std_logic_vector(1732,11); WHEN "0111101101" => manhi <= conv_std_logic_vector(3155778,24); manlo <= conv_std_logic_vector(260157975,28); exponent <= conv_std_logic_vector(1734,11); WHEN "0111101110" => manhi <= conv_std_logic_vector(10314533,24); manlo <= conv_std_logic_vector(1535990,28); exponent <= conv_std_logic_vector(1735,11); WHEN "0111101111" => manhi <= conv_std_logic_vector(1633536,24); manlo <= conv_std_logic_vector(68681060,28); exponent <= conv_std_logic_vector(1737,11); WHEN "0111110000" => manhi <= conv_std_logic_vector(8245590,24); manlo <= conv_std_logic_vector(175202070,28); exponent <= conv_std_logic_vector(1738,11); WHEN "0111110001" => manhi <= conv_std_logic_vector(227544,24); manlo <= conv_std_logic_vector(41675965,28); exponent <= conv_std_logic_vector(1740,11); WHEN "0111110010" => manhi <= conv_std_logic_vector(6334649,24); manlo <= conv_std_logic_vector(70777607,28); exponent <= conv_std_logic_vector(1741,11); WHEN "0111110011" => manhi <= conv_std_logic_vector(14635065,24); manlo <= conv_std_logic_vector(183612561,28); exponent <= conv_std_logic_vector(1742,11); WHEN "0111110100" => manhi <= conv_std_logic_vector(4569642,24); manlo <= conv_std_logic_vector(167240760,28); exponent <= conv_std_logic_vector(1744,11); WHEN "0111110101" => manhi <= conv_std_logic_vector(12236172,24); manlo <= conv_std_logic_vector(253623266,28); exponent <= conv_std_logic_vector(1745,11); WHEN "0111110110" => manhi <= conv_std_logic_vector(2939425,24); manlo <= conv_std_logic_vector(265128301,28); exponent <= conv_std_logic_vector(1747,11); WHEN "0111110111" => manhi <= conv_std_logic_vector(10020478,24); manlo <= conv_std_logic_vector(219223569,28); exponent <= conv_std_logic_vector(1748,11); WHEN "0111111000" => manhi <= conv_std_logic_vector(1433705,24); manlo <= conv_std_logic_vector(192250058,28); exponent <= conv_std_logic_vector(1750,11); WHEN "0111111001" => manhi <= conv_std_logic_vector(7973992,24); manlo <= conv_std_logic_vector(212144821,28); exponent <= conv_std_logic_vector(1751,11); WHEN "0111111010" => manhi <= conv_std_logic_vector(42974,24); manlo <= conv_std_logic_vector(72952107,28); exponent <= conv_std_logic_vector(1753,11); WHEN "0111111011" => manhi <= conv_std_logic_vector(6083792,24); manlo <= conv_std_logic_vector(210315148,28); exponent <= conv_std_logic_vector(1754,11); WHEN "0111111100" => manhi <= conv_std_logic_vector(14294116,24); manlo <= conv_std_logic_vector(101520926,28); exponent <= conv_std_logic_vector(1755,11); WHEN "0111111101" => manhi <= conv_std_logic_vector(4337943,24); manlo <= conv_std_logic_vector(146945490,28); exponent <= conv_std_logic_vector(1757,11); WHEN "0111111110" => manhi <= conv_std_logic_vector(11921261,24); manlo <= conv_std_logic_vector(67478049,28); exponent <= conv_std_logic_vector(1758,11); WHEN "0111111111" => manhi <= conv_std_logic_vector(2725421,24); manlo <= conv_std_logic_vector(81662013,28); exponent <= conv_std_logic_vector(1760,11); WHEN "1000000000" => manhi <= conv_std_logic_vector(9729616,24); manlo <= conv_std_logic_vector(79332654,28); exponent <= conv_std_logic_vector(1761,11); WHEN "1000000001" => manhi <= conv_std_logic_vector(1236044,24); manlo <= conv_std_logic_vector(37511845,28); exponent <= conv_std_logic_vector(1763,11); WHEN "1000000010" => manhi <= conv_std_logic_vector(7705342,24); manlo <= conv_std_logic_vector(229400607,28); exponent <= conv_std_logic_vector(1764,11); WHEN "1000000011" => manhi <= conv_std_logic_vector(16498031,24); manlo <= conv_std_logic_vector(113896411,28); exponent <= conv_std_logic_vector(1765,11); WHEN "1000000100" => manhi <= conv_std_logic_vector(5835659,24); manlo <= conv_std_logic_vector(27578100,28); exponent <= conv_std_logic_vector(1767,11); WHEN "1000000101" => manhi <= conv_std_logic_vector(13956867,24); manlo <= conv_std_logic_vector(198774093,28); exponent <= conv_std_logic_vector(1768,11); WHEN "1000000110" => manhi <= conv_std_logic_vector(4108759,24); manlo <= conv_std_logic_vector(90336304,28); exponent <= conv_std_logic_vector(1770,11); WHEN "1000000111" => manhi <= conv_std_logic_vector(11609767,24); manlo <= conv_std_logic_vector(164675818,28); exponent <= conv_std_logic_vector(1771,11); WHEN "1000001000" => manhi <= conv_std_logic_vector(2513739,24); manlo <= conv_std_logic_vector(115510945,28); exponent <= conv_std_logic_vector(1773,11); WHEN "1000001001" => manhi <= conv_std_logic_vector(9441910,24); manlo <= conv_std_logic_vector(214725537,28); exponent <= conv_std_logic_vector(1774,11); WHEN "1000001010" => manhi <= conv_std_logic_vector(1040527,24); manlo <= conv_std_logic_vector(264292986,28); exponent <= conv_std_logic_vector(1776,11); WHEN "1000001011" => manhi <= conv_std_logic_vector(7439608,24); manlo <= conv_std_logic_vector(227819416,28); exponent <= conv_std_logic_vector(1777,11); WHEN "1000001100" => manhi <= conv_std_logic_vector(16136861,24); manlo <= conv_std_logic_vector(124712281,28); exponent <= conv_std_logic_vector(1778,11); WHEN "1000001101" => manhi <= conv_std_logic_vector(5590218,24); manlo <= conv_std_logic_vector(179347558,28); exponent <= conv_std_logic_vector(1780,11); WHEN "1000001110" => manhi <= conv_std_logic_vector(13623279,24); manlo <= conv_std_logic_vector(162081347,28); exponent <= conv_std_logic_vector(1781,11); WHEN "1000001111" => manhi <= conv_std_logic_vector(3882062,24); manlo <= conv_std_logic_vector(186291443,28); exponent <= conv_std_logic_vector(1783,11); WHEN "1000010000" => manhi <= conv_std_logic_vector(11301654,24); manlo <= conv_std_logic_vector(250040022,28); exponent <= conv_std_logic_vector(1784,11); WHEN "1000010001" => manhi <= conv_std_logic_vector(2304355,24); manlo <= conv_std_logic_vector(41383777,28); exponent <= conv_std_logic_vector(1786,11); WHEN "1000010010" => manhi <= conv_std_logic_vector(9157328,24); manlo <= conv_std_logic_vector(17021400,28); exponent <= conv_std_logic_vector(1787,11); WHEN "1000010011" => manhi <= conv_std_logic_vector(847133,24); manlo <= conv_std_logic_vector(258834653,28); exponent <= conv_std_logic_vector(1789,11); WHEN "1000010100" => manhi <= conv_std_logic_vector(7176759,24); manlo <= conv_std_logic_vector(33041815,28); exponent <= conv_std_logic_vector(1790,11); WHEN "1000010101" => manhi <= conv_std_logic_vector(15779611,24); manlo <= conv_std_logic_vector(174007449,28); exponent <= conv_std_logic_vector(1791,11); WHEN "1000010110" => manhi <= conv_std_logic_vector(5347442,24); manlo <= conv_std_logic_vector(66333886,28); exponent <= conv_std_logic_vector(1793,11); WHEN "1000010111" => manhi <= conv_std_logic_vector(13293312,24); manlo <= conv_std_logic_vector(63618366,28); exponent <= conv_std_logic_vector(1794,11); WHEN "1000011000" => manhi <= conv_std_logic_vector(3657826,24); manlo <= conv_std_logic_vector(166348998,28); exponent <= conv_std_logic_vector(1796,11); WHEN "1000011001" => manhi <= conv_std_logic_vector(10996886,24); manlo <= conv_std_logic_vector(136487624,28); exponent <= conv_std_logic_vector(1797,11); WHEN "1000011010" => manhi <= conv_std_logic_vector(2097243,24); manlo <= conv_std_logic_vector(144317262,28); exponent <= conv_std_logic_vector(1799,11); WHEN "1000011011" => manhi <= conv_std_logic_vector(8875834,24); manlo <= conv_std_logic_vector(51419886,28); exponent <= conv_std_logic_vector(1800,11); WHEN "1000011100" => manhi <= conv_std_logic_vector(655839,24); manlo <= conv_std_logic_vector(12096311,28); exponent <= conv_std_logic_vector(1802,11); WHEN "1000011101" => manhi <= conv_std_logic_vector(6916762,24); manlo <= conv_std_logic_vector(99793437,28); exponent <= conv_std_logic_vector(1803,11); WHEN "1000011110" => manhi <= conv_std_logic_vector(15426239,24); manlo <= conv_std_logic_vector(114334116,28); exponent <= conv_std_logic_vector(1804,11); WHEN "1000011111" => manhi <= conv_std_logic_vector(5107300,24); manlo <= conv_std_logic_vector(248161218,28); exponent <= conv_std_logic_vector(1806,11); WHEN "1000100000" => manhi <= conv_std_logic_vector(12966926,24); manlo <= conv_std_logic_vector(91321506,28); exponent <= conv_std_logic_vector(1807,11); WHEN "1000100001" => manhi <= conv_std_logic_vector(3436024,24); manlo <= conv_std_logic_vector(109150055,28); exponent <= conv_std_logic_vector(1809,11); WHEN "1000100010" => manhi <= conv_std_logic_vector(10695426,24); manlo <= conv_std_logic_vector(12291314,28); exponent <= conv_std_logic_vector(1810,11); WHEN "1000100011" => manhi <= conv_std_logic_vector(1892379,24); manlo <= conv_std_logic_vector(245137096,28); exponent <= conv_std_logic_vector(1812,11); WHEN "1000100100" => manhi <= conv_std_logic_vector(8597395,24); manlo <= conv_std_logic_vector(176569250,28); exponent <= conv_std_logic_vector(1813,11); WHEN "1000100101" => manhi <= conv_std_logic_vector(466620,24); manlo <= conv_std_logic_vector(119019308,28); exponent <= conv_std_logic_vector(1815,11); WHEN "1000100110" => manhi <= conv_std_logic_vector(6659587,24); manlo <= conv_std_logic_vector(168706814,28); exponent <= conv_std_logic_vector(1816,11); WHEN "1000100111" => manhi <= conv_std_logic_vector(15076702,24); manlo <= conv_std_logic_vector(190651618,28); exponent <= conv_std_logic_vector(1817,11); WHEN "1000101000" => manhi <= conv_std_logic_vector(4869766,24); manlo <= conv_std_logic_vector(26523901,28); exponent <= conv_std_logic_vector(1819,11); WHEN "1000101001" => manhi <= conv_std_logic_vector(12644083,24); manlo <= conv_std_logic_vector(10760420,28); exponent <= conv_std_logic_vector(1820,11); WHEN "1000101010" => manhi <= conv_std_logic_vector(3216629,24); manlo <= conv_std_logic_vector(171149379,28); exponent <= conv_std_logic_vector(1822,11); WHEN "1000101011" => manhi <= conv_std_logic_vector(10397237,24); manlo <= conv_std_logic_vector(171483537,28); exponent <= conv_std_logic_vector(1823,11); WHEN "1000101100" => manhi <= conv_std_logic_vector(1689739,24); manlo <= conv_std_logic_vector(236540182,28); exponent <= conv_std_logic_vector(1825,11); WHEN "1000101101" => manhi <= conv_std_logic_vector(8321979,24); manlo <= conv_std_logic_vector(80365386,28); exponent <= conv_std_logic_vector(1826,11); WHEN "1000101110" => manhi <= conv_std_logic_vector(279455,24); manlo <= conv_std_logic_vector(167185714,28); exponent <= conv_std_logic_vector(1828,11); WHEN "1000101111" => manhi <= conv_std_logic_vector(6405204,24); manlo <= conv_std_logic_vector(70637708,28); exponent <= conv_std_logic_vector(1829,11); WHEN "1000110000" => manhi <= conv_std_logic_vector(14730959,24); manlo <= conv_std_logic_vector(233674466,28); exponent <= conv_std_logic_vector(1830,11); WHEN "1000110001" => manhi <= conv_std_logic_vector(4634809,24); manlo <= conv_std_logic_vector(128626627,28); exponent <= conv_std_logic_vector(1832,11); WHEN "1000110010" => manhi <= conv_std_logic_vector(12324743,24); manlo <= conv_std_logic_vector(237637056,28); exponent <= conv_std_logic_vector(1833,11); WHEN "1000110011" => manhi <= conv_std_logic_vector(2999616,24); manlo <= conv_std_logic_vector(48899908,28); exponent <= conv_std_logic_vector(1835,11); WHEN "1000110100" => manhi <= conv_std_logic_vector(10102285,24); manlo <= conv_std_logic_vector(207402206,28); exponent <= conv_std_logic_vector(1836,11); WHEN "1000110101" => manhi <= conv_std_logic_vector(1489299,24); manlo <= conv_std_logic_vector(82314533,28); exponent <= conv_std_logic_vector(1838,11); WHEN "1000110110" => manhi <= conv_std_logic_vector(8049552,24); manlo <= conv_std_logic_vector(84197942,28); exponent <= conv_std_logic_vector(1839,11); WHEN "1000110111" => manhi <= conv_std_logic_vector(94322,24); manlo <= conv_std_logic_vector(78275083,28); exponent <= conv_std_logic_vector(1841,11); WHEN "1000111000" => manhi <= conv_std_logic_vector(6153581,24); manlo <= conv_std_logic_vector(262556746,28); exponent <= conv_std_logic_vector(1842,11); WHEN "1000111001" => manhi <= conv_std_logic_vector(14388969,24); manlo <= conv_std_logic_vector(195412276,28); exponent <= conv_std_logic_vector(1843,11); WHEN "1000111010" => manhi <= conv_std_logic_vector(4402403,24); manlo <= conv_std_logic_vector(21925377,28); exponent <= conv_std_logic_vector(1845,11); WHEN "1000111011" => manhi <= conv_std_logic_vector(12008870,24); manlo <= conv_std_logic_vector(225943576,28); exponent <= conv_std_logic_vector(1846,11); WHEN "1000111100" => manhi <= conv_std_logic_vector(2784958,24); manlo <= conv_std_logic_vector(51959162,28); exponent <= conv_std_logic_vector(1848,11); WHEN "1000111101" => manhi <= conv_std_logic_vector(9810535,24); manlo <= conv_std_logic_vector(85297068,28); exponent <= conv_std_logic_vector(1849,11); WHEN "1000111110" => manhi <= conv_std_logic_vector(1291034,24); manlo <= conv_std_logic_vector(85003113,28); exponent <= conv_std_logic_vector(1851,11); WHEN "1000111111" => manhi <= conv_std_logic_vector(7780082,24); manlo <= conv_std_logic_vector(68159752,28); exponent <= conv_std_logic_vector(1852,11); WHEN "1001000000" => manhi <= conv_std_logic_vector(16599612,24); manlo <= conv_std_logic_vector(214703512,28); exponent <= conv_std_logic_vector(1853,11); WHEN "1001000001" => manhi <= conv_std_logic_vector(5904690,24); manlo <= conv_std_logic_vector(215968023,28); exponent <= conv_std_logic_vector(1855,11); WHEN "1001000010" => manhi <= conv_std_logic_vector(14050691,24); manlo <= conv_std_logic_vector(147853227,28); exponent <= conv_std_logic_vector(1856,11); WHEN "1001000011" => manhi <= conv_std_logic_vector(4172519,24); manlo <= conv_std_logic_vector(60716388,28); exponent <= conv_std_logic_vector(1858,11); WHEN "1001000100" => manhi <= conv_std_logic_vector(11696426,24); manlo <= conv_std_logic_vector(77359100,28); exponent <= conv_std_logic_vector(1859,11); WHEN "1001000101" => manhi <= conv_std_logic_vector(2572630,24); manlo <= conv_std_logic_vector(28321055,28); exponent <= conv_std_logic_vector(1861,11); WHEN "1001000110" => manhi <= conv_std_logic_vector(9521951,24); manlo <= conv_std_logic_vector(141206574,28); exponent <= conv_std_logic_vector(1862,11); WHEN "1001000111" => manhi <= conv_std_logic_vector(1094921,24); manlo <= conv_std_logic_vector(79834212,28); exponent <= conv_std_logic_vector(1864,11); WHEN "1001001000" => manhi <= conv_std_logic_vector(7513537,24); manlo <= conv_std_logic_vector(6880382,28); exponent <= conv_std_logic_vector(1865,11); WHEN "1001001001" => manhi <= conv_std_logic_vector(16237340,24); manlo <= conv_std_logic_vector(73707069,28); exponent <= conv_std_logic_vector(1866,11); WHEN "1001001010" => manhi <= conv_std_logic_vector(5658501,24); manlo <= conv_std_logic_vector(26563701,28); exponent <= conv_std_logic_vector(1868,11); WHEN "1001001011" => manhi <= conv_std_logic_vector(13716085,24); manlo <= conv_std_logic_vector(13226359,28); exponent <= conv_std_logic_vector(1869,11); WHEN "1001001100" => manhi <= conv_std_logic_vector(3945130,24); manlo <= conv_std_logic_vector(143073903,28); exponent <= conv_std_logic_vector(1871,11); WHEN "1001001101" => manhi <= conv_std_logic_vector(11387373,24); manlo <= conv_std_logic_vector(3175990,28); exponent <= conv_std_logic_vector(1872,11); WHEN "1001001110" => manhi <= conv_std_logic_vector(2362606,24); manlo <= conv_std_logic_vector(168904878,28); exponent <= conv_std_logic_vector(1874,11); WHEN "1001001111" => manhi <= conv_std_logic_vector(9236500,24); manlo <= conv_std_logic_vector(7105104,28); exponent <= conv_std_logic_vector(1875,11); WHEN "1001010000" => manhi <= conv_std_logic_vector(900936,24); manlo <= conv_std_logic_vector(239272854,28); exponent <= conv_std_logic_vector(1877,11); WHEN "1001010001" => manhi <= conv_std_logic_vector(7249884,24); manlo <= conv_std_logic_vector(236935482,28); exponent <= conv_std_logic_vector(1878,11); WHEN "1001010010" => manhi <= conv_std_logic_vector(15878999,24); manlo <= conv_std_logic_vector(230836932,28); exponent <= conv_std_logic_vector(1879,11); WHEN "1001010011" => manhi <= conv_std_logic_vector(5414983,24); manlo <= conv_std_logic_vector(144840810,28); exponent <= conv_std_logic_vector(1881,11); WHEN "1001010100" => manhi <= conv_std_logic_vector(13385110,24); manlo <= conv_std_logic_vector(99584369,28); exponent <= conv_std_logic_vector(1882,11); WHEN "1001010101" => manhi <= conv_std_logic_vector(3720209,24); manlo <= conv_std_logic_vector(246845719,28); exponent <= conv_std_logic_vector(1884,11); WHEN "1001010110" => manhi <= conv_std_logic_vector(11081674,24); manlo <= conv_std_logic_vector(54674652,28); exponent <= conv_std_logic_vector(1885,11); WHEN "1001010111" => manhi <= conv_std_logic_vector(2154862,24); manlo <= conv_std_logic_vector(201440422,28); exponent <= conv_std_logic_vector(1887,11); WHEN "1001011000" => manhi <= conv_std_logic_vector(8954146,24); manlo <= conv_std_logic_vector(220416825,28); exponent <= conv_std_logic_vector(1888,11); WHEN "1001011001" => manhi <= conv_std_logic_vector(709057,24); manlo <= conv_std_logic_vector(266967657,28); exponent <= conv_std_logic_vector(1890,11); WHEN "1001011010" => manhi <= conv_std_logic_vector(6989094,24); manlo <= conv_std_logic_vector(113654547,28); exponent <= conv_std_logic_vector(1891,11); WHEN "1001011011" => manhi <= conv_std_logic_vector(15524548,24); manlo <= conv_std_logic_vector(235342013,28); exponent <= conv_std_logic_vector(1892,11); WHEN "1001011100" => manhi <= conv_std_logic_vector(5174109,24); manlo <= conv_std_logic_vector(32986511,28); exponent <= conv_std_logic_vector(1894,11); WHEN "1001011101" => manhi <= conv_std_logic_vector(13057728,24); manlo <= conv_std_logic_vector(25787653,28); exponent <= conv_std_logic_vector(1895,11); WHEN "1001011110" => manhi <= conv_std_logic_vector(3497730,24); manlo <= conv_std_logic_vector(160351868,28); exponent <= conv_std_logic_vector(1897,11); WHEN "1001011111" => manhi <= conv_std_logic_vector(10779293,24); manlo <= conv_std_logic_vector(121946709,28); exponent <= conv_std_logic_vector(1898,11); WHEN "1001100000" => manhi <= conv_std_logic_vector(1949373,24); manlo <= conv_std_logic_vector(194974600,28); exponent <= conv_std_logic_vector(1900,11); WHEN "1001100001" => manhi <= conv_std_logic_vector(8674858,24); manlo <= conv_std_logic_vector(75445083,28); exponent <= conv_std_logic_vector(1901,11); WHEN "1001100010" => manhi <= conv_std_logic_vector(519261,24); manlo <= conv_std_logic_vector(202318540,28); exponent <= conv_std_logic_vector(1903,11); WHEN "1001100011" => manhi <= conv_std_logic_vector(6731134,24); manlo <= conv_std_logic_vector(157600610,28); exponent <= conv_std_logic_vector(1904,11); WHEN "1001100100" => manhi <= conv_std_logic_vector(15173945,24); manlo <= conv_std_logic_vector(29256816,28); exponent <= conv_std_logic_vector(1905,11); WHEN "1001100101" => manhi <= conv_std_logic_vector(4935849,24); manlo <= conv_std_logic_vector(42999013,28); exponent <= conv_std_logic_vector(1907,11); WHEN "1001100110" => manhi <= conv_std_logic_vector(12733899,24); manlo <= conv_std_logic_vector(62421287,28); exponent <= conv_std_logic_vector(1908,11); WHEN "1001100111" => manhi <= conv_std_logic_vector(3277666,24); manlo <= conv_std_logic_vector(18399062,28); exponent <= conv_std_logic_vector(1910,11); WHEN "1001101000" => manhi <= conv_std_logic_vector(10480194,24); manlo <= conv_std_logic_vector(201166396,28); exponent <= conv_std_logic_vector(1911,11); WHEN "1001101001" => manhi <= conv_std_logic_vector(1746115,24); manlo <= conv_std_logic_vector(22209480,28); exponent <= conv_std_logic_vector(1913,11); WHEN "1001101010" => manhi <= conv_std_logic_vector(8398601,24); manlo <= conv_std_logic_vector(38216343,28); exponent <= conv_std_logic_vector(1914,11); WHEN "1001101011" => manhi <= conv_std_logic_vector(331525,24); manlo <= conv_std_logic_vector(151310615,28); exponent <= conv_std_logic_vector(1916,11); WHEN "1001101100" => manhi <= conv_std_logic_vector(6475974,24); manlo <= conv_std_logic_vector(174528998,28); exponent <= conv_std_logic_vector(1917,11); WHEN "1001101101" => manhi <= conv_std_logic_vector(14827146,24); manlo <= conv_std_logic_vector(214487191,28); exponent <= conv_std_logic_vector(1918,11); WHEN "1001101110" => manhi <= conv_std_logic_vector(4700175,24); manlo <= conv_std_logic_vector(73593076,28); exponent <= conv_std_logic_vector(1920,11); WHEN "1001101111" => manhi <= conv_std_logic_vector(12413585,24); manlo <= conv_std_logic_vector(56806573,28); exponent <= conv_std_logic_vector(1921,11); WHEN "1001110000" => manhi <= conv_std_logic_vector(3059990,24); manlo <= conv_std_logic_vector(32998071,28); exponent <= conv_std_logic_vector(1923,11); WHEN "1001110001" => manhi <= conv_std_logic_vector(10184342,24); manlo <= conv_std_logic_vector(125003687,28); exponent <= conv_std_logic_vector(1924,11); WHEN "1001110010" => manhi <= conv_std_logic_vector(1545062,24); manlo <= conv_std_logic_vector(164026180,28); exponent <= conv_std_logic_vector(1926,11); WHEN "1001110011" => manhi <= conv_std_logic_vector(8125342,24); manlo <= conv_std_logic_vector(134803968,28); exponent <= conv_std_logic_vector(1927,11); WHEN "1001110100" => manhi <= conv_std_logic_vector(145827,24); manlo <= conv_std_logic_vector(17356019,28); exponent <= conv_std_logic_vector(1929,11); WHEN "1001110101" => manhi <= conv_std_logic_vector(6223584,24); manlo <= conv_std_logic_vector(59711433,28); exponent <= conv_std_logic_vector(1930,11); WHEN "1001110110" => manhi <= conv_std_logic_vector(14484112,24); manlo <= conv_std_logic_vector(172427100,28); exponent <= conv_std_logic_vector(1931,11); WHEN "1001110111" => manhi <= conv_std_logic_vector(4467059,24); manlo <= conv_std_logic_vector(106163660,28); exponent <= conv_std_logic_vector(1933,11); WHEN "1001111000" => manhi <= conv_std_logic_vector(12096747,24); manlo <= conv_std_logic_vector(237074316,28); exponent <= conv_std_logic_vector(1934,11); WHEN "1001111001" => manhi <= conv_std_logic_vector(2844676,24); manlo <= conv_std_logic_vector(224090291,28); exponent <= conv_std_logic_vector(1936,11); WHEN "1001111010" => manhi <= conv_std_logic_vector(9891701,24); manlo <= conv_std_logic_vector(98356275,28); exponent <= conv_std_logic_vector(1937,11); WHEN "1001111011" => manhi <= conv_std_logic_vector(1346192,24); manlo <= conv_std_logic_vector(98098154,28); exponent <= conv_std_logic_vector(1939,11); WHEN "1001111100" => manhi <= conv_std_logic_vector(7855049,24); manlo <= conv_std_logic_vector(218711727,28); exponent <= conv_std_logic_vector(1940,11); WHEN "1001111101" => manhi <= conv_std_logic_vector(16701504,24); manlo <= conv_std_logic_vector(74899902,28); exponent <= conv_std_logic_vector(1941,11); WHEN "1001111110" => manhi <= conv_std_logic_vector(5973933,24); manlo <= conv_std_logic_vector(65399866,28); exponent <= conv_std_logic_vector(1943,11); WHEN "1001111111" => manhi <= conv_std_logic_vector(14144801,24); manlo <= conv_std_logic_vector(210121699,28); exponent <= conv_std_logic_vector(1944,11); WHEN "1010000000" => manhi <= conv_std_logic_vector(4236473,24); manlo <= conv_std_logic_vector(203888522,28); exponent <= conv_std_logic_vector(1946,11); WHEN "1010000001" => manhi <= conv_std_logic_vector(11783349,24); manlo <= conv_std_logic_vector(137203293,28); exponent <= conv_std_logic_vector(1947,11); WHEN "1010000010" => manhi <= conv_std_logic_vector(2631700,24); manlo <= conv_std_logic_vector(150283410,28); exponent <= conv_std_logic_vector(1949,11); WHEN "1010000011" => manhi <= conv_std_logic_vector(9602236,24); manlo <= conv_std_logic_vector(160352104,28); exponent <= conv_std_logic_vector(1950,11); WHEN "1010000100" => manhi <= conv_std_logic_vector(1149480,24); manlo <= conv_std_logic_vector(177173803,28); exponent <= conv_std_logic_vector(1952,11); WHEN "1010000101" => manhi <= conv_std_logic_vector(7587690,24); manlo <= conv_std_logic_vector(238268718,28); exponent <= conv_std_logic_vector(1953,11); WHEN "1010000110" => manhi <= conv_std_logic_vector(16338125,24); manlo <= conv_std_logic_vector(220749839,28); exponent <= conv_std_logic_vector(1954,11); WHEN "1010000111" => manhi <= conv_std_logic_vector(5726991,24); manlo <= conv_std_logic_vector(262994505,28); exponent <= conv_std_logic_vector(1956,11); WHEN "1010001000" => manhi <= conv_std_logic_vector(13809173,24); manlo <= conv_std_logic_vector(216783842,28); exponent <= conv_std_logic_vector(1957,11); WHEN "1010001001" => manhi <= conv_std_logic_vector(4008390,24); manlo <= conv_std_logic_vector(242405077,28); exponent <= conv_std_logic_vector(1959,11); WHEN "1010001010" => manhi <= conv_std_logic_vector(11473352,24); manlo <= conv_std_logic_vector(206426515,28); exponent <= conv_std_logic_vector(1960,11); WHEN "1010001011" => manhi <= conv_std_logic_vector(2421035,24); manlo <= conv_std_logic_vector(250208807,28); exponent <= conv_std_logic_vector(1962,11); WHEN "1010001100" => manhi <= conv_std_logic_vector(9315913,24); manlo <= conv_std_logic_vector(183235034,28); exponent <= conv_std_logic_vector(1963,11); WHEN "1010001101" => manhi <= conv_std_logic_vector(954904,24); manlo <= conv_std_logic_vector(17706469,28); exponent <= conv_std_logic_vector(1965,11); WHEN "1010001110" => manhi <= conv_std_logic_vector(7323233,24); manlo <= conv_std_logic_vector(235600136,28); exponent <= conv_std_logic_vector(1966,11); WHEN "1010001111" => manhi <= conv_std_logic_vector(15978691,24); manlo <= conv_std_logic_vector(128873524,28); exponent <= conv_std_logic_vector(1967,11); WHEN "1010010000" => manhi <= conv_std_logic_vector(5482731,24); manlo <= conv_std_logic_vector(5222268,28); exponent <= conv_std_logic_vector(1969,11); WHEN "1010010001" => manhi <= conv_std_logic_vector(13477188,24); manlo <= conv_std_logic_vector(199372940,28); exponent <= conv_std_logic_vector(1970,11); WHEN "1010010010" => manhi <= conv_std_logic_vector(3782783,24); manlo <= conv_std_logic_vector(177367827,28); exponent <= conv_std_logic_vector(1972,11); WHEN "1010010011" => manhi <= conv_std_logic_vector(11166720,24); manlo <= conv_std_logic_vector(197425116,28); exponent <= conv_std_logic_vector(1973,11); WHEN "1010010100" => manhi <= conv_std_logic_vector(2212657,24); manlo <= conv_std_logic_vector(231097832,28); exponent <= conv_std_logic_vector(1975,11); WHEN "1010010101" => manhi <= conv_std_logic_vector(9032698,24); manlo <= conv_std_logic_vector(139698050,28); exponent <= conv_std_logic_vector(1976,11); WHEN "1010010110" => manhi <= conv_std_logic_vector(762439,24); manlo <= conv_std_logic_vector(109718127,28); exponent <= conv_std_logic_vector(1978,11); WHEN "1010010111" => manhi <= conv_std_logic_vector(7061647,24); manlo <= conv_std_logic_vector(77173752,28); exponent <= conv_std_logic_vector(1979,11); WHEN "1010011000" => manhi <= conv_std_logic_vector(15623158,24); manlo <= conv_std_logic_vector(118851961,28); exponent <= conv_std_logic_vector(1980,11); WHEN "1010011001" => manhi <= conv_std_logic_vector(5241121,24); manlo <= conv_std_logic_vector(72680114,28); exponent <= conv_std_logic_vector(1982,11); WHEN "1010011010" => manhi <= conv_std_logic_vector(13148807,24); manlo <= conv_std_logic_vector(12881486,28); exponent <= conv_std_logic_vector(1983,11); WHEN "1010011011" => manhi <= conv_std_logic_vector(3559625,24); manlo <= conv_std_logic_vector(43579850,28); exponent <= conv_std_logic_vector(1985,11); WHEN "1010011100" => manhi <= conv_std_logic_vector(10863416,24); manlo <= conv_std_logic_vector(238889758,28); exponent <= conv_std_logic_vector(1986,11); WHEN "1010011101" => manhi <= conv_std_logic_vector(2006541,24); manlo <= conv_std_logic_vector(141721451,28); exponent <= conv_std_logic_vector(1988,11); WHEN "1010011110" => manhi <= conv_std_logic_vector(8752557,24); manlo <= conv_std_logic_vector(101792997,28); exponent <= conv_std_logic_vector(1989,11); WHEN "1010011111" => manhi <= conv_std_logic_vector(572063,24); manlo <= conv_std_logic_vector(205445723,28); exponent <= conv_std_logic_vector(1991,11); WHEN "1010100000" => manhi <= conv_std_logic_vector(6802899,24); manlo <= conv_std_logic_vector(258099270,28); exponent <= conv_std_logic_vector(1992,11); WHEN "1010100001" => manhi <= conv_std_logic_vector(15271484,24); manlo <= conv_std_logic_vector(98124990,28); exponent <= conv_std_logic_vector(1993,11); WHEN "1010100010" => manhi <= conv_std_logic_vector(5002133,24); manlo <= conv_std_logic_vector(256985826,28); exponent <= conv_std_logic_vector(1995,11); WHEN "1010100011" => manhi <= conv_std_logic_vector(12823989,24); manlo <= conv_std_logic_vector(164377270,28); exponent <= conv_std_logic_vector(1996,11); WHEN "1010100100" => manhi <= conv_std_logic_vector(3338888,24); manlo <= conv_std_logic_vector(222569178,28); exponent <= conv_std_logic_vector(1998,11); WHEN "1010100101" => manhi <= conv_std_logic_vector(10563405,24); manlo <= conv_std_logic_vector(29046646,28); exponent <= conv_std_logic_vector(1999,11); WHEN "1010100110" => manhi <= conv_std_logic_vector(1802662,24); manlo <= conv_std_logic_vector(103161316,28); exponent <= conv_std_logic_vector(2001,11); WHEN "1010100111" => manhi <= conv_std_logic_vector(8475456,24); manlo <= conv_std_logic_vector(239852126,28); exponent <= conv_std_logic_vector(2002,11); WHEN "1010101000" => manhi <= conv_std_logic_vector(383754,24); manlo <= conv_std_logic_vector(123914668,28); exponent <= conv_std_logic_vector(2004,11); WHEN "1010101001" => manhi <= conv_std_logic_vector(6546961,24); manlo <= conv_std_logic_vector(22084044,28); exponent <= conv_std_logic_vector(2005,11); WHEN "1010101010" => manhi <= conv_std_logic_vector(14923627,24); manlo <= conv_std_logic_vector(97508377,28); exponent <= conv_std_logic_vector(2006,11); WHEN "1010101011" => manhi <= conv_std_logic_vector(4765740,24); manlo <= conv_std_logic_vector(165164368,28); exponent <= conv_std_logic_vector(2008,11); WHEN "1010101100" => manhi <= conv_std_logic_vector(12502697,24); manlo <= conv_std_logic_vector(201140216,28); exponent <= conv_std_logic_vector(2009,11); WHEN "1010101101" => manhi <= conv_std_logic_vector(3120548,24); manlo <= conv_std_logic_vector(99561759,28); exponent <= conv_std_logic_vector(2011,11); WHEN "1010101110" => manhi <= conv_std_logic_vector(10266649,24); manlo <= conv_std_logic_vector(176679877,28); exponent <= conv_std_logic_vector(2012,11); WHEN "1010101111" => manhi <= conv_std_logic_vector(1600996,24); manlo <= conv_std_logic_vector(39589446,28); exponent <= conv_std_logic_vector(2014,11); WHEN "1010110000" => manhi <= conv_std_logic_vector(8201364,24); manlo <= conv_std_logic_vector(16114999,28); exponent <= conv_std_logic_vector(2015,11); WHEN "1010110001" => manhi <= conv_std_logic_vector(197489,24); manlo <= conv_std_logic_vector(18649371,28); exponent <= conv_std_logic_vector(2017,11); WHEN "1010110010" => manhi <= conv_std_logic_vector(6293800,24); manlo <= conv_std_logic_vector(44802372,28); exponent <= conv_std_logic_vector(2018,11); WHEN "1010110011" => manhi <= conv_std_logic_vector(14579546,24); manlo <= conv_std_logic_vector(1419236,28); exponent <= conv_std_logic_vector(2019,11); WHEN "1010110100" => manhi <= conv_std_logic_vector(4531913,24); manlo <= conv_std_logic_vector(24044223,28); exponent <= conv_std_logic_vector(2021,11); WHEN "1010110101" => manhi <= conv_std_logic_vector(12184893,24); manlo <= conv_std_logic_vector(51602800,28); exponent <= conv_std_logic_vector(2022,11); WHEN "1010110110" => manhi <= conv_std_logic_vector(2904577,24); manlo <= conv_std_logic_vector(210124577,28); exponent <= conv_std_logic_vector(2024,11); WHEN "1010110111" => manhi <= conv_std_logic_vector(9973115,24); manlo <= conv_std_logic_vector(52505388,28); exponent <= conv_std_logic_vector(2025,11); WHEN "1010111000" => manhi <= conv_std_logic_vector(1401518,24); manlo <= conv_std_logic_vector(214362802,28); exponent <= conv_std_logic_vector(2027,11); WHEN "1010111001" => manhi <= conv_std_logic_vector(7930246,24); manlo <= conv_std_logic_vector(62721516,28); exponent <= conv_std_logic_vector(2028,11); WHEN "1010111010" => manhi <= conv_std_logic_vector(13245,24); manlo <= conv_std_logic_vector(108520727,28); exponent <= conv_std_logic_vector(2030,11); WHEN "1010111011" => manhi <= conv_std_logic_vector(6043387,24); manlo <= conv_std_logic_vector(17001813,28); exponent <= conv_std_logic_vector(2031,11); WHEN "1010111100" => manhi <= conv_std_logic_vector(14239199,24); manlo <= conv_std_logic_vector(83422350,28); exponent <= conv_std_logic_vector(2032,11); WHEN "1010111101" => manhi <= conv_std_logic_vector(4300623,24); manlo <= conv_std_logic_vector(142486326,28); exponent <= conv_std_logic_vector(2034,11); WHEN "1010111110" => manhi <= conv_std_logic_vector(11870538,24); manlo <= conv_std_logic_vector(24126621,28); exponent <= conv_std_logic_vector(2035,11); WHEN "1010111111" => manhi <= conv_std_logic_vector(2690951,24); manlo <= conv_std_logic_vector(91850592,28); exponent <= conv_std_logic_vector(2037,11); WHEN "1011000000" => manhi <= conv_std_logic_vector(9682766,24); manlo <= conv_std_logic_vector(203960059,28); exponent <= conv_std_logic_vector(2038,11); WHEN "1011000001" => manhi <= conv_std_logic_vector(1204206,24); manlo <= conv_std_logic_vector(155513539,28); exponent <= conv_std_logic_vector(2040,11); WHEN "1011000010" => manhi <= conv_std_logic_vector(7662071,24); manlo <= conv_std_logic_vector(33184566,28); exponent <= conv_std_logic_vector(2041,11); WHEN "1011000011" => manhi <= conv_std_logic_vector(16439219,24); manlo <= conv_std_logic_vector(11896414,28); exponent <= conv_std_logic_vector(2042,11); WHEN "1011000100" => manhi <= conv_std_logic_vector(5795691,24); manlo <= conv_std_logic_vector(254151921,28); exponent <= conv_std_logic_vector(2044,11); WHEN "1011000101" => manhi <= conv_std_logic_vector(13902546,24); manlo <= conv_std_logic_vector(199613595,28); exponent <= conv_std_logic_vector(2045,11); WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:30:03 02/06/2015 -- Design Name: -- Module Name: addN_testbench - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity addN_tb is generic( M: integer:=5); end addN_tb; architecture archi of addN_tb is signal entree1, entree2, sortie: std_logic_vector(M-1 downto 0); component addN generic(N: integer := 5); port (a,b: in std_logic_vector ( N-1 downto 0); s: out std_logic_vector (N-1 downto 0)); end component; begin -- de la même manière que l'on fait un port map, on va faire un generic map pour -- attribuer une valeur au paramètre N de AddN uut: addN generic map (N => M) port map (a=> entree1, b => entree2, s => sortie); stimuli_entree1: process begin entree1 <= (others => '0'); wait for 50 ns; loop entree1 <= entree1 + 1; wait for 50 ns; end loop; end process; stimuli_entree2: process begin entree2<= (others => '0') ; loop if entree1=0 then entree2 <= entree2 + 1; end if; wait for 50 ns ; end loop ; end process; end archi;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:30:03 02/06/2015 -- Design Name: -- Module Name: addN_testbench - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity addN_tb is generic( M: integer:=5); end addN_tb; architecture archi of addN_tb is signal entree1, entree2, sortie: std_logic_vector(M-1 downto 0); component addN generic(N: integer := 5); port (a,b: in std_logic_vector ( N-1 downto 0); s: out std_logic_vector (N-1 downto 0)); end component; begin -- de la même manière que l'on fait un port map, on va faire un generic map pour -- attribuer une valeur au paramètre N de AddN uut: addN generic map (N => M) port map (a=> entree1, b => entree2, s => sortie); stimuli_entree1: process begin entree1 <= (others => '0'); wait for 50 ns; loop entree1 <= entree1 + 1; wait for 50 ns; end loop; end process; stimuli_entree2: process begin entree2<= (others => '0') ; loop if entree1=0 then entree2 <= entree2 + 1; end if; wait for 50 ns ; end loop ; end process; end archi;
package STRSYN is attribute SigDir : string; attribute SigType : string; attribute SigBias : string; end STRSYN; entity opfd is port ( terminal in1: electrical; terminal in2: electrical; terminal out1: electrical; terminal out2: electrical; terminal vbias4: electrical; terminal gnd: electrical; terminal vdd: electrical; terminal vbias1: electrical; terminal vref: electrical; terminal vbias2: electrical; terminal vbias3: electrical); end opfd; architecture simple of opfd is -- Attributes for Ports attribute SigDir of in1:terminal is "input"; attribute SigType of in1:terminal is "undef"; attribute SigDir of in2:terminal is "input"; attribute SigType of in2:terminal is "undef"; attribute SigDir of out1:terminal is "output"; attribute SigType of out1:terminal is "undef"; attribute SigDir of out2:terminal is "output"; attribute SigType of out2:terminal is "undef"; attribute SigDir of vbias4:terminal is "reference"; attribute SigType of vbias4:terminal is "voltage"; attribute SigDir of gnd:terminal is "reference"; attribute SigType of gnd:terminal is "current"; attribute SigBias of gnd:terminal is "negative"; attribute SigDir of vdd:terminal is "reference"; attribute SigType of vdd:terminal is "current"; attribute SigBias of vdd:terminal is "positive"; attribute SigDir of vbias1:terminal is "reference"; attribute SigType of vbias1:terminal is "voltage"; attribute SigDir of vref:terminal is "reference"; attribute SigType of vref:terminal is "current"; attribute SigBias of vref:terminal is "negative"; attribute SigDir of vbias2:terminal is "reference"; attribute SigType of vbias2:terminal is "voltage"; attribute SigDir of vbias3:terminal is "reference"; attribute SigType of vbias3:terminal is "voltage"; terminal net1: electrical; terminal net2: electrical; terminal net3: electrical; terminal net4: electrical; terminal net5: electrical; terminal net6: electrical; terminal net7: electrical; terminal net8: electrical; terminal net9: electrical; terminal net10: electrical; terminal net11: electrical; begin subnet0_subnet0_m1 : entity nmos(behave) generic map( L => Ldiff_0, Ldiff_0init => 4.85e-06, W => Wdiff_0, Wdiff_0init => 4.38e-05, scope => private ) port map( D => net2, G => in1, S => net5 ); subnet0_subnet0_m2 : entity nmos(behave) generic map( L => Ldiff_0, Ldiff_0init => 4.85e-06, W => Wdiff_0, Wdiff_0init => 4.38e-05, scope => private ) port map( D => net1, G => in2, S => net5 ); subnet0_subnet0_m3 : entity nmos(behave) generic map( L => LBias, LBiasinit => 9.5e-07, W => W_0, W_0init => 3.105e-05 ) port map( D => net5, G => vbias4, S => gnd ); subnet0_subnet0_m4 : entity nmos(behave) generic map( L => Ldiff_0, Ldiff_0init => 4.85e-06, W => Wdiff_0, Wdiff_0init => 4.38e-05, scope => private ) port map( D => net6, G => in1, S => net5 ); subnet0_subnet0_m5 : entity nmos(behave) generic map( L => Ldiff_0, Ldiff_0init => 4.85e-06, W => Wdiff_0, Wdiff_0init => 4.38e-05, scope => private ) port map( D => net6, G => in2, S => net5 ); subnet0_subnet0_m6 : entity pmos(behave) generic map( L => Lcmdiffp_0, Lcmdiffp_0init => 1.23e-05, W => Wcmdiffp_0, Wcmdiffp_0init => 1.36e-05, scope => private ) port map( D => net6, G => net6, S => vdd ); subnet0_subnet0_m7 : entity pmos(behave) generic map( L => Lcmdiffp_0, Lcmdiffp_0init => 1.23e-05, W => Wcmdiffp_0, Wcmdiffp_0init => 1.36e-05, scope => private ) port map( D => net6, G => net6, S => vdd ); subnet0_subnet0_m8 : entity pmos(behave) generic map( L => Lcmdiffp_0, Lcmdiffp_0init => 1.23e-05, W => Wcmdiffp_0, Wcmdiffp_0init => 1.36e-05, scope => private ) port map( D => net1, G => net6, S => vdd ); subnet0_subnet0_m9 : entity pmos(behave) generic map( L => Lcmdiffp_0, Lcmdiffp_0init => 1.23e-05, W => Wcmdiffp_0, Wcmdiffp_0init => 1.36e-05, scope => private ) port map( D => net2, G => net6, S => vdd ); subnet0_subnet1_m1 : entity nmos(behave) generic map( L => L_2, L_2init => 5.75e-06, W => Wsrc_1, Wsrc_1init => 6.765e-05, scope => Wprivate, symmetry_scope => sym_3 ) port map( D => net3, G => net1, S => gnd ); subnet0_subnet2_m1 : entity nmos(behave) generic map( L => L_3, L_3init => 5.4e-06, W => Wsrc_1, Wsrc_1init => 6.765e-05, scope => Wprivate, symmetry_scope => sym_3 ) port map( D => net4, G => net2, S => gnd ); subnet0_subnet3_m1 : entity pmos(behave) generic map( L => Lcm_2, Lcm_2init => 3.5e-07, W => Wcm_2, Wcm_2init => 1.855e-05, scope => private, symmetry_scope => sym_4 ) port map( D => net3, G => net3, S => vdd ); subnet0_subnet3_m2 : entity pmos(behave) generic map( L => Lcm_2, Lcm_2init => 3.5e-07, W => Wcmout_2, Wcmout_2init => 7.73e-05, scope => private, symmetry_scope => sym_4 ) port map( D => out1, G => net3, S => vdd ); subnet0_subnet3_c1 : entity cap(behave) generic map( C => C_4, symmetry_scope => sym_4 ) port map( P => out1, N => net3 ); subnet0_subnet4_m1 : entity pmos(behave) generic map( L => Lcm_2, Lcm_2init => 3.5e-07, W => Wcm_2, Wcm_2init => 1.855e-05, scope => private, symmetry_scope => sym_4 ) port map( D => net4, G => net4, S => vdd ); subnet0_subnet4_m2 : entity pmos(behave) generic map( L => Lcm_2, Lcm_2init => 3.5e-07, W => Wcmout_2, Wcmout_2init => 7.73e-05, scope => private, symmetry_scope => sym_4 ) port map( D => out2, G => net4, S => vdd ); subnet0_subnet4_c1 : entity cap(behave) generic map( C => C_5, symmetry_scope => sym_4 ) port map( P => out2, N => net4 ); subnet0_subnet5_m1 : entity nmos(behave) generic map( L => LBias, LBiasinit => 9.5e-07, W => Wcursrc_3, Wcursrc_3init => 5.115e-05, scope => Wprivate, symmetry_scope => sym_5 ) port map( D => out1, G => vbias4, S => gnd ); subnet0_subnet6_m1 : entity nmos(behave) generic map( L => LBias, LBiasinit => 9.5e-07, W => Wcursrc_3, Wcursrc_3init => 5.115e-05, scope => Wprivate, symmetry_scope => sym_5 ) port map( D => out2, G => vbias4, S => gnd ); subnet1_subnet0_r1 : entity res(behave) generic map( R => 1e+07 ) port map( P => net7, N => out1 ); subnet1_subnet0_r2 : entity res(behave) generic map( R => 1e+07 ) port map( P => net7, N => out2 ); subnet1_subnet0_c2 : entity cap(behave) generic map( C => Ccmfb ) port map( P => net10, N => vref ); subnet1_subnet0_c1 : entity cap(behave) generic map( C => Ccmfb ) port map( P => net9, N => net7 ); subnet1_subnet0_t1 : entity pmos(behave) generic map( L => LBias, LBiasinit => 9.5e-07, W => W_1, W_1init => 1.785e-05 ) port map( D => net8, G => vbias1, S => vdd ); subnet1_subnet0_t2 : entity pmos(behave) generic map( L => Lcmdiff_0, Lcmdiff_0init => 7.7e-06, W => Wcmdiff_0, Wcmdiff_0init => 7.935e-05, scope => private ) port map( D => net10, G => vref, S => net8 ); subnet1_subnet0_t3 : entity pmos(behave) generic map( L => Lcmdiff_0, Lcmdiff_0init => 7.7e-06, W => Wcmdiff_0, Wcmdiff_0init => 7.935e-05, scope => private ) port map( D => net9, G => net7, S => net8 ); subnet1_subnet0_t4 : entity nmos(behave) generic map( L => Lcm_0, Lcm_0init => 7.15e-06, W => Wcmfbload_0, Wcmfbload_0init => 6e-07, scope => private ) port map( D => net9, G => net9, S => gnd ); subnet1_subnet0_t5 : entity nmos(behave) generic map( L => Lcm_0, Lcm_0init => 7.15e-06, W => Wcmfbload_0, Wcmfbload_0init => 6e-07, scope => private ) port map( D => net10, G => net9, S => gnd ); subnet1_subnet0_t6 : entity nmos(behave) generic map( L => Lcmbias_0, Lcmbias_0init => 1.05e-06, W => Wcmbias_0, Wcmbias_0init => 7.435e-05, scope => private ) port map( D => out1, G => net10, S => gnd ); subnet1_subnet0_t7 : entity nmos(behave) generic map( L => Lcmbias_0, Lcmbias_0init => 1.05e-06, W => Wcmbias_0, Wcmbias_0init => 7.435e-05, scope => private ) port map( D => out2, G => net10, S => gnd ); subnet2_subnet0_m1 : entity pmos(behave) generic map( L => LBias, LBiasinit => 9.5e-07, W => (pfak)*(WBias), WBiasinit => 5.7e-06 ) port map( D => vbias1, G => vbias1, S => vdd ); subnet2_subnet0_m2 : entity pmos(behave) generic map( L => (pfak)*(LBias), LBiasinit => 9.5e-07, W => (pfak)*(WBias), WBiasinit => 5.7e-06 ) port map( D => vbias2, G => vbias2, S => vbias1 ); subnet2_subnet0_i1 : entity idc(behave) generic map( I => 1.145e-05 ) port map( P => vdd, N => vbias3 ); subnet2_subnet0_m3 : entity nmos(behave) generic map( L => (pfak)*(LBias), LBiasinit => 9.5e-07, W => WBias, WBiasinit => 5.7e-06 ) port map( D => vbias3, G => vbias3, S => vbias4 ); subnet2_subnet0_m4 : entity nmos(behave) generic map( L => LBias, LBiasinit => 9.5e-07, W => WBias, WBiasinit => 5.7e-06 ) port map( D => vbias2, G => vbias3, S => net11 ); subnet2_subnet0_m5 : entity nmos(behave) generic map( L => LBias, LBiasinit => 9.5e-07, W => WBias, WBiasinit => 5.7e-06 ) port map( D => vbias4, G => vbias4, S => gnd ); subnet2_subnet0_m6 : entity nmos(behave) generic map( L => LBias, LBiasinit => 9.5e-07, W => WBias, WBiasinit => 5.7e-06 ) port map( D => net11, G => vbias4, S => gnd ); end simple;
------------------------------------------------------------------------------------- -- FILE NAME : shift_bytes.vhd -- AUTHOR : Luis -- COMPANY : -- UNITS : Entity - -- Architecture - Behavioral -- LANGUAGE : VHDL -- DATE : AUG 21, 2014 ------------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------------- -- DESCRIPTION -- =========== -- Accept an input data stream and shifts the bytes -- -- ------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------- -- LIBRARIES ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- non-IEEE packages use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use ieee.std_logic_arith.all; ------------------------------------------------------------------------------------- -- ENTITY ------------------------------------------------------------------------------------- entity shift_bytes is port ( clk_in : in std_logic; rst_in : in std_logic; data_in : in std_logic_vector(63 downto 0); valid_in : in std_logic; data_out : out std_logic_vector(63 downto 0); valid_out : out std_logic; shift_amount_in : in std_logic_vector(2 downto 0) ); end shift_bytes; ------------------------------------------------------------------------------------- -- ARCHITECTURE ------------------------------------------------------------------------------------- architecture Behavioral of shift_bytes is ------------------------------------------------------------------------------------- -- CONSTANTS ------------------------------------------------------------------------------------- type bus008 is array(natural range <>) of std_logic_vector( 7 downto 0); type bus064 is array(natural range <>) of std_logic_vector(63 downto 0); ------------------------------------------------------------------------------------- -- SIGNALS ------------------------------------------------------------------------------------- signal valid_pipe : std_logic_vector(2 downto 0); signal data_pipe : bus064(2 downto 0); signal data_pipe_byte : bus008(23 downto 0); --*********************************************************************************** begin --*********************************************************************************** -- buffer 3 cycles process(clk_in) begin if rising_edge(clk_in) then valid_pipe(2) <= valid_in; valid_pipe(1) <= valid_pipe(2); valid_pipe(0) <= valid_pipe(1); if valid_in = '1' then data_pipe(2) <= data_in; data_pipe(1) <= data_pipe(2); data_pipe(0) <= data_pipe(1); end if; end if; end process; -- Remap data_pipe_byte(23) <= data_pipe(2)(63 downto 56); data_pipe_byte(22) <= data_pipe(2)(55 downto 48); data_pipe_byte(21) <= data_pipe(2)(47 downto 40); data_pipe_byte(20) <= data_pipe(2)(39 downto 32); data_pipe_byte(19) <= data_pipe(2)(31 downto 24); data_pipe_byte(18) <= data_pipe(2)(23 downto 16); data_pipe_byte(17) <= data_pipe(2)(15 downto 8); data_pipe_byte(16) <= data_pipe(2)( 7 downto 0); data_pipe_byte(15) <= data_pipe(1)(63 downto 56); data_pipe_byte(14) <= data_pipe(1)(55 downto 48); data_pipe_byte(13) <= data_pipe(1)(47 downto 40); data_pipe_byte(12) <= data_pipe(1)(39 downto 32); data_pipe_byte(11) <= data_pipe(1)(31 downto 24); data_pipe_byte(10) <= data_pipe(1)(23 downto 16); data_pipe_byte(9) <= data_pipe(1)(15 downto 8); data_pipe_byte(8) <= data_pipe(1)( 7 downto 0); data_pipe_byte(7) <= data_pipe(0)(63 downto 56); data_pipe_byte(6) <= data_pipe(0)(55 downto 48); data_pipe_byte(5) <= data_pipe(0)(47 downto 40); data_pipe_byte(4) <= data_pipe(0)(39 downto 32); data_pipe_byte(3) <= data_pipe(0)(31 downto 24); data_pipe_byte(2) <= data_pipe(0)(23 downto 16); data_pipe_byte(1) <= data_pipe(0)(15 downto 8); data_pipe_byte(0) <= data_pipe(0)( 7 downto 0); process(clk_in) begin if rising_edge(clk_in) then if rst_in = '1' then data_out <= (others=>'0'); valid_out <= '0'; else case shift_amount_in is when "000" => data_out <= data_pipe_byte(15) & data_pipe_byte(14) & data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8); valid_out <= valid_in; when "001" => data_out <= data_pipe_byte(14) & data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8) & data_pipe_byte(7); valid_out <= valid_in; when "010" => data_out <= data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8) & data_pipe_byte(7) & data_pipe_byte(6); valid_out <= valid_in; when "011" => data_out <= data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8) & data_pipe_byte(7) & data_pipe_byte(6) & data_pipe_byte(5); valid_out <= valid_in; when "100" => data_out <= data_pipe_byte(15) & data_pipe_byte(14) & data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8); valid_out <= valid_in; when "101" => data_out <= data_pipe_byte(14) & data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8) & data_pipe_byte(7); valid_out <= valid_in; when "110" => data_out <= data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8) & data_pipe_byte(7) & data_pipe_byte(6); valid_out <= valid_in; when "111" => data_out <= data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8) & data_pipe_byte(7) & data_pipe_byte(6) & data_pipe_byte(5); valid_out <= valid_in; when others => data_out <= data_pipe_byte(15) & data_pipe_byte(14) & data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8); valid_out <= valid_in; end case; end if; end if; end process; --*********************************************************************************** end architecture Behavioral; --***********************************************************************************
-- DDR controller constant CFG_DDR2SP : integer := CONFIG_DDR2SP; constant CFG_DDR2SP_INIT : integer := CONFIG_DDR2SP_INIT; constant CFG_DDR2SP_FREQ : integer := CONFIG_DDR2SP_FREQ; constant CFG_DDR2SP_DATAWIDTH : integer := CONFIG_DDR2SP_DATAWIDTH; constant CFG_DDR2SP_COL : integer := CONFIG_DDR2SP_COL; constant CFG_DDR2SP_SIZE : integer := CONFIG_DDR2SP_MBYTE; constant CFG_DDR2SP_DELAY0 : integer := CONFIG_DDR2SP_DELAY0; constant CFG_DDR2SP_DELAY1 : integer := CONFIG_DDR2SP_DELAY1; constant CFG_DDR2SP_DELAY2 : integer := CONFIG_DDR2SP_DELAY2; constant CFG_DDR2SP_DELAY3 : integer := CONFIG_DDR2SP_DELAY3; constant CFG_DDR2SP_DELAY4 : integer := CONFIG_DDR2SP_DELAY4; constant CFG_DDR2SP_DELAY5 : integer := CONFIG_DDR2SP_DELAY5; constant CFG_DDR2SP_DELAY6 : integer := CONFIG_DDR2SP_DELAY6; constant CFG_DDR2SP_DELAY7 : integer := CONFIG_DDR2SP_DELAY7;
-- DDR controller constant CFG_DDR2SP : integer := CONFIG_DDR2SP; constant CFG_DDR2SP_INIT : integer := CONFIG_DDR2SP_INIT; constant CFG_DDR2SP_FREQ : integer := CONFIG_DDR2SP_FREQ; constant CFG_DDR2SP_DATAWIDTH : integer := CONFIG_DDR2SP_DATAWIDTH; constant CFG_DDR2SP_COL : integer := CONFIG_DDR2SP_COL; constant CFG_DDR2SP_SIZE : integer := CONFIG_DDR2SP_MBYTE; constant CFG_DDR2SP_DELAY0 : integer := CONFIG_DDR2SP_DELAY0; constant CFG_DDR2SP_DELAY1 : integer := CONFIG_DDR2SP_DELAY1; constant CFG_DDR2SP_DELAY2 : integer := CONFIG_DDR2SP_DELAY2; constant CFG_DDR2SP_DELAY3 : integer := CONFIG_DDR2SP_DELAY3; constant CFG_DDR2SP_DELAY4 : integer := CONFIG_DDR2SP_DELAY4; constant CFG_DDR2SP_DELAY5 : integer := CONFIG_DDR2SP_DELAY5; constant CFG_DDR2SP_DELAY6 : integer := CONFIG_DDR2SP_DELAY6; constant CFG_DDR2SP_DELAY7 : integer := CONFIG_DDR2SP_DELAY7;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tp1 is port ( clk: in std_logic ); end; architecture tp1_arq of tp1 is begin end;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Top File for the Example Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- Filename: rom_memory_tb.vhd -- Description: -- Testbench Top -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.ALL; ENTITY rom_memory_tb IS END ENTITY; ARCHITECTURE rom_memory_tb_ARCH OF rom_memory_tb IS SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL CLK : STD_LOGIC := '1'; SIGNAL RESET : STD_LOGIC; BEGIN CLK_GEN: PROCESS BEGIN CLK <= NOT CLK; WAIT FOR 100 NS; CLK <= NOT CLK; WAIT FOR 100 NS; END PROCESS; RST_GEN: PROCESS BEGIN RESET <= '1'; WAIT FOR 1000 NS; RESET <= '0'; WAIT; END PROCESS; --STOP_SIM: PROCESS BEGIN -- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS -- ASSERT FALSE -- REPORT "END SIMULATION TIME REACHED" -- SEVERITY FAILURE; --END PROCESS; -- PROCESS BEGIN WAIT UNTIL STATUS(8)='1'; IF( STATUS(7 downto 0)/="0") THEN ASSERT false REPORT "Test Completed Successfully" SEVERITY NOTE; REPORT "Simulation Failed" SEVERITY FAILURE; ELSE ASSERT false REPORT "TEST PASS" SEVERITY NOTE; REPORT "Test Completed Successfully" SEVERITY FAILURE; END IF; END PROCESS; rom_memory_synth_inst:ENTITY work.rom_memory_synth GENERIC MAP (C_ROM_SYNTH => 0) PORT MAP( CLK_IN => CLK, RESET_IN => RESET, STATUS => STATUS ); END ARCHITECTURE;
LIBRARY Ieee; USE ieee.std_logic_1164.all; ENTITY CLAH16bits IS PORT ( val1,val2: IN STD_LOGIC_VECTOR(15 DOWNTO 0); CarryIn: IN STD_LOGIC; CarryOut: OUT STD_LOGIC; clk: IN STD_LOGIC; rst: IN STD_LOGIC; SomaResult:OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END CLAH16bits; ARCHITECTURE strc_CLAH16bits of CLAH16bits is SIGNAL Cin_sig, Cout_sig: STD_LOGIC; SIGNAL P0_sig, P1_sig, P2_sig, P3_sig, P4_sig, P5_sig, P6_sig, P7_sig: STD_LOGIC; SIGNAL G0_sig, G1_sig, G2_sig, G3_sig, G4_sig, G5_sig, G6_sig, G7_sig: STD_LOGIC; SIGNAL Cout1_temp_sig, Cout2_temp_sig, Cout3_temp_sig, Cout4_temp_sig, Cout5_temp_sig, Cout6_temp_sig, Cout7_temp_sig: STD_LOGIC; SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL SomaT1,SomaT2,SomaT3,SomaT4,SomaT5,SomaT6,SomaT7,SomaT8:STD_LOGIC_VECTOR(1 DOWNTO 0); Component CLA2bits PORT ( val1,val2: IN STD_LOGIC_VECTOR(1 DOWNTO 0); SomaResult:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); CarryIn: IN STD_LOGIC; P, G: OUT STD_LOGIC ); end component; Component Reg1Bit PORT ( valIn: in std_logic; clk: in std_logic; rst: in std_logic; valOut: out std_logic ); end component; Component Reg16Bit PORT ( valIn: in std_logic_vector(15 downto 0); clk: in std_logic; rst: in std_logic; valOut: out std_logic_vector(15 downto 0) ); end component; Component CLGB PORT ( P0, P1, G0, G1, Cin: IN STD_LOGIC; Cout1, Cout2: OUT STD_LOGIC ); end component; BEGIN --registradores-- Reg_CarryIn: Reg1Bit PORT MAP ( valIn=>CarryIn, clk=>clk, rst=>rst, valOut=>Cin_sig ); Reg_A: Reg16Bit PORT MAP ( valIn=>val1, clk=>clk, rst=>rst, valOut=>A_sig ); Reg_B: Reg16Bit PORT MAP ( valIn=>val2, clk=>clk, rst=>rst, valOut=>B_sig ); Reg_CarryOut: Reg1Bit PORT MAP ( valIn=>Cout_sig, clk=>clk, rst=>rst, valOut=>CarryOut ); Reg_Ssoma: Reg16Bit PORT MAP ( valIn=>Out_sig, clk=>clk, rst=>rst, valOut=>SomaResult ); Som1: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(1 DOWNTO 0), val2(1 DOWNTO 0) => B_sig(1 DOWNTO 0), CarryIn=>Cin_sig, P=>P0_sig, G=>G0_sig, SomaResult=>SomaT1 ); CLGB1: CLGB PORT MAP( P0=>P0_sig, G0=>G0_sig, P1=>P1_sig, G1=>G1_sig, Cin=>Cin_sig, Cout1=>Cout1_temp_sig, Cout2=>Cout2_temp_sig ); Som2: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(3 DOWNTO 2), val2(1 DOWNTO 0) => B_sig(3 DOWNTO 2), CarryIn=>Cout1_temp_sig, P=>P1_sig, G=>G1_sig, SomaResult=>SomaT2 ); Som3: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(5 DOWNTO 4), val2(1 DOWNTO 0) => B_sig(5 DOWNTO 4), CarryIn=>Cout2_temp_sig, P=>P2_sig, G=>G2_sig, SomaResult=>SomaT3 ); CLGB2: CLGB PORT MAP( P0=>P2_sig, G0=>G2_sig, P1=>P3_sig, G1=>G3_sig, Cin=>Cout2_temp_sig, Cout1=>Cout3_temp_sig, Cout2=>Cout4_temp_sig ); Som4: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(7 DOWNTO 6), val2(1 DOWNTO 0) => B_sig(7 DOWNTO 6), CarryIn=>Cout3_temp_sig, P=>P3_sig, G=>G3_sig, SomaResult=>SomaT4 ); --novoooooooo-- Som5: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(9 DOWNTO 8), val2(1 DOWNTO 0) => B_sig(9 DOWNTO 8), CarryIn=>Cout4_temp_sig, P=>P4_sig, G=>G4_sig, SomaResult=>SomaT5 ); CLGB3: CLGB PORT MAP( P0=>P4_sig, G0=>G4_sig, P1=>P5_sig, G1=>G5_sig, Cin=>Cout4_temp_sig, Cout1=>Cout5_temp_sig, Cout2=>Cout6_temp_sig ); Som6: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(11 DOWNTO 10), val2(1 DOWNTO 0) => B_sig(11 DOWNTO 10), CarryIn=>Cout5_temp_sig, P=>P5_sig, G=>G5_sig, SomaResult=>SomaT6 ); Som7: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(13 DOWNTO 12), val2(1 DOWNTO 0) => B_sig(13 DOWNTO 12), CarryIn=>Cout6_temp_sig, P=>P6_sig, G=>G6_sig, SomaResult=>SomaT7 ); CLGB4: CLGB PORT MAP( P0=>P6_sig, G0=>G6_sig, P1=>P7_sig, G1=>G7_sig, Cin=>Cout6_temp_sig, Cout1=>Cout7_temp_sig, Cout2=>Cout_sig ); Som8: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(15 DOWNTO 14), val2(1 DOWNTO 0) => B_sig(15 DOWNTO 14), CarryIn=>Cout7_temp_sig, P=>P7_sig, G=>G7_sig, SomaResult=>SomaT8 ); Out_sig <= SomaT8 & SomaT7 & SomaT6 & SomaT5 & SomaT4 & SomaT3 & SomaT2 & SomaT1; END strc_CLAH16bits;
-- modelled according to IEEE Std 1801-2015, 11.2 package upf is function supply_on ( constant supply_name : string; constant voltage : real) return boolean; function supply_partial_on ( constant supply_name : string; constant voltage : real) return boolean; function supply_off ( constant supply_name : string) return boolean; end upf;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: bmg_stim_gen.vhd -- -- Description: -- Stimulus Generation For SROM -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY REGISTER_LOGIC_SROM IS PORT( Q : OUT STD_LOGIC; CLK : IN STD_LOGIC; RST : IN STD_LOGIC; D : IN STD_LOGIC ); END REGISTER_LOGIC_SROM; ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS SIGNAL Q_O : STD_LOGIC :='0'; BEGIN Q <= Q_O; FF_BEH: PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST /= '0' ) THEN Q_O <= '0'; ELSE Q_O <= D; END IF; END IF; END PROCESS; END REGISTER_ARCH; LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; --USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY BMG_STIM_GEN IS GENERIC ( C_ROM_SYNTH : INTEGER := 0 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; ADDRA: OUT STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0'); DATA_IN : IN STD_LOGIC_VECTOR (11 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END BMG_STIM_GEN; ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS FUNCTION hex_to_std_logic_vector( hex_str : STRING; return_width : INTEGER) RETURN STD_LOGIC_VECTOR IS VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1 DOWNTO 0); BEGIN tmp := (OTHERS => '0'); FOR i IN 1 TO hex_str'LENGTH LOOP CASE hex_str((hex_str'LENGTH+1)-i) IS WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000"; WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001"; WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010"; WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011"; WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100"; WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101"; WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110"; WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111"; WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000"; WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001"; WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010"; WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011"; WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100"; WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101"; WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110"; WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111"; WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111"; END CASE; END LOOP; RETURN tmp(return_width-1 DOWNTO 0); END hex_to_std_logic_vector; CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0'); SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0'); SIGNAL DO_READ : STD_LOGIC := '0'; SIGNAL CHECK_DATA : STD_LOGIC := '0'; SIGNAL CHECK_DATA_R : STD_LOGIC := '0'; SIGNAL CHECK_DATA_2R : STD_LOGIC := '0'; SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0'); CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0):= hex_to_std_logic_vector("0",12); BEGIN SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE type mem_type is array (76799 downto 0) of std_logic_vector(11 downto 0); FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS VARIABLE temp_return : STD_LOGIC; BEGIN IF (input = '0') THEN temp_return := '0'; ELSE temp_return := '1'; END IF; RETURN temp_return; END bit_to_sl; function char_to_std_logic ( char : in character) return std_logic is variable data : std_logic; begin if char = '0' then data := '0'; elsif char = '1' then data := '1'; elsif char = 'X' then data := 'X'; else assert false report "character which is not '0', '1' or 'X'." severity warning; data := 'U'; end if; return data; end char_to_std_logic; impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER; C_LOAD_INIT_FILE : INTEGER ; C_INIT_FILE_NAME : STRING ; DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0); width : INTEGER; depth : INTEGER) RETURN mem_type IS VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0')); FILE init_file : TEXT; VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0); VARIABLE bitline : LINE; variable bitsgood : boolean := true; variable bitchar : character; VARIABLE i : INTEGER; VARIABLE j : INTEGER; BEGIN --Display output message indicating that the behavioral model is being --initialized ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE; -- Setup the default data -- Default data is with respect to write_port_A and may be wider -- or narrower than init_return width. The following loops map -- default data into the memory IF (C_USE_DEFAULT_DATA=1) THEN FOR i IN 0 TO depth-1 LOOP init_return(i) := DEFAULT_DATA; END LOOP; END IF; -- Read in the .mif file -- The init data is formatted with respect to write port A dimensions. -- The init_return vector is formatted with respect to minimum width and -- maximum depth; the following loops map the .mif file into the memory IF (C_LOAD_INIT_FILE=1) THEN file_open(init_file, C_INIT_FILE_NAME, read_mode); i := 0; WHILE (i < depth AND NOT endfile(init_file)) LOOP mem_vector := (OTHERS => '0'); readline(init_file, bitline); -- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0)); FOR j IN 0 TO width-1 LOOP read(bitline,bitchar,bitsgood); init_return(i)(width-1-j) := char_to_std_logic(bitchar); END LOOP; i := i + 1; END LOOP; file_close(init_file); END IF; RETURN init_return; END FUNCTION; --*************************************************************** -- convert bit to STD_LOGIC --*************************************************************** constant c_init : mem_type := init_memory(0, 1, "background.mif", DEFAULT_DATA, 12, 76800); constant rom : mem_type := c_init; BEGIN EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr))); CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN GENERIC MAP( C_MAX_DEPTH =>76800 ) PORT MAP( CLK => CLK, RST => RST, EN => CHECK_DATA_2R, LOAD => '0', LOAD_VALUE => ZERO, ADDR_OUT => CHECK_READ_ADDR ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(CHECK_DATA_2R ='1') THEN IF(EXPECTED_DATA = DATA_IN) THEN STATUS<='0'; ELSE STATUS <= '1'; END IF; END IF; END IF; END PROCESS; END GENERATE; -- Simulatable ROM --Synthesizable ROM SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(CHECK_DATA_2R='1') THEN IF(DATA_IN=DEFAULT_DATA) THEN STATUS <= '0'; ELSE STATUS <= '1'; END IF; END IF; END IF; END PROCESS; END GENERATE; READ_ADDR_INT(16 DOWNTO 0) <= READ_ADDR(16 DOWNTO 0); ADDRA <= READ_ADDR_INT ; CHECK_DATA <= DO_READ; RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN GENERIC MAP( C_MAX_DEPTH => 76800 ) PORT MAP( CLK => CLK, RST => RST, EN => DO_READ, LOAD => '0', LOAD_VALUE => ZERO, ADDR_OUT => READ_ADDR ); RD_PROCESS: PROCESS (CLK) BEGIN IF (RISING_EDGE(CLK)) THEN IF(RST='1') THEN DO_READ <= '0'; ELSE DO_READ <= '1'; END IF; END IF; END PROCESS; BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE BEGIN DFF_RIGHT: IF I=0 GENERATE BEGIN SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM PORT MAP( Q => DO_READ_REG(0), CLK =>CLK, RST=>RST, D =>DO_READ ); END GENERATE DFF_RIGHT; DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE BEGIN SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM PORT MAP( Q => DO_READ_REG(I), CLK =>CLK, RST=>RST, D =>DO_READ_REG(I-1) ); END GENERATE DFF_OTHERS; END GENERATE BEGIN_SHIFT_REG; CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM PORT MAP( Q => CHECK_DATA_2R, CLK =>CLK, RST=>RST, D =>CHECK_DATA_R ); CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM PORT MAP( Q => CHECK_DATA_R, CLK =>CLK, RST=>RST, D =>CHECK_DATA ); END ARCHITECTURE;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> -- Benedikt Reuter <breutr@gmail.com> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity queens_slice is generic ( N : positive; -- size of field L : natural -- number of preplaced outer rings ); port ( -- Global Clock clk : in std_logic; rst : in std_logic; -- Inputs (strobed) start : in std_logic; -- Strobe for Start BH_l : in std_logic_vector(0 to N-2*L-1); -- Blocking for leftmost Column BU_l : in std_logic_vector(0 to 2*N-4*L-2); BD_l : in std_logic_vector(0 to 2*N-4*L-2); BV_l : in std_logic_vector(0 to N-2*L-1); -- Output Strobes sol : out std_logic; done : out std_logic ); end queens_slice; library IEEE; use IEEE.numeric_std.all; architecture rtl of queens_slice is --------------------------------------------------------------------------- -- Matrix to iterate through -- These types are plain ugly but the multidiemsional tMatrix(<>, <>) -- is not slicable. Thus, these types are still better than lots of -- generate loops working through the columns. subtype tColumn is std_logic_vector(L to N-L-1); type tField is array(L to N-L-1) of tColumn; -- Placed Queen Matrix signal QN : tField := (others => (others => '-')); component arbit_forward generic ( N : positive -- Length of Token Chain ); port ( tin : in std_logic; -- Fed Token have : in std_logic_vector(0 to N-1); -- Token Owner pass : in std_logic_vector(0 to N-1); -- Token Passers grnt : out std_logic_vector(0 to N-1); -- Token Output tout : out std_logic -- Unused Token ); end component; -- Blocking Signals signal BH : std_logic_vector(L to N-L-1) := (others => '-'); -- Window: L to N-L-1 signal BV : std_logic_vector(L to N-L-1) := (others => '-'); -- Window: L -- put rotates left signal BU : std_logic_vector(2*L to 2*N-2*L-2) := (others => '-'); -- Window: N-1 to 2*N-2*L-2 -- put rotates right signal BD : std_logic_vector(2*L to 2*N-2*L-2) := (others => '-'); -- Window: 2*L to N-1 -- put rotates left signal s : std_logic_vector(L to N-L-1); signal put : std_logic; begin assert false report LF& "Queens@TUD Solver Slice [N="&integer'image(N)&", L="&integer'image(L)&']' &LF& "Copyright (C) 2015-2016 Thomas B. Preusser <thomas.preusser@utexas.edu> " &LF& " Benedikt Reuter <breutr@gmail.com>" &LF& "This design is free software, and you are welcome to redistribute it " &LF& "under the conditions of the GPL version 3. " &LF& "It comes with ABSOLUTELY NO WARRANTY. " &LF& "For details see the notice in the file COPYING."&LF severity note; ---------------------------------------------------------------------------- -- Queen Matrix process(clk) begin if rising_edge(clk) then if put = '1' then QN(L to N-L-2) <= QN(L+1 to N-L-1); else QN(L to N-L-2) <= tColumn'(tColumn'range => '-') & QN(L to N-L-3); end if; end if; end process; ---------------------------------------------------------------------------- -- Blocking Signals process(clk) variable b : std_logic_vector(2*L to 2*N-2*L-2); begin if rising_edge(clk) then -- Initialization if start = '1' then BH <= BH_l; BV <= BV_l; BU <= BU_l; BD <= BD_l; else -- In Progress if put = '1' then -- Add placed Queen BH <= BH or s; BV <= BV(BV'left+1 to BV'right) & BV(BV'left); b := BU(BU'left to N-2) & (BU(N-1 to BU'right) or s); BU <= b(b'right) & b(b'left to b'right-1); b := (BD(BD'left to N-1) or s) & BD(N to BD'right); BD <= b(b'left+1 to b'right) & b(b'left); else -- Clear Queen BH <= BH and not QN(N-L-2); BV <= BV(BV'right) & BV(BV'left to BV'right-1); b := BU(BU'left+1 to BU'right) & BU(BU'left); BU <= b(b'left to N-2) & (b(N-1 to b'right) and not QN(N-L-2)); b := BD(BD'right) & BD(BD'left to BD'right-1); BD <= (b(b'left to N-1) and not QN(N-L-2)) & b(N to b'right); end if; end if; end if; end process; ---------------------------------------------------------------------------- -- Placement Calculation blkPlace : block -- State signal CS : std_logic_vector(L to N-L-1) := (others => '0'); -- Column Front Selector signal Ins : std_logic := '-'; -- Direction signal H : std_logic_vector(L to N-L-1) := (others => '-'); -- Last Placement in active Col -- Combined Blocking signal pass : std_logic_vector(L to N-L-1); signal tout : std_logic; begin -- Combine Blocking Signals pass <= BH or BD(2*L to N-1) or BU(N-1 to 2*N-2*L-2) when BV(L) = '0' else (others => '1'); col : arbit_forward generic map ( N => N-2*L ) port map ( tin => Ins, have => H, pass => pass, grnt => s, tout => tout ); QN(N-L-1) <= s; -- Column Front Selector, a shift-based counter with: process(clk) begin if rising_edge(clk) then if rst = '1' then CS <= (others => '0'); elsif start = '1' then CS <= (others => '0'); CS(CS'left) <= '1'; else if put = '1' then CS <= '0' & CS(CS'left to CS'right-1); else CS <= CS(CS'left+1 to CS'right) & '0'; end if; end if; end if; end process; -- Direction Control process(clk) begin if rising_edge(clk) then if start = '1' then H <= (others => '0'); Ins <= not BV_l(BV_l'left); elsif put = '1' then H <= (others => '0'); Ins <= not BV(L+1); else H <= QN(N-L-2); Ins <= BV(BV'right); end if; end if; end process; -- Control put <= (not tout) and not CS(CS'right); -- Outputs process(clk) begin if rising_edge(clk) then if rst = '1' or start = '1' then sol <= '0'; done <= '0'; else sol <= (not tout) and CS(CS'right); done <= tout and CS(CS'left); end if; end if; end process; end block blkPlace; end rtl;
entity var4 is end; use work.pkg.all; architecture behav of var4 is begin process variable v1 : rec_4; variable v2 : rec_4dyn; begin v2 := v1; wait; end process; end behav;
entity var4 is end; use work.pkg.all; architecture behav of var4 is begin process variable v1 : rec_4; variable v2 : rec_4dyn; begin v2 := v1; wait; end process; end behav;
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p9mk9oDYGr8pmZkWXbY2TLDcNbG5E8gje77Jb79LHblLzT6z9srp4YogxjZP3AdpB91kWPxyMOW6 yZ8yldjKJQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block mVXEkppMj6g1IXjCy7VbBKs+xRMg53vy4CptQMu5kxBNHV1PdY2Z6vTMCczc46movp6tA+re7V/F HsTTtWCV8ZPfOv3mcdhM4UeGfFJKyzETnvTW+7FBhhQEC7rVDuHV/zQIpFu2woT92yIODVDJv0OJ d7TknpWbiizNGWwk/hI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p9mk9oDYGr8pmZkWXbY2TLDcNbG5E8gje77Jb79LHblLzT6z9srp4YogxjZP3AdpB91kWPxyMOW6 yZ8yldjKJQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block mVXEkppMj6g1IXjCy7VbBKs+xRMg53vy4CptQMu5kxBNHV1PdY2Z6vTMCczc46movp6tA+re7V/F HsTTtWCV8ZPfOv3mcdhM4UeGfFJKyzETnvTW+7FBhhQEC7rVDuHV/zQIpFu2woT92yIODVDJv0OJ d7TknpWbiizNGWwk/hI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p9mk9oDYGr8pmZkWXbY2TLDcNbG5E8gje77Jb79LHblLzT6z9srp4YogxjZP3AdpB91kWPxyMOW6 yZ8yldjKJQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block mVXEkppMj6g1IXjCy7VbBKs+xRMg53vy4CptQMu5kxBNHV1PdY2Z6vTMCczc46movp6tA+re7V/F HsTTtWCV8ZPfOv3mcdhM4UeGfFJKyzETnvTW+7FBhhQEC7rVDuHV/zQIpFu2woT92yIODVDJv0OJ d7TknpWbiizNGWwk/hI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p9mk9oDYGr8pmZkWXbY2TLDcNbG5E8gje77Jb79LHblLzT6z9srp4YogxjZP3AdpB91kWPxyMOW6 yZ8yldjKJQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block mVXEkppMj6g1IXjCy7VbBKs+xRMg53vy4CptQMu5kxBNHV1PdY2Z6vTMCczc46movp6tA+re7V/F HsTTtWCV8ZPfOv3mcdhM4UeGfFJKyzETnvTW+7FBhhQEC7rVDuHV/zQIpFu2woT92yIODVDJv0OJ d7TknpWbiizNGWwk/hI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block kaEPvPGfpEJgQQGZTZXbF/2CvE4Ypzvh7RT2RT4lopARsSjuV2b5tLmuzYSb85Q5AFDGlfRWDwtx F2YZzMpA5KuWPN8p6nQWyhLNm/SzroKHii7qBz7lYa3mPULaNNzH3dQ4LQE55pFWYPOfv3yGdzz+ x0MEF1ydRO95dewin0KqN+iIoWFhfzxKJvwhtWiiI/X05UUfC8+LXpcJqGLxKw605Jlb+NeKbbhq fYieug+3ebVwrZawhJ1LjKOdIJ8rUBrE5RUDvZKfy1WLh7meweDSbRCQB5rPDK3OcggQilKZ2mNq 8WI66wOyhQxGZBLF65BiKY2T7DqYxJCp5hGwRQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CVvJhNJw6EHSDIQ731Kbkfkwh9Wl9VKmiOV38T/SVAU+kI3c+cxqP00ao5AoKfnBVtld7H9d2J6J kXhNjYdDnAvSRM/7oTsMkgQ3b7EgkwQVLR7bm4uQPlxcIXIdQ0tZoHzgZNTJUL7DL73vJLbed2E/ KzI+61P+AYGjXhbYkqY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ga5Bitt3CebGZAmuyISY0yRlSG9x1Tj+suj5BLHTSTSYidEbK8uW4qCTr6BxF0yV4Xp11LL0s44p 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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.io_bus_pkg.all; entity real_time_clock_tb is end; architecture tb of real_time_clock_tb is signal clock : std_logic := '0'; signal reset : std_logic := '0'; signal req : t_io_req := c_io_req_init; signal resp : t_io_resp := c_io_resp_init; begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; i_dut: entity work.real_time_clock generic map ( g_freq => 100 ) port map ( clock => clock, reset => reset, req => req, resp => resp ); end;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.io_bus_pkg.all; entity real_time_clock_tb is end; architecture tb of real_time_clock_tb is signal clock : std_logic := '0'; signal reset : std_logic := '0'; signal req : t_io_req := c_io_req_init; signal resp : t_io_resp := c_io_resp_init; begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; i_dut: entity work.real_time_clock generic map ( g_freq => 100 ) port map ( clock => clock, reset => reset, req => req, resp => resp ); end;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.io_bus_pkg.all; entity real_time_clock_tb is end; architecture tb of real_time_clock_tb is signal clock : std_logic := '0'; signal reset : std_logic := '0'; signal req : t_io_req := c_io_req_init; signal resp : t_io_resp := c_io_resp_init; begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; i_dut: entity work.real_time_clock generic map ( g_freq => 100 ) port map ( clock => clock, reset => reset, req => req, resp => resp ); end;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.io_bus_pkg.all; entity real_time_clock_tb is end; architecture tb of real_time_clock_tb is signal clock : std_logic := '0'; signal reset : std_logic := '0'; signal req : t_io_req := c_io_req_init; signal resp : t_io_resp := c_io_resp_init; begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; i_dut: entity work.real_time_clock generic map ( g_freq => 100 ) port map ( clock => clock, reset => reset, req => req, resp => resp ); end;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.io_bus_pkg.all; entity real_time_clock_tb is end; architecture tb of real_time_clock_tb is signal clock : std_logic := '0'; signal reset : std_logic := '0'; signal req : t_io_req := c_io_req_init; signal resp : t_io_resp := c_io_resp_init; begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; i_dut: entity work.real_time_clock generic map ( g_freq => 100 ) port map ( clock => clock, reset => reset, req => req, resp => resp ); end;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity projeto_2 is port ( entrada : in std_logic_vector (2 downto 0) := "000"; reset : in std_logic := '0'; enable : in std_logic := '1'; clk : in std_logic; saida : out std_logic_vector (2 downto 0) ); end projeto_2; architecture Behavioral of projeto_2 is signal auxEntrada : std_logic_vector (2 downto 0); begin process (clk, reset) begin if (reset = '1') then auxEntrada <= "000"; elsif (rising_edge(clk)) then if (enable = '1') then if (entrada = "000") then auxEntrada <= "010"; elsif (entrada = "010") then auxEntrada <= "101"; elsif (entrada = "101") then auxEntrada <= "110"; else auxEntrada <= "000"; end if; end if; saida <= auxEntrada; end if; end process; end Behavioral;
entity FIFO is end entity FIFO; --vhdl_comp_off entity FIFO is --vhdl_comp_on entity FIFO is end entity;
--************************************************************************************************ -- PM_FETCH_DEC(internal module) for AVR core -- Version 2.6! (Special version for the JTAG OCD) -- Designed by Ruslan Lepetenok 14.11.2001 -- Modified 31.05.06 -- Modification: -- Registered ramre/ramwe outputs -- cpu_busy logic modified(affects RCALL/ICALL/CALL instruction interract with interrupt) -- SLEEP and CLRWDT instructions support was added -- V-flag bug fixed (AND/ANDI/OR/ORI/EOR) -- V-flag bug fixed (ADIW/SBIW) -- Unused outputs(sreg_bit_num[2..0],idc_sbi_out,idc_cbi_out,idc_bld_out) were removed. -- Output alu_data_d_in[7..0] was removed. -- Gloabal clock enable(cp2en) was added -- cpu_busy(push/pop) + irq bug was fixed 14.07.05 -- BRXX+IRQ interaction was modified -> cpu_busy -- LDS/STS now requires only two cycles for execution (13.01.06 -> last modificatioon) --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.AVRuCPackage.all; entity pm_fetch_dec is port( -- Clock and reset cp2 : in std_logic; cp2en : in std_logic; ireset : in std_logic; -- JTAG OCD support valid_instr : out std_logic; insert_nop : in std_logic; block_irq : in std_logic; change_flow : out std_logic; -- Program memory pc : out std_logic_vector (15 downto 0); inst : in std_logic_vector (15 downto 0); -- I/O control adr : out std_logic_vector (15 downto 0); iore : out std_logic; iowe : out std_logic; -- Data memory control ramadr : out std_logic_vector (15 downto 0); ramre : out std_logic; ramwe : out std_logic; cpuwait : in std_logic; -- Data paths dbusin : in std_logic_vector (7 downto 0); dbusout : out std_logic_vector (7 downto 0); -- Interrupt irqlines : in std_logic_vector (22 downto 0); irqack : out std_logic; irqackad : out std_logic_vector(4 downto 0); --Sleep sleepi : out std_logic; irqok : out std_logic; --Watchdog wdri : out std_logic; -- ALU interface(Data inputs) alu_data_r_in : out std_logic_vector(7 downto 0); -- ALU interface(Instruction inputs) idc_add_out : out std_logic; idc_adc_out : out std_logic; idc_adiw_out : out std_logic; idc_sub_out : out std_logic; idc_subi_out : out std_logic; idc_sbc_out : out std_logic; idc_sbci_out : out std_logic; idc_sbiw_out : out std_logic; adiw_st_out : out std_logic; sbiw_st_out : out std_logic; idc_and_out : out std_logic; idc_andi_out : out std_logic; idc_or_out : out std_logic; idc_ori_out : out std_logic; idc_eor_out : out std_logic; idc_com_out : out std_logic; idc_neg_out : out std_logic; idc_inc_out : out std_logic; idc_dec_out : out std_logic; idc_cp_out : out std_logic; idc_cpc_out : out std_logic; idc_cpi_out : out std_logic; idc_cpse_out : out std_logic; idc_lsr_out : out std_logic; idc_ror_out : out std_logic; idc_asr_out : out std_logic; idc_swap_out : out std_logic; -- ALU interface(Data output) alu_data_out : in std_logic_vector(7 downto 0); -- ALU interface(Flag outputs) alu_c_flag_out : in std_logic; alu_z_flag_out : in std_logic; alu_n_flag_out : in std_logic; alu_v_flag_out : in std_logic; alu_s_flag_out : in std_logic; alu_h_flag_out : in std_logic; -- General purpose register file interface reg_rd_in : out std_logic_vector (7 downto 0); reg_rd_out : in std_logic_vector (7 downto 0); reg_rd_adr : out std_logic_vector (4 downto 0); reg_rr_out : in std_logic_vector (7 downto 0); reg_rr_adr : out std_logic_vector (4 downto 0); reg_rd_wr : out std_logic; post_inc : out std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS pre_dec : out std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS reg_h_wr : out std_logic; reg_h_out : in std_logic_vector (15 downto 0); reg_h_adr : out std_logic_vector (2 downto 0); -- x,y,z reg_z_out : in std_logic_vector (15 downto 0); -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS -- I/O register file interface sreg_fl_in : out std_logic_vector(7 downto 0); globint : in std_logic; -- SREG I flag sreg_fl_wr_en : out std_logic_vector(7 downto 0); --FLAGS WRITE ENABLE SIGNALS spl_out : in std_logic_vector(7 downto 0); sph_out : in std_logic_vector(7 downto 0); sp_ndown_up : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-) sp_en : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS rampz_out : in std_logic_vector(7 downto 0); -- Bit processor interface bit_num_r_io : out std_logic_vector (2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS bitpr_io_out : in std_logic_vector(7 downto 0); -- SBI/CBI OUT branch : out std_logic_vector (2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION bit_pr_sreg_out : in std_logic_vector(7 downto 0); -- BCLR/BSET/BST(T-FLAG ONLY) bld_op_out : in std_logic_vector(7 downto 0); -- BLD OUT (T FLAG) bit_test_op_out : in std_logic; -- OUTPUT OF SBIC/SBIS/SBRS/SBRC sbi_st_out : out std_logic; cbi_st_out : out std_logic; idc_bst_out : out std_logic; idc_bset_out : out std_logic; idc_bclr_out : out std_logic; idc_sbic_out : out std_logic; idc_sbis_out : out std_logic; idc_sbrs_out : out std_logic; idc_sbrc_out : out std_logic; idc_brbs_out : out std_logic; idc_brbc_out : out std_logic; idc_reti_out : out std_logic); end pm_fetch_dec; architecture RTL of pm_fetch_dec is -- COPIES OF OUTPUTS signal ramadr_reg_in : std_logic_vector(15 downto 0); -- INPUT OF THE ADDRESS REGISTER signal ramadr_reg_en : std_logic; -- ADRESS REGISTER CLOCK ENABLE SIGNAL signal irqack_int : std_logic; signal irqackad_int : std_logic_vector(irqackad'range); -- #################################################### -- INTERNAL SIGNALS -- #################################################### -- NEW SIGNALS signal two_word_inst : std_logic; -- CALL/JMP/STS/LDS INSTRUCTION INDICATOR signal ram_adr_int : std_logic_vector (15 downto 0); constant const_ram_to_reg : std_logic_vector := "00000000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19 constant const_ram_to_io_a : std_logic_vector := "00000000001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F constant const_ram_to_io_b : std_logic_vector := "00000000010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F --constant const_ram_to_io_c : std_logic_vector := "0001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x1000 0x1FFF constant const_ram_to_io_c : std_logic_vector := "0010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x2000 0x2FFF -> change by Zvonimir Bandic constant const_ram_to_io_d : std_logic_vector := "00100000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x1000 0x3FFF -- LD/LDD/ST/STD SIGNALS signal adiw_sbiw_encoder_out : std_logic_vector (4 downto 0); signal adiw_sbiw_encoder_mux_out : std_logic_vector (4 downto 0); -- PROGRAM COUNTER SIGNALS signal program_counter_tmp : std_logic_vector (15 downto 0); -- TO STORE PC DURING LPM/ELPM INSTRUCTIONS signal program_counter : std_logic_vector (15 downto 0); signal program_counter_in : std_logic_vector (15 downto 0); signal program_counter_high_fr : std_logic_vector (7 downto 0); -- TO STORE PC FOR CALL,IRQ,RCALL,ICALL signal pc_low : std_logic_vector (7 downto 0); signal pc_high : std_logic_vector (7 downto 0); signal pc_low_en : std_logic; signal pc_high_en : std_logic; signal offset_brbx : std_logic_vector (15 downto 0); -- OFFSET FOR BRCS/BRCC INSTRUCTION !!CHECKED signal offset_rxx : std_logic_vector (15 downto 0); -- OFFSET FOR RJMP/RCALL INSTRUCTION !!CHECKED signal pa15_pm : std_logic; -- ADDRESS LINE 15 FOR LPM/ELPM INSTRUCTIONS ('0' FOR LPM,RAMPZ(0) FOR ELPM) signal alu_reg_wr : std_logic; -- ALU INSTRUCTIONS PRODUCING WRITE TO THE GENERAL PURPOSE REGISTER FILE -- DATA MEMORY,GENERAL PURPOSE REGISTERS AND I/O REGISTERS LOGIC --! IMPORTANT NOTICE : OPERATIONS WHICH USE STACK POINTER (SPH:SPL) CAN NOT ACCCSESS GENERAL -- PURPOSE REGISTER FILE AND INPUT/OUTPUT REGISTER FILE ! -- THESE OPERATIONS ARE : RCALL/ICALL/CALL/RET/RETI/PUSH/POP INSTRUCTIONS AND INTERRUPT signal reg_file_adr_space : std_logic; -- ACCSESS TO THE REGISTER FILE signal io_file_adr_space : std_logic; -- ACCSESS TO THE I/O FILE -- STATE MACHINES SIGNALS signal irq_start : std_logic; signal nirq_st0 : std_logic; signal irq_st1 : std_logic; signal irq_st2 : std_logic; signal irq_st3 : std_logic; signal ncall_st0 : std_logic; signal call_st1 : std_logic; signal call_st2 : std_logic; signal call_st3 : std_logic; signal nrcall_st0 : std_logic; signal rcall_st1 : std_logic; signal rcall_st2 : std_logic; signal nicall_st0 : std_logic; signal icall_st1 : std_logic; signal icall_st2 : std_logic; signal njmp_st0 : std_logic; signal jmp_st1 : std_logic; signal jmp_st2 : std_logic; signal ijmp_st : std_logic; signal rjmp_st : std_logic; signal nret_st0 : std_logic; signal ret_st1 : std_logic; signal ret_st2 : std_logic; signal ret_st3 : std_logic; signal nreti_st0 : std_logic; signal reti_st1 : std_logic; signal reti_st2 : std_logic; signal reti_st3 : std_logic; signal brxx_st : std_logic; -- BRANCHES signal adiw_st : std_logic; signal sbiw_st : std_logic; signal nskip_inst_st0 : std_logic; signal skip_inst_st1 : std_logic; signal skip_inst_st2 : std_logic; -- ALL SKIP INSTRUCTIONS SBRS/SBRC/SBIS/SBIC/CPSE signal skip_inst_start : std_logic; signal nlpm_st0 : std_logic; signal lpm_st1 : std_logic; signal lpm_st2 : std_logic; signal nelpm_st0 : std_logic; signal elpm_st1 : std_logic; signal elpm_st2 : std_logic; --signal nsts_st0 : std_logic; --signal sts_st1 : std_logic; --signal sts_st2 : std_logic; signal sts_st : std_logic; --signal nlds_st0 : std_logic; --signal lds_st1 : std_logic; --signal lds_st2 : std_logic; signal lds_st : std_logic; signal st_st : std_logic; signal ld_st : std_logic; signal sbi_st : std_logic; signal cbi_st : std_logic; signal push_st : std_logic; signal pop_st : std_logic; -- INTERNAL STATE MACHINES signal nop_insert_st : std_logic; signal cpu_busy : std_logic; -- INTERNAL COPIES OF OUTPUTS signal pc_int : std_logic_vector (15 downto 0); signal adr_int : std_logic_vector (15 downto 0); signal iore_int : std_logic; signal iowe_int : std_logic; signal ramadr_int : std_logic_vector (15 downto 0); signal ramre_int : std_logic; signal ramwe_int : std_logic; signal dbusout_int : std_logic_vector (7 downto 0); -- COMMAND REGISTER signal instruction_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER signal instruction_code_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER WITH NOP INSERTION signal instruction_reg_ena : std_logic; -- CLOCK ENABLE -- IRQ INTERNAL LOGIC signal irq_int : std_logic; signal irq_vector_adr : std_logic_vector(15 downto 0); -- INTERRUPT RELATING REGISTERS signal pc_for_interrupt : std_logic_vector(15 downto 0); -- DATA EXTRACTOR SIGNALS signal dex_dat8_immed : std_logic_vector (7 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ANDI,ORI,SUBI,SBCI,CPI,LDI signal dex_dat6_immed : std_logic_vector (5 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ADIW,SBIW signal dex_adr12mem_s : std_logic_vector (11 downto 0); -- RELATIVE ADDRESS (SIGNED) -> RCALL,RJMP signal dex_adr6port : std_logic_vector (5 downto 0); -- I/O PORT ADDRESS -> IN,OUT signal dex_adr5port : std_logic_vector (4 downto 0); -- I/O PORT ADDRESS -> CBI,SBI,SBIC,SBIS signal dex_adr_disp : std_logic_vector (5 downto 0); -- DISPLACEMENT FO ADDDRESS -> STD,LDD signal dex_condition : std_logic_vector (2 downto 0); -- CONDITION -> BRBC,BRBS signal dex_bitnum_sreg : std_logic_vector (2 downto 0); -- NUMBER OF BIT IN SREG -> BCLR,BSET signal dex_adrreg_r : std_logic_vector (4 downto 0); -- SOURCE REGISTER ADDRESS -> ....... signal dex_adrreg_d : std_logic_vector (4 downto 0); -- DESTINATION REGISTER ADDRESS -> ...... signal dex_bitop_bitnum : std_logic_vector(2 downto 0); -- NUMBER OF BIT FOR BIT ORIENTEDE OPERATION -> BST/BLD+SBI/CBI+SBIC/SBIS+SBRC/SBRS !! CHECKED signal dex_brxx_offset : std_logic_vector (6 downto 0); -- RELATIVE ADDRESS (SIGNED) -> BRBC,BRBS !! CHECKED signal dex_adiw_sbiw_reg_adr : std_logic_vector (1 downto 0); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS signal dex_adrreg_d_latched : std_logic_vector (4 downto 0); -- STORE ADDRESS OF DESTINATION REGISTER FOR LDS/STS/POP INSTRUCTIONS signal gp_reg_tmp : std_logic_vector (7 downto 0); -- STORE DATA FROM THE REGISTERS FOR STS,ST INSTRUCTIONS signal cbi_sbi_io_adr_tmp : std_logic_vector (4 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION signal cbi_sbi_bit_num_tmp : std_logic_vector (2 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION -- INSTRUCTIONS DECODER SIGNALS signal idc_adc : std_logic; -- INSTRUCTION ADC signal idc_add : std_logic; -- INSTRUCTION ADD signal idc_adiw : std_logic; -- INSTRUCTION ADIW signal idc_and : std_logic; -- INSTRUCTION AND signal idc_andi : std_logic; -- INSTRUCTION ANDI signal idc_asr : std_logic; -- INSTRUCTION ASR signal idc_bclr : std_logic; -- INSTRUCTION BCLR signal idc_bld : std_logic; -- INSTRUCTION BLD signal idc_brbc : std_logic; -- INSTRUCTION BRBC signal idc_brbs : std_logic; -- INSTRUCTION BRBS signal idc_bset : std_logic; -- INSTRUCTION BSET signal idc_bst : std_logic; -- INSTRUCTION BST signal idc_call : std_logic; -- INSTRUCTION CALL signal idc_cbi : std_logic; -- INSTRUCTION CBI signal idc_com : std_logic; -- INSTRUCTION COM signal idc_cp : std_logic; -- INSTRUCTION CP signal idc_cpc : std_logic; -- INSTRUCTION CPC signal idc_cpi : std_logic; -- INSTRUCTION CPI signal idc_cpse : std_logic; -- INSTRUCTION CPSE signal idc_dec : std_logic; -- INSTRUCTION DEC signal idc_elpm : std_logic; -- INSTRUCTION ELPM signal idc_eor : std_logic; -- INSTRUCTION EOR signal idc_icall : std_logic; -- INSTRUCTION ICALL signal idc_ijmp : std_logic; -- INSTRUCTION IJMP signal idc_in : std_logic; -- INSTRUCTION IN signal idc_inc : std_logic; -- INSTRUCTION INC signal idc_jmp : std_logic; -- INSTRUCTION JMP signal idc_ld_x : std_logic; -- INSTRUCTION LD Rx,X ; LD Rx,X+ ;LD Rx,-X signal idc_ld_y : std_logic; -- INSTRUCTION LD Rx,Y ; LD Rx,Y+ ;LD Rx,-Y signal idc_ldd_y : std_logic; -- INSTRUCTION LDD Rx,Y+q signal idc_ld_z : std_logic; -- INSTRUCTION LD Rx,Z ; LD Rx,Z+ ;LD Rx,-Z signal idc_ldd_z : std_logic; -- INSTRUCTION LDD Rx,Z+q signal idc_ldi : std_logic; -- INSTRUCTION LDI signal idc_lds : std_logic; -- INSTRUCTION LDS signal idc_lpm : std_logic; -- INSTRUCTION LPM signal idc_lsr : std_logic; -- INSTRUCTION LSR signal idc_mov : std_logic; -- INSTRUCTION MOV signal idc_mul : std_logic; -- INSTRUCTION MUL signal idc_neg : std_logic; -- INSTRUCTION NEG signal idc_nop : std_logic; -- INSTRUCTION NOP signal idc_or : std_logic; -- INSTRUCTION OR signal idc_ori : std_logic; -- INSTRUCTION ORI signal idc_out : std_logic; -- INSTRUCTION OUT signal idc_pop : std_logic; -- INSTRUCTION POP signal idc_push : std_logic; -- INSTRUCTION PUSH signal idc_rcall : std_logic; -- INSTRUCTION RCALL signal idc_ret : std_logic; -- INSTRUCTION RET signal idc_reti : std_logic; -- INSTRUCTION RETI signal idc_rjmp : std_logic; -- INSTRUCTION RJMP signal idc_ror : std_logic; -- INSTRUCTION ROR signal idc_sbc : std_logic; -- INSTRUCTION SBC signal idc_sbci : std_logic; -- INSTRUCTION SBCI signal idc_sbi : std_logic; -- INSTRUCTION SBI signal idc_sbic : std_logic; -- INSTRUCTION SBIC signal idc_sbis : std_logic; -- INSTRUCTION SBIS signal idc_sbiw : std_logic; -- INSTRUCTION SBIW signal idc_sbrc : std_logic; -- INSTRUCTION SBRC signal idc_sbrs : std_logic; -- INSTRUCTION SBRS signal idc_sleep : std_logic; -- INSTRUCTION SLEEP signal idc_st_x : std_logic; -- INSTRUCTION LD X,Rx ; LD X+,Rx ;LD -X,Rx signal idc_st_y : std_logic; -- INSTRUCTION LD Y,Rx ; LD Y+,Rx ;LD -Y,Rx signal idc_std_y : std_logic; -- INSTRUCTION LDD Y+q,Rx signal idc_st_z : std_logic; -- INSTRUCTION LD Z,Rx ; LD Z+,Rx ;LD -Z,Rx signal idc_std_z : std_logic; -- INSTRUCTION LDD Z+q,Rx signal idc_sts : std_logic; -- INSTRUCTION STS signal idc_sub : std_logic; -- INSTRUCTION SUB signal idc_subi : std_logic; -- INSTRUCTION SUBI signal idc_swap : std_logic; -- INSTRUCTION SWAP signal idc_wdr : std_logic; -- INSTRUCTION WDR -- ADDITIONAL SIGNALS signal idc_psinc : std_logic; -- POST INCREMENT FLAG FOR LD,ST INSTRUCTIONS signal idc_prdec : std_logic; -- PRE DECREMENT FLAG FOR LD,ST INSTRUCTIONS -- ################################################## -- SREG FLAGS WRITE ENABLE SIGNALS alias sreg_c_wr_en : std_logic is sreg_fl_wr_en(0); alias sreg_z_wr_en : std_logic is sreg_fl_wr_en(1); alias sreg_n_wr_en : std_logic is sreg_fl_wr_en(2); alias sreg_v_wr_en : std_logic is sreg_fl_wr_en(3); alias sreg_s_wr_en : std_logic is sreg_fl_wr_en(4); alias sreg_h_wr_en : std_logic is sreg_fl_wr_en(5); alias sreg_t_wr_en : std_logic is sreg_fl_wr_en(6); alias sreg_i_wr_en : std_logic is sreg_fl_wr_en(7); signal sreg_bop_wr_en : std_logic_vector (7 downto 0); signal sreg_adr_eq : std_logic; -- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& begin -- INSTRUCTION FETCH instruction_reg_ena <= '1'; -- FOR TEST instruction_fetch:process(cp2,ireset) begin if ireset='0' then -- RESET instruction_reg <= (others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if instruction_reg_ena='1' then instruction_reg <= inst; end if; end if; end if; end process; -- TWO WORDS INSTRUCTION DETECTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER) two_word_inst <= '1' when ((instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010111") or -- CALL (instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010110")) or -- JMP (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010000000") or -- LDS (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010010000") -- STS else '0'; -- TO DETECT CALL/JMP/LDS/STS INSTRUCTIONS FOR SBRS/SBRC/SBIS/SBIC/CPSE -- DATA EXTRACTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER) dex_dat8_immed <= instruction_reg(11 downto 8) & instruction_reg(3 downto 0); dex_dat6_immed <= instruction_reg(7 downto 6) & instruction_reg(3 downto 0); dex_adr12mem_s <= instruction_reg(11 downto 0); dex_adr6port <= instruction_reg(10 downto 9) & instruction_reg(3 downto 0); dex_adr5port <= instruction_reg(7 downto 3); dex_adr_disp <= instruction_reg(13) & instruction_reg(11 downto 10) & instruction_reg(2 downto 0); dex_condition <= instruction_reg(2 downto 0); dex_bitop_bitnum <= instruction_reg(2 downto 0); -- NUMBER(POSITION) OF TESTING BIT IN SBRC/SBRS/SBIC/SBIS INSTRUCTION dex_bitnum_sreg <= instruction_reg(6 downto 4); dex_adrreg_r <= instruction_reg(9) & instruction_reg(3 downto 0); dex_adrreg_d <= instruction_reg(8 downto 4); dex_brxx_offset <= instruction_reg(9 downto 3); -- OFFSET FOR BRBC/BRBS dex_adiw_sbiw_reg_adr <= instruction_reg(5 downto 4); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS --dex_adrindreg <= instruction_reg(3 downto 2); -- LATCH Rd ADDDRESS FOR LDS/STS/POP INSTRUCTIONS latcht_rd_adr:process(cp2,ireset) begin if ireset ='0' then dex_adrreg_d_latched <= (others => '0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if ((idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z) or idc_sts or (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)or idc_lds or idc_pop)='1' then dex_adrreg_d_latched <= dex_adrreg_d; end if; end if; end if; end process; -- +++++++++++++++++++++++++++++++++++++++++++++++++ -- R24:R25/R26:R27/R28:R29/R30:R31 ADIW/SBIW ADDRESS CONTROL LOGIC adiw_sbiw_encoder_out <= "11"&dex_adiw_sbiw_reg_adr&'0'; adiw_sbiw_high_reg_adr:process(cp2,ireset) begin if ireset ='0' then adiw_sbiw_encoder_mux_out <= (others=>'0'); elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_out +1; end if; end if; end process; -- ########################## -- NOP INSERTION --instruction_code_reg <= instruction_reg when nop_insert_st='0' else (others => '0'); instruction_code_reg <= (others => '0') when (nop_insert_st='1') else -- NOP instruction_reg; -- Instruction nop_insert_st <= adiw_st or sbiw_st or cbi_st or sbi_st or rjmp_st or ijmp_st or pop_st or push_st or brxx_st or ld_st or st_st or ncall_st0 or nirq_st0 or nret_st0 or nreti_st0 or nlpm_st0 or njmp_st0 or nrcall_st0 or nicall_st0 or sts_st or lds_st or nskip_inst_st0; -- INSTRUCTION DECODER (CONNECTED AFTER NOP INSERTION LOGIC) idc_adc <= '1' when instruction_code_reg(15 downto 10) = "000111" else '0'; -- 000111XXXXXXXXXX idc_add <= '1' when instruction_code_reg(15 downto 10) = "000011" else '0'; -- 000011XXXXXXXXXX idc_adiw <= '1' when instruction_code_reg(15 downto 8) = "10010110" else '0'; -- 10010110XXXXXXXX idc_and <= '1' when instruction_code_reg(15 downto 10) = "001000" else '0'; -- 001000XXXXXXXXXX idc_andi <= '1' when instruction_code_reg(15 downto 12) = "0111" else '0'; -- 0111XXXXXXXXXXXX idc_asr <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100101" else '0'; -- 1001010XXXXX0101 idc_bclr <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010011000" else '0'; -- 100101001XXX1000 idc_bld <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3) = "11111000" else '0'; -- 1111100XXXXX0XXX idc_brbc <= '1' when instruction_code_reg(15 downto 10) = "111101" else '0'; -- 111101XXXXXXXXXX idc_brbs <= '1' when instruction_code_reg(15 downto 10) = "111100" else '0'; -- 111100XXXXXXXXXX idc_bset <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010001000" else '0'; -- 100101000XXX1000 idc_bst <= '1' when instruction_code_reg(15 downto 9) = "1111101" else '0'; -- 1111101XXXXXXXXX idc_call <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010111" else '0'; -- 1001010XXXXX111X idc_cbi <= '1' when instruction_code_reg(15 downto 8) = "10011000" else '0'; -- 10011000XXXXXXXX idc_com <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100000" else '0'; -- 1001010XXXXX0000 idc_cp <= '1' when instruction_code_reg(15 downto 10) = "000101" else '0'; -- 000101XXXXXXXXXX idc_cpc <= '1' when instruction_code_reg(15 downto 10) = "000001" else '0'; -- 000001XXXXXXXXXX idc_cpi <= '1' when instruction_code_reg(15 downto 12) = "0011" else '0'; -- 0011XXXXXXXXXXXX idc_cpse <= '1' when instruction_code_reg(15 downto 10) = "000100" else '0'; -- 000100XXXXXXXXXX idc_dec <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010101010" else '0'; -- 1001010XXXXX1010 idc_elpm <= '1' when instruction_code_reg = "1001010111011000" else '0'; -- 1001010111011000 idc_eor <= '1' when instruction_code_reg(15 downto 10) = "001001" else '0'; -- 001001XXXXXXXXXX idc_icall<= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101011001" else '0'; -- 10010101XXXX1001 idc_ijmp <= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101001001" else '0'; -- 10010100XXXX1001 idc_in <= '1' when instruction_code_reg(15 downto 11) = "10110" else '0'; -- 10110XXXXXXXXXXX idc_inc <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100011" else '0'; -- 1001010XXXXX0011 idc_jmp <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010110" else '0'; -- 1001010XXXXX110X -- LD,LDD idc_ld_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001100" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001101" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001110" else '0'; idc_ld_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001010") else '0'; idc_ldd_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10001" else '0'; -- 10X0XX0XXXXX1XXX idc_ld_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000010") else '0'; idc_ldd_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10000" else '0'; -- 10X0XX0XXXXX0XXX -- ###### idc_ldi <= '1' when instruction_code_reg(15 downto 12) = "1110" else '0'; -- 1110XXXXXXXXXXXX idc_lds <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010000000" else '0'; -- 1001000XXXXX0000 idc_lpm <= '1' when instruction_code_reg = "1001010111001000" else '0'; -- 1001010111001000 idc_lsr <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100110" else '0'; -- 1001010XXXXX0110 idc_mov <= '1' when instruction_code_reg(15 downto 10) = "001011" else '0'; -- 001011XXXXXXXXXX idc_mul <= '1' when instruction_code_reg(15 downto 10) = "100111" else '0'; -- 100111XXXXXXXXXX idc_neg <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100001" else '0'; -- 1001010XXXXX0001 idc_nop <= '1' when instruction_code_reg = "0000000000000000" else '0'; -- 0000000000000000 idc_or <= '1' when instruction_code_reg(15 downto 10) = "001010" else '0'; -- 001010XXXXXXXXXX idc_ori <= '1' when instruction_code_reg(15 downto 12) = "0110" else '0'; -- 0110XXXXXXXXXXXX idc_out <= '1' when instruction_code_reg(15 downto 11) = "10111" else '0'; -- 10111XXXXXXXXXXX idc_pop <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001111" else '0'; -- 1001000XXXXX1111 idc_push<= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011111" else '0'; -- 1001001XXXXX1111 idc_rcall<= '1' when instruction_code_reg(15 downto 12) = "1101" else '0'; -- 1101XXXXXXXXXXXX idc_ret <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101001000" else '0'; -- 100101010XX01000 idc_reti <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101011000" else '0'; -- 100101010XX11000 idc_rjmp <= '1' when instruction_code_reg(15 downto 12) = "1100" else '0'; -- 1100XXXXXXXXXXXX idc_ror <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100111" else '0'; -- 1001010XXXXX0111 idc_sbc <= '1' when instruction_code_reg(15 downto 10) = "000010" else '0'; -- 000010XXXXXXXXXX idc_sbci <= '1' when instruction_code_reg(15 downto 12) = "0100" else '0'; -- 0100XXXXXXXXXXXX idc_sbi <= '1' when instruction_code_reg(15 downto 8) = "10011010" else '0'; -- 10011010XXXXXXXX idc_sbic <= '1' when instruction_code_reg(15 downto 8) = "10011001" else '0'; -- 10011001XXXXXXXX idc_sbis <= '1' when instruction_code_reg(15 downto 8) = "10011011" else '0'; -- 10011011XXXXXXXX idc_sbiw <= '1' when instruction_code_reg(15 downto 8) = "10010111" else '0'; -- 10010111XXXXXXXX idc_sbrc <= '1' when instruction_code_reg(15 downto 9) = "1111110" else '0'; -- 1111110XXXXXXXXX idc_sbrs <= '1' when instruction_code_reg(15 downto 9) = "1111111" else '0'; -- 1111111XXXXXXXXX idc_sleep<= '1' when instruction_code_reg(15 downto 5)&instruction_code_reg(3 downto 0) = "100101011001000" else '0'; -- 10010101100X1000 -- ST,STD idc_st_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011100" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011101" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011110" else '0'; idc_st_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011010") else '0'; idc_std_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10011" else '0'; -- 10X0XX1XXXXX1XXX idc_st_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010010") else '0'; idc_std_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10010" else '0'; -- 10X0XX1XXXXX0XXX -- ###### idc_sts <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010010000" else '0'; -- 1001001XXXXX0000 idc_sub <= '1' when instruction_code_reg(15 downto 10) = "000110" else '0'; -- 000110XXXXXXXXXX idc_subi <= '1' when instruction_code_reg(15 downto 12) = "0101" else '0'; -- 0101XXXXXXXXXXXX idc_swap <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100010" else '0'; -- 1001010XXXXX0010 idc_wdr <= '1' when instruction_code_reg(15 downto 5)&instruction_code_reg(3 downto 0) = "100101011011000" else '0'; -- 10010101101X1000 -- ADDITIONAL SIGNALS idc_psinc <= '1' when (instruction_code_reg(1 downto 0) = "01" and (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0'; -- POST INCREMENT FOR LD/ST INSTRUCTIONS idc_prdec <= '1' when (instruction_code_reg(1 downto 0) = "10" and (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0'; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS -- ########################################################################################################## -- WRITE ENABLE SIGNALS FOR ramadr_reg ramadr_reg_en <= idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or idc_lds or -- LD/LDD/LDS(two cycle execution) idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or idc_sts or -- ST/STS/STS(two cycle execution) idc_push or idc_pop or idc_rcall or (rcall_st1 and not cpuwait) or idc_icall or (icall_st1 and not cpuwait) or -- RCALL/ICALL call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait) or -- CALL/IRQ idc_ret or (ret_st1 and not cpuwait ) or idc_reti or (reti_st1 and not cpuwait); -- RET/RETI -- ?? -- RAMADR MUX ramadr_reg_in <= sph_out&spl_out when (idc_rcall or (rcall_st1 and not cpuwait)or idc_icall or (icall_st1 and not cpuwait)or -- RCALL/ICALL call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait) or -- CALL/IRQ idc_push )='1' else -- PUSH (sph_out&spl_out)+1 when (idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait) or idc_pop)='1' else -- RET/RETI/POP inst when (idc_lds or idc_sts) ='1' else -- LDS/STS (two cycle execution) reg_h_out when (idc_ld_x or idc_ld_y or idc_ld_z or idc_st_x or idc_st_y or idc_st_z)='1' else -- LD/ST (reg_h_out + ("000000000"&dex_adr_disp)); -- LDD/STD -- ADDRESS REGISTER ramadr_reg:process(cp2,ireset) begin if ireset='0' then ramadr_int <= (others => '0'); elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then ramadr_int <= ramadr_reg_in; end if; end if; end if; end process; ramadr <= ramadr_int; -- GENERAL PURPOSE REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS gp_reg_adr:process(cp2,ireset) begin if ireset='0' then reg_file_adr_space <='0'; elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then if (ramadr_reg_in(15 downto 5)=const_ram_to_reg) then reg_file_adr_space <= '1'; -- ADRESS RANGE 0x0000-0x001F -> REGISTERS (R0-R31) else reg_file_adr_space <= '0'; end if; end if; end if; end if; end process; -- I/O REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS io_reg_adr:process(cp2,ireset) begin if ireset='0' then io_file_adr_space<='0'; elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then if (ramadr_reg_in(15 downto 5)=const_ram_to_io_a or ramadr_reg_in(15 downto 5)=const_ram_to_io_b or ramadr_reg_in(15 downto 12)=const_ram_to_io_c) then io_file_adr_space <= '1'; -- ADRESS RANGE 0x0020-0x005F -> I/O PORTS (0x00-0x3F) and ADRESS RANGE 0x1000-0x1FFF -> I/O PORTS (0x0FE0-0x1FDF) User Ports else io_file_adr_space <= '0'; end if; end if; end if; end if; end process; -- ########################################################################################################## -- REGRE/REGWE LOGIC (5 BIT ADDSRESS BUS (INTERNAL ONLY) 32 LOCATIONS (R0-R31)) -- WRITE ENABLE FOR Rd REGISTERS alu_reg_wr <= idc_adc or idc_add or idc_adiw or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or idc_sbiw or sbiw_st or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or idc_swap; reg_rd_wr <= idc_in or alu_reg_wr or idc_bld or -- ALU INSTRUCTIONS + IN/BLD INSRTRUCTION (pop_st or ld_st or lds_st)or -- POP/LD/LDD/LDS INSTRUCTIONS ((st_st or sts_st) and reg_file_adr_space)or -- ST/STD/STS INSTRUCTION lpm_st2 or idc_ldi or idc_mov; -- LPM/LDI/MOV INSTRUCTION reg_rd_adr <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else "00000" when lpm_st2='1' else adiw_sbiw_encoder_out when (idc_adiw or idc_sbiw)='1' else adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else dex_adrreg_d_latched when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else ramadr_int(4 downto 0) when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_d; reg_rr_adr <= ramadr_int(4 downto 0) when ((ld_st or lds_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_d_latched when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_r; -- MULTIPLEXER FOR REGISTER FILE Rd INPUT reg_rd_in <= dbusin when (idc_in or ((lds_st or ld_st)and not reg_file_adr_space) or pop_st)='1' else -- FROM INPUT DATA BUS reg_rr_out when ((lds_st or ld_st) and reg_file_adr_space)='1' else gp_reg_tmp when ((st_st or sts_st) and reg_file_adr_space)='1' else -- ST/STD/STS & ADDRESS FROM 0 TO 31 (REGISTER FILE) bld_op_out when (idc_bld='1')else -- FROM BIT PROCESSOR BLD COMMAND reg_rr_out when (idc_mov='1')else -- FOR MOV INSTRUCTION instruction_reg(15 downto 8) when (lpm_st2='1' and reg_z_out(0)='1') else -- LPM/ELPM instruction_reg(7 downto 0) when (lpm_st2='1' and reg_z_out(0)='0') else -- LPM/ELPM dex_dat8_immed when idc_ldi='1' else alu_data_out; -- FROM ALU DATA OUT -- IORE/IOWE LOGIC (6 BIT ADDRESS adr[5..0] FOR I/O PORTS(64 LOCATIONS)) iore_int <= idc_in or idc_sbi or idc_cbi or idc_sbic or idc_sbis or ((ld_st or lds_st) and io_file_adr_space); -- IN/SBI/CBI iowe_int <= '1' when ((idc_out or sbi_st or cbi_st) or ((st_st or sts_st) and io_file_adr_space))='1' else '0'; -- OUT/SBI/CBI + !! ST/STS/STD -- adr[5..0] BUS MULTIPLEXER adr_int <= "0000000000"&dex_adr6port when (idc_in or idc_out) = '1' else -- IN/OUT INSTRUCTIONS "0000000000"&'0'&dex_adr5port when (idc_cbi or idc_sbi or idc_sbic or idc_sbis) ='1' else -- CBI/SBI (READ PHASE) + SBIS/SBIC "0000000000"&'0'&cbi_sbi_io_adr_tmp when (cbi_st or sbi_st)='1' else -- CBI/SBI (WRITE PHASE) ramadr_int-x"20"; --(6)&ramadr_int(4 downto 0); -- LD/LDS/LDD/ST/STS/STD -- ramre LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS)) --ramre_int <= not(reg_file_adr_space or io_file_adr_space) and -- (ld_st or lds_st2 or pop_st or -- LD/LDD/LDS/POP/ -- ret_st1 or ret_st2 or reti_st1 or reti_st2); -- RET/RETI DataMemoryRead:process(cp2,ireset) begin if ireset='0' then -- Reset ramre_int <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then -- Clock enable case ramre_int is when '0' => if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and ramadr_reg_in(15 downto 12)/=const_ram_to_io_c and ramadr_reg_in(15 downto 5)/=const_ram_to_reg and (idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or -- LD/LDD instruction idc_lds or -- LDS instruction(two cycle execution) idc_pop or -- POP instruction idc_ret or -- RET instruction idc_reti)='1') -- RETI instruction then ramre_int <='1'; end if; when '1' => if ((ld_st or lds_st or pop_st or ret_st2 or reti_st2)and not cpuwait)='1' then ramre_int <='0'; end if; when others => null; end case; end if; end if; end process; -- ramwe LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS)) --ramwe_int <= not(reg_file_adr_space or io_file_adr_space) and -- (st_st or sts_st2 or push_st or rcall_st1 or rcall_st2 or -- ST/STD/STS/PUSH/RCALL -- icall_st1 or icall_st2 or -- ICALL -- call_st2 or call_st3 or -- CALL -- irq_st2 or irq_st3); -- INTERRUPT DataMemoryWrite:process(cp2,ireset) begin if ireset='0' then -- Reset ramwe_int <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then -- Clock enable case ramwe_int is when '0' => if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and ramadr_reg_in(15 downto 12)/=const_ram_to_io_c and ramadr_reg_in(15 downto 5)/=const_ram_to_reg and (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or -- ST/STD instruction idc_sts or -- STS instruction (two cycle execution) idc_push or -- PUSH instruction idc_rcall or -- RCALL instruction idc_icall or -- ICALL instruction call_st1 or -- CALL instruction irq_st1)='1') -- Interrupt then ramwe_int <='1'; end if; when '1' => if ((st_st or sts_st or push_st or rcall_st2 or icall_st2 or call_st3 or irq_st3)and not cpuwait)='1' then ramwe_int <='0'; end if; when others => null; end case; end if; end if; end process; -- DBUSOUT MULTIPLEXER dbusout_mux_logic: for i in dbusout_int'range generate dbusout_int(i)<= (reg_rd_out(i) and (idc_push or idc_sts or (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS (gp_reg_tmp(i) and (st_st or sts_st))or -- NEW (bitpr_io_out(i) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS (program_counter(i) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC (program_counter_high_fr(i) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC (pc_for_interrupt(i) and irq_st1) or (pc_for_interrupt(i+8) and irq_st2) or (reg_rd_out(i) and idc_out); -- OUT end generate; -- ALU CONNECTION -- ALU Rr INPUT MUX alu_data_r_in <= dex_dat8_immed when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi)='1' else "00"&dex_dat6_immed when (idc_adiw or idc_sbiw) ='1' else "00000000" when (adiw_st or sbiw_st) ='1' else reg_rr_out; -- gp_reg_tmp STORES TEMPREOARY THE VALUE OF SOURCE REGISTER DURING ST/STD/STS INSTRUCTION gp_registers_trig:process(cp2,ireset) begin if (ireset='0') then gp_reg_tmp <= (others=>'0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable -- if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or sts_st1)='1' then -- CLOCK ENABLE if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or idc_sts)='1' then -- CLOCK ENABLE gp_reg_tmp <= reg_rd_out; end if; end if; end if; end process; -- ********************************************************************************************************** -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- +++++++++++++++++++++++++++++++++++++++ PROGRAM COUNTER ++++++++++++++++++++++++++++++++++++++++++++++++++ -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ program_counter_high_store:process(cp2,ireset) begin if ireset='0' then -- RESET program_counter_high_fr <=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if (idc_rcall or idc_icall or call_st1 or irq_st1) ='1' then program_counter_high_fr <= program_counter(15 downto 8); -- STORE HIGH BYTE OF THE PROGRAMM COUNTER FOR RCALL/ICALL/CALL INSTRUCTIONS AND INTERRUPTS end if; end if; end if; end process; program_counter_for_lpm_elpm:process(cp2,ireset) begin if ireset='0' then -- RESET program_counter_tmp<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if (idc_lpm or idc_elpm) ='1' then program_counter_tmp <= program_counter; end if; end if; end if; end process; pa15_pm <= rampz_out(0) and idc_elpm; -- '0' WHEN LPM INSTRUCTIONS RAMPZ(0) WHEN ELPM INSTRUCTION -- OFFSET FOR BRBC/BRBS INSTRUCTIONS +63/-64 offset_brbx <= "0000000000"&dex_brxx_offset(5 downto 0) when (dex_brxx_offset(6)='0') else -- + "1111111111"&dex_brxx_offset(5 downto 0); -- - -- OFFSET FOR RJMP/RCALL INSTRUCTIONS +2047/-2048 offset_rxx <= "00000"&dex_adr12mem_s(10 downto 0) when (dex_adr12mem_s(11)='0') else -- + "11111"&dex_adr12mem_s(10 downto 0); -- - program_counter <= pc_high&pc_low; program_counter_in <= program_counter + offset_brbx when ((idc_brbc or idc_brbs) and bit_test_op_out) ='1'else -- BRBC/BRBS program_counter + offset_rxx when (idc_rjmp or idc_rcall)='1'else -- RJMP/RCALL reg_z_out when (idc_ijmp or idc_icall)='1'else -- IJMP/ICALL pa15_pm&reg_z_out(15 downto 1) when (idc_lpm or idc_elpm) ='1'else -- LPM/ELPM instruction_reg when (jmp_st1 or call_st1)='1'else -- JMP/CALL "0000000000"&irqackad_int&'0' when irq_st1 ='1' else -- INTERRUPT dbusin&"00000000" when (ret_st1 or reti_st1)='1' else -- RET/RETI -> PC HIGH BYTE "00000000"&dbusin when (ret_st2 or reti_st2)='1' else -- RET/RETI -> PC LOW BYTE program_counter_tmp when (lpm_st1)='1' -- AFTER LPM/ELPM INSTRUCTION else program_counter+1; -- THE MOST USUAL CASE pc_low_en <= not (idc_ld_x or idc_ld_y or idc_ld_z or idc_ldd_y or idc_ldd_z or idc_st_x or idc_st_y or idc_st_z or idc_std_y or idc_std_z or ((sts_st or lds_st) and cpuwait)or idc_adiw or idc_sbiw or idc_push or idc_pop or idc_cbi or idc_sbi or rcall_st1 or icall_st1 or call_st2 or irq_st2 or cpuwait or ret_st1 or reti_st1); pc_high_en <= not (idc_ld_x or idc_ld_y or idc_ld_z or idc_ldd_y or idc_ldd_z or idc_st_x or idc_st_y or idc_st_z or idc_std_y or idc_std_z or ((sts_st or lds_st) and cpuwait) or idc_adiw or idc_sbiw or idc_push or idc_pop or idc_cbi or idc_sbi or rcall_st1 or icall_st1 or call_st2 or irq_st2 or cpuwait or ret_st2 or reti_st2); program_counter_low:process(cp2,ireset) begin if ireset='0' then -- RESET pc_low<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if pc_low_en ='1' then pc_low <= program_counter_in(7 downto 0); end if; end if; end if; end process; program_counter_high:process(cp2,ireset) begin if ireset='0' then -- RESET pc_high<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if pc_high_en ='1' then pc_high <= program_counter_in(15 downto 8); end if; end if; end if; end process; pc <= program_counter; program_counter_for_interrupt:process(cp2,ireset) begin if ireset='0' then -- RESET pc_for_interrupt <=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if irq_start ='1' then pc_for_interrupt <= program_counter; end if; end if; end if; end process; -- END OF PROGRAM COUNTER -- STATE MACHINES skip_inst_start <= ((idc_sbrc or idc_sbrs or idc_sbic or idc_sbis) and bit_test_op_out)or (idc_cpse and alu_z_flag_out); skip_instruction_sm:process(cp2,ireset) begin if ireset='0' then -- RESET nskip_inst_st0 <= '0'; skip_inst_st1 <= '0'; skip_inst_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nskip_inst_st0 <= (not nskip_inst_st0 and skip_inst_start) or (nskip_inst_st0 and not((skip_inst_st1 and not two_word_inst) or skip_inst_st2)); skip_inst_st1 <= (not skip_inst_st1 and not nskip_inst_st0 and skip_inst_start); skip_inst_st2 <= not skip_inst_st2 and skip_inst_st1 and two_word_inst; end if; end if; end process; alu_state_machines:process(cp2,ireset) begin if ireset='0' then -- RESET adiw_st <= '0'; sbiw_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable adiw_st <= not adiw_st and idc_adiw; sbiw_st <= not sbiw_st and idc_sbiw; end if; end if; end process; lpm_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nlpm_st0 <= '0'; lpm_st1 <= '0'; lpm_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nlpm_st0 <= (not nlpm_st0 and (idc_lpm or idc_elpm)) or (nlpm_st0 and not lpm_st2); lpm_st1 <= (not lpm_st1 and not nlpm_st0 and (idc_lpm or idc_elpm)); -- ?? lpm_st2 <= not lpm_st2 and lpm_st1; end if; end if; end process; lds_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET lds_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable lds_st <= (not lds_st and idc_lds) or (lds_st and cpuwait); end if; end if; end process; sts_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET sts_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable sts_st <= (not sts_st and idc_sts) or (sts_st and cpuwait); end if; end if; end process; jmp_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET njmp_st0 <= '0'; jmp_st1 <= '0'; jmp_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable njmp_st0 <= (not njmp_st0 and idc_jmp) or (njmp_st0 and not jmp_st2); jmp_st1 <= not jmp_st1 and not njmp_st0 and idc_jmp; -- ?? jmp_st2 <= not jmp_st2 and jmp_st1; end if; end if; end process; rcall_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nrcall_st0 <= '0'; rcall_st1 <= '0'; rcall_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nrcall_st0 <= (not nrcall_st0 and idc_rcall) or (nrcall_st0 and not (rcall_st2 and not cpuwait)); rcall_st1 <= (not rcall_st1 and not nrcall_st0 and idc_rcall) or (rcall_st1 and cpuwait); rcall_st2 <= (not rcall_st2 and rcall_st1 and not cpuwait) or (rcall_st2 and cpuwait); end if; end if; end process; icall_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nicall_st0 <= '0'; icall_st1 <= '0'; icall_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nicall_st0 <= (not nicall_st0 and idc_icall) or (nicall_st0 and not (icall_st2 and not cpuwait)); icall_st1 <= (not icall_st1 and not nicall_st0 and idc_icall) or (icall_st1 and cpuwait); icall_st2 <= (not icall_st2 and icall_st1 and not cpuwait) or (icall_st2 and cpuwait); end if; end if; end process; call_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET ncall_st0 <= '0'; call_st1 <= '0'; call_st2 <= '0'; call_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable ncall_st0 <= (not ncall_st0 and idc_call) or (ncall_st0 and not( call_st3 and not cpuwait)); call_st1 <= not call_st1 and not ncall_st0 and idc_call; call_st2 <= (not call_st2 and call_st1) or (call_st2 and cpuwait); call_st3 <= (not call_st3 and call_st2 and not cpuwait) or (call_st3 and cpuwait); end if; end if; end process; ret_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nret_st0 <= '0'; ret_st1 <= '0'; ret_st2 <= '0'; ret_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nret_st0 <= (not nret_st0 and idc_ret) or (nret_st0 and not ret_st3); ret_st1 <= (not ret_st1 and not nret_st0 and idc_ret) or (ret_st1 and cpuwait); ret_st2 <= (not ret_st2 and ret_st1 and not cpuwait) or (ret_st2 and cpuwait) ; ret_st3 <= not ret_st3 and ret_st2 and not cpuwait; end if; end if; end process; reti_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nreti_st0 <= '0'; reti_st1 <= '0'; reti_st2 <= '0'; reti_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nreti_st0 <= (not nreti_st0 and idc_reti) or (nreti_st0 and not reti_st3); reti_st1 <= (not reti_st1 and not nreti_st0 and idc_reti) or (reti_st1 and cpuwait); reti_st2 <= (not reti_st2 and reti_st1 and not cpuwait) or (reti_st2 and cpuwait) ; reti_st3 <= not reti_st3 and reti_st2 and not cpuwait; end if; end if; end process; -- INTERRUPT LOGIC AND STATE MACHINE irq_int <= '0' when irqlines="00000000000000000000000" else '1'; irq_vector_adr(15 downto 6)<=(others => '0'); irq_vector_adr(0) <= '0'; -- PRIORITY ENCODER irq_vector_adr(5 downto 1) <= "00001" when irqlines(0)='1' else -- 0x0002 "00010" when irqlines(1)='1' else -- 0x0004 "00011" when irqlines(2)='1' else -- 0x0006 "00100" when irqlines(3)='1' else -- 0x0008 "00101" when irqlines(4)='1' else -- 0x000A "00110" when irqlines(5)='1' else -- 0x000C "00111" when irqlines(6)='1' else -- 0x000E "01000" when irqlines(7)='1' else -- 0x0010 "01001" when irqlines(8)='1' else -- 0x0012 "01010" when irqlines(9)='1' else -- 0x0014 "01011" when irqlines(10)='1' else -- 0x0016 "01100" when irqlines(11)='1' else -- 0x0018 "01101" when irqlines(12)='1' else -- 0x001A "01110" when irqlines(13)='1' else -- 0x001C "01111" when irqlines(14)='1' else -- 0x001E "10000" when irqlines(15)='1' else -- 0x0020 "10001" when irqlines(16)='1' else -- 0x0022 "10010" when irqlines(17)='1' else -- 0x0024 "10011" when irqlines(18)='1' else -- 0x0026 "10100" when irqlines(19)='1' else -- 0x0028 "10101" when irqlines(20)='1' else -- 0x002A "10110" when irqlines(21)='1' else -- 0x002C "10111" when irqlines(22)='1' else -- 0x002E "00000"; -- MULTI CYCLE INSTRUCTION FLAG FOR IRQ cpu_busy <= idc_adiw or idc_sbiw or idc_cbi or idc_sbi or idc_rjmp or idc_ijmp or idc_jmp or jmp_st1 or -- idc_brbs or idc_brbc or -- Old variant ((idc_brbc or idc_brbs) and bit_test_op_out) or idc_lpm or lpm_st1 or skip_inst_start or (skip_inst_st1 and two_word_inst) or idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or (ld_st and cpuwait) or idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or (st_st and cpuwait) or idc_lds or (lds_st and cpuwait) or idc_sts or (sts_st and cpuwait) or idc_rcall or rcall_st1 or (rcall_st2 and cpuwait) or -- RCALL idc_icall or icall_st1 or (icall_st2 and cpuwait) or -- ICALL idc_call or call_st1 or call_st2 or (call_st3 and cpuwait) or -- CALL idc_push or (push_st and cpuwait) or -- PUSH (added 14.07.05) idc_pop or (pop_st and cpuwait) or -- POP (added 14.07.05) (idc_bclr and sreg_bop_wr_en(7)) or -- ??? CLI (iowe_int and sreg_adr_eq and not dbusout_int(7))or -- ??? Writing '0' to I flag (OUT/STD/ST/STD) nirq_st0 or -- idc_ret or nret_st0 or -- Old variant idc_ret or ret_st1 or ret_st2 or -- idc_reti or nreti_st0; -- At least one instruction must be executed after RETI and before the new interrupt. idc_reti or reti_st1 or reti_st2; sreg_adr_eq <= '1' when adr_int=SREG_Address else '0'; --irq_start <= irq_int and not cpu_busy and globint; irq_start <= irq_int and not cpu_busy and globint; irq_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nirq_st0 <= '0'; irq_st1 <= '0'; irq_st2 <= '0'; irq_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nirq_st0 <= (not nirq_st0 and irq_start) or (nirq_st0 and not (irq_st3 and not cpuwait)); irq_st1 <= (not irq_st1 and not nirq_st0 and irq_start); irq_st2 <= (not irq_st2 and irq_st1) or (irq_st2 and cpuwait); irq_st3 <= (not irq_st3 and irq_st2 and not cpuwait) or (irq_st3 and cpuwait); end if; end if; end process; irqack_reg:process(cp2,ireset) begin if ireset='0' then -- RESET irqack_int<='0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable irqack_int<= not irqack_int and irq_start; end if; end if; end process; irqack <= irqack_int; irqackad_reg:process(cp2,ireset) begin if ireset='0' then -- RESET irqackad_int<=(others=>'0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable irqackad_int<=irq_vector_adr(5 downto 1); end if; end if; end process; irqackad <= irqackad_int; -- ******************************************************************************************* rjmp_push_pop_ijmp_state_brxx_machine:process(cp2,ireset) begin if ireset='0' then -- RESET rjmp_st <= '0'; ijmp_st <= '0'; push_st <= '0'; pop_st <= '0'; brxx_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable rjmp_st <= idc_rjmp; -- ?? ijmp_st <= idc_ijmp; push_st <= (not push_st and idc_push) or (push_st and cpuwait); pop_st <= (not pop_st and idc_pop) or (pop_st and cpuwait); brxx_st <= not brxx_st and (idc_brbc or idc_brbs) and bit_test_op_out; end if; end if; end process; -- LD/LDD/ST/STD ld_st_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET ld_st <= '0'; st_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable ld_st <= (not ld_st and (idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z)) or (ld_st and cpuwait); st_st <= (not st_st and (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)) or (st_st and cpuwait); end if; end if; end process; -- SBI/CBI sbi_cbi_machine:process(cp2,ireset) begin if ireset='0' then -- RESET sbi_st <= '0'; cbi_st <= '0'; cbi_sbi_io_adr_tmp <= (others => '0'); cbi_sbi_bit_num_tmp <= (others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable sbi_st <= not sbi_st and idc_sbi; cbi_st <= not cbi_st and idc_cbi; cbi_sbi_io_adr_tmp <= dex_adr5port; cbi_sbi_bit_num_tmp <= dex_bitop_bitnum; end if; end if; end process; -- ######################################################################################## -- SREG FLAGS WRITE ENABLE LOGIC bclr_bset_op_en_logic:for i in sreg_bop_wr_en'range generate sreg_bop_wr_en(i) <= '1' when (dex_bitnum_sreg=i and (idc_bclr or idc_bset)='1') else '0'; end generate; sreg_c_wr_en <= idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_com or idc_neg or idc_cp or idc_cpc or idc_cpi or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(0); sreg_z_wr_en <= idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(1); sreg_n_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or sbiw_st or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(2); sreg_v_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or -- idc_adiw idc_sbc or idc_sbci or sbiw_st or idc_neg or idc_com or -- idc_sbiw idc_inc or idc_dec or idc_cp or idc_cpc or idc_cpi or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(3) or idc_and or idc_andi or idc_or or idc_ori or idc_eor; -- V-flag bug fixing sreg_s_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or sbiw_st or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(4); sreg_h_wr_en <= idc_add or idc_adc or idc_sub or idc_subi or idc_cp or idc_cpc or idc_cpi or idc_sbc or idc_sbci or idc_neg or sreg_bop_wr_en(5); sreg_t_wr_en <= idc_bst or sreg_bop_wr_en(6); sreg_i_wr_en <= irq_st1 or reti_st3 or sreg_bop_wr_en(7); -- WAS "irq_start" sreg_fl_in <= bit_pr_sreg_out when (idc_bst or idc_bclr or idc_bset)='1' else -- TO THE SREG reti_st3&'0'&alu_h_flag_out&alu_s_flag_out&alu_v_flag_out&alu_n_flag_out&alu_z_flag_out&alu_c_flag_out; -- ################################################################################################################# -- ********************************************************************************************* -- ************** INSTRUCTION DECODER OUTPUTS FOR THE OTHER BLOCKS **************************** -- ********************************************************************************************* -- FOR ALU idc_add_out <= idc_add; idc_adc_out <= idc_adc; idc_adiw_out <= idc_adiw; idc_sub_out <= idc_sub; idc_subi_out <= idc_subi; idc_sbc_out <= idc_sbc; idc_sbci_out <= idc_sbci; idc_sbiw_out <= idc_sbiw; adiw_st_out <= adiw_st; sbiw_st_out <= sbiw_st; idc_and_out <= idc_and; idc_andi_out <= idc_andi; idc_or_out <= idc_or; idc_ori_out <= idc_ori; idc_eor_out <= idc_eor; idc_com_out <= idc_com; idc_neg_out <= idc_neg; idc_inc_out <= idc_inc; idc_dec_out <= idc_dec; idc_cp_out <= idc_cp; idc_cpc_out <= idc_cpc; idc_cpi_out <= idc_cpi; idc_cpse_out <= idc_cpse; idc_lsr_out <= idc_lsr; idc_ror_out <= idc_ror; idc_asr_out <= idc_asr; idc_swap_out <= idc_swap; -- FOR THE BIT PROCESSOR sbi_st_out <= sbi_st; cbi_st_out <= cbi_st; idc_bst_out <= idc_bst; idc_bset_out <= idc_bset; idc_bclr_out <= idc_bclr; idc_sbic_out <= idc_sbic; idc_sbis_out <= idc_sbis; idc_sbrs_out <= idc_sbrs; idc_sbrc_out <= idc_sbrc; idc_brbs_out <= idc_brbs; idc_brbc_out <= idc_brbc; idc_reti_out <= idc_reti; -- POST INCREMENT/PRE DECREMENT FOR THE X,Y,Z REGISTERS post_inc <= idc_psinc; pre_dec <= idc_prdec; reg_h_wr <= (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z) and (idc_psinc or idc_prdec); reg_h_adr(0)<= idc_st_x or idc_ld_x; reg_h_adr(1)<= idc_st_y or idc_std_y or idc_ld_y or idc_ldd_y; reg_h_adr(2)<= idc_st_z or idc_std_z or idc_ld_z or idc_ldd_z; -- STACK POINTER CONTROL sp_ndown_up <= idc_pop or idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait); -- ????????? sp_en <= idc_push or idc_pop or idc_rcall or (rcall_st1 and not cpuwait) or idc_icall or (icall_st1 and not cpuwait) or idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait) or call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait); --???????? branch <= dex_condition; bit_num_r_io <= cbi_sbi_bit_num_tmp when (cbi_st or sbi_st)='1' else dex_bitop_bitnum; adr <= adr_int; ramre <= ramre_int; ramwe <= ramwe_int; iore <= iore_int; iowe <= iowe_int; dbusout <= dbusout_int; -- Sleep Control sleepi <= idc_sleep; irqok <= irq_int; -- Watchdog wdri <= idc_wdr; -- ************************** JTAG OCD support ************************************ -- Change of flow change_flow <= '0'; valid_instr <= '0'; end RTL;
--************************************************************************************************ -- PM_FETCH_DEC(internal module) for AVR core -- Version 2.6! (Special version for the JTAG OCD) -- Designed by Ruslan Lepetenok 14.11.2001 -- Modified 31.05.06 -- Modification: -- Registered ramre/ramwe outputs -- cpu_busy logic modified(affects RCALL/ICALL/CALL instruction interract with interrupt) -- SLEEP and CLRWDT instructions support was added -- V-flag bug fixed (AND/ANDI/OR/ORI/EOR) -- V-flag bug fixed (ADIW/SBIW) -- Unused outputs(sreg_bit_num[2..0],idc_sbi_out,idc_cbi_out,idc_bld_out) were removed. -- Output alu_data_d_in[7..0] was removed. -- Gloabal clock enable(cp2en) was added -- cpu_busy(push/pop) + irq bug was fixed 14.07.05 -- BRXX+IRQ interaction was modified -> cpu_busy -- LDS/STS now requires only two cycles for execution (13.01.06 -> last modificatioon) --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.AVRuCPackage.all; entity pm_fetch_dec is port( -- Clock and reset cp2 : in std_logic; cp2en : in std_logic; ireset : in std_logic; -- JTAG OCD support valid_instr : out std_logic; insert_nop : in std_logic; block_irq : in std_logic; change_flow : out std_logic; -- Program memory pc : out std_logic_vector (15 downto 0); inst : in std_logic_vector (15 downto 0); -- I/O control adr : out std_logic_vector (15 downto 0); iore : out std_logic; iowe : out std_logic; -- Data memory control ramadr : out std_logic_vector (15 downto 0); ramre : out std_logic; ramwe : out std_logic; cpuwait : in std_logic; -- Data paths dbusin : in std_logic_vector (7 downto 0); dbusout : out std_logic_vector (7 downto 0); -- Interrupt irqlines : in std_logic_vector (22 downto 0); irqack : out std_logic; irqackad : out std_logic_vector(4 downto 0); --Sleep sleepi : out std_logic; irqok : out std_logic; --Watchdog wdri : out std_logic; -- ALU interface(Data inputs) alu_data_r_in : out std_logic_vector(7 downto 0); -- ALU interface(Instruction inputs) idc_add_out : out std_logic; idc_adc_out : out std_logic; idc_adiw_out : out std_logic; idc_sub_out : out std_logic; idc_subi_out : out std_logic; idc_sbc_out : out std_logic; idc_sbci_out : out std_logic; idc_sbiw_out : out std_logic; adiw_st_out : out std_logic; sbiw_st_out : out std_logic; idc_and_out : out std_logic; idc_andi_out : out std_logic; idc_or_out : out std_logic; idc_ori_out : out std_logic; idc_eor_out : out std_logic; idc_com_out : out std_logic; idc_neg_out : out std_logic; idc_inc_out : out std_logic; idc_dec_out : out std_logic; idc_cp_out : out std_logic; idc_cpc_out : out std_logic; idc_cpi_out : out std_logic; idc_cpse_out : out std_logic; idc_lsr_out : out std_logic; idc_ror_out : out std_logic; idc_asr_out : out std_logic; idc_swap_out : out std_logic; -- ALU interface(Data output) alu_data_out : in std_logic_vector(7 downto 0); -- ALU interface(Flag outputs) alu_c_flag_out : in std_logic; alu_z_flag_out : in std_logic; alu_n_flag_out : in std_logic; alu_v_flag_out : in std_logic; alu_s_flag_out : in std_logic; alu_h_flag_out : in std_logic; -- General purpose register file interface reg_rd_in : out std_logic_vector (7 downto 0); reg_rd_out : in std_logic_vector (7 downto 0); reg_rd_adr : out std_logic_vector (4 downto 0); reg_rr_out : in std_logic_vector (7 downto 0); reg_rr_adr : out std_logic_vector (4 downto 0); reg_rd_wr : out std_logic; post_inc : out std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS pre_dec : out std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS reg_h_wr : out std_logic; reg_h_out : in std_logic_vector (15 downto 0); reg_h_adr : out std_logic_vector (2 downto 0); -- x,y,z reg_z_out : in std_logic_vector (15 downto 0); -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS -- I/O register file interface sreg_fl_in : out std_logic_vector(7 downto 0); globint : in std_logic; -- SREG I flag sreg_fl_wr_en : out std_logic_vector(7 downto 0); --FLAGS WRITE ENABLE SIGNALS spl_out : in std_logic_vector(7 downto 0); sph_out : in std_logic_vector(7 downto 0); sp_ndown_up : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-) sp_en : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS rampz_out : in std_logic_vector(7 downto 0); -- Bit processor interface bit_num_r_io : out std_logic_vector (2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS bitpr_io_out : in std_logic_vector(7 downto 0); -- SBI/CBI OUT branch : out std_logic_vector (2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION bit_pr_sreg_out : in std_logic_vector(7 downto 0); -- BCLR/BSET/BST(T-FLAG ONLY) bld_op_out : in std_logic_vector(7 downto 0); -- BLD OUT (T FLAG) bit_test_op_out : in std_logic; -- OUTPUT OF SBIC/SBIS/SBRS/SBRC sbi_st_out : out std_logic; cbi_st_out : out std_logic; idc_bst_out : out std_logic; idc_bset_out : out std_logic; idc_bclr_out : out std_logic; idc_sbic_out : out std_logic; idc_sbis_out : out std_logic; idc_sbrs_out : out std_logic; idc_sbrc_out : out std_logic; idc_brbs_out : out std_logic; idc_brbc_out : out std_logic; idc_reti_out : out std_logic); end pm_fetch_dec; architecture RTL of pm_fetch_dec is -- COPIES OF OUTPUTS signal ramadr_reg_in : std_logic_vector(15 downto 0); -- INPUT OF THE ADDRESS REGISTER signal ramadr_reg_en : std_logic; -- ADRESS REGISTER CLOCK ENABLE SIGNAL signal irqack_int : std_logic; signal irqackad_int : std_logic_vector(irqackad'range); -- #################################################### -- INTERNAL SIGNALS -- #################################################### -- NEW SIGNALS signal two_word_inst : std_logic; -- CALL/JMP/STS/LDS INSTRUCTION INDICATOR signal ram_adr_int : std_logic_vector (15 downto 0); constant const_ram_to_reg : std_logic_vector := "00000000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19 constant const_ram_to_io_a : std_logic_vector := "00000000001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F constant const_ram_to_io_b : std_logic_vector := "00000000010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F --constant const_ram_to_io_c : std_logic_vector := "0001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x1000 0x1FFF constant const_ram_to_io_c : std_logic_vector := "0010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x2000 0x2FFF -> change by Zvonimir Bandic constant const_ram_to_io_d : std_logic_vector := "00100000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x1000 0x3FFF -- LD/LDD/ST/STD SIGNALS signal adiw_sbiw_encoder_out : std_logic_vector (4 downto 0); signal adiw_sbiw_encoder_mux_out : std_logic_vector (4 downto 0); -- PROGRAM COUNTER SIGNALS signal program_counter_tmp : std_logic_vector (15 downto 0); -- TO STORE PC DURING LPM/ELPM INSTRUCTIONS signal program_counter : std_logic_vector (15 downto 0); signal program_counter_in : std_logic_vector (15 downto 0); signal program_counter_high_fr : std_logic_vector (7 downto 0); -- TO STORE PC FOR CALL,IRQ,RCALL,ICALL signal pc_low : std_logic_vector (7 downto 0); signal pc_high : std_logic_vector (7 downto 0); signal pc_low_en : std_logic; signal pc_high_en : std_logic; signal offset_brbx : std_logic_vector (15 downto 0); -- OFFSET FOR BRCS/BRCC INSTRUCTION !!CHECKED signal offset_rxx : std_logic_vector (15 downto 0); -- OFFSET FOR RJMP/RCALL INSTRUCTION !!CHECKED signal pa15_pm : std_logic; -- ADDRESS LINE 15 FOR LPM/ELPM INSTRUCTIONS ('0' FOR LPM,RAMPZ(0) FOR ELPM) signal alu_reg_wr : std_logic; -- ALU INSTRUCTIONS PRODUCING WRITE TO THE GENERAL PURPOSE REGISTER FILE -- DATA MEMORY,GENERAL PURPOSE REGISTERS AND I/O REGISTERS LOGIC --! IMPORTANT NOTICE : OPERATIONS WHICH USE STACK POINTER (SPH:SPL) CAN NOT ACCCSESS GENERAL -- PURPOSE REGISTER FILE AND INPUT/OUTPUT REGISTER FILE ! -- THESE OPERATIONS ARE : RCALL/ICALL/CALL/RET/RETI/PUSH/POP INSTRUCTIONS AND INTERRUPT signal reg_file_adr_space : std_logic; -- ACCSESS TO THE REGISTER FILE signal io_file_adr_space : std_logic; -- ACCSESS TO THE I/O FILE -- STATE MACHINES SIGNALS signal irq_start : std_logic; signal nirq_st0 : std_logic; signal irq_st1 : std_logic; signal irq_st2 : std_logic; signal irq_st3 : std_logic; signal ncall_st0 : std_logic; signal call_st1 : std_logic; signal call_st2 : std_logic; signal call_st3 : std_logic; signal nrcall_st0 : std_logic; signal rcall_st1 : std_logic; signal rcall_st2 : std_logic; signal nicall_st0 : std_logic; signal icall_st1 : std_logic; signal icall_st2 : std_logic; signal njmp_st0 : std_logic; signal jmp_st1 : std_logic; signal jmp_st2 : std_logic; signal ijmp_st : std_logic; signal rjmp_st : std_logic; signal nret_st0 : std_logic; signal ret_st1 : std_logic; signal ret_st2 : std_logic; signal ret_st3 : std_logic; signal nreti_st0 : std_logic; signal reti_st1 : std_logic; signal reti_st2 : std_logic; signal reti_st3 : std_logic; signal brxx_st : std_logic; -- BRANCHES signal adiw_st : std_logic; signal sbiw_st : std_logic; signal nskip_inst_st0 : std_logic; signal skip_inst_st1 : std_logic; signal skip_inst_st2 : std_logic; -- ALL SKIP INSTRUCTIONS SBRS/SBRC/SBIS/SBIC/CPSE signal skip_inst_start : std_logic; signal nlpm_st0 : std_logic; signal lpm_st1 : std_logic; signal lpm_st2 : std_logic; signal nelpm_st0 : std_logic; signal elpm_st1 : std_logic; signal elpm_st2 : std_logic; --signal nsts_st0 : std_logic; --signal sts_st1 : std_logic; --signal sts_st2 : std_logic; signal sts_st : std_logic; --signal nlds_st0 : std_logic; --signal lds_st1 : std_logic; --signal lds_st2 : std_logic; signal lds_st : std_logic; signal st_st : std_logic; signal ld_st : std_logic; signal sbi_st : std_logic; signal cbi_st : std_logic; signal push_st : std_logic; signal pop_st : std_logic; -- INTERNAL STATE MACHINES signal nop_insert_st : std_logic; signal cpu_busy : std_logic; -- INTERNAL COPIES OF OUTPUTS signal pc_int : std_logic_vector (15 downto 0); signal adr_int : std_logic_vector (15 downto 0); signal iore_int : std_logic; signal iowe_int : std_logic; signal ramadr_int : std_logic_vector (15 downto 0); signal ramre_int : std_logic; signal ramwe_int : std_logic; signal dbusout_int : std_logic_vector (7 downto 0); -- COMMAND REGISTER signal instruction_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER signal instruction_code_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER WITH NOP INSERTION signal instruction_reg_ena : std_logic; -- CLOCK ENABLE -- IRQ INTERNAL LOGIC signal irq_int : std_logic; signal irq_vector_adr : std_logic_vector(15 downto 0); -- INTERRUPT RELATING REGISTERS signal pc_for_interrupt : std_logic_vector(15 downto 0); -- DATA EXTRACTOR SIGNALS signal dex_dat8_immed : std_logic_vector (7 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ANDI,ORI,SUBI,SBCI,CPI,LDI signal dex_dat6_immed : std_logic_vector (5 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ADIW,SBIW signal dex_adr12mem_s : std_logic_vector (11 downto 0); -- RELATIVE ADDRESS (SIGNED) -> RCALL,RJMP signal dex_adr6port : std_logic_vector (5 downto 0); -- I/O PORT ADDRESS -> IN,OUT signal dex_adr5port : std_logic_vector (4 downto 0); -- I/O PORT ADDRESS -> CBI,SBI,SBIC,SBIS signal dex_adr_disp : std_logic_vector (5 downto 0); -- DISPLACEMENT FO ADDDRESS -> STD,LDD signal dex_condition : std_logic_vector (2 downto 0); -- CONDITION -> BRBC,BRBS signal dex_bitnum_sreg : std_logic_vector (2 downto 0); -- NUMBER OF BIT IN SREG -> BCLR,BSET signal dex_adrreg_r : std_logic_vector (4 downto 0); -- SOURCE REGISTER ADDRESS -> ....... signal dex_adrreg_d : std_logic_vector (4 downto 0); -- DESTINATION REGISTER ADDRESS -> ...... signal dex_bitop_bitnum : std_logic_vector(2 downto 0); -- NUMBER OF BIT FOR BIT ORIENTEDE OPERATION -> BST/BLD+SBI/CBI+SBIC/SBIS+SBRC/SBRS !! CHECKED signal dex_brxx_offset : std_logic_vector (6 downto 0); -- RELATIVE ADDRESS (SIGNED) -> BRBC,BRBS !! CHECKED signal dex_adiw_sbiw_reg_adr : std_logic_vector (1 downto 0); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS signal dex_adrreg_d_latched : std_logic_vector (4 downto 0); -- STORE ADDRESS OF DESTINATION REGISTER FOR LDS/STS/POP INSTRUCTIONS signal gp_reg_tmp : std_logic_vector (7 downto 0); -- STORE DATA FROM THE REGISTERS FOR STS,ST INSTRUCTIONS signal cbi_sbi_io_adr_tmp : std_logic_vector (4 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION signal cbi_sbi_bit_num_tmp : std_logic_vector (2 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION -- INSTRUCTIONS DECODER SIGNALS signal idc_adc : std_logic; -- INSTRUCTION ADC signal idc_add : std_logic; -- INSTRUCTION ADD signal idc_adiw : std_logic; -- INSTRUCTION ADIW signal idc_and : std_logic; -- INSTRUCTION AND signal idc_andi : std_logic; -- INSTRUCTION ANDI signal idc_asr : std_logic; -- INSTRUCTION ASR signal idc_bclr : std_logic; -- INSTRUCTION BCLR signal idc_bld : std_logic; -- INSTRUCTION BLD signal idc_brbc : std_logic; -- INSTRUCTION BRBC signal idc_brbs : std_logic; -- INSTRUCTION BRBS signal idc_bset : std_logic; -- INSTRUCTION BSET signal idc_bst : std_logic; -- INSTRUCTION BST signal idc_call : std_logic; -- INSTRUCTION CALL signal idc_cbi : std_logic; -- INSTRUCTION CBI signal idc_com : std_logic; -- INSTRUCTION COM signal idc_cp : std_logic; -- INSTRUCTION CP signal idc_cpc : std_logic; -- INSTRUCTION CPC signal idc_cpi : std_logic; -- INSTRUCTION CPI signal idc_cpse : std_logic; -- INSTRUCTION CPSE signal idc_dec : std_logic; -- INSTRUCTION DEC signal idc_elpm : std_logic; -- INSTRUCTION ELPM signal idc_eor : std_logic; -- INSTRUCTION EOR signal idc_icall : std_logic; -- INSTRUCTION ICALL signal idc_ijmp : std_logic; -- INSTRUCTION IJMP signal idc_in : std_logic; -- INSTRUCTION IN signal idc_inc : std_logic; -- INSTRUCTION INC signal idc_jmp : std_logic; -- INSTRUCTION JMP signal idc_ld_x : std_logic; -- INSTRUCTION LD Rx,X ; LD Rx,X+ ;LD Rx,-X signal idc_ld_y : std_logic; -- INSTRUCTION LD Rx,Y ; LD Rx,Y+ ;LD Rx,-Y signal idc_ldd_y : std_logic; -- INSTRUCTION LDD Rx,Y+q signal idc_ld_z : std_logic; -- INSTRUCTION LD Rx,Z ; LD Rx,Z+ ;LD Rx,-Z signal idc_ldd_z : std_logic; -- INSTRUCTION LDD Rx,Z+q signal idc_ldi : std_logic; -- INSTRUCTION LDI signal idc_lds : std_logic; -- INSTRUCTION LDS signal idc_lpm : std_logic; -- INSTRUCTION LPM signal idc_lsr : std_logic; -- INSTRUCTION LSR signal idc_mov : std_logic; -- INSTRUCTION MOV signal idc_mul : std_logic; -- INSTRUCTION MUL signal idc_neg : std_logic; -- INSTRUCTION NEG signal idc_nop : std_logic; -- INSTRUCTION NOP signal idc_or : std_logic; -- INSTRUCTION OR signal idc_ori : std_logic; -- INSTRUCTION ORI signal idc_out : std_logic; -- INSTRUCTION OUT signal idc_pop : std_logic; -- INSTRUCTION POP signal idc_push : std_logic; -- INSTRUCTION PUSH signal idc_rcall : std_logic; -- INSTRUCTION RCALL signal idc_ret : std_logic; -- INSTRUCTION RET signal idc_reti : std_logic; -- INSTRUCTION RETI signal idc_rjmp : std_logic; -- INSTRUCTION RJMP signal idc_ror : std_logic; -- INSTRUCTION ROR signal idc_sbc : std_logic; -- INSTRUCTION SBC signal idc_sbci : std_logic; -- INSTRUCTION SBCI signal idc_sbi : std_logic; -- INSTRUCTION SBI signal idc_sbic : std_logic; -- INSTRUCTION SBIC signal idc_sbis : std_logic; -- INSTRUCTION SBIS signal idc_sbiw : std_logic; -- INSTRUCTION SBIW signal idc_sbrc : std_logic; -- INSTRUCTION SBRC signal idc_sbrs : std_logic; -- INSTRUCTION SBRS signal idc_sleep : std_logic; -- INSTRUCTION SLEEP signal idc_st_x : std_logic; -- INSTRUCTION LD X,Rx ; LD X+,Rx ;LD -X,Rx signal idc_st_y : std_logic; -- INSTRUCTION LD Y,Rx ; LD Y+,Rx ;LD -Y,Rx signal idc_std_y : std_logic; -- INSTRUCTION LDD Y+q,Rx signal idc_st_z : std_logic; -- INSTRUCTION LD Z,Rx ; LD Z+,Rx ;LD -Z,Rx signal idc_std_z : std_logic; -- INSTRUCTION LDD Z+q,Rx signal idc_sts : std_logic; -- INSTRUCTION STS signal idc_sub : std_logic; -- INSTRUCTION SUB signal idc_subi : std_logic; -- INSTRUCTION SUBI signal idc_swap : std_logic; -- INSTRUCTION SWAP signal idc_wdr : std_logic; -- INSTRUCTION WDR -- ADDITIONAL SIGNALS signal idc_psinc : std_logic; -- POST INCREMENT FLAG FOR LD,ST INSTRUCTIONS signal idc_prdec : std_logic; -- PRE DECREMENT FLAG FOR LD,ST INSTRUCTIONS -- ################################################## -- SREG FLAGS WRITE ENABLE SIGNALS alias sreg_c_wr_en : std_logic is sreg_fl_wr_en(0); alias sreg_z_wr_en : std_logic is sreg_fl_wr_en(1); alias sreg_n_wr_en : std_logic is sreg_fl_wr_en(2); alias sreg_v_wr_en : std_logic is sreg_fl_wr_en(3); alias sreg_s_wr_en : std_logic is sreg_fl_wr_en(4); alias sreg_h_wr_en : std_logic is sreg_fl_wr_en(5); alias sreg_t_wr_en : std_logic is sreg_fl_wr_en(6); alias sreg_i_wr_en : std_logic is sreg_fl_wr_en(7); signal sreg_bop_wr_en : std_logic_vector (7 downto 0); signal sreg_adr_eq : std_logic; -- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& begin -- INSTRUCTION FETCH instruction_reg_ena <= '1'; -- FOR TEST instruction_fetch:process(cp2,ireset) begin if ireset='0' then -- RESET instruction_reg <= (others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if instruction_reg_ena='1' then instruction_reg <= inst; end if; end if; end if; end process; -- TWO WORDS INSTRUCTION DETECTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER) two_word_inst <= '1' when ((instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010111") or -- CALL (instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010110")) or -- JMP (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010000000") or -- LDS (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010010000") -- STS else '0'; -- TO DETECT CALL/JMP/LDS/STS INSTRUCTIONS FOR SBRS/SBRC/SBIS/SBIC/CPSE -- DATA EXTRACTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER) dex_dat8_immed <= instruction_reg(11 downto 8) & instruction_reg(3 downto 0); dex_dat6_immed <= instruction_reg(7 downto 6) & instruction_reg(3 downto 0); dex_adr12mem_s <= instruction_reg(11 downto 0); dex_adr6port <= instruction_reg(10 downto 9) & instruction_reg(3 downto 0); dex_adr5port <= instruction_reg(7 downto 3); dex_adr_disp <= instruction_reg(13) & instruction_reg(11 downto 10) & instruction_reg(2 downto 0); dex_condition <= instruction_reg(2 downto 0); dex_bitop_bitnum <= instruction_reg(2 downto 0); -- NUMBER(POSITION) OF TESTING BIT IN SBRC/SBRS/SBIC/SBIS INSTRUCTION dex_bitnum_sreg <= instruction_reg(6 downto 4); dex_adrreg_r <= instruction_reg(9) & instruction_reg(3 downto 0); dex_adrreg_d <= instruction_reg(8 downto 4); dex_brxx_offset <= instruction_reg(9 downto 3); -- OFFSET FOR BRBC/BRBS dex_adiw_sbiw_reg_adr <= instruction_reg(5 downto 4); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS --dex_adrindreg <= instruction_reg(3 downto 2); -- LATCH Rd ADDDRESS FOR LDS/STS/POP INSTRUCTIONS latcht_rd_adr:process(cp2,ireset) begin if ireset ='0' then dex_adrreg_d_latched <= (others => '0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if ((idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z) or idc_sts or (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)or idc_lds or idc_pop)='1' then dex_adrreg_d_latched <= dex_adrreg_d; end if; end if; end if; end process; -- +++++++++++++++++++++++++++++++++++++++++++++++++ -- R24:R25/R26:R27/R28:R29/R30:R31 ADIW/SBIW ADDRESS CONTROL LOGIC adiw_sbiw_encoder_out <= "11"&dex_adiw_sbiw_reg_adr&'0'; adiw_sbiw_high_reg_adr:process(cp2,ireset) begin if ireset ='0' then adiw_sbiw_encoder_mux_out <= (others=>'0'); elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_out +1; end if; end if; end process; -- ########################## -- NOP INSERTION --instruction_code_reg <= instruction_reg when nop_insert_st='0' else (others => '0'); instruction_code_reg <= (others => '0') when (nop_insert_st='1') else -- NOP instruction_reg; -- Instruction nop_insert_st <= adiw_st or sbiw_st or cbi_st or sbi_st or rjmp_st or ijmp_st or pop_st or push_st or brxx_st or ld_st or st_st or ncall_st0 or nirq_st0 or nret_st0 or nreti_st0 or nlpm_st0 or njmp_st0 or nrcall_st0 or nicall_st0 or sts_st or lds_st or nskip_inst_st0; -- INSTRUCTION DECODER (CONNECTED AFTER NOP INSERTION LOGIC) idc_adc <= '1' when instruction_code_reg(15 downto 10) = "000111" else '0'; -- 000111XXXXXXXXXX idc_add <= '1' when instruction_code_reg(15 downto 10) = "000011" else '0'; -- 000011XXXXXXXXXX idc_adiw <= '1' when instruction_code_reg(15 downto 8) = "10010110" else '0'; -- 10010110XXXXXXXX idc_and <= '1' when instruction_code_reg(15 downto 10) = "001000" else '0'; -- 001000XXXXXXXXXX idc_andi <= '1' when instruction_code_reg(15 downto 12) = "0111" else '0'; -- 0111XXXXXXXXXXXX idc_asr <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100101" else '0'; -- 1001010XXXXX0101 idc_bclr <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010011000" else '0'; -- 100101001XXX1000 idc_bld <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3) = "11111000" else '0'; -- 1111100XXXXX0XXX idc_brbc <= '1' when instruction_code_reg(15 downto 10) = "111101" else '0'; -- 111101XXXXXXXXXX idc_brbs <= '1' when instruction_code_reg(15 downto 10) = "111100" else '0'; -- 111100XXXXXXXXXX idc_bset <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010001000" else '0'; -- 100101000XXX1000 idc_bst <= '1' when instruction_code_reg(15 downto 9) = "1111101" else '0'; -- 1111101XXXXXXXXX idc_call <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010111" else '0'; -- 1001010XXXXX111X idc_cbi <= '1' when instruction_code_reg(15 downto 8) = "10011000" else '0'; -- 10011000XXXXXXXX idc_com <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100000" else '0'; -- 1001010XXXXX0000 idc_cp <= '1' when instruction_code_reg(15 downto 10) = "000101" else '0'; -- 000101XXXXXXXXXX idc_cpc <= '1' when instruction_code_reg(15 downto 10) = "000001" else '0'; -- 000001XXXXXXXXXX idc_cpi <= '1' when instruction_code_reg(15 downto 12) = "0011" else '0'; -- 0011XXXXXXXXXXXX idc_cpse <= '1' when instruction_code_reg(15 downto 10) = "000100" else '0'; -- 000100XXXXXXXXXX idc_dec <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010101010" else '0'; -- 1001010XXXXX1010 idc_elpm <= '1' when instruction_code_reg = "1001010111011000" else '0'; -- 1001010111011000 idc_eor <= '1' when instruction_code_reg(15 downto 10) = "001001" else '0'; -- 001001XXXXXXXXXX idc_icall<= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101011001" else '0'; -- 10010101XXXX1001 idc_ijmp <= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101001001" else '0'; -- 10010100XXXX1001 idc_in <= '1' when instruction_code_reg(15 downto 11) = "10110" else '0'; -- 10110XXXXXXXXXXX idc_inc <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100011" else '0'; -- 1001010XXXXX0011 idc_jmp <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010110" else '0'; -- 1001010XXXXX110X -- LD,LDD idc_ld_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001100" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001101" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001110" else '0'; idc_ld_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001010") else '0'; idc_ldd_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10001" else '0'; -- 10X0XX0XXXXX1XXX idc_ld_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000010") else '0'; idc_ldd_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10000" else '0'; -- 10X0XX0XXXXX0XXX -- ###### idc_ldi <= '1' when instruction_code_reg(15 downto 12) = "1110" else '0'; -- 1110XXXXXXXXXXXX idc_lds <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010000000" else '0'; -- 1001000XXXXX0000 idc_lpm <= '1' when instruction_code_reg = "1001010111001000" else '0'; -- 1001010111001000 idc_lsr <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100110" else '0'; -- 1001010XXXXX0110 idc_mov <= '1' when instruction_code_reg(15 downto 10) = "001011" else '0'; -- 001011XXXXXXXXXX idc_mul <= '1' when instruction_code_reg(15 downto 10) = "100111" else '0'; -- 100111XXXXXXXXXX idc_neg <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100001" else '0'; -- 1001010XXXXX0001 idc_nop <= '1' when instruction_code_reg = "0000000000000000" else '0'; -- 0000000000000000 idc_or <= '1' when instruction_code_reg(15 downto 10) = "001010" else '0'; -- 001010XXXXXXXXXX idc_ori <= '1' when instruction_code_reg(15 downto 12) = "0110" else '0'; -- 0110XXXXXXXXXXXX idc_out <= '1' when instruction_code_reg(15 downto 11) = "10111" else '0'; -- 10111XXXXXXXXXXX idc_pop <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001111" else '0'; -- 1001000XXXXX1111 idc_push<= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011111" else '0'; -- 1001001XXXXX1111 idc_rcall<= '1' when instruction_code_reg(15 downto 12) = "1101" else '0'; -- 1101XXXXXXXXXXXX idc_ret <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101001000" else '0'; -- 100101010XX01000 idc_reti <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101011000" else '0'; -- 100101010XX11000 idc_rjmp <= '1' when instruction_code_reg(15 downto 12) = "1100" else '0'; -- 1100XXXXXXXXXXXX idc_ror <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100111" else '0'; -- 1001010XXXXX0111 idc_sbc <= '1' when instruction_code_reg(15 downto 10) = "000010" else '0'; -- 000010XXXXXXXXXX idc_sbci <= '1' when instruction_code_reg(15 downto 12) = "0100" else '0'; -- 0100XXXXXXXXXXXX idc_sbi <= '1' when instruction_code_reg(15 downto 8) = "10011010" else '0'; -- 10011010XXXXXXXX idc_sbic <= '1' when instruction_code_reg(15 downto 8) = "10011001" else '0'; -- 10011001XXXXXXXX idc_sbis <= '1' when instruction_code_reg(15 downto 8) = "10011011" else '0'; -- 10011011XXXXXXXX idc_sbiw <= '1' when instruction_code_reg(15 downto 8) = "10010111" else '0'; -- 10010111XXXXXXXX idc_sbrc <= '1' when instruction_code_reg(15 downto 9) = "1111110" else '0'; -- 1111110XXXXXXXXX idc_sbrs <= '1' when instruction_code_reg(15 downto 9) = "1111111" else '0'; -- 1111111XXXXXXXXX idc_sleep<= '1' when instruction_code_reg(15 downto 5)&instruction_code_reg(3 downto 0) = "100101011001000" else '0'; -- 10010101100X1000 -- ST,STD idc_st_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011100" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011101" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011110" else '0'; idc_st_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011010") else '0'; idc_std_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10011" else '0'; -- 10X0XX1XXXXX1XXX idc_st_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010010") else '0'; idc_std_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10010" else '0'; -- 10X0XX1XXXXX0XXX -- ###### idc_sts <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010010000" else '0'; -- 1001001XXXXX0000 idc_sub <= '1' when instruction_code_reg(15 downto 10) = "000110" else '0'; -- 000110XXXXXXXXXX idc_subi <= '1' when instruction_code_reg(15 downto 12) = "0101" else '0'; -- 0101XXXXXXXXXXXX idc_swap <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100010" else '0'; -- 1001010XXXXX0010 idc_wdr <= '1' when instruction_code_reg(15 downto 5)&instruction_code_reg(3 downto 0) = "100101011011000" else '0'; -- 10010101101X1000 -- ADDITIONAL SIGNALS idc_psinc <= '1' when (instruction_code_reg(1 downto 0) = "01" and (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0'; -- POST INCREMENT FOR LD/ST INSTRUCTIONS idc_prdec <= '1' when (instruction_code_reg(1 downto 0) = "10" and (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0'; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS -- ########################################################################################################## -- WRITE ENABLE SIGNALS FOR ramadr_reg ramadr_reg_en <= idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or idc_lds or -- LD/LDD/LDS(two cycle execution) idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or idc_sts or -- ST/STS/STS(two cycle execution) idc_push or idc_pop or idc_rcall or (rcall_st1 and not cpuwait) or idc_icall or (icall_st1 and not cpuwait) or -- RCALL/ICALL call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait) or -- CALL/IRQ idc_ret or (ret_st1 and not cpuwait ) or idc_reti or (reti_st1 and not cpuwait); -- RET/RETI -- ?? -- RAMADR MUX ramadr_reg_in <= sph_out&spl_out when (idc_rcall or (rcall_st1 and not cpuwait)or idc_icall or (icall_st1 and not cpuwait)or -- RCALL/ICALL call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait) or -- CALL/IRQ idc_push )='1' else -- PUSH (sph_out&spl_out)+1 when (idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait) or idc_pop)='1' else -- RET/RETI/POP inst when (idc_lds or idc_sts) ='1' else -- LDS/STS (two cycle execution) reg_h_out when (idc_ld_x or idc_ld_y or idc_ld_z or idc_st_x or idc_st_y or idc_st_z)='1' else -- LD/ST (reg_h_out + ("000000000"&dex_adr_disp)); -- LDD/STD -- ADDRESS REGISTER ramadr_reg:process(cp2,ireset) begin if ireset='0' then ramadr_int <= (others => '0'); elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then ramadr_int <= ramadr_reg_in; end if; end if; end if; end process; ramadr <= ramadr_int; -- GENERAL PURPOSE REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS gp_reg_adr:process(cp2,ireset) begin if ireset='0' then reg_file_adr_space <='0'; elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then if (ramadr_reg_in(15 downto 5)=const_ram_to_reg) then reg_file_adr_space <= '1'; -- ADRESS RANGE 0x0000-0x001F -> REGISTERS (R0-R31) else reg_file_adr_space <= '0'; end if; end if; end if; end if; end process; -- I/O REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS io_reg_adr:process(cp2,ireset) begin if ireset='0' then io_file_adr_space<='0'; elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then if (ramadr_reg_in(15 downto 5)=const_ram_to_io_a or ramadr_reg_in(15 downto 5)=const_ram_to_io_b or ramadr_reg_in(15 downto 12)=const_ram_to_io_c) then io_file_adr_space <= '1'; -- ADRESS RANGE 0x0020-0x005F -> I/O PORTS (0x00-0x3F) and ADRESS RANGE 0x1000-0x1FFF -> I/O PORTS (0x0FE0-0x1FDF) User Ports else io_file_adr_space <= '0'; end if; end if; end if; end if; end process; -- ########################################################################################################## -- REGRE/REGWE LOGIC (5 BIT ADDSRESS BUS (INTERNAL ONLY) 32 LOCATIONS (R0-R31)) -- WRITE ENABLE FOR Rd REGISTERS alu_reg_wr <= idc_adc or idc_add or idc_adiw or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or idc_sbiw or sbiw_st or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or idc_swap; reg_rd_wr <= idc_in or alu_reg_wr or idc_bld or -- ALU INSTRUCTIONS + IN/BLD INSRTRUCTION (pop_st or ld_st or lds_st)or -- POP/LD/LDD/LDS INSTRUCTIONS ((st_st or sts_st) and reg_file_adr_space)or -- ST/STD/STS INSTRUCTION lpm_st2 or idc_ldi or idc_mov; -- LPM/LDI/MOV INSTRUCTION reg_rd_adr <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else "00000" when lpm_st2='1' else adiw_sbiw_encoder_out when (idc_adiw or idc_sbiw)='1' else adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else dex_adrreg_d_latched when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else ramadr_int(4 downto 0) when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_d; reg_rr_adr <= ramadr_int(4 downto 0) when ((ld_st or lds_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_d_latched when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_r; -- MULTIPLEXER FOR REGISTER FILE Rd INPUT reg_rd_in <= dbusin when (idc_in or ((lds_st or ld_st)and not reg_file_adr_space) or pop_st)='1' else -- FROM INPUT DATA BUS reg_rr_out when ((lds_st or ld_st) and reg_file_adr_space)='1' else gp_reg_tmp when ((st_st or sts_st) and reg_file_adr_space)='1' else -- ST/STD/STS & ADDRESS FROM 0 TO 31 (REGISTER FILE) bld_op_out when (idc_bld='1')else -- FROM BIT PROCESSOR BLD COMMAND reg_rr_out when (idc_mov='1')else -- FOR MOV INSTRUCTION instruction_reg(15 downto 8) when (lpm_st2='1' and reg_z_out(0)='1') else -- LPM/ELPM instruction_reg(7 downto 0) when (lpm_st2='1' and reg_z_out(0)='0') else -- LPM/ELPM dex_dat8_immed when idc_ldi='1' else alu_data_out; -- FROM ALU DATA OUT -- IORE/IOWE LOGIC (6 BIT ADDRESS adr[5..0] FOR I/O PORTS(64 LOCATIONS)) iore_int <= idc_in or idc_sbi or idc_cbi or idc_sbic or idc_sbis or ((ld_st or lds_st) and io_file_adr_space); -- IN/SBI/CBI iowe_int <= '1' when ((idc_out or sbi_st or cbi_st) or ((st_st or sts_st) and io_file_adr_space))='1' else '0'; -- OUT/SBI/CBI + !! ST/STS/STD -- adr[5..0] BUS MULTIPLEXER adr_int <= "0000000000"&dex_adr6port when (idc_in or idc_out) = '1' else -- IN/OUT INSTRUCTIONS "0000000000"&'0'&dex_adr5port when (idc_cbi or idc_sbi or idc_sbic or idc_sbis) ='1' else -- CBI/SBI (READ PHASE) + SBIS/SBIC "0000000000"&'0'&cbi_sbi_io_adr_tmp when (cbi_st or sbi_st)='1' else -- CBI/SBI (WRITE PHASE) ramadr_int-x"20"; --(6)&ramadr_int(4 downto 0); -- LD/LDS/LDD/ST/STS/STD -- ramre LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS)) --ramre_int <= not(reg_file_adr_space or io_file_adr_space) and -- (ld_st or lds_st2 or pop_st or -- LD/LDD/LDS/POP/ -- ret_st1 or ret_st2 or reti_st1 or reti_st2); -- RET/RETI DataMemoryRead:process(cp2,ireset) begin if ireset='0' then -- Reset ramre_int <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then -- Clock enable case ramre_int is when '0' => if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and ramadr_reg_in(15 downto 12)/=const_ram_to_io_c and ramadr_reg_in(15 downto 5)/=const_ram_to_reg and (idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or -- LD/LDD instruction idc_lds or -- LDS instruction(two cycle execution) idc_pop or -- POP instruction idc_ret or -- RET instruction idc_reti)='1') -- RETI instruction then ramre_int <='1'; end if; when '1' => if ((ld_st or lds_st or pop_st or ret_st2 or reti_st2)and not cpuwait)='1' then ramre_int <='0'; end if; when others => null; end case; end if; end if; end process; -- ramwe LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS)) --ramwe_int <= not(reg_file_adr_space or io_file_adr_space) and -- (st_st or sts_st2 or push_st or rcall_st1 or rcall_st2 or -- ST/STD/STS/PUSH/RCALL -- icall_st1 or icall_st2 or -- ICALL -- call_st2 or call_st3 or -- CALL -- irq_st2 or irq_st3); -- INTERRUPT DataMemoryWrite:process(cp2,ireset) begin if ireset='0' then -- Reset ramwe_int <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then -- Clock enable case ramwe_int is when '0' => if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and ramadr_reg_in(15 downto 12)/=const_ram_to_io_c and ramadr_reg_in(15 downto 5)/=const_ram_to_reg and (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or -- ST/STD instruction idc_sts or -- STS instruction (two cycle execution) idc_push or -- PUSH instruction idc_rcall or -- RCALL instruction idc_icall or -- ICALL instruction call_st1 or -- CALL instruction irq_st1)='1') -- Interrupt then ramwe_int <='1'; end if; when '1' => if ((st_st or sts_st or push_st or rcall_st2 or icall_st2 or call_st3 or irq_st3)and not cpuwait)='1' then ramwe_int <='0'; end if; when others => null; end case; end if; end if; end process; -- DBUSOUT MULTIPLEXER dbusout_mux_logic: for i in dbusout_int'range generate dbusout_int(i)<= (reg_rd_out(i) and (idc_push or idc_sts or (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS (gp_reg_tmp(i) and (st_st or sts_st))or -- NEW (bitpr_io_out(i) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS (program_counter(i) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC (program_counter_high_fr(i) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC (pc_for_interrupt(i) and irq_st1) or (pc_for_interrupt(i+8) and irq_st2) or (reg_rd_out(i) and idc_out); -- OUT end generate; -- ALU CONNECTION -- ALU Rr INPUT MUX alu_data_r_in <= dex_dat8_immed when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi)='1' else "00"&dex_dat6_immed when (idc_adiw or idc_sbiw) ='1' else "00000000" when (adiw_st or sbiw_st) ='1' else reg_rr_out; -- gp_reg_tmp STORES TEMPREOARY THE VALUE OF SOURCE REGISTER DURING ST/STD/STS INSTRUCTION gp_registers_trig:process(cp2,ireset) begin if (ireset='0') then gp_reg_tmp <= (others=>'0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable -- if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or sts_st1)='1' then -- CLOCK ENABLE if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or idc_sts)='1' then -- CLOCK ENABLE gp_reg_tmp <= reg_rd_out; end if; end if; end if; end process; -- ********************************************************************************************************** -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- +++++++++++++++++++++++++++++++++++++++ PROGRAM COUNTER ++++++++++++++++++++++++++++++++++++++++++++++++++ -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ program_counter_high_store:process(cp2,ireset) begin if ireset='0' then -- RESET program_counter_high_fr <=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if (idc_rcall or idc_icall or call_st1 or irq_st1) ='1' then program_counter_high_fr <= program_counter(15 downto 8); -- STORE HIGH BYTE OF THE PROGRAMM COUNTER FOR RCALL/ICALL/CALL INSTRUCTIONS AND INTERRUPTS end if; end if; end if; end process; program_counter_for_lpm_elpm:process(cp2,ireset) begin if ireset='0' then -- RESET program_counter_tmp<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if (idc_lpm or idc_elpm) ='1' then program_counter_tmp <= program_counter; end if; end if; end if; end process; pa15_pm <= rampz_out(0) and idc_elpm; -- '0' WHEN LPM INSTRUCTIONS RAMPZ(0) WHEN ELPM INSTRUCTION -- OFFSET FOR BRBC/BRBS INSTRUCTIONS +63/-64 offset_brbx <= "0000000000"&dex_brxx_offset(5 downto 0) when (dex_brxx_offset(6)='0') else -- + "1111111111"&dex_brxx_offset(5 downto 0); -- - -- OFFSET FOR RJMP/RCALL INSTRUCTIONS +2047/-2048 offset_rxx <= "00000"&dex_adr12mem_s(10 downto 0) when (dex_adr12mem_s(11)='0') else -- + "11111"&dex_adr12mem_s(10 downto 0); -- - program_counter <= pc_high&pc_low; program_counter_in <= program_counter + offset_brbx when ((idc_brbc or idc_brbs) and bit_test_op_out) ='1'else -- BRBC/BRBS program_counter + offset_rxx when (idc_rjmp or idc_rcall)='1'else -- RJMP/RCALL reg_z_out when (idc_ijmp or idc_icall)='1'else -- IJMP/ICALL pa15_pm&reg_z_out(15 downto 1) when (idc_lpm or idc_elpm) ='1'else -- LPM/ELPM instruction_reg when (jmp_st1 or call_st1)='1'else -- JMP/CALL "0000000000"&irqackad_int&'0' when irq_st1 ='1' else -- INTERRUPT dbusin&"00000000" when (ret_st1 or reti_st1)='1' else -- RET/RETI -> PC HIGH BYTE "00000000"&dbusin when (ret_st2 or reti_st2)='1' else -- RET/RETI -> PC LOW BYTE program_counter_tmp when (lpm_st1)='1' -- AFTER LPM/ELPM INSTRUCTION else program_counter+1; -- THE MOST USUAL CASE pc_low_en <= not (idc_ld_x or idc_ld_y or idc_ld_z or idc_ldd_y or idc_ldd_z or idc_st_x or idc_st_y or idc_st_z or idc_std_y or idc_std_z or ((sts_st or lds_st) and cpuwait)or idc_adiw or idc_sbiw or idc_push or idc_pop or idc_cbi or idc_sbi or rcall_st1 or icall_st1 or call_st2 or irq_st2 or cpuwait or ret_st1 or reti_st1); pc_high_en <= not (idc_ld_x or idc_ld_y or idc_ld_z or idc_ldd_y or idc_ldd_z or idc_st_x or idc_st_y or idc_st_z or idc_std_y or idc_std_z or ((sts_st or lds_st) and cpuwait) or idc_adiw or idc_sbiw or idc_push or idc_pop or idc_cbi or idc_sbi or rcall_st1 or icall_st1 or call_st2 or irq_st2 or cpuwait or ret_st2 or reti_st2); program_counter_low:process(cp2,ireset) begin if ireset='0' then -- RESET pc_low<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if pc_low_en ='1' then pc_low <= program_counter_in(7 downto 0); end if; end if; end if; end process; program_counter_high:process(cp2,ireset) begin if ireset='0' then -- RESET pc_high<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if pc_high_en ='1' then pc_high <= program_counter_in(15 downto 8); end if; end if; end if; end process; pc <= program_counter; program_counter_for_interrupt:process(cp2,ireset) begin if ireset='0' then -- RESET pc_for_interrupt <=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if irq_start ='1' then pc_for_interrupt <= program_counter; end if; end if; end if; end process; -- END OF PROGRAM COUNTER -- STATE MACHINES skip_inst_start <= ((idc_sbrc or idc_sbrs or idc_sbic or idc_sbis) and bit_test_op_out)or (idc_cpse and alu_z_flag_out); skip_instruction_sm:process(cp2,ireset) begin if ireset='0' then -- RESET nskip_inst_st0 <= '0'; skip_inst_st1 <= '0'; skip_inst_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nskip_inst_st0 <= (not nskip_inst_st0 and skip_inst_start) or (nskip_inst_st0 and not((skip_inst_st1 and not two_word_inst) or skip_inst_st2)); skip_inst_st1 <= (not skip_inst_st1 and not nskip_inst_st0 and skip_inst_start); skip_inst_st2 <= not skip_inst_st2 and skip_inst_st1 and two_word_inst; end if; end if; end process; alu_state_machines:process(cp2,ireset) begin if ireset='0' then -- RESET adiw_st <= '0'; sbiw_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable adiw_st <= not adiw_st and idc_adiw; sbiw_st <= not sbiw_st and idc_sbiw; end if; end if; end process; lpm_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nlpm_st0 <= '0'; lpm_st1 <= '0'; lpm_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nlpm_st0 <= (not nlpm_st0 and (idc_lpm or idc_elpm)) or (nlpm_st0 and not lpm_st2); lpm_st1 <= (not lpm_st1 and not nlpm_st0 and (idc_lpm or idc_elpm)); -- ?? lpm_st2 <= not lpm_st2 and lpm_st1; end if; end if; end process; lds_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET lds_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable lds_st <= (not lds_st and idc_lds) or (lds_st and cpuwait); end if; end if; end process; sts_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET sts_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable sts_st <= (not sts_st and idc_sts) or (sts_st and cpuwait); end if; end if; end process; jmp_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET njmp_st0 <= '0'; jmp_st1 <= '0'; jmp_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable njmp_st0 <= (not njmp_st0 and idc_jmp) or (njmp_st0 and not jmp_st2); jmp_st1 <= not jmp_st1 and not njmp_st0 and idc_jmp; -- ?? jmp_st2 <= not jmp_st2 and jmp_st1; end if; end if; end process; rcall_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nrcall_st0 <= '0'; rcall_st1 <= '0'; rcall_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nrcall_st0 <= (not nrcall_st0 and idc_rcall) or (nrcall_st0 and not (rcall_st2 and not cpuwait)); rcall_st1 <= (not rcall_st1 and not nrcall_st0 and idc_rcall) or (rcall_st1 and cpuwait); rcall_st2 <= (not rcall_st2 and rcall_st1 and not cpuwait) or (rcall_st2 and cpuwait); end if; end if; end process; icall_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nicall_st0 <= '0'; icall_st1 <= '0'; icall_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nicall_st0 <= (not nicall_st0 and idc_icall) or (nicall_st0 and not (icall_st2 and not cpuwait)); icall_st1 <= (not icall_st1 and not nicall_st0 and idc_icall) or (icall_st1 and cpuwait); icall_st2 <= (not icall_st2 and icall_st1 and not cpuwait) or (icall_st2 and cpuwait); end if; end if; end process; call_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET ncall_st0 <= '0'; call_st1 <= '0'; call_st2 <= '0'; call_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable ncall_st0 <= (not ncall_st0 and idc_call) or (ncall_st0 and not( call_st3 and not cpuwait)); call_st1 <= not call_st1 and not ncall_st0 and idc_call; call_st2 <= (not call_st2 and call_st1) or (call_st2 and cpuwait); call_st3 <= (not call_st3 and call_st2 and not cpuwait) or (call_st3 and cpuwait); end if; end if; end process; ret_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nret_st0 <= '0'; ret_st1 <= '0'; ret_st2 <= '0'; ret_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nret_st0 <= (not nret_st0 and idc_ret) or (nret_st0 and not ret_st3); ret_st1 <= (not ret_st1 and not nret_st0 and idc_ret) or (ret_st1 and cpuwait); ret_st2 <= (not ret_st2 and ret_st1 and not cpuwait) or (ret_st2 and cpuwait) ; ret_st3 <= not ret_st3 and ret_st2 and not cpuwait; end if; end if; end process; reti_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nreti_st0 <= '0'; reti_st1 <= '0'; reti_st2 <= '0'; reti_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nreti_st0 <= (not nreti_st0 and idc_reti) or (nreti_st0 and not reti_st3); reti_st1 <= (not reti_st1 and not nreti_st0 and idc_reti) or (reti_st1 and cpuwait); reti_st2 <= (not reti_st2 and reti_st1 and not cpuwait) or (reti_st2 and cpuwait) ; reti_st3 <= not reti_st3 and reti_st2 and not cpuwait; end if; end if; end process; -- INTERRUPT LOGIC AND STATE MACHINE irq_int <= '0' when irqlines="00000000000000000000000" else '1'; irq_vector_adr(15 downto 6)<=(others => '0'); irq_vector_adr(0) <= '0'; -- PRIORITY ENCODER irq_vector_adr(5 downto 1) <= "00001" when irqlines(0)='1' else -- 0x0002 "00010" when irqlines(1)='1' else -- 0x0004 "00011" when irqlines(2)='1' else -- 0x0006 "00100" when irqlines(3)='1' else -- 0x0008 "00101" when irqlines(4)='1' else -- 0x000A "00110" when irqlines(5)='1' else -- 0x000C "00111" when irqlines(6)='1' else -- 0x000E "01000" when irqlines(7)='1' else -- 0x0010 "01001" when irqlines(8)='1' else -- 0x0012 "01010" when irqlines(9)='1' else -- 0x0014 "01011" when irqlines(10)='1' else -- 0x0016 "01100" when irqlines(11)='1' else -- 0x0018 "01101" when irqlines(12)='1' else -- 0x001A "01110" when irqlines(13)='1' else -- 0x001C "01111" when irqlines(14)='1' else -- 0x001E "10000" when irqlines(15)='1' else -- 0x0020 "10001" when irqlines(16)='1' else -- 0x0022 "10010" when irqlines(17)='1' else -- 0x0024 "10011" when irqlines(18)='1' else -- 0x0026 "10100" when irqlines(19)='1' else -- 0x0028 "10101" when irqlines(20)='1' else -- 0x002A "10110" when irqlines(21)='1' else -- 0x002C "10111" when irqlines(22)='1' else -- 0x002E "00000"; -- MULTI CYCLE INSTRUCTION FLAG FOR IRQ cpu_busy <= idc_adiw or idc_sbiw or idc_cbi or idc_sbi or idc_rjmp or idc_ijmp or idc_jmp or jmp_st1 or -- idc_brbs or idc_brbc or -- Old variant ((idc_brbc or idc_brbs) and bit_test_op_out) or idc_lpm or lpm_st1 or skip_inst_start or (skip_inst_st1 and two_word_inst) or idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or (ld_st and cpuwait) or idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or (st_st and cpuwait) or idc_lds or (lds_st and cpuwait) or idc_sts or (sts_st and cpuwait) or idc_rcall or rcall_st1 or (rcall_st2 and cpuwait) or -- RCALL idc_icall or icall_st1 or (icall_st2 and cpuwait) or -- ICALL idc_call or call_st1 or call_st2 or (call_st3 and cpuwait) or -- CALL idc_push or (push_st and cpuwait) or -- PUSH (added 14.07.05) idc_pop or (pop_st and cpuwait) or -- POP (added 14.07.05) (idc_bclr and sreg_bop_wr_en(7)) or -- ??? CLI (iowe_int and sreg_adr_eq and not dbusout_int(7))or -- ??? Writing '0' to I flag (OUT/STD/ST/STD) nirq_st0 or -- idc_ret or nret_st0 or -- Old variant idc_ret or ret_st1 or ret_st2 or -- idc_reti or nreti_st0; -- At least one instruction must be executed after RETI and before the new interrupt. idc_reti or reti_st1 or reti_st2; sreg_adr_eq <= '1' when adr_int=SREG_Address else '0'; --irq_start <= irq_int and not cpu_busy and globint; irq_start <= irq_int and not cpu_busy and globint; irq_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nirq_st0 <= '0'; irq_st1 <= '0'; irq_st2 <= '0'; irq_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nirq_st0 <= (not nirq_st0 and irq_start) or (nirq_st0 and not (irq_st3 and not cpuwait)); irq_st1 <= (not irq_st1 and not nirq_st0 and irq_start); irq_st2 <= (not irq_st2 and irq_st1) or (irq_st2 and cpuwait); irq_st3 <= (not irq_st3 and irq_st2 and not cpuwait) or (irq_st3 and cpuwait); end if; end if; end process; irqack_reg:process(cp2,ireset) begin if ireset='0' then -- RESET irqack_int<='0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable irqack_int<= not irqack_int and irq_start; end if; end if; end process; irqack <= irqack_int; irqackad_reg:process(cp2,ireset) begin if ireset='0' then -- RESET irqackad_int<=(others=>'0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable irqackad_int<=irq_vector_adr(5 downto 1); end if; end if; end process; irqackad <= irqackad_int; -- ******************************************************************************************* rjmp_push_pop_ijmp_state_brxx_machine:process(cp2,ireset) begin if ireset='0' then -- RESET rjmp_st <= '0'; ijmp_st <= '0'; push_st <= '0'; pop_st <= '0'; brxx_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable rjmp_st <= idc_rjmp; -- ?? ijmp_st <= idc_ijmp; push_st <= (not push_st and idc_push) or (push_st and cpuwait); pop_st <= (not pop_st and idc_pop) or (pop_st and cpuwait); brxx_st <= not brxx_st and (idc_brbc or idc_brbs) and bit_test_op_out; end if; end if; end process; -- LD/LDD/ST/STD ld_st_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET ld_st <= '0'; st_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable ld_st <= (not ld_st and (idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z)) or (ld_st and cpuwait); st_st <= (not st_st and (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)) or (st_st and cpuwait); end if; end if; end process; -- SBI/CBI sbi_cbi_machine:process(cp2,ireset) begin if ireset='0' then -- RESET sbi_st <= '0'; cbi_st <= '0'; cbi_sbi_io_adr_tmp <= (others => '0'); cbi_sbi_bit_num_tmp <= (others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable sbi_st <= not sbi_st and idc_sbi; cbi_st <= not cbi_st and idc_cbi; cbi_sbi_io_adr_tmp <= dex_adr5port; cbi_sbi_bit_num_tmp <= dex_bitop_bitnum; end if; end if; end process; -- ######################################################################################## -- SREG FLAGS WRITE ENABLE LOGIC bclr_bset_op_en_logic:for i in sreg_bop_wr_en'range generate sreg_bop_wr_en(i) <= '1' when (dex_bitnum_sreg=i and (idc_bclr or idc_bset)='1') else '0'; end generate; sreg_c_wr_en <= idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_com or idc_neg or idc_cp or idc_cpc or idc_cpi or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(0); sreg_z_wr_en <= idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(1); sreg_n_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or sbiw_st or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(2); sreg_v_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or -- idc_adiw idc_sbc or idc_sbci or sbiw_st or idc_neg or idc_com or -- idc_sbiw idc_inc or idc_dec or idc_cp or idc_cpc or idc_cpi or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(3) or idc_and or idc_andi or idc_or or idc_ori or idc_eor; -- V-flag bug fixing sreg_s_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or sbiw_st or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(4); sreg_h_wr_en <= idc_add or idc_adc or idc_sub or idc_subi or idc_cp or idc_cpc or idc_cpi or idc_sbc or idc_sbci or idc_neg or sreg_bop_wr_en(5); sreg_t_wr_en <= idc_bst or sreg_bop_wr_en(6); sreg_i_wr_en <= irq_st1 or reti_st3 or sreg_bop_wr_en(7); -- WAS "irq_start" sreg_fl_in <= bit_pr_sreg_out when (idc_bst or idc_bclr or idc_bset)='1' else -- TO THE SREG reti_st3&'0'&alu_h_flag_out&alu_s_flag_out&alu_v_flag_out&alu_n_flag_out&alu_z_flag_out&alu_c_flag_out; -- ################################################################################################################# -- ********************************************************************************************* -- ************** INSTRUCTION DECODER OUTPUTS FOR THE OTHER BLOCKS **************************** -- ********************************************************************************************* -- FOR ALU idc_add_out <= idc_add; idc_adc_out <= idc_adc; idc_adiw_out <= idc_adiw; idc_sub_out <= idc_sub; idc_subi_out <= idc_subi; idc_sbc_out <= idc_sbc; idc_sbci_out <= idc_sbci; idc_sbiw_out <= idc_sbiw; adiw_st_out <= adiw_st; sbiw_st_out <= sbiw_st; idc_and_out <= idc_and; idc_andi_out <= idc_andi; idc_or_out <= idc_or; idc_ori_out <= idc_ori; idc_eor_out <= idc_eor; idc_com_out <= idc_com; idc_neg_out <= idc_neg; idc_inc_out <= idc_inc; idc_dec_out <= idc_dec; idc_cp_out <= idc_cp; idc_cpc_out <= idc_cpc; idc_cpi_out <= idc_cpi; idc_cpse_out <= idc_cpse; idc_lsr_out <= idc_lsr; idc_ror_out <= idc_ror; idc_asr_out <= idc_asr; idc_swap_out <= idc_swap; -- FOR THE BIT PROCESSOR sbi_st_out <= sbi_st; cbi_st_out <= cbi_st; idc_bst_out <= idc_bst; idc_bset_out <= idc_bset; idc_bclr_out <= idc_bclr; idc_sbic_out <= idc_sbic; idc_sbis_out <= idc_sbis; idc_sbrs_out <= idc_sbrs; idc_sbrc_out <= idc_sbrc; idc_brbs_out <= idc_brbs; idc_brbc_out <= idc_brbc; idc_reti_out <= idc_reti; -- POST INCREMENT/PRE DECREMENT FOR THE X,Y,Z REGISTERS post_inc <= idc_psinc; pre_dec <= idc_prdec; reg_h_wr <= (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z) and (idc_psinc or idc_prdec); reg_h_adr(0)<= idc_st_x or idc_ld_x; reg_h_adr(1)<= idc_st_y or idc_std_y or idc_ld_y or idc_ldd_y; reg_h_adr(2)<= idc_st_z or idc_std_z or idc_ld_z or idc_ldd_z; -- STACK POINTER CONTROL sp_ndown_up <= idc_pop or idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait); -- ????????? sp_en <= idc_push or idc_pop or idc_rcall or (rcall_st1 and not cpuwait) or idc_icall or (icall_st1 and not cpuwait) or idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait) or call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait); --???????? branch <= dex_condition; bit_num_r_io <= cbi_sbi_bit_num_tmp when (cbi_st or sbi_st)='1' else dex_bitop_bitnum; adr <= adr_int; ramre <= ramre_int; ramwe <= ramwe_int; iore <= iore_int; iowe <= iowe_int; dbusout <= dbusout_int; -- Sleep Control sleepi <= idc_sleep; irqok <= irq_int; -- Watchdog wdri <= idc_wdr; -- ************************** JTAG OCD support ************************************ -- Change of flow change_flow <= '0'; valid_instr <= '0'; end RTL;
--************************************************************************************************ -- PM_FETCH_DEC(internal module) for AVR core -- Version 2.6! (Special version for the JTAG OCD) -- Designed by Ruslan Lepetenok 14.11.2001 -- Modified 31.05.06 -- Modification: -- Registered ramre/ramwe outputs -- cpu_busy logic modified(affects RCALL/ICALL/CALL instruction interract with interrupt) -- SLEEP and CLRWDT instructions support was added -- V-flag bug fixed (AND/ANDI/OR/ORI/EOR) -- V-flag bug fixed (ADIW/SBIW) -- Unused outputs(sreg_bit_num[2..0],idc_sbi_out,idc_cbi_out,idc_bld_out) were removed. -- Output alu_data_d_in[7..0] was removed. -- Gloabal clock enable(cp2en) was added -- cpu_busy(push/pop) + irq bug was fixed 14.07.05 -- BRXX+IRQ interaction was modified -> cpu_busy -- LDS/STS now requires only two cycles for execution (13.01.06 -> last modificatioon) --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.AVRuCPackage.all; entity pm_fetch_dec is port( -- Clock and reset cp2 : in std_logic; cp2en : in std_logic; ireset : in std_logic; -- JTAG OCD support valid_instr : out std_logic; insert_nop : in std_logic; block_irq : in std_logic; change_flow : out std_logic; -- Program memory pc : out std_logic_vector (15 downto 0); inst : in std_logic_vector (15 downto 0); -- I/O control adr : out std_logic_vector (15 downto 0); iore : out std_logic; iowe : out std_logic; -- Data memory control ramadr : out std_logic_vector (15 downto 0); ramre : out std_logic; ramwe : out std_logic; cpuwait : in std_logic; -- Data paths dbusin : in std_logic_vector (7 downto 0); dbusout : out std_logic_vector (7 downto 0); -- Interrupt irqlines : in std_logic_vector (22 downto 0); irqack : out std_logic; irqackad : out std_logic_vector(4 downto 0); --Sleep sleepi : out std_logic; irqok : out std_logic; --Watchdog wdri : out std_logic; -- ALU interface(Data inputs) alu_data_r_in : out std_logic_vector(7 downto 0); -- ALU interface(Instruction inputs) idc_add_out : out std_logic; idc_adc_out : out std_logic; idc_adiw_out : out std_logic; idc_sub_out : out std_logic; idc_subi_out : out std_logic; idc_sbc_out : out std_logic; idc_sbci_out : out std_logic; idc_sbiw_out : out std_logic; adiw_st_out : out std_logic; sbiw_st_out : out std_logic; idc_and_out : out std_logic; idc_andi_out : out std_logic; idc_or_out : out std_logic; idc_ori_out : out std_logic; idc_eor_out : out std_logic; idc_com_out : out std_logic; idc_neg_out : out std_logic; idc_inc_out : out std_logic; idc_dec_out : out std_logic; idc_cp_out : out std_logic; idc_cpc_out : out std_logic; idc_cpi_out : out std_logic; idc_cpse_out : out std_logic; idc_lsr_out : out std_logic; idc_ror_out : out std_logic; idc_asr_out : out std_logic; idc_swap_out : out std_logic; -- ALU interface(Data output) alu_data_out : in std_logic_vector(7 downto 0); -- ALU interface(Flag outputs) alu_c_flag_out : in std_logic; alu_z_flag_out : in std_logic; alu_n_flag_out : in std_logic; alu_v_flag_out : in std_logic; alu_s_flag_out : in std_logic; alu_h_flag_out : in std_logic; -- General purpose register file interface reg_rd_in : out std_logic_vector (7 downto 0); reg_rd_out : in std_logic_vector (7 downto 0); reg_rd_adr : out std_logic_vector (4 downto 0); reg_rr_out : in std_logic_vector (7 downto 0); reg_rr_adr : out std_logic_vector (4 downto 0); reg_rd_wr : out std_logic; post_inc : out std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS pre_dec : out std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS reg_h_wr : out std_logic; reg_h_out : in std_logic_vector (15 downto 0); reg_h_adr : out std_logic_vector (2 downto 0); -- x,y,z reg_z_out : in std_logic_vector (15 downto 0); -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS -- I/O register file interface sreg_fl_in : out std_logic_vector(7 downto 0); globint : in std_logic; -- SREG I flag sreg_fl_wr_en : out std_logic_vector(7 downto 0); --FLAGS WRITE ENABLE SIGNALS spl_out : in std_logic_vector(7 downto 0); sph_out : in std_logic_vector(7 downto 0); sp_ndown_up : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-) sp_en : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS rampz_out : in std_logic_vector(7 downto 0); -- Bit processor interface bit_num_r_io : out std_logic_vector (2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS bitpr_io_out : in std_logic_vector(7 downto 0); -- SBI/CBI OUT branch : out std_logic_vector (2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION bit_pr_sreg_out : in std_logic_vector(7 downto 0); -- BCLR/BSET/BST(T-FLAG ONLY) bld_op_out : in std_logic_vector(7 downto 0); -- BLD OUT (T FLAG) bit_test_op_out : in std_logic; -- OUTPUT OF SBIC/SBIS/SBRS/SBRC sbi_st_out : out std_logic; cbi_st_out : out std_logic; idc_bst_out : out std_logic; idc_bset_out : out std_logic; idc_bclr_out : out std_logic; idc_sbic_out : out std_logic; idc_sbis_out : out std_logic; idc_sbrs_out : out std_logic; idc_sbrc_out : out std_logic; idc_brbs_out : out std_logic; idc_brbc_out : out std_logic; idc_reti_out : out std_logic); end pm_fetch_dec; architecture RTL of pm_fetch_dec is -- COPIES OF OUTPUTS signal ramadr_reg_in : std_logic_vector(15 downto 0); -- INPUT OF THE ADDRESS REGISTER signal ramadr_reg_en : std_logic; -- ADRESS REGISTER CLOCK ENABLE SIGNAL signal irqack_int : std_logic; signal irqackad_int : std_logic_vector(irqackad'range); -- #################################################### -- INTERNAL SIGNALS -- #################################################### -- NEW SIGNALS signal two_word_inst : std_logic; -- CALL/JMP/STS/LDS INSTRUCTION INDICATOR signal ram_adr_int : std_logic_vector (15 downto 0); constant const_ram_to_reg : std_logic_vector := "00000000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19 constant const_ram_to_io_a : std_logic_vector := "00000000001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F constant const_ram_to_io_b : std_logic_vector := "00000000010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F --constant const_ram_to_io_c : std_logic_vector := "0001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x1000 0x1FFF constant const_ram_to_io_c : std_logic_vector := "0010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x2000 0x2FFF -> change by Zvonimir Bandic constant const_ram_to_io_d : std_logic_vector := "00100000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x1000 0x3FFF -- LD/LDD/ST/STD SIGNALS signal adiw_sbiw_encoder_out : std_logic_vector (4 downto 0); signal adiw_sbiw_encoder_mux_out : std_logic_vector (4 downto 0); -- PROGRAM COUNTER SIGNALS signal program_counter_tmp : std_logic_vector (15 downto 0); -- TO STORE PC DURING LPM/ELPM INSTRUCTIONS signal program_counter : std_logic_vector (15 downto 0); signal program_counter_in : std_logic_vector (15 downto 0); signal program_counter_high_fr : std_logic_vector (7 downto 0); -- TO STORE PC FOR CALL,IRQ,RCALL,ICALL signal pc_low : std_logic_vector (7 downto 0); signal pc_high : std_logic_vector (7 downto 0); signal pc_low_en : std_logic; signal pc_high_en : std_logic; signal offset_brbx : std_logic_vector (15 downto 0); -- OFFSET FOR BRCS/BRCC INSTRUCTION !!CHECKED signal offset_rxx : std_logic_vector (15 downto 0); -- OFFSET FOR RJMP/RCALL INSTRUCTION !!CHECKED signal pa15_pm : std_logic; -- ADDRESS LINE 15 FOR LPM/ELPM INSTRUCTIONS ('0' FOR LPM,RAMPZ(0) FOR ELPM) signal alu_reg_wr : std_logic; -- ALU INSTRUCTIONS PRODUCING WRITE TO THE GENERAL PURPOSE REGISTER FILE -- DATA MEMORY,GENERAL PURPOSE REGISTERS AND I/O REGISTERS LOGIC --! IMPORTANT NOTICE : OPERATIONS WHICH USE STACK POINTER (SPH:SPL) CAN NOT ACCCSESS GENERAL -- PURPOSE REGISTER FILE AND INPUT/OUTPUT REGISTER FILE ! -- THESE OPERATIONS ARE : RCALL/ICALL/CALL/RET/RETI/PUSH/POP INSTRUCTIONS AND INTERRUPT signal reg_file_adr_space : std_logic; -- ACCSESS TO THE REGISTER FILE signal io_file_adr_space : std_logic; -- ACCSESS TO THE I/O FILE -- STATE MACHINES SIGNALS signal irq_start : std_logic; signal nirq_st0 : std_logic; signal irq_st1 : std_logic; signal irq_st2 : std_logic; signal irq_st3 : std_logic; signal ncall_st0 : std_logic; signal call_st1 : std_logic; signal call_st2 : std_logic; signal call_st3 : std_logic; signal nrcall_st0 : std_logic; signal rcall_st1 : std_logic; signal rcall_st2 : std_logic; signal nicall_st0 : std_logic; signal icall_st1 : std_logic; signal icall_st2 : std_logic; signal njmp_st0 : std_logic; signal jmp_st1 : std_logic; signal jmp_st2 : std_logic; signal ijmp_st : std_logic; signal rjmp_st : std_logic; signal nret_st0 : std_logic; signal ret_st1 : std_logic; signal ret_st2 : std_logic; signal ret_st3 : std_logic; signal nreti_st0 : std_logic; signal reti_st1 : std_logic; signal reti_st2 : std_logic; signal reti_st3 : std_logic; signal brxx_st : std_logic; -- BRANCHES signal adiw_st : std_logic; signal sbiw_st : std_logic; signal nskip_inst_st0 : std_logic; signal skip_inst_st1 : std_logic; signal skip_inst_st2 : std_logic; -- ALL SKIP INSTRUCTIONS SBRS/SBRC/SBIS/SBIC/CPSE signal skip_inst_start : std_logic; signal nlpm_st0 : std_logic; signal lpm_st1 : std_logic; signal lpm_st2 : std_logic; signal nelpm_st0 : std_logic; signal elpm_st1 : std_logic; signal elpm_st2 : std_logic; --signal nsts_st0 : std_logic; --signal sts_st1 : std_logic; --signal sts_st2 : std_logic; signal sts_st : std_logic; --signal nlds_st0 : std_logic; --signal lds_st1 : std_logic; --signal lds_st2 : std_logic; signal lds_st : std_logic; signal st_st : std_logic; signal ld_st : std_logic; signal sbi_st : std_logic; signal cbi_st : std_logic; signal push_st : std_logic; signal pop_st : std_logic; -- INTERNAL STATE MACHINES signal nop_insert_st : std_logic; signal cpu_busy : std_logic; -- INTERNAL COPIES OF OUTPUTS signal pc_int : std_logic_vector (15 downto 0); signal adr_int : std_logic_vector (15 downto 0); signal iore_int : std_logic; signal iowe_int : std_logic; signal ramadr_int : std_logic_vector (15 downto 0); signal ramre_int : std_logic; signal ramwe_int : std_logic; signal dbusout_int : std_logic_vector (7 downto 0); -- COMMAND REGISTER signal instruction_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER signal instruction_code_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER WITH NOP INSERTION signal instruction_reg_ena : std_logic; -- CLOCK ENABLE -- IRQ INTERNAL LOGIC signal irq_int : std_logic; signal irq_vector_adr : std_logic_vector(15 downto 0); -- INTERRUPT RELATING REGISTERS signal pc_for_interrupt : std_logic_vector(15 downto 0); -- DATA EXTRACTOR SIGNALS signal dex_dat8_immed : std_logic_vector (7 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ANDI,ORI,SUBI,SBCI,CPI,LDI signal dex_dat6_immed : std_logic_vector (5 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ADIW,SBIW signal dex_adr12mem_s : std_logic_vector (11 downto 0); -- RELATIVE ADDRESS (SIGNED) -> RCALL,RJMP signal dex_adr6port : std_logic_vector (5 downto 0); -- I/O PORT ADDRESS -> IN,OUT signal dex_adr5port : std_logic_vector (4 downto 0); -- I/O PORT ADDRESS -> CBI,SBI,SBIC,SBIS signal dex_adr_disp : std_logic_vector (5 downto 0); -- DISPLACEMENT FO ADDDRESS -> STD,LDD signal dex_condition : std_logic_vector (2 downto 0); -- CONDITION -> BRBC,BRBS signal dex_bitnum_sreg : std_logic_vector (2 downto 0); -- NUMBER OF BIT IN SREG -> BCLR,BSET signal dex_adrreg_r : std_logic_vector (4 downto 0); -- SOURCE REGISTER ADDRESS -> ....... signal dex_adrreg_d : std_logic_vector (4 downto 0); -- DESTINATION REGISTER ADDRESS -> ...... signal dex_bitop_bitnum : std_logic_vector(2 downto 0); -- NUMBER OF BIT FOR BIT ORIENTEDE OPERATION -> BST/BLD+SBI/CBI+SBIC/SBIS+SBRC/SBRS !! CHECKED signal dex_brxx_offset : std_logic_vector (6 downto 0); -- RELATIVE ADDRESS (SIGNED) -> BRBC,BRBS !! CHECKED signal dex_adiw_sbiw_reg_adr : std_logic_vector (1 downto 0); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS signal dex_adrreg_d_latched : std_logic_vector (4 downto 0); -- STORE ADDRESS OF DESTINATION REGISTER FOR LDS/STS/POP INSTRUCTIONS signal gp_reg_tmp : std_logic_vector (7 downto 0); -- STORE DATA FROM THE REGISTERS FOR STS,ST INSTRUCTIONS signal cbi_sbi_io_adr_tmp : std_logic_vector (4 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION signal cbi_sbi_bit_num_tmp : std_logic_vector (2 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION -- INSTRUCTIONS DECODER SIGNALS signal idc_adc : std_logic; -- INSTRUCTION ADC signal idc_add : std_logic; -- INSTRUCTION ADD signal idc_adiw : std_logic; -- INSTRUCTION ADIW signal idc_and : std_logic; -- INSTRUCTION AND signal idc_andi : std_logic; -- INSTRUCTION ANDI signal idc_asr : std_logic; -- INSTRUCTION ASR signal idc_bclr : std_logic; -- INSTRUCTION BCLR signal idc_bld : std_logic; -- INSTRUCTION BLD signal idc_brbc : std_logic; -- INSTRUCTION BRBC signal idc_brbs : std_logic; -- INSTRUCTION BRBS signal idc_bset : std_logic; -- INSTRUCTION BSET signal idc_bst : std_logic; -- INSTRUCTION BST signal idc_call : std_logic; -- INSTRUCTION CALL signal idc_cbi : std_logic; -- INSTRUCTION CBI signal idc_com : std_logic; -- INSTRUCTION COM signal idc_cp : std_logic; -- INSTRUCTION CP signal idc_cpc : std_logic; -- INSTRUCTION CPC signal idc_cpi : std_logic; -- INSTRUCTION CPI signal idc_cpse : std_logic; -- INSTRUCTION CPSE signal idc_dec : std_logic; -- INSTRUCTION DEC signal idc_elpm : std_logic; -- INSTRUCTION ELPM signal idc_eor : std_logic; -- INSTRUCTION EOR signal idc_icall : std_logic; -- INSTRUCTION ICALL signal idc_ijmp : std_logic; -- INSTRUCTION IJMP signal idc_in : std_logic; -- INSTRUCTION IN signal idc_inc : std_logic; -- INSTRUCTION INC signal idc_jmp : std_logic; -- INSTRUCTION JMP signal idc_ld_x : std_logic; -- INSTRUCTION LD Rx,X ; LD Rx,X+ ;LD Rx,-X signal idc_ld_y : std_logic; -- INSTRUCTION LD Rx,Y ; LD Rx,Y+ ;LD Rx,-Y signal idc_ldd_y : std_logic; -- INSTRUCTION LDD Rx,Y+q signal idc_ld_z : std_logic; -- INSTRUCTION LD Rx,Z ; LD Rx,Z+ ;LD Rx,-Z signal idc_ldd_z : std_logic; -- INSTRUCTION LDD Rx,Z+q signal idc_ldi : std_logic; -- INSTRUCTION LDI signal idc_lds : std_logic; -- INSTRUCTION LDS signal idc_lpm : std_logic; -- INSTRUCTION LPM signal idc_lsr : std_logic; -- INSTRUCTION LSR signal idc_mov : std_logic; -- INSTRUCTION MOV signal idc_mul : std_logic; -- INSTRUCTION MUL signal idc_neg : std_logic; -- INSTRUCTION NEG signal idc_nop : std_logic; -- INSTRUCTION NOP signal idc_or : std_logic; -- INSTRUCTION OR signal idc_ori : std_logic; -- INSTRUCTION ORI signal idc_out : std_logic; -- INSTRUCTION OUT signal idc_pop : std_logic; -- INSTRUCTION POP signal idc_push : std_logic; -- INSTRUCTION PUSH signal idc_rcall : std_logic; -- INSTRUCTION RCALL signal idc_ret : std_logic; -- INSTRUCTION RET signal idc_reti : std_logic; -- INSTRUCTION RETI signal idc_rjmp : std_logic; -- INSTRUCTION RJMP signal idc_ror : std_logic; -- INSTRUCTION ROR signal idc_sbc : std_logic; -- INSTRUCTION SBC signal idc_sbci : std_logic; -- INSTRUCTION SBCI signal idc_sbi : std_logic; -- INSTRUCTION SBI signal idc_sbic : std_logic; -- INSTRUCTION SBIC signal idc_sbis : std_logic; -- INSTRUCTION SBIS signal idc_sbiw : std_logic; -- INSTRUCTION SBIW signal idc_sbrc : std_logic; -- INSTRUCTION SBRC signal idc_sbrs : std_logic; -- INSTRUCTION SBRS signal idc_sleep : std_logic; -- INSTRUCTION SLEEP signal idc_st_x : std_logic; -- INSTRUCTION LD X,Rx ; LD X+,Rx ;LD -X,Rx signal idc_st_y : std_logic; -- INSTRUCTION LD Y,Rx ; LD Y+,Rx ;LD -Y,Rx signal idc_std_y : std_logic; -- INSTRUCTION LDD Y+q,Rx signal idc_st_z : std_logic; -- INSTRUCTION LD Z,Rx ; LD Z+,Rx ;LD -Z,Rx signal idc_std_z : std_logic; -- INSTRUCTION LDD Z+q,Rx signal idc_sts : std_logic; -- INSTRUCTION STS signal idc_sub : std_logic; -- INSTRUCTION SUB signal idc_subi : std_logic; -- INSTRUCTION SUBI signal idc_swap : std_logic; -- INSTRUCTION SWAP signal idc_wdr : std_logic; -- INSTRUCTION WDR -- ADDITIONAL SIGNALS signal idc_psinc : std_logic; -- POST INCREMENT FLAG FOR LD,ST INSTRUCTIONS signal idc_prdec : std_logic; -- PRE DECREMENT FLAG FOR LD,ST INSTRUCTIONS -- ################################################## -- SREG FLAGS WRITE ENABLE SIGNALS alias sreg_c_wr_en : std_logic is sreg_fl_wr_en(0); alias sreg_z_wr_en : std_logic is sreg_fl_wr_en(1); alias sreg_n_wr_en : std_logic is sreg_fl_wr_en(2); alias sreg_v_wr_en : std_logic is sreg_fl_wr_en(3); alias sreg_s_wr_en : std_logic is sreg_fl_wr_en(4); alias sreg_h_wr_en : std_logic is sreg_fl_wr_en(5); alias sreg_t_wr_en : std_logic is sreg_fl_wr_en(6); alias sreg_i_wr_en : std_logic is sreg_fl_wr_en(7); signal sreg_bop_wr_en : std_logic_vector (7 downto 0); signal sreg_adr_eq : std_logic; -- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& begin -- INSTRUCTION FETCH instruction_reg_ena <= '1'; -- FOR TEST instruction_fetch:process(cp2,ireset) begin if ireset='0' then -- RESET instruction_reg <= (others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if instruction_reg_ena='1' then instruction_reg <= inst; end if; end if; end if; end process; -- TWO WORDS INSTRUCTION DETECTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER) two_word_inst <= '1' when ((instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010111") or -- CALL (instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010110")) or -- JMP (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010000000") or -- LDS (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010010000") -- STS else '0'; -- TO DETECT CALL/JMP/LDS/STS INSTRUCTIONS FOR SBRS/SBRC/SBIS/SBIC/CPSE -- DATA EXTRACTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER) dex_dat8_immed <= instruction_reg(11 downto 8) & instruction_reg(3 downto 0); dex_dat6_immed <= instruction_reg(7 downto 6) & instruction_reg(3 downto 0); dex_adr12mem_s <= instruction_reg(11 downto 0); dex_adr6port <= instruction_reg(10 downto 9) & instruction_reg(3 downto 0); dex_adr5port <= instruction_reg(7 downto 3); dex_adr_disp <= instruction_reg(13) & instruction_reg(11 downto 10) & instruction_reg(2 downto 0); dex_condition <= instruction_reg(2 downto 0); dex_bitop_bitnum <= instruction_reg(2 downto 0); -- NUMBER(POSITION) OF TESTING BIT IN SBRC/SBRS/SBIC/SBIS INSTRUCTION dex_bitnum_sreg <= instruction_reg(6 downto 4); dex_adrreg_r <= instruction_reg(9) & instruction_reg(3 downto 0); dex_adrreg_d <= instruction_reg(8 downto 4); dex_brxx_offset <= instruction_reg(9 downto 3); -- OFFSET FOR BRBC/BRBS dex_adiw_sbiw_reg_adr <= instruction_reg(5 downto 4); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS --dex_adrindreg <= instruction_reg(3 downto 2); -- LATCH Rd ADDDRESS FOR LDS/STS/POP INSTRUCTIONS latcht_rd_adr:process(cp2,ireset) begin if ireset ='0' then dex_adrreg_d_latched <= (others => '0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if ((idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z) or idc_sts or (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)or idc_lds or idc_pop)='1' then dex_adrreg_d_latched <= dex_adrreg_d; end if; end if; end if; end process; -- +++++++++++++++++++++++++++++++++++++++++++++++++ -- R24:R25/R26:R27/R28:R29/R30:R31 ADIW/SBIW ADDRESS CONTROL LOGIC adiw_sbiw_encoder_out <= "11"&dex_adiw_sbiw_reg_adr&'0'; adiw_sbiw_high_reg_adr:process(cp2,ireset) begin if ireset ='0' then adiw_sbiw_encoder_mux_out <= (others=>'0'); elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_out +1; end if; end if; end process; -- ########################## -- NOP INSERTION --instruction_code_reg <= instruction_reg when nop_insert_st='0' else (others => '0'); instruction_code_reg <= (others => '0') when (nop_insert_st='1') else -- NOP instruction_reg; -- Instruction nop_insert_st <= adiw_st or sbiw_st or cbi_st or sbi_st or rjmp_st or ijmp_st or pop_st or push_st or brxx_st or ld_st or st_st or ncall_st0 or nirq_st0 or nret_st0 or nreti_st0 or nlpm_st0 or njmp_st0 or nrcall_st0 or nicall_st0 or sts_st or lds_st or nskip_inst_st0; -- INSTRUCTION DECODER (CONNECTED AFTER NOP INSERTION LOGIC) idc_adc <= '1' when instruction_code_reg(15 downto 10) = "000111" else '0'; -- 000111XXXXXXXXXX idc_add <= '1' when instruction_code_reg(15 downto 10) = "000011" else '0'; -- 000011XXXXXXXXXX idc_adiw <= '1' when instruction_code_reg(15 downto 8) = "10010110" else '0'; -- 10010110XXXXXXXX idc_and <= '1' when instruction_code_reg(15 downto 10) = "001000" else '0'; -- 001000XXXXXXXXXX idc_andi <= '1' when instruction_code_reg(15 downto 12) = "0111" else '0'; -- 0111XXXXXXXXXXXX idc_asr <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100101" else '0'; -- 1001010XXXXX0101 idc_bclr <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010011000" else '0'; -- 100101001XXX1000 idc_bld <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3) = "11111000" else '0'; -- 1111100XXXXX0XXX idc_brbc <= '1' when instruction_code_reg(15 downto 10) = "111101" else '0'; -- 111101XXXXXXXXXX idc_brbs <= '1' when instruction_code_reg(15 downto 10) = "111100" else '0'; -- 111100XXXXXXXXXX idc_bset <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010001000" else '0'; -- 100101000XXX1000 idc_bst <= '1' when instruction_code_reg(15 downto 9) = "1111101" else '0'; -- 1111101XXXXXXXXX idc_call <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010111" else '0'; -- 1001010XXXXX111X idc_cbi <= '1' when instruction_code_reg(15 downto 8) = "10011000" else '0'; -- 10011000XXXXXXXX idc_com <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100000" else '0'; -- 1001010XXXXX0000 idc_cp <= '1' when instruction_code_reg(15 downto 10) = "000101" else '0'; -- 000101XXXXXXXXXX idc_cpc <= '1' when instruction_code_reg(15 downto 10) = "000001" else '0'; -- 000001XXXXXXXXXX idc_cpi <= '1' when instruction_code_reg(15 downto 12) = "0011" else '0'; -- 0011XXXXXXXXXXXX idc_cpse <= '1' when instruction_code_reg(15 downto 10) = "000100" else '0'; -- 000100XXXXXXXXXX idc_dec <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010101010" else '0'; -- 1001010XXXXX1010 idc_elpm <= '1' when instruction_code_reg = "1001010111011000" else '0'; -- 1001010111011000 idc_eor <= '1' when instruction_code_reg(15 downto 10) = "001001" else '0'; -- 001001XXXXXXXXXX idc_icall<= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101011001" else '0'; -- 10010101XXXX1001 idc_ijmp <= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101001001" else '0'; -- 10010100XXXX1001 idc_in <= '1' when instruction_code_reg(15 downto 11) = "10110" else '0'; -- 10110XXXXXXXXXXX idc_inc <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100011" else '0'; -- 1001010XXXXX0011 idc_jmp <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010110" else '0'; -- 1001010XXXXX110X -- LD,LDD idc_ld_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001100" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001101" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001110" else '0'; idc_ld_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001010") else '0'; idc_ldd_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10001" else '0'; -- 10X0XX0XXXXX1XXX idc_ld_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000010") else '0'; idc_ldd_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10000" else '0'; -- 10X0XX0XXXXX0XXX -- ###### idc_ldi <= '1' when instruction_code_reg(15 downto 12) = "1110" else '0'; -- 1110XXXXXXXXXXXX idc_lds <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010000000" else '0'; -- 1001000XXXXX0000 idc_lpm <= '1' when instruction_code_reg = "1001010111001000" else '0'; -- 1001010111001000 idc_lsr <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100110" else '0'; -- 1001010XXXXX0110 idc_mov <= '1' when instruction_code_reg(15 downto 10) = "001011" else '0'; -- 001011XXXXXXXXXX idc_mul <= '1' when instruction_code_reg(15 downto 10) = "100111" else '0'; -- 100111XXXXXXXXXX idc_neg <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100001" else '0'; -- 1001010XXXXX0001 idc_nop <= '1' when instruction_code_reg = "0000000000000000" else '0'; -- 0000000000000000 idc_or <= '1' when instruction_code_reg(15 downto 10) = "001010" else '0'; -- 001010XXXXXXXXXX idc_ori <= '1' when instruction_code_reg(15 downto 12) = "0110" else '0'; -- 0110XXXXXXXXXXXX idc_out <= '1' when instruction_code_reg(15 downto 11) = "10111" else '0'; -- 10111XXXXXXXXXXX idc_pop <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001111" else '0'; -- 1001000XXXXX1111 idc_push<= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011111" else '0'; -- 1001001XXXXX1111 idc_rcall<= '1' when instruction_code_reg(15 downto 12) = "1101" else '0'; -- 1101XXXXXXXXXXXX idc_ret <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101001000" else '0'; -- 100101010XX01000 idc_reti <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101011000" else '0'; -- 100101010XX11000 idc_rjmp <= '1' when instruction_code_reg(15 downto 12) = "1100" else '0'; -- 1100XXXXXXXXXXXX idc_ror <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100111" else '0'; -- 1001010XXXXX0111 idc_sbc <= '1' when instruction_code_reg(15 downto 10) = "000010" else '0'; -- 000010XXXXXXXXXX idc_sbci <= '1' when instruction_code_reg(15 downto 12) = "0100" else '0'; -- 0100XXXXXXXXXXXX idc_sbi <= '1' when instruction_code_reg(15 downto 8) = "10011010" else '0'; -- 10011010XXXXXXXX idc_sbic <= '1' when instruction_code_reg(15 downto 8) = "10011001" else '0'; -- 10011001XXXXXXXX idc_sbis <= '1' when instruction_code_reg(15 downto 8) = "10011011" else '0'; -- 10011011XXXXXXXX idc_sbiw <= '1' when instruction_code_reg(15 downto 8) = "10010111" else '0'; -- 10010111XXXXXXXX idc_sbrc <= '1' when instruction_code_reg(15 downto 9) = "1111110" else '0'; -- 1111110XXXXXXXXX idc_sbrs <= '1' when instruction_code_reg(15 downto 9) = "1111111" else '0'; -- 1111111XXXXXXXXX idc_sleep<= '1' when instruction_code_reg(15 downto 5)&instruction_code_reg(3 downto 0) = "100101011001000" else '0'; -- 10010101100X1000 -- ST,STD idc_st_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011100" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011101" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011110" else '0'; idc_st_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011010") else '0'; idc_std_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10011" else '0'; -- 10X0XX1XXXXX1XXX idc_st_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010010") else '0'; idc_std_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10010" else '0'; -- 10X0XX1XXXXX0XXX -- ###### idc_sts <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010010000" else '0'; -- 1001001XXXXX0000 idc_sub <= '1' when instruction_code_reg(15 downto 10) = "000110" else '0'; -- 000110XXXXXXXXXX idc_subi <= '1' when instruction_code_reg(15 downto 12) = "0101" else '0'; -- 0101XXXXXXXXXXXX idc_swap <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100010" else '0'; -- 1001010XXXXX0010 idc_wdr <= '1' when instruction_code_reg(15 downto 5)&instruction_code_reg(3 downto 0) = "100101011011000" else '0'; -- 10010101101X1000 -- ADDITIONAL SIGNALS idc_psinc <= '1' when (instruction_code_reg(1 downto 0) = "01" and (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0'; -- POST INCREMENT FOR LD/ST INSTRUCTIONS idc_prdec <= '1' when (instruction_code_reg(1 downto 0) = "10" and (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0'; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS -- ########################################################################################################## -- WRITE ENABLE SIGNALS FOR ramadr_reg ramadr_reg_en <= idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or idc_lds or -- LD/LDD/LDS(two cycle execution) idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or idc_sts or -- ST/STS/STS(two cycle execution) idc_push or idc_pop or idc_rcall or (rcall_st1 and not cpuwait) or idc_icall or (icall_st1 and not cpuwait) or -- RCALL/ICALL call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait) or -- CALL/IRQ idc_ret or (ret_st1 and not cpuwait ) or idc_reti or (reti_st1 and not cpuwait); -- RET/RETI -- ?? -- RAMADR MUX ramadr_reg_in <= sph_out&spl_out when (idc_rcall or (rcall_st1 and not cpuwait)or idc_icall or (icall_st1 and not cpuwait)or -- RCALL/ICALL call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait) or -- CALL/IRQ idc_push )='1' else -- PUSH (sph_out&spl_out)+1 when (idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait) or idc_pop)='1' else -- RET/RETI/POP inst when (idc_lds or idc_sts) ='1' else -- LDS/STS (two cycle execution) reg_h_out when (idc_ld_x or idc_ld_y or idc_ld_z or idc_st_x or idc_st_y or idc_st_z)='1' else -- LD/ST (reg_h_out + ("000000000"&dex_adr_disp)); -- LDD/STD -- ADDRESS REGISTER ramadr_reg:process(cp2,ireset) begin if ireset='0' then ramadr_int <= (others => '0'); elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then ramadr_int <= ramadr_reg_in; end if; end if; end if; end process; ramadr <= ramadr_int; -- GENERAL PURPOSE REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS gp_reg_adr:process(cp2,ireset) begin if ireset='0' then reg_file_adr_space <='0'; elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then if (ramadr_reg_in(15 downto 5)=const_ram_to_reg) then reg_file_adr_space <= '1'; -- ADRESS RANGE 0x0000-0x001F -> REGISTERS (R0-R31) else reg_file_adr_space <= '0'; end if; end if; end if; end if; end process; -- I/O REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS io_reg_adr:process(cp2,ireset) begin if ireset='0' then io_file_adr_space<='0'; elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then if (ramadr_reg_in(15 downto 5)=const_ram_to_io_a or ramadr_reg_in(15 downto 5)=const_ram_to_io_b or ramadr_reg_in(15 downto 12)=const_ram_to_io_c) then io_file_adr_space <= '1'; -- ADRESS RANGE 0x0020-0x005F -> I/O PORTS (0x00-0x3F) and ADRESS RANGE 0x1000-0x1FFF -> I/O PORTS (0x0FE0-0x1FDF) User Ports else io_file_adr_space <= '0'; end if; end if; end if; end if; end process; -- ########################################################################################################## -- REGRE/REGWE LOGIC (5 BIT ADDSRESS BUS (INTERNAL ONLY) 32 LOCATIONS (R0-R31)) -- WRITE ENABLE FOR Rd REGISTERS alu_reg_wr <= idc_adc or idc_add or idc_adiw or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or idc_sbiw or sbiw_st or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or idc_swap; reg_rd_wr <= idc_in or alu_reg_wr or idc_bld or -- ALU INSTRUCTIONS + IN/BLD INSRTRUCTION (pop_st or ld_st or lds_st)or -- POP/LD/LDD/LDS INSTRUCTIONS ((st_st or sts_st) and reg_file_adr_space)or -- ST/STD/STS INSTRUCTION lpm_st2 or idc_ldi or idc_mov; -- LPM/LDI/MOV INSTRUCTION reg_rd_adr <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else "00000" when lpm_st2='1' else adiw_sbiw_encoder_out when (idc_adiw or idc_sbiw)='1' else adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else dex_adrreg_d_latched when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else ramadr_int(4 downto 0) when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_d; reg_rr_adr <= ramadr_int(4 downto 0) when ((ld_st or lds_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_d_latched when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_r; -- MULTIPLEXER FOR REGISTER FILE Rd INPUT reg_rd_in <= dbusin when (idc_in or ((lds_st or ld_st)and not reg_file_adr_space) or pop_st)='1' else -- FROM INPUT DATA BUS reg_rr_out when ((lds_st or ld_st) and reg_file_adr_space)='1' else gp_reg_tmp when ((st_st or sts_st) and reg_file_adr_space)='1' else -- ST/STD/STS & ADDRESS FROM 0 TO 31 (REGISTER FILE) bld_op_out when (idc_bld='1')else -- FROM BIT PROCESSOR BLD COMMAND reg_rr_out when (idc_mov='1')else -- FOR MOV INSTRUCTION instruction_reg(15 downto 8) when (lpm_st2='1' and reg_z_out(0)='1') else -- LPM/ELPM instruction_reg(7 downto 0) when (lpm_st2='1' and reg_z_out(0)='0') else -- LPM/ELPM dex_dat8_immed when idc_ldi='1' else alu_data_out; -- FROM ALU DATA OUT -- IORE/IOWE LOGIC (6 BIT ADDRESS adr[5..0] FOR I/O PORTS(64 LOCATIONS)) iore_int <= idc_in or idc_sbi or idc_cbi or idc_sbic or idc_sbis or ((ld_st or lds_st) and io_file_adr_space); -- IN/SBI/CBI iowe_int <= '1' when ((idc_out or sbi_st or cbi_st) or ((st_st or sts_st) and io_file_adr_space))='1' else '0'; -- OUT/SBI/CBI + !! ST/STS/STD -- adr[5..0] BUS MULTIPLEXER adr_int <= "0000000000"&dex_adr6port when (idc_in or idc_out) = '1' else -- IN/OUT INSTRUCTIONS "0000000000"&'0'&dex_adr5port when (idc_cbi or idc_sbi or idc_sbic or idc_sbis) ='1' else -- CBI/SBI (READ PHASE) + SBIS/SBIC "0000000000"&'0'&cbi_sbi_io_adr_tmp when (cbi_st or sbi_st)='1' else -- CBI/SBI (WRITE PHASE) ramadr_int-x"20"; --(6)&ramadr_int(4 downto 0); -- LD/LDS/LDD/ST/STS/STD -- ramre LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS)) --ramre_int <= not(reg_file_adr_space or io_file_adr_space) and -- (ld_st or lds_st2 or pop_st or -- LD/LDD/LDS/POP/ -- ret_st1 or ret_st2 or reti_st1 or reti_st2); -- RET/RETI DataMemoryRead:process(cp2,ireset) begin if ireset='0' then -- Reset ramre_int <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then -- Clock enable case ramre_int is when '0' => if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and ramadr_reg_in(15 downto 12)/=const_ram_to_io_c and ramadr_reg_in(15 downto 5)/=const_ram_to_reg and (idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or -- LD/LDD instruction idc_lds or -- LDS instruction(two cycle execution) idc_pop or -- POP instruction idc_ret or -- RET instruction idc_reti)='1') -- RETI instruction then ramre_int <='1'; end if; when '1' => if ((ld_st or lds_st or pop_st or ret_st2 or reti_st2)and not cpuwait)='1' then ramre_int <='0'; end if; when others => null; end case; end if; end if; end process; -- ramwe LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS)) --ramwe_int <= not(reg_file_adr_space or io_file_adr_space) and -- (st_st or sts_st2 or push_st or rcall_st1 or rcall_st2 or -- ST/STD/STS/PUSH/RCALL -- icall_st1 or icall_st2 or -- ICALL -- call_st2 or call_st3 or -- CALL -- irq_st2 or irq_st3); -- INTERRUPT DataMemoryWrite:process(cp2,ireset) begin if ireset='0' then -- Reset ramwe_int <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then -- Clock enable case ramwe_int is when '0' => if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and ramadr_reg_in(15 downto 12)/=const_ram_to_io_c and ramadr_reg_in(15 downto 5)/=const_ram_to_reg and (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or -- ST/STD instruction idc_sts or -- STS instruction (two cycle execution) idc_push or -- PUSH instruction idc_rcall or -- RCALL instruction idc_icall or -- ICALL instruction call_st1 or -- CALL instruction irq_st1)='1') -- Interrupt then ramwe_int <='1'; end if; when '1' => if ((st_st or sts_st or push_st or rcall_st2 or icall_st2 or call_st3 or irq_st3)and not cpuwait)='1' then ramwe_int <='0'; end if; when others => null; end case; end if; end if; end process; -- DBUSOUT MULTIPLEXER dbusout_mux_logic: for i in dbusout_int'range generate dbusout_int(i)<= (reg_rd_out(i) and (idc_push or idc_sts or (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS (gp_reg_tmp(i) and (st_st or sts_st))or -- NEW (bitpr_io_out(i) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS (program_counter(i) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC (program_counter_high_fr(i) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC (pc_for_interrupt(i) and irq_st1) or (pc_for_interrupt(i+8) and irq_st2) or (reg_rd_out(i) and idc_out); -- OUT end generate; -- ALU CONNECTION -- ALU Rr INPUT MUX alu_data_r_in <= dex_dat8_immed when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi)='1' else "00"&dex_dat6_immed when (idc_adiw or idc_sbiw) ='1' else "00000000" when (adiw_st or sbiw_st) ='1' else reg_rr_out; -- gp_reg_tmp STORES TEMPREOARY THE VALUE OF SOURCE REGISTER DURING ST/STD/STS INSTRUCTION gp_registers_trig:process(cp2,ireset) begin if (ireset='0') then gp_reg_tmp <= (others=>'0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable -- if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or sts_st1)='1' then -- CLOCK ENABLE if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or idc_sts)='1' then -- CLOCK ENABLE gp_reg_tmp <= reg_rd_out; end if; end if; end if; end process; -- ********************************************************************************************************** -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- +++++++++++++++++++++++++++++++++++++++ PROGRAM COUNTER ++++++++++++++++++++++++++++++++++++++++++++++++++ -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ program_counter_high_store:process(cp2,ireset) begin if ireset='0' then -- RESET program_counter_high_fr <=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if (idc_rcall or idc_icall or call_st1 or irq_st1) ='1' then program_counter_high_fr <= program_counter(15 downto 8); -- STORE HIGH BYTE OF THE PROGRAMM COUNTER FOR RCALL/ICALL/CALL INSTRUCTIONS AND INTERRUPTS end if; end if; end if; end process; program_counter_for_lpm_elpm:process(cp2,ireset) begin if ireset='0' then -- RESET program_counter_tmp<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if (idc_lpm or idc_elpm) ='1' then program_counter_tmp <= program_counter; end if; end if; end if; end process; pa15_pm <= rampz_out(0) and idc_elpm; -- '0' WHEN LPM INSTRUCTIONS RAMPZ(0) WHEN ELPM INSTRUCTION -- OFFSET FOR BRBC/BRBS INSTRUCTIONS +63/-64 offset_brbx <= "0000000000"&dex_brxx_offset(5 downto 0) when (dex_brxx_offset(6)='0') else -- + "1111111111"&dex_brxx_offset(5 downto 0); -- - -- OFFSET FOR RJMP/RCALL INSTRUCTIONS +2047/-2048 offset_rxx <= "00000"&dex_adr12mem_s(10 downto 0) when (dex_adr12mem_s(11)='0') else -- + "11111"&dex_adr12mem_s(10 downto 0); -- - program_counter <= pc_high&pc_low; program_counter_in <= program_counter + offset_brbx when ((idc_brbc or idc_brbs) and bit_test_op_out) ='1'else -- BRBC/BRBS program_counter + offset_rxx when (idc_rjmp or idc_rcall)='1'else -- RJMP/RCALL reg_z_out when (idc_ijmp or idc_icall)='1'else -- IJMP/ICALL pa15_pm&reg_z_out(15 downto 1) when (idc_lpm or idc_elpm) ='1'else -- LPM/ELPM instruction_reg when (jmp_st1 or call_st1)='1'else -- JMP/CALL "0000000000"&irqackad_int&'0' when irq_st1 ='1' else -- INTERRUPT dbusin&"00000000" when (ret_st1 or reti_st1)='1' else -- RET/RETI -> PC HIGH BYTE "00000000"&dbusin when (ret_st2 or reti_st2)='1' else -- RET/RETI -> PC LOW BYTE program_counter_tmp when (lpm_st1)='1' -- AFTER LPM/ELPM INSTRUCTION else program_counter+1; -- THE MOST USUAL CASE pc_low_en <= not (idc_ld_x or idc_ld_y or idc_ld_z or idc_ldd_y or idc_ldd_z or idc_st_x or idc_st_y or idc_st_z or idc_std_y or idc_std_z or ((sts_st or lds_st) and cpuwait)or idc_adiw or idc_sbiw or idc_push or idc_pop or idc_cbi or idc_sbi or rcall_st1 or icall_st1 or call_st2 or irq_st2 or cpuwait or ret_st1 or reti_st1); pc_high_en <= not (idc_ld_x or idc_ld_y or idc_ld_z or idc_ldd_y or idc_ldd_z or idc_st_x or idc_st_y or idc_st_z or idc_std_y or idc_std_z or ((sts_st or lds_st) and cpuwait) or idc_adiw or idc_sbiw or idc_push or idc_pop or idc_cbi or idc_sbi or rcall_st1 or icall_st1 or call_st2 or irq_st2 or cpuwait or ret_st2 or reti_st2); program_counter_low:process(cp2,ireset) begin if ireset='0' then -- RESET pc_low<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if pc_low_en ='1' then pc_low <= program_counter_in(7 downto 0); end if; end if; end if; end process; program_counter_high:process(cp2,ireset) begin if ireset='0' then -- RESET pc_high<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if pc_high_en ='1' then pc_high <= program_counter_in(15 downto 8); end if; end if; end if; end process; pc <= program_counter; program_counter_for_interrupt:process(cp2,ireset) begin if ireset='0' then -- RESET pc_for_interrupt <=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if irq_start ='1' then pc_for_interrupt <= program_counter; end if; end if; end if; end process; -- END OF PROGRAM COUNTER -- STATE MACHINES skip_inst_start <= ((idc_sbrc or idc_sbrs or idc_sbic or idc_sbis) and bit_test_op_out)or (idc_cpse and alu_z_flag_out); skip_instruction_sm:process(cp2,ireset) begin if ireset='0' then -- RESET nskip_inst_st0 <= '0'; skip_inst_st1 <= '0'; skip_inst_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nskip_inst_st0 <= (not nskip_inst_st0 and skip_inst_start) or (nskip_inst_st0 and not((skip_inst_st1 and not two_word_inst) or skip_inst_st2)); skip_inst_st1 <= (not skip_inst_st1 and not nskip_inst_st0 and skip_inst_start); skip_inst_st2 <= not skip_inst_st2 and skip_inst_st1 and two_word_inst; end if; end if; end process; alu_state_machines:process(cp2,ireset) begin if ireset='0' then -- RESET adiw_st <= '0'; sbiw_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable adiw_st <= not adiw_st and idc_adiw; sbiw_st <= not sbiw_st and idc_sbiw; end if; end if; end process; lpm_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nlpm_st0 <= '0'; lpm_st1 <= '0'; lpm_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nlpm_st0 <= (not nlpm_st0 and (idc_lpm or idc_elpm)) or (nlpm_st0 and not lpm_st2); lpm_st1 <= (not lpm_st1 and not nlpm_st0 and (idc_lpm or idc_elpm)); -- ?? lpm_st2 <= not lpm_st2 and lpm_st1; end if; end if; end process; lds_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET lds_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable lds_st <= (not lds_st and idc_lds) or (lds_st and cpuwait); end if; end if; end process; sts_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET sts_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable sts_st <= (not sts_st and idc_sts) or (sts_st and cpuwait); end if; end if; end process; jmp_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET njmp_st0 <= '0'; jmp_st1 <= '0'; jmp_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable njmp_st0 <= (not njmp_st0 and idc_jmp) or (njmp_st0 and not jmp_st2); jmp_st1 <= not jmp_st1 and not njmp_st0 and idc_jmp; -- ?? jmp_st2 <= not jmp_st2 and jmp_st1; end if; end if; end process; rcall_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nrcall_st0 <= '0'; rcall_st1 <= '0'; rcall_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nrcall_st0 <= (not nrcall_st0 and idc_rcall) or (nrcall_st0 and not (rcall_st2 and not cpuwait)); rcall_st1 <= (not rcall_st1 and not nrcall_st0 and idc_rcall) or (rcall_st1 and cpuwait); rcall_st2 <= (not rcall_st2 and rcall_st1 and not cpuwait) or (rcall_st2 and cpuwait); end if; end if; end process; icall_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nicall_st0 <= '0'; icall_st1 <= '0'; icall_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nicall_st0 <= (not nicall_st0 and idc_icall) or (nicall_st0 and not (icall_st2 and not cpuwait)); icall_st1 <= (not icall_st1 and not nicall_st0 and idc_icall) or (icall_st1 and cpuwait); icall_st2 <= (not icall_st2 and icall_st1 and not cpuwait) or (icall_st2 and cpuwait); end if; end if; end process; call_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET ncall_st0 <= '0'; call_st1 <= '0'; call_st2 <= '0'; call_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable ncall_st0 <= (not ncall_st0 and idc_call) or (ncall_st0 and not( call_st3 and not cpuwait)); call_st1 <= not call_st1 and not ncall_st0 and idc_call; call_st2 <= (not call_st2 and call_st1) or (call_st2 and cpuwait); call_st3 <= (not call_st3 and call_st2 and not cpuwait) or (call_st3 and cpuwait); end if; end if; end process; ret_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nret_st0 <= '0'; ret_st1 <= '0'; ret_st2 <= '0'; ret_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nret_st0 <= (not nret_st0 and idc_ret) or (nret_st0 and not ret_st3); ret_st1 <= (not ret_st1 and not nret_st0 and idc_ret) or (ret_st1 and cpuwait); ret_st2 <= (not ret_st2 and ret_st1 and not cpuwait) or (ret_st2 and cpuwait) ; ret_st3 <= not ret_st3 and ret_st2 and not cpuwait; end if; end if; end process; reti_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nreti_st0 <= '0'; reti_st1 <= '0'; reti_st2 <= '0'; reti_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nreti_st0 <= (not nreti_st0 and idc_reti) or (nreti_st0 and not reti_st3); reti_st1 <= (not reti_st1 and not nreti_st0 and idc_reti) or (reti_st1 and cpuwait); reti_st2 <= (not reti_st2 and reti_st1 and not cpuwait) or (reti_st2 and cpuwait) ; reti_st3 <= not reti_st3 and reti_st2 and not cpuwait; end if; end if; end process; -- INTERRUPT LOGIC AND STATE MACHINE irq_int <= '0' when irqlines="00000000000000000000000" else '1'; irq_vector_adr(15 downto 6)<=(others => '0'); irq_vector_adr(0) <= '0'; -- PRIORITY ENCODER irq_vector_adr(5 downto 1) <= "00001" when irqlines(0)='1' else -- 0x0002 "00010" when irqlines(1)='1' else -- 0x0004 "00011" when irqlines(2)='1' else -- 0x0006 "00100" when irqlines(3)='1' else -- 0x0008 "00101" when irqlines(4)='1' else -- 0x000A "00110" when irqlines(5)='1' else -- 0x000C "00111" when irqlines(6)='1' else -- 0x000E "01000" when irqlines(7)='1' else -- 0x0010 "01001" when irqlines(8)='1' else -- 0x0012 "01010" when irqlines(9)='1' else -- 0x0014 "01011" when irqlines(10)='1' else -- 0x0016 "01100" when irqlines(11)='1' else -- 0x0018 "01101" when irqlines(12)='1' else -- 0x001A "01110" when irqlines(13)='1' else -- 0x001C "01111" when irqlines(14)='1' else -- 0x001E "10000" when irqlines(15)='1' else -- 0x0020 "10001" when irqlines(16)='1' else -- 0x0022 "10010" when irqlines(17)='1' else -- 0x0024 "10011" when irqlines(18)='1' else -- 0x0026 "10100" when irqlines(19)='1' else -- 0x0028 "10101" when irqlines(20)='1' else -- 0x002A "10110" when irqlines(21)='1' else -- 0x002C "10111" when irqlines(22)='1' else -- 0x002E "00000"; -- MULTI CYCLE INSTRUCTION FLAG FOR IRQ cpu_busy <= idc_adiw or idc_sbiw or idc_cbi or idc_sbi or idc_rjmp or idc_ijmp or idc_jmp or jmp_st1 or -- idc_brbs or idc_brbc or -- Old variant ((idc_brbc or idc_brbs) and bit_test_op_out) or idc_lpm or lpm_st1 or skip_inst_start or (skip_inst_st1 and two_word_inst) or idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or (ld_st and cpuwait) or idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or (st_st and cpuwait) or idc_lds or (lds_st and cpuwait) or idc_sts or (sts_st and cpuwait) or idc_rcall or rcall_st1 or (rcall_st2 and cpuwait) or -- RCALL idc_icall or icall_st1 or (icall_st2 and cpuwait) or -- ICALL idc_call or call_st1 or call_st2 or (call_st3 and cpuwait) or -- CALL idc_push or (push_st and cpuwait) or -- PUSH (added 14.07.05) idc_pop or (pop_st and cpuwait) or -- POP (added 14.07.05) (idc_bclr and sreg_bop_wr_en(7)) or -- ??? CLI (iowe_int and sreg_adr_eq and not dbusout_int(7))or -- ??? Writing '0' to I flag (OUT/STD/ST/STD) nirq_st0 or -- idc_ret or nret_st0 or -- Old variant idc_ret or ret_st1 or ret_st2 or -- idc_reti or nreti_st0; -- At least one instruction must be executed after RETI and before the new interrupt. idc_reti or reti_st1 or reti_st2; sreg_adr_eq <= '1' when adr_int=SREG_Address else '0'; --irq_start <= irq_int and not cpu_busy and globint; irq_start <= irq_int and not cpu_busy and globint; irq_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nirq_st0 <= '0'; irq_st1 <= '0'; irq_st2 <= '0'; irq_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nirq_st0 <= (not nirq_st0 and irq_start) or (nirq_st0 and not (irq_st3 and not cpuwait)); irq_st1 <= (not irq_st1 and not nirq_st0 and irq_start); irq_st2 <= (not irq_st2 and irq_st1) or (irq_st2 and cpuwait); irq_st3 <= (not irq_st3 and irq_st2 and not cpuwait) or (irq_st3 and cpuwait); end if; end if; end process; irqack_reg:process(cp2,ireset) begin if ireset='0' then -- RESET irqack_int<='0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable irqack_int<= not irqack_int and irq_start; end if; end if; end process; irqack <= irqack_int; irqackad_reg:process(cp2,ireset) begin if ireset='0' then -- RESET irqackad_int<=(others=>'0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable irqackad_int<=irq_vector_adr(5 downto 1); end if; end if; end process; irqackad <= irqackad_int; -- ******************************************************************************************* rjmp_push_pop_ijmp_state_brxx_machine:process(cp2,ireset) begin if ireset='0' then -- RESET rjmp_st <= '0'; ijmp_st <= '0'; push_st <= '0'; pop_st <= '0'; brxx_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable rjmp_st <= idc_rjmp; -- ?? ijmp_st <= idc_ijmp; push_st <= (not push_st and idc_push) or (push_st and cpuwait); pop_st <= (not pop_st and idc_pop) or (pop_st and cpuwait); brxx_st <= not brxx_st and (idc_brbc or idc_brbs) and bit_test_op_out; end if; end if; end process; -- LD/LDD/ST/STD ld_st_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET ld_st <= '0'; st_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable ld_st <= (not ld_st and (idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z)) or (ld_st and cpuwait); st_st <= (not st_st and (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)) or (st_st and cpuwait); end if; end if; end process; -- SBI/CBI sbi_cbi_machine:process(cp2,ireset) begin if ireset='0' then -- RESET sbi_st <= '0'; cbi_st <= '0'; cbi_sbi_io_adr_tmp <= (others => '0'); cbi_sbi_bit_num_tmp <= (others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable sbi_st <= not sbi_st and idc_sbi; cbi_st <= not cbi_st and idc_cbi; cbi_sbi_io_adr_tmp <= dex_adr5port; cbi_sbi_bit_num_tmp <= dex_bitop_bitnum; end if; end if; end process; -- ######################################################################################## -- SREG FLAGS WRITE ENABLE LOGIC bclr_bset_op_en_logic:for i in sreg_bop_wr_en'range generate sreg_bop_wr_en(i) <= '1' when (dex_bitnum_sreg=i and (idc_bclr or idc_bset)='1') else '0'; end generate; sreg_c_wr_en <= idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_com or idc_neg or idc_cp or idc_cpc or idc_cpi or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(0); sreg_z_wr_en <= idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(1); sreg_n_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or sbiw_st or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(2); sreg_v_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or -- idc_adiw idc_sbc or idc_sbci or sbiw_st or idc_neg or idc_com or -- idc_sbiw idc_inc or idc_dec or idc_cp or idc_cpc or idc_cpi or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(3) or idc_and or idc_andi or idc_or or idc_ori or idc_eor; -- V-flag bug fixing sreg_s_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or sbiw_st or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(4); sreg_h_wr_en <= idc_add or idc_adc or idc_sub or idc_subi or idc_cp or idc_cpc or idc_cpi or idc_sbc or idc_sbci or idc_neg or sreg_bop_wr_en(5); sreg_t_wr_en <= idc_bst or sreg_bop_wr_en(6); sreg_i_wr_en <= irq_st1 or reti_st3 or sreg_bop_wr_en(7); -- WAS "irq_start" sreg_fl_in <= bit_pr_sreg_out when (idc_bst or idc_bclr or idc_bset)='1' else -- TO THE SREG reti_st3&'0'&alu_h_flag_out&alu_s_flag_out&alu_v_flag_out&alu_n_flag_out&alu_z_flag_out&alu_c_flag_out; -- ################################################################################################################# -- ********************************************************************************************* -- ************** INSTRUCTION DECODER OUTPUTS FOR THE OTHER BLOCKS **************************** -- ********************************************************************************************* -- FOR ALU idc_add_out <= idc_add; idc_adc_out <= idc_adc; idc_adiw_out <= idc_adiw; idc_sub_out <= idc_sub; idc_subi_out <= idc_subi; idc_sbc_out <= idc_sbc; idc_sbci_out <= idc_sbci; idc_sbiw_out <= idc_sbiw; adiw_st_out <= adiw_st; sbiw_st_out <= sbiw_st; idc_and_out <= idc_and; idc_andi_out <= idc_andi; idc_or_out <= idc_or; idc_ori_out <= idc_ori; idc_eor_out <= idc_eor; idc_com_out <= idc_com; idc_neg_out <= idc_neg; idc_inc_out <= idc_inc; idc_dec_out <= idc_dec; idc_cp_out <= idc_cp; idc_cpc_out <= idc_cpc; idc_cpi_out <= idc_cpi; idc_cpse_out <= idc_cpse; idc_lsr_out <= idc_lsr; idc_ror_out <= idc_ror; idc_asr_out <= idc_asr; idc_swap_out <= idc_swap; -- FOR THE BIT PROCESSOR sbi_st_out <= sbi_st; cbi_st_out <= cbi_st; idc_bst_out <= idc_bst; idc_bset_out <= idc_bset; idc_bclr_out <= idc_bclr; idc_sbic_out <= idc_sbic; idc_sbis_out <= idc_sbis; idc_sbrs_out <= idc_sbrs; idc_sbrc_out <= idc_sbrc; idc_brbs_out <= idc_brbs; idc_brbc_out <= idc_brbc; idc_reti_out <= idc_reti; -- POST INCREMENT/PRE DECREMENT FOR THE X,Y,Z REGISTERS post_inc <= idc_psinc; pre_dec <= idc_prdec; reg_h_wr <= (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z) and (idc_psinc or idc_prdec); reg_h_adr(0)<= idc_st_x or idc_ld_x; reg_h_adr(1)<= idc_st_y or idc_std_y or idc_ld_y or idc_ldd_y; reg_h_adr(2)<= idc_st_z or idc_std_z or idc_ld_z or idc_ldd_z; -- STACK POINTER CONTROL sp_ndown_up <= idc_pop or idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait); -- ????????? sp_en <= idc_push or idc_pop or idc_rcall or (rcall_st1 and not cpuwait) or idc_icall or (icall_st1 and not cpuwait) or idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait) or call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait); --???????? branch <= dex_condition; bit_num_r_io <= cbi_sbi_bit_num_tmp when (cbi_st or sbi_st)='1' else dex_bitop_bitnum; adr <= adr_int; ramre <= ramre_int; ramwe <= ramwe_int; iore <= iore_int; iowe <= iowe_int; dbusout <= dbusout_int; -- Sleep Control sleepi <= idc_sleep; irqok <= irq_int; -- Watchdog wdri <= idc_wdr; -- ************************** JTAG OCD support ************************************ -- Change of flow change_flow <= '0'; valid_instr <= '0'; end RTL;
--************************************************************************************************ -- PM_FETCH_DEC(internal module) for AVR core -- Version 2.6! (Special version for the JTAG OCD) -- Designed by Ruslan Lepetenok 14.11.2001 -- Modified 31.05.06 -- Modification: -- Registered ramre/ramwe outputs -- cpu_busy logic modified(affects RCALL/ICALL/CALL instruction interract with interrupt) -- SLEEP and CLRWDT instructions support was added -- V-flag bug fixed (AND/ANDI/OR/ORI/EOR) -- V-flag bug fixed (ADIW/SBIW) -- Unused outputs(sreg_bit_num[2..0],idc_sbi_out,idc_cbi_out,idc_bld_out) were removed. -- Output alu_data_d_in[7..0] was removed. -- Gloabal clock enable(cp2en) was added -- cpu_busy(push/pop) + irq bug was fixed 14.07.05 -- BRXX+IRQ interaction was modified -> cpu_busy -- LDS/STS now requires only two cycles for execution (13.01.06 -> last modificatioon) --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.AVRuCPackage.all; entity pm_fetch_dec is port( -- Clock and reset cp2 : in std_logic; cp2en : in std_logic; ireset : in std_logic; -- JTAG OCD support valid_instr : out std_logic; insert_nop : in std_logic; block_irq : in std_logic; change_flow : out std_logic; -- Program memory pc : out std_logic_vector (15 downto 0); inst : in std_logic_vector (15 downto 0); -- I/O control adr : out std_logic_vector (15 downto 0); iore : out std_logic; iowe : out std_logic; -- Data memory control ramadr : out std_logic_vector (15 downto 0); ramre : out std_logic; ramwe : out std_logic; cpuwait : in std_logic; -- Data paths dbusin : in std_logic_vector (7 downto 0); dbusout : out std_logic_vector (7 downto 0); -- Interrupt irqlines : in std_logic_vector (22 downto 0); irqack : out std_logic; irqackad : out std_logic_vector(4 downto 0); --Sleep sleepi : out std_logic; irqok : out std_logic; --Watchdog wdri : out std_logic; -- ALU interface(Data inputs) alu_data_r_in : out std_logic_vector(7 downto 0); -- ALU interface(Instruction inputs) idc_add_out : out std_logic; idc_adc_out : out std_logic; idc_adiw_out : out std_logic; idc_sub_out : out std_logic; idc_subi_out : out std_logic; idc_sbc_out : out std_logic; idc_sbci_out : out std_logic; idc_sbiw_out : out std_logic; adiw_st_out : out std_logic; sbiw_st_out : out std_logic; idc_and_out : out std_logic; idc_andi_out : out std_logic; idc_or_out : out std_logic; idc_ori_out : out std_logic; idc_eor_out : out std_logic; idc_com_out : out std_logic; idc_neg_out : out std_logic; idc_inc_out : out std_logic; idc_dec_out : out std_logic; idc_cp_out : out std_logic; idc_cpc_out : out std_logic; idc_cpi_out : out std_logic; idc_cpse_out : out std_logic; idc_lsr_out : out std_logic; idc_ror_out : out std_logic; idc_asr_out : out std_logic; idc_swap_out : out std_logic; -- ALU interface(Data output) alu_data_out : in std_logic_vector(7 downto 0); -- ALU interface(Flag outputs) alu_c_flag_out : in std_logic; alu_z_flag_out : in std_logic; alu_n_flag_out : in std_logic; alu_v_flag_out : in std_logic; alu_s_flag_out : in std_logic; alu_h_flag_out : in std_logic; -- General purpose register file interface reg_rd_in : out std_logic_vector (7 downto 0); reg_rd_out : in std_logic_vector (7 downto 0); reg_rd_adr : out std_logic_vector (4 downto 0); reg_rr_out : in std_logic_vector (7 downto 0); reg_rr_adr : out std_logic_vector (4 downto 0); reg_rd_wr : out std_logic; post_inc : out std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS pre_dec : out std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS reg_h_wr : out std_logic; reg_h_out : in std_logic_vector (15 downto 0); reg_h_adr : out std_logic_vector (2 downto 0); -- x,y,z reg_z_out : in std_logic_vector (15 downto 0); -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS -- I/O register file interface sreg_fl_in : out std_logic_vector(7 downto 0); globint : in std_logic; -- SREG I flag sreg_fl_wr_en : out std_logic_vector(7 downto 0); --FLAGS WRITE ENABLE SIGNALS spl_out : in std_logic_vector(7 downto 0); sph_out : in std_logic_vector(7 downto 0); sp_ndown_up : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-) sp_en : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS rampz_out : in std_logic_vector(7 downto 0); -- Bit processor interface bit_num_r_io : out std_logic_vector (2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS bitpr_io_out : in std_logic_vector(7 downto 0); -- SBI/CBI OUT branch : out std_logic_vector (2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION bit_pr_sreg_out : in std_logic_vector(7 downto 0); -- BCLR/BSET/BST(T-FLAG ONLY) bld_op_out : in std_logic_vector(7 downto 0); -- BLD OUT (T FLAG) bit_test_op_out : in std_logic; -- OUTPUT OF SBIC/SBIS/SBRS/SBRC sbi_st_out : out std_logic; cbi_st_out : out std_logic; idc_bst_out : out std_logic; idc_bset_out : out std_logic; idc_bclr_out : out std_logic; idc_sbic_out : out std_logic; idc_sbis_out : out std_logic; idc_sbrs_out : out std_logic; idc_sbrc_out : out std_logic; idc_brbs_out : out std_logic; idc_brbc_out : out std_logic; idc_reti_out : out std_logic); end pm_fetch_dec; architecture RTL of pm_fetch_dec is -- COPIES OF OUTPUTS signal ramadr_reg_in : std_logic_vector(15 downto 0); -- INPUT OF THE ADDRESS REGISTER signal ramadr_reg_en : std_logic; -- ADRESS REGISTER CLOCK ENABLE SIGNAL signal irqack_int : std_logic; signal irqackad_int : std_logic_vector(irqackad'range); -- #################################################### -- INTERNAL SIGNALS -- #################################################### -- NEW SIGNALS signal two_word_inst : std_logic; -- CALL/JMP/STS/LDS INSTRUCTION INDICATOR signal ram_adr_int : std_logic_vector (15 downto 0); constant const_ram_to_reg : std_logic_vector := "00000000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19 constant const_ram_to_io_a : std_logic_vector := "00000000001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F constant const_ram_to_io_b : std_logic_vector := "00000000010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F --constant const_ram_to_io_c : std_logic_vector := "0001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x1000 0x1FFF constant const_ram_to_io_c : std_logic_vector := "0010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x2000 0x2FFF -> change by Zvonimir Bandic constant const_ram_to_io_d : std_logic_vector := "00100000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x1000 0x3FFF -- LD/LDD/ST/STD SIGNALS signal adiw_sbiw_encoder_out : std_logic_vector (4 downto 0); signal adiw_sbiw_encoder_mux_out : std_logic_vector (4 downto 0); -- PROGRAM COUNTER SIGNALS signal program_counter_tmp : std_logic_vector (15 downto 0); -- TO STORE PC DURING LPM/ELPM INSTRUCTIONS signal program_counter : std_logic_vector (15 downto 0); signal program_counter_in : std_logic_vector (15 downto 0); signal program_counter_high_fr : std_logic_vector (7 downto 0); -- TO STORE PC FOR CALL,IRQ,RCALL,ICALL signal pc_low : std_logic_vector (7 downto 0); signal pc_high : std_logic_vector (7 downto 0); signal pc_low_en : std_logic; signal pc_high_en : std_logic; signal offset_brbx : std_logic_vector (15 downto 0); -- OFFSET FOR BRCS/BRCC INSTRUCTION !!CHECKED signal offset_rxx : std_logic_vector (15 downto 0); -- OFFSET FOR RJMP/RCALL INSTRUCTION !!CHECKED signal pa15_pm : std_logic; -- ADDRESS LINE 15 FOR LPM/ELPM INSTRUCTIONS ('0' FOR LPM,RAMPZ(0) FOR ELPM) signal alu_reg_wr : std_logic; -- ALU INSTRUCTIONS PRODUCING WRITE TO THE GENERAL PURPOSE REGISTER FILE -- DATA MEMORY,GENERAL PURPOSE REGISTERS AND I/O REGISTERS LOGIC --! IMPORTANT NOTICE : OPERATIONS WHICH USE STACK POINTER (SPH:SPL) CAN NOT ACCCSESS GENERAL -- PURPOSE REGISTER FILE AND INPUT/OUTPUT REGISTER FILE ! -- THESE OPERATIONS ARE : RCALL/ICALL/CALL/RET/RETI/PUSH/POP INSTRUCTIONS AND INTERRUPT signal reg_file_adr_space : std_logic; -- ACCSESS TO THE REGISTER FILE signal io_file_adr_space : std_logic; -- ACCSESS TO THE I/O FILE -- STATE MACHINES SIGNALS signal irq_start : std_logic; signal nirq_st0 : std_logic; signal irq_st1 : std_logic; signal irq_st2 : std_logic; signal irq_st3 : std_logic; signal ncall_st0 : std_logic; signal call_st1 : std_logic; signal call_st2 : std_logic; signal call_st3 : std_logic; signal nrcall_st0 : std_logic; signal rcall_st1 : std_logic; signal rcall_st2 : std_logic; signal nicall_st0 : std_logic; signal icall_st1 : std_logic; signal icall_st2 : std_logic; signal njmp_st0 : std_logic; signal jmp_st1 : std_logic; signal jmp_st2 : std_logic; signal ijmp_st : std_logic; signal rjmp_st : std_logic; signal nret_st0 : std_logic; signal ret_st1 : std_logic; signal ret_st2 : std_logic; signal ret_st3 : std_logic; signal nreti_st0 : std_logic; signal reti_st1 : std_logic; signal reti_st2 : std_logic; signal reti_st3 : std_logic; signal brxx_st : std_logic; -- BRANCHES signal adiw_st : std_logic; signal sbiw_st : std_logic; signal nskip_inst_st0 : std_logic; signal skip_inst_st1 : std_logic; signal skip_inst_st2 : std_logic; -- ALL SKIP INSTRUCTIONS SBRS/SBRC/SBIS/SBIC/CPSE signal skip_inst_start : std_logic; signal nlpm_st0 : std_logic; signal lpm_st1 : std_logic; signal lpm_st2 : std_logic; signal nelpm_st0 : std_logic; signal elpm_st1 : std_logic; signal elpm_st2 : std_logic; --signal nsts_st0 : std_logic; --signal sts_st1 : std_logic; --signal sts_st2 : std_logic; signal sts_st : std_logic; --signal nlds_st0 : std_logic; --signal lds_st1 : std_logic; --signal lds_st2 : std_logic; signal lds_st : std_logic; signal st_st : std_logic; signal ld_st : std_logic; signal sbi_st : std_logic; signal cbi_st : std_logic; signal push_st : std_logic; signal pop_st : std_logic; -- INTERNAL STATE MACHINES signal nop_insert_st : std_logic; signal cpu_busy : std_logic; -- INTERNAL COPIES OF OUTPUTS signal pc_int : std_logic_vector (15 downto 0); signal adr_int : std_logic_vector (15 downto 0); signal iore_int : std_logic; signal iowe_int : std_logic; signal ramadr_int : std_logic_vector (15 downto 0); signal ramre_int : std_logic; signal ramwe_int : std_logic; signal dbusout_int : std_logic_vector (7 downto 0); -- COMMAND REGISTER signal instruction_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER signal instruction_code_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER WITH NOP INSERTION signal instruction_reg_ena : std_logic; -- CLOCK ENABLE -- IRQ INTERNAL LOGIC signal irq_int : std_logic; signal irq_vector_adr : std_logic_vector(15 downto 0); -- INTERRUPT RELATING REGISTERS signal pc_for_interrupt : std_logic_vector(15 downto 0); -- DATA EXTRACTOR SIGNALS signal dex_dat8_immed : std_logic_vector (7 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ANDI,ORI,SUBI,SBCI,CPI,LDI signal dex_dat6_immed : std_logic_vector (5 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ADIW,SBIW signal dex_adr12mem_s : std_logic_vector (11 downto 0); -- RELATIVE ADDRESS (SIGNED) -> RCALL,RJMP signal dex_adr6port : std_logic_vector (5 downto 0); -- I/O PORT ADDRESS -> IN,OUT signal dex_adr5port : std_logic_vector (4 downto 0); -- I/O PORT ADDRESS -> CBI,SBI,SBIC,SBIS signal dex_adr_disp : std_logic_vector (5 downto 0); -- DISPLACEMENT FO ADDDRESS -> STD,LDD signal dex_condition : std_logic_vector (2 downto 0); -- CONDITION -> BRBC,BRBS signal dex_bitnum_sreg : std_logic_vector (2 downto 0); -- NUMBER OF BIT IN SREG -> BCLR,BSET signal dex_adrreg_r : std_logic_vector (4 downto 0); -- SOURCE REGISTER ADDRESS -> ....... signal dex_adrreg_d : std_logic_vector (4 downto 0); -- DESTINATION REGISTER ADDRESS -> ...... signal dex_bitop_bitnum : std_logic_vector(2 downto 0); -- NUMBER OF BIT FOR BIT ORIENTEDE OPERATION -> BST/BLD+SBI/CBI+SBIC/SBIS+SBRC/SBRS !! CHECKED signal dex_brxx_offset : std_logic_vector (6 downto 0); -- RELATIVE ADDRESS (SIGNED) -> BRBC,BRBS !! CHECKED signal dex_adiw_sbiw_reg_adr : std_logic_vector (1 downto 0); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS signal dex_adrreg_d_latched : std_logic_vector (4 downto 0); -- STORE ADDRESS OF DESTINATION REGISTER FOR LDS/STS/POP INSTRUCTIONS signal gp_reg_tmp : std_logic_vector (7 downto 0); -- STORE DATA FROM THE REGISTERS FOR STS,ST INSTRUCTIONS signal cbi_sbi_io_adr_tmp : std_logic_vector (4 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION signal cbi_sbi_bit_num_tmp : std_logic_vector (2 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION -- INSTRUCTIONS DECODER SIGNALS signal idc_adc : std_logic; -- INSTRUCTION ADC signal idc_add : std_logic; -- INSTRUCTION ADD signal idc_adiw : std_logic; -- INSTRUCTION ADIW signal idc_and : std_logic; -- INSTRUCTION AND signal idc_andi : std_logic; -- INSTRUCTION ANDI signal idc_asr : std_logic; -- INSTRUCTION ASR signal idc_bclr : std_logic; -- INSTRUCTION BCLR signal idc_bld : std_logic; -- INSTRUCTION BLD signal idc_brbc : std_logic; -- INSTRUCTION BRBC signal idc_brbs : std_logic; -- INSTRUCTION BRBS signal idc_bset : std_logic; -- INSTRUCTION BSET signal idc_bst : std_logic; -- INSTRUCTION BST signal idc_call : std_logic; -- INSTRUCTION CALL signal idc_cbi : std_logic; -- INSTRUCTION CBI signal idc_com : std_logic; -- INSTRUCTION COM signal idc_cp : std_logic; -- INSTRUCTION CP signal idc_cpc : std_logic; -- INSTRUCTION CPC signal idc_cpi : std_logic; -- INSTRUCTION CPI signal idc_cpse : std_logic; -- INSTRUCTION CPSE signal idc_dec : std_logic; -- INSTRUCTION DEC signal idc_elpm : std_logic; -- INSTRUCTION ELPM signal idc_eor : std_logic; -- INSTRUCTION EOR signal idc_icall : std_logic; -- INSTRUCTION ICALL signal idc_ijmp : std_logic; -- INSTRUCTION IJMP signal idc_in : std_logic; -- INSTRUCTION IN signal idc_inc : std_logic; -- INSTRUCTION INC signal idc_jmp : std_logic; -- INSTRUCTION JMP signal idc_ld_x : std_logic; -- INSTRUCTION LD Rx,X ; LD Rx,X+ ;LD Rx,-X signal idc_ld_y : std_logic; -- INSTRUCTION LD Rx,Y ; LD Rx,Y+ ;LD Rx,-Y signal idc_ldd_y : std_logic; -- INSTRUCTION LDD Rx,Y+q signal idc_ld_z : std_logic; -- INSTRUCTION LD Rx,Z ; LD Rx,Z+ ;LD Rx,-Z signal idc_ldd_z : std_logic; -- INSTRUCTION LDD Rx,Z+q signal idc_ldi : std_logic; -- INSTRUCTION LDI signal idc_lds : std_logic; -- INSTRUCTION LDS signal idc_lpm : std_logic; -- INSTRUCTION LPM signal idc_lsr : std_logic; -- INSTRUCTION LSR signal idc_mov : std_logic; -- INSTRUCTION MOV signal idc_mul : std_logic; -- INSTRUCTION MUL signal idc_neg : std_logic; -- INSTRUCTION NEG signal idc_nop : std_logic; -- INSTRUCTION NOP signal idc_or : std_logic; -- INSTRUCTION OR signal idc_ori : std_logic; -- INSTRUCTION ORI signal idc_out : std_logic; -- INSTRUCTION OUT signal idc_pop : std_logic; -- INSTRUCTION POP signal idc_push : std_logic; -- INSTRUCTION PUSH signal idc_rcall : std_logic; -- INSTRUCTION RCALL signal idc_ret : std_logic; -- INSTRUCTION RET signal idc_reti : std_logic; -- INSTRUCTION RETI signal idc_rjmp : std_logic; -- INSTRUCTION RJMP signal idc_ror : std_logic; -- INSTRUCTION ROR signal idc_sbc : std_logic; -- INSTRUCTION SBC signal idc_sbci : std_logic; -- INSTRUCTION SBCI signal idc_sbi : std_logic; -- INSTRUCTION SBI signal idc_sbic : std_logic; -- INSTRUCTION SBIC signal idc_sbis : std_logic; -- INSTRUCTION SBIS signal idc_sbiw : std_logic; -- INSTRUCTION SBIW signal idc_sbrc : std_logic; -- INSTRUCTION SBRC signal idc_sbrs : std_logic; -- INSTRUCTION SBRS signal idc_sleep : std_logic; -- INSTRUCTION SLEEP signal idc_st_x : std_logic; -- INSTRUCTION LD X,Rx ; LD X+,Rx ;LD -X,Rx signal idc_st_y : std_logic; -- INSTRUCTION LD Y,Rx ; LD Y+,Rx ;LD -Y,Rx signal idc_std_y : std_logic; -- INSTRUCTION LDD Y+q,Rx signal idc_st_z : std_logic; -- INSTRUCTION LD Z,Rx ; LD Z+,Rx ;LD -Z,Rx signal idc_std_z : std_logic; -- INSTRUCTION LDD Z+q,Rx signal idc_sts : std_logic; -- INSTRUCTION STS signal idc_sub : std_logic; -- INSTRUCTION SUB signal idc_subi : std_logic; -- INSTRUCTION SUBI signal idc_swap : std_logic; -- INSTRUCTION SWAP signal idc_wdr : std_logic; -- INSTRUCTION WDR -- ADDITIONAL SIGNALS signal idc_psinc : std_logic; -- POST INCREMENT FLAG FOR LD,ST INSTRUCTIONS signal idc_prdec : std_logic; -- PRE DECREMENT FLAG FOR LD,ST INSTRUCTIONS -- ################################################## -- SREG FLAGS WRITE ENABLE SIGNALS alias sreg_c_wr_en : std_logic is sreg_fl_wr_en(0); alias sreg_z_wr_en : std_logic is sreg_fl_wr_en(1); alias sreg_n_wr_en : std_logic is sreg_fl_wr_en(2); alias sreg_v_wr_en : std_logic is sreg_fl_wr_en(3); alias sreg_s_wr_en : std_logic is sreg_fl_wr_en(4); alias sreg_h_wr_en : std_logic is sreg_fl_wr_en(5); alias sreg_t_wr_en : std_logic is sreg_fl_wr_en(6); alias sreg_i_wr_en : std_logic is sreg_fl_wr_en(7); signal sreg_bop_wr_en : std_logic_vector (7 downto 0); signal sreg_adr_eq : std_logic; -- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& begin -- INSTRUCTION FETCH instruction_reg_ena <= '1'; -- FOR TEST instruction_fetch:process(cp2,ireset) begin if ireset='0' then -- RESET instruction_reg <= (others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if instruction_reg_ena='1' then instruction_reg <= inst; end if; end if; end if; end process; -- TWO WORDS INSTRUCTION DETECTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER) two_word_inst <= '1' when ((instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010111") or -- CALL (instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010110")) or -- JMP (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010000000") or -- LDS (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010010000") -- STS else '0'; -- TO DETECT CALL/JMP/LDS/STS INSTRUCTIONS FOR SBRS/SBRC/SBIS/SBIC/CPSE -- DATA EXTRACTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER) dex_dat8_immed <= instruction_reg(11 downto 8) & instruction_reg(3 downto 0); dex_dat6_immed <= instruction_reg(7 downto 6) & instruction_reg(3 downto 0); dex_adr12mem_s <= instruction_reg(11 downto 0); dex_adr6port <= instruction_reg(10 downto 9) & instruction_reg(3 downto 0); dex_adr5port <= instruction_reg(7 downto 3); dex_adr_disp <= instruction_reg(13) & instruction_reg(11 downto 10) & instruction_reg(2 downto 0); dex_condition <= instruction_reg(2 downto 0); dex_bitop_bitnum <= instruction_reg(2 downto 0); -- NUMBER(POSITION) OF TESTING BIT IN SBRC/SBRS/SBIC/SBIS INSTRUCTION dex_bitnum_sreg <= instruction_reg(6 downto 4); dex_adrreg_r <= instruction_reg(9) & instruction_reg(3 downto 0); dex_adrreg_d <= instruction_reg(8 downto 4); dex_brxx_offset <= instruction_reg(9 downto 3); -- OFFSET FOR BRBC/BRBS dex_adiw_sbiw_reg_adr <= instruction_reg(5 downto 4); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS --dex_adrindreg <= instruction_reg(3 downto 2); -- LATCH Rd ADDDRESS FOR LDS/STS/POP INSTRUCTIONS latcht_rd_adr:process(cp2,ireset) begin if ireset ='0' then dex_adrreg_d_latched <= (others => '0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if ((idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z) or idc_sts or (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)or idc_lds or idc_pop)='1' then dex_adrreg_d_latched <= dex_adrreg_d; end if; end if; end if; end process; -- +++++++++++++++++++++++++++++++++++++++++++++++++ -- R24:R25/R26:R27/R28:R29/R30:R31 ADIW/SBIW ADDRESS CONTROL LOGIC adiw_sbiw_encoder_out <= "11"&dex_adiw_sbiw_reg_adr&'0'; adiw_sbiw_high_reg_adr:process(cp2,ireset) begin if ireset ='0' then adiw_sbiw_encoder_mux_out <= (others=>'0'); elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_out +1; end if; end if; end process; -- ########################## -- NOP INSERTION --instruction_code_reg <= instruction_reg when nop_insert_st='0' else (others => '0'); instruction_code_reg <= (others => '0') when (nop_insert_st='1') else -- NOP instruction_reg; -- Instruction nop_insert_st <= adiw_st or sbiw_st or cbi_st or sbi_st or rjmp_st or ijmp_st or pop_st or push_st or brxx_st or ld_st or st_st or ncall_st0 or nirq_st0 or nret_st0 or nreti_st0 or nlpm_st0 or njmp_st0 or nrcall_st0 or nicall_st0 or sts_st or lds_st or nskip_inst_st0; -- INSTRUCTION DECODER (CONNECTED AFTER NOP INSERTION LOGIC) idc_adc <= '1' when instruction_code_reg(15 downto 10) = "000111" else '0'; -- 000111XXXXXXXXXX idc_add <= '1' when instruction_code_reg(15 downto 10) = "000011" else '0'; -- 000011XXXXXXXXXX idc_adiw <= '1' when instruction_code_reg(15 downto 8) = "10010110" else '0'; -- 10010110XXXXXXXX idc_and <= '1' when instruction_code_reg(15 downto 10) = "001000" else '0'; -- 001000XXXXXXXXXX idc_andi <= '1' when instruction_code_reg(15 downto 12) = "0111" else '0'; -- 0111XXXXXXXXXXXX idc_asr <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100101" else '0'; -- 1001010XXXXX0101 idc_bclr <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010011000" else '0'; -- 100101001XXX1000 idc_bld <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3) = "11111000" else '0'; -- 1111100XXXXX0XXX idc_brbc <= '1' when instruction_code_reg(15 downto 10) = "111101" else '0'; -- 111101XXXXXXXXXX idc_brbs <= '1' when instruction_code_reg(15 downto 10) = "111100" else '0'; -- 111100XXXXXXXXXX idc_bset <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010001000" else '0'; -- 100101000XXX1000 idc_bst <= '1' when instruction_code_reg(15 downto 9) = "1111101" else '0'; -- 1111101XXXXXXXXX idc_call <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010111" else '0'; -- 1001010XXXXX111X idc_cbi <= '1' when instruction_code_reg(15 downto 8) = "10011000" else '0'; -- 10011000XXXXXXXX idc_com <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100000" else '0'; -- 1001010XXXXX0000 idc_cp <= '1' when instruction_code_reg(15 downto 10) = "000101" else '0'; -- 000101XXXXXXXXXX idc_cpc <= '1' when instruction_code_reg(15 downto 10) = "000001" else '0'; -- 000001XXXXXXXXXX idc_cpi <= '1' when instruction_code_reg(15 downto 12) = "0011" else '0'; -- 0011XXXXXXXXXXXX idc_cpse <= '1' when instruction_code_reg(15 downto 10) = "000100" else '0'; -- 000100XXXXXXXXXX idc_dec <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010101010" else '0'; -- 1001010XXXXX1010 idc_elpm <= '1' when instruction_code_reg = "1001010111011000" else '0'; -- 1001010111011000 idc_eor <= '1' when instruction_code_reg(15 downto 10) = "001001" else '0'; -- 001001XXXXXXXXXX idc_icall<= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101011001" else '0'; -- 10010101XXXX1001 idc_ijmp <= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101001001" else '0'; -- 10010100XXXX1001 idc_in <= '1' when instruction_code_reg(15 downto 11) = "10110" else '0'; -- 10110XXXXXXXXXXX idc_inc <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100011" else '0'; -- 1001010XXXXX0011 idc_jmp <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010110" else '0'; -- 1001010XXXXX110X -- LD,LDD idc_ld_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001100" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001101" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001110" else '0'; idc_ld_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001010") else '0'; idc_ldd_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10001" else '0'; -- 10X0XX0XXXXX1XXX idc_ld_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000010") else '0'; idc_ldd_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10000" else '0'; -- 10X0XX0XXXXX0XXX -- ###### idc_ldi <= '1' when instruction_code_reg(15 downto 12) = "1110" else '0'; -- 1110XXXXXXXXXXXX idc_lds <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010000000" else '0'; -- 1001000XXXXX0000 idc_lpm <= '1' when instruction_code_reg = "1001010111001000" else '0'; -- 1001010111001000 idc_lsr <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100110" else '0'; -- 1001010XXXXX0110 idc_mov <= '1' when instruction_code_reg(15 downto 10) = "001011" else '0'; -- 001011XXXXXXXXXX idc_mul <= '1' when instruction_code_reg(15 downto 10) = "100111" else '0'; -- 100111XXXXXXXXXX idc_neg <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100001" else '0'; -- 1001010XXXXX0001 idc_nop <= '1' when instruction_code_reg = "0000000000000000" else '0'; -- 0000000000000000 idc_or <= '1' when instruction_code_reg(15 downto 10) = "001010" else '0'; -- 001010XXXXXXXXXX idc_ori <= '1' when instruction_code_reg(15 downto 12) = "0110" else '0'; -- 0110XXXXXXXXXXXX idc_out <= '1' when instruction_code_reg(15 downto 11) = "10111" else '0'; -- 10111XXXXXXXXXXX idc_pop <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001111" else '0'; -- 1001000XXXXX1111 idc_push<= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011111" else '0'; -- 1001001XXXXX1111 idc_rcall<= '1' when instruction_code_reg(15 downto 12) = "1101" else '0'; -- 1101XXXXXXXXXXXX idc_ret <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101001000" else '0'; -- 100101010XX01000 idc_reti <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101011000" else '0'; -- 100101010XX11000 idc_rjmp <= '1' when instruction_code_reg(15 downto 12) = "1100" else '0'; -- 1100XXXXXXXXXXXX idc_ror <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100111" else '0'; -- 1001010XXXXX0111 idc_sbc <= '1' when instruction_code_reg(15 downto 10) = "000010" else '0'; -- 000010XXXXXXXXXX idc_sbci <= '1' when instruction_code_reg(15 downto 12) = "0100" else '0'; -- 0100XXXXXXXXXXXX idc_sbi <= '1' when instruction_code_reg(15 downto 8) = "10011010" else '0'; -- 10011010XXXXXXXX idc_sbic <= '1' when instruction_code_reg(15 downto 8) = "10011001" else '0'; -- 10011001XXXXXXXX idc_sbis <= '1' when instruction_code_reg(15 downto 8) = "10011011" else '0'; -- 10011011XXXXXXXX idc_sbiw <= '1' when instruction_code_reg(15 downto 8) = "10010111" else '0'; -- 10010111XXXXXXXX idc_sbrc <= '1' when instruction_code_reg(15 downto 9) = "1111110" else '0'; -- 1111110XXXXXXXXX idc_sbrs <= '1' when instruction_code_reg(15 downto 9) = "1111111" else '0'; -- 1111111XXXXXXXXX idc_sleep<= '1' when instruction_code_reg(15 downto 5)&instruction_code_reg(3 downto 0) = "100101011001000" else '0'; -- 10010101100X1000 -- ST,STD idc_st_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011100" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011101" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011110" else '0'; idc_st_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011010") else '0'; idc_std_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10011" else '0'; -- 10X0XX1XXXXX1XXX idc_st_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010010") else '0'; idc_std_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10010" else '0'; -- 10X0XX1XXXXX0XXX -- ###### idc_sts <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010010000" else '0'; -- 1001001XXXXX0000 idc_sub <= '1' when instruction_code_reg(15 downto 10) = "000110" else '0'; -- 000110XXXXXXXXXX idc_subi <= '1' when instruction_code_reg(15 downto 12) = "0101" else '0'; -- 0101XXXXXXXXXXXX idc_swap <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100010" else '0'; -- 1001010XXXXX0010 idc_wdr <= '1' when instruction_code_reg(15 downto 5)&instruction_code_reg(3 downto 0) = "100101011011000" else '0'; -- 10010101101X1000 -- ADDITIONAL SIGNALS idc_psinc <= '1' when (instruction_code_reg(1 downto 0) = "01" and (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0'; -- POST INCREMENT FOR LD/ST INSTRUCTIONS idc_prdec <= '1' when (instruction_code_reg(1 downto 0) = "10" and (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0'; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS -- ########################################################################################################## -- WRITE ENABLE SIGNALS FOR ramadr_reg ramadr_reg_en <= idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or idc_lds or -- LD/LDD/LDS(two cycle execution) idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or idc_sts or -- ST/STS/STS(two cycle execution) idc_push or idc_pop or idc_rcall or (rcall_st1 and not cpuwait) or idc_icall or (icall_st1 and not cpuwait) or -- RCALL/ICALL call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait) or -- CALL/IRQ idc_ret or (ret_st1 and not cpuwait ) or idc_reti or (reti_st1 and not cpuwait); -- RET/RETI -- ?? -- RAMADR MUX ramadr_reg_in <= sph_out&spl_out when (idc_rcall or (rcall_st1 and not cpuwait)or idc_icall or (icall_st1 and not cpuwait)or -- RCALL/ICALL call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait) or -- CALL/IRQ idc_push )='1' else -- PUSH (sph_out&spl_out)+1 when (idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait) or idc_pop)='1' else -- RET/RETI/POP inst when (idc_lds or idc_sts) ='1' else -- LDS/STS (two cycle execution) reg_h_out when (idc_ld_x or idc_ld_y or idc_ld_z or idc_st_x or idc_st_y or idc_st_z)='1' else -- LD/ST (reg_h_out + ("000000000"&dex_adr_disp)); -- LDD/STD -- ADDRESS REGISTER ramadr_reg:process(cp2,ireset) begin if ireset='0' then ramadr_int <= (others => '0'); elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then ramadr_int <= ramadr_reg_in; end if; end if; end if; end process; ramadr <= ramadr_int; -- GENERAL PURPOSE REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS gp_reg_adr:process(cp2,ireset) begin if ireset='0' then reg_file_adr_space <='0'; elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then if (ramadr_reg_in(15 downto 5)=const_ram_to_reg) then reg_file_adr_space <= '1'; -- ADRESS RANGE 0x0000-0x001F -> REGISTERS (R0-R31) else reg_file_adr_space <= '0'; end if; end if; end if; end if; end process; -- I/O REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS io_reg_adr:process(cp2,ireset) begin if ireset='0' then io_file_adr_space<='0'; elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then if (ramadr_reg_in(15 downto 5)=const_ram_to_io_a or ramadr_reg_in(15 downto 5)=const_ram_to_io_b or ramadr_reg_in(15 downto 12)=const_ram_to_io_c) then io_file_adr_space <= '1'; -- ADRESS RANGE 0x0020-0x005F -> I/O PORTS (0x00-0x3F) and ADRESS RANGE 0x1000-0x1FFF -> I/O PORTS (0x0FE0-0x1FDF) User Ports else io_file_adr_space <= '0'; end if; end if; end if; end if; end process; -- ########################################################################################################## -- REGRE/REGWE LOGIC (5 BIT ADDSRESS BUS (INTERNAL ONLY) 32 LOCATIONS (R0-R31)) -- WRITE ENABLE FOR Rd REGISTERS alu_reg_wr <= idc_adc or idc_add or idc_adiw or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or idc_sbiw or sbiw_st or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or idc_swap; reg_rd_wr <= idc_in or alu_reg_wr or idc_bld or -- ALU INSTRUCTIONS + IN/BLD INSRTRUCTION (pop_st or ld_st or lds_st)or -- POP/LD/LDD/LDS INSTRUCTIONS ((st_st or sts_st) and reg_file_adr_space)or -- ST/STD/STS INSTRUCTION lpm_st2 or idc_ldi or idc_mov; -- LPM/LDI/MOV INSTRUCTION reg_rd_adr <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else "00000" when lpm_st2='1' else adiw_sbiw_encoder_out when (idc_adiw or idc_sbiw)='1' else adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else dex_adrreg_d_latched when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else ramadr_int(4 downto 0) when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_d; reg_rr_adr <= ramadr_int(4 downto 0) when ((ld_st or lds_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_d_latched when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_r; -- MULTIPLEXER FOR REGISTER FILE Rd INPUT reg_rd_in <= dbusin when (idc_in or ((lds_st or ld_st)and not reg_file_adr_space) or pop_st)='1' else -- FROM INPUT DATA BUS reg_rr_out when ((lds_st or ld_st) and reg_file_adr_space)='1' else gp_reg_tmp when ((st_st or sts_st) and reg_file_adr_space)='1' else -- ST/STD/STS & ADDRESS FROM 0 TO 31 (REGISTER FILE) bld_op_out when (idc_bld='1')else -- FROM BIT PROCESSOR BLD COMMAND reg_rr_out when (idc_mov='1')else -- FOR MOV INSTRUCTION instruction_reg(15 downto 8) when (lpm_st2='1' and reg_z_out(0)='1') else -- LPM/ELPM instruction_reg(7 downto 0) when (lpm_st2='1' and reg_z_out(0)='0') else -- LPM/ELPM dex_dat8_immed when idc_ldi='1' else alu_data_out; -- FROM ALU DATA OUT -- IORE/IOWE LOGIC (6 BIT ADDRESS adr[5..0] FOR I/O PORTS(64 LOCATIONS)) iore_int <= idc_in or idc_sbi or idc_cbi or idc_sbic or idc_sbis or ((ld_st or lds_st) and io_file_adr_space); -- IN/SBI/CBI iowe_int <= '1' when ((idc_out or sbi_st or cbi_st) or ((st_st or sts_st) and io_file_adr_space))='1' else '0'; -- OUT/SBI/CBI + !! ST/STS/STD -- adr[5..0] BUS MULTIPLEXER adr_int <= "0000000000"&dex_adr6port when (idc_in or idc_out) = '1' else -- IN/OUT INSTRUCTIONS "0000000000"&'0'&dex_adr5port when (idc_cbi or idc_sbi or idc_sbic or idc_sbis) ='1' else -- CBI/SBI (READ PHASE) + SBIS/SBIC "0000000000"&'0'&cbi_sbi_io_adr_tmp when (cbi_st or sbi_st)='1' else -- CBI/SBI (WRITE PHASE) ramadr_int-x"20"; --(6)&ramadr_int(4 downto 0); -- LD/LDS/LDD/ST/STS/STD -- ramre LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS)) --ramre_int <= not(reg_file_adr_space or io_file_adr_space) and -- (ld_st or lds_st2 or pop_st or -- LD/LDD/LDS/POP/ -- ret_st1 or ret_st2 or reti_st1 or reti_st2); -- RET/RETI DataMemoryRead:process(cp2,ireset) begin if ireset='0' then -- Reset ramre_int <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then -- Clock enable case ramre_int is when '0' => if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and ramadr_reg_in(15 downto 12)/=const_ram_to_io_c and ramadr_reg_in(15 downto 5)/=const_ram_to_reg and (idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or -- LD/LDD instruction idc_lds or -- LDS instruction(two cycle execution) idc_pop or -- POP instruction idc_ret or -- RET instruction idc_reti)='1') -- RETI instruction then ramre_int <='1'; end if; when '1' => if ((ld_st or lds_st or pop_st or ret_st2 or reti_st2)and not cpuwait)='1' then ramre_int <='0'; end if; when others => null; end case; end if; end if; end process; -- ramwe LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS)) --ramwe_int <= not(reg_file_adr_space or io_file_adr_space) and -- (st_st or sts_st2 or push_st or rcall_st1 or rcall_st2 or -- ST/STD/STS/PUSH/RCALL -- icall_st1 or icall_st2 or -- ICALL -- call_st2 or call_st3 or -- CALL -- irq_st2 or irq_st3); -- INTERRUPT DataMemoryWrite:process(cp2,ireset) begin if ireset='0' then -- Reset ramwe_int <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then -- Clock enable case ramwe_int is when '0' => if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and ramadr_reg_in(15 downto 12)/=const_ram_to_io_c and ramadr_reg_in(15 downto 5)/=const_ram_to_reg and (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or -- ST/STD instruction idc_sts or -- STS instruction (two cycle execution) idc_push or -- PUSH instruction idc_rcall or -- RCALL instruction idc_icall or -- ICALL instruction call_st1 or -- CALL instruction irq_st1)='1') -- Interrupt then ramwe_int <='1'; end if; when '1' => if ((st_st or sts_st or push_st or rcall_st2 or icall_st2 or call_st3 or irq_st3)and not cpuwait)='1' then ramwe_int <='0'; end if; when others => null; end case; end if; end if; end process; -- DBUSOUT MULTIPLEXER dbusout_mux_logic: for i in dbusout_int'range generate dbusout_int(i)<= (reg_rd_out(i) and (idc_push or idc_sts or (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS (gp_reg_tmp(i) and (st_st or sts_st))or -- NEW (bitpr_io_out(i) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS (program_counter(i) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC (program_counter_high_fr(i) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC (pc_for_interrupt(i) and irq_st1) or (pc_for_interrupt(i+8) and irq_st2) or (reg_rd_out(i) and idc_out); -- OUT end generate; -- ALU CONNECTION -- ALU Rr INPUT MUX alu_data_r_in <= dex_dat8_immed when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi)='1' else "00"&dex_dat6_immed when (idc_adiw or idc_sbiw) ='1' else "00000000" when (adiw_st or sbiw_st) ='1' else reg_rr_out; -- gp_reg_tmp STORES TEMPREOARY THE VALUE OF SOURCE REGISTER DURING ST/STD/STS INSTRUCTION gp_registers_trig:process(cp2,ireset) begin if (ireset='0') then gp_reg_tmp <= (others=>'0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable -- if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or sts_st1)='1' then -- CLOCK ENABLE if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or idc_sts)='1' then -- CLOCK ENABLE gp_reg_tmp <= reg_rd_out; end if; end if; end if; end process; -- ********************************************************************************************************** -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- +++++++++++++++++++++++++++++++++++++++ PROGRAM COUNTER ++++++++++++++++++++++++++++++++++++++++++++++++++ -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ program_counter_high_store:process(cp2,ireset) begin if ireset='0' then -- RESET program_counter_high_fr <=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if (idc_rcall or idc_icall or call_st1 or irq_st1) ='1' then program_counter_high_fr <= program_counter(15 downto 8); -- STORE HIGH BYTE OF THE PROGRAMM COUNTER FOR RCALL/ICALL/CALL INSTRUCTIONS AND INTERRUPTS end if; end if; end if; end process; program_counter_for_lpm_elpm:process(cp2,ireset) begin if ireset='0' then -- RESET program_counter_tmp<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if (idc_lpm or idc_elpm) ='1' then program_counter_tmp <= program_counter; end if; end if; end if; end process; pa15_pm <= rampz_out(0) and idc_elpm; -- '0' WHEN LPM INSTRUCTIONS RAMPZ(0) WHEN ELPM INSTRUCTION -- OFFSET FOR BRBC/BRBS INSTRUCTIONS +63/-64 offset_brbx <= "0000000000"&dex_brxx_offset(5 downto 0) when (dex_brxx_offset(6)='0') else -- + "1111111111"&dex_brxx_offset(5 downto 0); -- - -- OFFSET FOR RJMP/RCALL INSTRUCTIONS +2047/-2048 offset_rxx <= "00000"&dex_adr12mem_s(10 downto 0) when (dex_adr12mem_s(11)='0') else -- + "11111"&dex_adr12mem_s(10 downto 0); -- - program_counter <= pc_high&pc_low; program_counter_in <= program_counter + offset_brbx when ((idc_brbc or idc_brbs) and bit_test_op_out) ='1'else -- BRBC/BRBS program_counter + offset_rxx when (idc_rjmp or idc_rcall)='1'else -- RJMP/RCALL reg_z_out when (idc_ijmp or idc_icall)='1'else -- IJMP/ICALL pa15_pm&reg_z_out(15 downto 1) when (idc_lpm or idc_elpm) ='1'else -- LPM/ELPM instruction_reg when (jmp_st1 or call_st1)='1'else -- JMP/CALL "0000000000"&irqackad_int&'0' when irq_st1 ='1' else -- INTERRUPT dbusin&"00000000" when (ret_st1 or reti_st1)='1' else -- RET/RETI -> PC HIGH BYTE "00000000"&dbusin when (ret_st2 or reti_st2)='1' else -- RET/RETI -> PC LOW BYTE program_counter_tmp when (lpm_st1)='1' -- AFTER LPM/ELPM INSTRUCTION else program_counter+1; -- THE MOST USUAL CASE pc_low_en <= not (idc_ld_x or idc_ld_y or idc_ld_z or idc_ldd_y or idc_ldd_z or idc_st_x or idc_st_y or idc_st_z or idc_std_y or idc_std_z or ((sts_st or lds_st) and cpuwait)or idc_adiw or idc_sbiw or idc_push or idc_pop or idc_cbi or idc_sbi or rcall_st1 or icall_st1 or call_st2 or irq_st2 or cpuwait or ret_st1 or reti_st1); pc_high_en <= not (idc_ld_x or idc_ld_y or idc_ld_z or idc_ldd_y or idc_ldd_z or idc_st_x or idc_st_y or idc_st_z or idc_std_y or idc_std_z or ((sts_st or lds_st) and cpuwait) or idc_adiw or idc_sbiw or idc_push or idc_pop or idc_cbi or idc_sbi or rcall_st1 or icall_st1 or call_st2 or irq_st2 or cpuwait or ret_st2 or reti_st2); program_counter_low:process(cp2,ireset) begin if ireset='0' then -- RESET pc_low<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if pc_low_en ='1' then pc_low <= program_counter_in(7 downto 0); end if; end if; end if; end process; program_counter_high:process(cp2,ireset) begin if ireset='0' then -- RESET pc_high<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if pc_high_en ='1' then pc_high <= program_counter_in(15 downto 8); end if; end if; end if; end process; pc <= program_counter; program_counter_for_interrupt:process(cp2,ireset) begin if ireset='0' then -- RESET pc_for_interrupt <=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if irq_start ='1' then pc_for_interrupt <= program_counter; end if; end if; end if; end process; -- END OF PROGRAM COUNTER -- STATE MACHINES skip_inst_start <= ((idc_sbrc or idc_sbrs or idc_sbic or idc_sbis) and bit_test_op_out)or (idc_cpse and alu_z_flag_out); skip_instruction_sm:process(cp2,ireset) begin if ireset='0' then -- RESET nskip_inst_st0 <= '0'; skip_inst_st1 <= '0'; skip_inst_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nskip_inst_st0 <= (not nskip_inst_st0 and skip_inst_start) or (nskip_inst_st0 and not((skip_inst_st1 and not two_word_inst) or skip_inst_st2)); skip_inst_st1 <= (not skip_inst_st1 and not nskip_inst_st0 and skip_inst_start); skip_inst_st2 <= not skip_inst_st2 and skip_inst_st1 and two_word_inst; end if; end if; end process; alu_state_machines:process(cp2,ireset) begin if ireset='0' then -- RESET adiw_st <= '0'; sbiw_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable adiw_st <= not adiw_st and idc_adiw; sbiw_st <= not sbiw_st and idc_sbiw; end if; end if; end process; lpm_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nlpm_st0 <= '0'; lpm_st1 <= '0'; lpm_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nlpm_st0 <= (not nlpm_st0 and (idc_lpm or idc_elpm)) or (nlpm_st0 and not lpm_st2); lpm_st1 <= (not lpm_st1 and not nlpm_st0 and (idc_lpm or idc_elpm)); -- ?? lpm_st2 <= not lpm_st2 and lpm_st1; end if; end if; end process; lds_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET lds_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable lds_st <= (not lds_st and idc_lds) or (lds_st and cpuwait); end if; end if; end process; sts_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET sts_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable sts_st <= (not sts_st and idc_sts) or (sts_st and cpuwait); end if; end if; end process; jmp_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET njmp_st0 <= '0'; jmp_st1 <= '0'; jmp_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable njmp_st0 <= (not njmp_st0 and idc_jmp) or (njmp_st0 and not jmp_st2); jmp_st1 <= not jmp_st1 and not njmp_st0 and idc_jmp; -- ?? jmp_st2 <= not jmp_st2 and jmp_st1; end if; end if; end process; rcall_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nrcall_st0 <= '0'; rcall_st1 <= '0'; rcall_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nrcall_st0 <= (not nrcall_st0 and idc_rcall) or (nrcall_st0 and not (rcall_st2 and not cpuwait)); rcall_st1 <= (not rcall_st1 and not nrcall_st0 and idc_rcall) or (rcall_st1 and cpuwait); rcall_st2 <= (not rcall_st2 and rcall_st1 and not cpuwait) or (rcall_st2 and cpuwait); end if; end if; end process; icall_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nicall_st0 <= '0'; icall_st1 <= '0'; icall_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nicall_st0 <= (not nicall_st0 and idc_icall) or (nicall_st0 and not (icall_st2 and not cpuwait)); icall_st1 <= (not icall_st1 and not nicall_st0 and idc_icall) or (icall_st1 and cpuwait); icall_st2 <= (not icall_st2 and icall_st1 and not cpuwait) or (icall_st2 and cpuwait); end if; end if; end process; call_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET ncall_st0 <= '0'; call_st1 <= '0'; call_st2 <= '0'; call_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable ncall_st0 <= (not ncall_st0 and idc_call) or (ncall_st0 and not( call_st3 and not cpuwait)); call_st1 <= not call_st1 and not ncall_st0 and idc_call; call_st2 <= (not call_st2 and call_st1) or (call_st2 and cpuwait); call_st3 <= (not call_st3 and call_st2 and not cpuwait) or (call_st3 and cpuwait); end if; end if; end process; ret_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nret_st0 <= '0'; ret_st1 <= '0'; ret_st2 <= '0'; ret_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nret_st0 <= (not nret_st0 and idc_ret) or (nret_st0 and not ret_st3); ret_st1 <= (not ret_st1 and not nret_st0 and idc_ret) or (ret_st1 and cpuwait); ret_st2 <= (not ret_st2 and ret_st1 and not cpuwait) or (ret_st2 and cpuwait) ; ret_st3 <= not ret_st3 and ret_st2 and not cpuwait; end if; end if; end process; reti_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nreti_st0 <= '0'; reti_st1 <= '0'; reti_st2 <= '0'; reti_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nreti_st0 <= (not nreti_st0 and idc_reti) or (nreti_st0 and not reti_st3); reti_st1 <= (not reti_st1 and not nreti_st0 and idc_reti) or (reti_st1 and cpuwait); reti_st2 <= (not reti_st2 and reti_st1 and not cpuwait) or (reti_st2 and cpuwait) ; reti_st3 <= not reti_st3 and reti_st2 and not cpuwait; end if; end if; end process; -- INTERRUPT LOGIC AND STATE MACHINE irq_int <= '0' when irqlines="00000000000000000000000" else '1'; irq_vector_adr(15 downto 6)<=(others => '0'); irq_vector_adr(0) <= '0'; -- PRIORITY ENCODER irq_vector_adr(5 downto 1) <= "00001" when irqlines(0)='1' else -- 0x0002 "00010" when irqlines(1)='1' else -- 0x0004 "00011" when irqlines(2)='1' else -- 0x0006 "00100" when irqlines(3)='1' else -- 0x0008 "00101" when irqlines(4)='1' else -- 0x000A "00110" when irqlines(5)='1' else -- 0x000C "00111" when irqlines(6)='1' else -- 0x000E "01000" when irqlines(7)='1' else -- 0x0010 "01001" when irqlines(8)='1' else -- 0x0012 "01010" when irqlines(9)='1' else -- 0x0014 "01011" when irqlines(10)='1' else -- 0x0016 "01100" when irqlines(11)='1' else -- 0x0018 "01101" when irqlines(12)='1' else -- 0x001A "01110" when irqlines(13)='1' else -- 0x001C "01111" when irqlines(14)='1' else -- 0x001E "10000" when irqlines(15)='1' else -- 0x0020 "10001" when irqlines(16)='1' else -- 0x0022 "10010" when irqlines(17)='1' else -- 0x0024 "10011" when irqlines(18)='1' else -- 0x0026 "10100" when irqlines(19)='1' else -- 0x0028 "10101" when irqlines(20)='1' else -- 0x002A "10110" when irqlines(21)='1' else -- 0x002C "10111" when irqlines(22)='1' else -- 0x002E "00000"; -- MULTI CYCLE INSTRUCTION FLAG FOR IRQ cpu_busy <= idc_adiw or idc_sbiw or idc_cbi or idc_sbi or idc_rjmp or idc_ijmp or idc_jmp or jmp_st1 or -- idc_brbs or idc_brbc or -- Old variant ((idc_brbc or idc_brbs) and bit_test_op_out) or idc_lpm or lpm_st1 or skip_inst_start or (skip_inst_st1 and two_word_inst) or idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or (ld_st and cpuwait) or idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or (st_st and cpuwait) or idc_lds or (lds_st and cpuwait) or idc_sts or (sts_st and cpuwait) or idc_rcall or rcall_st1 or (rcall_st2 and cpuwait) or -- RCALL idc_icall or icall_st1 or (icall_st2 and cpuwait) or -- ICALL idc_call or call_st1 or call_st2 or (call_st3 and cpuwait) or -- CALL idc_push or (push_st and cpuwait) or -- PUSH (added 14.07.05) idc_pop or (pop_st and cpuwait) or -- POP (added 14.07.05) (idc_bclr and sreg_bop_wr_en(7)) or -- ??? CLI (iowe_int and sreg_adr_eq and not dbusout_int(7))or -- ??? Writing '0' to I flag (OUT/STD/ST/STD) nirq_st0 or -- idc_ret or nret_st0 or -- Old variant idc_ret or ret_st1 or ret_st2 or -- idc_reti or nreti_st0; -- At least one instruction must be executed after RETI and before the new interrupt. idc_reti or reti_st1 or reti_st2; sreg_adr_eq <= '1' when adr_int=SREG_Address else '0'; --irq_start <= irq_int and not cpu_busy and globint; irq_start <= irq_int and not cpu_busy and globint; irq_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nirq_st0 <= '0'; irq_st1 <= '0'; irq_st2 <= '0'; irq_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nirq_st0 <= (not nirq_st0 and irq_start) or (nirq_st0 and not (irq_st3 and not cpuwait)); irq_st1 <= (not irq_st1 and not nirq_st0 and irq_start); irq_st2 <= (not irq_st2 and irq_st1) or (irq_st2 and cpuwait); irq_st3 <= (not irq_st3 and irq_st2 and not cpuwait) or (irq_st3 and cpuwait); end if; end if; end process; irqack_reg:process(cp2,ireset) begin if ireset='0' then -- RESET irqack_int<='0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable irqack_int<= not irqack_int and irq_start; end if; end if; end process; irqack <= irqack_int; irqackad_reg:process(cp2,ireset) begin if ireset='0' then -- RESET irqackad_int<=(others=>'0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable irqackad_int<=irq_vector_adr(5 downto 1); end if; end if; end process; irqackad <= irqackad_int; -- ******************************************************************************************* rjmp_push_pop_ijmp_state_brxx_machine:process(cp2,ireset) begin if ireset='0' then -- RESET rjmp_st <= '0'; ijmp_st <= '0'; push_st <= '0'; pop_st <= '0'; brxx_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable rjmp_st <= idc_rjmp; -- ?? ijmp_st <= idc_ijmp; push_st <= (not push_st and idc_push) or (push_st and cpuwait); pop_st <= (not pop_st and idc_pop) or (pop_st and cpuwait); brxx_st <= not brxx_st and (idc_brbc or idc_brbs) and bit_test_op_out; end if; end if; end process; -- LD/LDD/ST/STD ld_st_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET ld_st <= '0'; st_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable ld_st <= (not ld_st and (idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z)) or (ld_st and cpuwait); st_st <= (not st_st and (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)) or (st_st and cpuwait); end if; end if; end process; -- SBI/CBI sbi_cbi_machine:process(cp2,ireset) begin if ireset='0' then -- RESET sbi_st <= '0'; cbi_st <= '0'; cbi_sbi_io_adr_tmp <= (others => '0'); cbi_sbi_bit_num_tmp <= (others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable sbi_st <= not sbi_st and idc_sbi; cbi_st <= not cbi_st and idc_cbi; cbi_sbi_io_adr_tmp <= dex_adr5port; cbi_sbi_bit_num_tmp <= dex_bitop_bitnum; end if; end if; end process; -- ######################################################################################## -- SREG FLAGS WRITE ENABLE LOGIC bclr_bset_op_en_logic:for i in sreg_bop_wr_en'range generate sreg_bop_wr_en(i) <= '1' when (dex_bitnum_sreg=i and (idc_bclr or idc_bset)='1') else '0'; end generate; sreg_c_wr_en <= idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_com or idc_neg or idc_cp or idc_cpc or idc_cpi or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(0); sreg_z_wr_en <= idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(1); sreg_n_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or sbiw_st or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(2); sreg_v_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or -- idc_adiw idc_sbc or idc_sbci or sbiw_st or idc_neg or idc_com or -- idc_sbiw idc_inc or idc_dec or idc_cp or idc_cpc or idc_cpi or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(3) or idc_and or idc_andi or idc_or or idc_ori or idc_eor; -- V-flag bug fixing sreg_s_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or sbiw_st or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(4); sreg_h_wr_en <= idc_add or idc_adc or idc_sub or idc_subi or idc_cp or idc_cpc or idc_cpi or idc_sbc or idc_sbci or idc_neg or sreg_bop_wr_en(5); sreg_t_wr_en <= idc_bst or sreg_bop_wr_en(6); sreg_i_wr_en <= irq_st1 or reti_st3 or sreg_bop_wr_en(7); -- WAS "irq_start" sreg_fl_in <= bit_pr_sreg_out when (idc_bst or idc_bclr or idc_bset)='1' else -- TO THE SREG reti_st3&'0'&alu_h_flag_out&alu_s_flag_out&alu_v_flag_out&alu_n_flag_out&alu_z_flag_out&alu_c_flag_out; -- ################################################################################################################# -- ********************************************************************************************* -- ************** INSTRUCTION DECODER OUTPUTS FOR THE OTHER BLOCKS **************************** -- ********************************************************************************************* -- FOR ALU idc_add_out <= idc_add; idc_adc_out <= idc_adc; idc_adiw_out <= idc_adiw; idc_sub_out <= idc_sub; idc_subi_out <= idc_subi; idc_sbc_out <= idc_sbc; idc_sbci_out <= idc_sbci; idc_sbiw_out <= idc_sbiw; adiw_st_out <= adiw_st; sbiw_st_out <= sbiw_st; idc_and_out <= idc_and; idc_andi_out <= idc_andi; idc_or_out <= idc_or; idc_ori_out <= idc_ori; idc_eor_out <= idc_eor; idc_com_out <= idc_com; idc_neg_out <= idc_neg; idc_inc_out <= idc_inc; idc_dec_out <= idc_dec; idc_cp_out <= idc_cp; idc_cpc_out <= idc_cpc; idc_cpi_out <= idc_cpi; idc_cpse_out <= idc_cpse; idc_lsr_out <= idc_lsr; idc_ror_out <= idc_ror; idc_asr_out <= idc_asr; idc_swap_out <= idc_swap; -- FOR THE BIT PROCESSOR sbi_st_out <= sbi_st; cbi_st_out <= cbi_st; idc_bst_out <= idc_bst; idc_bset_out <= idc_bset; idc_bclr_out <= idc_bclr; idc_sbic_out <= idc_sbic; idc_sbis_out <= idc_sbis; idc_sbrs_out <= idc_sbrs; idc_sbrc_out <= idc_sbrc; idc_brbs_out <= idc_brbs; idc_brbc_out <= idc_brbc; idc_reti_out <= idc_reti; -- POST INCREMENT/PRE DECREMENT FOR THE X,Y,Z REGISTERS post_inc <= idc_psinc; pre_dec <= idc_prdec; reg_h_wr <= (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z) and (idc_psinc or idc_prdec); reg_h_adr(0)<= idc_st_x or idc_ld_x; reg_h_adr(1)<= idc_st_y or idc_std_y or idc_ld_y or idc_ldd_y; reg_h_adr(2)<= idc_st_z or idc_std_z or idc_ld_z or idc_ldd_z; -- STACK POINTER CONTROL sp_ndown_up <= idc_pop or idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait); -- ????????? sp_en <= idc_push or idc_pop or idc_rcall or (rcall_st1 and not cpuwait) or idc_icall or (icall_st1 and not cpuwait) or idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait) or call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait); --???????? branch <= dex_condition; bit_num_r_io <= cbi_sbi_bit_num_tmp when (cbi_st or sbi_st)='1' else dex_bitop_bitnum; adr <= adr_int; ramre <= ramre_int; ramwe <= ramwe_int; iore <= iore_int; iowe <= iowe_int; dbusout <= dbusout_int; -- Sleep Control sleepi <= idc_sleep; irqok <= irq_int; -- Watchdog wdri <= idc_wdr; -- ************************** JTAG OCD support ************************************ -- Change of flow change_flow <= '0'; valid_instr <= '0'; end RTL;
entity const4 is end entity; architecture test of const4 is type int2d is array (natural range <>, natural range <>) of integer; constant c : int2d := ( ( 0, 3, 4, 5 ), ( 6, 7, 8, 9 ) ); begin process is begin assert c'length(1) = 2; assert c'length(2) = 4; assert c(0, 0) = 0; assert c(0, 1) = 3; assert c(0, 3) = 5; assert c(1, 0) = 6; assert c(1, 1) = 7; assert c(1, 2) = 8; wait; end process; end architecture;
entity const4 is end entity; architecture test of const4 is type int2d is array (natural range <>, natural range <>) of integer; constant c : int2d := ( ( 0, 3, 4, 5 ), ( 6, 7, 8, 9 ) ); begin process is begin assert c'length(1) = 2; assert c'length(2) = 4; assert c(0, 0) = 0; assert c(0, 1) = 3; assert c(0, 3) = 5; assert c(1, 0) = 6; assert c(1, 1) = 7; assert c(1, 2) = 8; wait; end process; end architecture;
entity const4 is end entity; architecture test of const4 is type int2d is array (natural range <>, natural range <>) of integer; constant c : int2d := ( ( 0, 3, 4, 5 ), ( 6, 7, 8, 9 ) ); begin process is begin assert c'length(1) = 2; assert c'length(2) = 4; assert c(0, 0) = 0; assert c(0, 1) = 3; assert c(0, 3) = 5; assert c(1, 0) = 6; assert c(1, 1) = 7; assert c(1, 2) = 8; wait; end process; end architecture;
entity const4 is end entity; architecture test of const4 is type int2d is array (natural range <>, natural range <>) of integer; constant c : int2d := ( ( 0, 3, 4, 5 ), ( 6, 7, 8, 9 ) ); begin process is begin assert c'length(1) = 2; assert c'length(2) = 4; assert c(0, 0) = 0; assert c(0, 1) = 3; assert c(0, 3) = 5; assert c(1, 0) = 6; assert c(1, 1) = 7; assert c(1, 2) = 8; wait; end process; end architecture;
entity const4 is end entity; architecture test of const4 is type int2d is array (natural range <>, natural range <>) of integer; constant c : int2d := ( ( 0, 3, 4, 5 ), ( 6, 7, 8, 9 ) ); begin process is begin assert c'length(1) = 2; assert c'length(2) = 4; assert c(0, 0) = 0; assert c(0, 1) = 3; assert c(0, 3) = 5; assert c(1, 0) = 6; assert c(1, 1) = 7; assert c(1, 2) = 8; wait; end process; end architecture;
-- VHDL Entity R6502_TC.Reg_SP.symbol -- -- Created: -- by - eda.UNKNOWN (ENTWICKL4-XP-PR) -- at - 22:42:53 04.01.2009 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity Reg_SP is port( adr_low_i : in std_logic_vector (7 downto 0); clk_clk_i : in std_logic; ld_low_i : in std_logic; ld_sp_i : in std_logic; rst_rst_n_i : in std_logic; sel_sp_as_i : in std_logic; sel_sp_in_i : in std_logic; adr_sp_o : out std_logic_vector (15 downto 0) ); -- Declarations end Reg_SP ; -- Jens-D. Gutschmidt Project: R6502_TC -- scantara2003@yahoo.de -- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG -- -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or any later version. -- -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- CVS Revisins History -- -- $Log: not supported by cvs2svn $ -- <<-- more -->> -- Title: Stack Pointer Logic -- Path: R6502_TC/Reg_SP/struct -- Edited: by eda on 01 Jan 2009 -- -- VHDL Architecture R6502_TC.Reg_SP.struct -- -- Created: -- by - eda.UNKNOWN (ENTWICKL4-XP-PR) -- at - 22:42:53 04.01.2009 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; architecture struct of Reg_SP is -- Architecture declarations -- Internal signal declarations signal adr_sp_low_o_i : std_logic_vector(7 downto 0); signal load_o_i : std_logic; signal result_low1_o_i : std_logic_vector(7 downto 0); signal result_low_o_i : std_logic_vector(7 downto 0); signal sp_as_n_o_i : std_logic; signal val_one : std_logic_vector(7 downto 0); -- Implicit buffer signal declarations signal adr_sp_o_internal : std_logic_vector (15 downto 0); -- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'addsub' signal mw_U_11temp_din0 : std_logic_vector(8 downto 0); signal mw_U_11temp_din1 : std_logic_vector(8 downto 0); signal mw_U_11sum : unsigned(8 downto 0); -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff' signal mw_U_0reg_cval : std_logic_vector(7 downto 0); begin -- ModuleWare code(v1.9) for instance 'U_11' of 'addsub' mw_U_11temp_din0 <= '0' & adr_sp_low_o_i; mw_U_11temp_din1 <= '0' & val_one; u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1, sp_as_n_o_i) variable temp_carry : std_logic; begin temp_carry := '0'; if (sp_as_n_o_i = '1') then mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry; else mw_U_11sum <= unsigned(mw_U_11temp_din0) - unsigned(mw_U_11temp_din1) - temp_carry; end if; end process u_11combo_proc; result_low_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8); -- ModuleWare code(v1.9) for instance 'U_0' of 'adff' adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; u_0seq_proc: process (clk_clk_i, rst_rst_n_i) begin if (rst_rst_n_i = '0') then mw_U_0reg_cval <= "00000000"; elsif (clk_clk_i'event and clk_clk_i='1') then if (load_o_i = '1') then mw_U_0reg_cval <= result_low1_o_i; end if; end if; end process u_0seq_proc; -- ModuleWare code(v1.9) for instance 'U_6' of 'and' load_o_i <= ld_sp_i and ld_low_i; -- ModuleWare code(v1.9) for instance 'U_3' of 'buff' adr_sp_o_internal(15 DOWNTO 8) <= val_one; -- ModuleWare code(v1.9) for instance 'U_4' of 'constval' val_one <= "00000001"; -- ModuleWare code(v1.9) for instance 'U_2' of 'inv' sp_as_n_o_i <= not(sel_sp_as_i); -- ModuleWare code(v1.9) for instance 'U_8' of 'mux' u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i) begin case sel_sp_in_i is when '0' => result_low1_o_i <= result_low_o_i; when '1' => result_low1_o_i <= adr_low_i; when others => result_low1_o_i <= (others => 'X'); end case; end process u_8combo_proc; -- ModuleWare code(v1.9) for instance 'U_10' of 'tap' adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0); -- Instance port mappings. -- Implicit buffered output assignments adr_sp_o <= adr_sp_o_internal; end struct;
-- VHDL Entity R6502_TC.Reg_SP.symbol -- -- Created: -- by - eda.UNKNOWN (ENTWICKL4-XP-PR) -- at - 22:42:53 04.01.2009 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity Reg_SP is port( adr_low_i : in std_logic_vector (7 downto 0); clk_clk_i : in std_logic; ld_low_i : in std_logic; ld_sp_i : in std_logic; rst_rst_n_i : in std_logic; sel_sp_as_i : in std_logic; sel_sp_in_i : in std_logic; adr_sp_o : out std_logic_vector (15 downto 0) ); -- Declarations end Reg_SP ; -- Jens-D. Gutschmidt Project: R6502_TC -- scantara2003@yahoo.de -- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG -- -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or any later version. -- -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- CVS Revisins History -- -- $Log: not supported by cvs2svn $ -- <<-- more -->> -- Title: Stack Pointer Logic -- Path: R6502_TC/Reg_SP/struct -- Edited: by eda on 01 Jan 2009 -- -- VHDL Architecture R6502_TC.Reg_SP.struct -- -- Created: -- by - eda.UNKNOWN (ENTWICKL4-XP-PR) -- at - 22:42:53 04.01.2009 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; architecture struct of Reg_SP is -- Architecture declarations -- Internal signal declarations signal adr_sp_low_o_i : std_logic_vector(7 downto 0); signal load_o_i : std_logic; signal result_low1_o_i : std_logic_vector(7 downto 0); signal result_low_o_i : std_logic_vector(7 downto 0); signal sp_as_n_o_i : std_logic; signal val_one : std_logic_vector(7 downto 0); -- Implicit buffer signal declarations signal adr_sp_o_internal : std_logic_vector (15 downto 0); -- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'addsub' signal mw_U_11temp_din0 : std_logic_vector(8 downto 0); signal mw_U_11temp_din1 : std_logic_vector(8 downto 0); signal mw_U_11sum : unsigned(8 downto 0); -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff' signal mw_U_0reg_cval : std_logic_vector(7 downto 0); begin -- ModuleWare code(v1.9) for instance 'U_11' of 'addsub' mw_U_11temp_din0 <= '0' & adr_sp_low_o_i; mw_U_11temp_din1 <= '0' & val_one; u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1, sp_as_n_o_i) variable temp_carry : std_logic; begin temp_carry := '0'; if (sp_as_n_o_i = '1') then mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry; else mw_U_11sum <= unsigned(mw_U_11temp_din0) - unsigned(mw_U_11temp_din1) - temp_carry; end if; end process u_11combo_proc; result_low_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8); -- ModuleWare code(v1.9) for instance 'U_0' of 'adff' adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; u_0seq_proc: process (clk_clk_i, rst_rst_n_i) begin if (rst_rst_n_i = '0') then mw_U_0reg_cval <= "00000000"; elsif (clk_clk_i'event and clk_clk_i='1') then if (load_o_i = '1') then mw_U_0reg_cval <= result_low1_o_i; end if; end if; end process u_0seq_proc; -- ModuleWare code(v1.9) for instance 'U_6' of 'and' load_o_i <= ld_sp_i and ld_low_i; -- ModuleWare code(v1.9) for instance 'U_3' of 'buff' adr_sp_o_internal(15 DOWNTO 8) <= val_one; -- ModuleWare code(v1.9) for instance 'U_4' of 'constval' val_one <= "00000001"; -- ModuleWare code(v1.9) for instance 'U_2' of 'inv' sp_as_n_o_i <= not(sel_sp_as_i); -- ModuleWare code(v1.9) for instance 'U_8' of 'mux' u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i) begin case sel_sp_in_i is when '0' => result_low1_o_i <= result_low_o_i; when '1' => result_low1_o_i <= adr_low_i; when others => result_low1_o_i <= (others => 'X'); end case; end process u_8combo_proc; -- ModuleWare code(v1.9) for instance 'U_10' of 'tap' adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0); -- Instance port mappings. -- Implicit buffered output assignments adr_sp_o <= adr_sp_o_internal; end struct;
library verilog; use verilog.vl_types.all; entity inicial is generic( A : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0); B : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi1); C : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi0); D : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi1); E : vl_logic_vector(0 to 2) := (Hi1, Hi0, Hi0) ); port( giro : in vl_logic; entrada : in vl_logic; saida : in vl_logic; metais : in vl_logic; ledVerde : out vl_logic_vector(1 downto 0); ledVermelho : out vl_logic_vector(1 downto 0); display : out vl_logic_vector(6 downto 0); clock : in vl_logic ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of A : constant is 1; attribute mti_svvh_generic_type of B : constant is 1; attribute mti_svvh_generic_type of C : constant is 1; attribute mti_svvh_generic_type of D : constant is 1; attribute mti_svvh_generic_type of E : constant is 1; end inicial;
------------------------------------------------------------------------------- -- uartlite_tx - entity/architecture pair ------------------------------------------------------------------------------- -- -- ******************************************************************* -- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.* -- -- ** * -- -- ** This file contains confidential and proprietary information * -- -- ** of Xilinx, Inc. and is protected under U.S. and * -- -- ** international copyright and other intellectual property * -- -- ** laws. * -- -- ** * -- -- ** DISCLAIMER * -- -- ** This disclaimer is not a license and does not grant any * -- -- ** rights to the materials distributed herewith. Except as * -- -- ** otherwise provided in a valid license issued to you by * -- -- ** Xilinx, and to the maximum extent permitted by applicable * -- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * -- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * -- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * -- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * -- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * -- -- ** (2) Xilinx shall not be liable (whether in contract or tort, * -- -- ** including negligence, or under any other theory of * -- -- ** liability) for any loss or damage of any kind or nature * -- -- ** related to, arising under or in connection with these * -- -- ** materials, including for any direct, or any indirect, * -- -- ** special, incidental, or consequential loss or damage * -- -- ** (including loss of data, profits, goodwill, or any type of * -- -- ** loss or damage suffered as a result of any action brought * -- -- ** by a third party) even if such damage or loss was * -- -- ** reasonably foreseeable or Xilinx had been advised of the * -- -- ** possibility of the same. * -- -- ** * -- -- ** CRITICAL APPLICATIONS * -- -- ** Xilinx products are not designed or intended to be fail- * -- -- ** safe, or for use in any application requiring fail-safe * -- -- ** performance, such as life-support or safety devices or * -- -- ** systems, Class III medical devices, nuclear facilities, * -- -- ** applications related to the deployment of airbags, or any * -- -- ** other applications that could lead to death, personal * -- -- ** injury, or severe property or environmental damage * -- -- ** (individually and collectively, "Critical * -- -- ** Applications"). Customer assumes the sole risk and * -- -- ** liability of any use of Xilinx products in Critical * -- -- ** Applications, subject only to applicable laws and * -- -- ** regulations governing limitations on product liability. * -- -- ** * -- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * -- -- ** PART OF THIS FILE AT ALL TIMES. * -- ******************************************************************* -- ------------------------------------------------------------------------------- -- Filename: uartlite_tx.vhd -- Version: v2.0 -- Description: UART Lite Transmit Interface Module -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.UNSIGNED; use IEEE.numeric_std.to_unsigned; use IEEE.numeric_std."-"; library lib_srl_fifo_v1_0_2; -- dynshreg_i_f refered from proc_common_v4_0_20_a library axi_uartlite_v2_0_10; -- uartlite_core refered from axi_uartlite_v2_0_10 use axi_uartlite_v2_0_10.all; -- srl_fifo_f refered from proc_common_v4_0_20_a use lib_srl_fifo_v1_0_2.srl_fifo_f; ------------------------------------------------------------------------------- -- Port Declaration ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Generics : ------------------------------------------------------------------------------- -- UART Lite generics -- C_DATA_BITS -- The number of data bits in the serial frame -- C_USE_PARITY -- Determines whether parity is used or not -- C_ODD_PARITY -- If parity is used determines whether parity -- is even or odd -- System generics -- C_FAMILY -- Xilinx FPGA Family ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Ports : ------------------------------------------------------------------------------- -- System Signals -- Clk -- Clock signal -- Rst -- Reset signal -- UART Lite interface -- TX -- Transmit Data -- Internal UART interface signals -- EN_16x_Baud -- Enable signal which is 16x times baud rate -- Write_TX_FIFO -- Write transmit FIFO -- Reset_TX_FIFO -- Reset transmit FIFO -- TX_Data -- Transmit data input -- TX_Buffer_Full -- Transmit buffer full -- TX_Buffer_Empty -- Transmit buffer empty ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Entity Section ------------------------------------------------------------------------------- entity uartlite_tx is generic ( C_FAMILY : string := "virtex7"; C_DATA_BITS : integer range 5 to 8 := 8; C_USE_PARITY : integer range 0 to 1 := 0; C_ODD_PARITY : integer range 0 to 1 := 0 ); port ( Clk : in std_logic; Reset : in std_logic; EN_16x_Baud : in std_logic; TX : out std_logic; Write_TX_FIFO : in std_logic; Reset_TX_FIFO : in std_logic; TX_Data : in std_logic_vector(0 to C_DATA_BITS-1); TX_Buffer_Full : out std_logic; TX_Buffer_Empty : out std_logic ); end entity uartlite_tx; ------------------------------------------------------------------------------- -- Architecture Section ------------------------------------------------------------------------------- architecture RTL of uartlite_tx is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes"; type bo2sl_type is array(boolean) of std_logic; constant bo2sl : bo2sl_type := (false => '0', true => '1'); ------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------- constant MUX_SEL_INIT : std_logic_vector(0 to 2) := std_logic_vector(to_unsigned(C_DATA_BITS-1, 3)); ------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------- signal parity : std_logic; signal tx_Run1 : std_logic; signal select_Parity : std_logic; signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1); signal div16 : std_logic; signal tx_Data_Enable : std_logic; signal tx_Start : std_logic; signal tx_DataBits : std_logic; signal tx_Run : std_logic; signal mux_sel : std_logic_vector(0 to 2); signal mux_sel_is_zero : std_logic; signal mux_01 : std_logic; signal mux_23 : std_logic; signal mux_45 : std_logic; signal mux_67 : std_logic; signal mux_0123 : std_logic; signal mux_4567 : std_logic; signal mux_Out : std_logic; signal serial_Data : std_logic; signal fifo_Read : std_logic; signal fifo_Data_Present : std_logic := '0'; signal fifo_Data_Empty : std_logic; signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1); signal fifo_wr : std_logic; signal fifo_rd : std_logic; signal tx_buffer_full_i : std_logic; signal TX_FIFO_Reset : std_logic; begin -- architecture IMP --------------------------------------------------------------------------- --MID_START_BIT_SRL16_I : Shift register is used to generate div16 that -- gets shifted for 16 times(as Addr = 15) when -- EN_16x_Baud is high. --------------------------------------------------------------------------- MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0_10.dynshreg_i_f generic map ( C_DEPTH => 16, C_DWIDTH => 1, C_INIT_VALUE => X"8000", C_FAMILY => C_FAMILY ) port map ( Clk => Clk, Clken => EN_16x_Baud, Addr => "1111", Din(0) => div16, Dout(0) => div16 ); ------------------------------------------------------------------------ -- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and -- EN_16x_Baud is 1. It will deasserted in the -- next clock cycle. ------------------------------------------------------------------------ TX_DATA_ENABLE_DFF: Process (Clk) is begin if (Clk'event and Clk = '1') then -- rising clock edge if Reset = '1' then -- synchronous reset (active high) tx_Data_Enable <= '0'; else if (tx_Data_Enable = '1') then tx_Data_Enable <= '0'; elsif (EN_16x_Baud = '1') then tx_Data_Enable <= div16; end if; end if; end if; end process TX_DATA_ENABLE_DFF; ------------------------------------------------------------------------ -- TX_START_DFF : tx_start is '1' for the start bit in a transmission ------------------------------------------------------------------------ TX_START_DFF : process (Clk) is begin if Clk'event and Clk = '1' then -- rising clock edge if Reset = '1' then -- synchronous reset (active high) tx_Start <= '0'; else tx_Start <= (not(tx_Run) and (tx_Start or (fifo_Data_Present and tx_Data_Enable))); end if; end if; end process TX_START_DFF; -------------------------------------------------------------------------- -- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission -------------------------------------------------------------------------- TX_DATA_DFF : process (Clk) is begin if Clk'event and Clk = '1' then -- rising clock edge if Reset = '1' then -- synchronous reset (active high) tx_DataBits <= '0'; else tx_DataBits <= (not(fifo_Read) and (tx_DataBits or (tx_Start and tx_Data_Enable))); end if; end if; end process TX_DATA_DFF; ------------------------------------------------------------------------- -- COUNTER : If mux_sel is zero then reload with the init value else if -- tx_DataBits = '1', decrement ------------------------------------------------------------------------- COUNTER : process (Clk) is begin -- process Mux_Addr_DFF if Clk'event and Clk = '1' then -- rising clock edge if Reset = '1' then -- synchronous reset (active high) mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1, mux_sel'length)); elsif (tx_Data_Enable = '1') then if (mux_sel_is_zero = '1') then mux_sel <= MUX_SEL_INIT; elsif (tx_DataBits = '1') then mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1); end if; end if; end if; end process COUNTER; ------------------------------------------------------------------------ -- Detecting when mux_sel is zero, i.e. all data bits are transfered ------------------------------------------------------------------------ mux_sel_is_zero <= '1' when mux_sel = "000" else '0'; -------------------------------------------------------------------------- -- FIFO_READ_DFF : Read out the next data from the transmit fifo when the -- data has been transmitted -------------------------------------------------------------------------- FIFO_READ_DFF : process (Clk) is begin -- process FIFO_Read_DFF if Clk'event and Clk = '1' then -- rising clock edge if Reset = '1' then -- synchronous reset (active high) fifo_Read <= '0'; else fifo_Read <= tx_Data_Enable and mux_sel_is_zero; end if; end if; end process FIFO_READ_DFF; -------------------------------------------------------------------------- -- Select which bit within the data word to transmit -------------------------------------------------------------------------- -------------------------------------------------------------------------- -- PARITY_BIT_INSERTION : Need special treatment for inserting the parity -- bit because of parity generation -------------------------------------------------------------------------- data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2); data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else fifo_DOut(C_DATA_BITS-1); mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else data_to_transfer(0); mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else data_to_transfer(2); -------------------------------------------------------------------------- -- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5 -------------------------------------------------------------------------- DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate mux_45 <= data_to_transfer(4); mux_67 <= '0'; end generate DATA_BITS_IS_5; -------------------------------------------------------------------------- -- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6 -------------------------------------------------------------------------- DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else data_to_transfer(4); mux_67 <= '0'; end generate DATA_BITS_IS_6; -------------------------------------------------------------------------- -- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7 -------------------------------------------------------------------------- DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else data_to_transfer(4); mux_67 <= data_to_transfer(6); end generate DATA_BITS_IS_7; -------------------------------------------------------------------------- -- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8 -------------------------------------------------------------------------- DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else data_to_transfer(4); mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else data_to_transfer(6); end generate DATA_BITS_IS_8; mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01; mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45; mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123; -------------------------------------------------------------------------- -- SERIAL_DATA_DFF : Register the mux_Out -------------------------------------------------------------------------- SERIAL_DATA_DFF : process (Clk) is begin if Clk'event and Clk = '1' then -- rising clock edge if Reset = '1' then -- synchronous reset (active high) serial_Data <= '0'; else serial_Data <= mux_Out; end if; end if; end process SERIAL_DATA_DFF; -------------------------------------------------------------------------- -- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit -- Force a '1' when tx_run is '0', Idle -- otherwise put out the serial_data -------------------------------------------------------------------------- SERIAL_OUT_DFF : process (Clk) is begin -- process Serial_Out_DFF if Clk'event and Clk = '1' then -- rising clock edge if Reset = '1' then -- synchronous reset (active high) TX <= '1'; else TX <= (not(tx_Run) or serial_Data) and (not(tx_Start)); end if; end if; end process SERIAL_OUT_DFF; -------------------------------------------------------------------------- -- USING_PARITY : Generate parity handling when C_USE_PARITY = 1 -------------------------------------------------------------------------- USING_PARITY : if (C_USE_PARITY = 1) generate PARITY_DFF: Process (Clk) is begin if (Clk'event and Clk = '1') then if (tx_Start = '1') then parity <= bo2sl(C_ODD_PARITY = 1); elsif (tx_Data_Enable = '1') then parity <= parity xor serial_Data; end if; end if; end process PARITY_DFF; TX_RUN1_DFF : process (Clk) is begin if Clk'event and Clk = '1' then -- rising clock edge if Reset = '1' then -- synchronous reset (active high) tx_Run1 <= '0'; elsif (tx_Data_Enable = '1') then tx_Run1 <= tx_DataBits; end if; end if; end process TX_RUN1_DFF; tx_Run <= tx_Run1 or tx_DataBits; SELECT_PARITY_DFF : process (Clk) is begin if Clk'event and Clk = '1' then -- rising clock edge if Reset = '1' then -- synchronous reset (active high) select_Parity <= '0'; elsif (tx_Data_Enable = '1') then select_Parity <= mux_sel_is_zero; end if; end if; end process SELECT_PARITY_DFF; end generate USING_PARITY; -------------------------------------------------------------------------- -- NO_PARITY : When C_USE_PARITY = 0 select parity as '0' -------------------------------------------------------------------------- NO_PARITY : if (C_USE_PARITY = 0) generate tx_Run <= tx_DataBits; select_Parity <= '0'; end generate NO_PARITY; -------------------------------------------------------------------------- -- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO -------------------------------------------------------------------------- fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i); -------------------------------------------------------------------------- -- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO -------------------------------------------------------------------------- fifo_rd <= fifo_Read and (not fifo_Data_Empty); -------------------------------------------------------------------------- -- Reset TX FIFO when requested from the control register or system reset -------------------------------------------------------------------------- TX_FIFO_Reset <= Reset_TX_FIFO or Reset; -------------------------------------------------------------------------- -- SRL_FIFO_I : Transmit FIFO Interface -------------------------------------------------------------------------- SRL_FIFO_I : entity lib_srl_fifo_v1_0_2.srl_fifo_f generic map ( C_DWIDTH => C_DATA_BITS, C_DEPTH => 16, C_FAMILY => C_FAMILY ) port map ( Clk => Clk, Reset => TX_FIFO_Reset, FIFO_Write => fifo_wr, Data_In => TX_Data, FIFO_Read => fifo_rd, Data_Out => fifo_DOut, FIFO_Full => tx_buffer_full_i, FIFO_Empty => fifo_Data_Empty ); TX_Buffer_Full <= tx_buffer_full_i; TX_Buffer_Empty <= fifo_Data_Empty; fifo_Data_Present <= not fifo_Data_Empty; end architecture RTL;
-- ------------------------------------------------------------- -- -- Entity Declaration for inst_m_e -- -- Generated -- by: wig -- on: Wed Nov 30 06:48:17 2005 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_m_e-e.vhd,v 1.2 2005/11/30 14:04:04 wig Exp $ -- $Date: 2005/11/30 14:04:04 $ -- $Log: inst_m_e-e.vhd,v $ -- Revision 1.2 2005/11/30 14:04:04 wig -- Updated testcase references -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.42 , wilfried.gaensheimer@micronas.com -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_m_e -- entity inst_m_e is -- Generics: generic( -- Generated Generics for Entity inst_m_e FOO : integer := 19 -- Generic generator -- End of Generated Generics for Entity inst_m_e ); -- Generated Port Declaration: -- No Generated Port for Entity inst_m_e end inst_m_e; -- -- End of Generated Entity inst_m_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity somadorSubtrator is Port ( a0 : in STD_LOGIC; a1 : in STD_LOGIC; a2 : in STD_LOGIC; b0 : in STD_LOGIC; b1 : in STD_LOGIC; b2 : in STD_LOGIC; sel : in STD_LOGIC; s0 : out STD_LOGIC; s1 : out STD_LOGIC; s2 : out STD_LOGIC; cout0 : out STD_LOGIC; cout1 : out STD_LOGIC; E : out STD_LOGIC); end somadorSubtrator; architecture Behavioral of somadorSubtrator is signal caux : std_logic; signal comp0 : std_logic; signal comp1 : std_logic; signal comp2 : std_logic; signal compdois0 : std_logic; signal compdois1 : std_logic; signal compdois2 : std_logic; begin process (a0,a1,a2,b0,b1,b2, sel) begin if (sel = '0') then --soma if (a2 = '0') and (b2 = '0') then s0 <= (a0 xor (b0 xor '0')); caux <= a0 and b0; s1 <= (a1 xor (b1 xor caux)); cout1 <= (a0 and b0) or (a0 and caux) or (b0 and caux); s2 <= a2; elsif (a2 = '1') then -- a é negativo comp0 = (a0 xor '1'); comp1 = (a1 xor '1'); comp2 = (a2 xor '1'); compdois0 <= (a0 xor '1'); caux <= a0 and '1'; compdois1 <= (a1 xor ('1' xor caux)); cout1 <= (a0 and '1') or (a0 and caux) or ('1' and caux); s2 <= a2; elsif (b2 = '1') then -- b é negativo end if; else --subtrai end if; end process; end Behavioral;
------------------------------------------------------------------------------- -- Title : Goertel Muxes ------------------------------------------------------------------------------- -- Author : strongly-typed -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Selects one data word, one coefficient and one input from the -- arrays of different channels/frequencies. Truely combinatorial. -- goertzel_pipeline has registers at its inputs. ------------------------------------------------------------------------------- -- Copyright (c) 2012 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.signalprocessing_pkg.all; entity goertzel_muxes is generic ( CHANNELS : positive := 12; FREQUENCIES : positive); port ( -- control pins of the muxes, from control unit mux_delay1_p : in std_logic; mux_delay2_p : in std_logic; mux_coef : in natural range FREQUENCIES-1 downto 0; mux_input : in natural range CHANNELS-1 downto 0; -- data to mux bram_data : in goertzel_result_type; coefs_p : in goertzel_coefs_type; inputs_p : in goertzel_inputs_type; -- outputs of the mux delay1_p : out goertzel_data_type; delay2_p : out goertzel_data_type; coef_p : out goertzel_coef_type; input_p : out goertzel_input_type); end entity goertzel_muxes; architecture behavourial of goertzel_muxes is begin -- architecture behavourial -- be able to blank the input. This is necessary at the beginning of a -- cycle. delay1_p <= bram_data(0) when (mux_delay1_p = '1') else (others => '0'); delay2_p <= bram_data(1) when (mux_delay2_p = '1') else (others => '0'); -- select one coefficient from all coefficients coef_p <= coefs_p(mux_coef); -- select one input from all inputs input_p <= inputs_p(mux_input); end architecture behavourial;
------------------------------------------------------------------------------- -- Title : Goertel Muxes ------------------------------------------------------------------------------- -- Author : strongly-typed -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Selects one data word, one coefficient and one input from the -- arrays of different channels/frequencies. Truely combinatorial. -- goertzel_pipeline has registers at its inputs. ------------------------------------------------------------------------------- -- Copyright (c) 2012 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.signalprocessing_pkg.all; entity goertzel_muxes is generic ( CHANNELS : positive := 12; FREQUENCIES : positive); port ( -- control pins of the muxes, from control unit mux_delay1_p : in std_logic; mux_delay2_p : in std_logic; mux_coef : in natural range FREQUENCIES-1 downto 0; mux_input : in natural range CHANNELS-1 downto 0; -- data to mux bram_data : in goertzel_result_type; coefs_p : in goertzel_coefs_type; inputs_p : in goertzel_inputs_type; -- outputs of the mux delay1_p : out goertzel_data_type; delay2_p : out goertzel_data_type; coef_p : out goertzel_coef_type; input_p : out goertzel_input_type); end entity goertzel_muxes; architecture behavourial of goertzel_muxes is begin -- architecture behavourial -- be able to blank the input. This is necessary at the beginning of a -- cycle. delay1_p <= bram_data(0) when (mux_delay1_p = '1') else (others => '0'); delay2_p <= bram_data(1) when (mux_delay2_p = '1') else (others => '0'); -- select one coefficient from all coefficients coef_p <= coefs_p(mux_coef); -- select one input from all inputs input_p <= inputs_p(mux_input); end architecture behavourial;
-- NEED RESULT: ARCH00337.P1: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P2: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P3: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P4: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P5: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P6: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P7: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P8: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P9: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P10: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P11: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P12: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P13: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P14: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P15: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P16: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337.P17: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: P17: Transport transactions completed entirely passed -- NEED RESULT: P16: Transport transactions completed entirely passed -- NEED RESULT: P15: Transport transactions completed entirely passed -- NEED RESULT: P14: Transport transactions completed entirely passed -- NEED RESULT: P13: Transport transactions completed entirely passed -- NEED RESULT: P12: Transport transactions completed entirely passed -- NEED RESULT: P11: Transport transactions completed entirely passed -- NEED RESULT: P10: Transport transactions completed entirely passed -- NEED RESULT: P9: Transport transactions completed entirely passed -- NEED RESULT: P8: Transport transactions completed entirely passed -- NEED RESULT: P7: Transport transactions completed entirely passed -- NEED RESULT: P6: Transport transactions completed entirely passed -- NEED RESULT: P5: Transport transactions completed entirely passed -- NEED RESULT: P4: Transport transactions completed entirely passed -- NEED RESULT: P3: Transport transactions completed entirely passed -- NEED RESULT: P2: Transport transactions completed entirely passed -- NEED RESULT: P1: Transport transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00337 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (2) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00337(ARCH00337) -- ENT00337_Test_Bench(ARCH00337_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00337 is end ENT00337 ; -- -- architecture ARCH00337 of ENT00337 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_boolean : chk_sig_type := -1 ; signal chk_bit : chk_sig_type := -1 ; signal chk_severity_level : chk_sig_type := -1 ; signal chk_character : chk_sig_type := -1 ; signal chk_st_enum1 : chk_sig_type := -1 ; signal chk_integer : chk_sig_type := -1 ; signal chk_st_int1 : chk_sig_type := -1 ; signal chk_time : chk_sig_type := -1 ; signal chk_st_phys1 : chk_sig_type := -1 ; signal chk_real : chk_sig_type := -1 ; signal chk_st_real1 : chk_sig_type := -1 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; signal chk_st_arr1 : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; signal chk_st_arr3 : chk_sig_type := -1 ; -- subtype chk_time_type is Time ; signal s_boolean_savt : chk_time_type := 0 ns ; signal s_bit_savt : chk_time_type := 0 ns ; signal s_severity_level_savt : chk_time_type := 0 ns ; signal s_character_savt : chk_time_type := 0 ns ; signal s_st_enum1_savt : chk_time_type := 0 ns ; signal s_integer_savt : chk_time_type := 0 ns ; signal s_st_int1_savt : chk_time_type := 0 ns ; signal s_time_savt : chk_time_type := 0 ns ; signal s_st_phys1_savt : chk_time_type := 0 ns ; signal s_real_savt : chk_time_type := 0 ns ; signal s_st_real1_savt : chk_time_type := 0 ns ; signal s_st_rec1_savt : chk_time_type := 0 ns ; signal s_st_rec2_savt : chk_time_type := 0 ns ; signal s_st_rec3_savt : chk_time_type := 0 ns ; signal s_st_arr1_savt : chk_time_type := 0 ns ; signal s_st_arr2_savt : chk_time_type := 0 ns ; signal s_st_arr3_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_boolean_cnt : chk_cnt_type := 0 ; signal s_bit_cnt : chk_cnt_type := 0 ; signal s_severity_level_cnt : chk_cnt_type := 0 ; signal s_character_cnt : chk_cnt_type := 0 ; signal s_st_enum1_cnt : chk_cnt_type := 0 ; signal s_integer_cnt : chk_cnt_type := 0 ; signal s_st_int1_cnt : chk_cnt_type := 0 ; signal s_time_cnt : chk_cnt_type := 0 ; signal s_st_phys1_cnt : chk_cnt_type := 0 ; signal s_real_cnt : chk_cnt_type := 0 ; signal s_st_real1_cnt : chk_cnt_type := 0 ; signal s_st_rec1_cnt : chk_cnt_type := 0 ; signal s_st_rec2_cnt : chk_cnt_type := 0 ; signal s_st_rec3_cnt : chk_cnt_type := 0 ; signal s_st_arr1_cnt : chk_cnt_type := 0 ; signal s_st_arr2_cnt : chk_cnt_type := 0 ; signal s_st_arr3_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal boolean_select : select_type := 1 ; signal bit_select : select_type := 1 ; signal severity_level_select : select_type := 1 ; signal character_select : select_type := 1 ; signal st_enum1_select : select_type := 1 ; signal integer_select : select_type := 1 ; signal st_int1_select : select_type := 1 ; signal time_select : select_type := 1 ; signal st_phys1_select : select_type := 1 ; signal real_select : select_type := 1 ; signal st_real1_select : select_type := 1 ; signal st_rec1_select : select_type := 1 ; signal st_rec2_select : select_type := 1 ; signal st_rec3_select : select_type := 1 ; signal st_arr1_select : select_type := 1 ; signal st_arr2_select : select_type := 1 ; signal st_arr3_select : select_type := 1 ; -- signal s_boolean : boolean := c_boolean_1 ; signal s_bit : bit := c_bit_1 ; signal s_severity_level : severity_level := c_severity_level_1 ; signal s_character : character := c_character_1 ; signal s_st_enum1 : st_enum1 := c_st_enum1_1 ; signal s_integer : integer := c_integer_1 ; signal s_st_int1 : st_int1 := c_st_int1_1 ; signal s_time : time := c_time_1 ; signal s_st_phys1 : st_phys1 := c_st_phys1_1 ; signal s_real : real := c_real_1 ; signal s_st_real1 : st_real1 := c_st_real1_1 ; signal s_st_rec1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3 : st_arr3 := c_st_arr3_1 ; -- begin CHG1 : process ( s_boolean ) variable correct : boolean ; begin case s_boolean_cnt is when 0 => null ; -- s_boolean <= transport -- c_boolean_2 after 10 ns, -- c_boolean_1 after 20 ns ; -- when 1 => correct := s_boolean = c_boolean_2 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- boolean_select <= transport 2 ; -- s_boolean <= transport -- c_boolean_2 after 10 ns , -- c_boolean_1 after 20 ns , -- c_boolean_2 after 30 ns , -- c_boolean_1 after 40 ns ; -- when 3 => correct := s_boolean = c_boolean_2 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; boolean_select <= transport 3 ; -- s_boolean <= transport -- c_boolean_1 after 5 ns ; -- when 4 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_boolean_savt <= transport Std.Standard.Now ; chk_boolean <= transport s_boolean_cnt after (1 us - Std.Standard.Now) ; s_boolean_cnt <= transport s_boolean_cnt + 1 ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_boolean ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_boolean = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_boolean <= transport c_boolean_2 after 10 ns, c_boolean_1 after 20 ns when boolean_select = 1 else -- c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns when boolean_select = 2 else -- c_boolean_1 after 5 ns ; -- CHG2 : process ( s_bit ) variable correct : boolean ; begin case s_bit_cnt is when 0 => null ; -- s_bit <= transport -- c_bit_2 after 10 ns, -- c_bit_1 after 20 ns ; -- when 1 => correct := s_bit = c_bit_2 and (s_bit_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P2" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- bit_select <= transport 2 ; -- s_bit <= transport -- c_bit_2 after 10 ns , -- c_bit_1 after 20 ns , -- c_bit_2 after 30 ns , -- c_bit_1 after 40 ns ; -- when 3 => correct := s_bit = c_bit_2 and (s_bit_savt + 10 ns) = Std.Standard.Now ; bit_select <= transport 3 ; -- s_bit <= transport -- c_bit_1 after 5 ns ; -- when 4 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_bit_savt <= transport Std.Standard.Now ; chk_bit <= transport s_bit_cnt after (1 us - Std.Standard.Now) ; s_bit_cnt <= transport s_bit_cnt + 1 ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_bit ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions completed entirely", chk_bit = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- -- s_bit <= transport c_bit_2 after 10 ns, c_bit_1 after 20 ns when bit_select = 1 else -- c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns when bit_select = 2 else -- c_bit_1 after 5 ns ; -- CHG3 : process ( s_severity_level ) variable correct : boolean ; begin case s_severity_level_cnt is when 0 => null ; -- s_severity_level <= transport -- c_severity_level_2 after 10 ns, -- c_severity_level_1 after 20 ns ; -- when 1 => correct := s_severity_level = c_severity_level_2 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P3" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- severity_level_select <= transport 2 ; -- s_severity_level <= transport -- c_severity_level_2 after 10 ns , -- c_severity_level_1 after 20 ns , -- c_severity_level_2 after 30 ns , -- c_severity_level_1 after 40 ns ; -- when 3 => correct := s_severity_level = c_severity_level_2 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; severity_level_select <= transport 3 ; -- s_severity_level <= transport -- c_severity_level_1 after 5 ns ; -- when 4 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_severity_level_savt <= transport Std.Standard.Now ; chk_severity_level <= transport s_severity_level_cnt after (1 us - Std.Standard.Now) ; s_severity_level_cnt <= transport s_severity_level_cnt + 1 ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_severity_level ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions completed entirely", chk_severity_level = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- -- s_severity_level <= transport c_severity_level_2 after 10 ns, c_severity_level_1 after 20 ns when severity_level_select = 1 else -- c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns when severity_level_select = 2 else -- c_severity_level_1 after 5 ns ; -- CHG4 : process ( s_character ) variable correct : boolean ; begin case s_character_cnt is when 0 => null ; -- s_character <= transport -- c_character_2 after 10 ns, -- c_character_1 after 20 ns ; -- when 1 => correct := s_character = c_character_2 and (s_character_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_character = c_character_1 and (s_character_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P4" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- character_select <= transport 2 ; -- s_character <= transport -- c_character_2 after 10 ns , -- c_character_1 after 20 ns , -- c_character_2 after 30 ns , -- c_character_1 after 40 ns ; -- when 3 => correct := s_character = c_character_2 and (s_character_savt + 10 ns) = Std.Standard.Now ; character_select <= transport 3 ; -- s_character <= transport -- c_character_1 after 5 ns ; -- when 4 => correct := correct and s_character = c_character_1 and (s_character_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_character_savt <= transport Std.Standard.Now ; chk_character <= transport s_character_cnt after (1 us - Std.Standard.Now) ; s_character_cnt <= transport s_character_cnt + 1 ; -- end process CHG4 ; -- PGEN_CHKP_4 : process ( chk_character ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions completed entirely", chk_character = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- -- s_character <= transport c_character_2 after 10 ns, c_character_1 after 20 ns when character_select = 1 else -- c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns when character_select = 2 else -- c_character_1 after 5 ns ; -- CHG5 : process ( s_st_enum1 ) variable correct : boolean ; begin case s_st_enum1_cnt is when 0 => null ; -- s_st_enum1 <= transport -- c_st_enum1_2 after 10 ns, -- c_st_enum1_1 after 20 ns ; -- when 1 => correct := s_st_enum1 = c_st_enum1_2 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P5" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_enum1_select <= transport 2 ; -- s_st_enum1 <= transport -- c_st_enum1_2 after 10 ns , -- c_st_enum1_1 after 20 ns , -- c_st_enum1_2 after 30 ns , -- c_st_enum1_1 after 40 ns ; -- when 3 => correct := s_st_enum1 = c_st_enum1_2 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; st_enum1_select <= transport 3 ; -- s_st_enum1 <= transport -- c_st_enum1_1 after 5 ns ; -- when 4 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_enum1_savt <= transport Std.Standard.Now ; chk_st_enum1 <= transport s_st_enum1_cnt after (1 us - Std.Standard.Now) ; s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ; -- end process CHG5 ; -- PGEN_CHKP_5 : process ( chk_st_enum1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions completed entirely", chk_st_enum1 = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- -- s_st_enum1 <= transport c_st_enum1_2 after 10 ns, c_st_enum1_1 after 20 ns when st_enum1_select = 1 else -- c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns when st_enum1_select = 2 else -- c_st_enum1_1 after 5 ns ; -- CHG6 : process ( s_integer ) variable correct : boolean ; begin case s_integer_cnt is when 0 => null ; -- s_integer <= transport -- c_integer_2 after 10 ns, -- c_integer_1 after 20 ns ; -- when 1 => correct := s_integer = c_integer_2 and (s_integer_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P6" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- integer_select <= transport 2 ; -- s_integer <= transport -- c_integer_2 after 10 ns , -- c_integer_1 after 20 ns , -- c_integer_2 after 30 ns , -- c_integer_1 after 40 ns ; -- when 3 => correct := s_integer = c_integer_2 and (s_integer_savt + 10 ns) = Std.Standard.Now ; integer_select <= transport 3 ; -- s_integer <= transport -- c_integer_1 after 5 ns ; -- when 4 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_integer_savt <= transport Std.Standard.Now ; chk_integer <= transport s_integer_cnt after (1 us - Std.Standard.Now) ; s_integer_cnt <= transport s_integer_cnt + 1 ; -- end process CHG6 ; -- PGEN_CHKP_6 : process ( chk_integer ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions completed entirely", chk_integer = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- -- s_integer <= transport c_integer_2 after 10 ns, c_integer_1 after 20 ns when integer_select = 1 else -- c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns when integer_select = 2 else -- c_integer_1 after 5 ns ; -- CHG7 : process ( s_st_int1 ) variable correct : boolean ; begin case s_st_int1_cnt is when 0 => null ; -- s_st_int1 <= transport -- c_st_int1_2 after 10 ns, -- c_st_int1_1 after 20 ns ; -- when 1 => correct := s_st_int1 = c_st_int1_2 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P7" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_int1_select <= transport 2 ; -- s_st_int1 <= transport -- c_st_int1_2 after 10 ns , -- c_st_int1_1 after 20 ns , -- c_st_int1_2 after 30 ns , -- c_st_int1_1 after 40 ns ; -- when 3 => correct := s_st_int1 = c_st_int1_2 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; st_int1_select <= transport 3 ; -- s_st_int1 <= transport -- c_st_int1_1 after 5 ns ; -- when 4 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_int1_savt <= transport Std.Standard.Now ; chk_st_int1 <= transport s_st_int1_cnt after (1 us - Std.Standard.Now) ; s_st_int1_cnt <= transport s_st_int1_cnt + 1 ; -- end process CHG7 ; -- PGEN_CHKP_7 : process ( chk_st_int1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions completed entirely", chk_st_int1 = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- -- s_st_int1 <= transport c_st_int1_2 after 10 ns, c_st_int1_1 after 20 ns when st_int1_select = 1 else -- c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns when st_int1_select = 2 else -- c_st_int1_1 after 5 ns ; -- CHG8 : process ( s_time ) variable correct : boolean ; begin case s_time_cnt is when 0 => null ; -- s_time <= transport -- c_time_2 after 10 ns, -- c_time_1 after 20 ns ; -- when 1 => correct := s_time = c_time_2 and (s_time_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_time = c_time_1 and (s_time_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P8" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- time_select <= transport 2 ; -- s_time <= transport -- c_time_2 after 10 ns , -- c_time_1 after 20 ns , -- c_time_2 after 30 ns , -- c_time_1 after 40 ns ; -- when 3 => correct := s_time = c_time_2 and (s_time_savt + 10 ns) = Std.Standard.Now ; time_select <= transport 3 ; -- s_time <= transport -- c_time_1 after 5 ns ; -- when 4 => correct := correct and s_time = c_time_1 and (s_time_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_time_savt <= transport Std.Standard.Now ; chk_time <= transport s_time_cnt after (1 us - Std.Standard.Now) ; s_time_cnt <= transport s_time_cnt + 1 ; -- end process CHG8 ; -- PGEN_CHKP_8 : process ( chk_time ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions completed entirely", chk_time = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- -- s_time <= transport c_time_2 after 10 ns, c_time_1 after 20 ns when time_select = 1 else -- c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns when time_select = 2 else -- c_time_1 after 5 ns ; -- CHG9 : process ( s_st_phys1 ) variable correct : boolean ; begin case s_st_phys1_cnt is when 0 => null ; -- s_st_phys1 <= transport -- c_st_phys1_2 after 10 ns, -- c_st_phys1_1 after 20 ns ; -- when 1 => correct := s_st_phys1 = c_st_phys1_2 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P9" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_phys1_select <= transport 2 ; -- s_st_phys1 <= transport -- c_st_phys1_2 after 10 ns , -- c_st_phys1_1 after 20 ns , -- c_st_phys1_2 after 30 ns , -- c_st_phys1_1 after 40 ns ; -- when 3 => correct := s_st_phys1 = c_st_phys1_2 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; st_phys1_select <= transport 3 ; -- s_st_phys1 <= transport -- c_st_phys1_1 after 5 ns ; -- when 4 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_phys1_savt <= transport Std.Standard.Now ; chk_st_phys1 <= transport s_st_phys1_cnt after (1 us - Std.Standard.Now) ; s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ; -- end process CHG9 ; -- PGEN_CHKP_9 : process ( chk_st_phys1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions completed entirely", chk_st_phys1 = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- -- s_st_phys1 <= transport c_st_phys1_2 after 10 ns, c_st_phys1_1 after 20 ns when st_phys1_select = 1 else -- c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns when st_phys1_select = 2 else -- c_st_phys1_1 after 5 ns ; -- CHG10 : process ( s_real ) variable correct : boolean ; begin case s_real_cnt is when 0 => null ; -- s_real <= transport -- c_real_2 after 10 ns, -- c_real_1 after 20 ns ; -- when 1 => correct := s_real = c_real_2 and (s_real_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_real = c_real_1 and (s_real_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P10" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- real_select <= transport 2 ; -- s_real <= transport -- c_real_2 after 10 ns , -- c_real_1 after 20 ns , -- c_real_2 after 30 ns , -- c_real_1 after 40 ns ; -- when 3 => correct := s_real = c_real_2 and (s_real_savt + 10 ns) = Std.Standard.Now ; real_select <= transport 3 ; -- s_real <= transport -- c_real_1 after 5 ns ; -- when 4 => correct := correct and s_real = c_real_1 and (s_real_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_real_savt <= transport Std.Standard.Now ; chk_real <= transport s_real_cnt after (1 us - Std.Standard.Now) ; s_real_cnt <= transport s_real_cnt + 1 ; -- end process CHG10 ; -- PGEN_CHKP_10 : process ( chk_real ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Transport transactions completed entirely", chk_real = 4 ) ; end if ; end process PGEN_CHKP_10 ; -- -- s_real <= transport c_real_2 after 10 ns, c_real_1 after 20 ns when real_select = 1 else -- c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns when real_select = 2 else -- c_real_1 after 5 ns ; -- CHG11 : process ( s_st_real1 ) variable correct : boolean ; begin case s_st_real1_cnt is when 0 => null ; -- s_st_real1 <= transport -- c_st_real1_2 after 10 ns, -- c_st_real1_1 after 20 ns ; -- when 1 => correct := s_st_real1 = c_st_real1_2 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P11" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_real1_select <= transport 2 ; -- s_st_real1 <= transport -- c_st_real1_2 after 10 ns , -- c_st_real1_1 after 20 ns , -- c_st_real1_2 after 30 ns , -- c_st_real1_1 after 40 ns ; -- when 3 => correct := s_st_real1 = c_st_real1_2 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; st_real1_select <= transport 3 ; -- s_st_real1 <= transport -- c_st_real1_1 after 5 ns ; -- when 4 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_real1_savt <= transport Std.Standard.Now ; chk_st_real1 <= transport s_st_real1_cnt after (1 us - Std.Standard.Now) ; s_st_real1_cnt <= transport s_st_real1_cnt + 1 ; -- end process CHG11 ; -- PGEN_CHKP_11 : process ( chk_st_real1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Transport transactions completed entirely", chk_st_real1 = 4 ) ; end if ; end process PGEN_CHKP_11 ; -- -- s_st_real1 <= transport c_st_real1_2 after 10 ns, c_st_real1_1 after 20 ns when st_real1_select = 1 else -- c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns when st_real1_select = 2 else -- c_st_real1_1 after 5 ns ; -- CHG12 : process ( s_st_rec1 ) variable correct : boolean ; begin case s_st_rec1_cnt is when 0 => null ; -- s_st_rec1 <= transport -- c_st_rec1_2 after 10 ns, -- c_st_rec1_1 after 20 ns ; -- when 1 => correct := s_st_rec1 = c_st_rec1_2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P12" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_select <= transport 2 ; -- s_st_rec1 <= transport -- c_st_rec1_2 after 10 ns , -- c_st_rec1_1 after 20 ns , -- c_st_rec1_2 after 30 ns , -- c_st_rec1_1 after 40 ns ; -- when 3 => correct := s_st_rec1 = c_st_rec1_2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; st_rec1_select <= transport 3 ; -- s_st_rec1 <= transport -- c_st_rec1_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec1_savt <= transport Std.Standard.Now ; chk_st_rec1 <= transport s_st_rec1_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ; -- end process CHG12 ; -- PGEN_CHKP_12 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Transport transactions completed entirely", chk_st_rec1 = 4 ) ; end if ; end process PGEN_CHKP_12 ; -- -- s_st_rec1 <= transport c_st_rec1_2 after 10 ns, c_st_rec1_1 after 20 ns when st_rec1_select = 1 else -- c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns when st_rec1_select = 2 else -- c_st_rec1_1 after 5 ns ; -- CHG13 : process ( s_st_rec2 ) variable correct : boolean ; begin case s_st_rec2_cnt is when 0 => null ; -- s_st_rec2 <= transport -- c_st_rec2_2 after 10 ns, -- c_st_rec2_1 after 20 ns ; -- when 1 => correct := s_st_rec2 = c_st_rec2_2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P13" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec2_select <= transport 2 ; -- s_st_rec2 <= transport -- c_st_rec2_2 after 10 ns , -- c_st_rec2_1 after 20 ns , -- c_st_rec2_2 after 30 ns , -- c_st_rec2_1 after 40 ns ; -- when 3 => correct := s_st_rec2 = c_st_rec2_2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; st_rec2_select <= transport 3 ; -- s_st_rec2 <= transport -- c_st_rec2_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec2_savt <= transport Std.Standard.Now ; chk_st_rec2 <= transport s_st_rec2_cnt after (1 us - Std.Standard.Now) ; s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ; -- end process CHG13 ; -- PGEN_CHKP_13 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Transport transactions completed entirely", chk_st_rec2 = 4 ) ; end if ; end process PGEN_CHKP_13 ; -- -- s_st_rec2 <= transport c_st_rec2_2 after 10 ns, c_st_rec2_1 after 20 ns when st_rec2_select = 1 else -- c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns when st_rec2_select = 2 else -- c_st_rec2_1 after 5 ns ; -- CHG14 : process ( s_st_rec3 ) variable correct : boolean ; begin case s_st_rec3_cnt is when 0 => null ; -- s_st_rec3 <= transport -- c_st_rec3_2 after 10 ns, -- c_st_rec3_1 after 20 ns ; -- when 1 => correct := s_st_rec3 = c_st_rec3_2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P14" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec3_select <= transport 2 ; -- s_st_rec3 <= transport -- c_st_rec3_2 after 10 ns , -- c_st_rec3_1 after 20 ns , -- c_st_rec3_2 after 30 ns , -- c_st_rec3_1 after 40 ns ; -- when 3 => correct := s_st_rec3 = c_st_rec3_2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; st_rec3_select <= transport 3 ; -- s_st_rec3 <= transport -- c_st_rec3_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec3_savt <= transport Std.Standard.Now ; chk_st_rec3 <= transport s_st_rec3_cnt after (1 us - Std.Standard.Now) ; s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ; -- end process CHG14 ; -- PGEN_CHKP_14 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Transport transactions completed entirely", chk_st_rec3 = 4 ) ; end if ; end process PGEN_CHKP_14 ; -- -- s_st_rec3 <= transport c_st_rec3_2 after 10 ns, c_st_rec3_1 after 20 ns when st_rec3_select = 1 else -- c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns when st_rec3_select = 2 else -- c_st_rec3_1 after 5 ns ; -- CHG15 : process ( s_st_arr1 ) variable correct : boolean ; begin case s_st_arr1_cnt is when 0 => null ; -- s_st_arr1 <= transport -- c_st_arr1_2 after 10 ns, -- c_st_arr1_1 after 20 ns ; -- when 1 => correct := s_st_arr1 = c_st_arr1_2 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P15" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr1_select <= transport 2 ; -- s_st_arr1 <= transport -- c_st_arr1_2 after 10 ns , -- c_st_arr1_1 after 20 ns , -- c_st_arr1_2 after 30 ns , -- c_st_arr1_1 after 40 ns ; -- when 3 => correct := s_st_arr1 = c_st_arr1_2 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; st_arr1_select <= transport 3 ; -- s_st_arr1 <= transport -- c_st_arr1_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_arr1_savt <= transport Std.Standard.Now ; chk_st_arr1 <= transport s_st_arr1_cnt after (1 us - Std.Standard.Now) ; s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ; -- end process CHG15 ; -- PGEN_CHKP_15 : process ( chk_st_arr1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Transport transactions completed entirely", chk_st_arr1 = 4 ) ; end if ; end process PGEN_CHKP_15 ; -- -- s_st_arr1 <= transport c_st_arr1_2 after 10 ns, c_st_arr1_1 after 20 ns when st_arr1_select = 1 else -- c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns when st_arr1_select = 2 else -- c_st_arr1_1 after 5 ns ; -- CHG16 : process ( s_st_arr2 ) variable correct : boolean ; begin case s_st_arr2_cnt is when 0 => null ; -- s_st_arr2 <= transport -- c_st_arr2_2 after 10 ns, -- c_st_arr2_1 after 20 ns ; -- when 1 => correct := s_st_arr2 = c_st_arr2_2 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P16" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr2_select <= transport 2 ; -- s_st_arr2 <= transport -- c_st_arr2_2 after 10 ns , -- c_st_arr2_1 after 20 ns , -- c_st_arr2_2 after 30 ns , -- c_st_arr2_1 after 40 ns ; -- when 3 => correct := s_st_arr2 = c_st_arr2_2 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; st_arr2_select <= transport 3 ; -- s_st_arr2 <= transport -- c_st_arr2_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_arr2_savt <= transport Std.Standard.Now ; chk_st_arr2 <= transport s_st_arr2_cnt after (1 us - Std.Standard.Now) ; s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ; -- end process CHG16 ; -- PGEN_CHKP_16 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Transport transactions completed entirely", chk_st_arr2 = 4 ) ; end if ; end process PGEN_CHKP_16 ; -- -- s_st_arr2 <= transport c_st_arr2_2 after 10 ns, c_st_arr2_1 after 20 ns when st_arr2_select = 1 else -- c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns when st_arr2_select = 2 else -- c_st_arr2_1 after 5 ns ; -- CHG17 : process ( s_st_arr3 ) variable correct : boolean ; begin case s_st_arr3_cnt is when 0 => null ; -- s_st_arr3 <= transport -- c_st_arr3_2 after 10 ns, -- c_st_arr3_1 after 20 ns ; -- when 1 => correct := s_st_arr3 = c_st_arr3_2 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00337.P17" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr3_select <= transport 2 ; -- s_st_arr3 <= transport -- c_st_arr3_2 after 10 ns , -- c_st_arr3_1 after 20 ns , -- c_st_arr3_2 after 30 ns , -- c_st_arr3_1 after 40 ns ; -- when 3 => correct := s_st_arr3 = c_st_arr3_2 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; st_arr3_select <= transport 3 ; -- s_st_arr3 <= transport -- c_st_arr3_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00337" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00337" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_arr3_savt <= transport Std.Standard.Now ; chk_st_arr3 <= transport s_st_arr3_cnt after (1 us - Std.Standard.Now) ; s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ; -- end process CHG17 ; -- PGEN_CHKP_17 : process ( chk_st_arr3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Transport transactions completed entirely", chk_st_arr3 = 4 ) ; end if ; end process PGEN_CHKP_17 ; -- -- s_st_arr3 <= transport c_st_arr3_2 after 10 ns, c_st_arr3_1 after 20 ns when st_arr3_select = 1 else -- c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns when st_arr3_select = 2 else -- c_st_arr3_1 after 5 ns ; -- end ARCH00337 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00337_Test_Bench is end ENT00337_Test_Bench ; -- -- architecture ARCH00337_Test_Bench of ENT00337_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00337 ( ARCH00337 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00337_Test_Bench ;
-- Copyright (C) 1991-2010 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. -- PROGRAM "Quartus II 64-Bit" -- VERSION "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version" -- CREATED "Thu Oct 31 13:57:57 2013" LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY nedge_s IS PORT ( D : IN STD_LOGIC; CK : IN STD_LOGIC; Q : OUT STD_LOGIC ); END nedge_s; ARCHITECTURE bdf_type OF nedge_s IS SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC; BEGIN SYNTHESIZED_WIRE_0 <= '1'; SYNTHESIZED_WIRE_1 <= '1'; SYNTHESIZED_WIRE_2 <= '1'; SYNTHESIZED_WIRE_3 <= '1'; SYNTHESIZED_WIRE_4 <= '1'; SYNTHESIZED_WIRE_6 <= '1'; PROCESS(CK,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_1) BEGIN IF (SYNTHESIZED_WIRE_0 = '0') THEN SYNTHESIZED_WIRE_8 <= '0'; ELSIF (SYNTHESIZED_WIRE_1 = '0') THEN SYNTHESIZED_WIRE_8 <= '1'; ELSIF (RISING_EDGE(CK)) THEN SYNTHESIZED_WIRE_8 <= D; END IF; END PROCESS; PROCESS(CK,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_3) BEGIN IF (SYNTHESIZED_WIRE_2 = '0') THEN SYNTHESIZED_WIRE_9 <= '0'; ELSIF (SYNTHESIZED_WIRE_3 = '0') THEN SYNTHESIZED_WIRE_9 <= '1'; ELSIF (RISING_EDGE(CK)) THEN SYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_8; END IF; END PROCESS; PROCESS(CK,SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_6) BEGIN IF (SYNTHESIZED_WIRE_4 = '0') THEN Q <= '0'; ELSIF (SYNTHESIZED_WIRE_6 = '0') THEN Q <= '1'; ELSIF (RISING_EDGE(CK)) THEN Q <= SYNTHESIZED_WIRE_5; END IF; END PROCESS; SYNTHESIZED_WIRE_5 <= SYNTHESIZED_WIRE_7 AND SYNTHESIZED_WIRE_9; SYNTHESIZED_WIRE_7 <= SYNTHESIZED_WIRE_8 XOR SYNTHESIZED_WIRE_9; END bdf_type;
-- Copyright (C) 1991-2010 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. -- PROGRAM "Quartus II 64-Bit" -- VERSION "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version" -- CREATED "Thu Oct 31 13:57:57 2013" LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY nedge_s IS PORT ( D : IN STD_LOGIC; CK : IN STD_LOGIC; Q : OUT STD_LOGIC ); END nedge_s; ARCHITECTURE bdf_type OF nedge_s IS SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC; BEGIN SYNTHESIZED_WIRE_0 <= '1'; SYNTHESIZED_WIRE_1 <= '1'; SYNTHESIZED_WIRE_2 <= '1'; SYNTHESIZED_WIRE_3 <= '1'; SYNTHESIZED_WIRE_4 <= '1'; SYNTHESIZED_WIRE_6 <= '1'; PROCESS(CK,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_1) BEGIN IF (SYNTHESIZED_WIRE_0 = '0') THEN SYNTHESIZED_WIRE_8 <= '0'; ELSIF (SYNTHESIZED_WIRE_1 = '0') THEN SYNTHESIZED_WIRE_8 <= '1'; ELSIF (RISING_EDGE(CK)) THEN SYNTHESIZED_WIRE_8 <= D; END IF; END PROCESS; PROCESS(CK,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_3) BEGIN IF (SYNTHESIZED_WIRE_2 = '0') THEN SYNTHESIZED_WIRE_9 <= '0'; ELSIF (SYNTHESIZED_WIRE_3 = '0') THEN SYNTHESIZED_WIRE_9 <= '1'; ELSIF (RISING_EDGE(CK)) THEN SYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_8; END IF; END PROCESS; PROCESS(CK,SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_6) BEGIN IF (SYNTHESIZED_WIRE_4 = '0') THEN Q <= '0'; ELSIF (SYNTHESIZED_WIRE_6 = '0') THEN Q <= '1'; ELSIF (RISING_EDGE(CK)) THEN Q <= SYNTHESIZED_WIRE_5; END IF; END PROCESS; SYNTHESIZED_WIRE_5 <= SYNTHESIZED_WIRE_7 AND SYNTHESIZED_WIRE_9; SYNTHESIZED_WIRE_7 <= SYNTHESIZED_WIRE_8 XOR SYNTHESIZED_WIRE_9; END bdf_type;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.cordic_lib.all; library floatfixlib; use floatfixlib.float_pkg.all; entity tester_ram_interna is generic( N_BITS_COORD : integer := 32 --- REVISAR ); port( clk_i: in std_logic; -- Clock general rst_i: in std_logic := '0'; -- Botón de reset pos_leida: out t_pos; ena_o: out std_logic := '0'; ram_int_refresh: out std_logic := '0' ); attribute loc: string; attribute loc of clk_i: signal is "B8"; end; architecture tester_ram_interna_arq of tester_ram_interna is signal RxRdy: std_logic := '0'; -- Dato listo para leerse signal Dout_uart: std_logic_vector(15 downto 0) := (others => '0'); signal Dout_memint: t_pos_mem := (others => (others => '0')); signal pos_leida_aux: t_pos := (others => CERO); type memo_t is array(0 to 39) of std_logic_vector(15 downto 0); constant testmemo : memo_t := ( "0000000000000000", "0000000000000100", "0000000000001100", "0000000001100000", "0000000000000010", "0000000000000001", "1000001100000000", "1000000000010000", "0100000000010000", "1111111111111111", "1111111111111110", "1111101111101111", "0000000000000010", "1000000000000011", "0000000000000011", "0000000001100000", "0000000000000010", "0000000000000001", "1000001100000000", "1000000000010000", "0100000000010000", "1111111111111111", "1111111111111110", "1111111111111110", "1111101111101111", "0000000000000010", "1000000000000011", "0000000000000011", "0000000001100000", "0000000000000010", "0100000000010000", "1111111111111111", "1111111111111110", "1111101111101111", "0000000000000010", "1000000000000011", "0000000000000011", "0000000001100000", "0000000000000001", "0000000000000010" ); begin process(clk_i) variable i : natural := 0; variable j : natural := 0; variable n : natural := 0; begin if rising_edge(clk_i) then i := i + 1; if i > 32 then i := 0; Dout_uart <= testmemo(j); RxRdy <= '1'; j := j + 1; if j >= testmemo'length then j := 0; end if; end if; --- else RxRdy <= '0'; if n < 150 then report "pos_leida 1 " & integer'image(to_integer(signed(pos_leida_aux(1))))-- & " ena_o " & ena_o severity note; report "pos_leida 2 " & integer'image(to_integer(signed(pos_leida_aux(2))))-- & " ena_o " & ena_o severity note; report "pos_leida 3 " & integer'image(to_integer(signed(pos_leida_aux(3))))-- & " ena_o " & ena_o severity note; n := n + 1; end if; end if; end process; --- Se guarda un dato de lectura listo en memoria [interna]. Continuamente se leen y guardan en vector pos_leida ram_int: entity work.ram_interna generic map( N_BITS => N_BITS_COORD---, ---CANT_P => 50---0 ) port map( clk => clk_i, rst => rst_i, Rx => RxRdy, Din => Dout_uart, Dout => Dout_memint, Rdy => ena_o, barrido => ram_int_refresh ); ---pos_leida_aux(i) <= to_float(std_logic_vector(to_signed(to_integer(signed(pos_leida_aux(i)),N_BITS_COORD)); pos_leida_aux(1) <= to_float(Dout_memint(1)); pos_leida_aux(2) <= to_float(Dout_memint(2)); pos_leida_aux(3) <= to_float(Dout_memint(3)); pos_leida <= pos_leida_aux; end;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; use work.cpu_pack.ALL; entity opcode_decoder is PORT( CLK_I : IN std_logic; T2 : IN std_logic; CLR : IN std_logic; CE : IN std_logic; OPCODE : IN std_logic_vector(7 downto 0); OP_CYC : IN cycle; -- current cycle (M1, M2, ...) INT : IN std_logic; -- interrupt RRZ : IN std_logic; -- RR is zero OP_CAT : OUT op_category; -- select signals D_SX : out std_logic_vector(1 downto 0); -- ALU select X D_SY : out std_logic_vector(3 downto 0); -- ALU select Y D_OP : out std_logic_vector(4 downto 0); -- ALU operation D_SA : out std_logic_vector(4 downto 0); -- select address D_SMQ : out std_logic; -- write enable/select signal D_WE_RR : out std_logic; D_WE_LL : out std_logic; D_WE_SP : out SP_OP; D_RD_O : out std_logic; D_WE_O : out std_logic; D_LOCK : out std_logic; -- input/output D_IO : out std_logic; PC_OP : out std_logic_vector(2 downto 0); LAST_M : out std_logic; -- last M cycle of an opcode HLT : out std_logic ); end opcode_decoder; architecture Behavioral of opcode_decoder is function pc(A : std_logic; OP : std_logic_vector(2 downto 0)) return std_logic_vector is begin if (A = '1') then return OP; else return PC_NEXT; end if; end; function hadr( A : std_logic; ADR : std_logic_vector(4 downto 0)) return std_logic_vector is begin return ADR(4 downto 1) & A; end; function mix(A : std_logic) return std_logic_vector is begin if (A = '1') then return ALU_X_MIX_Y; else return ALU_MOVE_Y; end if; end; function sp(A : std_logic; OP : SP_OP) return SP_OP is begin if (A = '1') then return OP; else return SP_NOP; end if; end; signal LAST : cycle; signal ENABLE_INT : std_logic; signal DISABLE_INT : std_logic; signal DISABLE_CNT : std_logic_vector(3 downto 0); signal HALT_REQ : std_logic; signal UNHALT_REQ : std_logic; signal HALTED : std_logic; signal INT_M1 : std_logic; signal INT_M2 : std_logic; begin LAST_M <= '1' when (OP_CYC = LAST) else '0'; HLT <= HALTED; -- show when CPU is halted -- HLT <= '1' when DISABLE_CNT = 0 else '0'; -- show when ints enabled process(CLK_I) begin if (rising_edge(CLK_I)) then if (CLR = '1') then DISABLE_CNT <= "0001"; -- 1 x disabled INT_M2 <= '0'; HALTED <= '0'; elsif (CE = '1' and T2 = '1') then if (DISABLE_INT = '1') then DISABLE_CNT <= DISABLE_CNT + 1; elsif (ENABLE_INT = '1' and DISABLE_CNT /= 0) then DISABLE_CNT <= DISABLE_CNT - 1; end if; if (UNHALT_REQ = '1') then HALTED <= '0'; elsif (HALT_REQ = '1') then HALTED <= '1'; end if; INT_M2 <= INT_M1; end if; end if; end process; process(OPCODE, OP_CYC, INT, RRZ, INT_M2, DISABLE_CNT, HALTED) variable IS_M1 : std_logic; variable IS_M2, IS_M1_M2 : std_logic; variable IS_M3, IS_M2_M3 : std_logic; variable IS_M4, IS_M3_M4 : std_logic; variable IS_M5 : std_logic; begin if (OP_CYC = M1) then IS_M1 := '1'; else IS_M1 := '0'; end if; if (OP_CYC = M2) then IS_M2 := '1'; else IS_M2 := '0'; end if; if (OP_CYC = M3) then IS_M3 := '1'; else IS_M3 := '0'; end if; if (OP_CYC = M4) then IS_M4 := '1'; else IS_M4 := '0'; end if; if (OP_CYC = M5) then IS_M5 := '1'; else IS_M5 := '0'; end if; IS_M1_M2 := IS_M1 or IS_M2; IS_M2_M3 := IS_M2 or IS_M3; IS_M3_M4 := IS_M3 or IS_M4; -- default: NOP -- OP_CAT <= undef; D_SX <= SX_ANY; D_SY <= SY_ANY; D_OP <= "00000"; D_SA <= "00000"; D_SMQ <= '0'; D_WE_RR <= '0'; D_WE_LL <= '0'; D_WE_SP <= SP_NOP; D_WE_O <= '0'; D_RD_O <= '0'; D_LOCK <= '0'; D_IO <= '0'; PC_OP <= PC_NEXT; LAST <= M1; -- default: single cycle opcode (M1 only) ENABLE_INT <= '0'; DISABLE_INT <= '0'; HALT_REQ <= '0'; UNHALT_REQ <= '0'; INT_M1 <= '0'; if ((IS_M1 = '1' and INT = '1' and DISABLE_CNT = "0000") -- new INT or or INT_M2 = '1' ) then -- continue INT OP_CAT <= INTR; LAST <= M2; INT_M1 <= IS_M1; D_OP <= ALU_X_ADD_Y; D_SX <= SX_PC; D_SY <= SY_SY0; -- PC + 0 (current PC) D_SA <= ADR_dSP; D_WE_O <= IS_M1_M2; D_LOCK <= IS_M1; PC_OP <= pc(IS_M1, PC_INT); D_SMQ <= IS_M1; D_WE_SP <= sp(IS_M1_M2, SP_LOAD); DISABLE_INT <= IS_M1; UNHALT_REQ <= '1'; elsif (HALTED = '1') then OP_CAT <= HALT_WAIT; LAST <= M2; PC_OP <= PC_WAIT; elsif (OPCODE(7) = '1') then case OPCODE(6 downto 4) is when "010" => OP_CAT <= ADD_RR_I; D_OP <= ALU_X_ADD_Y; D_SX <= SX_RR; D_SY <= SY_UQ; D_WE_RR <= IS_M1; when "011" => OP_CAT <= SUB_RR_I; D_OP <= ALU_X_SUB_Y; D_SX <= SX_RR; D_SY <= SY_UQ; D_WE_RR <= IS_M1; when "100" => OP_CAT <= MOVE_I_RR; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_SQ; D_WE_RR <= IS_M1; when "101" => OP_CAT <= SEQ_LL_I; D_OP <= ALU_X_EQ_Y; D_SX <= SX_LL; D_SY <= SY_SQ; D_WE_RR <= IS_M1; -- !! RR when "110" => OP_CAT <= MOVE_I_LL; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_UQ; D_WE_LL <= IS_M1; when "111" => case OPCODE(3 downto 0) is when "0100" => OP_CAT <= ADD_RR_I; D_OP <= ALU_X_ADD_Y; D_SX <= SX_RR; D_SY <= SY_I16; LAST <= M3; D_WE_RR <= IS_M3; when "0101" => OP_CAT <= ADD_RR_I; D_OP <= ALU_X_ADD_Y; D_SX <= SX_RR; D_SY <= SY_UI8; LAST <= M2; D_WE_RR <= IS_M2; when "0110" => OP_CAT <= SUB_RR_I; D_OP <= ALU_X_SUB_Y; D_SX <= SX_RR; D_SY <= SY_I16; LAST <= M3; D_WE_RR <= IS_M3; when "0111" => OP_CAT <= SUB_RR_I; D_OP <= ALU_X_SUB_Y; D_SX <= SX_RR; D_SY <= SY_UI8; LAST <= M2; D_WE_RR <= IS_M2; when "1000" => OP_CAT <= MOVE_I_RR; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_I16; LAST <= M3; D_WE_RR <= IS_M3; when "1001" => OP_CAT <= MOVE_I_RR; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_SI8; LAST <= M2; D_WE_RR <= IS_M2; when "1010" => OP_CAT <= SEQ_LL_I; D_OP <= ALU_X_EQ_Y; D_SX <= SX_LL; D_SY <= SY_I16; LAST <= M3; D_WE_RR <= IS_M3; -- SEQ sets RR ! when "1011" => OP_CAT <= SEQ_LL_I; D_OP <= ALU_X_EQ_Y; D_SX <= SX_LL; D_SY <= SY_SI8; LAST <= M2; D_WE_RR <= IS_M2; -- SEQ sets RR ! when "1100" => OP_CAT <= MOVE_I_LL; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_I16; LAST <= M3; D_WE_LL <= IS_M3; when "1101" => OP_CAT <= MOVE_I_LL; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_SI8; LAST <= M2; D_WE_LL <= IS_M2; when others => -- undefined end case; when others => -- undefined end case; else case OPCODE(6 downto 0) is -- 00000000000000000000000000000000000000000000000000000000000000000000 when "0000000" => OP_CAT <= HALT; HALT_REQ <= '1'; PC_OP <= PC_WAIT; when "0000001" => OP_CAT <= NOP; when "0000010" => OP_CAT <= JMP_i; LAST <= M3; PC_OP <= pc(IS_M2, PC_JMP); when "0000011" => OP_CAT <= JMP_RRNZ_i; LAST <= M3; PC_OP <= pc(IS_M2 and not RRZ, PC_JMP); when "0000100" => OP_CAT <= JMP_RRZ_i; LAST <= M3; PC_OP <= pc(IS_M2 and RRZ, PC_JMP); when "0000101" => OP_CAT <= CALL_i; LAST <= M3; D_OP <= ALU_X_ADD_Y; D_SX <= SX_PC; D_SY <= SY_SY3; -- PC + 3 D_SA <= ADR_dSP; D_WE_O <= IS_M1_M2; D_LOCK <= IS_M1; PC_OP <= pc(IS_M2, PC_JMP); D_SMQ <= IS_M1; D_WE_SP <= sp(IS_M1_M2, SP_LOAD); when "0000110" => OP_CAT <= CALL_RR; LAST <= M2; D_OP <= ALU_X_ADD_Y; D_SX <= SX_PC; D_SY <= SY_SY1; -- PC + 1 D_SA <= ADR_dSP; D_WE_O <= IS_M1_M2; D_LOCK <= IS_M1; PC_OP <= pc(IS_M1, PC_JPRR); D_SMQ <= IS_M1; D_WE_SP <= sp(IS_M1_M2, SP_LOAD); when "0000111" | "1111000" => if (OPCODE(0) = '1') then OP_CAT <= RET; else OP_CAT <= RETI; ENABLE_INT <= IS_M1; end if; LAST <= M5; D_SA <= ADR_SPi; -- read address: (SP)+ D_RD_O <= IS_M1_M2; D_LOCK <= IS_M1; D_WE_SP <= sp(IS_M1_M2, SP_INC); case OP_CYC is when M1 => PC_OP <= PC_WAIT; when M2 => PC_OP <= PC_WAIT; when M3 => PC_OP <= PC_RETL; when M4 => PC_OP <= PC_RETH; when others => end case; when "0001000" => OP_CAT <= MOVE_SPi_RR; D_SX <= SX_RR; D_SY <= SY_UM; D_SA <= ADR_SPi; D_RD_O <= IS_M1_M2; D_LOCK <= IS_M1; LAST <= M3; PC_OP <= pc(IS_M1_M2, PC_WAIT); D_WE_RR <= IS_M2_M3; D_WE_SP <= sp(IS_M1_M2, SP_INC); D_OP <= mix(IS_M3); when "0001001" => OP_CAT <= MOVE_SPi_RS; LAST <= M2; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_SM; D_SA <= ADR_SPi; D_RD_O <= IS_M1; D_WE_RR <= IS_M2; PC_OP <= pc(IS_M1, PC_WAIT); D_WE_SP <= sp(IS_M1, SP_INC); when "0001010" => OP_CAT <= MOVE_SPi_RU; LAST <= M2; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_UM; D_SA <= ADR_SPi; D_RD_O <= IS_M1; PC_OP <= pc(IS_M1, PC_WAIT); D_WE_SP <= sp(IS_M1, SP_INC); D_WE_RR <= IS_M2; when "0001011" => OP_CAT <= MOVE_SPi_LL; LAST <= M3; D_SX <= SX_LL; D_SY <= SY_UM; D_SA <= ADR_SPi; D_RD_O <= IS_M1_M2; D_LOCK <= IS_M1; PC_OP <= pc(IS_M1_M2, PC_WAIT); D_WE_SP <= sp(IS_M1_M2, SP_INC); D_WE_LL <= IS_M2_M3; D_OP <= mix(IS_M3); when "0001100" => OP_CAT <= MOVE_SPi_LS; LAST <= M2; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_SM; D_SA <= ADR_SPi; D_RD_O <= IS_M1; PC_OP <= pc(IS_M1, PC_WAIT); D_WE_SP <= sp(IS_M1, SP_INC); D_WE_LL <= IS_M2; when "0001101" => OP_CAT <= MOVE_SPi_LU; LAST <= M2; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_UM; D_SA <= ADR_SPi; D_RD_O <= IS_M1; PC_OP <= pc(IS_M1, PC_WAIT); D_WE_SP <= sp(IS_M1, SP_INC); D_WE_LL <= IS_M2; when "0001110" => OP_CAT <= MOVE_RR_dSP; LAST <= M2; D_OP <= ALU_X_OR_Y; D_SX <= SX_RR; D_SY <= SY_SY0; D_SA <= ADR_dSP; D_WE_O <= IS_M1_M2; D_LOCK <= IS_M1; PC_OP <= pc(IS_M1, PC_WAIT); D_WE_SP <= sp(IS_M1_M2, SP_LOAD); D_SMQ <= IS_M1; when "0001111" => OP_CAT <= MOVE_R_dSP; D_OP <= ALU_X_OR_Y; D_SX <= SX_RR; D_SY <= SY_SY0; D_SA <= ADR_dSP; D_WE_O <= '1'; D_WE_SP <= SP_LOAD; -- 11111111111111111111111111111111111111111111111111111111111111111111 when "0010000" => OP_CAT <= AND_RR_i; LAST <= M3; -- wait for ## D_OP <= ALU_X_AND_Y; D_SX <= SX_RR; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "0010001" => OP_CAT <= AND_RR_i; LAST <= M2; -- wait for # D_OP <= ALU_X_AND_Y; D_SX <= SX_RR; D_SY <= SY_UI8; D_WE_RR <= IS_M1; when "0010010" => OP_CAT <= OR_RR_i; LAST <= M3; -- wait for ## D_OP <= ALU_X_OR_Y; D_SX <= SX_RR; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "0010011" => OP_CAT <= OR_RR_i; LAST <= M2; -- wait for # D_OP <= ALU_X_OR_Y; D_SX <= SX_RR; D_SY <= SY_UI8; D_WE_RR <= IS_M1; when "0010100" => OP_CAT <= XOR_RR_i; LAST <= M3; -- wait for ## D_OP <= ALU_X_XOR_Y; D_SX <= SX_RR; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "0010101" => OP_CAT <= XOR_RR_i; LAST <= M2; -- wait for # D_OP <= ALU_X_XOR_Y; D_SX <= SX_RR; D_SY <= SY_UI8; D_WE_RR <= IS_M1; when "0010110" => OP_CAT <= SEQ_RR_i; LAST <= M3; -- wait for ## D_OP <= ALU_X_EQ_Y; D_SX <= SX_RR; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "0010111" => OP_CAT <= SEQ_RR_i; LAST <= M2; -- wait for # D_OP <= ALU_X_EQ_Y; D_SX <= SX_RR; D_SY <= SY_UI8; D_WE_RR <= IS_M1; when "0011000" => OP_CAT <= SNE_RR_i; LAST <= M3; -- wait for ## D_OP <= ALU_X_NE_Y; D_SX <= SX_RR; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "0011001" => OP_CAT <= SNE_RR_i; LAST <= M2; -- wait for # D_OP <= ALU_X_NE_Y; D_SX <= SX_RR; D_SY <= SY_UI8; D_WE_RR <= IS_M1; when "0011010" => OP_CAT <= SGE_RR_i; LAST <= M3; -- wait for ## D_OP <= ALU_X_GE_Y; D_SX <= SX_RR; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "0011011" => OP_CAT <= SGE_RR_i; LAST <= M2; -- wait for # D_OP <= ALU_X_GE_Y; D_SX <= SX_RR; D_SY <= SY_SI8; D_WE_RR <= IS_M1; when "0011100" => OP_CAT <= SGT_RR_i; LAST <= M3; -- wait for ## D_OP <= ALU_X_GT_Y; D_SX <= SX_RR; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "0011101" => OP_CAT <= SGT_RR_i; LAST <= M2; -- wait for # D_OP <= ALU_X_GT_Y; D_SX <= SX_RR; D_SY <= SY_SI8; D_WE_RR <= IS_M1; when "0011110" => OP_CAT <= SLE_RR_i; LAST <= M3; -- wait for ## D_OP <= ALU_X_LE_Y; D_SX <= SX_RR; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "0011111" => OP_CAT <= SLE_RR_i; LAST <= M2; -- wait for # D_OP <= ALU_X_LE_Y; D_SX <= SX_RR; D_SY <= SY_SI8; D_WE_RR <= IS_M1; -- 22222222222222222222222222222222222222222222222222222222222222222222 when "0100000" => OP_CAT <= SLT_RR_i; LAST <= M3; -- wait for ## D_OP <= ALU_X_LT_Y; D_SX <= SX_RR; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "0100001" => OP_CAT <= SLT_RR_i; LAST <= M2; -- wait for # D_OP <= ALU_X_LT_Y; D_SX <= SX_RR; D_SY <= SY_SI8; D_WE_RR <= IS_M1; when "0100010" => OP_CAT <= SHS_RR_i; LAST <= M3; -- wait for ## D_OP <= ALU_X_HS_Y; D_SX <= SX_RR; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "0100011" => OP_CAT <= SHS_RR_i; LAST <= M2; -- wait for # D_OP <= ALU_X_HS_Y; D_SX <= SX_RR; D_SY <= SY_UI8; D_WE_RR <= IS_M1; when "0100100" => OP_CAT <= SHI_RR_i; LAST <= M3; -- wait for ## D_OP <= ALU_X_HI_Y; D_SX <= SX_RR; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "0100101" => OP_CAT <= SHI_RR_i; LAST <= M2; -- wait for # D_OP <= ALU_X_HI_Y; D_SX <= SX_RR; D_SY <= SY_UI8; D_WE_RR <= IS_M1; when "0100110" => OP_CAT <= SLS_RR_i; LAST <= M3; -- wait for ## D_OP <= ALU_X_LS_Y; D_SX <= SX_RR; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "0100111" => OP_CAT <= SLS_RR_i; LAST <= M2; -- wait for # D_OP <= ALU_X_LS_Y; D_SX <= SX_RR; D_SY <= SY_UI8; D_WE_RR <= IS_M1; when "0101000" => OP_CAT <= SLO_RR_i; LAST <= M3; -- wait for ## D_OP <= ALU_X_LO_Y; D_SX <= SX_RR; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "0101001" => OP_CAT <= SLO_RR_i; LAST <= M2; -- wait for # D_OP <= ALU_X_LO_Y; D_SX <= SX_RR; D_SY <= SY_UI8; D_WE_RR <= IS_M1; when "0101010" => OP_CAT <= ADD_SP_I; LAST <= M3; -- wait for ## D_OP <= ALU_ANY; D_SX <= SX_ANY; D_SY <= SY_ANY; D_SA <= ADR_16SP_L; D_WE_SP <= sp(IS_M2, SP_LOAD); when "0101011" => OP_CAT <= ADD_SP_I; LAST <= M2; -- wait for # D_OP <= ALU_ANY; D_SX <= SX_ANY; D_SY <= SY_ANY; D_SA <= ADR_8SP_L; D_WE_SP <= sp(IS_M1, SP_LOAD); when "0101100" => OP_CAT <= CLRW_dSP; LAST <= M2; D_OP <= ALU_X_AND_Y; D_SX <= SX_ANY; D_SY <= SY_SY0; D_SA <= ADR_dSP; D_WE_O <= '1'; D_LOCK <= IS_M1; D_WE_SP <= SP_LOAD; PC_OP <= pc(IS_M1, PC_WAIT); when "0101101" => OP_CAT <= CLRB_dSP; D_OP <= ALU_X_AND_Y; D_SX <= SX_ANY; D_SY <= SY_SY0; D_SA <= ADR_dSP; D_WE_O <= IS_M1; D_WE_SP <= SP_LOAD; when "0101110" => OP_CAT <= IN_ci_RU; LAST <= M2; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_UM; D_SA <= ADR_IO; D_RD_O <= IS_M1; D_IO <= IS_M1; D_WE_RR <= IS_M2; when "0101111" => OP_CAT <= OUT_R_ci; LAST <= M2; D_OP <= ALU_X_OR_Y; D_SX <= SX_RR; D_SY <= SY_SY0; D_SA <= ADR_IO; D_WE_O <= IS_M1; D_IO <= IS_M1; -- 33333333333333333333333333333333333333333333333333333333333333333333 when "0110000" => OP_CAT <= AND_LL_RR; D_OP <= ALU_X_AND_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0110001" => OP_CAT <= OR_LL_RR; D_OP <= ALU_X_OR_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0110010" => OP_CAT <= XOR_LL_RR; D_OP <= ALU_X_XOR_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0110011" => OP_CAT <= SEQ_LL_RR; D_OP <= ALU_X_EQ_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0110100" => OP_CAT <= SNE_LL_RR; D_OP <= ALU_X_NE_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0110101" => OP_CAT <= SGE_LL_RR; D_OP <= ALU_X_GE_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0110110" => OP_CAT <= SGT_LL_RR; D_OP <= ALU_X_GT_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0110111" => OP_CAT <= SLE_LL_RR; D_OP <= ALU_X_LE_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0111000" => OP_CAT <= SLT_LL_RR; D_OP <= ALU_X_LT_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0111001" => OP_CAT <= SHS_LL_RR; D_OP <= ALU_X_HS_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0111010" => OP_CAT <= SHI_LL_RR; D_OP <= ALU_X_HI_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0111011" => OP_CAT <= SLS_LL_RR; D_OP <= ALU_X_LS_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0111100" => OP_CAT <= SLO_LL_RR; D_OP <= ALU_X_LO_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0111101" => OP_CAT <= LNOT_RR; D_OP <= ALU_X_EQ_Y; D_SX <= SX_RR; D_SY <= SY_SY0; D_WE_RR <= IS_M1; when "0111110" => OP_CAT <= NEG_RR; D_OP <= ALU_NEG_Y; D_SX <= SX_ANY; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "0111111" => OP_CAT <= NOT_RR; D_OP <= ALU_NOT_Y; D_SX <= SX_ANY; D_SY <= SY_RR; D_WE_RR <= IS_M1; -- 44444444444444444444444444444444444444444444444444444444444444444444 when "1000000" => OP_CAT <= MOVE_LL_RR; D_OP <= ALU_X_OR_Y; D_SX <= SX_LL; D_SY <= SY_SY0; D_WE_RR <= IS_M1; when "1000001" => OP_CAT <= MOVE_LL_cRR; LAST <= M2; PC_OP <= pc(IS_M1, PC_WAIT); D_OP <= ALU_X_OR_Y; D_SX <= SX_LL; D_SY <= SY_SY0; D_SA <= hadr(IS_M2, ADR_cRR_H); D_WE_O <= IS_M1_M2; D_LOCK <= IS_M1; D_SMQ <= IS_M2; when "1000010" => OP_CAT <= MOVE_L_cRR; D_OP <= ALU_X_OR_Y; D_SX <= SX_LL; D_SY <= SY_SY0; D_SA <= ADR_cRR_L; D_WE_O <= IS_M1; when "1000011" => OP_CAT <= MOVE_RR_LL; D_OP <= ALU_X_OR_Y; D_SX <= SX_RR; D_SY <= SY_SY0; D_WE_LL <= IS_M1; when "1000100" => OP_CAT <= MOVE_RR_cLL; LAST <= M2; PC_OP <= pc(IS_M1, PC_WAIT); D_OP <= ALU_X_OR_Y; D_SX <= SX_RR; D_SY <= SY_SY0; D_SA <= hadr(IS_M2, ADR_cLL_H); D_WE_O <= IS_M1_M2; D_LOCK <= IS_M1; D_SMQ <= IS_M2; when "1000101" => OP_CAT <= MOVE_R_cLL; D_OP <= ALU_X_OR_Y; D_SX <= SX_RR; D_SY <= SY_SY0; D_SA <= ADR_cLL_L; D_WE_O <= IS_M1; when "1000110" => OP_CAT <= MOVE_cRR_RR; LAST <= M3; D_SX <= SX_ANY; D_SY <= SY_UM; D_WE_RR <= not IS_M1; -- M2 or M3 PC_OP <= pc(IS_M1_M2, PC_WAIT); D_OP <= mix(IS_M3); D_SA <= hadr(IS_M2, ADR_cRR_H); D_RD_O <= IS_M1_M2; D_LOCK <= IS_M1; when "1000111" => OP_CAT <= MOVE_cRR_RS; LAST <= M2; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_SM; D_SA <= ADR_cRR_L; D_RD_O <= IS_M1; D_WE_RR <= IS_M2; PC_OP <= pc(IS_M1, PC_WAIT); when "1001000" => OP_CAT <= MOVE_cRR_RU; LAST <= M2; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_UM; D_SA <= ADR_cRR_L; D_RD_O <= IS_M1; D_WE_RR <= IS_M2; PC_OP <= pc(IS_M1, PC_WAIT); when "1001001" => OP_CAT <= MOVE_ci_RR; LAST <= M4; D_SX <= SX_RR; D_SY <= SY_UM; PC_OP <= pc(IS_M3, PC_WAIT); D_OP <= mix(IS_M4); D_WE_RR <= IS_M3_M4; D_SA <= hadr(IS_M3, ADR_cI16_H); D_RD_O <= IS_M2_M3; D_LOCK <= IS_M2; when "1001010" => OP_CAT <= MOVE_ci_RS; LAST <= M3; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_SM; D_SA <= ADR_cI16_L; D_RD_O <= IS_M2; D_WE_RR <= IS_M3; when "1001011" => OP_CAT <= MOVE_ci_RU; LAST <= M3; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_UM; D_SA <= ADR_cI16_L; D_RD_O <= IS_M2; D_WE_RR <= IS_M3; when "1001100" => OP_CAT <= MOVE_ci_LL; LAST <= M4; D_SX <= SX_LL; D_SY <= SY_UM; PC_OP <= pc(IS_M3, PC_WAIT); D_OP <= mix(IS_M4); D_SA <= hadr(IS_M3, ADR_cI16_H); D_RD_O <= IS_M2_M3; D_LOCK <= IS_M2; D_WE_LL <= IS_M3_M4; when "1001101" => OP_CAT <= MOVE_ci_LS; LAST <= M3; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_SM; D_SA <= ADR_cI16_L; D_RD_O <= IS_M2; D_WE_LL <= IS_M3; when "1001110" => OP_CAT <= MOVE_ci_LU; LAST <= M3; D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_UM; D_SA <= ADR_cI16_L; D_RD_O <= IS_M2; D_WE_LL <= IS_M3; when "1001111" => OP_CAT <= MOVE_RR_SP; D_SA <= ADR_cRR_L; D_WE_SP <= SP_LOAD; -- 55555555555555555555555555555555555555555555555555555555555555555555 when "1010000" => -- spare when "1010001" => -- spare when "1010010" => OP_CAT <= LSL_RR_i; LAST <= M2; D_OP <= ALU_X_LSL_Y; D_SX <= SX_RR; D_SY <= SY_UI8; D_WE_RR <= IS_M1; when "1010011" => OP_CAT <= ASR_RR_i; LAST <= M2; D_OP <= ALU_X_ASR_Y; D_SX <= SX_RR; D_SY <= SY_UI8; D_WE_RR <= IS_M1; when "1010100" => OP_CAT <= LSR_RR_i; LAST <= M2; D_OP <= ALU_X_LSR_Y; D_SX <= SX_RR; D_SY <= SY_UI8; D_WE_RR <= IS_M1; when "1010101" => OP_CAT <= LSL_LL_RR; D_OP <= ALU_X_LSL_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "1010110" => OP_CAT <= ASR_LL_RR; D_OP <= ALU_X_ASR_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "1010111" => OP_CAT <= LSR_LL_RR; D_OP <= ALU_X_LSR_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "1011000" => OP_CAT <= ADD_LL_RR; D_OP <= ALU_X_ADD_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "1011001" => OP_CAT <= SUB_LL_RR; D_OP <= ALU_X_SUB_Y; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "1011010" => OP_CAT <= MOVE_RR_ci; LAST <= M3; D_SX <= SX_RR; D_SY <= SY_SY0; D_OP <= ALU_X_OR_Y; D_SA <= hadr(IS_M3, ADR_cI16_H); D_WE_O <= IS_M2_M3; D_LOCK <= IS_M2; D_SMQ <= IS_M3; when "1011011" => OP_CAT <= MOVE_R_ci; LAST <= M3; D_SX <= SX_RR; D_SY <= SY_SY0; D_OP <= ALU_X_OR_Y; D_SA <= ADR_cI16_L; D_WE_O <= IS_M2; when "1011100" => -- long offset / long move OP_CAT <= MOVE_RR_uSP; LAST <= M3; D_SX <= SX_RR; D_SY <= SY_SY0; D_OP <= ALU_X_OR_Y; D_SA <= hadr(IS_M3, ADR_16SP_H); D_WE_O <= IS_M2_M3; D_LOCK <= IS_M2; D_SMQ <= IS_M3; when "1011101" => -- short offset / long move OP_CAT <= MOVE_RR_uSP; LAST <= M2; D_SX <= SX_RR; D_SY <= SY_SY0; D_OP <= ALU_X_OR_Y; D_SA <= hadr(IS_M2, ADR_8SP_H); D_WE_O <= IS_M1_M2; D_LOCK <= IS_M1; D_SMQ <= IS_M2; when "1011110" => -- long offset / short move OP_CAT <= MOVE_R_uSP; LAST <= M3; D_SX <= SX_RR; D_SY <= SY_SY0; D_OP <= ALU_X_OR_Y; D_SA <= ADR_16SP_L; D_WE_O <= IS_M2; D_OP <= ALU_X_OR_Y; when "1011111" => -- short offset / short move OP_CAT <= MOVE_R_uSP; LAST <= M2; D_SX <= SX_RR; D_SY <= SY_SY0; D_OP <= ALU_X_OR_Y; D_SA <= ADR_8SP_L; D_WE_O <= IS_M1; D_OP <= ALU_X_OR_Y; -- 66666666666666666666666666666666666666666666666666666666666666666666 when "1100000" => -- long offset, long move OP_CAT <= MOVE_uSP_RR; LAST <= M4; D_SX <= SX_RR; D_SY <= SY_UM; PC_OP <= pc(IS_M3, PC_WAIT); D_OP <= mix(IS_M3_M4); D_SA <= hadr(IS_M3, ADR_16SP_H); D_RD_O <= IS_M2_M3; D_LOCK <= IS_M2; D_WE_RR <= IS_M3_M4; when "1100001" => -- short offset, long move OP_CAT <= MOVE_uSP_RR; LAST <= M3; D_SX <= SX_RR; D_SY <= SY_UM; PC_OP <= pc(IS_M2, PC_WAIT); D_OP <= mix(IS_M3); D_SA <= hadr(IS_M2, ADR_8SP_H); D_RD_O <= IS_M1_M2; D_LOCK <= IS_M1; D_WE_RR <= IS_M2_M3; when "1100010" => -- long offset, short move OP_CAT <= MOVE_uSP_RS; LAST <= M3; D_OP <= ALU_MOVE_Y; D_SX <= SX_RR; D_SY <= SY_SM; D_SA <= ADR_16SP_L; D_RD_O <= IS_M2; D_WE_RR <= IS_M3; when "1100011" => -- short offset, short move OP_CAT <= MOVE_uSP_RS; LAST <= M2; D_OP <= ALU_MOVE_Y; D_SX <= SX_RR; D_SY <= SY_SM; D_SA <= ADR_8SP_L; D_RD_O <= IS_M1; D_WE_RR <= IS_M2; when "1100100" => -- long offset, short move OP_CAT <= MOVE_uSP_RU; LAST <= M3; D_OP <= ALU_MOVE_Y; D_SX <= SX_RR; D_SY <= SY_UM; D_SA <= ADR_16SP_L; D_RD_O <= IS_M2; D_WE_RR <= IS_M3; when "1100101" => -- short offset, short move OP_CAT <= MOVE_uSP_RU; LAST <= M2; D_OP <= ALU_MOVE_Y; D_SX <= SX_RR; D_SY <= SY_UM; D_SA <= ADR_8SP_L; D_RD_O <= IS_M1; D_WE_RR <= IS_M2; when "1100110" => -- long offset, long move OP_CAT <= MOVE_uSP_LL; LAST <= M4; D_SX <= SX_LL; D_SY <= SY_UM; PC_OP <= pc(IS_M3, PC_WAIT); D_OP <= mix(IS_M4); D_SA <= hadr(IS_M3, ADR_8SP_H); D_RD_O <= IS_M2_M3; D_LOCK <= IS_M2; D_WE_LL <= IS_M3_M4; when "1100111" => -- short offset, long move OP_CAT <= MOVE_uSP_LL; LAST <= M3; D_SX <= SX_LL; D_SY <= SY_UM; PC_OP <= pc(IS_M2, PC_WAIT); D_OP <= mix(IS_M3); D_SA <= hadr(IS_M2, ADR_8SP_H); D_RD_O <= IS_M1_M2; D_LOCK <= IS_M1; D_WE_LL <= IS_M2_M3; when "1101000" => -- long offset, short move OP_CAT <= MOVE_uSP_LS; LAST <= M3; D_OP <= ALU_MOVE_Y; D_SX <= SX_RR; D_SY <= SY_SM; D_SA <= ADR_16SP_L; D_RD_O <= IS_M2; D_WE_LL <= IS_M3; when "1101001" => -- short offset, short move OP_CAT <= MOVE_uSP_LS; LAST <= M2; D_OP <= ALU_MOVE_Y; D_SX <= SX_RR; D_SY <= SY_SM; D_SA <= ADR_8SP_L; D_RD_O <= IS_M1; D_WE_LL <= IS_M2; when "1101010" => -- long offset, short move OP_CAT <= MOVE_uSP_LU; LAST <= M3; D_OP <= ALU_MOVE_Y; D_SX <= SX_RR; D_SY <= SY_UM; D_SA <= ADR_16SP_L; D_RD_O <= IS_M2; D_WE_LL <= IS_M3; when "1101011" => -- short offset, short move OP_CAT <= MOVE_uSP_LU; LAST <= M2; D_OP <= ALU_MOVE_Y; D_SX <= SX_RR; D_SY <= SY_UM; D_SA <= ADR_8SP_L; D_RD_O <= IS_M1; D_WE_LL <= IS_M2; when "1101100" => OP_CAT <= LEA_uSP_RR; LAST <= M3; D_OP <= ALU_X_ADD_Y; D_SX <= SX_SP; D_SY <= SY_I16; D_WE_RR <= IS_M2; when "1101101" => OP_CAT <= LEA_uSP_RR; LAST <= M2; D_OP <= ALU_X_ADD_Y; D_SX <= SX_SP; D_SY <= SY_UI8; D_WE_RR <= IS_M1; when "1101110" => OP_CAT <= MOVE_dRR_dLL; LAST <= M3; D_WE_RR <= IS_M1; D_RD_O <= IS_M1; D_WE_O <= IS_M2; D_WE_LL <= IS_M3; PC_OP <= pc(IS_M1_M2, PC_WAIT); case OP_CYC is when M1 => -- decrement RR D_OP <= ALU_X_SUB_Y; D_SX <= SX_RR; D_SY <= SY_SY1; D_SA <= ADR_dRR; when M2 => -- write read memory D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_UM; D_SA <= ADR_dLL; when others => -- decrement LL D_OP <= ALU_X_SUB_Y; D_SX <= SX_LL; D_SY <= SY_SY1; end case; when "1101111" => OP_CAT <= MOVE_RRi_LLi; LAST <= M3; D_WE_RR <= IS_M1; D_RD_O <= IS_M1; D_WE_O <= IS_M2; D_WE_LL <= IS_M3; PC_OP <= pc(IS_M1_M2, PC_WAIT); case OP_CYC is when M1 => -- decrement RR D_OP <= ALU_X_ADD_Y; D_SX <= SX_RR; D_SY <= SY_SY1; D_SA <= ADR_RRi; when M2 => -- write read memory D_OP <= ALU_MOVE_Y; D_SX <= SX_ANY; D_SY <= SY_UM; D_SA <= ADR_dLL; when others => -- decrement LL D_OP <= ALU_X_ADD_Y; D_SX <= SX_LL; D_SY <= SY_SY1; end case; -- 77777777777777777777777777777777777777777777777777777777777777777777 when "1110000" => OP_CAT <= MUL_IS; D_OP <= ALU_MUL_IS; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "1110001" => OP_CAT <= MUL_IU; D_OP <= ALU_MUL_IU; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "1110010" => OP_CAT <= DIV_IS; D_OP <= ALU_DIV_IS; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "1110011" => OP_CAT <= DIV_IU; D_OP <= ALU_DIV_IU; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "1110100" => OP_CAT <= MD_STEP; D_OP <= ALU_MD_STP; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "1110101" => OP_CAT <= MD_FIN; D_OP <= ALU_MD_FIN; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "1110110" => OP_CAT <= MOD_FIN; D_OP <= ALU_MOD_FIN; D_SX <= SX_LL; D_SY <= SY_RR; D_WE_RR <= IS_M1; when "1110111" => OP_CAT <= EI; ENABLE_INT <= IS_M1; when "1111001" => OP_CAT <= DI; DISABLE_INT <= IS_M1; -- undefined -------------------------------------------------------- when others => end case; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity FeqDiv is Generic( width : integer ); Port( clkIn : in STD_LOGIC; clkOut : out STD_LOGIC); end FeqDiv; architecture Behavioral of FeqDiv is signal inner : STD_LOGIC_VECTOR(1 to width); attribute KEEP : string; attribute KEEP of clkIn: signal is "TRUE"; attribute KEEP of clkOut: signal is "TRUE"; attribute KEEP of inner: signal is "TRUE"; begin chain: for D in 1 to width generate begin chainBegin: if D = 1 generate begin process(clkIn) begin if rising_edge(clkIn) then inner(D) <= not inner(D); end if; end process; end generate; chainRest: if D /= 1 generate begin process(inner(D-1)) begin if rising_edge(inner(D-1)) then inner(D) <= not inner(D); end if; end process; end generate; end generate; clkOut <= inner(width); end Behavioral;
-- -*- vhdl -*- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- use work.cpu_btb_pkg.all; library ieee; use ieee.std_logic_1164.all; entity cpu_btb is port ( clk : in std_ulogic; rstn : in std_ulogic; cpu_btb_ctrl_in : in cpu_btb_ctrl_in_type; cpu_btb_dp_in : in cpu_btb_dp_in_type; cpu_btb_ctrl_out : out cpu_btb_ctrl_out_type; cpu_btb_dp_out : out cpu_btb_dp_out_type ); end entity;
------------------------------------------------------------------------------- -- xps_intc_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library xps_intc_v2_00_a; use xps_intc_v2_00_a.all; entity xps_intc_0_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 15); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 127); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 127); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 0); Sl_MWrErr : out std_logic_vector(0 to 0); Sl_MRdErr : out std_logic_vector(0 to 0); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 0); Intr : in std_logic_vector(6 downto 0); Irq : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of xps_intc_0_wrapper : entity is "xps_intc_v2_00_a"; end xps_intc_0_wrapper; architecture STRUCTURE of xps_intc_0_wrapper is component xps_intc is generic ( C_FAMILY : STRING; C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_NUM_INTR_INPUTS : INTEGER; C_KIND_OF_INTR : std_logic_vector(31 downto 0); C_KIND_OF_EDGE : std_logic_vector(31 downto 0); C_KIND_OF_LVL : std_logic_vector(31 downto 0); C_HAS_IPR : INTEGER; C_HAS_SIE : INTEGER; C_HAS_CIE : INTEGER; C_HAS_IVR : INTEGER; C_IRQ_IS_LEVEL : INTEGER; C_IRQ_ACTIVE : std_logic ); port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Intr : in std_logic_vector((C_NUM_INTR_INPUTS-1) downto 0); Irq : out std_logic ); end component; begin xps_intc_0 : xps_intc generic map ( C_FAMILY => "virtex5", C_BASEADDR => X"81800000", C_HIGHADDR => X"8180ffff", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 128, C_SPLB_P2P => 0, C_SPLB_NUM_MASTERS => 1, C_SPLB_MID_WIDTH => 1, C_SPLB_NATIVE_DWIDTH => 32, C_SPLB_SUPPORT_BURSTS => 0, C_NUM_INTR_INPUTS => 7, C_KIND_OF_INTR => B"11111111111111111111111110000100", C_KIND_OF_EDGE => B"11111111111111111111111111111111", C_KIND_OF_LVL => B"11111111111111111111111111110111", C_HAS_IPR => 1, C_HAS_SIE => 1, C_HAS_CIE => 1, C_HAS_IVR => 1, C_IRQ_IS_LEVEL => 1, C_IRQ_ACTIVE => '1' ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_PAValid => PLB_PAValid, PLB_masterID => PLB_masterID, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrDBus => PLB_wrDBus, PLB_UABus => PLB_UABus, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_MSize => PLB_MSize, PLB_lockErr => PLB_lockErr, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_rdDBus => Sl_rdDBus, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_wrBTerm => Sl_wrBTerm, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdBTerm => Sl_rdBTerm, Sl_MIRQ => Sl_MIRQ, Intr => Intr, Irq => Irq ); end architecture STRUCTURE;
architecture rtl of fifo is type t_record is record a : std_logic; b : std_logic; end record t_record; type t_record is RECORD a : std_logic; b : std_logic; end record t_record; begin end architecture rtl;
-------------------------------------------------------------------------------- -- Gideon's Logic Architectures - Copyright 2014 -- Entity: usb_host_controller -- Date:2015-01-18 -- Author: Gideon -- Description: -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.io_bus_pkg.all; use work.usb_pkg.all; use work.usb_cmd_pkg.all; entity usb_host_controller is generic ( g_simulation : boolean := false ); port ( clock : in std_logic; reset : in std_logic; ulpi_nxt : in std_logic; ulpi_dir : in std_logic; ulpi_stp : out std_logic; ulpi_data : inout std_logic_vector(7 downto 0); -- sys_clock : in std_logic; sys_reset : in std_logic; sys_io_req : in t_io_req; sys_io_resp : out t_io_resp ); end entity; architecture arch of usb_host_controller is signal nano_addr : unsigned(7 downto 0); signal nano_write : std_logic; signal nano_read : std_logic; signal nano_wdata : std_logic_vector(15 downto 0); signal nano_rdata : std_logic_vector(15 downto 0); signal nano_stall : std_logic := '0'; signal reg_read : std_logic := '0'; signal reg_write : std_logic := '0'; signal reg_ack : std_logic; signal reg_address : std_logic_vector(5 downto 0); signal reg_wdata : std_logic_vector(7 downto 0); signal reg_rdata : std_logic_vector(7 downto 0); signal status : std_logic_vector(7 downto 0); signal speed : std_logic_vector(1 downto 0) := "10"; signal do_chirp : std_logic; signal chirp_data : std_logic; signal sof_enable : std_logic; signal operational : std_logic; signal connected : std_logic; signal buf_address : unsigned(10 downto 0); signal buf_en : std_logic; signal buf_we : std_logic; signal buf_rdata : std_logic_vector(7 downto 0); signal buf_wdata : std_logic_vector(7 downto 0); signal usb_tx_req : t_usb_tx_req; signal usb_tx_resp : t_usb_tx_resp; signal usb_rx : t_usb_rx; signal usb_cmd_req : t_usb_cmd_req; signal usb_cmd_resp : t_usb_cmd_resp; signal io_data_rdata : std_logic_vector(7 downto 0); signal io_data_en : std_logic; signal io_data_ack : std_logic; signal io_reg_req : t_io_req; signal io_reg_resp : t_io_resp; signal io_nano_req : t_io_req; signal io_nano_resp : t_io_resp; signal io_data_req : t_io_req; signal io_data_resp : t_io_resp; signal io_usb_reg_req : t_io_req; signal io_usb_reg_resp : t_io_resp; begin i_split: entity work.io_bus_splitter generic map ( g_range_lo => 12, g_range_hi => 13, g_ports => 3 ) port map ( clock => sys_clock, req => sys_io_req, resp => sys_io_resp, reqs(0) => io_reg_req, reqs(1) => io_nano_req, reqs(2) => io_data_req, resps(0) => io_reg_resp, resps(1) => io_nano_resp, resps(2) => io_data_resp ); i_bridge: entity work.io_bus_bridge generic map ( g_addr_width => 4 ) port map ( clock_a => sys_clock, reset_a => sys_reset, req_a => io_reg_req, resp_a => io_reg_resp, clock_b => clock, reset_b => reset, req_b => io_usb_reg_req, resp_b => io_usb_reg_resp ); i_intf: entity work.usb_host_interface generic map ( g_simulation => g_simulation ) port map ( clock => clock, reset => reset, usb_rx => usb_rx, usb_tx_req => usb_tx_req, usb_tx_resp => usb_tx_resp, reg_read => reg_read, reg_write => reg_write, reg_address => reg_address, reg_wdata => reg_wdata, reg_rdata => reg_rdata, reg_ack => reg_ack, do_chirp => do_chirp, chirp_data => chirp_data, status => status, speed => speed, ulpi_nxt => ulpi_nxt, ulpi_stp => ulpi_stp, ulpi_dir => ulpi_dir, ulpi_data => ulpi_data ); i_seq: entity work.host_sequencer port map ( clock => clock, reset => reset, buf_address => buf_address, buf_en => buf_en, buf_we => buf_we, buf_rdata => buf_rdata, buf_wdata => buf_wdata, sof_enable => sof_enable, speed => speed, usb_cmd_req => usb_cmd_req, usb_cmd_resp => usb_cmd_resp, usb_rx => usb_rx, usb_tx_req => usb_tx_req, usb_tx_resp => usb_tx_resp ); i_mem: entity work.dpram generic map ( g_width_bits => 8, g_depth_bits => 11, g_storage => "block" ) port map ( a_clock => clock, a_address => buf_address, a_rdata => buf_rdata, a_wdata => buf_wdata, a_en => buf_en, a_we => buf_we, b_clock => sys_clock, b_address => io_data_req.address(10 downto 0), b_rdata => io_data_rdata, b_wdata => io_data_req.data, b_en => io_data_en, b_we => io_data_req.write ); process(sys_clock) begin if rising_edge(sys_clock) then io_data_ack <= io_data_req.read or io_data_req.write; end if; end process; io_data_en <= io_data_req.read or io_data_req.write; io_data_resp.data <= io_data_rdata when io_data_ack='1' else X"00"; io_data_resp.ack <= io_data_ack; io_data_resp.irq <= '0'; i_nano_io: entity work.nano_minimal_io generic map ( g_support_suspend => false ) port map ( clock => clock, reset => reset, io_addr => nano_addr, io_write => nano_write, io_read => nano_read, io_wdata => nano_wdata, io_rdata => nano_rdata, stall => nano_stall, reg_read => reg_read, reg_write => reg_write, reg_ack => reg_ack, reg_address => reg_address, reg_wdata => reg_wdata, reg_rdata => reg_rdata, status => status, do_chirp => do_chirp, chirp_data => chirp_data, connected => connected, operational => operational, suspended => open, sof_enable => sof_enable, speed => speed ); i_cmd_io: entity work.usb_cmd_io port map ( clock => clock, reset => reset, io_req => io_usb_reg_req, io_resp => io_usb_reg_resp, -- status (maybe only temporary) connected => connected, operational => operational, speed => speed, cmd_req => usb_cmd_req, cmd_resp => usb_cmd_resp ); i_nano: entity work.nano port map ( clock => clock, reset => reset, io_addr => nano_addr, io_write => nano_write, io_read => nano_read, io_wdata => nano_wdata, io_rdata => nano_rdata, stall => nano_stall, sys_clock => sys_clock, sys_reset => sys_reset, sys_io_req => io_nano_req, sys_io_resp => io_nano_resp ); end arch;
-------------------------------------------------------------------------------- -- Gideon's Logic Architectures - Copyright 2014 -- Entity: usb_host_controller -- Date:2015-01-18 -- Author: Gideon -- Description: -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.io_bus_pkg.all; use work.usb_pkg.all; use work.usb_cmd_pkg.all; entity usb_host_controller is generic ( g_simulation : boolean := false ); port ( clock : in std_logic; reset : in std_logic; ulpi_nxt : in std_logic; ulpi_dir : in std_logic; ulpi_stp : out std_logic; ulpi_data : inout std_logic_vector(7 downto 0); -- sys_clock : in std_logic; sys_reset : in std_logic; sys_io_req : in t_io_req; sys_io_resp : out t_io_resp ); end entity; architecture arch of usb_host_controller is signal nano_addr : unsigned(7 downto 0); signal nano_write : std_logic; signal nano_read : std_logic; signal nano_wdata : std_logic_vector(15 downto 0); signal nano_rdata : std_logic_vector(15 downto 0); signal nano_stall : std_logic := '0'; signal reg_read : std_logic := '0'; signal reg_write : std_logic := '0'; signal reg_ack : std_logic; signal reg_address : std_logic_vector(5 downto 0); signal reg_wdata : std_logic_vector(7 downto 0); signal reg_rdata : std_logic_vector(7 downto 0); signal status : std_logic_vector(7 downto 0); signal speed : std_logic_vector(1 downto 0) := "10"; signal do_chirp : std_logic; signal chirp_data : std_logic; signal sof_enable : std_logic; signal operational : std_logic; signal connected : std_logic; signal buf_address : unsigned(10 downto 0); signal buf_en : std_logic; signal buf_we : std_logic; signal buf_rdata : std_logic_vector(7 downto 0); signal buf_wdata : std_logic_vector(7 downto 0); signal usb_tx_req : t_usb_tx_req; signal usb_tx_resp : t_usb_tx_resp; signal usb_rx : t_usb_rx; signal usb_cmd_req : t_usb_cmd_req; signal usb_cmd_resp : t_usb_cmd_resp; signal io_data_rdata : std_logic_vector(7 downto 0); signal io_data_en : std_logic; signal io_data_ack : std_logic; signal io_reg_req : t_io_req; signal io_reg_resp : t_io_resp; signal io_nano_req : t_io_req; signal io_nano_resp : t_io_resp; signal io_data_req : t_io_req; signal io_data_resp : t_io_resp; signal io_usb_reg_req : t_io_req; signal io_usb_reg_resp : t_io_resp; begin i_split: entity work.io_bus_splitter generic map ( g_range_lo => 12, g_range_hi => 13, g_ports => 3 ) port map ( clock => sys_clock, req => sys_io_req, resp => sys_io_resp, reqs(0) => io_reg_req, reqs(1) => io_nano_req, reqs(2) => io_data_req, resps(0) => io_reg_resp, resps(1) => io_nano_resp, resps(2) => io_data_resp ); i_bridge: entity work.io_bus_bridge generic map ( g_addr_width => 4 ) port map ( clock_a => sys_clock, reset_a => sys_reset, req_a => io_reg_req, resp_a => io_reg_resp, clock_b => clock, reset_b => reset, req_b => io_usb_reg_req, resp_b => io_usb_reg_resp ); i_intf: entity work.usb_host_interface generic map ( g_simulation => g_simulation ) port map ( clock => clock, reset => reset, usb_rx => usb_rx, usb_tx_req => usb_tx_req, usb_tx_resp => usb_tx_resp, reg_read => reg_read, reg_write => reg_write, reg_address => reg_address, reg_wdata => reg_wdata, reg_rdata => reg_rdata, reg_ack => reg_ack, do_chirp => do_chirp, chirp_data => chirp_data, status => status, speed => speed, ulpi_nxt => ulpi_nxt, ulpi_stp => ulpi_stp, ulpi_dir => ulpi_dir, ulpi_data => ulpi_data ); i_seq: entity work.host_sequencer port map ( clock => clock, reset => reset, buf_address => buf_address, buf_en => buf_en, buf_we => buf_we, buf_rdata => buf_rdata, buf_wdata => buf_wdata, sof_enable => sof_enable, speed => speed, usb_cmd_req => usb_cmd_req, usb_cmd_resp => usb_cmd_resp, usb_rx => usb_rx, usb_tx_req => usb_tx_req, usb_tx_resp => usb_tx_resp ); i_mem: entity work.dpram generic map ( g_width_bits => 8, g_depth_bits => 11, g_storage => "block" ) port map ( a_clock => clock, a_address => buf_address, a_rdata => buf_rdata, a_wdata => buf_wdata, a_en => buf_en, a_we => buf_we, b_clock => sys_clock, b_address => io_data_req.address(10 downto 0), b_rdata => io_data_rdata, b_wdata => io_data_req.data, b_en => io_data_en, b_we => io_data_req.write ); process(sys_clock) begin if rising_edge(sys_clock) then io_data_ack <= io_data_req.read or io_data_req.write; end if; end process; io_data_en <= io_data_req.read or io_data_req.write; io_data_resp.data <= io_data_rdata when io_data_ack='1' else X"00"; io_data_resp.ack <= io_data_ack; io_data_resp.irq <= '0'; i_nano_io: entity work.nano_minimal_io generic map ( g_support_suspend => false ) port map ( clock => clock, reset => reset, io_addr => nano_addr, io_write => nano_write, io_read => nano_read, io_wdata => nano_wdata, io_rdata => nano_rdata, stall => nano_stall, reg_read => reg_read, reg_write => reg_write, reg_ack => reg_ack, reg_address => reg_address, reg_wdata => reg_wdata, reg_rdata => reg_rdata, status => status, do_chirp => do_chirp, chirp_data => chirp_data, connected => connected, operational => operational, suspended => open, sof_enable => sof_enable, speed => speed ); i_cmd_io: entity work.usb_cmd_io port map ( clock => clock, reset => reset, io_req => io_usb_reg_req, io_resp => io_usb_reg_resp, -- status (maybe only temporary) connected => connected, operational => operational, speed => speed, cmd_req => usb_cmd_req, cmd_resp => usb_cmd_resp ); i_nano: entity work.nano port map ( clock => clock, reset => reset, io_addr => nano_addr, io_write => nano_write, io_read => nano_read, io_wdata => nano_wdata, io_rdata => nano_rdata, stall => nano_stall, sys_clock => sys_clock, sys_reset => sys_reset, sys_io_req => io_nano_req, sys_io_resp => io_nano_resp ); end arch;
library IEEE; use IEEE.std_logic_1164.all; entity SCIT1 is port (A, B, CIN : in std_logic; COUT, S : out std_logic ); end entity SCIT1; architecture SCIT1_BODY of SCIT1 is begin VYSTUP : process (A, B, CIN) begin S <= A xor B xor CIN after 2 ns; end process; PRENOS : process (A, B, CIN) begin COUT <= (CIN and A) or (CIN and B) or (A and B) after 3 ns; --wait on A, B, CIN; end process; end architecture SCIT1_BODY;
--================================================================================================================================ -- Copyright 2020 Bitvis -- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. -- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT. -- -- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on -- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and limitations under the License. --================================================================================================================================ -- Note : Any functionality not explicitly described in the documentation is subject to change at any time ---------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------- -- Description : See library quick reference (under 'doc') and README-file(s) --------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; library std; use std.textio.all; --================================================================================================================================ --================================================================================================================================ package gmii_bfm_pkg is --========================================================================================== -- Types and constants for GMII BFM --========================================================================================== constant C_SCOPE : string := "GMII BFM"; -- Interface record for BFM signals to DUT type t_gmii_tx_if is record gtxclk : std_logic; txd : std_logic_vector(7 downto 0); txen : std_logic; end record; -- Interface record for BFM signals from DUT type t_gmii_rx_if is record rxclk : std_logic; rxd : std_logic_vector(7 downto 0); rxdv : std_logic; end record; -- Configuration record to be assigned in the test harness. type t_gmii_bfm_config is record max_wait_cycles : integer; -- Used for setting the maximum cycles to wait before an alert is issued when -- waiting for signals from the DUT. max_wait_cycles_severity : t_alert_level; -- Severity if max_wait_cycles expires. clock_period : time; -- Period of the clock signal. clock_period_margin : time; -- Input clock period margin to specified clock_period clock_margin_severity : t_alert_level; -- The above margin will have this severity setup_time : time; -- Setup time for generated signals, set to clock_period/4 hold_time : time; -- Hold time for generated signals, set to clock_period/4 bfm_sync : t_bfm_sync; -- Synchronisation of the BFM procedures, i.e. using clock signals, using setup_time and hold_time. match_strictness : t_match_strictness; -- Matching strictness for std_logic values in check procedures. id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the BFM end record; -- Define the default value for the BFM config constant C_GMII_BFM_CONFIG_DEFAULT : t_gmii_bfm_config := ( max_wait_cycles => 12, -- Standard minimum interpacket gap (Gigabith Ethernet) max_wait_cycles_severity => ERROR, clock_period => -1 ns, clock_period_margin => 0 ns, clock_margin_severity => TB_ERROR, setup_time => -1 ns, hold_time => -1 ns, bfm_sync => SYNC_ON_CLOCK_ONLY, match_strictness => MATCH_EXACT, id_for_bfm => ID_BFM ); --========================================================================================== -- BFM procedures --========================================================================================== -- This function returns a GMII interface with initialized signals. -- All input signals are initialized to 0 -- All output signals are initialized to Z function init_gmii_if_signals return t_gmii_tx_if; function init_gmii_if_signals return t_gmii_rx_if; --------------------------------------------------------------------------------------------- -- GMII Write -- BFM -> DUT --------------------------------------------------------------------------------------------- procedure gmii_write ( constant data_array : in t_slv_array; constant msg : in string := ""; signal gmii_tx_if : inout t_gmii_tx_if; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_gmii_bfm_config := C_GMII_BFM_CONFIG_DEFAULT ); --------------------------------------------------------------------------------------------- -- GMII Read -- DUT -> BFM --------------------------------------------------------------------------------------------- procedure gmii_read ( variable data_array : out t_slv_array; variable data_len : out natural; constant msg : in string := ""; signal gmii_rx_if : inout t_gmii_rx_if; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_gmii_bfm_config := C_GMII_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ); --------------------------------------------------------------------------------------------- -- GMII Expect --------------------------------------------------------------------------------------------- procedure gmii_expect ( constant data_exp : in t_slv_array; constant msg : in string := ""; signal gmii_rx_if : inout t_gmii_rx_if; constant alert_level : in t_alert_level := ERROR; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_gmii_bfm_config := C_GMII_BFM_CONFIG_DEFAULT ); end package gmii_bfm_pkg; --================================================================================================================================ --================================================================================================================================ package body gmii_bfm_pkg is function init_gmii_if_signals return t_gmii_tx_if is variable init_if : t_gmii_tx_if; begin init_if.gtxclk := 'Z'; init_if.txd := (init_if.txd'range => '0'); init_if.txen := '0'; return init_if; end function; function init_gmii_if_signals return t_gmii_rx_if is variable init_if : t_gmii_rx_if; begin init_if.rxclk := 'Z'; init_if.rxd := (init_if.rxd'range => 'Z'); init_if.rxdv := 'Z'; return init_if; end function; --------------------------------------------------------------------------------------------- -- GMII Write -- BFM -> DUT --------------------------------------------------------------------------------------------- procedure gmii_write( constant data_array : in t_slv_array; constant msg : in string := ""; signal gmii_tx_if : inout t_gmii_tx_if; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_gmii_bfm_config := C_GMII_BFM_CONFIG_DEFAULT ) is constant proc_name : string := "gmii_write"; constant proc_call : string := proc_name & "(" & to_string(data_array'length) & " bytes)"; variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking begin check_value(data_array'ascending, TB_FAILURE, "Sanity check: Check that data_array is ascending (defined with 'to'), for byte order clarity.", scope, ID_NEVER, msg_id_panel, proc_call); if config.bfm_sync = SYNC_WITH_SETUP_AND_HOLD then check_value(config.clock_period > -1 ns, TB_FAILURE, "Sanity check: Check that clock_period is set.", scope, ID_NEVER, msg_id_panel, proc_call); check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call); check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call); end if; gmii_tx_if <= init_gmii_if_signals; -- Wait according to config.bfm_sync setup wait_on_bfm_sync_start(gmii_tx_if.gtxclk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge); log(config.id_for_bfm, proc_call & "=> " & add_msg_delimiter(msg), scope, msg_id_panel); -- Write all the bytes in the data_array for i in data_array'range loop gmii_tx_if.txd <= data_array(i); gmii_tx_if.txen <= '1'; -- Check the clock margin wait until rising_edge(gmii_tx_if.gtxclk); if v_time_of_rising_edge < 0 ns then v_time_of_rising_edge := now; end if; check_clock_period_margin(gmii_tx_if.gtxclk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge, config.clock_period, config.clock_period_margin, config.clock_margin_severity); -- Wait according to config.bfm_sync setup wait_on_bfm_exit(gmii_tx_if.gtxclk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge); end loop; gmii_tx_if <= init_gmii_if_signals; log(config.id_for_bfm, proc_call & " DONE. " & add_msg_delimiter(msg), scope, msg_id_panel); end procedure; --------------------------------------------------------------------------------------------- -- GMII Read -- DUT -> BFM --------------------------------------------------------------------------------------------- procedure gmii_read( variable data_array : out t_slv_array; variable data_len : out natural; constant msg : in string := ""; signal gmii_rx_if : inout t_gmii_rx_if; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_gmii_bfm_config := C_GMII_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ) is constant local_proc_name : string := "gmii_read"; -- Internal proc_name; Used if called from sequencer or VVC constant local_proc_call : string := local_proc_name & "(" & to_string(data_array'length) & " bytes)"; variable v_proc_call : line; -- Current proc_call, external or local variable v_normalized_data : t_slv_array(0 to data_array'length-1)(7 downto 0); variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking variable v_byte_cnt : natural := 0; variable v_done : boolean := false; variable v_timeout : boolean := false; variable v_wait_cycles : natural := 0; begin if ext_proc_call = "" then -- Called directly from sequencer/VVC, log 'gmii_read...' write(v_proc_call, local_proc_call); else -- Called from another BFM procedure, log 'ext_proc_call while executing gmii_read...' write(v_proc_call, ext_proc_call & " while executing " & local_proc_name); end if; check_value(data_array'ascending, TB_FAILURE, "Sanity check: Check that data_array is ascending (defined with 'to'), for byte order clarity.", scope, ID_NEVER, msg_id_panel, v_proc_call.all); if config.bfm_sync = SYNC_WITH_SETUP_AND_HOLD then check_value(config.clock_period > -1 ns, TB_FAILURE, "Sanity check: Check that clock_period is set.", scope, ID_NEVER, msg_id_panel, v_proc_call.all); check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, v_proc_call.all); check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, v_proc_call.all); end if; gmii_rx_if <= init_gmii_if_signals; -- Wait according to config.bfm_sync setup wait_on_bfm_sync_start(gmii_rx_if.rxclk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge); log(config.id_for_bfm, v_proc_call.all & "=> " & add_msg_delimiter(msg), scope, msg_id_panel); -- Wait for the first rising edge to sample the data and check the clock margin wait until rising_edge(gmii_rx_if.rxclk); v_time_of_rising_edge := now; check_clock_period_margin(gmii_rx_if.rxclk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge, config.clock_period, config.clock_period_margin, config.clock_margin_severity); -- Wait for data valid to be active while gmii_rx_if.rxdv /= '1' and v_wait_cycles < config.max_wait_cycles loop wait_on_bfm_sync_start(gmii_rx_if.rxclk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge); wait until rising_edge(gmii_rx_if.rxclk); v_wait_cycles := v_wait_cycles + 1; end loop; if gmii_rx_if.rxdv /= '1' then v_timeout := true; v_done := true; end if; -- Sample the data while not(v_done) loop if gmii_rx_if.rxdv = '1' then v_normalized_data(v_byte_cnt) := gmii_rx_if.rxd; if v_byte_cnt = v_normalized_data'length-1 then v_done := true; else wait_on_bfm_exit(gmii_rx_if.rxclk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge); wait until rising_edge(gmii_rx_if.rxclk); end if; v_byte_cnt := v_byte_cnt + 1; else -- Data valid went low v_done := true; end if; end loop; data_array := v_normalized_data; data_len := v_byte_cnt; -- Wait according to bfm_sync config if not(v_timeout) then wait_on_bfm_exit(gmii_rx_if.rxclk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge); end if; -- Done. Check if there was a timeout or it was successful if v_timeout then alert(config.max_wait_cycles_severity, v_proc_call.all & "=> Failed. Timeout while waiting for valid data. " & add_msg_delimiter(msg), scope); else if ext_proc_call = "" then log(config.id_for_bfm, v_proc_call.all & " DONE. " & add_msg_delimiter(msg), scope, msg_id_panel); else -- Log will be handled by calling procedure (e.g. gmii_expect) end if; end if; DEALLOCATE(v_proc_call); end procedure; --------------------------------------------------------------------------------------------- -- GMII Expect --------------------------------------------------------------------------------------------- procedure gmii_expect ( constant data_exp : in t_slv_array; constant msg : in string := ""; signal gmii_rx_if : inout t_gmii_rx_if; constant alert_level : in t_alert_level := ERROR; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_gmii_bfm_config := C_GMII_BFM_CONFIG_DEFAULT ) is constant proc_name : string := "gmii_expect"; constant proc_call : string := proc_name & "(" & to_string(data_exp'length) & " bytes)"; variable v_normalized_data : t_slv_array(0 to data_exp'length-1)(7 downto 0) := data_exp; variable v_rx_data_array : t_slv_array(v_normalized_data'range)(7 downto 0); variable v_rx_data_len : natural; variable v_length_error : boolean := false; variable v_data_error_cnt : natural := 0; variable v_first_wrong_byte : natural; variable v_alert_radix : t_radix; begin check_value(data_exp'ascending, TB_FAILURE, "Sanity check: Check that data_exp is ascending (defined with 'to'), for byte order clarity.", scope, ID_NEVER, msg_id_panel, proc_call); -- Read data gmii_read(v_rx_data_array, v_rx_data_len, msg, gmii_rx_if, scope, msg_id_panel, config, proc_call); -- Check the length of the received data if v_rx_data_len /= v_normalized_data'length then v_length_error := true; end if; -- Check if each received bit matches the expected. -- Report the first wrong byte (iterate from the last to the first) for byte in v_rx_data_array'high downto 0 loop for i in v_rx_data_array(byte)'range loop -- Allow don't care in expected value and use match strictness from config for comparison if v_normalized_data(byte)(i) = '-' or check_value(v_rx_data_array(byte)(i), v_normalized_data(byte)(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then -- Check is OK else -- Received byte doesn't match v_data_error_cnt := v_data_error_cnt + 1; v_first_wrong_byte := byte; end if; end loop; end loop; -- Done. Report result if v_length_error then alert(alert_level, proc_call & "=> Failed. Mismatch in received data length. Was " & to_string(v_rx_data_len) & ". Expected " & to_string(v_normalized_data'length) & "." & LF & add_msg_delimiter(msg), scope); elsif v_data_error_cnt /= 0 then -- Use binary representation when mismatch is due to weak signals v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_data_array(v_first_wrong_byte), v_normalized_data(v_first_wrong_byte), MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX; alert(alert_level, proc_call & "=> Failed in "& to_string(v_data_error_cnt) & " data bits. First mismatch in byte# " & to_string(v_first_wrong_byte) & ". Was " & to_string(v_rx_data_array(v_first_wrong_byte), v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(v_normalized_data(v_first_wrong_byte), v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope); else log(config.id_for_bfm, proc_call & "=> OK, received " & to_string(v_rx_data_array'length) & " bytes. " & add_msg_delimiter(msg), scope, msg_id_panel); end if; end procedure; end package body gmii_bfm_pkg;
------------------------------------------------------------------------------ ---- ---- ---- Lattuino CPU configuration ---- ---- ---- ---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ---- ---- ---- ---- Description: ---- ---- Configuration parameters for the Lattuino CPU. ---- ---- ---- ---- To Do: ---- ---- - ---- ---- ---- ---- Author: ---- ---- - Salvador E. Tropea, salvador en inti.gob.ar ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Copyright (c) 2017 Salvador E. Tropea <salvador en inti.gob.ar> ---- ---- Copyright (c) 2017 Instituto Nacional de Tecnología Industrial ---- ---- ---- ---- Distributed under the GPL v2 or newer license ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Design unit: CPUConfig (Package) ---- ---- File name: cpuconfig.vhdl ---- ---- Note: None ---- ---- Limitations: None known ---- ---- Errors: None known ---- ---- Library: lattuino ---- ---- Dependencies: IEEE.std_logic_1164 ---- ---- IEEE.numeric_std ---- ---- SPI.Devices ---- ---- Target FPGA: iCE40HX4K-TQ144 ---- ---- Language: VHDL ---- ---- Wishbone: None ---- ---- Synthesis tools: Lattice iCECube2 2016.02.27810 ---- ---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- ---- Text editor: SETEdit 0.5.x ---- ---- ---- ------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; package CPUConfig is -- SPI support constant ENABLE_SPI : std_logic:='1'; -- Use a PLL to achieve SCK<=F_CLK and not half constant ENA_2xSCK : boolean:=true; -- Clock Frequency -- IMPORTANT! any change here needs a review of the PLL FILTER_RANGE constant F_CLK : natural:=24e6; -- UART baudrate constant BAUD_RATE : natural:=115200; -- Starting address for the bootloader (in words) constant RESET_JUMP : natural:=3768; -- tn25: 696, 45: 1720, 85: 3768 -- RAM address width constant RAM_ADDR_W : positive:=9; -- tn25: 7 45: 8 85: 9 (128 to 512 b) -- ROM address width constant ROM_ADDR_W : positive:=12; -- tn25: 10 45: 11 85: 12 (2/4/8 kib) -- CapSense button 1 is used as RESET constant ENABLE_B1_RESET : boolean:=true; -- PWMs support constant ENA_PWM0 : boolean:=true; constant ENA_PWM1 : boolean:=true; constant ENA_PWM2 : boolean:=true; constant ENA_PWM3 : boolean:=true; constant ENA_PWM4 : boolean:=true; constant ENA_PWM5 : boolean:=true; -- Interrupt pins support constant ENA_INT0 : boolean:=true; constant ENA_INT1 : boolean:=true; -- Micro and miliseconds timer constant ENA_TIME_CNT : std_logic:='1'; -- 16 bits timer (for Tone generation) constant ENA_TMR16 : std_logic:='1'; -- A/D converter support constant ENABLE_AD : std_logic:='1'; end package CPUConfig;
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2013 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file fifo_mem.vhd when simulating -- the core, fifo_mem. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY fifo_mem IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END fifo_mem; ARCHITECTURE fifo_mem_a OF fifo_mem IS -- synthesis translate_off COMPONENT wrapped_fifo_mem PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_fifo_mem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) GENERIC MAP ( c_addra_width => 11, c_addrb_width => 11, c_algorithm => 1, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 1, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_enable_32bit_address => 0, c_family => "spartan3", c_has_axi_id => 0, c_has_ena => 0, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file => "BlankString", c_init_file_name => "fifo_mem.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 1, c_mux_pipeline_stages => 0, c_prim_type => 1, c_read_depth_a => 2048, c_read_depth_b => 2048, c_read_width_a => 8, c_read_width_b => 8, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_bram_block => 0, c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 1, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 2048, c_write_depth_b => 2048, c_write_mode_a => "WRITE_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 8, c_write_width_b => 8, c_xdevicefamily => "spartan3e" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_fifo_mem PORT MAP ( clka => clka, wea => wea, addra => addra, dina => dina, clkb => clkb, addrb => addrb, doutb => doutb ); -- synthesis translate_on END fifo_mem_a;
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2013 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file fifo_mem.vhd when simulating -- the core, fifo_mem. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY fifo_mem IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END fifo_mem; ARCHITECTURE fifo_mem_a OF fifo_mem IS -- synthesis translate_off COMPONENT wrapped_fifo_mem PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_fifo_mem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) GENERIC MAP ( c_addra_width => 11, c_addrb_width => 11, c_algorithm => 1, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 1, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_enable_32bit_address => 0, c_family => "spartan3", c_has_axi_id => 0, c_has_ena => 0, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file => "BlankString", c_init_file_name => "fifo_mem.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 1, c_mux_pipeline_stages => 0, c_prim_type => 1, c_read_depth_a => 2048, c_read_depth_b => 2048, c_read_width_a => 8, c_read_width_b => 8, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_bram_block => 0, c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 1, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 2048, c_write_depth_b => 2048, c_write_mode_a => "WRITE_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 8, c_write_width_b => 8, c_xdevicefamily => "spartan3e" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_fifo_mem PORT MAP ( clka => clka, wea => wea, addra => addra, dina => dina, clkb => clkb, addrb => addrb, doutb => doutb ); -- synthesis translate_on END fifo_mem_a;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA package bus_monitor_pkg is type stats_type is record ifetch_freq, write_freq, read_freq : real; end record stats_type; component bus_monitor is generic ( verbose, dump_stats : boolean := false ); port ( mem_req, ifetch, write : in bit; bus_stats : out stats_type ); end component bus_monitor; end package bus_monitor_pkg; use work.bus_monitor_pkg.all; entity bus_monitor is generic ( verbose, dump_stats : boolean := false ); port ( mem_req, ifetch, write : in bit; bus_stats : out stats_type ); end entity bus_monitor; architecture general_purpose of bus_monitor is begin access_monitor : process is variable access_count, ifetch_count, write_count, read_count : natural := 0; use std.textio; variable L : textio.line; begin wait until mem_req = '1'; if ifetch = '1' then ifetch_count := ifetch_count + 1; if verbose then textio.write(L, string'("Ifetch")); textio.writeline(textio.output, L); end if; elsif write = '1' then write_count := write_count + 1; if verbose then textio.write(L, string'("Write")); textio.writeline(textio.output, L); end if; else read_count := read_count + 1; if verbose then textio.write(L, string'("Read")); textio.writeline(textio.output, L); end if; end if; access_count := access_count + 1; bus_stats.ifetch_freq <= real(ifetch_count) / real(access_count); bus_stats.write_freq <= real(write_count) / real(access_count); bus_stats.read_freq <= real(read_count) / real(access_count); if dump_stats and access_count mod 5 = 0 then textio.write(L, string'("Ifetch frequency = ")); textio.write(L, real(ifetch_count) / real(access_count)); textio.writeline(textio.output, L); textio.write(L, string'("Write frequency = ")); textio.write(L, real(write_count) / real(access_count)); textio.writeline(textio.output, L); textio.write(L, string'("Read frequency = ")); textio.write(L, real(read_count) / real(access_count)); textio.writeline(textio.output, L); end if; end process access_monitor; end architecture general_purpose; -- code from book (in text) entity computer_system is generic ( instrumented : boolean := false ); port ( -- . . . ); -- not in book other_port : in bit := '0' ); -- end not in book end entity computer_system; -- end code from book -- code from book architecture block_level of computer_system is -- . . . -- type and component declarations for cpu and memory, etc. signal clock : bit; -- the system clock signal mem_req : bit; -- cpu access request to memory signal ifetch : bit; -- indicates access is to fetch an instruction signal write : bit; -- indicates access is a write -- . . . -- other signal declarations begin -- . . . -- component instances for cpu and memory, etc. instrumentation : if instrumented generate use work.bus_monitor_pkg; signal bus_stats : bus_monitor_pkg.stats_type; begin cpu_bus_monitor : component bus_monitor_pkg.bus_monitor port map ( mem_req, ifetch, write, bus_stats ); end generate instrumentation; -- not in book stimulus : process is begin ifetch <= '1'; write <= '0'; mem_req <= '1', '0' after 10 ns; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '1'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '0'; wait for 20 ns; wait; end process stimulus; -- end not in book end architecture block_level; -- end code from book
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA package bus_monitor_pkg is type stats_type is record ifetch_freq, write_freq, read_freq : real; end record stats_type; component bus_monitor is generic ( verbose, dump_stats : boolean := false ); port ( mem_req, ifetch, write : in bit; bus_stats : out stats_type ); end component bus_monitor; end package bus_monitor_pkg; use work.bus_monitor_pkg.all; entity bus_monitor is generic ( verbose, dump_stats : boolean := false ); port ( mem_req, ifetch, write : in bit; bus_stats : out stats_type ); end entity bus_monitor; architecture general_purpose of bus_monitor is begin access_monitor : process is variable access_count, ifetch_count, write_count, read_count : natural := 0; use std.textio; variable L : textio.line; begin wait until mem_req = '1'; if ifetch = '1' then ifetch_count := ifetch_count + 1; if verbose then textio.write(L, string'("Ifetch")); textio.writeline(textio.output, L); end if; elsif write = '1' then write_count := write_count + 1; if verbose then textio.write(L, string'("Write")); textio.writeline(textio.output, L); end if; else read_count := read_count + 1; if verbose then textio.write(L, string'("Read")); textio.writeline(textio.output, L); end if; end if; access_count := access_count + 1; bus_stats.ifetch_freq <= real(ifetch_count) / real(access_count); bus_stats.write_freq <= real(write_count) / real(access_count); bus_stats.read_freq <= real(read_count) / real(access_count); if dump_stats and access_count mod 5 = 0 then textio.write(L, string'("Ifetch frequency = ")); textio.write(L, real(ifetch_count) / real(access_count)); textio.writeline(textio.output, L); textio.write(L, string'("Write frequency = ")); textio.write(L, real(write_count) / real(access_count)); textio.writeline(textio.output, L); textio.write(L, string'("Read frequency = ")); textio.write(L, real(read_count) / real(access_count)); textio.writeline(textio.output, L); end if; end process access_monitor; end architecture general_purpose; -- code from book (in text) entity computer_system is generic ( instrumented : boolean := false ); port ( -- . . . ); -- not in book other_port : in bit := '0' ); -- end not in book end entity computer_system; -- end code from book -- code from book architecture block_level of computer_system is -- . . . -- type and component declarations for cpu and memory, etc. signal clock : bit; -- the system clock signal mem_req : bit; -- cpu access request to memory signal ifetch : bit; -- indicates access is to fetch an instruction signal write : bit; -- indicates access is a write -- . . . -- other signal declarations begin -- . . . -- component instances for cpu and memory, etc. instrumentation : if instrumented generate use work.bus_monitor_pkg; signal bus_stats : bus_monitor_pkg.stats_type; begin cpu_bus_monitor : component bus_monitor_pkg.bus_monitor port map ( mem_req, ifetch, write, bus_stats ); end generate instrumentation; -- not in book stimulus : process is begin ifetch <= '1'; write <= '0'; mem_req <= '1', '0' after 10 ns; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '1'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '0'; wait for 20 ns; wait; end process stimulus; -- end not in book end architecture block_level; -- end code from book
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA package bus_monitor_pkg is type stats_type is record ifetch_freq, write_freq, read_freq : real; end record stats_type; component bus_monitor is generic ( verbose, dump_stats : boolean := false ); port ( mem_req, ifetch, write : in bit; bus_stats : out stats_type ); end component bus_monitor; end package bus_monitor_pkg; use work.bus_monitor_pkg.all; entity bus_monitor is generic ( verbose, dump_stats : boolean := false ); port ( mem_req, ifetch, write : in bit; bus_stats : out stats_type ); end entity bus_monitor; architecture general_purpose of bus_monitor is begin access_monitor : process is variable access_count, ifetch_count, write_count, read_count : natural := 0; use std.textio; variable L : textio.line; begin wait until mem_req = '1'; if ifetch = '1' then ifetch_count := ifetch_count + 1; if verbose then textio.write(L, string'("Ifetch")); textio.writeline(textio.output, L); end if; elsif write = '1' then write_count := write_count + 1; if verbose then textio.write(L, string'("Write")); textio.writeline(textio.output, L); end if; else read_count := read_count + 1; if verbose then textio.write(L, string'("Read")); textio.writeline(textio.output, L); end if; end if; access_count := access_count + 1; bus_stats.ifetch_freq <= real(ifetch_count) / real(access_count); bus_stats.write_freq <= real(write_count) / real(access_count); bus_stats.read_freq <= real(read_count) / real(access_count); if dump_stats and access_count mod 5 = 0 then textio.write(L, string'("Ifetch frequency = ")); textio.write(L, real(ifetch_count) / real(access_count)); textio.writeline(textio.output, L); textio.write(L, string'("Write frequency = ")); textio.write(L, real(write_count) / real(access_count)); textio.writeline(textio.output, L); textio.write(L, string'("Read frequency = ")); textio.write(L, real(read_count) / real(access_count)); textio.writeline(textio.output, L); end if; end process access_monitor; end architecture general_purpose; -- code from book (in text) entity computer_system is generic ( instrumented : boolean := false ); port ( -- . . . ); -- not in book other_port : in bit := '0' ); -- end not in book end entity computer_system; -- end code from book -- code from book architecture block_level of computer_system is -- . . . -- type and component declarations for cpu and memory, etc. signal clock : bit; -- the system clock signal mem_req : bit; -- cpu access request to memory signal ifetch : bit; -- indicates access is to fetch an instruction signal write : bit; -- indicates access is a write -- . . . -- other signal declarations begin -- . . . -- component instances for cpu and memory, etc. instrumentation : if instrumented generate use work.bus_monitor_pkg; signal bus_stats : bus_monitor_pkg.stats_type; begin cpu_bus_monitor : component bus_monitor_pkg.bus_monitor port map ( mem_req, ifetch, write, bus_stats ); end generate instrumentation; -- not in book stimulus : process is begin ifetch <= '1'; write <= '0'; mem_req <= '1', '0' after 10 ns; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '1'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '0'; wait for 20 ns; wait; end process stimulus; -- end not in book end architecture block_level; -- end code from book
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2016.1 -- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity doImgProc is generic ( C_S_AXI_CRTL_BUS_ADDR_WIDTH : INTEGER := 5; C_S_AXI_CRTL_BUS_DATA_WIDTH : INTEGER := 32; C_S_AXI_KERNEL_BUS_ADDR_WIDTH : INTEGER := 5; C_S_AXI_KERNEL_BUS_DATA_WIDTH : INTEGER := 32 ); port ( ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; inStream_TDATA : IN STD_LOGIC_VECTOR (7 downto 0); inStream_TVALID : IN STD_LOGIC; inStream_TREADY : OUT STD_LOGIC; inStream_TKEEP : IN STD_LOGIC_VECTOR (0 downto 0); inStream_TSTRB : IN STD_LOGIC_VECTOR (0 downto 0); inStream_TUSER : IN STD_LOGIC_VECTOR (1 downto 0); inStream_TLAST : IN STD_LOGIC_VECTOR (0 downto 0); inStream_TID : IN STD_LOGIC_VECTOR (4 downto 0); inStream_TDEST : IN STD_LOGIC_VECTOR (5 downto 0); outStream_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0); outStream_TVALID : OUT STD_LOGIC; outStream_TREADY : IN STD_LOGIC; outStream_TKEEP : OUT STD_LOGIC_VECTOR (0 downto 0); outStream_TSTRB : OUT STD_LOGIC_VECTOR (0 downto 0); outStream_TUSER : OUT STD_LOGIC_VECTOR (1 downto 0); outStream_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0); outStream_TID : OUT STD_LOGIC_VECTOR (4 downto 0); outStream_TDEST : OUT STD_LOGIC_VECTOR (5 downto 0); s_axi_CRTL_BUS_AWVALID : IN STD_LOGIC; s_axi_CRTL_BUS_AWREADY : OUT STD_LOGIC; s_axi_CRTL_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_ADDR_WIDTH-1 downto 0); s_axi_CRTL_BUS_WVALID : IN STD_LOGIC; s_axi_CRTL_BUS_WREADY : OUT STD_LOGIC; s_axi_CRTL_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH-1 downto 0); s_axi_CRTL_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH/8-1 downto 0); s_axi_CRTL_BUS_ARVALID : IN STD_LOGIC; s_axi_CRTL_BUS_ARREADY : OUT STD_LOGIC; s_axi_CRTL_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_ADDR_WIDTH-1 downto 0); s_axi_CRTL_BUS_RVALID : OUT STD_LOGIC; s_axi_CRTL_BUS_RREADY : IN STD_LOGIC; s_axi_CRTL_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH-1 downto 0); s_axi_CRTL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_CRTL_BUS_BVALID : OUT STD_LOGIC; s_axi_CRTL_BUS_BREADY : IN STD_LOGIC; s_axi_CRTL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); interrupt : OUT STD_LOGIC; s_axi_KERNEL_BUS_AWVALID : IN STD_LOGIC; s_axi_KERNEL_BUS_AWREADY : OUT STD_LOGIC; s_axi_KERNEL_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_ADDR_WIDTH-1 downto 0); s_axi_KERNEL_BUS_WVALID : IN STD_LOGIC; s_axi_KERNEL_BUS_WREADY : OUT STD_LOGIC; s_axi_KERNEL_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH-1 downto 0); s_axi_KERNEL_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH/8-1 downto 0); s_axi_KERNEL_BUS_ARVALID : IN STD_LOGIC; s_axi_KERNEL_BUS_ARREADY : OUT STD_LOGIC; s_axi_KERNEL_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_ADDR_WIDTH-1 downto 0); s_axi_KERNEL_BUS_RVALID : OUT STD_LOGIC; s_axi_KERNEL_BUS_RREADY : IN STD_LOGIC; s_axi_KERNEL_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH-1 downto 0); s_axi_KERNEL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_KERNEL_BUS_BVALID : OUT STD_LOGIC; s_axi_KERNEL_BUS_BREADY : IN STD_LOGIC; s_axi_KERNEL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0) ); end; architecture behav of doImgProc is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "doImgProc,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.340000,HLS_SYN_LAT=2359816,HLS_SYN_TPT=none,HLS_SYN_MEM=5,HLS_SYN_DSP=9,HLS_SYN_FF=1034,HLS_SYN_LUT=1363}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001"; constant ap_ST_pp0_stg0_fsm_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010"; constant ap_ST_pp0_stg1_fsm_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100"; constant ap_ST_pp0_stg2_fsm_3 : STD_LOGIC_VECTOR (10 downto 0) := "00000001000"; constant ap_ST_pp0_stg3_fsm_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000010000"; constant ap_ST_pp0_stg4_fsm_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000100000"; constant ap_ST_pp0_stg5_fsm_6 : STD_LOGIC_VECTOR (10 downto 0) := "00001000000"; constant ap_ST_pp0_stg6_fsm_7 : STD_LOGIC_VECTOR (10 downto 0) := "00010000000"; constant ap_ST_pp0_stg7_fsm_8 : STD_LOGIC_VECTOR (10 downto 0) := "00100000000"; constant ap_ST_pp0_stg8_fsm_9 : STD_LOGIC_VECTOR (10 downto 0) := "01000000000"; constant ap_ST_st17_fsm_10 : STD_LOGIC_VECTOR (10 downto 0) := "10000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv19_1 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000001"; constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000"; constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001"; constant ap_const_lv64_2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010"; constant ap_const_lv64_3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000011"; constant ap_const_lv64_4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100"; constant ap_const_lv64_5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000101"; constant ap_const_lv64_6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000110"; constant ap_const_lv64_7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000111"; constant ap_const_lv64_8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; constant ap_const_lv19_40001 : STD_LOGIC_VECTOR (18 downto 0) := "1000000000000000001"; constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111"; constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000"; constant ap_const_lv32_1FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111111111"; constant ap_const_lv19_201 : STD_LOGIC_VECTOR (18 downto 0) := "0000000001000000001"; constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv17_0 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv15_0 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000000"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv10_201 : STD_LOGIC_VECTOR (9 downto 0) := "1000000001"; constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001"; signal ap_rst_n_inv : STD_LOGIC; signal ap_start : STD_LOGIC; signal ap_done : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_CS_fsm : STD_LOGIC_VECTOR (10 downto 0) := "00000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_28 : BOOLEAN; signal ap_ready : STD_LOGIC; signal kernel_address0 : STD_LOGIC_VECTOR (3 downto 0); signal kernel_ce0 : STD_LOGIC; signal kernel_q0 : STD_LOGIC_VECTOR (7 downto 0); signal operation : STD_LOGIC_VECTOR (31 downto 0); signal inStream_TDATA_blk_n : STD_LOGIC; signal ap_sig_cseq_ST_pp0_stg1_fsm_2 : STD_LOGIC; signal ap_sig_65 : BOOLEAN; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal exitcond1_reg_1305 : STD_LOGIC_VECTOR (0 downto 0); signal outStream_TDATA_blk_n : STD_LOGIC; signal ap_sig_cseq_ST_pp0_stg5_fsm_6 : STD_LOGIC; signal ap_sig_82 : BOOLEAN; signal tmp_12_reg_1347 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st17_fsm_10 : STD_LOGIC; signal ap_sig_95 : BOOLEAN; signal exitcond_fu_1224_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_id_V_reg_406 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_user_V_reg_419 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_strb_V_reg_432 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_keep_V_reg_445 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_dest_V_reg_458 : STD_LOGIC_VECTOR (5 downto 0); signal col_assign_reg_471 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_reg_482 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_reg_493 : STD_LOGIC_VECTOR (31 downto 0); signal countWait_reg_505 : STD_LOGIC_VECTOR (18 downto 0); signal reg_527 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_188 : BOOLEAN; signal ap_sig_cseq_ST_pp0_stg4_fsm_5 : STD_LOGIC; signal ap_sig_198 : BOOLEAN; signal ap_sig_cseq_ST_pp0_stg7_fsm_8 : STD_LOGIC; signal ap_sig_208 : BOOLEAN; signal reg_531 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_cseq_ST_pp0_stg2_fsm_3 : STD_LOGIC; signal ap_sig_219 : BOOLEAN; signal ap_sig_ioackin_outStream_TREADY : STD_LOGIC; signal ap_sig_cseq_ST_pp0_stg8_fsm_9 : STD_LOGIC; signal ap_sig_237 : BOOLEAN; signal lineBuff_val_0_q0 : STD_LOGIC_VECTOR (7 downto 0); signal reg_535 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_cseq_ST_pp0_stg3_fsm_4 : STD_LOGIC; signal ap_sig_249 : BOOLEAN; signal lineBuff_val_0_q1 : STD_LOGIC_VECTOR (7 downto 0); signal reg_540 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_cseq_ST_pp0_stg6_fsm_7 : STD_LOGIC; signal ap_sig_260 : BOOLEAN; signal ap_sig_cseq_ST_pp0_stg0_fsm_1 : STD_LOGIC; signal ap_sig_270 : BOOLEAN; signal sel_tmp2_fu_544_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp2_reg_1290 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp5_fu_550_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp5_reg_1295 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp8_fu_556_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp8_reg_1300 : STD_LOGIC_VECTOR (0 downto 0); signal exitcond1_fu_562_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_s_fu_568_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_s_reg_1309 : STD_LOGIC_VECTOR (63 downto 0); signal lineBuff_val_1_addr_reg_1314 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_2_addr_reg_1319 : STD_LOGIC_VECTOR (8 downto 0); signal or_cond_fu_606_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_reg_1324 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_fu_612_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_reg_1332 : STD_LOGIC_VECTOR (0 downto 0); signal idxCol_1_fu_630_p3 : STD_LOGIC_VECTOR (31 downto 0); signal idxCol_1_reg_1337 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_1_fu_638_p3 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_1_reg_1342 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_12_fu_646_p2 : STD_LOGIC_VECTOR (0 downto 0); signal phitmp_fu_652_p2 : STD_LOGIC_VECTOR (18 downto 0); signal phitmp_reg_1351 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_keep_V_1_reg_1356 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_strb_V_1_reg_1362 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_user_V_1_reg_1368 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_id_V_1_reg_1374 : STD_LOGIC_VECTOR (4 downto 0); signal ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_dest_V_1_reg_1380 : STD_LOGIC_VECTOR (5 downto 0); signal ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1 : STD_LOGIC_VECTOR (5 downto 0); signal col_assign_1_0_2_fu_703_p2 : STD_LOGIC_VECTOR (31 downto 0); signal col_assign_1_0_2_reg_1396 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp3_fu_716_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp3_reg_1421 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp6_fu_728_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp6_reg_1426 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp9_fu_740_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp9_reg_1431 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal pixConvolved_2_fu_752_p3 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_2_reg_1436 : STD_LOGIC_VECTOR (31 downto 0); signal lineBuff_val_0_load_1_reg_1441 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_q0 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_load_1_reg_1451 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_q1 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_load_2_reg_1456 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_q0 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_load_1_reg_1466 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_q1 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_load_2_reg_1471 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_0_fu_773_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_0_reg_1481 : STD_LOGIC_VECTOR (15 downto 0); signal lineBuff_val_1_load_3_reg_1486 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_load_3_reg_1491 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_14_fu_779_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_14_reg_1496 : STD_LOGIC_VECTOR (7 downto 0); signal tmp4_fu_796_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp4_reg_1504 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_15_fu_801_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_15_reg_1509 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_2_fu_813_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_2_reg_1517 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_16_fu_819_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_16_reg_1522 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_0_fu_830_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_0_reg_1530 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_0_2_i_fu_851_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_0_2_i_reg_1535 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_fu_858_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_reg_1541 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_0_2_i_fu_877_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_0_2_i_reg_1549 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_1_fu_891_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_1_reg_1555 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_1_i_fu_901_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_1_i_reg_1560 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_18_fu_907_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_18_reg_1566 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_i_fu_915_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_i_reg_1574 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_2_fu_928_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_2_reg_1580 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_1_1_i_fu_938_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_1_1_i_reg_1585 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_19_fu_944_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_19_reg_1591 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_1_i_fu_952_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_1_i_reg_1599 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_0_fu_965_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_0_reg_1605 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_1_2_i_fu_975_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_1_2_i_reg_1610 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_20_fu_981_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_20_reg_1616 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_2_i_fu_989_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_2_i_reg_1624 : STD_LOGIC_VECTOR (7 downto 0); signal tmp1_fu_1008_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp1_reg_1630 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_2_i_fu_1017_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_2_i_reg_1635 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_21_fu_1023_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_21_reg_1641 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_i_fu_1031_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_i_reg_1649 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_2_fu_1044_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_2_reg_1655 : STD_LOGIC_VECTOR (15 downto 0); signal tmp3_fu_1054_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp3_reg_1660 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_2_1_i_fu_1063_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_2_1_i_reg_1665 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_22_fu_1069_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_22_reg_1671 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_1_i_fu_1077_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_1_i_reg_1679 : STD_LOGIC_VECTOR (7 downto 0); signal valOutput_fu_1097_p2 : STD_LOGIC_VECTOR (15 downto 0); signal valOutput_reg_1685 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_6_reg_1690 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_reg_1695 : STD_LOGIC_VECTOR (12 downto 0); signal sel_tmp10_fu_1147_p3 : STD_LOGIC_VECTOR (7 downto 0); signal sel_tmp10_reg_1700 : STD_LOGIC_VECTOR (7 downto 0); signal countWait_2_fu_1230_p2 : STD_LOGIC_VECTOR (9 downto 0); signal lineBuff_val_0_address0 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_0_ce0 : STD_LOGIC; signal lineBuff_val_0_we0 : STD_LOGIC; signal lineBuff_val_0_address1 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_0_ce1 : STD_LOGIC; signal lineBuff_val_1_address0 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_1_ce0 : STD_LOGIC; signal lineBuff_val_1_we0 : STD_LOGIC; signal lineBuff_val_1_address1 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_1_ce1 : STD_LOGIC; signal lineBuff_val_2_address0 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_2_ce0 : STD_LOGIC; signal lineBuff_val_2_we0 : STD_LOGIC; signal lineBuff_val_2_address1 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_2_ce1 : STD_LOGIC; signal col_assign_phi_fu_475_p4 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_phi_fu_486_p4 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_phi_fu_497_p4 : STD_LOGIC_VECTOR (31 downto 0); signal countWait_phi_fu_509_p4 : STD_LOGIC_VECTOR (18 downto 0); signal countWait_1_reg_516 : STD_LOGIC_VECTOR (9 downto 0); signal tmp_7_fu_683_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_25_0_1_fu_696_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_25_0_2_fu_759_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_data_V_fu_1217_p3 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ioackin_outStream_TREADY : STD_LOGIC := '0'; signal tmp_3_fu_574_p4 : STD_LOGIC_VECTOR (30 downto 0); signal tmp_4_fu_590_p4 : STD_LOGIC_VECTOR (30 downto 0); signal icmp_fu_584_p2 : STD_LOGIC_VECTOR (0 downto 0); signal icmp4_fu_600_p2 : STD_LOGIC_VECTOR (0 downto 0); signal idxCol_fu_618_p2 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_2_fu_624_p2 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_3_fu_690_p2 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp1_fu_709_p3 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp4_fu_720_p3 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp7_fu_732_p3 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_1_fu_744_p3 : STD_LOGIC_VECTOR (31 downto 0); signal window_val_0_0_fu_773_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_0_fu_773_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_1_fu_790_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_1_fu_790_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_1_fu_790_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_2_fu_813_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_2_fu_813_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_0_fu_830_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_0_fu_830_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_0_1_i_fu_836_p2 : STD_LOGIC_VECTOR (0 downto 0); signal valInWindow_0_minVal_1_0_1_i_fu_840_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_0_2_i_fu_846_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_0_1_i_fu_862_p2 : STD_LOGIC_VECTOR (0 downto 0); signal valInWindow_0_maxVal_1_0_1_i_fu_866_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_11_0_2_i_fu_872_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_1_1_fu_891_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_1_fu_891_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_1_i_fu_897_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_i_fu_911_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_1_2_fu_928_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_2_fu_928_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_1_1_i_fu_934_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_1_i_fu_948_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_2_0_fu_965_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_0_fu_965_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_1_2_i_fu_971_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_2_i_fu_985_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_2_1_fu_1002_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_1_fu_1002_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_1_fu_1002_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_2_i_fu_1013_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_2_i_fu_1027_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_2_2_fu_1044_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_2_fu_1044_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp2_fu_1050_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_2_1_i_fu_1059_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_2_1_i_fu_1073_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp5_fu_1083_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp6_fu_1087_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp7_fu_1092_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_2_2_i_fu_1120_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_2_2_i_fu_1130_p2 : STD_LOGIC_VECTOR (0 downto 0); signal valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_2_2_i_fu_1124_p3 : STD_LOGIC_VECTOR (7 downto 0); signal sel_tmp_fu_1140_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_18_tr_fu_1154_p1 : STD_LOGIC_VECTOR (16 downto 0); signal p_neg_fu_1157_p2 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_8_fu_1163_p4 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_7_cast_fu_1173_p1 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_1_fu_1177_p1 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_2_fu_1180_p2 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_10_cast_fu_1186_p1 : STD_LOGIC_VECTOR (14 downto 0); signal valOutput_1_fu_1190_p3 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_13_fu_1201_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_10_fu_1197_p1 : STD_LOGIC_VECTOR (7 downto 0); signal p_s_fu_1209_p3 : STD_LOGIC_VECTOR (7 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (10 downto 0); signal window_val_0_0_fu_773_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_1_fu_790_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_2_fu_813_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_0_fu_830_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_1_fu_891_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_2_fu_928_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_0_fu_965_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_1_fu_1002_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_2_fu_1044_p10 : STD_LOGIC_VECTOR (15 downto 0); signal ap_sig_1220 : BOOLEAN; component doImgProc_lineBuff_val_0 IS generic ( DataWidth : INTEGER; AddressRange : INTEGER; AddressWidth : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR (8 downto 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR (7 downto 0); q0 : OUT STD_LOGIC_VECTOR (7 downto 0); address1 : IN STD_LOGIC_VECTOR (8 downto 0); ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR (7 downto 0) ); end component; component doImgProc_CRTL_BUS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; ap_start : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; ap_ready : IN STD_LOGIC; ap_done : IN STD_LOGIC; ap_idle : IN STD_LOGIC; operation : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component doImgProc_KERNEL_BUS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; kernel_address0 : IN STD_LOGIC_VECTOR (3 downto 0); kernel_ce0 : IN STD_LOGIC; kernel_q0 : OUT STD_LOGIC_VECTOR (7 downto 0) ); end component; begin doImgProc_CRTL_BUS_s_axi_U : component doImgProc_CRTL_BUS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_CRTL_BUS_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CRTL_BUS_DATA_WIDTH) port map ( AWVALID => s_axi_CRTL_BUS_AWVALID, AWREADY => s_axi_CRTL_BUS_AWREADY, AWADDR => s_axi_CRTL_BUS_AWADDR, WVALID => s_axi_CRTL_BUS_WVALID, WREADY => s_axi_CRTL_BUS_WREADY, WDATA => s_axi_CRTL_BUS_WDATA, WSTRB => s_axi_CRTL_BUS_WSTRB, ARVALID => s_axi_CRTL_BUS_ARVALID, ARREADY => s_axi_CRTL_BUS_ARREADY, ARADDR => s_axi_CRTL_BUS_ARADDR, RVALID => s_axi_CRTL_BUS_RVALID, RREADY => s_axi_CRTL_BUS_RREADY, RDATA => s_axi_CRTL_BUS_RDATA, RRESP => s_axi_CRTL_BUS_RRESP, BVALID => s_axi_CRTL_BUS_BVALID, BREADY => s_axi_CRTL_BUS_BREADY, BRESP => s_axi_CRTL_BUS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, ap_start => ap_start, interrupt => interrupt, ap_ready => ap_ready, ap_done => ap_done, ap_idle => ap_idle, operation => operation); doImgProc_KERNEL_BUS_s_axi_U : component doImgProc_KERNEL_BUS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_KERNEL_BUS_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_KERNEL_BUS_DATA_WIDTH) port map ( AWVALID => s_axi_KERNEL_BUS_AWVALID, AWREADY => s_axi_KERNEL_BUS_AWREADY, AWADDR => s_axi_KERNEL_BUS_AWADDR, WVALID => s_axi_KERNEL_BUS_WVALID, WREADY => s_axi_KERNEL_BUS_WREADY, WDATA => s_axi_KERNEL_BUS_WDATA, WSTRB => s_axi_KERNEL_BUS_WSTRB, ARVALID => s_axi_KERNEL_BUS_ARVALID, ARREADY => s_axi_KERNEL_BUS_ARREADY, ARADDR => s_axi_KERNEL_BUS_ARADDR, RVALID => s_axi_KERNEL_BUS_RVALID, RREADY => s_axi_KERNEL_BUS_RREADY, RDATA => s_axi_KERNEL_BUS_RDATA, RRESP => s_axi_KERNEL_BUS_RRESP, BVALID => s_axi_KERNEL_BUS_BVALID, BREADY => s_axi_KERNEL_BUS_BREADY, BRESP => s_axi_KERNEL_BUS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, kernel_address0 => kernel_address0, kernel_ce0 => kernel_ce0, kernel_q0 => kernel_q0); lineBuff_val_0_U : component doImgProc_lineBuff_val_0 generic map ( DataWidth => 8, AddressRange => 512, AddressWidth => 9) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => lineBuff_val_0_address0, ce0 => lineBuff_val_0_ce0, we0 => lineBuff_val_0_we0, d0 => lineBuff_val_1_q0, q0 => lineBuff_val_0_q0, address1 => lineBuff_val_0_address1, ce1 => lineBuff_val_0_ce1, q1 => lineBuff_val_0_q1); lineBuff_val_1_U : component doImgProc_lineBuff_val_0 generic map ( DataWidth => 8, AddressRange => 512, AddressWidth => 9) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => lineBuff_val_1_address0, ce0 => lineBuff_val_1_ce0, we0 => lineBuff_val_1_we0, d0 => lineBuff_val_2_q0, q0 => lineBuff_val_1_q0, address1 => lineBuff_val_1_address1, ce1 => lineBuff_val_1_ce1, q1 => lineBuff_val_1_q1); lineBuff_val_2_U : component doImgProc_lineBuff_val_0 generic map ( DataWidth => 8, AddressRange => 512, AddressWidth => 9) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => lineBuff_val_2_address0, ce0 => lineBuff_val_2_ce0, we0 => lineBuff_val_2_we0, d0 => inStream_TDATA, q0 => lineBuff_val_2_q0, address1 => lineBuff_val_2_address1, ce1 => lineBuff_val_2_ce1, q1 => lineBuff_val_2_q1); ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; ap_reg_ioackin_outStream_TREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ioackin_outStream_TREADY <= ap_const_logic_0; else if ((((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))))) then ap_reg_ioackin_outStream_TREADY <= ap_const_logic_0; elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_1 = outStream_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_1 = outStream_TREADY)))) then ap_reg_ioackin_outStream_TREADY <= ap_const_logic_1; end if; end if; end if; end process; ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_1; end if; end if; end if; end process; ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_1; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and not((exitcond1_reg_1305 = ap_const_lv1_0))))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; end if; end if; end if; end process; col_assign_reg_471_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then col_assign_reg_471 <= idxCol_1_reg_1337; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then col_assign_reg_471 <= ap_const_lv32_0; end if; end if; end process; countWait_1_reg_516_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)))) then countWait_1_reg_516 <= ap_const_lv10_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then countWait_1_reg_516 <= countWait_2_fu_1230_p2; end if; end if; end process; countWait_reg_505_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then countWait_reg_505 <= phitmp_reg_1351; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then countWait_reg_505 <= ap_const_lv19_1; end if; end if; end process; idxRow_reg_482_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then idxRow_reg_482 <= idxRow_1_reg_1342; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then idxRow_reg_482 <= ap_const_lv32_0; end if; end if; end process; pixConvolved_reg_493_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then pixConvolved_reg_493 <= pixConvolved_2_reg_1436; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then pixConvolved_reg_493 <= ap_const_lv32_0; end if; end if; end process; reg_535_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_sig_1220) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) then reg_535 <= lineBuff_val_0_q1; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then reg_535 <= lineBuff_val_0_q0; end if; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1 <= exitcond1_reg_1305; ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1 <= tmp_12_reg_1347; exitcond1_reg_1305 <= exitcond1_fu_562_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1 <= sel_tmp3_reg_1421; ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1 <= sel_tmp6_reg_1426; ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1 <= sel_tmp9_reg_1431; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)))) then ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1 <= tmp_dest_V_1_reg_1380; ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1 <= tmp_id_V_1_reg_1374; ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1 <= tmp_keep_V_1_reg_1356; ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1 <= tmp_strb_V_1_reg_1362; ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1 <= tmp_user_V_1_reg_1368; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3))) then col_assign_1_0_2_reg_1396 <= col_assign_1_0_2_fu_703_p2; sel_tmp3_reg_1421 <= sel_tmp3_fu_716_p2; sel_tmp6_reg_1426 <= sel_tmp6_fu_728_p2; sel_tmp9_reg_1431 <= sel_tmp9_fu_740_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_562_p2))) then idxCol_1_reg_1337 <= idxCol_1_fu_630_p3; idxRow_1_reg_1342 <= idxRow_1_fu_638_p3; phitmp_reg_1351 <= phitmp_fu_652_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4))) then lineBuff_val_0_load_1_reg_1441 <= lineBuff_val_0_q1; lineBuff_val_1_load_1_reg_1451 <= lineBuff_val_1_q0; lineBuff_val_1_load_2_reg_1456 <= lineBuff_val_1_q1; lineBuff_val_2_load_1_reg_1466 <= lineBuff_val_2_q0; lineBuff_val_2_load_2_reg_1471 <= lineBuff_val_2_q1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_562_p2))) then lineBuff_val_1_addr_reg_1314 <= tmp_s_fu_568_p1(9 - 1 downto 0); lineBuff_val_2_addr_reg_1319 <= tmp_s_fu_568_p1(9 - 1 downto 0); or_cond_reg_1324 <= or_cond_fu_606_p2; tmp_11_reg_1332 <= tmp_11_fu_612_p2; tmp_12_reg_1347 <= tmp_12_fu_646_p2; tmp_s_reg_1309(31 downto 0) <= tmp_s_fu_568_p1(31 downto 0); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5))) then lineBuff_val_1_load_3_reg_1486 <= lineBuff_val_1_q1; lineBuff_val_2_load_3_reg_1491 <= lineBuff_val_2_q1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3))) then pixConvolved_2_reg_1436 <= pixConvolved_2_fu_752_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)))) then reg_527 <= kernel_q0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)))) then reg_531 <= kernel_q0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then reg_540 <= kernel_q0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1))) then sel_tmp10_reg_1700 <= sel_tmp10_fu_1147_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then sel_tmp2_reg_1290 <= sel_tmp2_fu_544_p2; sel_tmp5_reg_1295 <= sel_tmp5_fu_550_p2; sel_tmp8_reg_1300 <= sel_tmp8_fu_556_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and not((ap_const_lv1_0 = sel_tmp9_reg_1431)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp1_reg_1630 <= tmp1_fu_1008_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1)))) then tmp3_reg_1660 <= tmp3_fu_1054_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = sel_tmp9_reg_1431)))) then tmp4_reg_1504 <= tmp4_fu_796_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_14_reg_1496 <= tmp_14_fu_779_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_15_reg_1509 <= tmp_15_fu_801_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_16_reg_1522 <= tmp_16_fu_819_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_17_reg_1541 <= tmp_17_fu_858_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_18_reg_1566 <= tmp_18_fu_907_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_19_reg_1591 <= tmp_19_fu_944_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp_20_reg_1616 <= tmp_20_fu_981_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp_21_reg_1641 <= tmp_21_fu_1023_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1))) then tmp_22_reg_1671 <= tmp_22_fu_1069_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1)))) then tmp_6_reg_1690 <= valOutput_fu_1097_p2(15 downto 15); tmp_9_reg_1695 <= valOutput_fu_1097_p2(15 downto 3); valOutput_reg_1685 <= valOutput_fu_1097_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)))) then tmp_dest_V_1_reg_1380 <= inStream_TDEST; tmp_id_V_1_reg_1374 <= inStream_TID; tmp_keep_V_1_reg_1356 <= inStream_TKEEP; tmp_strb_V_1_reg_1362 <= inStream_TSTRB; tmp_user_V_1_reg_1368 <= inStream_TUSER; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp_dest_V_reg_458 <= ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1; tmp_id_V_reg_406 <= ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1; tmp_keep_V_reg_445 <= ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1; tmp_strb_V_reg_432 <= ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1; tmp_user_V_reg_419 <= ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then valInWindow_0_maxVal_1_0_2_i_reg_1549 <= valInWindow_0_maxVal_1_0_2_i_fu_877_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then valInWindow_0_maxVal_1_1_1_i_reg_1599 <= valInWindow_0_maxVal_1_1_1_i_fu_952_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_maxVal_1_1_2_i_reg_1624 <= valInWindow_0_maxVal_1_1_2_i_fu_989_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then valInWindow_0_maxVal_1_1_i_reg_1574 <= valInWindow_0_maxVal_1_1_i_fu_915_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1)))) then valInWindow_0_maxVal_1_2_1_i_reg_1679 <= valInWindow_0_maxVal_1_2_1_i_fu_1077_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_maxVal_1_2_i_reg_1649 <= valInWindow_0_maxVal_1_2_i_fu_1031_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then valInWindow_0_minVal_1_0_2_i_reg_1535 <= valInWindow_0_minVal_1_0_2_i_fu_851_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then valInWindow_0_minVal_1_1_1_i_reg_1585 <= valInWindow_0_minVal_1_1_1_i_fu_938_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_minVal_1_1_2_i_reg_1610 <= valInWindow_0_minVal_1_1_2_i_fu_975_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then valInWindow_0_minVal_1_1_i_reg_1560 <= valInWindow_0_minVal_1_1_i_fu_901_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1)))) then valInWindow_0_minVal_1_2_1_i_reg_1665 <= valInWindow_0_minVal_1_2_1_i_fu_1063_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_minVal_1_2_i_reg_1635 <= valInWindow_0_minVal_1_2_i_fu_1017_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5))) then window_val_0_0_reg_1481 <= window_val_0_0_fu_773_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7))) then window_val_0_2_reg_1517 <= window_val_0_2_fu_813_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8))) then window_val_1_0_reg_1530 <= window_val_1_0_fu_830_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9))) then window_val_1_1_reg_1555 <= window_val_1_1_fu_891_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then window_val_1_2_reg_1580 <= window_val_1_2_fu_928_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then window_val_2_0_reg_1605 <= window_val_2_0_fu_965_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then window_val_2_2_reg_1655 <= window_val_2_2_fu_1044_p2; end if; end if; end process; tmp_s_reg_1309(63 downto 32) <= "00000000000000000000000000000000"; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, exitcond_fu_1224_p2, ap_sig_188, ap_sig_ioackin_outStream_TREADY, exitcond1_fu_562_p2) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_pp0_stg0_fsm_1 => if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then ap_NS_fsm <= ap_ST_pp0_stg1_fsm_2; else ap_NS_fsm <= ap_ST_st17_fsm_10; end if; when ap_ST_pp0_stg1_fsm_2 => if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) then ap_NS_fsm <= ap_ST_pp0_stg2_fsm_3; else ap_NS_fsm <= ap_ST_pp0_stg1_fsm_2; end if; when ap_ST_pp0_stg2_fsm_3 => ap_NS_fsm <= ap_ST_pp0_stg3_fsm_4; when ap_ST_pp0_stg3_fsm_4 => ap_NS_fsm <= ap_ST_pp0_stg4_fsm_5; when ap_ST_pp0_stg4_fsm_5 => ap_NS_fsm <= ap_ST_pp0_stg5_fsm_6; when ap_ST_pp0_stg5_fsm_6 => if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))))) then ap_NS_fsm <= ap_ST_pp0_stg6_fsm_7; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then ap_NS_fsm <= ap_ST_st17_fsm_10; else ap_NS_fsm <= ap_ST_pp0_stg5_fsm_6; end if; when ap_ST_pp0_stg6_fsm_7 => ap_NS_fsm <= ap_ST_pp0_stg7_fsm_8; when ap_ST_pp0_stg7_fsm_8 => ap_NS_fsm <= ap_ST_pp0_stg8_fsm_9; when ap_ST_pp0_stg8_fsm_9 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_1; when ap_ST_st17_fsm_10 => if ((not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then ap_NS_fsm <= ap_ST_st1_fsm_0; elsif (((ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then ap_NS_fsm <= ap_ST_st17_fsm_10; else ap_NS_fsm <= ap_ST_st17_fsm_10; end if; when others => ap_NS_fsm <= "XXXXXXXXXXX"; end case; end process; ap_done_assign_proc : process(ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_sig_ioackin_outStream_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_sig_ioackin_outStream_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; ap_sig_1220_assign_proc : process(ap_reg_ppiten_pp0_it0, exitcond1_reg_1305) begin ap_sig_1220 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0)); end process; ap_sig_188_assign_proc : process(inStream_TVALID, exitcond1_reg_1305) begin ap_sig_188 <= ((exitcond1_reg_1305 = ap_const_lv1_0) and (inStream_TVALID = ap_const_logic_0)); end process; ap_sig_198_assign_proc : process(ap_CS_fsm) begin ap_sig_198 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5)); end process; ap_sig_208_assign_proc : process(ap_CS_fsm) begin ap_sig_208 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8)); end process; ap_sig_219_assign_proc : process(ap_CS_fsm) begin ap_sig_219 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; ap_sig_237_assign_proc : process(ap_CS_fsm) begin ap_sig_237 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9)); end process; ap_sig_249_assign_proc : process(ap_CS_fsm) begin ap_sig_249 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4)); end process; ap_sig_260_assign_proc : process(ap_CS_fsm) begin ap_sig_260 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7)); end process; ap_sig_270_assign_proc : process(ap_CS_fsm) begin ap_sig_270 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; ap_sig_28_assign_proc : process(ap_CS_fsm) begin ap_sig_28 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; ap_sig_65_assign_proc : process(ap_CS_fsm) begin ap_sig_65 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; ap_sig_82_assign_proc : process(ap_CS_fsm) begin ap_sig_82 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6)); end process; ap_sig_95_assign_proc : process(ap_CS_fsm) begin ap_sig_95 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10)); end process; ap_sig_cseq_ST_pp0_stg0_fsm_1_assign_proc : process(ap_sig_270) begin if (ap_sig_270) then ap_sig_cseq_ST_pp0_stg0_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg0_fsm_1 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg1_fsm_2_assign_proc : process(ap_sig_65) begin if (ap_sig_65) then ap_sig_cseq_ST_pp0_stg1_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg1_fsm_2 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg2_fsm_3_assign_proc : process(ap_sig_219) begin if (ap_sig_219) then ap_sig_cseq_ST_pp0_stg2_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg2_fsm_3 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg3_fsm_4_assign_proc : process(ap_sig_249) begin if (ap_sig_249) then ap_sig_cseq_ST_pp0_stg3_fsm_4 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg3_fsm_4 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg4_fsm_5_assign_proc : process(ap_sig_198) begin if (ap_sig_198) then ap_sig_cseq_ST_pp0_stg4_fsm_5 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg4_fsm_5 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg5_fsm_6_assign_proc : process(ap_sig_82) begin if (ap_sig_82) then ap_sig_cseq_ST_pp0_stg5_fsm_6 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg5_fsm_6 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg6_fsm_7_assign_proc : process(ap_sig_260) begin if (ap_sig_260) then ap_sig_cseq_ST_pp0_stg6_fsm_7 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg6_fsm_7 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg7_fsm_8_assign_proc : process(ap_sig_208) begin if (ap_sig_208) then ap_sig_cseq_ST_pp0_stg7_fsm_8 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg7_fsm_8 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg8_fsm_9_assign_proc : process(ap_sig_237) begin if (ap_sig_237) then ap_sig_cseq_ST_pp0_stg8_fsm_9 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg8_fsm_9 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_st17_fsm_10_assign_proc : process(ap_sig_95) begin if (ap_sig_95) then ap_sig_cseq_ST_st17_fsm_10 <= ap_const_logic_1; else ap_sig_cseq_ST_st17_fsm_10 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_28) begin if (ap_sig_28) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; ap_sig_ioackin_outStream_TREADY_assign_proc : process(outStream_TREADY, ap_reg_ioackin_outStream_TREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)) then ap_sig_ioackin_outStream_TREADY <= outStream_TREADY; else ap_sig_ioackin_outStream_TREADY <= ap_const_logic_1; end if; end process; col_assign_1_0_2_fu_703_p2 <= std_logic_vector(unsigned(ap_const_lv32_2) + unsigned(pixConvolved_phi_fu_497_p4)); col_assign_phi_fu_475_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, col_assign_reg_471, ap_sig_cseq_ST_pp0_stg0_fsm_1, idxCol_1_reg_1337) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then col_assign_phi_fu_475_p4 <= idxCol_1_reg_1337; else col_assign_phi_fu_475_p4 <= col_assign_reg_471; end if; end process; countWait_2_fu_1230_p2 <= std_logic_vector(unsigned(countWait_1_reg_516) + unsigned(ap_const_lv10_1)); countWait_phi_fu_509_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, countWait_reg_505, ap_sig_cseq_ST_pp0_stg0_fsm_1, phitmp_reg_1351) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then countWait_phi_fu_509_p4 <= phitmp_reg_1351; else countWait_phi_fu_509_p4 <= countWait_reg_505; end if; end process; exitcond1_fu_562_p2 <= "1" when (countWait_phi_fu_509_p4 = ap_const_lv19_40001) else "0"; exitcond_fu_1224_p2 <= "1" when (countWait_1_reg_516 = ap_const_lv10_201) else "0"; icmp4_fu_600_p2 <= "1" when (signed(tmp_4_fu_590_p4) > signed(ap_const_lv31_0)) else "0"; icmp_fu_584_p2 <= "1" when (signed(tmp_3_fu_574_p4) > signed(ap_const_lv31_0)) else "0"; idxCol_1_fu_630_p3 <= idxCol_fu_618_p2 when (tmp_11_fu_612_p2(0) = '1') else ap_const_lv32_0; idxCol_fu_618_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(col_assign_phi_fu_475_p4)); idxRow_1_fu_638_p3 <= idxRow_phi_fu_486_p4 when (tmp_11_fu_612_p2(0) = '1') else idxRow_2_fu_624_p2; idxRow_2_fu_624_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(idxRow_phi_fu_486_p4)); idxRow_phi_fu_486_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, idxRow_reg_482, ap_sig_cseq_ST_pp0_stg0_fsm_1, idxRow_1_reg_1342) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then idxRow_phi_fu_486_p4 <= idxRow_1_reg_1342; else idxRow_phi_fu_486_p4 <= idxRow_reg_482; end if; end process; inStream_TDATA_blk_n_assign_proc : process(inStream_TVALID, ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0))) then inStream_TDATA_blk_n <= inStream_TVALID; else inStream_TDATA_blk_n <= ap_const_logic_1; end if; end process; inStream_TREADY_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then inStream_TREADY <= ap_const_logic_1; else inStream_TREADY <= ap_const_logic_0; end if; end process; kernel_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_sig_cseq_ST_pp0_stg4_fsm_5, ap_sig_cseq_ST_pp0_stg7_fsm_8, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg8_fsm_9, ap_sig_cseq_ST_pp0_stg3_fsm_4, ap_sig_cseq_ST_pp0_stg6_fsm_7, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)) then kernel_address0 <= ap_const_lv64_8(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)) then kernel_address0 <= ap_const_lv64_7(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) then kernel_address0 <= ap_const_lv64_6(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6)) then kernel_address0 <= ap_const_lv64_5(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) then kernel_address0 <= ap_const_lv64_4(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then kernel_address0 <= ap_const_lv64_3(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then kernel_address0 <= ap_const_lv64_2(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then kernel_address0 <= ap_const_lv64_1(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then kernel_address0 <= ap_const_lv64_0(4 - 1 downto 0); else kernel_address0 <= "XXXX"; end if; else kernel_address0 <= "XXXX"; end if; end process; kernel_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_188, ap_sig_cseq_ST_pp0_stg4_fsm_5, ap_sig_cseq_ST_pp0_stg7_fsm_8, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_ioackin_outStream_TREADY, ap_sig_cseq_ST_pp0_stg8_fsm_9, ap_sig_cseq_ST_pp0_stg3_fsm_4, ap_sig_cseq_ST_pp0_stg6_fsm_7, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then kernel_ce0 <= ap_const_logic_1; else kernel_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_0_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, tmp_s_reg_1309, tmp_7_fu_683_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then lineBuff_val_0_address0 <= tmp_s_reg_1309(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_0_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0); else lineBuff_val_0_address0 <= "XXXXXXXXX"; end if; else lineBuff_val_0_address0 <= "XXXXXXXXX"; end if; end process; lineBuff_val_0_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then lineBuff_val_0_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_0_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0); else lineBuff_val_0_address1 <= "XXXXXXXXX"; end if; else lineBuff_val_0_address1 <= "XXXXXXXXX"; end if; end process; lineBuff_val_0_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)))) then lineBuff_val_0_ce0 <= ap_const_logic_1; else lineBuff_val_0_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_0_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then lineBuff_val_0_ce1 <= ap_const_logic_1; else lineBuff_val_0_ce1 <= ap_const_logic_0; end if; end process; lineBuff_val_0_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then lineBuff_val_0_we0 <= ap_const_logic_1; else lineBuff_val_0_we0 <= ap_const_logic_0; end if; end process; lineBuff_val_1_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1, tmp_s_fu_568_p1, lineBuff_val_1_addr_reg_1314, tmp_7_fu_683_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then lineBuff_val_1_address0 <= lineBuff_val_1_addr_reg_1314; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_1_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then lineBuff_val_1_address0 <= tmp_s_fu_568_p1(9 - 1 downto 0); else lineBuff_val_1_address0 <= "XXXXXXXXX"; end if; else lineBuff_val_1_address0 <= "XXXXXXXXX"; end if; end process; lineBuff_val_1_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then lineBuff_val_1_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_1_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0); else lineBuff_val_1_address1 <= "XXXXXXXXX"; end if; else lineBuff_val_1_address1 <= "XXXXXXXXX"; end if; end process; lineBuff_val_1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then lineBuff_val_1_ce0 <= ap_const_logic_1; else lineBuff_val_1_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_1_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then lineBuff_val_1_ce1 <= ap_const_logic_1; else lineBuff_val_1_ce1 <= ap_const_logic_0; end if; end process; lineBuff_val_1_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then lineBuff_val_1_we0 <= ap_const_logic_1; else lineBuff_val_1_we0 <= ap_const_logic_0; end if; end process; lineBuff_val_2_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1, tmp_s_fu_568_p1, lineBuff_val_2_addr_reg_1319, tmp_7_fu_683_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then lineBuff_val_2_address0 <= lineBuff_val_2_addr_reg_1319; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_2_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then lineBuff_val_2_address0 <= tmp_s_fu_568_p1(9 - 1 downto 0); else lineBuff_val_2_address0 <= "XXXXXXXXX"; end if; else lineBuff_val_2_address0 <= "XXXXXXXXX"; end if; end process; lineBuff_val_2_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then lineBuff_val_2_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_2_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0); else lineBuff_val_2_address1 <= "XXXXXXXXX"; end if; else lineBuff_val_2_address1 <= "XXXXXXXXX"; end if; end process; lineBuff_val_2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then lineBuff_val_2_ce0 <= ap_const_logic_1; else lineBuff_val_2_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_2_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then lineBuff_val_2_ce1 <= ap_const_logic_1; else lineBuff_val_2_ce1 <= ap_const_logic_0; end if; end process; lineBuff_val_2_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then lineBuff_val_2_we0 <= ap_const_logic_1; else lineBuff_val_2_we0 <= ap_const_logic_0; end if; end process; or_cond_fu_606_p2 <= (icmp_fu_584_p2 and icmp4_fu_600_p2); outStream_TDATA_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_data_V_fu_1217_p3) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TDATA <= ap_const_lv8_0; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TDATA <= tmp_data_V_fu_1217_p3; else outStream_TDATA <= "XXXXXXXX"; end if; end process; outStream_TDATA_blk_n_assign_proc : process(outStream_TREADY, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2)))) then outStream_TDATA_blk_n <= outStream_TREADY; else outStream_TDATA_blk_n <= ap_const_logic_1; end if; end process; outStream_TDEST_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_dest_V_reg_458, ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TDEST <= tmp_dest_V_reg_458; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TDEST <= ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1; else outStream_TDEST <= "XXXXXX"; end if; end process; outStream_TID_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_id_V_reg_406, ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TID <= tmp_id_V_reg_406; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TID <= ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1; else outStream_TID <= "XXXXX"; end if; end process; outStream_TKEEP_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_keep_V_reg_445, ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TKEEP <= tmp_keep_V_reg_445; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TKEEP <= ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1; else outStream_TKEEP <= "X"; end if; end process; outStream_TLAST_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, countWait_1_reg_516) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TLAST <= countWait_1_reg_516(9 downto 9); elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TLAST <= ap_const_lv1_0; else outStream_TLAST <= "X"; end if; end process; outStream_TSTRB_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_strb_V_reg_432, ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TSTRB <= tmp_strb_V_reg_432; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TSTRB <= ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1; else outStream_TSTRB <= "X"; end if; end process; outStream_TUSER_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_user_V_reg_419, ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TUSER <= tmp_user_V_reg_419; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TUSER <= ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1; else outStream_TUSER <= "XX"; end if; end process; outStream_TVALID_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_reg_ioackin_outStream_TREADY) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)))) then outStream_TVALID <= ap_const_logic_1; else outStream_TVALID <= ap_const_logic_0; end if; end process; p_neg_fu_1157_p2 <= std_logic_vector(unsigned(ap_const_lv17_0) - unsigned(tmp_18_tr_fu_1154_p1)); p_s_fu_1209_p3 <= ap_const_lv8_0 when (tmp_13_fu_1201_p3(0) = '1') else tmp_10_fu_1197_p1; phitmp_fu_652_p2 <= std_logic_vector(unsigned(countWait_phi_fu_509_p4) + unsigned(ap_const_lv19_1)); pixConvolved_1_fu_744_p3 <= pixConvolved_3_fu_690_p2 when (sel_tmp9_fu_740_p2(0) = '1') else sel_tmp7_fu_732_p3; pixConvolved_2_fu_752_p3 <= pixConvolved_1_fu_744_p3 when (tmp_11_reg_1332(0) = '1') else ap_const_lv32_0; pixConvolved_3_fu_690_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(pixConvolved_phi_fu_497_p4)); pixConvolved_phi_fu_497_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, pixConvolved_reg_493, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1, pixConvolved_2_reg_1436) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then pixConvolved_phi_fu_497_p4 <= pixConvolved_2_reg_1436; else pixConvolved_phi_fu_497_p4 <= pixConvolved_reg_493; end if; end process; sel_tmp10_fu_1147_p3 <= valInWindow_0_minVal_1_2_2_i_fu_1124_p3 when (ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1(0) = '1') else sel_tmp_fu_1140_p3; sel_tmp1_fu_709_p3 <= pixConvolved_3_fu_690_p2 when (or_cond_reg_1324(0) = '1') else pixConvolved_phi_fu_497_p4; sel_tmp2_fu_544_p2 <= "1" when (operation = ap_const_lv32_2) else "0"; sel_tmp3_fu_716_p2 <= (or_cond_reg_1324 and sel_tmp2_reg_1290); sel_tmp4_fu_720_p3 <= pixConvolved_3_fu_690_p2 when (sel_tmp3_fu_716_p2(0) = '1') else sel_tmp1_fu_709_p3; sel_tmp5_fu_550_p2 <= "1" when (operation = ap_const_lv32_1) else "0"; sel_tmp6_fu_728_p2 <= (or_cond_reg_1324 and sel_tmp5_reg_1295); sel_tmp7_fu_732_p3 <= pixConvolved_3_fu_690_p2 when (sel_tmp6_fu_728_p2(0) = '1') else sel_tmp4_fu_720_p3; sel_tmp8_fu_556_p2 <= "1" when (operation = ap_const_lv32_0) else "0"; sel_tmp9_fu_740_p2 <= (or_cond_reg_1324 and sel_tmp8_reg_1300); sel_tmp_fu_1140_p3 <= valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 when (ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1(0) = '1') else ap_const_lv8_0; tmp1_fu_1008_p2 <= std_logic_vector(unsigned(window_val_2_1_fu_1002_p2) + unsigned(window_val_2_0_reg_1605)); tmp2_fu_1050_p2 <= std_logic_vector(unsigned(window_val_1_1_reg_1555) + unsigned(window_val_1_2_reg_1580)); tmp3_fu_1054_p2 <= std_logic_vector(unsigned(tmp1_reg_1630) + unsigned(tmp2_fu_1050_p2)); tmp4_fu_796_p2 <= std_logic_vector(unsigned(window_val_0_0_reg_1481) + unsigned(window_val_0_1_fu_790_p2)); tmp5_fu_1083_p2 <= std_logic_vector(unsigned(window_val_2_2_reg_1655) + unsigned(window_val_0_2_reg_1517)); tmp6_fu_1087_p2 <= std_logic_vector(unsigned(window_val_1_0_reg_1530) + unsigned(tmp5_fu_1083_p2)); tmp7_fu_1092_p2 <= std_logic_vector(unsigned(tmp4_reg_1504) + unsigned(tmp6_fu_1087_p2)); tmp_10_cast_fu_1186_p1 <= std_logic_vector(resize(unsigned(tmp_1_fu_1177_p1),15)); tmp_10_fu_1197_p1 <= valOutput_1_fu_1190_p3(8 - 1 downto 0); tmp_11_0_1_i_fu_862_p2 <= "1" when (unsigned(tmp_15_reg_1509) > unsigned(tmp_14_reg_1496)) else "0"; tmp_11_0_2_i_fu_872_p2 <= "1" when (unsigned(tmp_16_reg_1522) > unsigned(valInWindow_0_maxVal_1_0_1_i_fu_866_p3)) else "0"; tmp_11_1_1_i_fu_948_p2 <= "1" when (unsigned(tmp_18_reg_1566) > unsigned(valInWindow_0_maxVal_1_1_i_reg_1574)) else "0"; tmp_11_1_2_i_fu_985_p2 <= "1" when (unsigned(tmp_19_reg_1591) > unsigned(valInWindow_0_maxVal_1_1_1_i_reg_1599)) else "0"; tmp_11_1_i_fu_911_p2 <= "1" when (unsigned(tmp_17_reg_1541) > unsigned(valInWindow_0_maxVal_1_0_2_i_reg_1549)) else "0"; tmp_11_2_1_i_fu_1073_p2 <= "1" when (unsigned(tmp_21_reg_1641) > unsigned(valInWindow_0_maxVal_1_2_i_reg_1649)) else "0"; tmp_11_2_2_i_fu_1130_p2 <= "1" when (unsigned(tmp_22_reg_1671) > unsigned(valInWindow_0_maxVal_1_2_1_i_reg_1679)) else "0"; tmp_11_2_i_fu_1027_p2 <= "1" when (unsigned(tmp_20_reg_1616) > unsigned(valInWindow_0_maxVal_1_1_2_i_reg_1624)) else "0"; tmp_11_fu_612_p2 <= "1" when (signed(col_assign_phi_fu_475_p4) < signed(ap_const_lv32_1FF)) else "0"; tmp_12_fu_646_p2 <= "1" when (unsigned(countWait_phi_fu_509_p4) > unsigned(ap_const_lv19_201)) else "0"; tmp_13_fu_1201_p3 <= valOutput_1_fu_1190_p3(14 downto 14); tmp_14_fu_779_p1 <= window_val_0_0_fu_773_p2(8 - 1 downto 0); tmp_15_fu_801_p1 <= window_val_0_1_fu_790_p2(8 - 1 downto 0); tmp_16_fu_819_p1 <= window_val_0_2_fu_813_p2(8 - 1 downto 0); tmp_17_fu_858_p1 <= window_val_1_0_fu_830_p2(8 - 1 downto 0); tmp_18_fu_907_p1 <= window_val_1_1_fu_891_p2(8 - 1 downto 0); tmp_18_tr_fu_1154_p1 <= std_logic_vector(resize(signed(valOutput_reg_1685),17)); tmp_19_fu_944_p1 <= window_val_1_2_fu_928_p2(8 - 1 downto 0); tmp_1_fu_1177_p1 <= std_logic_vector(resize(signed(tmp_9_reg_1695),14)); tmp_20_fu_981_p1 <= window_val_2_0_fu_965_p2(8 - 1 downto 0); tmp_21_fu_1023_p1 <= window_val_2_1_fu_1002_p2(8 - 1 downto 0); tmp_22_fu_1069_p1 <= window_val_2_2_fu_1044_p2(8 - 1 downto 0); tmp_25_0_1_fu_696_p1 <= std_logic_vector(resize(unsigned(pixConvolved_3_fu_690_p2),64)); tmp_25_0_2_fu_759_p1 <= std_logic_vector(resize(unsigned(col_assign_1_0_2_reg_1396),64)); tmp_2_fu_1180_p2 <= std_logic_vector(unsigned(ap_const_lv15_0) - unsigned(tmp_7_cast_fu_1173_p1)); tmp_3_fu_574_p4 <= idxRow_phi_fu_486_p4(31 downto 1); tmp_4_fu_590_p4 <= col_assign_phi_fu_475_p4(31 downto 1); tmp_5_0_1_i_fu_836_p2 <= "1" when (unsigned(tmp_15_reg_1509) < unsigned(tmp_14_reg_1496)) else "0"; tmp_5_0_2_i_fu_846_p2 <= "1" when (unsigned(tmp_16_reg_1522) < unsigned(valInWindow_0_minVal_1_0_1_i_fu_840_p3)) else "0"; tmp_5_1_1_i_fu_934_p2 <= "1" when (unsigned(tmp_18_reg_1566) < unsigned(valInWindow_0_minVal_1_1_i_reg_1560)) else "0"; tmp_5_1_2_i_fu_971_p2 <= "1" when (unsigned(tmp_19_reg_1591) < unsigned(valInWindow_0_minVal_1_1_1_i_reg_1585)) else "0"; tmp_5_1_i_fu_897_p2 <= "1" when (unsigned(tmp_17_reg_1541) < unsigned(valInWindow_0_minVal_1_0_2_i_reg_1535)) else "0"; tmp_5_2_1_i_fu_1059_p2 <= "1" when (unsigned(tmp_21_reg_1641) < unsigned(valInWindow_0_minVal_1_2_i_reg_1635)) else "0"; tmp_5_2_2_i_fu_1120_p2 <= "1" when (unsigned(tmp_22_reg_1671) < unsigned(valInWindow_0_minVal_1_2_1_i_reg_1665)) else "0"; tmp_5_2_i_fu_1013_p2 <= "1" when (unsigned(tmp_20_reg_1616) < unsigned(valInWindow_0_minVal_1_1_2_i_reg_1610)) else "0"; tmp_7_cast_fu_1173_p1 <= std_logic_vector(resize(unsigned(tmp_8_fu_1163_p4),15)); tmp_7_fu_683_p1 <= std_logic_vector(resize(unsigned(pixConvolved_phi_fu_497_p4),64)); tmp_8_fu_1163_p4 <= p_neg_fu_1157_p2(16 downto 3); tmp_data_V_fu_1217_p3 <= p_s_fu_1209_p3 when (ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1(0) = '1') else sel_tmp10_reg_1700; tmp_s_fu_568_p1 <= std_logic_vector(resize(unsigned(col_assign_phi_fu_475_p4),64)); valInWindow_0_maxVal_1_0_1_i_fu_866_p3 <= tmp_15_reg_1509 when (tmp_11_0_1_i_fu_862_p2(0) = '1') else tmp_14_reg_1496; valInWindow_0_maxVal_1_0_2_i_fu_877_p3 <= tmp_16_reg_1522 when (tmp_11_0_2_i_fu_872_p2(0) = '1') else valInWindow_0_maxVal_1_0_1_i_fu_866_p3; valInWindow_0_maxVal_1_1_1_i_fu_952_p3 <= tmp_18_reg_1566 when (tmp_11_1_1_i_fu_948_p2(0) = '1') else valInWindow_0_maxVal_1_1_i_reg_1574; valInWindow_0_maxVal_1_1_2_i_fu_989_p3 <= tmp_19_reg_1591 when (tmp_11_1_2_i_fu_985_p2(0) = '1') else valInWindow_0_maxVal_1_1_1_i_reg_1599; valInWindow_0_maxVal_1_1_i_fu_915_p3 <= tmp_17_reg_1541 when (tmp_11_1_i_fu_911_p2(0) = '1') else valInWindow_0_maxVal_1_0_2_i_reg_1549; valInWindow_0_maxVal_1_2_1_i_fu_1077_p3 <= tmp_21_reg_1641 when (tmp_11_2_1_i_fu_1073_p2(0) = '1') else valInWindow_0_maxVal_1_2_i_reg_1649; valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 <= tmp_22_reg_1671 when (tmp_11_2_2_i_fu_1130_p2(0) = '1') else valInWindow_0_maxVal_1_2_1_i_reg_1679; valInWindow_0_maxVal_1_2_i_fu_1031_p3 <= tmp_20_reg_1616 when (tmp_11_2_i_fu_1027_p2(0) = '1') else valInWindow_0_maxVal_1_1_2_i_reg_1624; valInWindow_0_minVal_1_0_1_i_fu_840_p3 <= tmp_15_reg_1509 when (tmp_5_0_1_i_fu_836_p2(0) = '1') else tmp_14_reg_1496; valInWindow_0_minVal_1_0_2_i_fu_851_p3 <= tmp_16_reg_1522 when (tmp_5_0_2_i_fu_846_p2(0) = '1') else valInWindow_0_minVal_1_0_1_i_fu_840_p3; valInWindow_0_minVal_1_1_1_i_fu_938_p3 <= tmp_18_reg_1566 when (tmp_5_1_1_i_fu_934_p2(0) = '1') else valInWindow_0_minVal_1_1_i_reg_1560; valInWindow_0_minVal_1_1_2_i_fu_975_p3 <= tmp_19_reg_1591 when (tmp_5_1_2_i_fu_971_p2(0) = '1') else valInWindow_0_minVal_1_1_1_i_reg_1585; valInWindow_0_minVal_1_1_i_fu_901_p3 <= tmp_17_reg_1541 when (tmp_5_1_i_fu_897_p2(0) = '1') else valInWindow_0_minVal_1_0_2_i_reg_1535; valInWindow_0_minVal_1_2_1_i_fu_1063_p3 <= tmp_21_reg_1641 when (tmp_5_2_1_i_fu_1059_p2(0) = '1') else valInWindow_0_minVal_1_2_i_reg_1635; valInWindow_0_minVal_1_2_2_i_fu_1124_p3 <= tmp_22_reg_1671 when (tmp_5_2_2_i_fu_1120_p2(0) = '1') else valInWindow_0_minVal_1_2_1_i_reg_1665; valInWindow_0_minVal_1_2_i_fu_1017_p3 <= tmp_20_reg_1616 when (tmp_5_2_i_fu_1013_p2(0) = '1') else valInWindow_0_minVal_1_1_2_i_reg_1610; valOutput_1_fu_1190_p3 <= tmp_2_fu_1180_p2 when (tmp_6_reg_1690(0) = '1') else tmp_10_cast_fu_1186_p1; valOutput_fu_1097_p2 <= std_logic_vector(unsigned(tmp3_reg_1660) + unsigned(tmp7_fu_1092_p2)); window_val_0_0_fu_773_p0 <= reg_527; window_val_0_0_fu_773_p1 <= window_val_0_0_fu_773_p10(8 - 1 downto 0); window_val_0_0_fu_773_p10 <= std_logic_vector(resize(unsigned(reg_535),16)); window_val_0_0_fu_773_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_0_fu_773_p0) * signed('0' &window_val_0_0_fu_773_p1))), 16)); window_val_0_1_fu_790_p0 <= reg_531; window_val_0_1_fu_790_p1 <= window_val_0_1_fu_790_p10(8 - 1 downto 0); window_val_0_1_fu_790_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_0_load_1_reg_1441),16)); window_val_0_1_fu_790_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_1_fu_790_p0) * signed('0' &window_val_0_1_fu_790_p1))), 16)); window_val_0_2_fu_813_p0 <= reg_540; window_val_0_2_fu_813_p1 <= window_val_0_2_fu_813_p10(8 - 1 downto 0); window_val_0_2_fu_813_p10 <= std_logic_vector(resize(unsigned(reg_535),16)); window_val_0_2_fu_813_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_2_fu_813_p0) * signed('0' &window_val_0_2_fu_813_p1))), 16)); window_val_1_0_fu_830_p0 <= reg_527; window_val_1_0_fu_830_p1 <= window_val_1_0_fu_830_p10(8 - 1 downto 0); window_val_1_0_fu_830_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_1_reg_1451),16)); window_val_1_0_fu_830_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_0_fu_830_p0) * signed('0' &window_val_1_0_fu_830_p1))), 16)); window_val_1_1_fu_891_p0 <= reg_531; window_val_1_1_fu_891_p1 <= window_val_1_1_fu_891_p10(8 - 1 downto 0); window_val_1_1_fu_891_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_2_reg_1456),16)); window_val_1_1_fu_891_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_1_fu_891_p0) * signed('0' &window_val_1_1_fu_891_p1))), 16)); window_val_1_2_fu_928_p0 <= reg_540; window_val_1_2_fu_928_p1 <= window_val_1_2_fu_928_p10(8 - 1 downto 0); window_val_1_2_fu_928_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_3_reg_1486),16)); window_val_1_2_fu_928_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_2_fu_928_p0) * signed('0' &window_val_1_2_fu_928_p1))), 16)); window_val_2_0_fu_965_p0 <= reg_527; window_val_2_0_fu_965_p1 <= window_val_2_0_fu_965_p10(8 - 1 downto 0); window_val_2_0_fu_965_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_1_reg_1466),16)); window_val_2_0_fu_965_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_0_fu_965_p0) * signed('0' &window_val_2_0_fu_965_p1))), 16)); window_val_2_1_fu_1002_p0 <= reg_531; window_val_2_1_fu_1002_p1 <= window_val_2_1_fu_1002_p10(8 - 1 downto 0); window_val_2_1_fu_1002_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_2_reg_1471),16)); window_val_2_1_fu_1002_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_1_fu_1002_p0) * signed('0' &window_val_2_1_fu_1002_p1))), 16)); window_val_2_2_fu_1044_p0 <= reg_540; window_val_2_2_fu_1044_p1 <= window_val_2_2_fu_1044_p10(8 - 1 downto 0); window_val_2_2_fu_1044_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_3_reg_1491),16)); window_val_2_2_fu_1044_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_2_fu_1044_p0) * signed('0' &window_val_2_2_fu_1044_p1))), 16)); end behav;
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2016.1 -- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity doImgProc is generic ( C_S_AXI_CRTL_BUS_ADDR_WIDTH : INTEGER := 5; C_S_AXI_CRTL_BUS_DATA_WIDTH : INTEGER := 32; C_S_AXI_KERNEL_BUS_ADDR_WIDTH : INTEGER := 5; C_S_AXI_KERNEL_BUS_DATA_WIDTH : INTEGER := 32 ); port ( ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; inStream_TDATA : IN STD_LOGIC_VECTOR (7 downto 0); inStream_TVALID : IN STD_LOGIC; inStream_TREADY : OUT STD_LOGIC; inStream_TKEEP : IN STD_LOGIC_VECTOR (0 downto 0); inStream_TSTRB : IN STD_LOGIC_VECTOR (0 downto 0); inStream_TUSER : IN STD_LOGIC_VECTOR (1 downto 0); inStream_TLAST : IN STD_LOGIC_VECTOR (0 downto 0); inStream_TID : IN STD_LOGIC_VECTOR (4 downto 0); inStream_TDEST : IN STD_LOGIC_VECTOR (5 downto 0); outStream_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0); outStream_TVALID : OUT STD_LOGIC; outStream_TREADY : IN STD_LOGIC; outStream_TKEEP : OUT STD_LOGIC_VECTOR (0 downto 0); outStream_TSTRB : OUT STD_LOGIC_VECTOR (0 downto 0); outStream_TUSER : OUT STD_LOGIC_VECTOR (1 downto 0); outStream_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0); outStream_TID : OUT STD_LOGIC_VECTOR (4 downto 0); outStream_TDEST : OUT STD_LOGIC_VECTOR (5 downto 0); s_axi_CRTL_BUS_AWVALID : IN STD_LOGIC; s_axi_CRTL_BUS_AWREADY : OUT STD_LOGIC; s_axi_CRTL_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_ADDR_WIDTH-1 downto 0); s_axi_CRTL_BUS_WVALID : IN STD_LOGIC; s_axi_CRTL_BUS_WREADY : OUT STD_LOGIC; s_axi_CRTL_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH-1 downto 0); s_axi_CRTL_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH/8-1 downto 0); s_axi_CRTL_BUS_ARVALID : IN STD_LOGIC; s_axi_CRTL_BUS_ARREADY : OUT STD_LOGIC; s_axi_CRTL_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_ADDR_WIDTH-1 downto 0); s_axi_CRTL_BUS_RVALID : OUT STD_LOGIC; s_axi_CRTL_BUS_RREADY : IN STD_LOGIC; s_axi_CRTL_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH-1 downto 0); s_axi_CRTL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_CRTL_BUS_BVALID : OUT STD_LOGIC; s_axi_CRTL_BUS_BREADY : IN STD_LOGIC; s_axi_CRTL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); interrupt : OUT STD_LOGIC; s_axi_KERNEL_BUS_AWVALID : IN STD_LOGIC; s_axi_KERNEL_BUS_AWREADY : OUT STD_LOGIC; s_axi_KERNEL_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_ADDR_WIDTH-1 downto 0); s_axi_KERNEL_BUS_WVALID : IN STD_LOGIC; s_axi_KERNEL_BUS_WREADY : OUT STD_LOGIC; s_axi_KERNEL_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH-1 downto 0); s_axi_KERNEL_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH/8-1 downto 0); s_axi_KERNEL_BUS_ARVALID : IN STD_LOGIC; s_axi_KERNEL_BUS_ARREADY : OUT STD_LOGIC; s_axi_KERNEL_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_ADDR_WIDTH-1 downto 0); s_axi_KERNEL_BUS_RVALID : OUT STD_LOGIC; s_axi_KERNEL_BUS_RREADY : IN STD_LOGIC; s_axi_KERNEL_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH-1 downto 0); s_axi_KERNEL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_KERNEL_BUS_BVALID : OUT STD_LOGIC; s_axi_KERNEL_BUS_BREADY : IN STD_LOGIC; s_axi_KERNEL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0) ); end; architecture behav of doImgProc is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "doImgProc,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.340000,HLS_SYN_LAT=2359816,HLS_SYN_TPT=none,HLS_SYN_MEM=5,HLS_SYN_DSP=9,HLS_SYN_FF=1034,HLS_SYN_LUT=1363}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001"; constant ap_ST_pp0_stg0_fsm_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010"; constant ap_ST_pp0_stg1_fsm_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100"; constant ap_ST_pp0_stg2_fsm_3 : STD_LOGIC_VECTOR (10 downto 0) := "00000001000"; constant ap_ST_pp0_stg3_fsm_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000010000"; constant ap_ST_pp0_stg4_fsm_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000100000"; constant ap_ST_pp0_stg5_fsm_6 : STD_LOGIC_VECTOR (10 downto 0) := "00001000000"; constant ap_ST_pp0_stg6_fsm_7 : STD_LOGIC_VECTOR (10 downto 0) := "00010000000"; constant ap_ST_pp0_stg7_fsm_8 : STD_LOGIC_VECTOR (10 downto 0) := "00100000000"; constant ap_ST_pp0_stg8_fsm_9 : STD_LOGIC_VECTOR (10 downto 0) := "01000000000"; constant ap_ST_st17_fsm_10 : STD_LOGIC_VECTOR (10 downto 0) := "10000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv19_1 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000001"; constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000"; constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001"; constant ap_const_lv64_2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010"; constant ap_const_lv64_3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000011"; constant ap_const_lv64_4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100"; constant ap_const_lv64_5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000101"; constant ap_const_lv64_6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000110"; constant ap_const_lv64_7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000111"; constant ap_const_lv64_8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; constant ap_const_lv19_40001 : STD_LOGIC_VECTOR (18 downto 0) := "1000000000000000001"; constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111"; constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000"; constant ap_const_lv32_1FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111111111"; constant ap_const_lv19_201 : STD_LOGIC_VECTOR (18 downto 0) := "0000000001000000001"; constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv17_0 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv15_0 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000000"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv10_201 : STD_LOGIC_VECTOR (9 downto 0) := "1000000001"; constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001"; signal ap_rst_n_inv : STD_LOGIC; signal ap_start : STD_LOGIC; signal ap_done : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_CS_fsm : STD_LOGIC_VECTOR (10 downto 0) := "00000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_28 : BOOLEAN; signal ap_ready : STD_LOGIC; signal kernel_address0 : STD_LOGIC_VECTOR (3 downto 0); signal kernel_ce0 : STD_LOGIC; signal kernel_q0 : STD_LOGIC_VECTOR (7 downto 0); signal operation : STD_LOGIC_VECTOR (31 downto 0); signal inStream_TDATA_blk_n : STD_LOGIC; signal ap_sig_cseq_ST_pp0_stg1_fsm_2 : STD_LOGIC; signal ap_sig_65 : BOOLEAN; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal exitcond1_reg_1305 : STD_LOGIC_VECTOR (0 downto 0); signal outStream_TDATA_blk_n : STD_LOGIC; signal ap_sig_cseq_ST_pp0_stg5_fsm_6 : STD_LOGIC; signal ap_sig_82 : BOOLEAN; signal tmp_12_reg_1347 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st17_fsm_10 : STD_LOGIC; signal ap_sig_95 : BOOLEAN; signal exitcond_fu_1224_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_id_V_reg_406 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_user_V_reg_419 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_strb_V_reg_432 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_keep_V_reg_445 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_dest_V_reg_458 : STD_LOGIC_VECTOR (5 downto 0); signal col_assign_reg_471 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_reg_482 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_reg_493 : STD_LOGIC_VECTOR (31 downto 0); signal countWait_reg_505 : STD_LOGIC_VECTOR (18 downto 0); signal reg_527 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_188 : BOOLEAN; signal ap_sig_cseq_ST_pp0_stg4_fsm_5 : STD_LOGIC; signal ap_sig_198 : BOOLEAN; signal ap_sig_cseq_ST_pp0_stg7_fsm_8 : STD_LOGIC; signal ap_sig_208 : BOOLEAN; signal reg_531 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_cseq_ST_pp0_stg2_fsm_3 : STD_LOGIC; signal ap_sig_219 : BOOLEAN; signal ap_sig_ioackin_outStream_TREADY : STD_LOGIC; signal ap_sig_cseq_ST_pp0_stg8_fsm_9 : STD_LOGIC; signal ap_sig_237 : BOOLEAN; signal lineBuff_val_0_q0 : STD_LOGIC_VECTOR (7 downto 0); signal reg_535 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_cseq_ST_pp0_stg3_fsm_4 : STD_LOGIC; signal ap_sig_249 : BOOLEAN; signal lineBuff_val_0_q1 : STD_LOGIC_VECTOR (7 downto 0); signal reg_540 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_cseq_ST_pp0_stg6_fsm_7 : STD_LOGIC; signal ap_sig_260 : BOOLEAN; signal ap_sig_cseq_ST_pp0_stg0_fsm_1 : STD_LOGIC; signal ap_sig_270 : BOOLEAN; signal sel_tmp2_fu_544_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp2_reg_1290 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp5_fu_550_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp5_reg_1295 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp8_fu_556_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp8_reg_1300 : STD_LOGIC_VECTOR (0 downto 0); signal exitcond1_fu_562_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_s_fu_568_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_s_reg_1309 : STD_LOGIC_VECTOR (63 downto 0); signal lineBuff_val_1_addr_reg_1314 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_2_addr_reg_1319 : STD_LOGIC_VECTOR (8 downto 0); signal or_cond_fu_606_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_reg_1324 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_fu_612_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_reg_1332 : STD_LOGIC_VECTOR (0 downto 0); signal idxCol_1_fu_630_p3 : STD_LOGIC_VECTOR (31 downto 0); signal idxCol_1_reg_1337 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_1_fu_638_p3 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_1_reg_1342 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_12_fu_646_p2 : STD_LOGIC_VECTOR (0 downto 0); signal phitmp_fu_652_p2 : STD_LOGIC_VECTOR (18 downto 0); signal phitmp_reg_1351 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_keep_V_1_reg_1356 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_strb_V_1_reg_1362 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_user_V_1_reg_1368 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_id_V_1_reg_1374 : STD_LOGIC_VECTOR (4 downto 0); signal ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_dest_V_1_reg_1380 : STD_LOGIC_VECTOR (5 downto 0); signal ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1 : STD_LOGIC_VECTOR (5 downto 0); signal col_assign_1_0_2_fu_703_p2 : STD_LOGIC_VECTOR (31 downto 0); signal col_assign_1_0_2_reg_1396 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp3_fu_716_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp3_reg_1421 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp6_fu_728_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp6_reg_1426 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp9_fu_740_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp9_reg_1431 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal pixConvolved_2_fu_752_p3 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_2_reg_1436 : STD_LOGIC_VECTOR (31 downto 0); signal lineBuff_val_0_load_1_reg_1441 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_q0 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_load_1_reg_1451 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_q1 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_load_2_reg_1456 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_q0 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_load_1_reg_1466 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_q1 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_load_2_reg_1471 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_0_fu_773_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_0_reg_1481 : STD_LOGIC_VECTOR (15 downto 0); signal lineBuff_val_1_load_3_reg_1486 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_load_3_reg_1491 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_14_fu_779_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_14_reg_1496 : STD_LOGIC_VECTOR (7 downto 0); signal tmp4_fu_796_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp4_reg_1504 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_15_fu_801_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_15_reg_1509 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_2_fu_813_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_2_reg_1517 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_16_fu_819_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_16_reg_1522 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_0_fu_830_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_0_reg_1530 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_0_2_i_fu_851_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_0_2_i_reg_1535 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_fu_858_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_reg_1541 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_0_2_i_fu_877_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_0_2_i_reg_1549 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_1_fu_891_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_1_reg_1555 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_1_i_fu_901_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_1_i_reg_1560 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_18_fu_907_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_18_reg_1566 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_i_fu_915_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_i_reg_1574 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_2_fu_928_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_2_reg_1580 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_1_1_i_fu_938_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_1_1_i_reg_1585 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_19_fu_944_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_19_reg_1591 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_1_i_fu_952_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_1_i_reg_1599 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_0_fu_965_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_0_reg_1605 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_1_2_i_fu_975_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_1_2_i_reg_1610 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_20_fu_981_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_20_reg_1616 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_2_i_fu_989_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_2_i_reg_1624 : STD_LOGIC_VECTOR (7 downto 0); signal tmp1_fu_1008_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp1_reg_1630 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_2_i_fu_1017_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_2_i_reg_1635 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_21_fu_1023_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_21_reg_1641 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_i_fu_1031_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_i_reg_1649 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_2_fu_1044_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_2_reg_1655 : STD_LOGIC_VECTOR (15 downto 0); signal tmp3_fu_1054_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp3_reg_1660 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_2_1_i_fu_1063_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_2_1_i_reg_1665 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_22_fu_1069_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_22_reg_1671 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_1_i_fu_1077_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_1_i_reg_1679 : STD_LOGIC_VECTOR (7 downto 0); signal valOutput_fu_1097_p2 : STD_LOGIC_VECTOR (15 downto 0); signal valOutput_reg_1685 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_6_reg_1690 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_reg_1695 : STD_LOGIC_VECTOR (12 downto 0); signal sel_tmp10_fu_1147_p3 : STD_LOGIC_VECTOR (7 downto 0); signal sel_tmp10_reg_1700 : STD_LOGIC_VECTOR (7 downto 0); signal countWait_2_fu_1230_p2 : STD_LOGIC_VECTOR (9 downto 0); signal lineBuff_val_0_address0 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_0_ce0 : STD_LOGIC; signal lineBuff_val_0_we0 : STD_LOGIC; signal lineBuff_val_0_address1 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_0_ce1 : STD_LOGIC; signal lineBuff_val_1_address0 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_1_ce0 : STD_LOGIC; signal lineBuff_val_1_we0 : STD_LOGIC; signal lineBuff_val_1_address1 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_1_ce1 : STD_LOGIC; signal lineBuff_val_2_address0 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_2_ce0 : STD_LOGIC; signal lineBuff_val_2_we0 : STD_LOGIC; signal lineBuff_val_2_address1 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_2_ce1 : STD_LOGIC; signal col_assign_phi_fu_475_p4 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_phi_fu_486_p4 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_phi_fu_497_p4 : STD_LOGIC_VECTOR (31 downto 0); signal countWait_phi_fu_509_p4 : STD_LOGIC_VECTOR (18 downto 0); signal countWait_1_reg_516 : STD_LOGIC_VECTOR (9 downto 0); signal tmp_7_fu_683_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_25_0_1_fu_696_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_25_0_2_fu_759_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_data_V_fu_1217_p3 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ioackin_outStream_TREADY : STD_LOGIC := '0'; signal tmp_3_fu_574_p4 : STD_LOGIC_VECTOR (30 downto 0); signal tmp_4_fu_590_p4 : STD_LOGIC_VECTOR (30 downto 0); signal icmp_fu_584_p2 : STD_LOGIC_VECTOR (0 downto 0); signal icmp4_fu_600_p2 : STD_LOGIC_VECTOR (0 downto 0); signal idxCol_fu_618_p2 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_2_fu_624_p2 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_3_fu_690_p2 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp1_fu_709_p3 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp4_fu_720_p3 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp7_fu_732_p3 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_1_fu_744_p3 : STD_LOGIC_VECTOR (31 downto 0); signal window_val_0_0_fu_773_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_0_fu_773_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_1_fu_790_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_1_fu_790_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_1_fu_790_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_2_fu_813_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_2_fu_813_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_0_fu_830_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_0_fu_830_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_0_1_i_fu_836_p2 : STD_LOGIC_VECTOR (0 downto 0); signal valInWindow_0_minVal_1_0_1_i_fu_840_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_0_2_i_fu_846_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_0_1_i_fu_862_p2 : STD_LOGIC_VECTOR (0 downto 0); signal valInWindow_0_maxVal_1_0_1_i_fu_866_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_11_0_2_i_fu_872_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_1_1_fu_891_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_1_fu_891_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_1_i_fu_897_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_i_fu_911_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_1_2_fu_928_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_2_fu_928_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_1_1_i_fu_934_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_1_i_fu_948_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_2_0_fu_965_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_0_fu_965_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_1_2_i_fu_971_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_2_i_fu_985_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_2_1_fu_1002_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_1_fu_1002_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_1_fu_1002_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_2_i_fu_1013_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_2_i_fu_1027_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_2_2_fu_1044_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_2_fu_1044_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp2_fu_1050_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_2_1_i_fu_1059_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_2_1_i_fu_1073_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp5_fu_1083_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp6_fu_1087_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp7_fu_1092_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_2_2_i_fu_1120_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_2_2_i_fu_1130_p2 : STD_LOGIC_VECTOR (0 downto 0); signal valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_2_2_i_fu_1124_p3 : STD_LOGIC_VECTOR (7 downto 0); signal sel_tmp_fu_1140_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_18_tr_fu_1154_p1 : STD_LOGIC_VECTOR (16 downto 0); signal p_neg_fu_1157_p2 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_8_fu_1163_p4 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_7_cast_fu_1173_p1 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_1_fu_1177_p1 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_2_fu_1180_p2 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_10_cast_fu_1186_p1 : STD_LOGIC_VECTOR (14 downto 0); signal valOutput_1_fu_1190_p3 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_13_fu_1201_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_10_fu_1197_p1 : STD_LOGIC_VECTOR (7 downto 0); signal p_s_fu_1209_p3 : STD_LOGIC_VECTOR (7 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (10 downto 0); signal window_val_0_0_fu_773_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_1_fu_790_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_2_fu_813_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_0_fu_830_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_1_fu_891_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_2_fu_928_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_0_fu_965_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_1_fu_1002_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_2_fu_1044_p10 : STD_LOGIC_VECTOR (15 downto 0); signal ap_sig_1220 : BOOLEAN; component doImgProc_lineBuff_val_0 IS generic ( DataWidth : INTEGER; AddressRange : INTEGER; AddressWidth : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR (8 downto 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR (7 downto 0); q0 : OUT STD_LOGIC_VECTOR (7 downto 0); address1 : IN STD_LOGIC_VECTOR (8 downto 0); ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR (7 downto 0) ); end component; component doImgProc_CRTL_BUS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; ap_start : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; ap_ready : IN STD_LOGIC; ap_done : IN STD_LOGIC; ap_idle : IN STD_LOGIC; operation : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component doImgProc_KERNEL_BUS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; kernel_address0 : IN STD_LOGIC_VECTOR (3 downto 0); kernel_ce0 : IN STD_LOGIC; kernel_q0 : OUT STD_LOGIC_VECTOR (7 downto 0) ); end component; begin doImgProc_CRTL_BUS_s_axi_U : component doImgProc_CRTL_BUS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_CRTL_BUS_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CRTL_BUS_DATA_WIDTH) port map ( AWVALID => s_axi_CRTL_BUS_AWVALID, AWREADY => s_axi_CRTL_BUS_AWREADY, AWADDR => s_axi_CRTL_BUS_AWADDR, WVALID => s_axi_CRTL_BUS_WVALID, WREADY => s_axi_CRTL_BUS_WREADY, WDATA => s_axi_CRTL_BUS_WDATA, WSTRB => s_axi_CRTL_BUS_WSTRB, ARVALID => s_axi_CRTL_BUS_ARVALID, ARREADY => s_axi_CRTL_BUS_ARREADY, ARADDR => s_axi_CRTL_BUS_ARADDR, RVALID => s_axi_CRTL_BUS_RVALID, RREADY => s_axi_CRTL_BUS_RREADY, RDATA => s_axi_CRTL_BUS_RDATA, RRESP => s_axi_CRTL_BUS_RRESP, BVALID => s_axi_CRTL_BUS_BVALID, BREADY => s_axi_CRTL_BUS_BREADY, BRESP => s_axi_CRTL_BUS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, ap_start => ap_start, interrupt => interrupt, ap_ready => ap_ready, ap_done => ap_done, ap_idle => ap_idle, operation => operation); doImgProc_KERNEL_BUS_s_axi_U : component doImgProc_KERNEL_BUS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_KERNEL_BUS_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_KERNEL_BUS_DATA_WIDTH) port map ( AWVALID => s_axi_KERNEL_BUS_AWVALID, AWREADY => s_axi_KERNEL_BUS_AWREADY, AWADDR => s_axi_KERNEL_BUS_AWADDR, WVALID => s_axi_KERNEL_BUS_WVALID, WREADY => s_axi_KERNEL_BUS_WREADY, WDATA => s_axi_KERNEL_BUS_WDATA, WSTRB => s_axi_KERNEL_BUS_WSTRB, ARVALID => s_axi_KERNEL_BUS_ARVALID, ARREADY => s_axi_KERNEL_BUS_ARREADY, ARADDR => s_axi_KERNEL_BUS_ARADDR, RVALID => s_axi_KERNEL_BUS_RVALID, RREADY => s_axi_KERNEL_BUS_RREADY, RDATA => s_axi_KERNEL_BUS_RDATA, RRESP => s_axi_KERNEL_BUS_RRESP, BVALID => s_axi_KERNEL_BUS_BVALID, BREADY => s_axi_KERNEL_BUS_BREADY, BRESP => s_axi_KERNEL_BUS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, kernel_address0 => kernel_address0, kernel_ce0 => kernel_ce0, kernel_q0 => kernel_q0); lineBuff_val_0_U : component doImgProc_lineBuff_val_0 generic map ( DataWidth => 8, AddressRange => 512, AddressWidth => 9) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => lineBuff_val_0_address0, ce0 => lineBuff_val_0_ce0, we0 => lineBuff_val_0_we0, d0 => lineBuff_val_1_q0, q0 => lineBuff_val_0_q0, address1 => lineBuff_val_0_address1, ce1 => lineBuff_val_0_ce1, q1 => lineBuff_val_0_q1); lineBuff_val_1_U : component doImgProc_lineBuff_val_0 generic map ( DataWidth => 8, AddressRange => 512, AddressWidth => 9) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => lineBuff_val_1_address0, ce0 => lineBuff_val_1_ce0, we0 => lineBuff_val_1_we0, d0 => lineBuff_val_2_q0, q0 => lineBuff_val_1_q0, address1 => lineBuff_val_1_address1, ce1 => lineBuff_val_1_ce1, q1 => lineBuff_val_1_q1); lineBuff_val_2_U : component doImgProc_lineBuff_val_0 generic map ( DataWidth => 8, AddressRange => 512, AddressWidth => 9) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => lineBuff_val_2_address0, ce0 => lineBuff_val_2_ce0, we0 => lineBuff_val_2_we0, d0 => inStream_TDATA, q0 => lineBuff_val_2_q0, address1 => lineBuff_val_2_address1, ce1 => lineBuff_val_2_ce1, q1 => lineBuff_val_2_q1); ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; ap_reg_ioackin_outStream_TREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ioackin_outStream_TREADY <= ap_const_logic_0; else if ((((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))))) then ap_reg_ioackin_outStream_TREADY <= ap_const_logic_0; elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_1 = outStream_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_1 = outStream_TREADY)))) then ap_reg_ioackin_outStream_TREADY <= ap_const_logic_1; end if; end if; end if; end process; ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_1; end if; end if; end if; end process; ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_1; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and not((exitcond1_reg_1305 = ap_const_lv1_0))))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; end if; end if; end if; end process; col_assign_reg_471_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then col_assign_reg_471 <= idxCol_1_reg_1337; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then col_assign_reg_471 <= ap_const_lv32_0; end if; end if; end process; countWait_1_reg_516_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)))) then countWait_1_reg_516 <= ap_const_lv10_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then countWait_1_reg_516 <= countWait_2_fu_1230_p2; end if; end if; end process; countWait_reg_505_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then countWait_reg_505 <= phitmp_reg_1351; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then countWait_reg_505 <= ap_const_lv19_1; end if; end if; end process; idxRow_reg_482_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then idxRow_reg_482 <= idxRow_1_reg_1342; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then idxRow_reg_482 <= ap_const_lv32_0; end if; end if; end process; pixConvolved_reg_493_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then pixConvolved_reg_493 <= pixConvolved_2_reg_1436; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then pixConvolved_reg_493 <= ap_const_lv32_0; end if; end if; end process; reg_535_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_sig_1220) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) then reg_535 <= lineBuff_val_0_q1; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then reg_535 <= lineBuff_val_0_q0; end if; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1 <= exitcond1_reg_1305; ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1 <= tmp_12_reg_1347; exitcond1_reg_1305 <= exitcond1_fu_562_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1 <= sel_tmp3_reg_1421; ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1 <= sel_tmp6_reg_1426; ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1 <= sel_tmp9_reg_1431; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)))) then ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1 <= tmp_dest_V_1_reg_1380; ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1 <= tmp_id_V_1_reg_1374; ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1 <= tmp_keep_V_1_reg_1356; ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1 <= tmp_strb_V_1_reg_1362; ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1 <= tmp_user_V_1_reg_1368; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3))) then col_assign_1_0_2_reg_1396 <= col_assign_1_0_2_fu_703_p2; sel_tmp3_reg_1421 <= sel_tmp3_fu_716_p2; sel_tmp6_reg_1426 <= sel_tmp6_fu_728_p2; sel_tmp9_reg_1431 <= sel_tmp9_fu_740_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_562_p2))) then idxCol_1_reg_1337 <= idxCol_1_fu_630_p3; idxRow_1_reg_1342 <= idxRow_1_fu_638_p3; phitmp_reg_1351 <= phitmp_fu_652_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4))) then lineBuff_val_0_load_1_reg_1441 <= lineBuff_val_0_q1; lineBuff_val_1_load_1_reg_1451 <= lineBuff_val_1_q0; lineBuff_val_1_load_2_reg_1456 <= lineBuff_val_1_q1; lineBuff_val_2_load_1_reg_1466 <= lineBuff_val_2_q0; lineBuff_val_2_load_2_reg_1471 <= lineBuff_val_2_q1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_562_p2))) then lineBuff_val_1_addr_reg_1314 <= tmp_s_fu_568_p1(9 - 1 downto 0); lineBuff_val_2_addr_reg_1319 <= tmp_s_fu_568_p1(9 - 1 downto 0); or_cond_reg_1324 <= or_cond_fu_606_p2; tmp_11_reg_1332 <= tmp_11_fu_612_p2; tmp_12_reg_1347 <= tmp_12_fu_646_p2; tmp_s_reg_1309(31 downto 0) <= tmp_s_fu_568_p1(31 downto 0); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5))) then lineBuff_val_1_load_3_reg_1486 <= lineBuff_val_1_q1; lineBuff_val_2_load_3_reg_1491 <= lineBuff_val_2_q1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3))) then pixConvolved_2_reg_1436 <= pixConvolved_2_fu_752_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)))) then reg_527 <= kernel_q0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)))) then reg_531 <= kernel_q0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then reg_540 <= kernel_q0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1))) then sel_tmp10_reg_1700 <= sel_tmp10_fu_1147_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then sel_tmp2_reg_1290 <= sel_tmp2_fu_544_p2; sel_tmp5_reg_1295 <= sel_tmp5_fu_550_p2; sel_tmp8_reg_1300 <= sel_tmp8_fu_556_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and not((ap_const_lv1_0 = sel_tmp9_reg_1431)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp1_reg_1630 <= tmp1_fu_1008_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1)))) then tmp3_reg_1660 <= tmp3_fu_1054_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = sel_tmp9_reg_1431)))) then tmp4_reg_1504 <= tmp4_fu_796_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_14_reg_1496 <= tmp_14_fu_779_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_15_reg_1509 <= tmp_15_fu_801_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_16_reg_1522 <= tmp_16_fu_819_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_17_reg_1541 <= tmp_17_fu_858_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_18_reg_1566 <= tmp_18_fu_907_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_19_reg_1591 <= tmp_19_fu_944_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp_20_reg_1616 <= tmp_20_fu_981_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp_21_reg_1641 <= tmp_21_fu_1023_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1))) then tmp_22_reg_1671 <= tmp_22_fu_1069_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1)))) then tmp_6_reg_1690 <= valOutput_fu_1097_p2(15 downto 15); tmp_9_reg_1695 <= valOutput_fu_1097_p2(15 downto 3); valOutput_reg_1685 <= valOutput_fu_1097_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)))) then tmp_dest_V_1_reg_1380 <= inStream_TDEST; tmp_id_V_1_reg_1374 <= inStream_TID; tmp_keep_V_1_reg_1356 <= inStream_TKEEP; tmp_strb_V_1_reg_1362 <= inStream_TSTRB; tmp_user_V_1_reg_1368 <= inStream_TUSER; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp_dest_V_reg_458 <= ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1; tmp_id_V_reg_406 <= ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1; tmp_keep_V_reg_445 <= ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1; tmp_strb_V_reg_432 <= ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1; tmp_user_V_reg_419 <= ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then valInWindow_0_maxVal_1_0_2_i_reg_1549 <= valInWindow_0_maxVal_1_0_2_i_fu_877_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then valInWindow_0_maxVal_1_1_1_i_reg_1599 <= valInWindow_0_maxVal_1_1_1_i_fu_952_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_maxVal_1_1_2_i_reg_1624 <= valInWindow_0_maxVal_1_1_2_i_fu_989_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then valInWindow_0_maxVal_1_1_i_reg_1574 <= valInWindow_0_maxVal_1_1_i_fu_915_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1)))) then valInWindow_0_maxVal_1_2_1_i_reg_1679 <= valInWindow_0_maxVal_1_2_1_i_fu_1077_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_maxVal_1_2_i_reg_1649 <= valInWindow_0_maxVal_1_2_i_fu_1031_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then valInWindow_0_minVal_1_0_2_i_reg_1535 <= valInWindow_0_minVal_1_0_2_i_fu_851_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then valInWindow_0_minVal_1_1_1_i_reg_1585 <= valInWindow_0_minVal_1_1_1_i_fu_938_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_minVal_1_1_2_i_reg_1610 <= valInWindow_0_minVal_1_1_2_i_fu_975_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then valInWindow_0_minVal_1_1_i_reg_1560 <= valInWindow_0_minVal_1_1_i_fu_901_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1)))) then valInWindow_0_minVal_1_2_1_i_reg_1665 <= valInWindow_0_minVal_1_2_1_i_fu_1063_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_minVal_1_2_i_reg_1635 <= valInWindow_0_minVal_1_2_i_fu_1017_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5))) then window_val_0_0_reg_1481 <= window_val_0_0_fu_773_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7))) then window_val_0_2_reg_1517 <= window_val_0_2_fu_813_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8))) then window_val_1_0_reg_1530 <= window_val_1_0_fu_830_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9))) then window_val_1_1_reg_1555 <= window_val_1_1_fu_891_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then window_val_1_2_reg_1580 <= window_val_1_2_fu_928_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then window_val_2_0_reg_1605 <= window_val_2_0_fu_965_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then window_val_2_2_reg_1655 <= window_val_2_2_fu_1044_p2; end if; end if; end process; tmp_s_reg_1309(63 downto 32) <= "00000000000000000000000000000000"; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, exitcond_fu_1224_p2, ap_sig_188, ap_sig_ioackin_outStream_TREADY, exitcond1_fu_562_p2) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_pp0_stg0_fsm_1 => if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then ap_NS_fsm <= ap_ST_pp0_stg1_fsm_2; else ap_NS_fsm <= ap_ST_st17_fsm_10; end if; when ap_ST_pp0_stg1_fsm_2 => if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) then ap_NS_fsm <= ap_ST_pp0_stg2_fsm_3; else ap_NS_fsm <= ap_ST_pp0_stg1_fsm_2; end if; when ap_ST_pp0_stg2_fsm_3 => ap_NS_fsm <= ap_ST_pp0_stg3_fsm_4; when ap_ST_pp0_stg3_fsm_4 => ap_NS_fsm <= ap_ST_pp0_stg4_fsm_5; when ap_ST_pp0_stg4_fsm_5 => ap_NS_fsm <= ap_ST_pp0_stg5_fsm_6; when ap_ST_pp0_stg5_fsm_6 => if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))))) then ap_NS_fsm <= ap_ST_pp0_stg6_fsm_7; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then ap_NS_fsm <= ap_ST_st17_fsm_10; else ap_NS_fsm <= ap_ST_pp0_stg5_fsm_6; end if; when ap_ST_pp0_stg6_fsm_7 => ap_NS_fsm <= ap_ST_pp0_stg7_fsm_8; when ap_ST_pp0_stg7_fsm_8 => ap_NS_fsm <= ap_ST_pp0_stg8_fsm_9; when ap_ST_pp0_stg8_fsm_9 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_1; when ap_ST_st17_fsm_10 => if ((not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then ap_NS_fsm <= ap_ST_st1_fsm_0; elsif (((ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then ap_NS_fsm <= ap_ST_st17_fsm_10; else ap_NS_fsm <= ap_ST_st17_fsm_10; end if; when others => ap_NS_fsm <= "XXXXXXXXXXX"; end case; end process; ap_done_assign_proc : process(ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_sig_ioackin_outStream_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_sig_ioackin_outStream_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; ap_sig_1220_assign_proc : process(ap_reg_ppiten_pp0_it0, exitcond1_reg_1305) begin ap_sig_1220 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0)); end process; ap_sig_188_assign_proc : process(inStream_TVALID, exitcond1_reg_1305) begin ap_sig_188 <= ((exitcond1_reg_1305 = ap_const_lv1_0) and (inStream_TVALID = ap_const_logic_0)); end process; ap_sig_198_assign_proc : process(ap_CS_fsm) begin ap_sig_198 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5)); end process; ap_sig_208_assign_proc : process(ap_CS_fsm) begin ap_sig_208 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8)); end process; ap_sig_219_assign_proc : process(ap_CS_fsm) begin ap_sig_219 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; ap_sig_237_assign_proc : process(ap_CS_fsm) begin ap_sig_237 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9)); end process; ap_sig_249_assign_proc : process(ap_CS_fsm) begin ap_sig_249 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4)); end process; ap_sig_260_assign_proc : process(ap_CS_fsm) begin ap_sig_260 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7)); end process; ap_sig_270_assign_proc : process(ap_CS_fsm) begin ap_sig_270 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; ap_sig_28_assign_proc : process(ap_CS_fsm) begin ap_sig_28 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; ap_sig_65_assign_proc : process(ap_CS_fsm) begin ap_sig_65 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; ap_sig_82_assign_proc : process(ap_CS_fsm) begin ap_sig_82 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6)); end process; ap_sig_95_assign_proc : process(ap_CS_fsm) begin ap_sig_95 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10)); end process; ap_sig_cseq_ST_pp0_stg0_fsm_1_assign_proc : process(ap_sig_270) begin if (ap_sig_270) then ap_sig_cseq_ST_pp0_stg0_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg0_fsm_1 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg1_fsm_2_assign_proc : process(ap_sig_65) begin if (ap_sig_65) then ap_sig_cseq_ST_pp0_stg1_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg1_fsm_2 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg2_fsm_3_assign_proc : process(ap_sig_219) begin if (ap_sig_219) then ap_sig_cseq_ST_pp0_stg2_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg2_fsm_3 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg3_fsm_4_assign_proc : process(ap_sig_249) begin if (ap_sig_249) then ap_sig_cseq_ST_pp0_stg3_fsm_4 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg3_fsm_4 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg4_fsm_5_assign_proc : process(ap_sig_198) begin if (ap_sig_198) then ap_sig_cseq_ST_pp0_stg4_fsm_5 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg4_fsm_5 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg5_fsm_6_assign_proc : process(ap_sig_82) begin if (ap_sig_82) then ap_sig_cseq_ST_pp0_stg5_fsm_6 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg5_fsm_6 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg6_fsm_7_assign_proc : process(ap_sig_260) begin if (ap_sig_260) then ap_sig_cseq_ST_pp0_stg6_fsm_7 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg6_fsm_7 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg7_fsm_8_assign_proc : process(ap_sig_208) begin if (ap_sig_208) then ap_sig_cseq_ST_pp0_stg7_fsm_8 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg7_fsm_8 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg8_fsm_9_assign_proc : process(ap_sig_237) begin if (ap_sig_237) then ap_sig_cseq_ST_pp0_stg8_fsm_9 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg8_fsm_9 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_st17_fsm_10_assign_proc : process(ap_sig_95) begin if (ap_sig_95) then ap_sig_cseq_ST_st17_fsm_10 <= ap_const_logic_1; else ap_sig_cseq_ST_st17_fsm_10 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_28) begin if (ap_sig_28) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; ap_sig_ioackin_outStream_TREADY_assign_proc : process(outStream_TREADY, ap_reg_ioackin_outStream_TREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)) then ap_sig_ioackin_outStream_TREADY <= outStream_TREADY; else ap_sig_ioackin_outStream_TREADY <= ap_const_logic_1; end if; end process; col_assign_1_0_2_fu_703_p2 <= std_logic_vector(unsigned(ap_const_lv32_2) + unsigned(pixConvolved_phi_fu_497_p4)); col_assign_phi_fu_475_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, col_assign_reg_471, ap_sig_cseq_ST_pp0_stg0_fsm_1, idxCol_1_reg_1337) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then col_assign_phi_fu_475_p4 <= idxCol_1_reg_1337; else col_assign_phi_fu_475_p4 <= col_assign_reg_471; end if; end process; countWait_2_fu_1230_p2 <= std_logic_vector(unsigned(countWait_1_reg_516) + unsigned(ap_const_lv10_1)); countWait_phi_fu_509_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, countWait_reg_505, ap_sig_cseq_ST_pp0_stg0_fsm_1, phitmp_reg_1351) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then countWait_phi_fu_509_p4 <= phitmp_reg_1351; else countWait_phi_fu_509_p4 <= countWait_reg_505; end if; end process; exitcond1_fu_562_p2 <= "1" when (countWait_phi_fu_509_p4 = ap_const_lv19_40001) else "0"; exitcond_fu_1224_p2 <= "1" when (countWait_1_reg_516 = ap_const_lv10_201) else "0"; icmp4_fu_600_p2 <= "1" when (signed(tmp_4_fu_590_p4) > signed(ap_const_lv31_0)) else "0"; icmp_fu_584_p2 <= "1" when (signed(tmp_3_fu_574_p4) > signed(ap_const_lv31_0)) else "0"; idxCol_1_fu_630_p3 <= idxCol_fu_618_p2 when (tmp_11_fu_612_p2(0) = '1') else ap_const_lv32_0; idxCol_fu_618_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(col_assign_phi_fu_475_p4)); idxRow_1_fu_638_p3 <= idxRow_phi_fu_486_p4 when (tmp_11_fu_612_p2(0) = '1') else idxRow_2_fu_624_p2; idxRow_2_fu_624_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(idxRow_phi_fu_486_p4)); idxRow_phi_fu_486_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, idxRow_reg_482, ap_sig_cseq_ST_pp0_stg0_fsm_1, idxRow_1_reg_1342) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then idxRow_phi_fu_486_p4 <= idxRow_1_reg_1342; else idxRow_phi_fu_486_p4 <= idxRow_reg_482; end if; end process; inStream_TDATA_blk_n_assign_proc : process(inStream_TVALID, ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0))) then inStream_TDATA_blk_n <= inStream_TVALID; else inStream_TDATA_blk_n <= ap_const_logic_1; end if; end process; inStream_TREADY_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then inStream_TREADY <= ap_const_logic_1; else inStream_TREADY <= ap_const_logic_0; end if; end process; kernel_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_sig_cseq_ST_pp0_stg4_fsm_5, ap_sig_cseq_ST_pp0_stg7_fsm_8, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg8_fsm_9, ap_sig_cseq_ST_pp0_stg3_fsm_4, ap_sig_cseq_ST_pp0_stg6_fsm_7, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)) then kernel_address0 <= ap_const_lv64_8(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)) then kernel_address0 <= ap_const_lv64_7(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) then kernel_address0 <= ap_const_lv64_6(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6)) then kernel_address0 <= ap_const_lv64_5(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) then kernel_address0 <= ap_const_lv64_4(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then kernel_address0 <= ap_const_lv64_3(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then kernel_address0 <= ap_const_lv64_2(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then kernel_address0 <= ap_const_lv64_1(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then kernel_address0 <= ap_const_lv64_0(4 - 1 downto 0); else kernel_address0 <= "XXXX"; end if; else kernel_address0 <= "XXXX"; end if; end process; kernel_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_188, ap_sig_cseq_ST_pp0_stg4_fsm_5, ap_sig_cseq_ST_pp0_stg7_fsm_8, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_ioackin_outStream_TREADY, ap_sig_cseq_ST_pp0_stg8_fsm_9, ap_sig_cseq_ST_pp0_stg3_fsm_4, ap_sig_cseq_ST_pp0_stg6_fsm_7, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then kernel_ce0 <= ap_const_logic_1; else kernel_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_0_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, tmp_s_reg_1309, tmp_7_fu_683_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then lineBuff_val_0_address0 <= tmp_s_reg_1309(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_0_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0); else lineBuff_val_0_address0 <= "XXXXXXXXX"; end if; else lineBuff_val_0_address0 <= "XXXXXXXXX"; end if; end process; lineBuff_val_0_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then lineBuff_val_0_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_0_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0); else lineBuff_val_0_address1 <= "XXXXXXXXX"; end if; else lineBuff_val_0_address1 <= "XXXXXXXXX"; end if; end process; lineBuff_val_0_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)))) then lineBuff_val_0_ce0 <= ap_const_logic_1; else lineBuff_val_0_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_0_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then lineBuff_val_0_ce1 <= ap_const_logic_1; else lineBuff_val_0_ce1 <= ap_const_logic_0; end if; end process; lineBuff_val_0_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then lineBuff_val_0_we0 <= ap_const_logic_1; else lineBuff_val_0_we0 <= ap_const_logic_0; end if; end process; lineBuff_val_1_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1, tmp_s_fu_568_p1, lineBuff_val_1_addr_reg_1314, tmp_7_fu_683_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then lineBuff_val_1_address0 <= lineBuff_val_1_addr_reg_1314; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_1_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then lineBuff_val_1_address0 <= tmp_s_fu_568_p1(9 - 1 downto 0); else lineBuff_val_1_address0 <= "XXXXXXXXX"; end if; else lineBuff_val_1_address0 <= "XXXXXXXXX"; end if; end process; lineBuff_val_1_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then lineBuff_val_1_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_1_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0); else lineBuff_val_1_address1 <= "XXXXXXXXX"; end if; else lineBuff_val_1_address1 <= "XXXXXXXXX"; end if; end process; lineBuff_val_1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then lineBuff_val_1_ce0 <= ap_const_logic_1; else lineBuff_val_1_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_1_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then lineBuff_val_1_ce1 <= ap_const_logic_1; else lineBuff_val_1_ce1 <= ap_const_logic_0; end if; end process; lineBuff_val_1_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then lineBuff_val_1_we0 <= ap_const_logic_1; else lineBuff_val_1_we0 <= ap_const_logic_0; end if; end process; lineBuff_val_2_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1, tmp_s_fu_568_p1, lineBuff_val_2_addr_reg_1319, tmp_7_fu_683_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then lineBuff_val_2_address0 <= lineBuff_val_2_addr_reg_1319; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_2_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then lineBuff_val_2_address0 <= tmp_s_fu_568_p1(9 - 1 downto 0); else lineBuff_val_2_address0 <= "XXXXXXXXX"; end if; else lineBuff_val_2_address0 <= "XXXXXXXXX"; end if; end process; lineBuff_val_2_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then lineBuff_val_2_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_2_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0); else lineBuff_val_2_address1 <= "XXXXXXXXX"; end if; else lineBuff_val_2_address1 <= "XXXXXXXXX"; end if; end process; lineBuff_val_2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then lineBuff_val_2_ce0 <= ap_const_logic_1; else lineBuff_val_2_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_2_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then lineBuff_val_2_ce1 <= ap_const_logic_1; else lineBuff_val_2_ce1 <= ap_const_logic_0; end if; end process; lineBuff_val_2_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then lineBuff_val_2_we0 <= ap_const_logic_1; else lineBuff_val_2_we0 <= ap_const_logic_0; end if; end process; or_cond_fu_606_p2 <= (icmp_fu_584_p2 and icmp4_fu_600_p2); outStream_TDATA_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_data_V_fu_1217_p3) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TDATA <= ap_const_lv8_0; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TDATA <= tmp_data_V_fu_1217_p3; else outStream_TDATA <= "XXXXXXXX"; end if; end process; outStream_TDATA_blk_n_assign_proc : process(outStream_TREADY, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2)))) then outStream_TDATA_blk_n <= outStream_TREADY; else outStream_TDATA_blk_n <= ap_const_logic_1; end if; end process; outStream_TDEST_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_dest_V_reg_458, ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TDEST <= tmp_dest_V_reg_458; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TDEST <= ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1; else outStream_TDEST <= "XXXXXX"; end if; end process; outStream_TID_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_id_V_reg_406, ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TID <= tmp_id_V_reg_406; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TID <= ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1; else outStream_TID <= "XXXXX"; end if; end process; outStream_TKEEP_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_keep_V_reg_445, ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TKEEP <= tmp_keep_V_reg_445; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TKEEP <= ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1; else outStream_TKEEP <= "X"; end if; end process; outStream_TLAST_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, countWait_1_reg_516) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TLAST <= countWait_1_reg_516(9 downto 9); elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TLAST <= ap_const_lv1_0; else outStream_TLAST <= "X"; end if; end process; outStream_TSTRB_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_strb_V_reg_432, ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TSTRB <= tmp_strb_V_reg_432; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TSTRB <= ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1; else outStream_TSTRB <= "X"; end if; end process; outStream_TUSER_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_user_V_reg_419, ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TUSER <= tmp_user_V_reg_419; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TUSER <= ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1; else outStream_TUSER <= "XX"; end if; end process; outStream_TVALID_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_reg_ioackin_outStream_TREADY) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)))) then outStream_TVALID <= ap_const_logic_1; else outStream_TVALID <= ap_const_logic_0; end if; end process; p_neg_fu_1157_p2 <= std_logic_vector(unsigned(ap_const_lv17_0) - unsigned(tmp_18_tr_fu_1154_p1)); p_s_fu_1209_p3 <= ap_const_lv8_0 when (tmp_13_fu_1201_p3(0) = '1') else tmp_10_fu_1197_p1; phitmp_fu_652_p2 <= std_logic_vector(unsigned(countWait_phi_fu_509_p4) + unsigned(ap_const_lv19_1)); pixConvolved_1_fu_744_p3 <= pixConvolved_3_fu_690_p2 when (sel_tmp9_fu_740_p2(0) = '1') else sel_tmp7_fu_732_p3; pixConvolved_2_fu_752_p3 <= pixConvolved_1_fu_744_p3 when (tmp_11_reg_1332(0) = '1') else ap_const_lv32_0; pixConvolved_3_fu_690_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(pixConvolved_phi_fu_497_p4)); pixConvolved_phi_fu_497_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, pixConvolved_reg_493, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1, pixConvolved_2_reg_1436) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then pixConvolved_phi_fu_497_p4 <= pixConvolved_2_reg_1436; else pixConvolved_phi_fu_497_p4 <= pixConvolved_reg_493; end if; end process; sel_tmp10_fu_1147_p3 <= valInWindow_0_minVal_1_2_2_i_fu_1124_p3 when (ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1(0) = '1') else sel_tmp_fu_1140_p3; sel_tmp1_fu_709_p3 <= pixConvolved_3_fu_690_p2 when (or_cond_reg_1324(0) = '1') else pixConvolved_phi_fu_497_p4; sel_tmp2_fu_544_p2 <= "1" when (operation = ap_const_lv32_2) else "0"; sel_tmp3_fu_716_p2 <= (or_cond_reg_1324 and sel_tmp2_reg_1290); sel_tmp4_fu_720_p3 <= pixConvolved_3_fu_690_p2 when (sel_tmp3_fu_716_p2(0) = '1') else sel_tmp1_fu_709_p3; sel_tmp5_fu_550_p2 <= "1" when (operation = ap_const_lv32_1) else "0"; sel_tmp6_fu_728_p2 <= (or_cond_reg_1324 and sel_tmp5_reg_1295); sel_tmp7_fu_732_p3 <= pixConvolved_3_fu_690_p2 when (sel_tmp6_fu_728_p2(0) = '1') else sel_tmp4_fu_720_p3; sel_tmp8_fu_556_p2 <= "1" when (operation = ap_const_lv32_0) else "0"; sel_tmp9_fu_740_p2 <= (or_cond_reg_1324 and sel_tmp8_reg_1300); sel_tmp_fu_1140_p3 <= valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 when (ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1(0) = '1') else ap_const_lv8_0; tmp1_fu_1008_p2 <= std_logic_vector(unsigned(window_val_2_1_fu_1002_p2) + unsigned(window_val_2_0_reg_1605)); tmp2_fu_1050_p2 <= std_logic_vector(unsigned(window_val_1_1_reg_1555) + unsigned(window_val_1_2_reg_1580)); tmp3_fu_1054_p2 <= std_logic_vector(unsigned(tmp1_reg_1630) + unsigned(tmp2_fu_1050_p2)); tmp4_fu_796_p2 <= std_logic_vector(unsigned(window_val_0_0_reg_1481) + unsigned(window_val_0_1_fu_790_p2)); tmp5_fu_1083_p2 <= std_logic_vector(unsigned(window_val_2_2_reg_1655) + unsigned(window_val_0_2_reg_1517)); tmp6_fu_1087_p2 <= std_logic_vector(unsigned(window_val_1_0_reg_1530) + unsigned(tmp5_fu_1083_p2)); tmp7_fu_1092_p2 <= std_logic_vector(unsigned(tmp4_reg_1504) + unsigned(tmp6_fu_1087_p2)); tmp_10_cast_fu_1186_p1 <= std_logic_vector(resize(unsigned(tmp_1_fu_1177_p1),15)); tmp_10_fu_1197_p1 <= valOutput_1_fu_1190_p3(8 - 1 downto 0); tmp_11_0_1_i_fu_862_p2 <= "1" when (unsigned(tmp_15_reg_1509) > unsigned(tmp_14_reg_1496)) else "0"; tmp_11_0_2_i_fu_872_p2 <= "1" when (unsigned(tmp_16_reg_1522) > unsigned(valInWindow_0_maxVal_1_0_1_i_fu_866_p3)) else "0"; tmp_11_1_1_i_fu_948_p2 <= "1" when (unsigned(tmp_18_reg_1566) > unsigned(valInWindow_0_maxVal_1_1_i_reg_1574)) else "0"; tmp_11_1_2_i_fu_985_p2 <= "1" when (unsigned(tmp_19_reg_1591) > unsigned(valInWindow_0_maxVal_1_1_1_i_reg_1599)) else "0"; tmp_11_1_i_fu_911_p2 <= "1" when (unsigned(tmp_17_reg_1541) > unsigned(valInWindow_0_maxVal_1_0_2_i_reg_1549)) else "0"; tmp_11_2_1_i_fu_1073_p2 <= "1" when (unsigned(tmp_21_reg_1641) > unsigned(valInWindow_0_maxVal_1_2_i_reg_1649)) else "0"; tmp_11_2_2_i_fu_1130_p2 <= "1" when (unsigned(tmp_22_reg_1671) > unsigned(valInWindow_0_maxVal_1_2_1_i_reg_1679)) else "0"; tmp_11_2_i_fu_1027_p2 <= "1" when (unsigned(tmp_20_reg_1616) > unsigned(valInWindow_0_maxVal_1_1_2_i_reg_1624)) else "0"; tmp_11_fu_612_p2 <= "1" when (signed(col_assign_phi_fu_475_p4) < signed(ap_const_lv32_1FF)) else "0"; tmp_12_fu_646_p2 <= "1" when (unsigned(countWait_phi_fu_509_p4) > unsigned(ap_const_lv19_201)) else "0"; tmp_13_fu_1201_p3 <= valOutput_1_fu_1190_p3(14 downto 14); tmp_14_fu_779_p1 <= window_val_0_0_fu_773_p2(8 - 1 downto 0); tmp_15_fu_801_p1 <= window_val_0_1_fu_790_p2(8 - 1 downto 0); tmp_16_fu_819_p1 <= window_val_0_2_fu_813_p2(8 - 1 downto 0); tmp_17_fu_858_p1 <= window_val_1_0_fu_830_p2(8 - 1 downto 0); tmp_18_fu_907_p1 <= window_val_1_1_fu_891_p2(8 - 1 downto 0); tmp_18_tr_fu_1154_p1 <= std_logic_vector(resize(signed(valOutput_reg_1685),17)); tmp_19_fu_944_p1 <= window_val_1_2_fu_928_p2(8 - 1 downto 0); tmp_1_fu_1177_p1 <= std_logic_vector(resize(signed(tmp_9_reg_1695),14)); tmp_20_fu_981_p1 <= window_val_2_0_fu_965_p2(8 - 1 downto 0); tmp_21_fu_1023_p1 <= window_val_2_1_fu_1002_p2(8 - 1 downto 0); tmp_22_fu_1069_p1 <= window_val_2_2_fu_1044_p2(8 - 1 downto 0); tmp_25_0_1_fu_696_p1 <= std_logic_vector(resize(unsigned(pixConvolved_3_fu_690_p2),64)); tmp_25_0_2_fu_759_p1 <= std_logic_vector(resize(unsigned(col_assign_1_0_2_reg_1396),64)); tmp_2_fu_1180_p2 <= std_logic_vector(unsigned(ap_const_lv15_0) - unsigned(tmp_7_cast_fu_1173_p1)); tmp_3_fu_574_p4 <= idxRow_phi_fu_486_p4(31 downto 1); tmp_4_fu_590_p4 <= col_assign_phi_fu_475_p4(31 downto 1); tmp_5_0_1_i_fu_836_p2 <= "1" when (unsigned(tmp_15_reg_1509) < unsigned(tmp_14_reg_1496)) else "0"; tmp_5_0_2_i_fu_846_p2 <= "1" when (unsigned(tmp_16_reg_1522) < unsigned(valInWindow_0_minVal_1_0_1_i_fu_840_p3)) else "0"; tmp_5_1_1_i_fu_934_p2 <= "1" when (unsigned(tmp_18_reg_1566) < unsigned(valInWindow_0_minVal_1_1_i_reg_1560)) else "0"; tmp_5_1_2_i_fu_971_p2 <= "1" when (unsigned(tmp_19_reg_1591) < unsigned(valInWindow_0_minVal_1_1_1_i_reg_1585)) else "0"; tmp_5_1_i_fu_897_p2 <= "1" when (unsigned(tmp_17_reg_1541) < unsigned(valInWindow_0_minVal_1_0_2_i_reg_1535)) else "0"; tmp_5_2_1_i_fu_1059_p2 <= "1" when (unsigned(tmp_21_reg_1641) < unsigned(valInWindow_0_minVal_1_2_i_reg_1635)) else "0"; tmp_5_2_2_i_fu_1120_p2 <= "1" when (unsigned(tmp_22_reg_1671) < unsigned(valInWindow_0_minVal_1_2_1_i_reg_1665)) else "0"; tmp_5_2_i_fu_1013_p2 <= "1" when (unsigned(tmp_20_reg_1616) < unsigned(valInWindow_0_minVal_1_1_2_i_reg_1610)) else "0"; tmp_7_cast_fu_1173_p1 <= std_logic_vector(resize(unsigned(tmp_8_fu_1163_p4),15)); tmp_7_fu_683_p1 <= std_logic_vector(resize(unsigned(pixConvolved_phi_fu_497_p4),64)); tmp_8_fu_1163_p4 <= p_neg_fu_1157_p2(16 downto 3); tmp_data_V_fu_1217_p3 <= p_s_fu_1209_p3 when (ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1(0) = '1') else sel_tmp10_reg_1700; tmp_s_fu_568_p1 <= std_logic_vector(resize(unsigned(col_assign_phi_fu_475_p4),64)); valInWindow_0_maxVal_1_0_1_i_fu_866_p3 <= tmp_15_reg_1509 when (tmp_11_0_1_i_fu_862_p2(0) = '1') else tmp_14_reg_1496; valInWindow_0_maxVal_1_0_2_i_fu_877_p3 <= tmp_16_reg_1522 when (tmp_11_0_2_i_fu_872_p2(0) = '1') else valInWindow_0_maxVal_1_0_1_i_fu_866_p3; valInWindow_0_maxVal_1_1_1_i_fu_952_p3 <= tmp_18_reg_1566 when (tmp_11_1_1_i_fu_948_p2(0) = '1') else valInWindow_0_maxVal_1_1_i_reg_1574; valInWindow_0_maxVal_1_1_2_i_fu_989_p3 <= tmp_19_reg_1591 when (tmp_11_1_2_i_fu_985_p2(0) = '1') else valInWindow_0_maxVal_1_1_1_i_reg_1599; valInWindow_0_maxVal_1_1_i_fu_915_p3 <= tmp_17_reg_1541 when (tmp_11_1_i_fu_911_p2(0) = '1') else valInWindow_0_maxVal_1_0_2_i_reg_1549; valInWindow_0_maxVal_1_2_1_i_fu_1077_p3 <= tmp_21_reg_1641 when (tmp_11_2_1_i_fu_1073_p2(0) = '1') else valInWindow_0_maxVal_1_2_i_reg_1649; valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 <= tmp_22_reg_1671 when (tmp_11_2_2_i_fu_1130_p2(0) = '1') else valInWindow_0_maxVal_1_2_1_i_reg_1679; valInWindow_0_maxVal_1_2_i_fu_1031_p3 <= tmp_20_reg_1616 when (tmp_11_2_i_fu_1027_p2(0) = '1') else valInWindow_0_maxVal_1_1_2_i_reg_1624; valInWindow_0_minVal_1_0_1_i_fu_840_p3 <= tmp_15_reg_1509 when (tmp_5_0_1_i_fu_836_p2(0) = '1') else tmp_14_reg_1496; valInWindow_0_minVal_1_0_2_i_fu_851_p3 <= tmp_16_reg_1522 when (tmp_5_0_2_i_fu_846_p2(0) = '1') else valInWindow_0_minVal_1_0_1_i_fu_840_p3; valInWindow_0_minVal_1_1_1_i_fu_938_p3 <= tmp_18_reg_1566 when (tmp_5_1_1_i_fu_934_p2(0) = '1') else valInWindow_0_minVal_1_1_i_reg_1560; valInWindow_0_minVal_1_1_2_i_fu_975_p3 <= tmp_19_reg_1591 when (tmp_5_1_2_i_fu_971_p2(0) = '1') else valInWindow_0_minVal_1_1_1_i_reg_1585; valInWindow_0_minVal_1_1_i_fu_901_p3 <= tmp_17_reg_1541 when (tmp_5_1_i_fu_897_p2(0) = '1') else valInWindow_0_minVal_1_0_2_i_reg_1535; valInWindow_0_minVal_1_2_1_i_fu_1063_p3 <= tmp_21_reg_1641 when (tmp_5_2_1_i_fu_1059_p2(0) = '1') else valInWindow_0_minVal_1_2_i_reg_1635; valInWindow_0_minVal_1_2_2_i_fu_1124_p3 <= tmp_22_reg_1671 when (tmp_5_2_2_i_fu_1120_p2(0) = '1') else valInWindow_0_minVal_1_2_1_i_reg_1665; valInWindow_0_minVal_1_2_i_fu_1017_p3 <= tmp_20_reg_1616 when (tmp_5_2_i_fu_1013_p2(0) = '1') else valInWindow_0_minVal_1_1_2_i_reg_1610; valOutput_1_fu_1190_p3 <= tmp_2_fu_1180_p2 when (tmp_6_reg_1690(0) = '1') else tmp_10_cast_fu_1186_p1; valOutput_fu_1097_p2 <= std_logic_vector(unsigned(tmp3_reg_1660) + unsigned(tmp7_fu_1092_p2)); window_val_0_0_fu_773_p0 <= reg_527; window_val_0_0_fu_773_p1 <= window_val_0_0_fu_773_p10(8 - 1 downto 0); window_val_0_0_fu_773_p10 <= std_logic_vector(resize(unsigned(reg_535),16)); window_val_0_0_fu_773_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_0_fu_773_p0) * signed('0' &window_val_0_0_fu_773_p1))), 16)); window_val_0_1_fu_790_p0 <= reg_531; window_val_0_1_fu_790_p1 <= window_val_0_1_fu_790_p10(8 - 1 downto 0); window_val_0_1_fu_790_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_0_load_1_reg_1441),16)); window_val_0_1_fu_790_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_1_fu_790_p0) * signed('0' &window_val_0_1_fu_790_p1))), 16)); window_val_0_2_fu_813_p0 <= reg_540; window_val_0_2_fu_813_p1 <= window_val_0_2_fu_813_p10(8 - 1 downto 0); window_val_0_2_fu_813_p10 <= std_logic_vector(resize(unsigned(reg_535),16)); window_val_0_2_fu_813_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_2_fu_813_p0) * signed('0' &window_val_0_2_fu_813_p1))), 16)); window_val_1_0_fu_830_p0 <= reg_527; window_val_1_0_fu_830_p1 <= window_val_1_0_fu_830_p10(8 - 1 downto 0); window_val_1_0_fu_830_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_1_reg_1451),16)); window_val_1_0_fu_830_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_0_fu_830_p0) * signed('0' &window_val_1_0_fu_830_p1))), 16)); window_val_1_1_fu_891_p0 <= reg_531; window_val_1_1_fu_891_p1 <= window_val_1_1_fu_891_p10(8 - 1 downto 0); window_val_1_1_fu_891_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_2_reg_1456),16)); window_val_1_1_fu_891_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_1_fu_891_p0) * signed('0' &window_val_1_1_fu_891_p1))), 16)); window_val_1_2_fu_928_p0 <= reg_540; window_val_1_2_fu_928_p1 <= window_val_1_2_fu_928_p10(8 - 1 downto 0); window_val_1_2_fu_928_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_3_reg_1486),16)); window_val_1_2_fu_928_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_2_fu_928_p0) * signed('0' &window_val_1_2_fu_928_p1))), 16)); window_val_2_0_fu_965_p0 <= reg_527; window_val_2_0_fu_965_p1 <= window_val_2_0_fu_965_p10(8 - 1 downto 0); window_val_2_0_fu_965_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_1_reg_1466),16)); window_val_2_0_fu_965_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_0_fu_965_p0) * signed('0' &window_val_2_0_fu_965_p1))), 16)); window_val_2_1_fu_1002_p0 <= reg_531; window_val_2_1_fu_1002_p1 <= window_val_2_1_fu_1002_p10(8 - 1 downto 0); window_val_2_1_fu_1002_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_2_reg_1471),16)); window_val_2_1_fu_1002_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_1_fu_1002_p0) * signed('0' &window_val_2_1_fu_1002_p1))), 16)); window_val_2_2_fu_1044_p0 <= reg_540; window_val_2_2_fu_1044_p1 <= window_val_2_2_fu_1044_p10(8 - 1 downto 0); window_val_2_2_fu_1044_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_3_reg_1491),16)); window_val_2_2_fu_1044_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_2_fu_1044_p0) * signed('0' &window_val_2_2_fu_1044_p1))), 16)); end behav;
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2016.1 -- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity doImgProc is generic ( C_S_AXI_CRTL_BUS_ADDR_WIDTH : INTEGER := 5; C_S_AXI_CRTL_BUS_DATA_WIDTH : INTEGER := 32; C_S_AXI_KERNEL_BUS_ADDR_WIDTH : INTEGER := 5; C_S_AXI_KERNEL_BUS_DATA_WIDTH : INTEGER := 32 ); port ( ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; inStream_TDATA : IN STD_LOGIC_VECTOR (7 downto 0); inStream_TVALID : IN STD_LOGIC; inStream_TREADY : OUT STD_LOGIC; inStream_TKEEP : IN STD_LOGIC_VECTOR (0 downto 0); inStream_TSTRB : IN STD_LOGIC_VECTOR (0 downto 0); inStream_TUSER : IN STD_LOGIC_VECTOR (1 downto 0); inStream_TLAST : IN STD_LOGIC_VECTOR (0 downto 0); inStream_TID : IN STD_LOGIC_VECTOR (4 downto 0); inStream_TDEST : IN STD_LOGIC_VECTOR (5 downto 0); outStream_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0); outStream_TVALID : OUT STD_LOGIC; outStream_TREADY : IN STD_LOGIC; outStream_TKEEP : OUT STD_LOGIC_VECTOR (0 downto 0); outStream_TSTRB : OUT STD_LOGIC_VECTOR (0 downto 0); outStream_TUSER : OUT STD_LOGIC_VECTOR (1 downto 0); outStream_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0); outStream_TID : OUT STD_LOGIC_VECTOR (4 downto 0); outStream_TDEST : OUT STD_LOGIC_VECTOR (5 downto 0); s_axi_CRTL_BUS_AWVALID : IN STD_LOGIC; s_axi_CRTL_BUS_AWREADY : OUT STD_LOGIC; s_axi_CRTL_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_ADDR_WIDTH-1 downto 0); s_axi_CRTL_BUS_WVALID : IN STD_LOGIC; s_axi_CRTL_BUS_WREADY : OUT STD_LOGIC; s_axi_CRTL_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH-1 downto 0); s_axi_CRTL_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH/8-1 downto 0); s_axi_CRTL_BUS_ARVALID : IN STD_LOGIC; s_axi_CRTL_BUS_ARREADY : OUT STD_LOGIC; s_axi_CRTL_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_ADDR_WIDTH-1 downto 0); s_axi_CRTL_BUS_RVALID : OUT STD_LOGIC; s_axi_CRTL_BUS_RREADY : IN STD_LOGIC; s_axi_CRTL_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH-1 downto 0); s_axi_CRTL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_CRTL_BUS_BVALID : OUT STD_LOGIC; s_axi_CRTL_BUS_BREADY : IN STD_LOGIC; s_axi_CRTL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); interrupt : OUT STD_LOGIC; s_axi_KERNEL_BUS_AWVALID : IN STD_LOGIC; s_axi_KERNEL_BUS_AWREADY : OUT STD_LOGIC; s_axi_KERNEL_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_ADDR_WIDTH-1 downto 0); s_axi_KERNEL_BUS_WVALID : IN STD_LOGIC; s_axi_KERNEL_BUS_WREADY : OUT STD_LOGIC; s_axi_KERNEL_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH-1 downto 0); s_axi_KERNEL_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH/8-1 downto 0); s_axi_KERNEL_BUS_ARVALID : IN STD_LOGIC; s_axi_KERNEL_BUS_ARREADY : OUT STD_LOGIC; s_axi_KERNEL_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_ADDR_WIDTH-1 downto 0); s_axi_KERNEL_BUS_RVALID : OUT STD_LOGIC; s_axi_KERNEL_BUS_RREADY : IN STD_LOGIC; s_axi_KERNEL_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH-1 downto 0); s_axi_KERNEL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_KERNEL_BUS_BVALID : OUT STD_LOGIC; s_axi_KERNEL_BUS_BREADY : IN STD_LOGIC; s_axi_KERNEL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0) ); end; architecture behav of doImgProc is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "doImgProc,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.340000,HLS_SYN_LAT=2359816,HLS_SYN_TPT=none,HLS_SYN_MEM=5,HLS_SYN_DSP=9,HLS_SYN_FF=1034,HLS_SYN_LUT=1363}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001"; constant ap_ST_pp0_stg0_fsm_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010"; constant ap_ST_pp0_stg1_fsm_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100"; constant ap_ST_pp0_stg2_fsm_3 : STD_LOGIC_VECTOR (10 downto 0) := "00000001000"; constant ap_ST_pp0_stg3_fsm_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000010000"; constant ap_ST_pp0_stg4_fsm_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000100000"; constant ap_ST_pp0_stg5_fsm_6 : STD_LOGIC_VECTOR (10 downto 0) := "00001000000"; constant ap_ST_pp0_stg6_fsm_7 : STD_LOGIC_VECTOR (10 downto 0) := "00010000000"; constant ap_ST_pp0_stg7_fsm_8 : STD_LOGIC_VECTOR (10 downto 0) := "00100000000"; constant ap_ST_pp0_stg8_fsm_9 : STD_LOGIC_VECTOR (10 downto 0) := "01000000000"; constant ap_ST_st17_fsm_10 : STD_LOGIC_VECTOR (10 downto 0) := "10000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv19_1 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000001"; constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000"; constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001"; constant ap_const_lv64_2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010"; constant ap_const_lv64_3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000011"; constant ap_const_lv64_4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100"; constant ap_const_lv64_5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000101"; constant ap_const_lv64_6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000110"; constant ap_const_lv64_7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000111"; constant ap_const_lv64_8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; constant ap_const_lv19_40001 : STD_LOGIC_VECTOR (18 downto 0) := "1000000000000000001"; constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111"; constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000"; constant ap_const_lv32_1FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111111111"; constant ap_const_lv19_201 : STD_LOGIC_VECTOR (18 downto 0) := "0000000001000000001"; constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv17_0 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv15_0 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000000"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv10_201 : STD_LOGIC_VECTOR (9 downto 0) := "1000000001"; constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001"; signal ap_rst_n_inv : STD_LOGIC; signal ap_start : STD_LOGIC; signal ap_done : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_CS_fsm : STD_LOGIC_VECTOR (10 downto 0) := "00000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_28 : BOOLEAN; signal ap_ready : STD_LOGIC; signal kernel_address0 : STD_LOGIC_VECTOR (3 downto 0); signal kernel_ce0 : STD_LOGIC; signal kernel_q0 : STD_LOGIC_VECTOR (7 downto 0); signal operation : STD_LOGIC_VECTOR (31 downto 0); signal inStream_TDATA_blk_n : STD_LOGIC; signal ap_sig_cseq_ST_pp0_stg1_fsm_2 : STD_LOGIC; signal ap_sig_65 : BOOLEAN; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal exitcond1_reg_1305 : STD_LOGIC_VECTOR (0 downto 0); signal outStream_TDATA_blk_n : STD_LOGIC; signal ap_sig_cseq_ST_pp0_stg5_fsm_6 : STD_LOGIC; signal ap_sig_82 : BOOLEAN; signal tmp_12_reg_1347 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st17_fsm_10 : STD_LOGIC; signal ap_sig_95 : BOOLEAN; signal exitcond_fu_1224_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_id_V_reg_406 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_user_V_reg_419 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_strb_V_reg_432 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_keep_V_reg_445 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_dest_V_reg_458 : STD_LOGIC_VECTOR (5 downto 0); signal col_assign_reg_471 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_reg_482 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_reg_493 : STD_LOGIC_VECTOR (31 downto 0); signal countWait_reg_505 : STD_LOGIC_VECTOR (18 downto 0); signal reg_527 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_188 : BOOLEAN; signal ap_sig_cseq_ST_pp0_stg4_fsm_5 : STD_LOGIC; signal ap_sig_198 : BOOLEAN; signal ap_sig_cseq_ST_pp0_stg7_fsm_8 : STD_LOGIC; signal ap_sig_208 : BOOLEAN; signal reg_531 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_cseq_ST_pp0_stg2_fsm_3 : STD_LOGIC; signal ap_sig_219 : BOOLEAN; signal ap_sig_ioackin_outStream_TREADY : STD_LOGIC; signal ap_sig_cseq_ST_pp0_stg8_fsm_9 : STD_LOGIC; signal ap_sig_237 : BOOLEAN; signal lineBuff_val_0_q0 : STD_LOGIC_VECTOR (7 downto 0); signal reg_535 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_cseq_ST_pp0_stg3_fsm_4 : STD_LOGIC; signal ap_sig_249 : BOOLEAN; signal lineBuff_val_0_q1 : STD_LOGIC_VECTOR (7 downto 0); signal reg_540 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_cseq_ST_pp0_stg6_fsm_7 : STD_LOGIC; signal ap_sig_260 : BOOLEAN; signal ap_sig_cseq_ST_pp0_stg0_fsm_1 : STD_LOGIC; signal ap_sig_270 : BOOLEAN; signal sel_tmp2_fu_544_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp2_reg_1290 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp5_fu_550_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp5_reg_1295 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp8_fu_556_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp8_reg_1300 : STD_LOGIC_VECTOR (0 downto 0); signal exitcond1_fu_562_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_s_fu_568_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_s_reg_1309 : STD_LOGIC_VECTOR (63 downto 0); signal lineBuff_val_1_addr_reg_1314 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_2_addr_reg_1319 : STD_LOGIC_VECTOR (8 downto 0); signal or_cond_fu_606_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_reg_1324 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_fu_612_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_reg_1332 : STD_LOGIC_VECTOR (0 downto 0); signal idxCol_1_fu_630_p3 : STD_LOGIC_VECTOR (31 downto 0); signal idxCol_1_reg_1337 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_1_fu_638_p3 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_1_reg_1342 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_12_fu_646_p2 : STD_LOGIC_VECTOR (0 downto 0); signal phitmp_fu_652_p2 : STD_LOGIC_VECTOR (18 downto 0); signal phitmp_reg_1351 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_keep_V_1_reg_1356 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_strb_V_1_reg_1362 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_user_V_1_reg_1368 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_id_V_1_reg_1374 : STD_LOGIC_VECTOR (4 downto 0); signal ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_dest_V_1_reg_1380 : STD_LOGIC_VECTOR (5 downto 0); signal ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1 : STD_LOGIC_VECTOR (5 downto 0); signal col_assign_1_0_2_fu_703_p2 : STD_LOGIC_VECTOR (31 downto 0); signal col_assign_1_0_2_reg_1396 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp3_fu_716_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp3_reg_1421 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp6_fu_728_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp6_reg_1426 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp9_fu_740_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp9_reg_1431 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal pixConvolved_2_fu_752_p3 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_2_reg_1436 : STD_LOGIC_VECTOR (31 downto 0); signal lineBuff_val_0_load_1_reg_1441 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_q0 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_load_1_reg_1451 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_q1 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_load_2_reg_1456 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_q0 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_load_1_reg_1466 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_q1 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_load_2_reg_1471 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_0_fu_773_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_0_reg_1481 : STD_LOGIC_VECTOR (15 downto 0); signal lineBuff_val_1_load_3_reg_1486 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_load_3_reg_1491 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_14_fu_779_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_14_reg_1496 : STD_LOGIC_VECTOR (7 downto 0); signal tmp4_fu_796_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp4_reg_1504 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_15_fu_801_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_15_reg_1509 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_2_fu_813_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_2_reg_1517 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_16_fu_819_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_16_reg_1522 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_0_fu_830_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_0_reg_1530 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_0_2_i_fu_851_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_0_2_i_reg_1535 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_fu_858_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_reg_1541 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_0_2_i_fu_877_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_0_2_i_reg_1549 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_1_fu_891_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_1_reg_1555 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_1_i_fu_901_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_1_i_reg_1560 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_18_fu_907_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_18_reg_1566 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_i_fu_915_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_i_reg_1574 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_2_fu_928_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_2_reg_1580 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_1_1_i_fu_938_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_1_1_i_reg_1585 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_19_fu_944_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_19_reg_1591 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_1_i_fu_952_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_1_i_reg_1599 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_0_fu_965_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_0_reg_1605 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_1_2_i_fu_975_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_1_2_i_reg_1610 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_20_fu_981_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_20_reg_1616 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_2_i_fu_989_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_2_i_reg_1624 : STD_LOGIC_VECTOR (7 downto 0); signal tmp1_fu_1008_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp1_reg_1630 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_2_i_fu_1017_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_2_i_reg_1635 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_21_fu_1023_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_21_reg_1641 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_i_fu_1031_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_i_reg_1649 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_2_fu_1044_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_2_reg_1655 : STD_LOGIC_VECTOR (15 downto 0); signal tmp3_fu_1054_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp3_reg_1660 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_2_1_i_fu_1063_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_2_1_i_reg_1665 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_22_fu_1069_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_22_reg_1671 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_1_i_fu_1077_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_1_i_reg_1679 : STD_LOGIC_VECTOR (7 downto 0); signal valOutput_fu_1097_p2 : STD_LOGIC_VECTOR (15 downto 0); signal valOutput_reg_1685 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_6_reg_1690 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_reg_1695 : STD_LOGIC_VECTOR (12 downto 0); signal sel_tmp10_fu_1147_p3 : STD_LOGIC_VECTOR (7 downto 0); signal sel_tmp10_reg_1700 : STD_LOGIC_VECTOR (7 downto 0); signal countWait_2_fu_1230_p2 : STD_LOGIC_VECTOR (9 downto 0); signal lineBuff_val_0_address0 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_0_ce0 : STD_LOGIC; signal lineBuff_val_0_we0 : STD_LOGIC; signal lineBuff_val_0_address1 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_0_ce1 : STD_LOGIC; signal lineBuff_val_1_address0 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_1_ce0 : STD_LOGIC; signal lineBuff_val_1_we0 : STD_LOGIC; signal lineBuff_val_1_address1 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_1_ce1 : STD_LOGIC; signal lineBuff_val_2_address0 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_2_ce0 : STD_LOGIC; signal lineBuff_val_2_we0 : STD_LOGIC; signal lineBuff_val_2_address1 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_2_ce1 : STD_LOGIC; signal col_assign_phi_fu_475_p4 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_phi_fu_486_p4 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_phi_fu_497_p4 : STD_LOGIC_VECTOR (31 downto 0); signal countWait_phi_fu_509_p4 : STD_LOGIC_VECTOR (18 downto 0); signal countWait_1_reg_516 : STD_LOGIC_VECTOR (9 downto 0); signal tmp_7_fu_683_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_25_0_1_fu_696_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_25_0_2_fu_759_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_data_V_fu_1217_p3 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ioackin_outStream_TREADY : STD_LOGIC := '0'; signal tmp_3_fu_574_p4 : STD_LOGIC_VECTOR (30 downto 0); signal tmp_4_fu_590_p4 : STD_LOGIC_VECTOR (30 downto 0); signal icmp_fu_584_p2 : STD_LOGIC_VECTOR (0 downto 0); signal icmp4_fu_600_p2 : STD_LOGIC_VECTOR (0 downto 0); signal idxCol_fu_618_p2 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_2_fu_624_p2 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_3_fu_690_p2 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp1_fu_709_p3 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp4_fu_720_p3 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp7_fu_732_p3 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_1_fu_744_p3 : STD_LOGIC_VECTOR (31 downto 0); signal window_val_0_0_fu_773_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_0_fu_773_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_1_fu_790_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_1_fu_790_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_1_fu_790_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_2_fu_813_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_2_fu_813_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_0_fu_830_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_0_fu_830_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_0_1_i_fu_836_p2 : STD_LOGIC_VECTOR (0 downto 0); signal valInWindow_0_minVal_1_0_1_i_fu_840_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_0_2_i_fu_846_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_0_1_i_fu_862_p2 : STD_LOGIC_VECTOR (0 downto 0); signal valInWindow_0_maxVal_1_0_1_i_fu_866_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_11_0_2_i_fu_872_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_1_1_fu_891_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_1_fu_891_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_1_i_fu_897_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_i_fu_911_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_1_2_fu_928_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_2_fu_928_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_1_1_i_fu_934_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_1_i_fu_948_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_2_0_fu_965_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_0_fu_965_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_1_2_i_fu_971_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_2_i_fu_985_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_2_1_fu_1002_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_1_fu_1002_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_1_fu_1002_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_2_i_fu_1013_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_2_i_fu_1027_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_2_2_fu_1044_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_2_fu_1044_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp2_fu_1050_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_2_1_i_fu_1059_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_2_1_i_fu_1073_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp5_fu_1083_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp6_fu_1087_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp7_fu_1092_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_2_2_i_fu_1120_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_2_2_i_fu_1130_p2 : STD_LOGIC_VECTOR (0 downto 0); signal valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_2_2_i_fu_1124_p3 : STD_LOGIC_VECTOR (7 downto 0); signal sel_tmp_fu_1140_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_18_tr_fu_1154_p1 : STD_LOGIC_VECTOR (16 downto 0); signal p_neg_fu_1157_p2 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_8_fu_1163_p4 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_7_cast_fu_1173_p1 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_1_fu_1177_p1 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_2_fu_1180_p2 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_10_cast_fu_1186_p1 : STD_LOGIC_VECTOR (14 downto 0); signal valOutput_1_fu_1190_p3 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_13_fu_1201_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_10_fu_1197_p1 : STD_LOGIC_VECTOR (7 downto 0); signal p_s_fu_1209_p3 : STD_LOGIC_VECTOR (7 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (10 downto 0); signal window_val_0_0_fu_773_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_1_fu_790_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_2_fu_813_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_0_fu_830_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_1_fu_891_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_2_fu_928_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_0_fu_965_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_1_fu_1002_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_2_fu_1044_p10 : STD_LOGIC_VECTOR (15 downto 0); signal ap_sig_1220 : BOOLEAN; component doImgProc_lineBuff_val_0 IS generic ( DataWidth : INTEGER; AddressRange : INTEGER; AddressWidth : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR (8 downto 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR (7 downto 0); q0 : OUT STD_LOGIC_VECTOR (7 downto 0); address1 : IN STD_LOGIC_VECTOR (8 downto 0); ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR (7 downto 0) ); end component; component doImgProc_CRTL_BUS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; ap_start : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; ap_ready : IN STD_LOGIC; ap_done : IN STD_LOGIC; ap_idle : IN STD_LOGIC; operation : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component doImgProc_KERNEL_BUS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; kernel_address0 : IN STD_LOGIC_VECTOR (3 downto 0); kernel_ce0 : IN STD_LOGIC; kernel_q0 : OUT STD_LOGIC_VECTOR (7 downto 0) ); end component; begin doImgProc_CRTL_BUS_s_axi_U : component doImgProc_CRTL_BUS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_CRTL_BUS_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CRTL_BUS_DATA_WIDTH) port map ( AWVALID => s_axi_CRTL_BUS_AWVALID, AWREADY => s_axi_CRTL_BUS_AWREADY, AWADDR => s_axi_CRTL_BUS_AWADDR, WVALID => s_axi_CRTL_BUS_WVALID, WREADY => s_axi_CRTL_BUS_WREADY, WDATA => s_axi_CRTL_BUS_WDATA, WSTRB => s_axi_CRTL_BUS_WSTRB, ARVALID => s_axi_CRTL_BUS_ARVALID, ARREADY => s_axi_CRTL_BUS_ARREADY, ARADDR => s_axi_CRTL_BUS_ARADDR, RVALID => s_axi_CRTL_BUS_RVALID, RREADY => s_axi_CRTL_BUS_RREADY, RDATA => s_axi_CRTL_BUS_RDATA, RRESP => s_axi_CRTL_BUS_RRESP, BVALID => s_axi_CRTL_BUS_BVALID, BREADY => s_axi_CRTL_BUS_BREADY, BRESP => s_axi_CRTL_BUS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, ap_start => ap_start, interrupt => interrupt, ap_ready => ap_ready, ap_done => ap_done, ap_idle => ap_idle, operation => operation); doImgProc_KERNEL_BUS_s_axi_U : component doImgProc_KERNEL_BUS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_KERNEL_BUS_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_KERNEL_BUS_DATA_WIDTH) port map ( AWVALID => s_axi_KERNEL_BUS_AWVALID, AWREADY => s_axi_KERNEL_BUS_AWREADY, AWADDR => s_axi_KERNEL_BUS_AWADDR, WVALID => s_axi_KERNEL_BUS_WVALID, WREADY => s_axi_KERNEL_BUS_WREADY, WDATA => s_axi_KERNEL_BUS_WDATA, WSTRB => s_axi_KERNEL_BUS_WSTRB, ARVALID => s_axi_KERNEL_BUS_ARVALID, ARREADY => s_axi_KERNEL_BUS_ARREADY, ARADDR => s_axi_KERNEL_BUS_ARADDR, RVALID => s_axi_KERNEL_BUS_RVALID, RREADY => s_axi_KERNEL_BUS_RREADY, RDATA => s_axi_KERNEL_BUS_RDATA, RRESP => s_axi_KERNEL_BUS_RRESP, BVALID => s_axi_KERNEL_BUS_BVALID, BREADY => s_axi_KERNEL_BUS_BREADY, BRESP => s_axi_KERNEL_BUS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, kernel_address0 => kernel_address0, kernel_ce0 => kernel_ce0, kernel_q0 => kernel_q0); lineBuff_val_0_U : component doImgProc_lineBuff_val_0 generic map ( DataWidth => 8, AddressRange => 512, AddressWidth => 9) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => lineBuff_val_0_address0, ce0 => lineBuff_val_0_ce0, we0 => lineBuff_val_0_we0, d0 => lineBuff_val_1_q0, q0 => lineBuff_val_0_q0, address1 => lineBuff_val_0_address1, ce1 => lineBuff_val_0_ce1, q1 => lineBuff_val_0_q1); lineBuff_val_1_U : component doImgProc_lineBuff_val_0 generic map ( DataWidth => 8, AddressRange => 512, AddressWidth => 9) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => lineBuff_val_1_address0, ce0 => lineBuff_val_1_ce0, we0 => lineBuff_val_1_we0, d0 => lineBuff_val_2_q0, q0 => lineBuff_val_1_q0, address1 => lineBuff_val_1_address1, ce1 => lineBuff_val_1_ce1, q1 => lineBuff_val_1_q1); lineBuff_val_2_U : component doImgProc_lineBuff_val_0 generic map ( DataWidth => 8, AddressRange => 512, AddressWidth => 9) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => lineBuff_val_2_address0, ce0 => lineBuff_val_2_ce0, we0 => lineBuff_val_2_we0, d0 => inStream_TDATA, q0 => lineBuff_val_2_q0, address1 => lineBuff_val_2_address1, ce1 => lineBuff_val_2_ce1, q1 => lineBuff_val_2_q1); ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; ap_reg_ioackin_outStream_TREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ioackin_outStream_TREADY <= ap_const_logic_0; else if ((((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))))) then ap_reg_ioackin_outStream_TREADY <= ap_const_logic_0; elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_1 = outStream_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_1 = outStream_TREADY)))) then ap_reg_ioackin_outStream_TREADY <= ap_const_logic_1; end if; end if; end if; end process; ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_1; end if; end if; end if; end process; ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_1; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and not((exitcond1_reg_1305 = ap_const_lv1_0))))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; end if; end if; end if; end process; col_assign_reg_471_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then col_assign_reg_471 <= idxCol_1_reg_1337; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then col_assign_reg_471 <= ap_const_lv32_0; end if; end if; end process; countWait_1_reg_516_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)))) then countWait_1_reg_516 <= ap_const_lv10_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then countWait_1_reg_516 <= countWait_2_fu_1230_p2; end if; end if; end process; countWait_reg_505_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then countWait_reg_505 <= phitmp_reg_1351; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then countWait_reg_505 <= ap_const_lv19_1; end if; end if; end process; idxRow_reg_482_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then idxRow_reg_482 <= idxRow_1_reg_1342; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then idxRow_reg_482 <= ap_const_lv32_0; end if; end if; end process; pixConvolved_reg_493_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then pixConvolved_reg_493 <= pixConvolved_2_reg_1436; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then pixConvolved_reg_493 <= ap_const_lv32_0; end if; end if; end process; reg_535_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_sig_1220) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) then reg_535 <= lineBuff_val_0_q1; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then reg_535 <= lineBuff_val_0_q0; end if; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1 <= exitcond1_reg_1305; ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1 <= tmp_12_reg_1347; exitcond1_reg_1305 <= exitcond1_fu_562_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1 <= sel_tmp3_reg_1421; ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1 <= sel_tmp6_reg_1426; ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1 <= sel_tmp9_reg_1431; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)))) then ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1 <= tmp_dest_V_1_reg_1380; ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1 <= tmp_id_V_1_reg_1374; ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1 <= tmp_keep_V_1_reg_1356; ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1 <= tmp_strb_V_1_reg_1362; ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1 <= tmp_user_V_1_reg_1368; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3))) then col_assign_1_0_2_reg_1396 <= col_assign_1_0_2_fu_703_p2; sel_tmp3_reg_1421 <= sel_tmp3_fu_716_p2; sel_tmp6_reg_1426 <= sel_tmp6_fu_728_p2; sel_tmp9_reg_1431 <= sel_tmp9_fu_740_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_562_p2))) then idxCol_1_reg_1337 <= idxCol_1_fu_630_p3; idxRow_1_reg_1342 <= idxRow_1_fu_638_p3; phitmp_reg_1351 <= phitmp_fu_652_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4))) then lineBuff_val_0_load_1_reg_1441 <= lineBuff_val_0_q1; lineBuff_val_1_load_1_reg_1451 <= lineBuff_val_1_q0; lineBuff_val_1_load_2_reg_1456 <= lineBuff_val_1_q1; lineBuff_val_2_load_1_reg_1466 <= lineBuff_val_2_q0; lineBuff_val_2_load_2_reg_1471 <= lineBuff_val_2_q1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_562_p2))) then lineBuff_val_1_addr_reg_1314 <= tmp_s_fu_568_p1(9 - 1 downto 0); lineBuff_val_2_addr_reg_1319 <= tmp_s_fu_568_p1(9 - 1 downto 0); or_cond_reg_1324 <= or_cond_fu_606_p2; tmp_11_reg_1332 <= tmp_11_fu_612_p2; tmp_12_reg_1347 <= tmp_12_fu_646_p2; tmp_s_reg_1309(31 downto 0) <= tmp_s_fu_568_p1(31 downto 0); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5))) then lineBuff_val_1_load_3_reg_1486 <= lineBuff_val_1_q1; lineBuff_val_2_load_3_reg_1491 <= lineBuff_val_2_q1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3))) then pixConvolved_2_reg_1436 <= pixConvolved_2_fu_752_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)))) then reg_527 <= kernel_q0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)))) then reg_531 <= kernel_q0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then reg_540 <= kernel_q0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1))) then sel_tmp10_reg_1700 <= sel_tmp10_fu_1147_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then sel_tmp2_reg_1290 <= sel_tmp2_fu_544_p2; sel_tmp5_reg_1295 <= sel_tmp5_fu_550_p2; sel_tmp8_reg_1300 <= sel_tmp8_fu_556_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and not((ap_const_lv1_0 = sel_tmp9_reg_1431)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp1_reg_1630 <= tmp1_fu_1008_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1)))) then tmp3_reg_1660 <= tmp3_fu_1054_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = sel_tmp9_reg_1431)))) then tmp4_reg_1504 <= tmp4_fu_796_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_14_reg_1496 <= tmp_14_fu_779_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_15_reg_1509 <= tmp_15_fu_801_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_16_reg_1522 <= tmp_16_fu_819_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_17_reg_1541 <= tmp_17_fu_858_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_18_reg_1566 <= tmp_18_fu_907_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_19_reg_1591 <= tmp_19_fu_944_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp_20_reg_1616 <= tmp_20_fu_981_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp_21_reg_1641 <= tmp_21_fu_1023_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1))) then tmp_22_reg_1671 <= tmp_22_fu_1069_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1)))) then tmp_6_reg_1690 <= valOutput_fu_1097_p2(15 downto 15); tmp_9_reg_1695 <= valOutput_fu_1097_p2(15 downto 3); valOutput_reg_1685 <= valOutput_fu_1097_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)))) then tmp_dest_V_1_reg_1380 <= inStream_TDEST; tmp_id_V_1_reg_1374 <= inStream_TID; tmp_keep_V_1_reg_1356 <= inStream_TKEEP; tmp_strb_V_1_reg_1362 <= inStream_TSTRB; tmp_user_V_1_reg_1368 <= inStream_TUSER; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp_dest_V_reg_458 <= ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1; tmp_id_V_reg_406 <= ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1; tmp_keep_V_reg_445 <= ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1; tmp_strb_V_reg_432 <= ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1; tmp_user_V_reg_419 <= ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then valInWindow_0_maxVal_1_0_2_i_reg_1549 <= valInWindow_0_maxVal_1_0_2_i_fu_877_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then valInWindow_0_maxVal_1_1_1_i_reg_1599 <= valInWindow_0_maxVal_1_1_1_i_fu_952_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_maxVal_1_1_2_i_reg_1624 <= valInWindow_0_maxVal_1_1_2_i_fu_989_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then valInWindow_0_maxVal_1_1_i_reg_1574 <= valInWindow_0_maxVal_1_1_i_fu_915_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1)))) then valInWindow_0_maxVal_1_2_1_i_reg_1679 <= valInWindow_0_maxVal_1_2_1_i_fu_1077_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_maxVal_1_2_i_reg_1649 <= valInWindow_0_maxVal_1_2_i_fu_1031_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then valInWindow_0_minVal_1_0_2_i_reg_1535 <= valInWindow_0_minVal_1_0_2_i_fu_851_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then valInWindow_0_minVal_1_1_1_i_reg_1585 <= valInWindow_0_minVal_1_1_1_i_fu_938_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_minVal_1_1_2_i_reg_1610 <= valInWindow_0_minVal_1_1_2_i_fu_975_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then valInWindow_0_minVal_1_1_i_reg_1560 <= valInWindow_0_minVal_1_1_i_fu_901_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1)))) then valInWindow_0_minVal_1_2_1_i_reg_1665 <= valInWindow_0_minVal_1_2_1_i_fu_1063_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_minVal_1_2_i_reg_1635 <= valInWindow_0_minVal_1_2_i_fu_1017_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5))) then window_val_0_0_reg_1481 <= window_val_0_0_fu_773_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7))) then window_val_0_2_reg_1517 <= window_val_0_2_fu_813_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8))) then window_val_1_0_reg_1530 <= window_val_1_0_fu_830_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9))) then window_val_1_1_reg_1555 <= window_val_1_1_fu_891_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then window_val_1_2_reg_1580 <= window_val_1_2_fu_928_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then window_val_2_0_reg_1605 <= window_val_2_0_fu_965_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then window_val_2_2_reg_1655 <= window_val_2_2_fu_1044_p2; end if; end if; end process; tmp_s_reg_1309(63 downto 32) <= "00000000000000000000000000000000"; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, exitcond_fu_1224_p2, ap_sig_188, ap_sig_ioackin_outStream_TREADY, exitcond1_fu_562_p2) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_pp0_stg0_fsm_1 => if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then ap_NS_fsm <= ap_ST_pp0_stg1_fsm_2; else ap_NS_fsm <= ap_ST_st17_fsm_10; end if; when ap_ST_pp0_stg1_fsm_2 => if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) then ap_NS_fsm <= ap_ST_pp0_stg2_fsm_3; else ap_NS_fsm <= ap_ST_pp0_stg1_fsm_2; end if; when ap_ST_pp0_stg2_fsm_3 => ap_NS_fsm <= ap_ST_pp0_stg3_fsm_4; when ap_ST_pp0_stg3_fsm_4 => ap_NS_fsm <= ap_ST_pp0_stg4_fsm_5; when ap_ST_pp0_stg4_fsm_5 => ap_NS_fsm <= ap_ST_pp0_stg5_fsm_6; when ap_ST_pp0_stg5_fsm_6 => if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))))) then ap_NS_fsm <= ap_ST_pp0_stg6_fsm_7; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then ap_NS_fsm <= ap_ST_st17_fsm_10; else ap_NS_fsm <= ap_ST_pp0_stg5_fsm_6; end if; when ap_ST_pp0_stg6_fsm_7 => ap_NS_fsm <= ap_ST_pp0_stg7_fsm_8; when ap_ST_pp0_stg7_fsm_8 => ap_NS_fsm <= ap_ST_pp0_stg8_fsm_9; when ap_ST_pp0_stg8_fsm_9 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_1; when ap_ST_st17_fsm_10 => if ((not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then ap_NS_fsm <= ap_ST_st1_fsm_0; elsif (((ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then ap_NS_fsm <= ap_ST_st17_fsm_10; else ap_NS_fsm <= ap_ST_st17_fsm_10; end if; when others => ap_NS_fsm <= "XXXXXXXXXXX"; end case; end process; ap_done_assign_proc : process(ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_sig_ioackin_outStream_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_sig_ioackin_outStream_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; ap_sig_1220_assign_proc : process(ap_reg_ppiten_pp0_it0, exitcond1_reg_1305) begin ap_sig_1220 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0)); end process; ap_sig_188_assign_proc : process(inStream_TVALID, exitcond1_reg_1305) begin ap_sig_188 <= ((exitcond1_reg_1305 = ap_const_lv1_0) and (inStream_TVALID = ap_const_logic_0)); end process; ap_sig_198_assign_proc : process(ap_CS_fsm) begin ap_sig_198 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5)); end process; ap_sig_208_assign_proc : process(ap_CS_fsm) begin ap_sig_208 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8)); end process; ap_sig_219_assign_proc : process(ap_CS_fsm) begin ap_sig_219 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; ap_sig_237_assign_proc : process(ap_CS_fsm) begin ap_sig_237 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9)); end process; ap_sig_249_assign_proc : process(ap_CS_fsm) begin ap_sig_249 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4)); end process; ap_sig_260_assign_proc : process(ap_CS_fsm) begin ap_sig_260 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7)); end process; ap_sig_270_assign_proc : process(ap_CS_fsm) begin ap_sig_270 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; ap_sig_28_assign_proc : process(ap_CS_fsm) begin ap_sig_28 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; ap_sig_65_assign_proc : process(ap_CS_fsm) begin ap_sig_65 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; ap_sig_82_assign_proc : process(ap_CS_fsm) begin ap_sig_82 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6)); end process; ap_sig_95_assign_proc : process(ap_CS_fsm) begin ap_sig_95 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10)); end process; ap_sig_cseq_ST_pp0_stg0_fsm_1_assign_proc : process(ap_sig_270) begin if (ap_sig_270) then ap_sig_cseq_ST_pp0_stg0_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg0_fsm_1 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg1_fsm_2_assign_proc : process(ap_sig_65) begin if (ap_sig_65) then ap_sig_cseq_ST_pp0_stg1_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg1_fsm_2 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg2_fsm_3_assign_proc : process(ap_sig_219) begin if (ap_sig_219) then ap_sig_cseq_ST_pp0_stg2_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg2_fsm_3 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg3_fsm_4_assign_proc : process(ap_sig_249) begin if (ap_sig_249) then ap_sig_cseq_ST_pp0_stg3_fsm_4 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg3_fsm_4 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg4_fsm_5_assign_proc : process(ap_sig_198) begin if (ap_sig_198) then ap_sig_cseq_ST_pp0_stg4_fsm_5 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg4_fsm_5 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg5_fsm_6_assign_proc : process(ap_sig_82) begin if (ap_sig_82) then ap_sig_cseq_ST_pp0_stg5_fsm_6 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg5_fsm_6 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg6_fsm_7_assign_proc : process(ap_sig_260) begin if (ap_sig_260) then ap_sig_cseq_ST_pp0_stg6_fsm_7 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg6_fsm_7 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg7_fsm_8_assign_proc : process(ap_sig_208) begin if (ap_sig_208) then ap_sig_cseq_ST_pp0_stg7_fsm_8 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg7_fsm_8 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg8_fsm_9_assign_proc : process(ap_sig_237) begin if (ap_sig_237) then ap_sig_cseq_ST_pp0_stg8_fsm_9 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg8_fsm_9 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_st17_fsm_10_assign_proc : process(ap_sig_95) begin if (ap_sig_95) then ap_sig_cseq_ST_st17_fsm_10 <= ap_const_logic_1; else ap_sig_cseq_ST_st17_fsm_10 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_28) begin if (ap_sig_28) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; ap_sig_ioackin_outStream_TREADY_assign_proc : process(outStream_TREADY, ap_reg_ioackin_outStream_TREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)) then ap_sig_ioackin_outStream_TREADY <= outStream_TREADY; else ap_sig_ioackin_outStream_TREADY <= ap_const_logic_1; end if; end process; col_assign_1_0_2_fu_703_p2 <= std_logic_vector(unsigned(ap_const_lv32_2) + unsigned(pixConvolved_phi_fu_497_p4)); col_assign_phi_fu_475_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, col_assign_reg_471, ap_sig_cseq_ST_pp0_stg0_fsm_1, idxCol_1_reg_1337) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then col_assign_phi_fu_475_p4 <= idxCol_1_reg_1337; else col_assign_phi_fu_475_p4 <= col_assign_reg_471; end if; end process; countWait_2_fu_1230_p2 <= std_logic_vector(unsigned(countWait_1_reg_516) + unsigned(ap_const_lv10_1)); countWait_phi_fu_509_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, countWait_reg_505, ap_sig_cseq_ST_pp0_stg0_fsm_1, phitmp_reg_1351) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then countWait_phi_fu_509_p4 <= phitmp_reg_1351; else countWait_phi_fu_509_p4 <= countWait_reg_505; end if; end process; exitcond1_fu_562_p2 <= "1" when (countWait_phi_fu_509_p4 = ap_const_lv19_40001) else "0"; exitcond_fu_1224_p2 <= "1" when (countWait_1_reg_516 = ap_const_lv10_201) else "0"; icmp4_fu_600_p2 <= "1" when (signed(tmp_4_fu_590_p4) > signed(ap_const_lv31_0)) else "0"; icmp_fu_584_p2 <= "1" when (signed(tmp_3_fu_574_p4) > signed(ap_const_lv31_0)) else "0"; idxCol_1_fu_630_p3 <= idxCol_fu_618_p2 when (tmp_11_fu_612_p2(0) = '1') else ap_const_lv32_0; idxCol_fu_618_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(col_assign_phi_fu_475_p4)); idxRow_1_fu_638_p3 <= idxRow_phi_fu_486_p4 when (tmp_11_fu_612_p2(0) = '1') else idxRow_2_fu_624_p2; idxRow_2_fu_624_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(idxRow_phi_fu_486_p4)); idxRow_phi_fu_486_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, idxRow_reg_482, ap_sig_cseq_ST_pp0_stg0_fsm_1, idxRow_1_reg_1342) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then idxRow_phi_fu_486_p4 <= idxRow_1_reg_1342; else idxRow_phi_fu_486_p4 <= idxRow_reg_482; end if; end process; inStream_TDATA_blk_n_assign_proc : process(inStream_TVALID, ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0))) then inStream_TDATA_blk_n <= inStream_TVALID; else inStream_TDATA_blk_n <= ap_const_logic_1; end if; end process; inStream_TREADY_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then inStream_TREADY <= ap_const_logic_1; else inStream_TREADY <= ap_const_logic_0; end if; end process; kernel_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_sig_cseq_ST_pp0_stg4_fsm_5, ap_sig_cseq_ST_pp0_stg7_fsm_8, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg8_fsm_9, ap_sig_cseq_ST_pp0_stg3_fsm_4, ap_sig_cseq_ST_pp0_stg6_fsm_7, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)) then kernel_address0 <= ap_const_lv64_8(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)) then kernel_address0 <= ap_const_lv64_7(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) then kernel_address0 <= ap_const_lv64_6(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6)) then kernel_address0 <= ap_const_lv64_5(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) then kernel_address0 <= ap_const_lv64_4(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then kernel_address0 <= ap_const_lv64_3(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then kernel_address0 <= ap_const_lv64_2(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then kernel_address0 <= ap_const_lv64_1(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then kernel_address0 <= ap_const_lv64_0(4 - 1 downto 0); else kernel_address0 <= "XXXX"; end if; else kernel_address0 <= "XXXX"; end if; end process; kernel_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_188, ap_sig_cseq_ST_pp0_stg4_fsm_5, ap_sig_cseq_ST_pp0_stg7_fsm_8, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_ioackin_outStream_TREADY, ap_sig_cseq_ST_pp0_stg8_fsm_9, ap_sig_cseq_ST_pp0_stg3_fsm_4, ap_sig_cseq_ST_pp0_stg6_fsm_7, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then kernel_ce0 <= ap_const_logic_1; else kernel_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_0_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, tmp_s_reg_1309, tmp_7_fu_683_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then lineBuff_val_0_address0 <= tmp_s_reg_1309(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_0_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0); else lineBuff_val_0_address0 <= "XXXXXXXXX"; end if; else lineBuff_val_0_address0 <= "XXXXXXXXX"; end if; end process; lineBuff_val_0_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then lineBuff_val_0_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_0_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0); else lineBuff_val_0_address1 <= "XXXXXXXXX"; end if; else lineBuff_val_0_address1 <= "XXXXXXXXX"; end if; end process; lineBuff_val_0_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)))) then lineBuff_val_0_ce0 <= ap_const_logic_1; else lineBuff_val_0_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_0_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then lineBuff_val_0_ce1 <= ap_const_logic_1; else lineBuff_val_0_ce1 <= ap_const_logic_0; end if; end process; lineBuff_val_0_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then lineBuff_val_0_we0 <= ap_const_logic_1; else lineBuff_val_0_we0 <= ap_const_logic_0; end if; end process; lineBuff_val_1_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1, tmp_s_fu_568_p1, lineBuff_val_1_addr_reg_1314, tmp_7_fu_683_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then lineBuff_val_1_address0 <= lineBuff_val_1_addr_reg_1314; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_1_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then lineBuff_val_1_address0 <= tmp_s_fu_568_p1(9 - 1 downto 0); else lineBuff_val_1_address0 <= "XXXXXXXXX"; end if; else lineBuff_val_1_address0 <= "XXXXXXXXX"; end if; end process; lineBuff_val_1_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then lineBuff_val_1_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_1_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0); else lineBuff_val_1_address1 <= "XXXXXXXXX"; end if; else lineBuff_val_1_address1 <= "XXXXXXXXX"; end if; end process; lineBuff_val_1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then lineBuff_val_1_ce0 <= ap_const_logic_1; else lineBuff_val_1_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_1_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then lineBuff_val_1_ce1 <= ap_const_logic_1; else lineBuff_val_1_ce1 <= ap_const_logic_0; end if; end process; lineBuff_val_1_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then lineBuff_val_1_we0 <= ap_const_logic_1; else lineBuff_val_1_we0 <= ap_const_logic_0; end if; end process; lineBuff_val_2_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1, tmp_s_fu_568_p1, lineBuff_val_2_addr_reg_1319, tmp_7_fu_683_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then lineBuff_val_2_address0 <= lineBuff_val_2_addr_reg_1319; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_2_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then lineBuff_val_2_address0 <= tmp_s_fu_568_p1(9 - 1 downto 0); else lineBuff_val_2_address0 <= "XXXXXXXXX"; end if; else lineBuff_val_2_address0 <= "XXXXXXXXX"; end if; end process; lineBuff_val_2_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then lineBuff_val_2_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_2_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0); else lineBuff_val_2_address1 <= "XXXXXXXXX"; end if; else lineBuff_val_2_address1 <= "XXXXXXXXX"; end if; end process; lineBuff_val_2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then lineBuff_val_2_ce0 <= ap_const_logic_1; else lineBuff_val_2_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_2_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then lineBuff_val_2_ce1 <= ap_const_logic_1; else lineBuff_val_2_ce1 <= ap_const_logic_0; end if; end process; lineBuff_val_2_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then lineBuff_val_2_we0 <= ap_const_logic_1; else lineBuff_val_2_we0 <= ap_const_logic_0; end if; end process; or_cond_fu_606_p2 <= (icmp_fu_584_p2 and icmp4_fu_600_p2); outStream_TDATA_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_data_V_fu_1217_p3) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TDATA <= ap_const_lv8_0; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TDATA <= tmp_data_V_fu_1217_p3; else outStream_TDATA <= "XXXXXXXX"; end if; end process; outStream_TDATA_blk_n_assign_proc : process(outStream_TREADY, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2)))) then outStream_TDATA_blk_n <= outStream_TREADY; else outStream_TDATA_blk_n <= ap_const_logic_1; end if; end process; outStream_TDEST_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_dest_V_reg_458, ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TDEST <= tmp_dest_V_reg_458; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TDEST <= ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1; else outStream_TDEST <= "XXXXXX"; end if; end process; outStream_TID_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_id_V_reg_406, ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TID <= tmp_id_V_reg_406; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TID <= ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1; else outStream_TID <= "XXXXX"; end if; end process; outStream_TKEEP_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_keep_V_reg_445, ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TKEEP <= tmp_keep_V_reg_445; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TKEEP <= ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1; else outStream_TKEEP <= "X"; end if; end process; outStream_TLAST_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, countWait_1_reg_516) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TLAST <= countWait_1_reg_516(9 downto 9); elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TLAST <= ap_const_lv1_0; else outStream_TLAST <= "X"; end if; end process; outStream_TSTRB_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_strb_V_reg_432, ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TSTRB <= tmp_strb_V_reg_432; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TSTRB <= ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1; else outStream_TSTRB <= "X"; end if; end process; outStream_TUSER_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_user_V_reg_419, ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TUSER <= tmp_user_V_reg_419; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TUSER <= ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1; else outStream_TUSER <= "XX"; end if; end process; outStream_TVALID_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_reg_ioackin_outStream_TREADY) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)))) then outStream_TVALID <= ap_const_logic_1; else outStream_TVALID <= ap_const_logic_0; end if; end process; p_neg_fu_1157_p2 <= std_logic_vector(unsigned(ap_const_lv17_0) - unsigned(tmp_18_tr_fu_1154_p1)); p_s_fu_1209_p3 <= ap_const_lv8_0 when (tmp_13_fu_1201_p3(0) = '1') else tmp_10_fu_1197_p1; phitmp_fu_652_p2 <= std_logic_vector(unsigned(countWait_phi_fu_509_p4) + unsigned(ap_const_lv19_1)); pixConvolved_1_fu_744_p3 <= pixConvolved_3_fu_690_p2 when (sel_tmp9_fu_740_p2(0) = '1') else sel_tmp7_fu_732_p3; pixConvolved_2_fu_752_p3 <= pixConvolved_1_fu_744_p3 when (tmp_11_reg_1332(0) = '1') else ap_const_lv32_0; pixConvolved_3_fu_690_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(pixConvolved_phi_fu_497_p4)); pixConvolved_phi_fu_497_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, pixConvolved_reg_493, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1, pixConvolved_2_reg_1436) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then pixConvolved_phi_fu_497_p4 <= pixConvolved_2_reg_1436; else pixConvolved_phi_fu_497_p4 <= pixConvolved_reg_493; end if; end process; sel_tmp10_fu_1147_p3 <= valInWindow_0_minVal_1_2_2_i_fu_1124_p3 when (ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1(0) = '1') else sel_tmp_fu_1140_p3; sel_tmp1_fu_709_p3 <= pixConvolved_3_fu_690_p2 when (or_cond_reg_1324(0) = '1') else pixConvolved_phi_fu_497_p4; sel_tmp2_fu_544_p2 <= "1" when (operation = ap_const_lv32_2) else "0"; sel_tmp3_fu_716_p2 <= (or_cond_reg_1324 and sel_tmp2_reg_1290); sel_tmp4_fu_720_p3 <= pixConvolved_3_fu_690_p2 when (sel_tmp3_fu_716_p2(0) = '1') else sel_tmp1_fu_709_p3; sel_tmp5_fu_550_p2 <= "1" when (operation = ap_const_lv32_1) else "0"; sel_tmp6_fu_728_p2 <= (or_cond_reg_1324 and sel_tmp5_reg_1295); sel_tmp7_fu_732_p3 <= pixConvolved_3_fu_690_p2 when (sel_tmp6_fu_728_p2(0) = '1') else sel_tmp4_fu_720_p3; sel_tmp8_fu_556_p2 <= "1" when (operation = ap_const_lv32_0) else "0"; sel_tmp9_fu_740_p2 <= (or_cond_reg_1324 and sel_tmp8_reg_1300); sel_tmp_fu_1140_p3 <= valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 when (ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1(0) = '1') else ap_const_lv8_0; tmp1_fu_1008_p2 <= std_logic_vector(unsigned(window_val_2_1_fu_1002_p2) + unsigned(window_val_2_0_reg_1605)); tmp2_fu_1050_p2 <= std_logic_vector(unsigned(window_val_1_1_reg_1555) + unsigned(window_val_1_2_reg_1580)); tmp3_fu_1054_p2 <= std_logic_vector(unsigned(tmp1_reg_1630) + unsigned(tmp2_fu_1050_p2)); tmp4_fu_796_p2 <= std_logic_vector(unsigned(window_val_0_0_reg_1481) + unsigned(window_val_0_1_fu_790_p2)); tmp5_fu_1083_p2 <= std_logic_vector(unsigned(window_val_2_2_reg_1655) + unsigned(window_val_0_2_reg_1517)); tmp6_fu_1087_p2 <= std_logic_vector(unsigned(window_val_1_0_reg_1530) + unsigned(tmp5_fu_1083_p2)); tmp7_fu_1092_p2 <= std_logic_vector(unsigned(tmp4_reg_1504) + unsigned(tmp6_fu_1087_p2)); tmp_10_cast_fu_1186_p1 <= std_logic_vector(resize(unsigned(tmp_1_fu_1177_p1),15)); tmp_10_fu_1197_p1 <= valOutput_1_fu_1190_p3(8 - 1 downto 0); tmp_11_0_1_i_fu_862_p2 <= "1" when (unsigned(tmp_15_reg_1509) > unsigned(tmp_14_reg_1496)) else "0"; tmp_11_0_2_i_fu_872_p2 <= "1" when (unsigned(tmp_16_reg_1522) > unsigned(valInWindow_0_maxVal_1_0_1_i_fu_866_p3)) else "0"; tmp_11_1_1_i_fu_948_p2 <= "1" when (unsigned(tmp_18_reg_1566) > unsigned(valInWindow_0_maxVal_1_1_i_reg_1574)) else "0"; tmp_11_1_2_i_fu_985_p2 <= "1" when (unsigned(tmp_19_reg_1591) > unsigned(valInWindow_0_maxVal_1_1_1_i_reg_1599)) else "0"; tmp_11_1_i_fu_911_p2 <= "1" when (unsigned(tmp_17_reg_1541) > unsigned(valInWindow_0_maxVal_1_0_2_i_reg_1549)) else "0"; tmp_11_2_1_i_fu_1073_p2 <= "1" when (unsigned(tmp_21_reg_1641) > unsigned(valInWindow_0_maxVal_1_2_i_reg_1649)) else "0"; tmp_11_2_2_i_fu_1130_p2 <= "1" when (unsigned(tmp_22_reg_1671) > unsigned(valInWindow_0_maxVal_1_2_1_i_reg_1679)) else "0"; tmp_11_2_i_fu_1027_p2 <= "1" when (unsigned(tmp_20_reg_1616) > unsigned(valInWindow_0_maxVal_1_1_2_i_reg_1624)) else "0"; tmp_11_fu_612_p2 <= "1" when (signed(col_assign_phi_fu_475_p4) < signed(ap_const_lv32_1FF)) else "0"; tmp_12_fu_646_p2 <= "1" when (unsigned(countWait_phi_fu_509_p4) > unsigned(ap_const_lv19_201)) else "0"; tmp_13_fu_1201_p3 <= valOutput_1_fu_1190_p3(14 downto 14); tmp_14_fu_779_p1 <= window_val_0_0_fu_773_p2(8 - 1 downto 0); tmp_15_fu_801_p1 <= window_val_0_1_fu_790_p2(8 - 1 downto 0); tmp_16_fu_819_p1 <= window_val_0_2_fu_813_p2(8 - 1 downto 0); tmp_17_fu_858_p1 <= window_val_1_0_fu_830_p2(8 - 1 downto 0); tmp_18_fu_907_p1 <= window_val_1_1_fu_891_p2(8 - 1 downto 0); tmp_18_tr_fu_1154_p1 <= std_logic_vector(resize(signed(valOutput_reg_1685),17)); tmp_19_fu_944_p1 <= window_val_1_2_fu_928_p2(8 - 1 downto 0); tmp_1_fu_1177_p1 <= std_logic_vector(resize(signed(tmp_9_reg_1695),14)); tmp_20_fu_981_p1 <= window_val_2_0_fu_965_p2(8 - 1 downto 0); tmp_21_fu_1023_p1 <= window_val_2_1_fu_1002_p2(8 - 1 downto 0); tmp_22_fu_1069_p1 <= window_val_2_2_fu_1044_p2(8 - 1 downto 0); tmp_25_0_1_fu_696_p1 <= std_logic_vector(resize(unsigned(pixConvolved_3_fu_690_p2),64)); tmp_25_0_2_fu_759_p1 <= std_logic_vector(resize(unsigned(col_assign_1_0_2_reg_1396),64)); tmp_2_fu_1180_p2 <= std_logic_vector(unsigned(ap_const_lv15_0) - unsigned(tmp_7_cast_fu_1173_p1)); tmp_3_fu_574_p4 <= idxRow_phi_fu_486_p4(31 downto 1); tmp_4_fu_590_p4 <= col_assign_phi_fu_475_p4(31 downto 1); tmp_5_0_1_i_fu_836_p2 <= "1" when (unsigned(tmp_15_reg_1509) < unsigned(tmp_14_reg_1496)) else "0"; tmp_5_0_2_i_fu_846_p2 <= "1" when (unsigned(tmp_16_reg_1522) < unsigned(valInWindow_0_minVal_1_0_1_i_fu_840_p3)) else "0"; tmp_5_1_1_i_fu_934_p2 <= "1" when (unsigned(tmp_18_reg_1566) < unsigned(valInWindow_0_minVal_1_1_i_reg_1560)) else "0"; tmp_5_1_2_i_fu_971_p2 <= "1" when (unsigned(tmp_19_reg_1591) < unsigned(valInWindow_0_minVal_1_1_1_i_reg_1585)) else "0"; tmp_5_1_i_fu_897_p2 <= "1" when (unsigned(tmp_17_reg_1541) < unsigned(valInWindow_0_minVal_1_0_2_i_reg_1535)) else "0"; tmp_5_2_1_i_fu_1059_p2 <= "1" when (unsigned(tmp_21_reg_1641) < unsigned(valInWindow_0_minVal_1_2_i_reg_1635)) else "0"; tmp_5_2_2_i_fu_1120_p2 <= "1" when (unsigned(tmp_22_reg_1671) < unsigned(valInWindow_0_minVal_1_2_1_i_reg_1665)) else "0"; tmp_5_2_i_fu_1013_p2 <= "1" when (unsigned(tmp_20_reg_1616) < unsigned(valInWindow_0_minVal_1_1_2_i_reg_1610)) else "0"; tmp_7_cast_fu_1173_p1 <= std_logic_vector(resize(unsigned(tmp_8_fu_1163_p4),15)); tmp_7_fu_683_p1 <= std_logic_vector(resize(unsigned(pixConvolved_phi_fu_497_p4),64)); tmp_8_fu_1163_p4 <= p_neg_fu_1157_p2(16 downto 3); tmp_data_V_fu_1217_p3 <= p_s_fu_1209_p3 when (ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1(0) = '1') else sel_tmp10_reg_1700; tmp_s_fu_568_p1 <= std_logic_vector(resize(unsigned(col_assign_phi_fu_475_p4),64)); valInWindow_0_maxVal_1_0_1_i_fu_866_p3 <= tmp_15_reg_1509 when (tmp_11_0_1_i_fu_862_p2(0) = '1') else tmp_14_reg_1496; valInWindow_0_maxVal_1_0_2_i_fu_877_p3 <= tmp_16_reg_1522 when (tmp_11_0_2_i_fu_872_p2(0) = '1') else valInWindow_0_maxVal_1_0_1_i_fu_866_p3; valInWindow_0_maxVal_1_1_1_i_fu_952_p3 <= tmp_18_reg_1566 when (tmp_11_1_1_i_fu_948_p2(0) = '1') else valInWindow_0_maxVal_1_1_i_reg_1574; valInWindow_0_maxVal_1_1_2_i_fu_989_p3 <= tmp_19_reg_1591 when (tmp_11_1_2_i_fu_985_p2(0) = '1') else valInWindow_0_maxVal_1_1_1_i_reg_1599; valInWindow_0_maxVal_1_1_i_fu_915_p3 <= tmp_17_reg_1541 when (tmp_11_1_i_fu_911_p2(0) = '1') else valInWindow_0_maxVal_1_0_2_i_reg_1549; valInWindow_0_maxVal_1_2_1_i_fu_1077_p3 <= tmp_21_reg_1641 when (tmp_11_2_1_i_fu_1073_p2(0) = '1') else valInWindow_0_maxVal_1_2_i_reg_1649; valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 <= tmp_22_reg_1671 when (tmp_11_2_2_i_fu_1130_p2(0) = '1') else valInWindow_0_maxVal_1_2_1_i_reg_1679; valInWindow_0_maxVal_1_2_i_fu_1031_p3 <= tmp_20_reg_1616 when (tmp_11_2_i_fu_1027_p2(0) = '1') else valInWindow_0_maxVal_1_1_2_i_reg_1624; valInWindow_0_minVal_1_0_1_i_fu_840_p3 <= tmp_15_reg_1509 when (tmp_5_0_1_i_fu_836_p2(0) = '1') else tmp_14_reg_1496; valInWindow_0_minVal_1_0_2_i_fu_851_p3 <= tmp_16_reg_1522 when (tmp_5_0_2_i_fu_846_p2(0) = '1') else valInWindow_0_minVal_1_0_1_i_fu_840_p3; valInWindow_0_minVal_1_1_1_i_fu_938_p3 <= tmp_18_reg_1566 when (tmp_5_1_1_i_fu_934_p2(0) = '1') else valInWindow_0_minVal_1_1_i_reg_1560; valInWindow_0_minVal_1_1_2_i_fu_975_p3 <= tmp_19_reg_1591 when (tmp_5_1_2_i_fu_971_p2(0) = '1') else valInWindow_0_minVal_1_1_1_i_reg_1585; valInWindow_0_minVal_1_1_i_fu_901_p3 <= tmp_17_reg_1541 when (tmp_5_1_i_fu_897_p2(0) = '1') else valInWindow_0_minVal_1_0_2_i_reg_1535; valInWindow_0_minVal_1_2_1_i_fu_1063_p3 <= tmp_21_reg_1641 when (tmp_5_2_1_i_fu_1059_p2(0) = '1') else valInWindow_0_minVal_1_2_i_reg_1635; valInWindow_0_minVal_1_2_2_i_fu_1124_p3 <= tmp_22_reg_1671 when (tmp_5_2_2_i_fu_1120_p2(0) = '1') else valInWindow_0_minVal_1_2_1_i_reg_1665; valInWindow_0_minVal_1_2_i_fu_1017_p3 <= tmp_20_reg_1616 when (tmp_5_2_i_fu_1013_p2(0) = '1') else valInWindow_0_minVal_1_1_2_i_reg_1610; valOutput_1_fu_1190_p3 <= tmp_2_fu_1180_p2 when (tmp_6_reg_1690(0) = '1') else tmp_10_cast_fu_1186_p1; valOutput_fu_1097_p2 <= std_logic_vector(unsigned(tmp3_reg_1660) + unsigned(tmp7_fu_1092_p2)); window_val_0_0_fu_773_p0 <= reg_527; window_val_0_0_fu_773_p1 <= window_val_0_0_fu_773_p10(8 - 1 downto 0); window_val_0_0_fu_773_p10 <= std_logic_vector(resize(unsigned(reg_535),16)); window_val_0_0_fu_773_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_0_fu_773_p0) * signed('0' &window_val_0_0_fu_773_p1))), 16)); window_val_0_1_fu_790_p0 <= reg_531; window_val_0_1_fu_790_p1 <= window_val_0_1_fu_790_p10(8 - 1 downto 0); window_val_0_1_fu_790_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_0_load_1_reg_1441),16)); window_val_0_1_fu_790_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_1_fu_790_p0) * signed('0' &window_val_0_1_fu_790_p1))), 16)); window_val_0_2_fu_813_p0 <= reg_540; window_val_0_2_fu_813_p1 <= window_val_0_2_fu_813_p10(8 - 1 downto 0); window_val_0_2_fu_813_p10 <= std_logic_vector(resize(unsigned(reg_535),16)); window_val_0_2_fu_813_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_2_fu_813_p0) * signed('0' &window_val_0_2_fu_813_p1))), 16)); window_val_1_0_fu_830_p0 <= reg_527; window_val_1_0_fu_830_p1 <= window_val_1_0_fu_830_p10(8 - 1 downto 0); window_val_1_0_fu_830_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_1_reg_1451),16)); window_val_1_0_fu_830_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_0_fu_830_p0) * signed('0' &window_val_1_0_fu_830_p1))), 16)); window_val_1_1_fu_891_p0 <= reg_531; window_val_1_1_fu_891_p1 <= window_val_1_1_fu_891_p10(8 - 1 downto 0); window_val_1_1_fu_891_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_2_reg_1456),16)); window_val_1_1_fu_891_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_1_fu_891_p0) * signed('0' &window_val_1_1_fu_891_p1))), 16)); window_val_1_2_fu_928_p0 <= reg_540; window_val_1_2_fu_928_p1 <= window_val_1_2_fu_928_p10(8 - 1 downto 0); window_val_1_2_fu_928_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_3_reg_1486),16)); window_val_1_2_fu_928_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_2_fu_928_p0) * signed('0' &window_val_1_2_fu_928_p1))), 16)); window_val_2_0_fu_965_p0 <= reg_527; window_val_2_0_fu_965_p1 <= window_val_2_0_fu_965_p10(8 - 1 downto 0); window_val_2_0_fu_965_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_1_reg_1466),16)); window_val_2_0_fu_965_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_0_fu_965_p0) * signed('0' &window_val_2_0_fu_965_p1))), 16)); window_val_2_1_fu_1002_p0 <= reg_531; window_val_2_1_fu_1002_p1 <= window_val_2_1_fu_1002_p10(8 - 1 downto 0); window_val_2_1_fu_1002_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_2_reg_1471),16)); window_val_2_1_fu_1002_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_1_fu_1002_p0) * signed('0' &window_val_2_1_fu_1002_p1))), 16)); window_val_2_2_fu_1044_p0 <= reg_540; window_val_2_2_fu_1044_p1 <= window_val_2_2_fu_1044_p10(8 - 1 downto 0); window_val_2_2_fu_1044_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_3_reg_1491),16)); window_val_2_2_fu_1044_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_2_fu_1044_p0) * signed('0' &window_val_2_2_fu_1044_p1))), 16)); end behav;
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2016.1 -- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity doImgProc is generic ( C_S_AXI_CRTL_BUS_ADDR_WIDTH : INTEGER := 5; C_S_AXI_CRTL_BUS_DATA_WIDTH : INTEGER := 32; C_S_AXI_KERNEL_BUS_ADDR_WIDTH : INTEGER := 5; C_S_AXI_KERNEL_BUS_DATA_WIDTH : INTEGER := 32 ); port ( ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; inStream_TDATA : IN STD_LOGIC_VECTOR (7 downto 0); inStream_TVALID : IN STD_LOGIC; inStream_TREADY : OUT STD_LOGIC; inStream_TKEEP : IN STD_LOGIC_VECTOR (0 downto 0); inStream_TSTRB : IN STD_LOGIC_VECTOR (0 downto 0); inStream_TUSER : IN STD_LOGIC_VECTOR (1 downto 0); inStream_TLAST : IN STD_LOGIC_VECTOR (0 downto 0); inStream_TID : IN STD_LOGIC_VECTOR (4 downto 0); inStream_TDEST : IN STD_LOGIC_VECTOR (5 downto 0); outStream_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0); outStream_TVALID : OUT STD_LOGIC; outStream_TREADY : IN STD_LOGIC; outStream_TKEEP : OUT STD_LOGIC_VECTOR (0 downto 0); outStream_TSTRB : OUT STD_LOGIC_VECTOR (0 downto 0); outStream_TUSER : OUT STD_LOGIC_VECTOR (1 downto 0); outStream_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0); outStream_TID : OUT STD_LOGIC_VECTOR (4 downto 0); outStream_TDEST : OUT STD_LOGIC_VECTOR (5 downto 0); s_axi_CRTL_BUS_AWVALID : IN STD_LOGIC; s_axi_CRTL_BUS_AWREADY : OUT STD_LOGIC; s_axi_CRTL_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_ADDR_WIDTH-1 downto 0); s_axi_CRTL_BUS_WVALID : IN STD_LOGIC; s_axi_CRTL_BUS_WREADY : OUT STD_LOGIC; s_axi_CRTL_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH-1 downto 0); s_axi_CRTL_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH/8-1 downto 0); s_axi_CRTL_BUS_ARVALID : IN STD_LOGIC; s_axi_CRTL_BUS_ARREADY : OUT STD_LOGIC; s_axi_CRTL_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_ADDR_WIDTH-1 downto 0); s_axi_CRTL_BUS_RVALID : OUT STD_LOGIC; s_axi_CRTL_BUS_RREADY : IN STD_LOGIC; s_axi_CRTL_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH-1 downto 0); s_axi_CRTL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_CRTL_BUS_BVALID : OUT STD_LOGIC; s_axi_CRTL_BUS_BREADY : IN STD_LOGIC; s_axi_CRTL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); interrupt : OUT STD_LOGIC; s_axi_KERNEL_BUS_AWVALID : IN STD_LOGIC; s_axi_KERNEL_BUS_AWREADY : OUT STD_LOGIC; s_axi_KERNEL_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_ADDR_WIDTH-1 downto 0); s_axi_KERNEL_BUS_WVALID : IN STD_LOGIC; s_axi_KERNEL_BUS_WREADY : OUT STD_LOGIC; s_axi_KERNEL_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH-1 downto 0); s_axi_KERNEL_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH/8-1 downto 0); s_axi_KERNEL_BUS_ARVALID : IN STD_LOGIC; s_axi_KERNEL_BUS_ARREADY : OUT STD_LOGIC; s_axi_KERNEL_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_ADDR_WIDTH-1 downto 0); s_axi_KERNEL_BUS_RVALID : OUT STD_LOGIC; s_axi_KERNEL_BUS_RREADY : IN STD_LOGIC; s_axi_KERNEL_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH-1 downto 0); s_axi_KERNEL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_KERNEL_BUS_BVALID : OUT STD_LOGIC; s_axi_KERNEL_BUS_BREADY : IN STD_LOGIC; s_axi_KERNEL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0) ); end; architecture behav of doImgProc is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "doImgProc,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.340000,HLS_SYN_LAT=2359816,HLS_SYN_TPT=none,HLS_SYN_MEM=5,HLS_SYN_DSP=9,HLS_SYN_FF=1034,HLS_SYN_LUT=1363}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001"; constant ap_ST_pp0_stg0_fsm_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010"; constant ap_ST_pp0_stg1_fsm_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100"; constant ap_ST_pp0_stg2_fsm_3 : STD_LOGIC_VECTOR (10 downto 0) := "00000001000"; constant ap_ST_pp0_stg3_fsm_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000010000"; constant ap_ST_pp0_stg4_fsm_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000100000"; constant ap_ST_pp0_stg5_fsm_6 : STD_LOGIC_VECTOR (10 downto 0) := "00001000000"; constant ap_ST_pp0_stg6_fsm_7 : STD_LOGIC_VECTOR (10 downto 0) := "00010000000"; constant ap_ST_pp0_stg7_fsm_8 : STD_LOGIC_VECTOR (10 downto 0) := "00100000000"; constant ap_ST_pp0_stg8_fsm_9 : STD_LOGIC_VECTOR (10 downto 0) := "01000000000"; constant ap_ST_st17_fsm_10 : STD_LOGIC_VECTOR (10 downto 0) := "10000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv19_1 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000001"; constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000"; constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001"; constant ap_const_lv64_2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010"; constant ap_const_lv64_3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000011"; constant ap_const_lv64_4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100"; constant ap_const_lv64_5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000101"; constant ap_const_lv64_6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000110"; constant ap_const_lv64_7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000111"; constant ap_const_lv64_8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; constant ap_const_lv19_40001 : STD_LOGIC_VECTOR (18 downto 0) := "1000000000000000001"; constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111"; constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000"; constant ap_const_lv32_1FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111111111"; constant ap_const_lv19_201 : STD_LOGIC_VECTOR (18 downto 0) := "0000000001000000001"; constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv17_0 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv15_0 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000000"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv10_201 : STD_LOGIC_VECTOR (9 downto 0) := "1000000001"; constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001"; signal ap_rst_n_inv : STD_LOGIC; signal ap_start : STD_LOGIC; signal ap_done : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_CS_fsm : STD_LOGIC_VECTOR (10 downto 0) := "00000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_28 : BOOLEAN; signal ap_ready : STD_LOGIC; signal kernel_address0 : STD_LOGIC_VECTOR (3 downto 0); signal kernel_ce0 : STD_LOGIC; signal kernel_q0 : STD_LOGIC_VECTOR (7 downto 0); signal operation : STD_LOGIC_VECTOR (31 downto 0); signal inStream_TDATA_blk_n : STD_LOGIC; signal ap_sig_cseq_ST_pp0_stg1_fsm_2 : STD_LOGIC; signal ap_sig_65 : BOOLEAN; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal exitcond1_reg_1305 : STD_LOGIC_VECTOR (0 downto 0); signal outStream_TDATA_blk_n : STD_LOGIC; signal ap_sig_cseq_ST_pp0_stg5_fsm_6 : STD_LOGIC; signal ap_sig_82 : BOOLEAN; signal tmp_12_reg_1347 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st17_fsm_10 : STD_LOGIC; signal ap_sig_95 : BOOLEAN; signal exitcond_fu_1224_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_id_V_reg_406 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_user_V_reg_419 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_strb_V_reg_432 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_keep_V_reg_445 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_dest_V_reg_458 : STD_LOGIC_VECTOR (5 downto 0); signal col_assign_reg_471 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_reg_482 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_reg_493 : STD_LOGIC_VECTOR (31 downto 0); signal countWait_reg_505 : STD_LOGIC_VECTOR (18 downto 0); signal reg_527 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_188 : BOOLEAN; signal ap_sig_cseq_ST_pp0_stg4_fsm_5 : STD_LOGIC; signal ap_sig_198 : BOOLEAN; signal ap_sig_cseq_ST_pp0_stg7_fsm_8 : STD_LOGIC; signal ap_sig_208 : BOOLEAN; signal reg_531 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_cseq_ST_pp0_stg2_fsm_3 : STD_LOGIC; signal ap_sig_219 : BOOLEAN; signal ap_sig_ioackin_outStream_TREADY : STD_LOGIC; signal ap_sig_cseq_ST_pp0_stg8_fsm_9 : STD_LOGIC; signal ap_sig_237 : BOOLEAN; signal lineBuff_val_0_q0 : STD_LOGIC_VECTOR (7 downto 0); signal reg_535 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_cseq_ST_pp0_stg3_fsm_4 : STD_LOGIC; signal ap_sig_249 : BOOLEAN; signal lineBuff_val_0_q1 : STD_LOGIC_VECTOR (7 downto 0); signal reg_540 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_cseq_ST_pp0_stg6_fsm_7 : STD_LOGIC; signal ap_sig_260 : BOOLEAN; signal ap_sig_cseq_ST_pp0_stg0_fsm_1 : STD_LOGIC; signal ap_sig_270 : BOOLEAN; signal sel_tmp2_fu_544_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp2_reg_1290 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp5_fu_550_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp5_reg_1295 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp8_fu_556_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp8_reg_1300 : STD_LOGIC_VECTOR (0 downto 0); signal exitcond1_fu_562_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_s_fu_568_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_s_reg_1309 : STD_LOGIC_VECTOR (63 downto 0); signal lineBuff_val_1_addr_reg_1314 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_2_addr_reg_1319 : STD_LOGIC_VECTOR (8 downto 0); signal or_cond_fu_606_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_reg_1324 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_fu_612_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_reg_1332 : STD_LOGIC_VECTOR (0 downto 0); signal idxCol_1_fu_630_p3 : STD_LOGIC_VECTOR (31 downto 0); signal idxCol_1_reg_1337 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_1_fu_638_p3 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_1_reg_1342 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_12_fu_646_p2 : STD_LOGIC_VECTOR (0 downto 0); signal phitmp_fu_652_p2 : STD_LOGIC_VECTOR (18 downto 0); signal phitmp_reg_1351 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_keep_V_1_reg_1356 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_strb_V_1_reg_1362 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_user_V_1_reg_1368 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_id_V_1_reg_1374 : STD_LOGIC_VECTOR (4 downto 0); signal ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_dest_V_1_reg_1380 : STD_LOGIC_VECTOR (5 downto 0); signal ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1 : STD_LOGIC_VECTOR (5 downto 0); signal col_assign_1_0_2_fu_703_p2 : STD_LOGIC_VECTOR (31 downto 0); signal col_assign_1_0_2_reg_1396 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp3_fu_716_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp3_reg_1421 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp6_fu_728_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp6_reg_1426 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp9_fu_740_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp9_reg_1431 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0); signal pixConvolved_2_fu_752_p3 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_2_reg_1436 : STD_LOGIC_VECTOR (31 downto 0); signal lineBuff_val_0_load_1_reg_1441 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_q0 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_load_1_reg_1451 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_q1 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_1_load_2_reg_1456 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_q0 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_load_1_reg_1466 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_q1 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_load_2_reg_1471 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_0_fu_773_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_0_reg_1481 : STD_LOGIC_VECTOR (15 downto 0); signal lineBuff_val_1_load_3_reg_1486 : STD_LOGIC_VECTOR (7 downto 0); signal lineBuff_val_2_load_3_reg_1491 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_14_fu_779_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_14_reg_1496 : STD_LOGIC_VECTOR (7 downto 0); signal tmp4_fu_796_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp4_reg_1504 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_15_fu_801_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_15_reg_1509 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_2_fu_813_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_2_reg_1517 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_16_fu_819_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_16_reg_1522 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_0_fu_830_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_0_reg_1530 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_0_2_i_fu_851_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_0_2_i_reg_1535 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_fu_858_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_reg_1541 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_0_2_i_fu_877_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_0_2_i_reg_1549 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_1_fu_891_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_1_reg_1555 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_1_i_fu_901_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_1_i_reg_1560 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_18_fu_907_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_18_reg_1566 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_i_fu_915_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_i_reg_1574 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_2_fu_928_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_2_reg_1580 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_1_1_i_fu_938_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_1_1_i_reg_1585 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_19_fu_944_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_19_reg_1591 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_1_i_fu_952_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_1_i_reg_1599 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_0_fu_965_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_0_reg_1605 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_1_2_i_fu_975_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_1_2_i_reg_1610 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_20_fu_981_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_20_reg_1616 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_2_i_fu_989_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_1_2_i_reg_1624 : STD_LOGIC_VECTOR (7 downto 0); signal tmp1_fu_1008_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp1_reg_1630 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_2_i_fu_1017_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_2_i_reg_1635 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_21_fu_1023_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_21_reg_1641 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_i_fu_1031_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_i_reg_1649 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_2_fu_1044_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_2_reg_1655 : STD_LOGIC_VECTOR (15 downto 0); signal tmp3_fu_1054_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp3_reg_1660 : STD_LOGIC_VECTOR (15 downto 0); signal valInWindow_0_minVal_1_2_1_i_fu_1063_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_2_1_i_reg_1665 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_22_fu_1069_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_22_reg_1671 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_1_i_fu_1077_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_maxVal_1_2_1_i_reg_1679 : STD_LOGIC_VECTOR (7 downto 0); signal valOutput_fu_1097_p2 : STD_LOGIC_VECTOR (15 downto 0); signal valOutput_reg_1685 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_6_reg_1690 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_reg_1695 : STD_LOGIC_VECTOR (12 downto 0); signal sel_tmp10_fu_1147_p3 : STD_LOGIC_VECTOR (7 downto 0); signal sel_tmp10_reg_1700 : STD_LOGIC_VECTOR (7 downto 0); signal countWait_2_fu_1230_p2 : STD_LOGIC_VECTOR (9 downto 0); signal lineBuff_val_0_address0 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_0_ce0 : STD_LOGIC; signal lineBuff_val_0_we0 : STD_LOGIC; signal lineBuff_val_0_address1 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_0_ce1 : STD_LOGIC; signal lineBuff_val_1_address0 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_1_ce0 : STD_LOGIC; signal lineBuff_val_1_we0 : STD_LOGIC; signal lineBuff_val_1_address1 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_1_ce1 : STD_LOGIC; signal lineBuff_val_2_address0 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_2_ce0 : STD_LOGIC; signal lineBuff_val_2_we0 : STD_LOGIC; signal lineBuff_val_2_address1 : STD_LOGIC_VECTOR (8 downto 0); signal lineBuff_val_2_ce1 : STD_LOGIC; signal col_assign_phi_fu_475_p4 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_phi_fu_486_p4 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_phi_fu_497_p4 : STD_LOGIC_VECTOR (31 downto 0); signal countWait_phi_fu_509_p4 : STD_LOGIC_VECTOR (18 downto 0); signal countWait_1_reg_516 : STD_LOGIC_VECTOR (9 downto 0); signal tmp_7_fu_683_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_25_0_1_fu_696_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_25_0_2_fu_759_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_data_V_fu_1217_p3 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ioackin_outStream_TREADY : STD_LOGIC := '0'; signal tmp_3_fu_574_p4 : STD_LOGIC_VECTOR (30 downto 0); signal tmp_4_fu_590_p4 : STD_LOGIC_VECTOR (30 downto 0); signal icmp_fu_584_p2 : STD_LOGIC_VECTOR (0 downto 0); signal icmp4_fu_600_p2 : STD_LOGIC_VECTOR (0 downto 0); signal idxCol_fu_618_p2 : STD_LOGIC_VECTOR (31 downto 0); signal idxRow_2_fu_624_p2 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_3_fu_690_p2 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp1_fu_709_p3 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp4_fu_720_p3 : STD_LOGIC_VECTOR (31 downto 0); signal sel_tmp7_fu_732_p3 : STD_LOGIC_VECTOR (31 downto 0); signal pixConvolved_1_fu_744_p3 : STD_LOGIC_VECTOR (31 downto 0); signal window_val_0_0_fu_773_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_0_fu_773_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_1_fu_790_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_1_fu_790_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_1_fu_790_p2 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_2_fu_813_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_0_2_fu_813_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_0_fu_830_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_0_fu_830_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_0_1_i_fu_836_p2 : STD_LOGIC_VECTOR (0 downto 0); signal valInWindow_0_minVal_1_0_1_i_fu_840_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_0_2_i_fu_846_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_0_1_i_fu_862_p2 : STD_LOGIC_VECTOR (0 downto 0); signal valInWindow_0_maxVal_1_0_1_i_fu_866_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_11_0_2_i_fu_872_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_1_1_fu_891_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_1_fu_891_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_1_i_fu_897_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_i_fu_911_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_1_2_fu_928_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_1_2_fu_928_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_1_1_i_fu_934_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_1_i_fu_948_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_2_0_fu_965_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_0_fu_965_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_1_2_i_fu_971_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_2_i_fu_985_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_2_1_fu_1002_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_1_fu_1002_p1 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_1_fu_1002_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_2_i_fu_1013_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_2_i_fu_1027_p2 : STD_LOGIC_VECTOR (0 downto 0); signal window_val_2_2_fu_1044_p0 : STD_LOGIC_VECTOR (7 downto 0); signal window_val_2_2_fu_1044_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp2_fu_1050_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_2_1_i_fu_1059_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_2_1_i_fu_1073_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp5_fu_1083_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp6_fu_1087_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp7_fu_1092_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_2_2_i_fu_1120_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_2_2_i_fu_1130_p2 : STD_LOGIC_VECTOR (0 downto 0); signal valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 : STD_LOGIC_VECTOR (7 downto 0); signal valInWindow_0_minVal_1_2_2_i_fu_1124_p3 : STD_LOGIC_VECTOR (7 downto 0); signal sel_tmp_fu_1140_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_18_tr_fu_1154_p1 : STD_LOGIC_VECTOR (16 downto 0); signal p_neg_fu_1157_p2 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_8_fu_1163_p4 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_7_cast_fu_1173_p1 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_1_fu_1177_p1 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_2_fu_1180_p2 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_10_cast_fu_1186_p1 : STD_LOGIC_VECTOR (14 downto 0); signal valOutput_1_fu_1190_p3 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_13_fu_1201_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_10_fu_1197_p1 : STD_LOGIC_VECTOR (7 downto 0); signal p_s_fu_1209_p3 : STD_LOGIC_VECTOR (7 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (10 downto 0); signal window_val_0_0_fu_773_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_1_fu_790_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_0_2_fu_813_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_0_fu_830_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_1_fu_891_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_1_2_fu_928_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_0_fu_965_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_1_fu_1002_p10 : STD_LOGIC_VECTOR (15 downto 0); signal window_val_2_2_fu_1044_p10 : STD_LOGIC_VECTOR (15 downto 0); signal ap_sig_1220 : BOOLEAN; component doImgProc_lineBuff_val_0 IS generic ( DataWidth : INTEGER; AddressRange : INTEGER; AddressWidth : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR (8 downto 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR (7 downto 0); q0 : OUT STD_LOGIC_VECTOR (7 downto 0); address1 : IN STD_LOGIC_VECTOR (8 downto 0); ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR (7 downto 0) ); end component; component doImgProc_CRTL_BUS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; ap_start : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; ap_ready : IN STD_LOGIC; ap_done : IN STD_LOGIC; ap_idle : IN STD_LOGIC; operation : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component doImgProc_KERNEL_BUS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; kernel_address0 : IN STD_LOGIC_VECTOR (3 downto 0); kernel_ce0 : IN STD_LOGIC; kernel_q0 : OUT STD_LOGIC_VECTOR (7 downto 0) ); end component; begin doImgProc_CRTL_BUS_s_axi_U : component doImgProc_CRTL_BUS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_CRTL_BUS_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CRTL_BUS_DATA_WIDTH) port map ( AWVALID => s_axi_CRTL_BUS_AWVALID, AWREADY => s_axi_CRTL_BUS_AWREADY, AWADDR => s_axi_CRTL_BUS_AWADDR, WVALID => s_axi_CRTL_BUS_WVALID, WREADY => s_axi_CRTL_BUS_WREADY, WDATA => s_axi_CRTL_BUS_WDATA, WSTRB => s_axi_CRTL_BUS_WSTRB, ARVALID => s_axi_CRTL_BUS_ARVALID, ARREADY => s_axi_CRTL_BUS_ARREADY, ARADDR => s_axi_CRTL_BUS_ARADDR, RVALID => s_axi_CRTL_BUS_RVALID, RREADY => s_axi_CRTL_BUS_RREADY, RDATA => s_axi_CRTL_BUS_RDATA, RRESP => s_axi_CRTL_BUS_RRESP, BVALID => s_axi_CRTL_BUS_BVALID, BREADY => s_axi_CRTL_BUS_BREADY, BRESP => s_axi_CRTL_BUS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, ap_start => ap_start, interrupt => interrupt, ap_ready => ap_ready, ap_done => ap_done, ap_idle => ap_idle, operation => operation); doImgProc_KERNEL_BUS_s_axi_U : component doImgProc_KERNEL_BUS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_KERNEL_BUS_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_KERNEL_BUS_DATA_WIDTH) port map ( AWVALID => s_axi_KERNEL_BUS_AWVALID, AWREADY => s_axi_KERNEL_BUS_AWREADY, AWADDR => s_axi_KERNEL_BUS_AWADDR, WVALID => s_axi_KERNEL_BUS_WVALID, WREADY => s_axi_KERNEL_BUS_WREADY, WDATA => s_axi_KERNEL_BUS_WDATA, WSTRB => s_axi_KERNEL_BUS_WSTRB, ARVALID => s_axi_KERNEL_BUS_ARVALID, ARREADY => s_axi_KERNEL_BUS_ARREADY, ARADDR => s_axi_KERNEL_BUS_ARADDR, RVALID => s_axi_KERNEL_BUS_RVALID, RREADY => s_axi_KERNEL_BUS_RREADY, RDATA => s_axi_KERNEL_BUS_RDATA, RRESP => s_axi_KERNEL_BUS_RRESP, BVALID => s_axi_KERNEL_BUS_BVALID, BREADY => s_axi_KERNEL_BUS_BREADY, BRESP => s_axi_KERNEL_BUS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, kernel_address0 => kernel_address0, kernel_ce0 => kernel_ce0, kernel_q0 => kernel_q0); lineBuff_val_0_U : component doImgProc_lineBuff_val_0 generic map ( DataWidth => 8, AddressRange => 512, AddressWidth => 9) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => lineBuff_val_0_address0, ce0 => lineBuff_val_0_ce0, we0 => lineBuff_val_0_we0, d0 => lineBuff_val_1_q0, q0 => lineBuff_val_0_q0, address1 => lineBuff_val_0_address1, ce1 => lineBuff_val_0_ce1, q1 => lineBuff_val_0_q1); lineBuff_val_1_U : component doImgProc_lineBuff_val_0 generic map ( DataWidth => 8, AddressRange => 512, AddressWidth => 9) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => lineBuff_val_1_address0, ce0 => lineBuff_val_1_ce0, we0 => lineBuff_val_1_we0, d0 => lineBuff_val_2_q0, q0 => lineBuff_val_1_q0, address1 => lineBuff_val_1_address1, ce1 => lineBuff_val_1_ce1, q1 => lineBuff_val_1_q1); lineBuff_val_2_U : component doImgProc_lineBuff_val_0 generic map ( DataWidth => 8, AddressRange => 512, AddressWidth => 9) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => lineBuff_val_2_address0, ce0 => lineBuff_val_2_ce0, we0 => lineBuff_val_2_we0, d0 => inStream_TDATA, q0 => lineBuff_val_2_q0, address1 => lineBuff_val_2_address1, ce1 => lineBuff_val_2_ce1, q1 => lineBuff_val_2_q1); ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; ap_reg_ioackin_outStream_TREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ioackin_outStream_TREADY <= ap_const_logic_0; else if ((((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))))) then ap_reg_ioackin_outStream_TREADY <= ap_const_logic_0; elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_1 = outStream_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_1 = outStream_TREADY)))) then ap_reg_ioackin_outStream_TREADY <= ap_const_logic_1; end if; end if; end if; end process; ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_1; end if; end if; end if; end process; ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_1; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and not((exitcond1_reg_1305 = ap_const_lv1_0))))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; end if; end if; end if; end process; col_assign_reg_471_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then col_assign_reg_471 <= idxCol_1_reg_1337; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then col_assign_reg_471 <= ap_const_lv32_0; end if; end if; end process; countWait_1_reg_516_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)))) then countWait_1_reg_516 <= ap_const_lv10_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then countWait_1_reg_516 <= countWait_2_fu_1230_p2; end if; end if; end process; countWait_reg_505_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then countWait_reg_505 <= phitmp_reg_1351; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then countWait_reg_505 <= ap_const_lv19_1; end if; end if; end process; idxRow_reg_482_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then idxRow_reg_482 <= idxRow_1_reg_1342; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then idxRow_reg_482 <= ap_const_lv32_0; end if; end if; end process; pixConvolved_reg_493_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then pixConvolved_reg_493 <= pixConvolved_2_reg_1436; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then pixConvolved_reg_493 <= ap_const_lv32_0; end if; end if; end process; reg_535_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_sig_1220) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) then reg_535 <= lineBuff_val_0_q1; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then reg_535 <= lineBuff_val_0_q0; end if; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1 <= exitcond1_reg_1305; ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1 <= tmp_12_reg_1347; exitcond1_reg_1305 <= exitcond1_fu_562_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1 <= sel_tmp3_reg_1421; ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1 <= sel_tmp6_reg_1426; ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1 <= sel_tmp9_reg_1431; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)))) then ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1 <= tmp_dest_V_1_reg_1380; ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1 <= tmp_id_V_1_reg_1374; ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1 <= tmp_keep_V_1_reg_1356; ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1 <= tmp_strb_V_1_reg_1362; ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1 <= tmp_user_V_1_reg_1368; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3))) then col_assign_1_0_2_reg_1396 <= col_assign_1_0_2_fu_703_p2; sel_tmp3_reg_1421 <= sel_tmp3_fu_716_p2; sel_tmp6_reg_1426 <= sel_tmp6_fu_728_p2; sel_tmp9_reg_1431 <= sel_tmp9_fu_740_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_562_p2))) then idxCol_1_reg_1337 <= idxCol_1_fu_630_p3; idxRow_1_reg_1342 <= idxRow_1_fu_638_p3; phitmp_reg_1351 <= phitmp_fu_652_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4))) then lineBuff_val_0_load_1_reg_1441 <= lineBuff_val_0_q1; lineBuff_val_1_load_1_reg_1451 <= lineBuff_val_1_q0; lineBuff_val_1_load_2_reg_1456 <= lineBuff_val_1_q1; lineBuff_val_2_load_1_reg_1466 <= lineBuff_val_2_q0; lineBuff_val_2_load_2_reg_1471 <= lineBuff_val_2_q1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_562_p2))) then lineBuff_val_1_addr_reg_1314 <= tmp_s_fu_568_p1(9 - 1 downto 0); lineBuff_val_2_addr_reg_1319 <= tmp_s_fu_568_p1(9 - 1 downto 0); or_cond_reg_1324 <= or_cond_fu_606_p2; tmp_11_reg_1332 <= tmp_11_fu_612_p2; tmp_12_reg_1347 <= tmp_12_fu_646_p2; tmp_s_reg_1309(31 downto 0) <= tmp_s_fu_568_p1(31 downto 0); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5))) then lineBuff_val_1_load_3_reg_1486 <= lineBuff_val_1_q1; lineBuff_val_2_load_3_reg_1491 <= lineBuff_val_2_q1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3))) then pixConvolved_2_reg_1436 <= pixConvolved_2_fu_752_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)))) then reg_527 <= kernel_q0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)))) then reg_531 <= kernel_q0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then reg_540 <= kernel_q0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1))) then sel_tmp10_reg_1700 <= sel_tmp10_fu_1147_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then sel_tmp2_reg_1290 <= sel_tmp2_fu_544_p2; sel_tmp5_reg_1295 <= sel_tmp5_fu_550_p2; sel_tmp8_reg_1300 <= sel_tmp8_fu_556_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and not((ap_const_lv1_0 = sel_tmp9_reg_1431)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp1_reg_1630 <= tmp1_fu_1008_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1)))) then tmp3_reg_1660 <= tmp3_fu_1054_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = sel_tmp9_reg_1431)))) then tmp4_reg_1504 <= tmp4_fu_796_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_14_reg_1496 <= tmp_14_fu_779_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_15_reg_1509 <= tmp_15_fu_801_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_16_reg_1522 <= tmp_16_fu_819_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_17_reg_1541 <= tmp_17_fu_858_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_18_reg_1566 <= tmp_18_fu_907_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then tmp_19_reg_1591 <= tmp_19_fu_944_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp_20_reg_1616 <= tmp_20_fu_981_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp_21_reg_1641 <= tmp_21_fu_1023_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1))) then tmp_22_reg_1671 <= tmp_22_fu_1069_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1)))) then tmp_6_reg_1690 <= valOutput_fu_1097_p2(15 downto 15); tmp_9_reg_1695 <= valOutput_fu_1097_p2(15 downto 3); valOutput_reg_1685 <= valOutput_fu_1097_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)))) then tmp_dest_V_1_reg_1380 <= inStream_TDEST; tmp_id_V_1_reg_1374 <= inStream_TID; tmp_keep_V_1_reg_1356 <= inStream_TKEEP; tmp_strb_V_1_reg_1362 <= inStream_TSTRB; tmp_user_V_1_reg_1368 <= inStream_TUSER; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then tmp_dest_V_reg_458 <= ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1; tmp_id_V_reg_406 <= ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1; tmp_keep_V_reg_445 <= ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1; tmp_strb_V_reg_432 <= ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1; tmp_user_V_reg_419 <= ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then valInWindow_0_maxVal_1_0_2_i_reg_1549 <= valInWindow_0_maxVal_1_0_2_i_fu_877_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then valInWindow_0_maxVal_1_1_1_i_reg_1599 <= valInWindow_0_maxVal_1_1_1_i_fu_952_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_maxVal_1_1_2_i_reg_1624 <= valInWindow_0_maxVal_1_1_2_i_fu_989_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then valInWindow_0_maxVal_1_1_i_reg_1574 <= valInWindow_0_maxVal_1_1_i_fu_915_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1)))) then valInWindow_0_maxVal_1_2_1_i_reg_1679 <= valInWindow_0_maxVal_1_2_1_i_fu_1077_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_maxVal_1_2_i_reg_1649 <= valInWindow_0_maxVal_1_2_i_fu_1031_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then valInWindow_0_minVal_1_0_2_i_reg_1535 <= valInWindow_0_minVal_1_0_2_i_fu_851_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then valInWindow_0_minVal_1_1_1_i_reg_1585 <= valInWindow_0_minVal_1_1_1_i_fu_938_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_minVal_1_1_2_i_reg_1610 <= valInWindow_0_minVal_1_1_2_i_fu_975_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then valInWindow_0_minVal_1_1_i_reg_1560 <= valInWindow_0_minVal_1_1_i_fu_901_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1)))) then valInWindow_0_minVal_1_2_1_i_reg_1665 <= valInWindow_0_minVal_1_2_1_i_fu_1063_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then valInWindow_0_minVal_1_2_i_reg_1635 <= valInWindow_0_minVal_1_2_i_fu_1017_p3; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5))) then window_val_0_0_reg_1481 <= window_val_0_0_fu_773_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7))) then window_val_0_2_reg_1517 <= window_val_0_2_fu_813_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8))) then window_val_1_0_reg_1530 <= window_val_1_0_fu_830_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9))) then window_val_1_1_reg_1555 <= window_val_1_1_fu_891_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then window_val_1_2_reg_1580 <= window_val_1_2_fu_928_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then window_val_2_0_reg_1605 <= window_val_2_0_fu_965_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then window_val_2_2_reg_1655 <= window_val_2_2_fu_1044_p2; end if; end if; end process; tmp_s_reg_1309(63 downto 32) <= "00000000000000000000000000000000"; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, exitcond_fu_1224_p2, ap_sig_188, ap_sig_ioackin_outStream_TREADY, exitcond1_fu_562_p2) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_pp0_stg0_fsm_1 => if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then ap_NS_fsm <= ap_ST_pp0_stg1_fsm_2; else ap_NS_fsm <= ap_ST_st17_fsm_10; end if; when ap_ST_pp0_stg1_fsm_2 => if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) then ap_NS_fsm <= ap_ST_pp0_stg2_fsm_3; else ap_NS_fsm <= ap_ST_pp0_stg1_fsm_2; end if; when ap_ST_pp0_stg2_fsm_3 => ap_NS_fsm <= ap_ST_pp0_stg3_fsm_4; when ap_ST_pp0_stg3_fsm_4 => ap_NS_fsm <= ap_ST_pp0_stg4_fsm_5; when ap_ST_pp0_stg4_fsm_5 => ap_NS_fsm <= ap_ST_pp0_stg5_fsm_6; when ap_ST_pp0_stg5_fsm_6 => if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))))) then ap_NS_fsm <= ap_ST_pp0_stg6_fsm_7; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then ap_NS_fsm <= ap_ST_st17_fsm_10; else ap_NS_fsm <= ap_ST_pp0_stg5_fsm_6; end if; when ap_ST_pp0_stg6_fsm_7 => ap_NS_fsm <= ap_ST_pp0_stg7_fsm_8; when ap_ST_pp0_stg7_fsm_8 => ap_NS_fsm <= ap_ST_pp0_stg8_fsm_9; when ap_ST_pp0_stg8_fsm_9 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_1; when ap_ST_st17_fsm_10 => if ((not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then ap_NS_fsm <= ap_ST_st1_fsm_0; elsif (((ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then ap_NS_fsm <= ap_ST_st17_fsm_10; else ap_NS_fsm <= ap_ST_st17_fsm_10; end if; when others => ap_NS_fsm <= "XXXXXXXXXXX"; end case; end process; ap_done_assign_proc : process(ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_sig_ioackin_outStream_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_sig_ioackin_outStream_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; ap_sig_1220_assign_proc : process(ap_reg_ppiten_pp0_it0, exitcond1_reg_1305) begin ap_sig_1220 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0)); end process; ap_sig_188_assign_proc : process(inStream_TVALID, exitcond1_reg_1305) begin ap_sig_188 <= ((exitcond1_reg_1305 = ap_const_lv1_0) and (inStream_TVALID = ap_const_logic_0)); end process; ap_sig_198_assign_proc : process(ap_CS_fsm) begin ap_sig_198 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5)); end process; ap_sig_208_assign_proc : process(ap_CS_fsm) begin ap_sig_208 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8)); end process; ap_sig_219_assign_proc : process(ap_CS_fsm) begin ap_sig_219 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; ap_sig_237_assign_proc : process(ap_CS_fsm) begin ap_sig_237 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9)); end process; ap_sig_249_assign_proc : process(ap_CS_fsm) begin ap_sig_249 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4)); end process; ap_sig_260_assign_proc : process(ap_CS_fsm) begin ap_sig_260 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7)); end process; ap_sig_270_assign_proc : process(ap_CS_fsm) begin ap_sig_270 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; ap_sig_28_assign_proc : process(ap_CS_fsm) begin ap_sig_28 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; ap_sig_65_assign_proc : process(ap_CS_fsm) begin ap_sig_65 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; ap_sig_82_assign_proc : process(ap_CS_fsm) begin ap_sig_82 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6)); end process; ap_sig_95_assign_proc : process(ap_CS_fsm) begin ap_sig_95 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10)); end process; ap_sig_cseq_ST_pp0_stg0_fsm_1_assign_proc : process(ap_sig_270) begin if (ap_sig_270) then ap_sig_cseq_ST_pp0_stg0_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg0_fsm_1 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg1_fsm_2_assign_proc : process(ap_sig_65) begin if (ap_sig_65) then ap_sig_cseq_ST_pp0_stg1_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg1_fsm_2 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg2_fsm_3_assign_proc : process(ap_sig_219) begin if (ap_sig_219) then ap_sig_cseq_ST_pp0_stg2_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg2_fsm_3 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg3_fsm_4_assign_proc : process(ap_sig_249) begin if (ap_sig_249) then ap_sig_cseq_ST_pp0_stg3_fsm_4 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg3_fsm_4 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg4_fsm_5_assign_proc : process(ap_sig_198) begin if (ap_sig_198) then ap_sig_cseq_ST_pp0_stg4_fsm_5 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg4_fsm_5 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg5_fsm_6_assign_proc : process(ap_sig_82) begin if (ap_sig_82) then ap_sig_cseq_ST_pp0_stg5_fsm_6 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg5_fsm_6 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg6_fsm_7_assign_proc : process(ap_sig_260) begin if (ap_sig_260) then ap_sig_cseq_ST_pp0_stg6_fsm_7 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg6_fsm_7 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg7_fsm_8_assign_proc : process(ap_sig_208) begin if (ap_sig_208) then ap_sig_cseq_ST_pp0_stg7_fsm_8 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg7_fsm_8 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_pp0_stg8_fsm_9_assign_proc : process(ap_sig_237) begin if (ap_sig_237) then ap_sig_cseq_ST_pp0_stg8_fsm_9 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg8_fsm_9 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_st17_fsm_10_assign_proc : process(ap_sig_95) begin if (ap_sig_95) then ap_sig_cseq_ST_st17_fsm_10 <= ap_const_logic_1; else ap_sig_cseq_ST_st17_fsm_10 <= ap_const_logic_0; end if; end process; ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_28) begin if (ap_sig_28) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; ap_sig_ioackin_outStream_TREADY_assign_proc : process(outStream_TREADY, ap_reg_ioackin_outStream_TREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)) then ap_sig_ioackin_outStream_TREADY <= outStream_TREADY; else ap_sig_ioackin_outStream_TREADY <= ap_const_logic_1; end if; end process; col_assign_1_0_2_fu_703_p2 <= std_logic_vector(unsigned(ap_const_lv32_2) + unsigned(pixConvolved_phi_fu_497_p4)); col_assign_phi_fu_475_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, col_assign_reg_471, ap_sig_cseq_ST_pp0_stg0_fsm_1, idxCol_1_reg_1337) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then col_assign_phi_fu_475_p4 <= idxCol_1_reg_1337; else col_assign_phi_fu_475_p4 <= col_assign_reg_471; end if; end process; countWait_2_fu_1230_p2 <= std_logic_vector(unsigned(countWait_1_reg_516) + unsigned(ap_const_lv10_1)); countWait_phi_fu_509_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, countWait_reg_505, ap_sig_cseq_ST_pp0_stg0_fsm_1, phitmp_reg_1351) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then countWait_phi_fu_509_p4 <= phitmp_reg_1351; else countWait_phi_fu_509_p4 <= countWait_reg_505; end if; end process; exitcond1_fu_562_p2 <= "1" when (countWait_phi_fu_509_p4 = ap_const_lv19_40001) else "0"; exitcond_fu_1224_p2 <= "1" when (countWait_1_reg_516 = ap_const_lv10_201) else "0"; icmp4_fu_600_p2 <= "1" when (signed(tmp_4_fu_590_p4) > signed(ap_const_lv31_0)) else "0"; icmp_fu_584_p2 <= "1" when (signed(tmp_3_fu_574_p4) > signed(ap_const_lv31_0)) else "0"; idxCol_1_fu_630_p3 <= idxCol_fu_618_p2 when (tmp_11_fu_612_p2(0) = '1') else ap_const_lv32_0; idxCol_fu_618_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(col_assign_phi_fu_475_p4)); idxRow_1_fu_638_p3 <= idxRow_phi_fu_486_p4 when (tmp_11_fu_612_p2(0) = '1') else idxRow_2_fu_624_p2; idxRow_2_fu_624_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(idxRow_phi_fu_486_p4)); idxRow_phi_fu_486_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, idxRow_reg_482, ap_sig_cseq_ST_pp0_stg0_fsm_1, idxRow_1_reg_1342) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then idxRow_phi_fu_486_p4 <= idxRow_1_reg_1342; else idxRow_phi_fu_486_p4 <= idxRow_reg_482; end if; end process; inStream_TDATA_blk_n_assign_proc : process(inStream_TVALID, ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0))) then inStream_TDATA_blk_n <= inStream_TVALID; else inStream_TDATA_blk_n <= ap_const_logic_1; end if; end process; inStream_TREADY_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then inStream_TREADY <= ap_const_logic_1; else inStream_TREADY <= ap_const_logic_0; end if; end process; kernel_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_sig_cseq_ST_pp0_stg4_fsm_5, ap_sig_cseq_ST_pp0_stg7_fsm_8, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg8_fsm_9, ap_sig_cseq_ST_pp0_stg3_fsm_4, ap_sig_cseq_ST_pp0_stg6_fsm_7, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)) then kernel_address0 <= ap_const_lv64_8(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)) then kernel_address0 <= ap_const_lv64_7(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) then kernel_address0 <= ap_const_lv64_6(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6)) then kernel_address0 <= ap_const_lv64_5(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) then kernel_address0 <= ap_const_lv64_4(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then kernel_address0 <= ap_const_lv64_3(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then kernel_address0 <= ap_const_lv64_2(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then kernel_address0 <= ap_const_lv64_1(4 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then kernel_address0 <= ap_const_lv64_0(4 - 1 downto 0); else kernel_address0 <= "XXXX"; end if; else kernel_address0 <= "XXXX"; end if; end process; kernel_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_188, ap_sig_cseq_ST_pp0_stg4_fsm_5, ap_sig_cseq_ST_pp0_stg7_fsm_8, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_ioackin_outStream_TREADY, ap_sig_cseq_ST_pp0_stg8_fsm_9, ap_sig_cseq_ST_pp0_stg3_fsm_4, ap_sig_cseq_ST_pp0_stg6_fsm_7, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then kernel_ce0 <= ap_const_logic_1; else kernel_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_0_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, tmp_s_reg_1309, tmp_7_fu_683_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then lineBuff_val_0_address0 <= tmp_s_reg_1309(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_0_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0); else lineBuff_val_0_address0 <= "XXXXXXXXX"; end if; else lineBuff_val_0_address0 <= "XXXXXXXXX"; end if; end process; lineBuff_val_0_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then lineBuff_val_0_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_0_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0); else lineBuff_val_0_address1 <= "XXXXXXXXX"; end if; else lineBuff_val_0_address1 <= "XXXXXXXXX"; end if; end process; lineBuff_val_0_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)))) then lineBuff_val_0_ce0 <= ap_const_logic_1; else lineBuff_val_0_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_0_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then lineBuff_val_0_ce1 <= ap_const_logic_1; else lineBuff_val_0_ce1 <= ap_const_logic_0; end if; end process; lineBuff_val_0_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then lineBuff_val_0_we0 <= ap_const_logic_1; else lineBuff_val_0_we0 <= ap_const_logic_0; end if; end process; lineBuff_val_1_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1, tmp_s_fu_568_p1, lineBuff_val_1_addr_reg_1314, tmp_7_fu_683_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then lineBuff_val_1_address0 <= lineBuff_val_1_addr_reg_1314; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_1_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then lineBuff_val_1_address0 <= tmp_s_fu_568_p1(9 - 1 downto 0); else lineBuff_val_1_address0 <= "XXXXXXXXX"; end if; else lineBuff_val_1_address0 <= "XXXXXXXXX"; end if; end process; lineBuff_val_1_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then lineBuff_val_1_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_1_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0); else lineBuff_val_1_address1 <= "XXXXXXXXX"; end if; else lineBuff_val_1_address1 <= "XXXXXXXXX"; end if; end process; lineBuff_val_1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then lineBuff_val_1_ce0 <= ap_const_logic_1; else lineBuff_val_1_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_1_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then lineBuff_val_1_ce1 <= ap_const_logic_1; else lineBuff_val_1_ce1 <= ap_const_logic_0; end if; end process; lineBuff_val_1_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then lineBuff_val_1_we0 <= ap_const_logic_1; else lineBuff_val_1_we0 <= ap_const_logic_0; end if; end process; lineBuff_val_2_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1, tmp_s_fu_568_p1, lineBuff_val_2_addr_reg_1319, tmp_7_fu_683_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then lineBuff_val_2_address0 <= lineBuff_val_2_addr_reg_1319; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_2_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then lineBuff_val_2_address0 <= tmp_s_fu_568_p1(9 - 1 downto 0); else lineBuff_val_2_address0 <= "XXXXXXXXX"; end if; else lineBuff_val_2_address0 <= "XXXXXXXXX"; end if; end process; lineBuff_val_2_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1) begin if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then lineBuff_val_2_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then lineBuff_val_2_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0); else lineBuff_val_2_address1 <= "XXXXXXXXX"; end if; else lineBuff_val_2_address1 <= "XXXXXXXXX"; end if; end process; lineBuff_val_2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then lineBuff_val_2_ce0 <= ap_const_logic_1; else lineBuff_val_2_ce0 <= ap_const_logic_0; end if; end process; lineBuff_val_2_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then lineBuff_val_2_ce1 <= ap_const_logic_1; else lineBuff_val_2_ce1 <= ap_const_logic_0; end if; end process; lineBuff_val_2_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then lineBuff_val_2_we0 <= ap_const_logic_1; else lineBuff_val_2_we0 <= ap_const_logic_0; end if; end process; or_cond_fu_606_p2 <= (icmp_fu_584_p2 and icmp4_fu_600_p2); outStream_TDATA_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_data_V_fu_1217_p3) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TDATA <= ap_const_lv8_0; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TDATA <= tmp_data_V_fu_1217_p3; else outStream_TDATA <= "XXXXXXXX"; end if; end process; outStream_TDATA_blk_n_assign_proc : process(outStream_TREADY, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2)))) then outStream_TDATA_blk_n <= outStream_TREADY; else outStream_TDATA_blk_n <= ap_const_logic_1; end if; end process; outStream_TDEST_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_dest_V_reg_458, ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TDEST <= tmp_dest_V_reg_458; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TDEST <= ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1; else outStream_TDEST <= "XXXXXX"; end if; end process; outStream_TID_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_id_V_reg_406, ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TID <= tmp_id_V_reg_406; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TID <= ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1; else outStream_TID <= "XXXXX"; end if; end process; outStream_TKEEP_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_keep_V_reg_445, ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TKEEP <= tmp_keep_V_reg_445; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TKEEP <= ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1; else outStream_TKEEP <= "X"; end if; end process; outStream_TLAST_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, countWait_1_reg_516) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TLAST <= countWait_1_reg_516(9 downto 9); elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TLAST <= ap_const_lv1_0; else outStream_TLAST <= "X"; end if; end process; outStream_TSTRB_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_strb_V_reg_432, ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TSTRB <= tmp_strb_V_reg_432; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TSTRB <= ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1; else outStream_TSTRB <= "X"; end if; end process; outStream_TUSER_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_user_V_reg_419, ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then outStream_TUSER <= tmp_user_V_reg_419; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then outStream_TUSER <= ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1; else outStream_TUSER <= "XX"; end if; end process; outStream_TVALID_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_reg_ioackin_outStream_TREADY) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)))) then outStream_TVALID <= ap_const_logic_1; else outStream_TVALID <= ap_const_logic_0; end if; end process; p_neg_fu_1157_p2 <= std_logic_vector(unsigned(ap_const_lv17_0) - unsigned(tmp_18_tr_fu_1154_p1)); p_s_fu_1209_p3 <= ap_const_lv8_0 when (tmp_13_fu_1201_p3(0) = '1') else tmp_10_fu_1197_p1; phitmp_fu_652_p2 <= std_logic_vector(unsigned(countWait_phi_fu_509_p4) + unsigned(ap_const_lv19_1)); pixConvolved_1_fu_744_p3 <= pixConvolved_3_fu_690_p2 when (sel_tmp9_fu_740_p2(0) = '1') else sel_tmp7_fu_732_p3; pixConvolved_2_fu_752_p3 <= pixConvolved_1_fu_744_p3 when (tmp_11_reg_1332(0) = '1') else ap_const_lv32_0; pixConvolved_3_fu_690_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(pixConvolved_phi_fu_497_p4)); pixConvolved_phi_fu_497_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, pixConvolved_reg_493, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1, pixConvolved_2_reg_1436) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then pixConvolved_phi_fu_497_p4 <= pixConvolved_2_reg_1436; else pixConvolved_phi_fu_497_p4 <= pixConvolved_reg_493; end if; end process; sel_tmp10_fu_1147_p3 <= valInWindow_0_minVal_1_2_2_i_fu_1124_p3 when (ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1(0) = '1') else sel_tmp_fu_1140_p3; sel_tmp1_fu_709_p3 <= pixConvolved_3_fu_690_p2 when (or_cond_reg_1324(0) = '1') else pixConvolved_phi_fu_497_p4; sel_tmp2_fu_544_p2 <= "1" when (operation = ap_const_lv32_2) else "0"; sel_tmp3_fu_716_p2 <= (or_cond_reg_1324 and sel_tmp2_reg_1290); sel_tmp4_fu_720_p3 <= pixConvolved_3_fu_690_p2 when (sel_tmp3_fu_716_p2(0) = '1') else sel_tmp1_fu_709_p3; sel_tmp5_fu_550_p2 <= "1" when (operation = ap_const_lv32_1) else "0"; sel_tmp6_fu_728_p2 <= (or_cond_reg_1324 and sel_tmp5_reg_1295); sel_tmp7_fu_732_p3 <= pixConvolved_3_fu_690_p2 when (sel_tmp6_fu_728_p2(0) = '1') else sel_tmp4_fu_720_p3; sel_tmp8_fu_556_p2 <= "1" when (operation = ap_const_lv32_0) else "0"; sel_tmp9_fu_740_p2 <= (or_cond_reg_1324 and sel_tmp8_reg_1300); sel_tmp_fu_1140_p3 <= valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 when (ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1(0) = '1') else ap_const_lv8_0; tmp1_fu_1008_p2 <= std_logic_vector(unsigned(window_val_2_1_fu_1002_p2) + unsigned(window_val_2_0_reg_1605)); tmp2_fu_1050_p2 <= std_logic_vector(unsigned(window_val_1_1_reg_1555) + unsigned(window_val_1_2_reg_1580)); tmp3_fu_1054_p2 <= std_logic_vector(unsigned(tmp1_reg_1630) + unsigned(tmp2_fu_1050_p2)); tmp4_fu_796_p2 <= std_logic_vector(unsigned(window_val_0_0_reg_1481) + unsigned(window_val_0_1_fu_790_p2)); tmp5_fu_1083_p2 <= std_logic_vector(unsigned(window_val_2_2_reg_1655) + unsigned(window_val_0_2_reg_1517)); tmp6_fu_1087_p2 <= std_logic_vector(unsigned(window_val_1_0_reg_1530) + unsigned(tmp5_fu_1083_p2)); tmp7_fu_1092_p2 <= std_logic_vector(unsigned(tmp4_reg_1504) + unsigned(tmp6_fu_1087_p2)); tmp_10_cast_fu_1186_p1 <= std_logic_vector(resize(unsigned(tmp_1_fu_1177_p1),15)); tmp_10_fu_1197_p1 <= valOutput_1_fu_1190_p3(8 - 1 downto 0); tmp_11_0_1_i_fu_862_p2 <= "1" when (unsigned(tmp_15_reg_1509) > unsigned(tmp_14_reg_1496)) else "0"; tmp_11_0_2_i_fu_872_p2 <= "1" when (unsigned(tmp_16_reg_1522) > unsigned(valInWindow_0_maxVal_1_0_1_i_fu_866_p3)) else "0"; tmp_11_1_1_i_fu_948_p2 <= "1" when (unsigned(tmp_18_reg_1566) > unsigned(valInWindow_0_maxVal_1_1_i_reg_1574)) else "0"; tmp_11_1_2_i_fu_985_p2 <= "1" when (unsigned(tmp_19_reg_1591) > unsigned(valInWindow_0_maxVal_1_1_1_i_reg_1599)) else "0"; tmp_11_1_i_fu_911_p2 <= "1" when (unsigned(tmp_17_reg_1541) > unsigned(valInWindow_0_maxVal_1_0_2_i_reg_1549)) else "0"; tmp_11_2_1_i_fu_1073_p2 <= "1" when (unsigned(tmp_21_reg_1641) > unsigned(valInWindow_0_maxVal_1_2_i_reg_1649)) else "0"; tmp_11_2_2_i_fu_1130_p2 <= "1" when (unsigned(tmp_22_reg_1671) > unsigned(valInWindow_0_maxVal_1_2_1_i_reg_1679)) else "0"; tmp_11_2_i_fu_1027_p2 <= "1" when (unsigned(tmp_20_reg_1616) > unsigned(valInWindow_0_maxVal_1_1_2_i_reg_1624)) else "0"; tmp_11_fu_612_p2 <= "1" when (signed(col_assign_phi_fu_475_p4) < signed(ap_const_lv32_1FF)) else "0"; tmp_12_fu_646_p2 <= "1" when (unsigned(countWait_phi_fu_509_p4) > unsigned(ap_const_lv19_201)) else "0"; tmp_13_fu_1201_p3 <= valOutput_1_fu_1190_p3(14 downto 14); tmp_14_fu_779_p1 <= window_val_0_0_fu_773_p2(8 - 1 downto 0); tmp_15_fu_801_p1 <= window_val_0_1_fu_790_p2(8 - 1 downto 0); tmp_16_fu_819_p1 <= window_val_0_2_fu_813_p2(8 - 1 downto 0); tmp_17_fu_858_p1 <= window_val_1_0_fu_830_p2(8 - 1 downto 0); tmp_18_fu_907_p1 <= window_val_1_1_fu_891_p2(8 - 1 downto 0); tmp_18_tr_fu_1154_p1 <= std_logic_vector(resize(signed(valOutput_reg_1685),17)); tmp_19_fu_944_p1 <= window_val_1_2_fu_928_p2(8 - 1 downto 0); tmp_1_fu_1177_p1 <= std_logic_vector(resize(signed(tmp_9_reg_1695),14)); tmp_20_fu_981_p1 <= window_val_2_0_fu_965_p2(8 - 1 downto 0); tmp_21_fu_1023_p1 <= window_val_2_1_fu_1002_p2(8 - 1 downto 0); tmp_22_fu_1069_p1 <= window_val_2_2_fu_1044_p2(8 - 1 downto 0); tmp_25_0_1_fu_696_p1 <= std_logic_vector(resize(unsigned(pixConvolved_3_fu_690_p2),64)); tmp_25_0_2_fu_759_p1 <= std_logic_vector(resize(unsigned(col_assign_1_0_2_reg_1396),64)); tmp_2_fu_1180_p2 <= std_logic_vector(unsigned(ap_const_lv15_0) - unsigned(tmp_7_cast_fu_1173_p1)); tmp_3_fu_574_p4 <= idxRow_phi_fu_486_p4(31 downto 1); tmp_4_fu_590_p4 <= col_assign_phi_fu_475_p4(31 downto 1); tmp_5_0_1_i_fu_836_p2 <= "1" when (unsigned(tmp_15_reg_1509) < unsigned(tmp_14_reg_1496)) else "0"; tmp_5_0_2_i_fu_846_p2 <= "1" when (unsigned(tmp_16_reg_1522) < unsigned(valInWindow_0_minVal_1_0_1_i_fu_840_p3)) else "0"; tmp_5_1_1_i_fu_934_p2 <= "1" when (unsigned(tmp_18_reg_1566) < unsigned(valInWindow_0_minVal_1_1_i_reg_1560)) else "0"; tmp_5_1_2_i_fu_971_p2 <= "1" when (unsigned(tmp_19_reg_1591) < unsigned(valInWindow_0_minVal_1_1_1_i_reg_1585)) else "0"; tmp_5_1_i_fu_897_p2 <= "1" when (unsigned(tmp_17_reg_1541) < unsigned(valInWindow_0_minVal_1_0_2_i_reg_1535)) else "0"; tmp_5_2_1_i_fu_1059_p2 <= "1" when (unsigned(tmp_21_reg_1641) < unsigned(valInWindow_0_minVal_1_2_i_reg_1635)) else "0"; tmp_5_2_2_i_fu_1120_p2 <= "1" when (unsigned(tmp_22_reg_1671) < unsigned(valInWindow_0_minVal_1_2_1_i_reg_1665)) else "0"; tmp_5_2_i_fu_1013_p2 <= "1" when (unsigned(tmp_20_reg_1616) < unsigned(valInWindow_0_minVal_1_1_2_i_reg_1610)) else "0"; tmp_7_cast_fu_1173_p1 <= std_logic_vector(resize(unsigned(tmp_8_fu_1163_p4),15)); tmp_7_fu_683_p1 <= std_logic_vector(resize(unsigned(pixConvolved_phi_fu_497_p4),64)); tmp_8_fu_1163_p4 <= p_neg_fu_1157_p2(16 downto 3); tmp_data_V_fu_1217_p3 <= p_s_fu_1209_p3 when (ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1(0) = '1') else sel_tmp10_reg_1700; tmp_s_fu_568_p1 <= std_logic_vector(resize(unsigned(col_assign_phi_fu_475_p4),64)); valInWindow_0_maxVal_1_0_1_i_fu_866_p3 <= tmp_15_reg_1509 when (tmp_11_0_1_i_fu_862_p2(0) = '1') else tmp_14_reg_1496; valInWindow_0_maxVal_1_0_2_i_fu_877_p3 <= tmp_16_reg_1522 when (tmp_11_0_2_i_fu_872_p2(0) = '1') else valInWindow_0_maxVal_1_0_1_i_fu_866_p3; valInWindow_0_maxVal_1_1_1_i_fu_952_p3 <= tmp_18_reg_1566 when (tmp_11_1_1_i_fu_948_p2(0) = '1') else valInWindow_0_maxVal_1_1_i_reg_1574; valInWindow_0_maxVal_1_1_2_i_fu_989_p3 <= tmp_19_reg_1591 when (tmp_11_1_2_i_fu_985_p2(0) = '1') else valInWindow_0_maxVal_1_1_1_i_reg_1599; valInWindow_0_maxVal_1_1_i_fu_915_p3 <= tmp_17_reg_1541 when (tmp_11_1_i_fu_911_p2(0) = '1') else valInWindow_0_maxVal_1_0_2_i_reg_1549; valInWindow_0_maxVal_1_2_1_i_fu_1077_p3 <= tmp_21_reg_1641 when (tmp_11_2_1_i_fu_1073_p2(0) = '1') else valInWindow_0_maxVal_1_2_i_reg_1649; valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 <= tmp_22_reg_1671 when (tmp_11_2_2_i_fu_1130_p2(0) = '1') else valInWindow_0_maxVal_1_2_1_i_reg_1679; valInWindow_0_maxVal_1_2_i_fu_1031_p3 <= tmp_20_reg_1616 when (tmp_11_2_i_fu_1027_p2(0) = '1') else valInWindow_0_maxVal_1_1_2_i_reg_1624; valInWindow_0_minVal_1_0_1_i_fu_840_p3 <= tmp_15_reg_1509 when (tmp_5_0_1_i_fu_836_p2(0) = '1') else tmp_14_reg_1496; valInWindow_0_minVal_1_0_2_i_fu_851_p3 <= tmp_16_reg_1522 when (tmp_5_0_2_i_fu_846_p2(0) = '1') else valInWindow_0_minVal_1_0_1_i_fu_840_p3; valInWindow_0_minVal_1_1_1_i_fu_938_p3 <= tmp_18_reg_1566 when (tmp_5_1_1_i_fu_934_p2(0) = '1') else valInWindow_0_minVal_1_1_i_reg_1560; valInWindow_0_minVal_1_1_2_i_fu_975_p3 <= tmp_19_reg_1591 when (tmp_5_1_2_i_fu_971_p2(0) = '1') else valInWindow_0_minVal_1_1_1_i_reg_1585; valInWindow_0_minVal_1_1_i_fu_901_p3 <= tmp_17_reg_1541 when (tmp_5_1_i_fu_897_p2(0) = '1') else valInWindow_0_minVal_1_0_2_i_reg_1535; valInWindow_0_minVal_1_2_1_i_fu_1063_p3 <= tmp_21_reg_1641 when (tmp_5_2_1_i_fu_1059_p2(0) = '1') else valInWindow_0_minVal_1_2_i_reg_1635; valInWindow_0_minVal_1_2_2_i_fu_1124_p3 <= tmp_22_reg_1671 when (tmp_5_2_2_i_fu_1120_p2(0) = '1') else valInWindow_0_minVal_1_2_1_i_reg_1665; valInWindow_0_minVal_1_2_i_fu_1017_p3 <= tmp_20_reg_1616 when (tmp_5_2_i_fu_1013_p2(0) = '1') else valInWindow_0_minVal_1_1_2_i_reg_1610; valOutput_1_fu_1190_p3 <= tmp_2_fu_1180_p2 when (tmp_6_reg_1690(0) = '1') else tmp_10_cast_fu_1186_p1; valOutput_fu_1097_p2 <= std_logic_vector(unsigned(tmp3_reg_1660) + unsigned(tmp7_fu_1092_p2)); window_val_0_0_fu_773_p0 <= reg_527; window_val_0_0_fu_773_p1 <= window_val_0_0_fu_773_p10(8 - 1 downto 0); window_val_0_0_fu_773_p10 <= std_logic_vector(resize(unsigned(reg_535),16)); window_val_0_0_fu_773_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_0_fu_773_p0) * signed('0' &window_val_0_0_fu_773_p1))), 16)); window_val_0_1_fu_790_p0 <= reg_531; window_val_0_1_fu_790_p1 <= window_val_0_1_fu_790_p10(8 - 1 downto 0); window_val_0_1_fu_790_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_0_load_1_reg_1441),16)); window_val_0_1_fu_790_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_1_fu_790_p0) * signed('0' &window_val_0_1_fu_790_p1))), 16)); window_val_0_2_fu_813_p0 <= reg_540; window_val_0_2_fu_813_p1 <= window_val_0_2_fu_813_p10(8 - 1 downto 0); window_val_0_2_fu_813_p10 <= std_logic_vector(resize(unsigned(reg_535),16)); window_val_0_2_fu_813_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_2_fu_813_p0) * signed('0' &window_val_0_2_fu_813_p1))), 16)); window_val_1_0_fu_830_p0 <= reg_527; window_val_1_0_fu_830_p1 <= window_val_1_0_fu_830_p10(8 - 1 downto 0); window_val_1_0_fu_830_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_1_reg_1451),16)); window_val_1_0_fu_830_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_0_fu_830_p0) * signed('0' &window_val_1_0_fu_830_p1))), 16)); window_val_1_1_fu_891_p0 <= reg_531; window_val_1_1_fu_891_p1 <= window_val_1_1_fu_891_p10(8 - 1 downto 0); window_val_1_1_fu_891_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_2_reg_1456),16)); window_val_1_1_fu_891_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_1_fu_891_p0) * signed('0' &window_val_1_1_fu_891_p1))), 16)); window_val_1_2_fu_928_p0 <= reg_540; window_val_1_2_fu_928_p1 <= window_val_1_2_fu_928_p10(8 - 1 downto 0); window_val_1_2_fu_928_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_3_reg_1486),16)); window_val_1_2_fu_928_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_2_fu_928_p0) * signed('0' &window_val_1_2_fu_928_p1))), 16)); window_val_2_0_fu_965_p0 <= reg_527; window_val_2_0_fu_965_p1 <= window_val_2_0_fu_965_p10(8 - 1 downto 0); window_val_2_0_fu_965_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_1_reg_1466),16)); window_val_2_0_fu_965_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_0_fu_965_p0) * signed('0' &window_val_2_0_fu_965_p1))), 16)); window_val_2_1_fu_1002_p0 <= reg_531; window_val_2_1_fu_1002_p1 <= window_val_2_1_fu_1002_p10(8 - 1 downto 0); window_val_2_1_fu_1002_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_2_reg_1471),16)); window_val_2_1_fu_1002_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_1_fu_1002_p0) * signed('0' &window_val_2_1_fu_1002_p1))), 16)); window_val_2_2_fu_1044_p0 <= reg_540; window_val_2_2_fu_1044_p1 <= window_val_2_2_fu_1044_p10(8 - 1 downto 0); window_val_2_2_fu_1044_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_3_reg_1491),16)); window_val_2_2_fu_1044_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_2_fu_1044_p0) * signed('0' &window_val_2_2_fu_1044_p1))), 16)); end behav;
-- *************************************************************************** -- *************************************************************************** -- Copyright 2013(c) Analog Devices, Inc. -- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com> -- -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without modification, -- are permitted provided that the following conditions are met: -- - Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- - Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in -- the documentation and/or other materials provided with the -- distribution. -- - Neither the name of Analog Devices, Inc. nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without specific prior written permission. -- - The use of this software may or may not infringe the patent rights -- of one or more patent holders. This license does not release you -- from the requirement that you obtain separate licenses from these -- patent holders to use this software. -- - Use of the software either in source or binary form, must be run -- on or directly connected to an Analog Devices Inc. component. -- -- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. -- -- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- *************************************************************************** -- *************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity axi_ctrlif is generic ( C_NUM_REG : integer := 32; C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_FAMILY : string := "virtex6" ); port ( -- AXI bus interface S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic; rd_addr : out integer range 0 to C_NUM_REG - 1; rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); rd_ack : out std_logic; rd_stb : in std_logic; wr_addr : out integer range 0 to C_NUM_REG - 1; wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); wr_ack : in std_logic; wr_stb : out std_logic ); end entity axi_ctrlif; architecture Behavioral of axi_ctrlif is type state_type is (IDLE, RESP, ACK); signal rd_state : state_type; signal wr_state : state_type; begin process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then rd_state <= IDLE; else case rd_state is when IDLE => if S_AXI_ARVALID = '1' then rd_state <= RESP; rd_addr <= to_integer(unsigned(S_AXI_ARADDR(31 downto 2))); end if; when RESP => if rd_stb = '1' and S_AXI_RREADY = '1' then rd_state <= IDLE; end if; when others => null; end case; end if; end if; end process; S_AXI_ARREADY <= '1' when rd_state = IDLE else '0'; S_AXI_RVALID <= '1' when rd_state = RESP and rd_stb = '1' else '0'; S_AXI_RRESP <= "00"; rd_ack <= '1' when rd_state = RESP and S_AXI_RREADY = '1' else '0'; S_AXI_RDATA <= rd_data; process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then wr_state <= IDLE; else case wr_state is when IDLE => if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_ack = '1' then wr_state <= ACK; end if; when ACK => wr_state <= RESP; when RESP => if S_AXI_BREADY = '1' then wr_state <= IDLE; end if; end case; end if; end if; end process; wr_stb <= '1' when S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_state = IDLE else '0'; wr_data <= S_AXI_WDATA; wr_addr <= to_integer(unsigned(S_AXI_AWADDR(31 downto 2))); S_AXI_AWREADY <= '1' when wr_state = ACK else '0'; S_AXI_WREADY <= '1' when wr_state = ACK else '0'; S_AXI_BRESP <= "00"; S_AXI_BVALID <= '1' when wr_state = RESP else '0'; end;
-- *************************************************************************** -- *************************************************************************** -- Copyright 2013(c) Analog Devices, Inc. -- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com> -- -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without modification, -- are permitted provided that the following conditions are met: -- - Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- - Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in -- the documentation and/or other materials provided with the -- distribution. -- - Neither the name of Analog Devices, Inc. nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without specific prior written permission. -- - The use of this software may or may not infringe the patent rights -- of one or more patent holders. This license does not release you -- from the requirement that you obtain separate licenses from these -- patent holders to use this software. -- - Use of the software either in source or binary form, must be run -- on or directly connected to an Analog Devices Inc. component. -- -- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. -- -- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- *************************************************************************** -- *************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity axi_ctrlif is generic ( C_NUM_REG : integer := 32; C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_FAMILY : string := "virtex6" ); port ( -- AXI bus interface S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic; rd_addr : out integer range 0 to C_NUM_REG - 1; rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); rd_ack : out std_logic; rd_stb : in std_logic; wr_addr : out integer range 0 to C_NUM_REG - 1; wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); wr_ack : in std_logic; wr_stb : out std_logic ); end entity axi_ctrlif; architecture Behavioral of axi_ctrlif is type state_type is (IDLE, RESP, ACK); signal rd_state : state_type; signal wr_state : state_type; begin process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then rd_state <= IDLE; else case rd_state is when IDLE => if S_AXI_ARVALID = '1' then rd_state <= RESP; rd_addr <= to_integer(unsigned(S_AXI_ARADDR(31 downto 2))); end if; when RESP => if rd_stb = '1' and S_AXI_RREADY = '1' then rd_state <= IDLE; end if; when others => null; end case; end if; end if; end process; S_AXI_ARREADY <= '1' when rd_state = IDLE else '0'; S_AXI_RVALID <= '1' when rd_state = RESP and rd_stb = '1' else '0'; S_AXI_RRESP <= "00"; rd_ack <= '1' when rd_state = RESP and S_AXI_RREADY = '1' else '0'; S_AXI_RDATA <= rd_data; process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then wr_state <= IDLE; else case wr_state is when IDLE => if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_ack = '1' then wr_state <= ACK; end if; when ACK => wr_state <= RESP; when RESP => if S_AXI_BREADY = '1' then wr_state <= IDLE; end if; end case; end if; end if; end process; wr_stb <= '1' when S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_state = IDLE else '0'; wr_data <= S_AXI_WDATA; wr_addr <= to_integer(unsigned(S_AXI_AWADDR(31 downto 2))); S_AXI_AWREADY <= '1' when wr_state = ACK else '0'; S_AXI_WREADY <= '1' when wr_state = ACK else '0'; S_AXI_BRESP <= "00"; S_AXI_BVALID <= '1' when wr_state = RESP else '0'; end;
-- *************************************************************************** -- *************************************************************************** -- Copyright 2013(c) Analog Devices, Inc. -- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com> -- -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without modification, -- are permitted provided that the following conditions are met: -- - Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- - Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in -- the documentation and/or other materials provided with the -- distribution. -- - Neither the name of Analog Devices, Inc. nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without specific prior written permission. -- - The use of this software may or may not infringe the patent rights -- of one or more patent holders. This license does not release you -- from the requirement that you obtain separate licenses from these -- patent holders to use this software. -- - Use of the software either in source or binary form, must be run -- on or directly connected to an Analog Devices Inc. component. -- -- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. -- -- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- *************************************************************************** -- *************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity axi_ctrlif is generic ( C_NUM_REG : integer := 32; C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_FAMILY : string := "virtex6" ); port ( -- AXI bus interface S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic; rd_addr : out integer range 0 to C_NUM_REG - 1; rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); rd_ack : out std_logic; rd_stb : in std_logic; wr_addr : out integer range 0 to C_NUM_REG - 1; wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); wr_ack : in std_logic; wr_stb : out std_logic ); end entity axi_ctrlif; architecture Behavioral of axi_ctrlif is type state_type is (IDLE, RESP, ACK); signal rd_state : state_type; signal wr_state : state_type; begin process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then rd_state <= IDLE; else case rd_state is when IDLE => if S_AXI_ARVALID = '1' then rd_state <= RESP; rd_addr <= to_integer(unsigned(S_AXI_ARADDR(31 downto 2))); end if; when RESP => if rd_stb = '1' and S_AXI_RREADY = '1' then rd_state <= IDLE; end if; when others => null; end case; end if; end if; end process; S_AXI_ARREADY <= '1' when rd_state = IDLE else '0'; S_AXI_RVALID <= '1' when rd_state = RESP and rd_stb = '1' else '0'; S_AXI_RRESP <= "00"; rd_ack <= '1' when rd_state = RESP and S_AXI_RREADY = '1' else '0'; S_AXI_RDATA <= rd_data; process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then wr_state <= IDLE; else case wr_state is when IDLE => if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_ack = '1' then wr_state <= ACK; end if; when ACK => wr_state <= RESP; when RESP => if S_AXI_BREADY = '1' then wr_state <= IDLE; end if; end case; end if; end if; end process; wr_stb <= '1' when S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_state = IDLE else '0'; wr_data <= S_AXI_WDATA; wr_addr <= to_integer(unsigned(S_AXI_AWADDR(31 downto 2))); S_AXI_AWREADY <= '1' when wr_state = ACK else '0'; S_AXI_WREADY <= '1' when wr_state = ACK else '0'; S_AXI_BRESP <= "00"; S_AXI_BVALID <= '1' when wr_state = RESP else '0'; end;
-- *************************************************************************** -- *************************************************************************** -- Copyright 2013(c) Analog Devices, Inc. -- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com> -- -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without modification, -- are permitted provided that the following conditions are met: -- - Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- - Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in -- the documentation and/or other materials provided with the -- distribution. -- - Neither the name of Analog Devices, Inc. nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without specific prior written permission. -- - The use of this software may or may not infringe the patent rights -- of one or more patent holders. This license does not release you -- from the requirement that you obtain separate licenses from these -- patent holders to use this software. -- - Use of the software either in source or binary form, must be run -- on or directly connected to an Analog Devices Inc. component. -- -- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. -- -- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- *************************************************************************** -- *************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity axi_ctrlif is generic ( C_NUM_REG : integer := 32; C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_FAMILY : string := "virtex6" ); port ( -- AXI bus interface S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic; rd_addr : out integer range 0 to C_NUM_REG - 1; rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); rd_ack : out std_logic; rd_stb : in std_logic; wr_addr : out integer range 0 to C_NUM_REG - 1; wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); wr_ack : in std_logic; wr_stb : out std_logic ); end entity axi_ctrlif; architecture Behavioral of axi_ctrlif is type state_type is (IDLE, RESP, ACK); signal rd_state : state_type; signal wr_state : state_type; begin process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then rd_state <= IDLE; else case rd_state is when IDLE => if S_AXI_ARVALID = '1' then rd_state <= RESP; rd_addr <= to_integer(unsigned(S_AXI_ARADDR(31 downto 2))); end if; when RESP => if rd_stb = '1' and S_AXI_RREADY = '1' then rd_state <= IDLE; end if; when others => null; end case; end if; end if; end process; S_AXI_ARREADY <= '1' when rd_state = IDLE else '0'; S_AXI_RVALID <= '1' when rd_state = RESP and rd_stb = '1' else '0'; S_AXI_RRESP <= "00"; rd_ack <= '1' when rd_state = RESP and S_AXI_RREADY = '1' else '0'; S_AXI_RDATA <= rd_data; process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then wr_state <= IDLE; else case wr_state is when IDLE => if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_ack = '1' then wr_state <= ACK; end if; when ACK => wr_state <= RESP; when RESP => if S_AXI_BREADY = '1' then wr_state <= IDLE; end if; end case; end if; end if; end process; wr_stb <= '1' when S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_state = IDLE else '0'; wr_data <= S_AXI_WDATA; wr_addr <= to_integer(unsigned(S_AXI_AWADDR(31 downto 2))); S_AXI_AWREADY <= '1' when wr_state = ACK else '0'; S_AXI_WREADY <= '1' when wr_state = ACK else '0'; S_AXI_BRESP <= "00"; S_AXI_BVALID <= '1' when wr_state = RESP else '0'; end;
-- *************************************************************************** -- *************************************************************************** -- Copyright 2013(c) Analog Devices, Inc. -- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com> -- -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without modification, -- are permitted provided that the following conditions are met: -- - Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- - Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in -- the documentation and/or other materials provided with the -- distribution. -- - Neither the name of Analog Devices, Inc. nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without specific prior written permission. -- - The use of this software may or may not infringe the patent rights -- of one or more patent holders. This license does not release you -- from the requirement that you obtain separate licenses from these -- patent holders to use this software. -- - Use of the software either in source or binary form, must be run -- on or directly connected to an Analog Devices Inc. component. -- -- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. -- -- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- *************************************************************************** -- *************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity axi_ctrlif is generic ( C_NUM_REG : integer := 32; C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_FAMILY : string := "virtex6" ); port ( -- AXI bus interface S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic; rd_addr : out integer range 0 to C_NUM_REG - 1; rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); rd_ack : out std_logic; rd_stb : in std_logic; wr_addr : out integer range 0 to C_NUM_REG - 1; wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); wr_ack : in std_logic; wr_stb : out std_logic ); end entity axi_ctrlif; architecture Behavioral of axi_ctrlif is type state_type is (IDLE, RESP, ACK); signal rd_state : state_type; signal wr_state : state_type; begin process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then rd_state <= IDLE; else case rd_state is when IDLE => if S_AXI_ARVALID = '1' then rd_state <= RESP; rd_addr <= to_integer(unsigned(S_AXI_ARADDR(31 downto 2))); end if; when RESP => if rd_stb = '1' and S_AXI_RREADY = '1' then rd_state <= IDLE; end if; when others => null; end case; end if; end if; end process; S_AXI_ARREADY <= '1' when rd_state = IDLE else '0'; S_AXI_RVALID <= '1' when rd_state = RESP and rd_stb = '1' else '0'; S_AXI_RRESP <= "00"; rd_ack <= '1' when rd_state = RESP and S_AXI_RREADY = '1' else '0'; S_AXI_RDATA <= rd_data; process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then wr_state <= IDLE; else case wr_state is when IDLE => if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_ack = '1' then wr_state <= ACK; end if; when ACK => wr_state <= RESP; when RESP => if S_AXI_BREADY = '1' then wr_state <= IDLE; end if; end case; end if; end if; end process; wr_stb <= '1' when S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_state = IDLE else '0'; wr_data <= S_AXI_WDATA; wr_addr <= to_integer(unsigned(S_AXI_AWADDR(31 downto 2))); S_AXI_AWREADY <= '1' when wr_state = ACK else '0'; S_AXI_WREADY <= '1' when wr_state = ACK else '0'; S_AXI_BRESP <= "00"; S_AXI_BVALID <= '1' when wr_state = RESP else '0'; end;
-- *************************************************************************** -- *************************************************************************** -- Copyright 2013(c) Analog Devices, Inc. -- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com> -- -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without modification, -- are permitted provided that the following conditions are met: -- - Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- - Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in -- the documentation and/or other materials provided with the -- distribution. -- - Neither the name of Analog Devices, Inc. nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without specific prior written permission. -- - The use of this software may or may not infringe the patent rights -- of one or more patent holders. This license does not release you -- from the requirement that you obtain separate licenses from these -- patent holders to use this software. -- - Use of the software either in source or binary form, must be run -- on or directly connected to an Analog Devices Inc. component. -- -- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. -- -- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- *************************************************************************** -- *************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity axi_ctrlif is generic ( C_NUM_REG : integer := 32; C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_FAMILY : string := "virtex6" ); port ( -- AXI bus interface S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic; rd_addr : out integer range 0 to C_NUM_REG - 1; rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); rd_ack : out std_logic; rd_stb : in std_logic; wr_addr : out integer range 0 to C_NUM_REG - 1; wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); wr_ack : in std_logic; wr_stb : out std_logic ); end entity axi_ctrlif; architecture Behavioral of axi_ctrlif is type state_type is (IDLE, RESP, ACK); signal rd_state : state_type; signal wr_state : state_type; begin process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then rd_state <= IDLE; else case rd_state is when IDLE => if S_AXI_ARVALID = '1' then rd_state <= RESP; rd_addr <= to_integer(unsigned(S_AXI_ARADDR(31 downto 2))); end if; when RESP => if rd_stb = '1' and S_AXI_RREADY = '1' then rd_state <= IDLE; end if; when others => null; end case; end if; end if; end process; S_AXI_ARREADY <= '1' when rd_state = IDLE else '0'; S_AXI_RVALID <= '1' when rd_state = RESP and rd_stb = '1' else '0'; S_AXI_RRESP <= "00"; rd_ack <= '1' when rd_state = RESP and S_AXI_RREADY = '1' else '0'; S_AXI_RDATA <= rd_data; process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then wr_state <= IDLE; else case wr_state is when IDLE => if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_ack = '1' then wr_state <= ACK; end if; when ACK => wr_state <= RESP; when RESP => if S_AXI_BREADY = '1' then wr_state <= IDLE; end if; end case; end if; end if; end process; wr_stb <= '1' when S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_state = IDLE else '0'; wr_data <= S_AXI_WDATA; wr_addr <= to_integer(unsigned(S_AXI_AWADDR(31 downto 2))); S_AXI_AWREADY <= '1' when wr_state = ACK else '0'; S_AXI_WREADY <= '1' when wr_state = ACK else '0'; S_AXI_BRESP <= "00"; S_AXI_BVALID <= '1' when wr_state = RESP else '0'; end;
-- *************************************************************************** -- *************************************************************************** -- Copyright 2013(c) Analog Devices, Inc. -- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com> -- -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without modification, -- are permitted provided that the following conditions are met: -- - Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- - Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in -- the documentation and/or other materials provided with the -- distribution. -- - Neither the name of Analog Devices, Inc. nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without specific prior written permission. -- - The use of this software may or may not infringe the patent rights -- of one or more patent holders. This license does not release you -- from the requirement that you obtain separate licenses from these -- patent holders to use this software. -- - Use of the software either in source or binary form, must be run -- on or directly connected to an Analog Devices Inc. component. -- -- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. -- -- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- *************************************************************************** -- *************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity axi_ctrlif is generic ( C_NUM_REG : integer := 32; C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_FAMILY : string := "virtex6" ); port ( -- AXI bus interface S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic; rd_addr : out integer range 0 to C_NUM_REG - 1; rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); rd_ack : out std_logic; rd_stb : in std_logic; wr_addr : out integer range 0 to C_NUM_REG - 1; wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); wr_ack : in std_logic; wr_stb : out std_logic ); end entity axi_ctrlif; architecture Behavioral of axi_ctrlif is type state_type is (IDLE, RESP, ACK); signal rd_state : state_type; signal wr_state : state_type; begin process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then rd_state <= IDLE; else case rd_state is when IDLE => if S_AXI_ARVALID = '1' then rd_state <= RESP; rd_addr <= to_integer(unsigned(S_AXI_ARADDR(31 downto 2))); end if; when RESP => if rd_stb = '1' and S_AXI_RREADY = '1' then rd_state <= IDLE; end if; when others => null; end case; end if; end if; end process; S_AXI_ARREADY <= '1' when rd_state = IDLE else '0'; S_AXI_RVALID <= '1' when rd_state = RESP and rd_stb = '1' else '0'; S_AXI_RRESP <= "00"; rd_ack <= '1' when rd_state = RESP and S_AXI_RREADY = '1' else '0'; S_AXI_RDATA <= rd_data; process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then wr_state <= IDLE; else case wr_state is when IDLE => if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_ack = '1' then wr_state <= ACK; end if; when ACK => wr_state <= RESP; when RESP => if S_AXI_BREADY = '1' then wr_state <= IDLE; end if; end case; end if; end if; end process; wr_stb <= '1' when S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_state = IDLE else '0'; wr_data <= S_AXI_WDATA; wr_addr <= to_integer(unsigned(S_AXI_AWADDR(31 downto 2))); S_AXI_AWREADY <= '1' when wr_state = ACK else '0'; S_AXI_WREADY <= '1' when wr_state = ACK else '0'; S_AXI_BRESP <= "00"; S_AXI_BVALID <= '1' when wr_state = RESP else '0'; end;
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file cdce72010_init_mem_int.vhd when simulating -- the core, cdce72010_init_mem_int. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY cdce72010_init_mem_int IS PORT ( clka : IN STD_LOGIC; addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END cdce72010_init_mem_int; ARCHITECTURE cdce72010_init_mem_int_a OF cdce72010_init_mem_int IS -- synthesis translate_off COMPONENT wrapped_cdce72010_init_mem_int PORT ( clka : IN STD_LOGIC; addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_cdce72010_init_mem_int USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral) GENERIC MAP ( c_addra_width => 4, c_addrb_width => 4, c_algorithm => 1, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_enable_32bit_address => 0, c_family => "virtex6", c_has_axi_id => 0, c_has_ena => 0, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file_name => "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/sim/cdce72010_init_mem_int.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 3, c_mux_pipeline_stages => 0, c_prim_type => 1, c_read_depth_a => 16, c_read_depth_b => 16, c_read_width_a => 32, c_read_width_b => 32, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 0, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 16, c_write_depth_b => 16, c_write_mode_a => "WRITE_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 32, c_write_width_b => 32, c_xdevicefamily => "virtex6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_cdce72010_init_mem_int PORT MAP ( clka => clka, addra => addra, douta => douta ); -- synthesis translate_on END cdce72010_init_mem_int_a;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:xlslice:1.0 -- IP Revision: 0 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY work; USE work.xlslice; ENTITY RAT_xlslice_0_0 IS PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END RAT_xlslice_0_0; ARCHITECTURE RAT_xlslice_0_0_arch OF RAT_xlslice_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_xlslice_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT xlslice IS GENERIC ( DIN_WIDTH : INTEGER; DIN_FROM : INTEGER; DIN_TO : INTEGER ); PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT xlslice; BEGIN U0 : xlslice GENERIC MAP ( DIN_WIDTH => 18, DIN_FROM => 12, DIN_TO => 3 ) PORT MAP ( Din => Din, Dout => Dout ); END RAT_xlslice_0_0_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:xlslice:1.0 -- IP Revision: 0 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY work; USE work.xlslice; ENTITY RAT_xlslice_0_0 IS PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END RAT_xlslice_0_0; ARCHITECTURE RAT_xlslice_0_0_arch OF RAT_xlslice_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_xlslice_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT xlslice IS GENERIC ( DIN_WIDTH : INTEGER; DIN_FROM : INTEGER; DIN_TO : INTEGER ); PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT xlslice; BEGIN U0 : xlslice GENERIC MAP ( DIN_WIDTH => 18, DIN_FROM => 12, DIN_TO => 3 ) PORT MAP ( Din => Din, Dout => Dout ); END RAT_xlslice_0_0_arch;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.amba.all; use work.iface.all; entity ahbtest is port ( rst : in std_logic; clk : in clk_type; -- peripheral bus -- pbi : in APB_Slv_In_Type; -- peripheral bus in -- pbo : out APB_Slv_Out_Type; -- peripheral bus out -- irq : out std_logic; -- interrupt request -- ahbi1 : in ahb_mst_in_type; -- dma port in -- ahbo1 : out ahb_mst_out_type; -- dma port out -- ahbi2 : in ahb_mst_in_type; -- dma port in -- ahbo2 : out ahb_mst_out_type; -- dma port out ahbi : in ahb_slv_in_type; ahbo : out ahb_slv_out_type ); end; architecture struct of ahbtest is type slavestate is (idle, error, split, retry, ws1); type reg_type is record haddr : std_logic_vector(31 downto 0); -- address bus hsel : std_logic; htrans : std_logic_vector(1 downto 0); -- transfer type hresp : std_logic_vector(1 downto 0); -- response type hmaster : std_logic_vector(3 downto 0); -- master smaster : std_logic_vector(3 downto 0); -- split master hwrite : std_logic; -- read/write hready : std_logic; -- ready splitcnt : natural; ss : slavestate; end record; signal r, rin : reg_type; begin comb : process(ahbi, r) variable v : reg_type; variable prdata : std_logic_vector(31 downto 0); variable vsplit : std_logic_vector(15 downto 0); begin v := r; v.hready := '0'; vsplit := (others => '0'); if r.splitcnt > 0 then v.splitcnt := r.splitcnt -1; if v.splitcnt = 0 then vsplit(conv_integer(unsigned(r.smaster))) := '1'; end if; end if; if (ahbi.hready = '1') then v.hready := '0'; v.haddr := ahbi.haddr; v.hwrite := ahbi.hwrite; v.hsel := ahbi.hsel; v.hwrite := ahbi.hwrite; v.hmaster := ahbi.hmaster; end if; if (ahbi.hsel and ahbi.hready) = '1' then if ((ahbi.htrans = HTRANS_NONSEQ) or (ahbi.htrans = HTRANS_SEQ)) and (r.hresp = HRESP_OKAY) then if (ahbi.haddr(5 downto 4) = "01") and ((ahbi.haddr(3) xor ahbi.haddr(2)) = '1') then v.hresp := HRESP_RETRY; v.ss := retry; elsif (ahbi.haddr(5 downto 4) = "10") and ((ahbi.haddr(3) xor ahbi.haddr(2)) = '1') then v.hresp := HRESP_SPLIT; v.ss := split; elsif (ahbi.haddr(5 downto 4) = "11") and ((ahbi.haddr(3) xor ahbi.haddr(2)) = '1') then v.hresp := HRESP_ERROR; v.ss := error; else v.hresp := HRESP_OKAY; if (ahbi.haddr(3 downto 2) = "00") then v.ss := ws1; else v.hready := '1'; end if; end if; else if (r.hresp = HRESP_SPLIT) and (r.splitcnt > 2) then v.ss := split; v.hresp := HRESP_SPLIT; else v.hresp := HRESP_OKAY; v.ss := idle; v.hready := '1'; end if; end if; end if; case r.ss is when idle => when retry => v.hresp := HRESP_RETRY; v.ss := idle; v.hready := '1'; when split => v.hresp := HRESP_SPLIT; v.ss := idle; v.hready := '1'; v.smaster := r.hmaster; if r.splitcnt = 0 then v.splitcnt := 15; end if; when error => v.hresp := HRESP_ERROR; v.ss := idle; v.hready := '1'; when ws1 => v.hresp := HRESP_OKAY; v.ss := idle; v.hready := '1'; end case; ahbo.hresp <= r.hresp; ahbo.hready <= r.hready; ahbo.hrdata <= r.haddr; ahbo.hsplit <= vsplit; if rst = '0' then v.hready := '1'; v.hsel := '0'; v.hresp := HRESP_OKAY; v.haddr := (others => '0'); end if; rin <= v; end process; -- ahbo1.haddr <= (others => '0') ; -- ahbo1.htrans <= HTRANS_IDLE; -- ahbo1.hbusreq <= '0'; -- ahbo1.hwdata <= (others => '0'); -- ahbo1.hlock <= '0'; -- ahbo1.hwrite <= '0'; -- ahbo1.hsize <= HSIZE_WORD; -- ahbo1.hburst <= HBURST_SINGLE; -- ahbo1.hprot <= (others => '0'); regs : process(clk) begin if rising_edge(clk) then r <= rin; end if; end process; end;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.amba.all; use work.iface.all; entity ahbtest is port ( rst : in std_logic; clk : in clk_type; -- peripheral bus -- pbi : in APB_Slv_In_Type; -- peripheral bus in -- pbo : out APB_Slv_Out_Type; -- peripheral bus out -- irq : out std_logic; -- interrupt request -- ahbi1 : in ahb_mst_in_type; -- dma port in -- ahbo1 : out ahb_mst_out_type; -- dma port out -- ahbi2 : in ahb_mst_in_type; -- dma port in -- ahbo2 : out ahb_mst_out_type; -- dma port out ahbi : in ahb_slv_in_type; ahbo : out ahb_slv_out_type ); end; architecture struct of ahbtest is type slavestate is (idle, error, split, retry, ws1); type reg_type is record haddr : std_logic_vector(31 downto 0); -- address bus hsel : std_logic; htrans : std_logic_vector(1 downto 0); -- transfer type hresp : std_logic_vector(1 downto 0); -- response type hmaster : std_logic_vector(3 downto 0); -- master smaster : std_logic_vector(3 downto 0); -- split master hwrite : std_logic; -- read/write hready : std_logic; -- ready splitcnt : natural; ss : slavestate; end record; signal r, rin : reg_type; begin comb : process(ahbi, r) variable v : reg_type; variable prdata : std_logic_vector(31 downto 0); variable vsplit : std_logic_vector(15 downto 0); begin v := r; v.hready := '0'; vsplit := (others => '0'); if r.splitcnt > 0 then v.splitcnt := r.splitcnt -1; if v.splitcnt = 0 then vsplit(conv_integer(unsigned(r.smaster))) := '1'; end if; end if; if (ahbi.hready = '1') then v.hready := '0'; v.haddr := ahbi.haddr; v.hwrite := ahbi.hwrite; v.hsel := ahbi.hsel; v.hwrite := ahbi.hwrite; v.hmaster := ahbi.hmaster; end if; if (ahbi.hsel and ahbi.hready) = '1' then if ((ahbi.htrans = HTRANS_NONSEQ) or (ahbi.htrans = HTRANS_SEQ)) and (r.hresp = HRESP_OKAY) then if (ahbi.haddr(5 downto 4) = "01") and ((ahbi.haddr(3) xor ahbi.haddr(2)) = '1') then v.hresp := HRESP_RETRY; v.ss := retry; elsif (ahbi.haddr(5 downto 4) = "10") and ((ahbi.haddr(3) xor ahbi.haddr(2)) = '1') then v.hresp := HRESP_SPLIT; v.ss := split; elsif (ahbi.haddr(5 downto 4) = "11") and ((ahbi.haddr(3) xor ahbi.haddr(2)) = '1') then v.hresp := HRESP_ERROR; v.ss := error; else v.hresp := HRESP_OKAY; if (ahbi.haddr(3 downto 2) = "00") then v.ss := ws1; else v.hready := '1'; end if; end if; else if (r.hresp = HRESP_SPLIT) and (r.splitcnt > 2) then v.ss := split; v.hresp := HRESP_SPLIT; else v.hresp := HRESP_OKAY; v.ss := idle; v.hready := '1'; end if; end if; end if; case r.ss is when idle => when retry => v.hresp := HRESP_RETRY; v.ss := idle; v.hready := '1'; when split => v.hresp := HRESP_SPLIT; v.ss := idle; v.hready := '1'; v.smaster := r.hmaster; if r.splitcnt = 0 then v.splitcnt := 15; end if; when error => v.hresp := HRESP_ERROR; v.ss := idle; v.hready := '1'; when ws1 => v.hresp := HRESP_OKAY; v.ss := idle; v.hready := '1'; end case; ahbo.hresp <= r.hresp; ahbo.hready <= r.hready; ahbo.hrdata <= r.haddr; ahbo.hsplit <= vsplit; if rst = '0' then v.hready := '1'; v.hsel := '0'; v.hresp := HRESP_OKAY; v.haddr := (others => '0'); end if; rin <= v; end process; -- ahbo1.haddr <= (others => '0') ; -- ahbo1.htrans <= HTRANS_IDLE; -- ahbo1.hbusreq <= '0'; -- ahbo1.hwdata <= (others => '0'); -- ahbo1.hlock <= '0'; -- ahbo1.hwrite <= '0'; -- ahbo1.hsize <= HSIZE_WORD; -- ahbo1.hburst <= HBURST_SINGLE; -- ahbo1.hprot <= (others => '0'); regs : process(clk) begin if rising_edge(clk) then r <= rin; end if; end process; end;
entity t1 is err; end t1;
entity t1 is err; end t1;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity stack_in_MUX is port(sel : in std_logic_vector(2 downto 0); ctl_immediate : in std_logic_vector(31 downto 0); ALU_result : in std_logic_vector(31 downto 0); IO_ipins_data : in std_logic_vector(31 downto 0); IO_iport_data : in std_logic_vector(31 downto 0); mem_data_out : in std_logic_vector(31 downto 0); output : out std_logic_vector(31 downto 0)); end stack_in_MUX; architecture Behavioral of stack_in_MUX is begin main : process(sel, ctl_immediate, ALU_result, IO_ipins_data, IO_iport_data, mem_data_out) is begin case (sel) is when "000" => output <= ctl_immediate; when "001" => output <= ALU_result; when "010" => output <= IO_ipins_data; when "011" => output <= IO_iport_data; when others => output <= mem_data_out; end case; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity stack_in_MUX is port(sel : in std_logic_vector(2 downto 0); ctl_immediate : in std_logic_vector(31 downto 0); ALU_result : in std_logic_vector(31 downto 0); IO_ipins_data : in std_logic_vector(31 downto 0); IO_iport_data : in std_logic_vector(31 downto 0); mem_data_out : in std_logic_vector(31 downto 0); output : out std_logic_vector(31 downto 0)); end stack_in_MUX; architecture Behavioral of stack_in_MUX is begin main : process(sel, ctl_immediate, ALU_result, IO_ipins_data, IO_iport_data, mem_data_out) is begin case (sel) is when "000" => output <= ctl_immediate; when "001" => output <= ALU_result; when "010" => output <= IO_ipins_data; when "011" => output <= IO_iport_data; when others => output <= mem_data_out; end case; end process; end Behavioral;
--------------------------------------------------------------------- -- TITLE: Arithmetic Logic Unit -- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) -- DATE CREATED: 2/8/01 -- FILENAME: alu.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the ALU. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mlite_pack.all; entity function_17 is port( INPUT_1 : in std_logic_vector(31 downto 0); INPUT_2 : in std_logic_vector(31 downto 0); OUTPUT_1 : out std_logic_vector(31 downto 0) ); end; --comb_alu_1 architecture logic of function_17 is begin ------------------------------------------------------------------------- computation : process (INPUT_1, INPUT_2) variable vTemp1 : std_logic_vector(7 downto 0); variable vTemp2 : std_logic_vector(7 downto 0); variable vTemp3 : std_logic_vector(7 downto 0); variable vTemp4 : std_logic_vector(7 downto 0); begin IF INPUT_2( 0 ) = '0' THEN vTemp1 := INPUT_1( 7 downto 0); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2( 7 downto 0)) ); END IF; IF INPUT_2( 8 ) = '0' THEN vTemp1 := INPUT_1(15 downto 8); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(15 downto 8)) ); END IF; IF INPUT_2( 16 ) = '0' THEN vTemp1 := INPUT_1(23 downto 16); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(23 downto 16)) ); END IF; IF INPUT_2( 24 ) = '0' THEN vTemp1 := INPUT_1(31 downto 24); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(31 downto 24)) ); END IF; OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1); end process; end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Arithmetic Logic Unit -- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) -- DATE CREATED: 2/8/01 -- FILENAME: alu.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the ALU. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mlite_pack.all; entity function_17 is port( INPUT_1 : in std_logic_vector(31 downto 0); INPUT_2 : in std_logic_vector(31 downto 0); OUTPUT_1 : out std_logic_vector(31 downto 0) ); end; --comb_alu_1 architecture logic of function_17 is begin ------------------------------------------------------------------------- computation : process (INPUT_1, INPUT_2) variable vTemp1 : std_logic_vector(7 downto 0); variable vTemp2 : std_logic_vector(7 downto 0); variable vTemp3 : std_logic_vector(7 downto 0); variable vTemp4 : std_logic_vector(7 downto 0); begin IF INPUT_2( 0 ) = '0' THEN vTemp1 := INPUT_1( 7 downto 0); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2( 7 downto 0)) ); END IF; IF INPUT_2( 8 ) = '0' THEN vTemp1 := INPUT_1(15 downto 8); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(15 downto 8)) ); END IF; IF INPUT_2( 16 ) = '0' THEN vTemp1 := INPUT_1(23 downto 16); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(23 downto 16)) ); END IF; IF INPUT_2( 24 ) = '0' THEN vTemp1 := INPUT_1(31 downto 24); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(31 downto 24)) ); END IF; OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1); end process; end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Arithmetic Logic Unit -- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) -- DATE CREATED: 2/8/01 -- FILENAME: alu.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the ALU. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mlite_pack.all; entity function_17 is port( INPUT_1 : in std_logic_vector(31 downto 0); INPUT_2 : in std_logic_vector(31 downto 0); OUTPUT_1 : out std_logic_vector(31 downto 0) ); end; --comb_alu_1 architecture logic of function_17 is begin ------------------------------------------------------------------------- computation : process (INPUT_1, INPUT_2) variable vTemp1 : std_logic_vector(7 downto 0); variable vTemp2 : std_logic_vector(7 downto 0); variable vTemp3 : std_logic_vector(7 downto 0); variable vTemp4 : std_logic_vector(7 downto 0); begin IF INPUT_2( 0 ) = '0' THEN vTemp1 := INPUT_1( 7 downto 0); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2( 7 downto 0)) ); END IF; IF INPUT_2( 8 ) = '0' THEN vTemp1 := INPUT_1(15 downto 8); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(15 downto 8)) ); END IF; IF INPUT_2( 16 ) = '0' THEN vTemp1 := INPUT_1(23 downto 16); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(23 downto 16)) ); END IF; IF INPUT_2( 24 ) = '0' THEN vTemp1 := INPUT_1(31 downto 24); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(31 downto 24)) ); END IF; OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1); end process; end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Arithmetic Logic Unit -- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) -- DATE CREATED: 2/8/01 -- FILENAME: alu.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the ALU. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mlite_pack.all; entity function_17 is port( INPUT_1 : in std_logic_vector(31 downto 0); INPUT_2 : in std_logic_vector(31 downto 0); OUTPUT_1 : out std_logic_vector(31 downto 0) ); end; --comb_alu_1 architecture logic of function_17 is begin ------------------------------------------------------------------------- computation : process (INPUT_1, INPUT_2) variable vTemp1 : std_logic_vector(7 downto 0); variable vTemp2 : std_logic_vector(7 downto 0); variable vTemp3 : std_logic_vector(7 downto 0); variable vTemp4 : std_logic_vector(7 downto 0); begin IF INPUT_2( 0 ) = '0' THEN vTemp1 := INPUT_1( 7 downto 0); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2( 7 downto 0)) ); END IF; IF INPUT_2( 8 ) = '0' THEN vTemp1 := INPUT_1(15 downto 8); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(15 downto 8)) ); END IF; IF INPUT_2( 16 ) = '0' THEN vTemp1 := INPUT_1(23 downto 16); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(23 downto 16)) ); END IF; IF INPUT_2( 24 ) = '0' THEN vTemp1 := INPUT_1(31 downto 24); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(31 downto 24)) ); END IF; OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1); end process; end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Arithmetic Logic Unit -- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) -- DATE CREATED: 2/8/01 -- FILENAME: alu.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the ALU. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mlite_pack.all; entity function_17 is port( INPUT_1 : in std_logic_vector(31 downto 0); INPUT_2 : in std_logic_vector(31 downto 0); OUTPUT_1 : out std_logic_vector(31 downto 0) ); end; --comb_alu_1 architecture logic of function_17 is begin ------------------------------------------------------------------------- computation : process (INPUT_1, INPUT_2) variable vTemp1 : std_logic_vector(7 downto 0); variable vTemp2 : std_logic_vector(7 downto 0); variable vTemp3 : std_logic_vector(7 downto 0); variable vTemp4 : std_logic_vector(7 downto 0); begin IF INPUT_2( 0 ) = '0' THEN vTemp1 := INPUT_1( 7 downto 0); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2( 7 downto 0)) ); END IF; IF INPUT_2( 8 ) = '0' THEN vTemp1 := INPUT_1(15 downto 8); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(15 downto 8)) ); END IF; IF INPUT_2( 16 ) = '0' THEN vTemp1 := INPUT_1(23 downto 16); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(23 downto 16)) ); END IF; IF INPUT_2( 24 ) = '0' THEN vTemp1 := INPUT_1(31 downto 24); ELSE vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(31 downto 24)) ); END IF; OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1); end process; end; --architecture logic
------------------------------------------------------------------------------ -- radio_controller.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- IMPORTANT: -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. -- -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. -- -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION -- OF THE USER_LOGIC ENTITY. ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: radio_controller.vhd -- Version: 1.03.a -- Description: Top level design, instantiates IPIF and user logic. -- Date: Sat Apr 15 16:16:16 2006 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v2_00_a; use proc_common_v2_00_a.proc_common_pkg.all; use proc_common_v2_00_a.ipif_pkg.all; library opb_ipif_v3_01_c; use opb_ipif_v3_01_c.all; library radio_controller_v1_03_a; use radio_controller_v1_03_a.all; ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_BASEADDR -- User logic base address -- C_HIGHADDR -- User logic high address -- C_OPB_AWIDTH -- OPB address bus width -- C_OPB_DWIDTH -- OPB data bus width -- C_FAMILY -- Target FPGA architecture -- -- Definition of Ports: -- OPB_Clk -- OPB Clock -- OPB_Rst -- OPB Reset -- Sl_DBus -- Slave data bus -- Sl_errAck -- Slave error acknowledge -- Sl_retry -- Slave retry -- Sl_toutSup -- Slave timeout suppress -- Sl_xferAck -- Slave transfer acknowledge -- OPB_ABus -- OPB address bus -- OPB_BE -- OPB byte enable -- OPB_DBus -- OPB data bus -- OPB_RNW -- OPB read/not write -- OPB_select -- OPB select -- OPB_seqAddr -- OPB sequential address ------------------------------------------------------------------------------ entity radio_controller is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_BASEADDR : std_logic_vector := X"00000000"; C_HIGHADDR : std_logic_vector := X"0000FFFF"; C_OPB_AWIDTH : integer := 32; C_OPB_DWIDTH : integer := 32; C_FAMILY : string := "virtex2p" -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ spi_clk : out std_logic; data_out : out std_logic; radio1_cs : out std_logic; radio2_cs : out std_logic; radio3_cs : out std_logic; radio4_cs : out std_logic; dac1_cs : out std_logic; dac2_cs : out std_logic; dac3_cs : out std_logic; dac4_cs : out std_logic; radio1_SHDN : out std_logic; radio1_TxEn : out std_logic; radio1_RxEn : out std_logic; radio1_RxHP : out std_logic; radio1_LD : in std_logic; radio1_24PA : out std_logic; radio1_5PA : out std_logic; radio1_ANTSW : out std_logic_vector(0 to 1); radio1_LED : out std_logic_vector(0 to 2); radio1_ADC_RX_DCS : out std_logic; radio1_ADC_RX_DFS : out std_logic; radio1_ADC_RX_OTRA : in std_logic; radio1_ADC_RX_OTRB : in std_logic; radio1_ADC_RX_PWDNA : out std_logic; radio1_ADC_RX_PWDNB : out std_logic; radio1_DIPSW : in std_logic_vector(0 to 3); radio1_RSSI_ADC_CLAMP : out std_logic; radio1_RSSI_ADC_HIZ : out std_logic; radio1_RSSI_ADC_OTR : in std_logic; radio1_RSSI_ADC_SLEEP : out std_logic; radio1_RSSI_ADC_D : in std_logic_vector(0 to 9); radio1_TX_DAC_PLL_LOCK : in std_logic; radio1_TX_DAC_RESET : out std_logic; radio1_RxHP_external : in std_logic; radio2_SHDN : out std_logic; radio2_TxEn : out std_logic; radio2_RxEn : out std_logic; radio2_RxHP : out std_logic; radio2_LD : in std_logic; radio2_24PA : out std_logic; radio2_5PA : out std_logic; radio2_ANTSW : out std_logic_vector(0 to 1); radio2_LED : out std_logic_vector(0 to 2); radio2_ADC_RX_DCS : out std_logic; radio2_ADC_RX_DFS : out std_logic; radio2_ADC_RX_OTRA : in std_logic; radio2_ADC_RX_OTRB : in std_logic; radio2_ADC_RX_PWDNA : out std_logic; radio2_ADC_RX_PWDNB : out std_logic; radio2_DIPSW : in std_logic_vector(0 to 3); radio2_RSSI_ADC_CLAMP : out std_logic; radio2_RSSI_ADC_HIZ : out std_logic; radio2_RSSI_ADC_OTR : in std_logic; radio2_RSSI_ADC_SLEEP : out std_logic; radio2_RSSI_ADC_D : in std_logic_vector(0 to 9); radio2_TX_DAC_PLL_LOCK : in std_logic; radio2_TX_DAC_RESET : out std_logic; radio2_RxHP_external : in std_logic; radio3_SHDN : out std_logic; radio3_TxEn : out std_logic; radio3_RxEn : out std_logic; radio3_RxHP : out std_logic; radio3_LD : in std_logic; radio3_24PA : out std_logic; radio3_5PA : out std_logic; radio3_ANTSW : out std_logic_vector(0 to 1); radio3_LED : out std_logic_vector(0 to 2); radio3_ADC_RX_DCS : out std_logic; radio3_ADC_RX_DFS : out std_logic; radio3_ADC_RX_OTRA : in std_logic; radio3_ADC_RX_OTRB : in std_logic; radio3_ADC_RX_PWDNA : out std_logic; radio3_ADC_RX_PWDNB : out std_logic; radio3_DIPSW : in std_logic_vector(0 to 3); radio3_RSSI_ADC_CLAMP : out std_logic; radio3_RSSI_ADC_HIZ : out std_logic; radio3_RSSI_ADC_OTR : in std_logic; radio3_RSSI_ADC_SLEEP : out std_logic; radio3_RSSI_ADC_D : in std_logic_vector(0 to 9); radio3_TX_DAC_PLL_LOCK : in std_logic; radio3_TX_DAC_RESET : out std_logic; radio3_RxHP_external : in std_logic; radio4_SHDN : out std_logic; radio4_TxEn : out std_logic; radio4_RxEn : out std_logic; radio4_RxHP : out std_logic; radio4_LD : in std_logic; radio4_24PA : out std_logic; radio4_5PA : out std_logic; radio4_ANTSW : out std_logic_vector(0 to 1); radio4_LED : out std_logic_vector(0 to 2); radio4_ADC_RX_DCS : out std_logic; radio4_ADC_RX_DFS : out std_logic; radio4_ADC_RX_OTRA : in std_logic; radio4_ADC_RX_OTRB : in std_logic; radio4_ADC_RX_PWDNA : out std_logic; radio4_ADC_RX_PWDNB : out std_logic; radio4_DIPSW : in std_logic_vector(0 to 3); radio4_RSSI_ADC_CLAMP : out std_logic; radio4_RSSI_ADC_HIZ : out std_logic; radio4_RSSI_ADC_OTR : in std_logic; radio4_RSSI_ADC_SLEEP : out std_logic; radio4_RSSI_ADC_D : in std_logic_vector(0 to 9); radio4_TX_DAC_PLL_LOCK : in std_logic; radio4_TX_DAC_RESET : out std_logic; radio4_RxHP_external : in std_logic; --USER ports added here -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete OPB_Clk : in std_logic; OPB_Rst : in std_logic; Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); Sl_errAck : out std_logic; Sl_retry : out std_logic; Sl_toutSup : out std_logic; Sl_xferAck : out std_logic; OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); OPB_RNW : in std_logic; OPB_select : in std_logic; OPB_seqAddr : in std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute SIGIS : string; attribute SIGIS of OPB_Clk : signal is "Clk"; attribute SIGIS of OPB_Rst : signal is "Rst"; end entity radio_controller; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of radio_controller is ------------------------------------------ -- Constant: array of address range identifiers ------------------------------------------ constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => USER_00 -- user logic S/W register address space ); ------------------------------------------ -- Constant: array of address pairs for each address range ------------------------------------------ constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0'); constant USER_BASEADDR : std_logic_vector := C_BASEADDR; constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR; constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address ); ------------------------------------------ -- Constant: array of data widths for each target address range ------------------------------------------ constant USER_DWIDTH : integer := 32; constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => USER_DWIDTH -- user logic data width ); ------------------------------------------ -- Constant: array of desired number of chip enables for each address range ------------------------------------------ constant USER_NUM_CE : integer := 8; constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => pad_power2(USER_NUM_CE) -- user logic number of CEs ); ------------------------------------------ -- Constant: array of unique properties for each address range ------------------------------------------ constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE := ( 0 => (others => 0) -- user logic slave space dependent properties (none defined) ); ------------------------------------------ -- Constant: pipeline mode -- 1 = include OPB-In pipeline registers -- 2 = include IP pipeline registers -- 3 = include OPB-In and IP pipeline registers -- 4 = include OPB-Out pipeline registers -- 5 = include OPB-In and OPB-Out pipeline registers -- 6 = include IP and OPB-Out pipeline registers -- 7 = include OPB-In, IP, and OPB-Out pipeline registers -- Note: -- only mode 4, 5, 7 are supported for this release ------------------------------------------ constant PIPELINE_MODEL : integer := 5; ------------------------------------------ -- Constant: user core ID code ------------------------------------------ constant DEV_BLK_ID : integer := 0; ------------------------------------------ -- Constant: enable MIR/Reset register ------------------------------------------ constant DEV_MIR_ENABLE : integer := 0; ------------------------------------------ -- Constant: array of IP interrupt mode -- 1 = Active-high interrupt condition -- 2 = Active-low interrupt condition -- 3 = Active-high pulse interrupt event -- 4 = Active-low pulse interrupt event -- 5 = Positive-edge interrupt event -- 6 = Negative-edge interrupt event ------------------------------------------ constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => 0 -- not used ); ------------------------------------------ -- Constant: enable device burst ------------------------------------------ constant DEV_BURST_ENABLE : integer := 0; ------------------------------------------ -- Constant: include address counter for burst transfers ------------------------------------------ constant INCLUDE_ADDR_CNTR : integer := 0; ------------------------------------------ -- Constant: include write buffer that decouples OPB and IPIC write transactions ------------------------------------------ constant INCLUDE_WR_BUF : integer := 0; ------------------------------------------ -- Constant: index for CS/CE ------------------------------------------ constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00); constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX); ------------------------------------------ -- IP Interconnect (IPIC) signal declarations -- do not delete -- prefix 'i' stands for IPIF while prefix 'u' stands for user logic -- typically user logic will be hooked up to IPIF directly via i<sig> -- unless signal slicing and muxing are needed via u<sig> ------------------------------------------ signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1); signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0'); signal iIP2Bus_Ack : std_logic := '0'; signal iIP2Bus_Error : std_logic := '0'; signal iIP2Bus_Retry : std_logic := '0'; signal iIP2Bus_ToutSup : std_logic := '0'; signal ZERO_IP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping signal iBus2IP_Clk : std_logic; signal iBus2IP_Reset : std_logic; signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1); signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1); signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1); signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1); signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1); ------------------------------------------ -- Component declaration for verilog user logic ------------------------------------------ component user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_DWIDTH : integer := 32; C_NUM_CE : integer := 8 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here spi_clk : out std_logic; data_out : out std_logic; Radio1_cs : out std_logic; Radio2_cs : out std_logic; Radio3_cs : out std_logic; Radio4_cs : out std_logic; Dac1_cs : out std_logic; Dac2_cs : out std_logic; Dac3_cs : out std_logic; Dac4_cs : out std_logic; Radio1_SHDN : out std_logic; Radio1_TxEn : out std_logic; Radio1_RxEn : out std_logic; Radio1_RxHP : out std_logic; Radio1_LD : in std_logic; Radio1_24PA : out std_logic; Radio1_5PA : out std_logic; Radio1_ANTSW : out std_logic_vector(0 to 1); Radio1_LED : out std_logic_vector(0 to 2); Radio1_ADC_RX_DCS : out std_logic; Radio1_ADC_RX_DFS : out std_logic; Radio1_ADC_RX_OTRA : in std_logic; Radio1_ADC_RX_OTRB : in std_logic; Radio1_ADC_RX_PWDNA : out std_logic; Radio1_ADC_RX_PWDNB : out std_logic; Radio1_DIPSW : in std_logic_vector(0 to 3); Radio1_RSSI_ADC_CLAMP : out std_logic; Radio1_RSSI_ADC_HIZ : out std_logic; Radio1_RSSI_ADC_OTR : in std_logic; Radio1_RSSI_ADC_SLEEP : out std_logic; Radio1_RSSI_ADC_D : in std_logic_vector(0 to 9); Radio1_TX_DAC_PLL_LOCK : in std_logic; Radio1_TX_DAC_RESET : out std_logic; Radio1_RxHP_external : in std_logic; Radio2_SHDN : out std_logic; Radio2_TxEn : out std_logic; Radio2_RxEn : out std_logic; Radio2_RxHP : out std_logic; Radio2_LD : in std_logic; Radio2_24PA : out std_logic; Radio2_5PA : out std_logic; Radio2_ANTSW : out std_logic_vector(0 to 1); Radio2_LED : out std_logic_vector(0 to 2); Radio2_ADC_RX_DCS : out std_logic; Radio2_ADC_RX_DFS : out std_logic; Radio2_ADC_RX_OTRA : in std_logic; Radio2_ADC_RX_OTRB : in std_logic; Radio2_ADC_RX_PWDNA : out std_logic; Radio2_ADC_RX_PWDNB : out std_logic; Radio2_DIPSW : in std_logic_vector(0 to 3); Radio2_RSSI_ADC_CLAMP : out std_logic; Radio2_RSSI_ADC_HIZ : out std_logic; Radio2_RSSI_ADC_OTR : in std_logic; Radio2_RSSI_ADC_SLEEP : out std_logic; Radio2_RSSI_ADC_D : in std_logic_vector(0 to 9); Radio2_TX_DAC_PLL_LOCK : in std_logic; Radio2_TX_DAC_RESET : out std_logic; Radio2_RxHP_external : in std_logic; Radio3_SHDN : out std_logic; Radio3_TxEn : out std_logic; Radio3_RxEn : out std_logic; Radio3_RxHP : out std_logic; Radio3_LD : in std_logic; Radio3_24PA : out std_logic; Radio3_5PA : out std_logic; Radio3_ANTSW : out std_logic_vector(0 to 1); Radio3_LED : out std_logic_vector(0 to 2); Radio3_ADC_RX_DCS : out std_logic; Radio3_ADC_RX_DFS : out std_logic; Radio3_ADC_RX_OTRA : in std_logic; Radio3_ADC_RX_OTRB : in std_logic; Radio3_ADC_RX_PWDNA : out std_logic; Radio3_ADC_RX_PWDNB : out std_logic; Radio3_DIPSW : in std_logic_vector(0 to 3); Radio3_RSSI_ADC_CLAMP : out std_logic; Radio3_RSSI_ADC_HIZ : out std_logic; Radio3_RSSI_ADC_OTR : in std_logic; Radio3_RSSI_ADC_SLEEP : out std_logic; Radio3_RSSI_ADC_D : in std_logic_vector(0 to 9); Radio3_TX_DAC_PLL_LOCK : in std_logic; Radio3_TX_DAC_RESET : out std_logic; Radio3_RxHP_external : in std_logic; Radio4_SHDN : out std_logic; Radio4_TxEn : out std_logic; Radio4_RxEn : out std_logic; Radio4_RxHP : out std_logic; Radio4_LD : in std_logic; Radio4_24PA : out std_logic; Radio4_5PA : out std_logic; Radio4_ANTSW : out std_logic_vector(0 to 1); Radio4_LED : out std_logic_vector(0 to 2); Radio4_ADC_RX_DCS : out std_logic; Radio4_ADC_RX_DFS : out std_logic; Radio4_ADC_RX_OTRA : in std_logic; Radio4_ADC_RX_OTRB : in std_logic; Radio4_ADC_RX_PWDNA : out std_logic; Radio4_ADC_RX_PWDNB : out std_logic; Radio4_DIPSW : in std_logic_vector(0 to 3); Radio4_RSSI_ADC_CLAMP : out std_logic; Radio4_RSSI_ADC_HIZ : out std_logic; Radio4_RSSI_ADC_OTR : in std_logic; Radio4_RSSI_ADC_SLEEP : out std_logic; Radio4_RSSI_ADC_D : in std_logic_vector(0 to 9); Radio4_TX_DAC_PLL_LOCK : in std_logic; Radio4_TX_DAC_RESET : out std_logic; Radio4_RxHP_external : in std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Reset : in std_logic; Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1); Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1); Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1); IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1); IP2Bus_Ack : out std_logic; IP2Bus_Retry : out std_logic; IP2Bus_Error : out std_logic; IP2Bus_ToutSup : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); end component user_logic; begin ------------------------------------------ -- instantiate the OPB IPIF ------------------------------------------ OPB_IPIF_I : entity opb_ipif_v3_01_c.opb_ipif generic map ( C_ARD_ID_ARRAY => ARD_ID_ARRAY, C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY, C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY, C_PIPELINE_MODEL => PIPELINE_MODEL, C_DEV_BLK_ID => DEV_BLK_ID, C_DEV_MIR_ENABLE => DEV_MIR_ENABLE, C_OPB_AWIDTH => C_OPB_AWIDTH, C_OPB_DWIDTH => C_OPB_DWIDTH, C_FAMILY => C_FAMILY, C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, C_DEV_BURST_ENABLE => DEV_BURST_ENABLE, C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR, C_INCLUDE_WR_BUF => INCLUDE_WR_BUF ) port map ( OPB_select => OPB_select, OPB_DBus => OPB_DBus, OPB_ABus => OPB_ABus, OPB_BE => OPB_BE, OPB_RNW => OPB_RNW, OPB_seqAddr => OPB_seqAddr, Sln_DBus => Sl_DBus, Sln_xferAck => Sl_xferAck, Sln_errAck => Sl_errAck, Sln_retry => Sl_retry, Sln_toutSup => Sl_toutSup, Bus2IP_CS => open, Bus2IP_CE => open, Bus2IP_RdCE => iBus2IP_RdCE, Bus2IP_WrCE => iBus2IP_WrCE, Bus2IP_Data => iBus2IP_Data, Bus2IP_Addr => open, Bus2IP_AddrValid => open, Bus2IP_BE => iBus2IP_BE, Bus2IP_RNW => open, Bus2IP_Burst => open, IP2Bus_Data => iIP2Bus_Data, IP2Bus_Ack => iIP2Bus_Ack, IP2Bus_AddrAck => '0', IP2Bus_Error => iIP2Bus_Error, IP2Bus_Retry => iIP2Bus_Retry, IP2Bus_ToutSup => iIP2Bus_ToutSup, IP2Bus_PostedWrInh => ZERO_IP2Bus_PostedWrInh, IP2RFIFO_Data => ZERO_IP2RFIFO_Data, IP2RFIFO_WrMark => '0', IP2RFIFO_WrRelease => '0', IP2RFIFO_WrReq => '0', IP2RFIFO_WrRestore => '0', RFIFO2IP_AlmostFull => open, RFIFO2IP_Full => open, RFIFO2IP_Vacancy => open, RFIFO2IP_WrAck => open, IP2WFIFO_RdMark => '0', IP2WFIFO_RdRelease => '0', IP2WFIFO_RdReq => '0', IP2WFIFO_RdRestore => '0', WFIFO2IP_AlmostEmpty => open, WFIFO2IP_Data => ZERO_WFIFO2IP_Data, WFIFO2IP_Empty => open, WFIFO2IP_Occupancy => open, WFIFO2IP_RdAck => open, IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent, IP2INTC_Irpt => open, Freeze => '0', Bus2IP_Freeze => open, OPB_Clk => OPB_Clk, Bus2IP_Clk => iBus2IP_Clk, IP2Bus_Clk => '0', Reset => OPB_Rst, Bus2IP_Reset => iBus2IP_Reset ); ------------------------------------------ -- instantiate the User Logic ------------------------------------------ USER_LOGIC_I : component user_logic generic map ( -- MAP USER GENERICS BELOW THIS LINE --------------- --USER generics mapped here -- MAP USER GENERICS ABOVE THIS LINE --------------- C_DWIDTH => USER_DWIDTH, C_NUM_CE => USER_NUM_CE ) port map ( -- MAP USER PORTS BELOW THIS LINE ------------------ --USER ports mapped here spi_clk => spi_clk, data_out => data_out, Radio1_cs => radio1_cs, Radio2_cs => radio2_cs, Radio3_cs => radio3_cs, Radio4_cs => radio4_cs, Dac1_cs => dac1_cs, Dac2_cs => dac2_cs, Dac3_cs => dac3_cs, Dac4_cs => dac4_cs, Radio1_SHDN => radio1_SHDN, Radio1_TxEn => radio1_TxEn, Radio1_RxEn => radio1_RxEn, Radio1_RxHP => radio1_RxHP, Radio1_LD => radio1_LD, Radio1_24PA => radio1_24PA, Radio1_5PA => radio1_5PA, Radio1_ANTSW => radio1_ANTSW, Radio1_LED => radio1_LED, Radio1_ADC_RX_DCS => radio1_ADC_RX_DCS, Radio1_ADC_RX_DFS => radio1_ADC_RX_DFS, Radio1_ADC_RX_OTRA => radio1_ADC_RX_OTRA, Radio1_ADC_RX_OTRB => radio1_ADC_RX_OTRB, Radio1_ADC_RX_PWDNA => radio1_ADC_RX_PWDNA, Radio1_ADC_RX_PWDNB => radio1_ADC_RX_PWDNB, Radio1_DIPSW => radio1_DIPSW, Radio1_RSSI_ADC_CLAMP => radio1_RSSI_ADC_CLAMP, Radio1_RSSI_ADC_HIZ => radio1_RSSI_ADC_HIZ, Radio1_RSSI_ADC_OTR => radio1_RSSI_ADC_OTR, Radio1_RSSI_ADC_SLEEP => radio1_RSSI_ADC_SLEEP, Radio1_RSSI_ADC_D => radio1_RSSI_ADC_D, Radio1_TX_DAC_PLL_LOCK => radio1_TX_DAC_PLL_LOCK, Radio1_TX_DAC_RESET => radio1_TX_DAC_RESET, Radio1_RxHP_external => radio1_RxHP_external, Radio2_SHDN => radio2_SHDN, Radio2_TxEn => radio2_TxEn, Radio2_RxEn => radio2_RxEn, Radio2_RxHP => radio2_RxHP, Radio2_LD => radio2_LD, Radio2_24PA => radio2_24PA, Radio2_5PA => radio2_5PA, Radio2_ANTSW => radio2_ANTSW, Radio2_LED => radio2_LED, Radio2_ADC_RX_DCS => radio2_ADC_RX_DCS, Radio2_ADC_RX_DFS => radio2_ADC_RX_DFS, Radio2_ADC_RX_OTRA => radio2_ADC_RX_OTRA, Radio2_ADC_RX_OTRB => radio2_ADC_RX_OTRB, Radio2_ADC_RX_PWDNA => radio2_ADC_RX_PWDNA, Radio2_ADC_RX_PWDNB => radio2_ADC_RX_PWDNB, Radio2_DIPSW => radio2_DIPSW, Radio2_RSSI_ADC_CLAMP => radio2_RSSI_ADC_CLAMP, Radio2_RSSI_ADC_HIZ => radio2_RSSI_ADC_HIZ, Radio2_RSSI_ADC_OTR => radio2_RSSI_ADC_OTR, Radio2_RSSI_ADC_SLEEP => radio2_RSSI_ADC_SLEEP, Radio2_RSSI_ADC_D => radio2_RSSI_ADC_D, Radio2_TX_DAC_PLL_LOCK => radio2_TX_DAC_PLL_LOCK, Radio2_TX_DAC_RESET => radio2_TX_DAC_RESET, Radio2_RxHP_external => radio2_RxHP_external, Radio3_SHDN => radio3_SHDN, Radio3_TxEn => radio3_TxEn, Radio3_RxEn => radio3_RxEn, Radio3_RxHP => radio3_RxHP, Radio3_LD => radio3_LD, Radio3_24PA => radio3_24PA, Radio3_5PA => radio3_5PA, Radio3_ANTSW => radio3_ANTSW, Radio3_LED => radio3_LED, Radio3_ADC_RX_DCS => radio3_ADC_RX_DCS, Radio3_ADC_RX_DFS => radio3_ADC_RX_DFS, Radio3_ADC_RX_OTRA => radio3_ADC_RX_OTRA, Radio3_ADC_RX_OTRB => radio3_ADC_RX_OTRB, Radio3_ADC_RX_PWDNA => radio3_ADC_RX_PWDNA, Radio3_ADC_RX_PWDNB => radio3_ADC_RX_PWDNB, Radio3_DIPSW => radio3_DIPSW, Radio3_RSSI_ADC_CLAMP => radio3_RSSI_ADC_CLAMP, Radio3_RSSI_ADC_HIZ => radio3_RSSI_ADC_HIZ, Radio3_RSSI_ADC_OTR => radio3_RSSI_ADC_OTR, Radio3_RSSI_ADC_SLEEP => radio3_RSSI_ADC_SLEEP, Radio3_RSSI_ADC_D => radio3_RSSI_ADC_D, Radio3_TX_DAC_PLL_LOCK => radio3_TX_DAC_PLL_LOCK, Radio3_TX_DAC_RESET => radio3_TX_DAC_RESET, Radio3_RxHP_external => radio3_RxHP_external, Radio4_SHDN => radio4_SHDN, Radio4_TxEn => radio4_TxEn, Radio4_RxEn => radio4_RxEn, Radio4_RxHP => radio4_RxHP, Radio4_LD => radio4_LD, Radio4_24PA => radio4_24PA, Radio4_5PA => radio4_5PA, Radio4_ANTSW => radio4_ANTSW, Radio4_LED => radio4_LED, Radio4_ADC_RX_DCS => radio4_ADC_RX_DCS, Radio4_ADC_RX_DFS => radio4_ADC_RX_DFS, Radio4_ADC_RX_OTRA => radio4_ADC_RX_OTRA, Radio4_ADC_RX_OTRB => radio4_ADC_RX_OTRB, Radio4_ADC_RX_PWDNA => radio4_ADC_RX_PWDNA, Radio4_ADC_RX_PWDNB => radio4_ADC_RX_PWDNB, Radio4_DIPSW => radio4_DIPSW, Radio4_RSSI_ADC_CLAMP => radio4_RSSI_ADC_CLAMP, Radio4_RSSI_ADC_HIZ => radio4_RSSI_ADC_HIZ, Radio4_RSSI_ADC_OTR => radio4_RSSI_ADC_OTR, Radio4_RSSI_ADC_SLEEP => radio4_RSSI_ADC_SLEEP, Radio4_RSSI_ADC_D => radio4_RSSI_ADC_D, Radio4_TX_DAC_PLL_LOCK => radio4_TX_DAC_PLL_LOCK, Radio4_TX_DAC_RESET => radio4_TX_DAC_RESET, Radio4_RxHP_external => radio4_RxHP_external, -- MAP USER PORTS ABOVE THIS LINE ------------------ Bus2IP_Clk => iBus2IP_Clk, Bus2IP_Reset => iBus2IP_Reset, Bus2IP_Data => uBus2IP_Data, Bus2IP_BE => uBus2IP_BE, Bus2IP_RdCE => uBus2IP_RdCE, Bus2IP_WrCE => uBus2IP_WrCE, IP2Bus_Data => uIP2Bus_Data, IP2Bus_Ack => iIP2Bus_Ack, IP2Bus_Retry => iIP2Bus_Retry, IP2Bus_Error => iIP2Bus_Error, IP2Bus_ToutSup => iIP2Bus_ToutSup ); ------------------------------------------ -- hooking up signal slicing ------------------------------------------ uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1); uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1); uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1); uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1); iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data; end IMP;
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Tue May 30 22:27:55 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub -rename_top system_ov7670_controller_1_0 -prefix -- system_ov7670_controller_1_0_ system_ov7670_controller_1_0_stub.vhdl -- Design : system_ov7670_controller_1_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity system_ov7670_controller_1_0 is Port ( clk : in STD_LOGIC; resend : in STD_LOGIC; config_finished : out STD_LOGIC; sioc : out STD_LOGIC; siod : inout STD_LOGIC; reset : out STD_LOGIC; pwdn : out STD_LOGIC; xclk : out STD_LOGIC ); end system_ov7670_controller_1_0; architecture stub of system_ov7670_controller_1_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "clk,resend,config_finished,sioc,siod,reset,pwdn,xclk"; attribute x_core_info : string; attribute x_core_info of stub : architecture is "ov7670_controller,Vivado 2016.4"; begin end;