content stringlengths 1 1.04M ⌀ |
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library ieee;
use ieee.numeric_bit.all;
entity xnor23 is
port (
a_i : in bit_vector (22 downto 0);
b_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity xnor23;
architecture rtl of xnor23 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity xnor23 is
port (
a_i : in bit_vector (22 downto 0);
b_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity xnor23;
architecture rtl of xnor23 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity xnor23 is
port (
a_i : in bit_vector (22 downto 0);
b_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity xnor23;
architecture rtl of xnor23 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity xnor23 is
port (
a_i : in bit_vector (22 downto 0);
b_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity xnor23;
architecture rtl of xnor23 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
sig1 <= sig2;
end process PROC_2;
end architecture ARCH;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
K3gmSOM7POFFC4Vp1wqdf/cLg+XFdquji8tynMaryJILZOozcHCJ8IbqNKWgRNMEfGkRM2IKYFsN
LRP6C817pg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
bgc2eKb8e8mC+Ugzf9NNufWY5ukUVeu8sNBuXX+VvLi2VCKfcf3/EbTbiETssKlazlqhEXTv2s1+
nLSgeAOQvsKkDmL6vWoF99ZY/TQhHgYMpSRuVYu/W0VO5yRCMlfOFd3J5FV0gEpYBeDF7QfHtlD8
tP44XxUa6jVzW5cL0vY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rAjgbHi5JFX9IZ8UdNgm2jLu+6hdXXnzmZy74gEMcsM2afVcE/vxipf6lcP3MG4z2i+EaLXX6pZf
jh34kSX7UYtVSFFtT8a3UxfX9uYvIUu1wDgKCcRNgnGwj35CE5JxC9dAhOddTbOTiw8vSEvUcg4L
TsB1Mxlbe2kxOuYzINWIcFpy8H+0Un5HAiFj2FXxf8GTwCiEQfGtb5R2kRKrQDxFu1LhtnURVitx
0D2bTp7YacAS0/1na7FAYgeadwKdc7mLjY7wv+0QEak2UsmYNsjdlVBoF2vW0IY1rD48azik/gky
GIL4tYgd0YqZtHWyQrBOsM38Z43VNKB0OGykzg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
2rwaGoQVBHpsVMi+VvJ+TcNYf6llQroavWPRdy680OGFIjv+Y+tlxOfqnqj7BD9BYfNn6PqoBSj8
UaRlTYK78WKFJcSSOkMUwQJkNuYjFpUVrnjSAmnaU3u/SfrqQ4eTMwTapwDbrc4qtKG5nlHj12ea
/7AMCgF8piF8Jf1kTCQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
drxCTC0qG5mm+tXdqjy3tcDXmIxtaglEAH3R2X+gDx3cCCwNYdPeCJWZrBioWo38u7rDw7K/6+4h
TgdQQwGFEZa37VPCDg9Frm4ZAAkUWLoa2prtIfoneHNVWIrUk94S8N28EL+B+g49xcq4suOn+OGv
gqNpbQhFCSXD/Mv/31oa/qOERDeXIxfmZo4nDIvZm6Q0ELswuYX7/cyxOxyjRPinhjWw7GY1l5E8
IaUHclQ0R1bZzuLRUEZ7+/tqE/6GlxyIRHUv0uafykZ0WSLiOBG5fFJ7T2+hnmovJoZRpkhyhCZa
CYvFA4xhe75T3lgbgCeyfJs47UZ/tAtfPqU5hw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12224)
`protect data_block
tq8Yf1MfsjaegmCxm7EgtgYvbd8DhPzhjDmYQLWbfOhwYLBzb1geWcSL6aEl8K1bBQnSOdD6CDqw
JNnX4HOxChnJ4poEi8eCPHVxAkXtSM4sMmYoO2viNhZngBzUkKS99Y6xk1MCMyi3hBvD+W2454QB
/PXcezEXjG3tUV/CfzPLaDYOouMAoyWGWRpfAOmbaQAmHNUfSZ24fUedeqEyIdSczlk048VUE4Ie
Yw01T9nPZ1sg9FZ8Iy/RLQdZt7N3uwu1GrJdhRcLzItDtM6TEbiiLtdwwDcHQMfFqIPGSdMlQZkc
Lp+qlMIK1eTsFbpr0fSqS5IxBACYyldd4HQ30bx00n91+cdtTEFyejDImCFI0iZHSLSNRVtqryGL
5c2MlWmykSqSrbiiZCaX7MbMnDi1eVi84w849Rc+1JRWM9uNI4Rkvtn5Yx7+LBqY70bHx+WWvnb8
Qa+riHOci5sTRmQVaOv02qu5Pta5O8C08t+rJ+jEPHxTLI/STdNbkn7u/XuMR3w5xUB4/JxT11Ry
5sUmFMBMfgQN6vB/Al51sQDFszvSSGQkgZe2n7NPZJGwgP0yIDloVxE4L3lAuG1N4muCT4T/nrDS
I7Oec2LMl0bO415te6uBT/EU+zmKI6FVjepwilADKs3JPKadhVLNsgIh9Z2VuLVuVUU4Kqp0NpNk
tbNO4TlShZ9tVtl1AYccv0lDUWsb56ir85kZwsSbJwbULQ3Te8rbNtCD0/zFG9l5e+crV1OEKDCe
hgNncILgNguooonxHLgP7XPVs8EUcPuYITuWa9aVKdbV22smOOzdXZQ87XlQyoVSiQ/SH/F3AV7+
LRgVYtXpEfky6m9Zk77tuP+WIX2xUXVE5nhlmyxZ2/zidXObZupHjqabBZQx3xa5ve1j78UCWqHh
UqzvhYVZJY1pMtZUxw4CSbZTggrhAaLQgWJ9ufZoBqmuDy7Di77wevWhy670RCjjmGD+573ZQ83i
DHb5hOIPuHJnPgjB7Q4L7ju8FK2neQ74M3k23zMfuy/81fPMrqp/E1rmto8awRbzEmzAZVHMRYFK
fJYgf17eaEYoeu1uWyVP8R991wsqUmHs5p3IC0aLKAF+Kbx/x2YYHF39/CFr6k5QF0fV+QRuWHTX
rlEW4cnwZxyDIv1PkkPmM25B8zx+UX3MzMmvWJu6ARHhj0xuAaFQ/Xk8eBw+72GJYohwbKTHy4vT
E1paOUvb3i+UFB2eis3zl7YhOBWPURxptJpqabcIpJ3T4S5lswKVrNMbnFGJWoroFWTI3gxaHHba
pXUhaSENhxCptdSh0a7gi08zomGtjTaVDqaRZvctKL6Q0zEkeiBU/qEGIQPvi6LmzOj+3jQBSp9N
le/2TOXQyNouE+FBN1rxVZkUsbfFA8O1W3OeiFddaKmb2f1FIlvhhvR+DnoK56X4wgjpU/xrX1c+
g7BV1gL+YdvAqzEvOq1UtGlM+xGP2JK4gapVEACDJmodCeTPiLguRjklF0VZxMTd9gH7fu7FaDQV
N4L0k/KWlWg06Z6BoQ5wCeDKUFnNslW6+/TuYAlHCRx8wBtdfND8DmHSUAApx9TkJQfawS2jNX6D
hQbWfeo9F0FTMv/DAuSYbTHcOuHkPacXSD657bkcdvICvHV8textYNFWvqxcwit11uHxNC1df5AF
ITdX912zoLkp0wLOP36zf9OUHavSJlDMLci+a7ukh+oFkhukA1McsTlcbYji6MjevKB6A4bH5MLE
JbYJ6vRT4rZmUndepTV+QDQFW+17OA9/hjGi1Le7vyYqc3JY82I2o8FqF+H3mMiaVNvlxiijnfDn
mF0uv1gzJ/+uBucI72miJRcd98UCFYIQOuY8GUVVvqtPx9M2rqiYZN6zu6h1kypdHhMdEWtb87F7
lJ15wnvR7E/87JUmUUawq9FS3DgKokJMHLZf++vOBDDrqG/fIKW+n/e1vv1KTPk+rRMk1RDTPUO3
75y0bRMiGMOypkNJ8iNBw7IUl37lm0H350REGbCJq8y938nZkGg1HMuw/lF7iwO4ZCbdflzspauz
2D8axtrnt7uYVerw9T9huePwnPWKldI/WmRCwcA/busiR8tphv90A+kNyJd04JhBXo60JXLVYfn1
ASvsiqkpGiCdoIm5sB4HMIBKJQuwwII9EHLkYSGI/Unl9UsLGT2XbJNVudmkCb5Oz0+sYcas9BHT
zOe8GUSR/OlLLpg0VmOg+osBebyS+LON7ofVJqX28u0+OXg6Y30kngHA43SqOO1W9Zitkg5JL/Pn
kkk1Ph9M2PTgFeu+ov+h3nJQzGwc5zt/8snUzx/jbefdCW9icLW+OA9drBDdFKbnBdAb5Cd+6v1c
lHF1YnJgVQi33Q8SFgGwSKMxDwkng7tenBHxNJESSifZlB9tsWqkYdUzV4C3gO4E5Dyv70QRH9B6
aUdQeT2Pk/vOkvJFXq7vmEHn5FSbIes6UArPAkj5zcBFQww8hT4/BrRVgBc2HP+03KFqIY1dx77B
gn/kTWDZgo3qxvZTjqFSeeym50/jjaE9iCdRG/znRhpwlEmp9j4ZAr0ss3q3DuodqrQY2vnzvMH+
ML0QdAtMZ9o8/s2jpPZSR7HK2+YGvo5whMBNiaSE6I4MXATpBky8YkTdJvpZLyOn2+ux+ok7j8D/
iVxRdvcwha3T/pEk4LNNXnVj8xB0qHpHBVNnj8tsFm6x+cCatPEJHOs2shrvPpdNWEDgqzeUrWOI
bF/y/K00WlzXdRc0O7imEBFDTP64bw8GADPItEf+B+IikZm3BWSxsA2foe+j7xOygDhHzMs5auoZ
GWD+grZGAlHT1nH6Uj/SQ6KbY1+hWuiMupL3lzdLenj9clr48+GUBTfKTb5itZ6wEmwgSD0HF3Sz
jaq0MjmrPjwP258lJjYBkeOPUORxlRpgP7w88voqIi/h+2acoiOAEg49E2ddcWe+8GRlhEbCLQQA
0Gtd6IyXn3g3wNS5FStwnzvkqyhKUbOFt1SCq8MmwdcTMW4aHsPD0YfkAPslfZPQ4NFch0BNwVJY
h8wdHmKt/5R63gPvFPUSakUIsPkKYuuAEz8Vg7O84Mu8R/xYsn9VBwBjnFf6hcv8WBy385daV2JM
xg4nLasLimHnQMJLlVgpNhW3c3pVbydIJRu3n/UGHCHvzae4OULz0rmCnwRByHk5T6ksIYKf0X20
5iukvSTN7hb6Qt3oVuz12G+dkLlg7JGCiwJPHSLEqkKIjx6yLqNnuHWEknGI3GpPYLffo9tezgLZ
BJztjNkQqbI7v0s15CU+M/djjsWaAA4SkZ+w+TbPRBrgvqvPjqVT2YZ4RwZIrymYZhcG+HLwkk8I
qeAVraGbN/lCCBonsjOob0UsuH2+MHeqNHR9fwxZNT6QtmVUmfAXfZz5hrrTe0/XA4giW69c5vbq
6f4G39wfbGukzuCIue9rkkLVQImg57j2SkcSGDGhE9U1M2j2Ml5AuvSR509GIZwl43ZCwaHqa+E2
wW29ZJzn4p4A1W6zMBxpPbB5JmVwtGW31J36rkIxGiqZV8+y8UlIE/FcCImfzaClsMT50HH51qxj
yFsPLGoOJRUZIM4Gx3dn781wKGZlTeY/JVzWDl6g/Ln7Se7SWA1kkR8xdnL1sUUutCry4ThZ1YNC
+ZTc65arGz+YGLZBHGPxu2GV2w57V/FZM+FRWaE4PFjuywlp2Vn0g/QJ8u7EW5NRr5shLzTbAsQs
SSN9nwEInGR2iHezGk1Qit78J0woa3HROyfs6d3Sn2nGYFsMcuh9LjWCkvp8pb+TNwHA/0gXFFvJ
xCJs4mz/yCcofJaQjda/m24N3FzyBJH7pWr8wehNnUsUbEsy/9OEHrPc0ZPR6MEzeISSgbLr75bf
3JXCpNCI2uZpqS6ggqK+jwE+ycyQW1OFNKigr29wkbGni9atYUHYO6cNt0QQsZGcpMo6J3dnD8N1
OFwwXGHhKrIdk+UDQAYjoZAW/M3ET4xKBqISeGKrjx7DKW5nxUmCMyBfrAgNKrktYZdmQcf4tk2H
AEjjBMQDa1iXpNW/cCGXe8CIE1bZeRH1ldGLZ3QVis2mtBX7w9Q3mWcmZ0zPgi5rAwwNXO0TM9lt
PCBxuOBmuSzQTsrP5oG26dijNyK1TmUnz2FHz8s9G/EJiXdLflBJR27xW62pYCMQ3JS3a/a/p7aM
epsQ/VAyhA1t8d9luN+D10O3g6hwlnUzaweai6IlcHo8KHi0880adI0d6HOZcy6nkiozsS6X4Cbw
sVbh6fBzE9oubhNNQB1mRat8j0e+apaZBucXofuWALsmmA2n7QwZ3I4+vTH/UBoRnQyvLrNFDtKT
soqSr+DcgiMsTbl8VgppwdNvtNtHsN0QEcV8+Ou9X/T1AmAyim+ecfN8dYC+VWU4pt92K7VvDfuE
wuyFtk3yIQPVrKCdedalT1Sy9isZzfw6fiGpKyHSzaWsrmhlGyqLM50jr6CD8WEpT51mkM+JgW04
NCTkZArkSRjUQNcpupmftsFJBUYhftSW8V8ouIS0EdGptLNsQUo4hcCeFDyo54JzV5uKq7XKiXm3
eV4YJvdyW/r8q/LS0jAUS+Df1S3oUKsvef3dPreiygv4X0Grh9KLDV7L+OeyDC4Y05YSz39K+oOz
fByQs2sgb+mYrb1BGvdq3RxjnCoCCtKr+oALubZ01YCA8cLgM0H8Lwucyqab/Ul1d0GD9++/fN42
JfM2F0g7VDCedHFkMHYcRSxV2aGHTiPXi2tWrlC9u9Q6jG8itjhXVxsZT4yn6KwhfmhVeCL9MxuL
JSPUAnlZm+oCWrA3zhuJX7aT49EVkBxBJ/knkc/brlqt1wrVxNJ7OvunfS7XE6KPgCb7ipbVQaVk
eTXuJ2sVB86SxGT6xibUqNKHVe9a+5pohnwnSDaHzPMrmcu3Odi69YskgmgF/W95yVjRd9+Kvi1+
9UAmJYH/gjL5+bWBlc8ddmmujaQETBExisrvmpmW/8nq6FGjAXmyz4O46tQIHbCiCH7ypdoTUq/Z
xYVNtsJujD00+HR7cCJvOVZF1TGr1yCGUGOwQsutXMyjXhd0N832zUxEtOe+NCn7D4sV+3/aQZQU
1Pl4CuVmR+HMlMhQRPGhvKH+dLVt5OW6vgB7JU58DVfxKImBG/BeiH3NJLdHIwkggoJgHpsazT2p
5mp8+1Vt/DgRx9HrNQCd/OJPxarrzHSSYzz4S8AM+uHwQGeMgHCOu8QG4ZQavqlo+e3Q1roBKxrJ
KquhFXDp17kHs88BJPlhI2snacVcLip4ujAowMQvJIh2ey9ljBFirqULyz2emTida/Tu+xQhSAmO
BZ1h27iA6bfIQn2PXVaPkcinxH7HivsA8AfrusSDNWooSZAhbBnKAgGYg+NfXrZBsc7rie2weEMn
EQeXhfjYVr8vBTrnArnJT7NNi8QIPHNJp9zO0sgX0IkbNqALIWufGrDSCWV9gchEdZRvp2wHym0D
fs1WvNQEiTn3rDZaGeWtpBwwmNtAjoSAxAJCrz9J4w4UX8FmAdrEkXfphiBabRbdq77js2uPyob+
vv0VRvDi9Vu6PJ40wVmoMbKXlHWJt+ax7hDZsnw4T7lhOPvBYmfeKvtZMaud/gdLK4CQvLEHWDPp
6cGTWO7hyhqEUSdvS6Ffuhb/Sfceib5IDM3Ri6kaD+6jS638cZZxVmPO+rIAH2VHElaMYE+IG68Z
vPhwuQtJr78o0fKDJz/b/SOk2Crk2BJeiRzTEb4OTR+MAsGfpAwJhFdOh05zAIFz9QIalfsNfZFb
LVjTbRcWUksl1JMqiN/yJj7eBwnVPK68apzSK/BR4dg6gydtgY3ao+/os/65Z6RAjJ7EQ++qFbBI
yMq1aMqkHSQruv0h8QAlLWLteTPATbjQDpQ9T6SRr2QDJtV8CfsbDyoxrGpPb2L1uvk8HDb21nV1
DPBQawwJZtX2ddJjEAGlzAXCI/7enwdkLnZ6TA+kH4Ixg+7wS1LFd0z1caBSeio7uWq2dZj5cxQg
EeLOMXuVmbTmV4wjwt7yvayN0yZSRGJaZNgsirOO8QlBbcxtQ6fKl9rxZP2L4uL9ppQK12TiGYPN
ftk0CuIpZ4JqP9oS2XYBI9IGXKoOk9xKfHLHBi8FzyxQ/RUD583laqwpka4ateAlXi/CED/AzoRA
QsFYHyJTtcc56tT/LaWqbQPOW8QyNU0ZcyRYb4lzyoxW2AcyMwGDyc1057TCyfp5RDTzqC23yGta
+AfbK7jFYTraOVQbZCZRbyowdWZijIuT1jwM24fK3XHhImLG8SxUmD0DeqIzvEPEahmx8AykG63h
clbBlUyQprpbPMoKismt5x97Sf3MDl+iUFcdkdioOQkQYcuzsGMpy4E3yf6pKbDAzuLSil0wsOQ+
K0XfBpoMTTPjguX+bIrl/EsfWLX6OWMYZE4Xchoa0myThgC3ehkedWwBm3OAf///030IqC1t1N+M
+f29daNrbnZaNRyaYBH3oa91vKTIiQ47kcjlUx7XdfuxCezycVjRrQpyd1HWedrfmhhZrswzy2mq
mygKdjpRejG4f7dotHH36S447D/pKE3gGTLsAj/03e8mGtlFU7nSWuvzFiW5RJ0w4xoSkygG/8Cq
LgM/kP/2+iBMUbd2MgPcnbrYKz62cByg40hBUbuZ8q+Tu9/WEQ+oqnNc+wA59fbOhF23972Y9L1P
MRxI6jU7xmXDORpKsEGXC/GEaR9JflY0fv+tiWcTU4xZvQ+Sy8Lxr0sjk176SWtCzsvrHBu7Qw7k
WRL+zg1rnKsw4JQLnWN1uGe2PEe8oBRSbEEImwkfokjy9XEjYia6Ygdx/sdSWkKqUI1dndpCSow9
E22aZ2J4ZfhbP6ATLZLjCyz7lgLMLb9NXqtZCd1jVdk5EeT0Nt6Y3Kdmj/tkclHTEe6U1QbC52uS
wCJCJs7PpVq5IEPeROgb5Gfa8rZKUcQQRDoYneZWbXz7d1hLJkjjgNr/5RF8fqNto1T5NhWcVdYk
ududmXmJvaxEWmcpll02Hx3roAOtvuAzhXGjF8IMEEcwEA+xJU8xv72pfev0Nt05Qc/utVyc6oxE
PEQBJZO1t5b7jfUSCLWzrn3HuyD3K8wCk6A6pl2GnR2BGIxh158YUEI0NKsTJVdLHY8Kcu0uBnSK
wjrv1IGKxs+qA408Lozfz4V3B0Mm4JjLqrF367wDaouTdjg4uk05zGvWeqUcHUYnt5cI+3VzWRoU
D22jDcRaYL80vklHYtgKma7EHrIiIr9wJAEyHHCyt7boH7hToDB52EWak8z2YN0FrotJacLpiXCX
ZCDszoWTBQ021z8XStwt6ce0IZLQ4FpRINCDqH5Q+t5nGu70iH0HVcK76gIGai7P0RccJnbLayfH
TE6tKnxQF/acln0gmZsFuRwXSo6skO/3VZ98TftTo09xQfK/4iCojdXIwYllJVm+saMSdC6cNkQh
h6xrIa7d7ZtNwjDATTKKg+4qDxFsLBC+axgzvTii3i0y6a+P7CfzXpW70/Kw5V+KyMlm9/nUo1oo
ueSA5OpKYLSdM+7Yq8F1kMmnV84sliPHzYej6oZEy6Gbv1mkBfeCKpNZpeo0pzVsOlB7buSSQTxu
JCNiWBKHbl9cORT1jLmZSHr57wmr7LZN0i4GAnuxYEilpAMFU0vi1MHJFu6mf9N6tUqDRXFGFkQl
lo72N51s2GsrTqAMwIKrPH0NvxsE8FXenetcv5mCDN/auT8l7Vet3W559ALdbuqP9IBALk+plm7k
u8A8rEZZ3wS+ZFqhYI0S73SLoUyF9vwzxpmQSjopX+lVLT7l4TpJ9f1K5avCtd1scikjIs+T3FDJ
nEb4ZECFjSOgC3ceKkLNAdV27R979bCbTAf+Uo7PJsQyzP86Dz2gO3j8TVyTeML30pwZPz/mr4KK
ZNC8DGbyR/IABTTXFm8W3v/YHLgDfE3VyE42w0UJaHvA7y9qIOrn2PblTrJoeiJKWTqM95pvFg84
K5+wI8+AfgUJ6PzSVly5/lCPDSn/XjMqnU2vDS43/1WFNCH54SefAMpJx4SuMvs1UZ18cHkYykSz
GD7m0TuETxgQRqhEvxH02imH8H34J/wHiF3PPpBucTOFiJXMQt5YEE+VeyjzjwRsBvc4JkkiYX9Q
e4SeZ8h5NNCpyib2abA4DURPaI4hyEyvcaMFjpczQdirwqrewaE5c0ymEN5IM1pQNk1UQsvX7Q1V
sQU/OSulvtmck1kIq/9+kni/5fthHd78a0EvBlXBhBAzP8QzyHF1BRMWGN9ewpvdGRHWtqdnMAzP
v6L14K+F6aF6sr7u4ntweod/X057ebruORYxor6CkdqeI7UXf2+2sHdopOzRDz6qFVHVGrzaOILH
YqhmJp1i04UJ4iL1ZxIQzY4A99jALm5mvpwqEIbaHw0MI3kfBE1HKEvphbaDBu31tkl+r6ALPj99
D4NKBLY5fXWbL8QkX8T1skaolhuvhbkBYmZAUdLHALnUGoi8bEGSaTQjben1mXoKHw8kQ1KfZUGB
4OmAZOerse0c3kCbi5bmJ+kbbLJeTbVE0tsxwKGZRRhhgm88bhoZkG5zhUQOAh+l7+NAiyejxqQM
uumr6Ri8r2iUr7dfpgz8nGfiHwK/yxWydFZvLaGN/nEgjeHLvYXS8cDaMgaO8Jss3FiQskItPc5S
wivgqIUjvUZ5Uc5mULk5rnyXn9K8QivYl4VOWpjYtJcHo+SzQtBb8502CZ7+s/rd19PMyEGUsUty
rwZuornGxOMsSG5h1bWw8E46VttPD4Vz5qA4WZU8YcPmH5i19jfsnkU+Iz3uMSL7F7w01E9j8noQ
bXt3tCwFMVGfsH1gTp+Ivt9CE6LGiZ7dW+ZLjpO9ggRcv8CKV7iFrH0iFDdeg9Bpj/Kijg39vgTO
3hnOwqLWYnLovN+sRdiAk9DuLrp32haVuTO1p0V9GtTd+Kdn/7WkIpLVw3HeF7Vr5utihhLrHlBE
zzTq2jnyNgCcCkRbeJ+u3hROLIqq/jqxG1I3z098E4FxlmuqOPoilsPYzkYTd4xTjVHYSvqO/8m/
vZJh6R1Kutb/7XTXdzo13PQ0MiZUer0GjL9CbhRCBvCGDV2aZ+VMUbyOn1m278jeoVpZyiMX+8j6
CYLGieFZO+h1xNuMfHpGnC2VeCHUXcyKuxzaA24bPqJGRp1iAYPvKKBEgausvn2ntJ9tluKv6mia
Jdf7ftF8sdjFuJ3FVrZ8jibD0vu2xCJKArC61eXKCVzByzZdhwGnl4YCqB4Ct7zyjkwKQNDgWxSg
H2oQo8QoV709IuiuSSpr7wIieXOmSY02a/wWjxYyc7krDuWupx0Eku4aeJeQnSwusr90txvRvoLZ
0YdLGtEgQ/RHR1HwogyFVPxxJb3NgSRLBAZNppsC/X716I4J2wEhahLoOyveVFhs60LoSSgwfrXm
9kvqLG+WV/89g/U2BGg7e4siL6EgXX+5gytt3fsaFZimDwxkptkyIt6yrtwpQEiRt+WqencaY6/E
1jv9yAK0tkOIlBLIvugBhtAdls8GktgLSyck9dhhRPFE44qFeYEcIMNwbTXbIetEWAmBrrRTlmfG
Kv4xMUTDTcNNCRA+Rw9790mjSP/6aTI5MgPCNYvnrUaDKyoeUu390Nx6zOmWvLTb6p9IkR/6apBG
DjdU1zpQFliIP3EQtPnvJqmX3rRJbdW14wPdVY2rPgcYO48/t14i+DW2NAPk8WFiZ112HBg/WlgO
4Wb/03BF2rRcdFrOWexvokdcwzB5an9uUqeydFtbAzfbPAkTaoDhDhGBZXFwMH/kMQMgd01tkWR8
S8wJ3Q+3mgM1/MSSxhPK9ZLEc8fgO2YAXFqP8pSu8fJ7mAKOkAoXB77VIwKjO8lLKXq5cTJIIDvd
sx3K1QVlhhNODdufMJOlfU62OQ5FyWgxVK7lGP1uR/PH/Ds9QTH+/kEW159rJRMQek2HlT+JOQlv
3am19WSJMhGBqBKGT4lzh0K9SEtT+/fvFM4HEkLinJnkfei0HgCgBX+WiYyT727S66MmTm9qcCkU
FTjbde0bsZqyFVvWYckXRxC3/3oDCr9lRc6uOBMILLVPH2bFRpu84XS4A54Pyn0vTMHSJRWU+pp0
lpGl7TOsfqJ6oUwdBvCfjP7cNmjff6OL90aEA4wQaVBtK6AjM5gdPeWMwdxyfXvQfXfd0l2R8G8s
HXk1xhdXKmD5Zu9G/V7QZY9gaoPXlP8mwdXwzwllUrmpgXkBk4DkGzzKb2KakRWErTDZalVRhU/O
m9FzpgCXKdoVWWnuy5lRZRchKQNGDwpZgwJVrnhoQP8nzU/9NasB5O+DTNB5q9UJ734ZIfaWhDQ8
f66/33d8AozeL9ASqRvAhTeYX3LvYHQuUGmzo0TgJRSMuUbpa0JUAt7fCtA58ScX9Tgk1+bpAnvx
1c0AxxAoLWPI8cQbERtIRzZyLm7Z5vhI4YN5VJNiry7n3QO2pHke345zqMmQ5oCoMkXkaUUP2WwJ
uHzvG3k9hizRPA3YMlXbTzjHT4YKMsmCbHyiSS28JZRyokQUcPJWBuznk38Agb/EbVA8LlRoFeJS
p+OC1erZMxgJ4ZB7wR8luYyePMYAFgSG5S3UsFYMg3ayY+6zHMtp4h+wlk/JPjfMfO1G1p6iG2gd
/li/RnxbOIl73Yfvt8wrQQKFXoaasA/dOM/zvxCE/8xv//e9EhGNMozngJkqM/wY1rwmeK4PL4Fz
W6jkWS29nJBd8ypZPfglTYCI1djd0v3xIbOra4puIAFblX+K1bpsKFQcfliNshqoG0dcXFGxPG6O
KTIUIXdtY25HInOkyoY96QlKHPe7VsyFWE+em+21ALQw9wLLdY17tJAf7XhIortRCu+Dzjg5ombY
i1PnrlCmgsrV5u5oSOhoPCDFUTlc8LeZnjeR3DWGju/N6NLp2bUDVNZfUuxkL2rap9XsPlnc75wY
lXA8VQe0ykq+HeHRQks6g/ehxRrRDLpzdZf4AGN3K0WBo2MwtAuagrXc1BwZEkRv71HbkzT03C/U
i3xIMgA1Wmb1IbPQcDvujfpy3OMLJb4fHZ97IAawy+wbA4eiPLPa3EhZg/17JUy1HXBOeuNjox7x
UkZH8/QTHQ9imTL7kWeuuApUL6AIXvMGAOw7rTbXL04V/Hq0Tm5TiVdJOx5GQRANsSj9OFLRYTow
OqUz5uurEXjhjqCCfPJpcTvzkzvcJ1vxhnQF8rTPlQaw5Pkk9U1PupBJzl36Z1ICITmDX1/Hj8WU
aG7drTS5hmHZOwMtoCxIFCqI7Nc8RnM6YyzyLXbWARNArBCl/5SLoeLUnju03Q7cOlNx+GE4ihUb
So3inE4xfo5hp38eZVB/+lQ4pHkiAzL76TP3XBpErLEdbzCE86HPyQnzdLLK99uCWoVtG6jzf5g+
upknnQbn/J8n2OsHOMwFLvFB4uYaMhMAYxVzKMFFCObJGG8wfL7Rw+8sQ2qvAT9J88XQmJKSJXR6
v2GORPXScxsyzaQiK8U3edG0WD4Nu/LKvRQwPjVfN1svuUulEVTp3besPLGRAUc/yFVYQ+4WqGHZ
R/R01YlD7xoGxkVkZSLWBmKyPPZBRMGqLa3LyvRVZmbV2ZKjjcAumQJfQFAuhmUAbf/io7/LHA7F
SPWJNXhjiZXccGffAMwdGrQ9CzCSYl0jeLsMjvTlHkTrBJFxaGznEXRidwdovjT6U5BIf5R4Sxmi
tdp4xrK6hLUBV0SLBgd0dX8tMEW4NCerT/kZU5Csn5YwKCVHEq0aWqIr/BdV9TqJbBWNCkfHGTav
wS+BO3HfdAmvnal8NWxxtDabvh4XTeE1AB2GHLWp/nJ3oQEEPdu4SouU2icgxvWPsBAq7GdsdW/w
CHyc5lj1TiQIXxHC6QTbBpkWhx7k3ZOHUcyzb+NmaNIUcyw7/ewIjpGC3Jae+d5qb0YOQ/zV3KCK
cAIdk0vff0H6joOV3GXyzE3eJfEiPU7G5jIfzFtSnXbMjIlurYmtqwHnaNdx3/GB8plCFpl3y6CY
Gfjz4t0RZ+hYafCAGlRcdFMIDGIaCL3EoyvHeI7p/LUpMHol3+HCTps7nQ3j2eof91lJ4Xye1LtC
E6JEstNagTWfEhJB+KAQKXUrH0jjqoYlw2fwdjZuBUUjFX3Ft2sBNflIxWDPFBHWD3uwBoSG8fT1
Y7Km5P70QnhhgThYtbIVyR2U4jfyJeY5ItqpvqSTk5Eya3e7gNqWd7l90Ih8iTQ04hnYofq+tPRG
uEdcM46F7CGg4Dr7r5nvFbVilCFim9S9NkBW/ukGCNcp3zyHhFK5BF5I8GF0cV+sqvCyOvf+2HJx
RODL/u785eNBA/f9dV1fnZKPiRvI5hfSjPP0PZi83Zm9V2Jz1Tu2uSFHOy40WqUHF77F27EimUZH
B1wLgRCsUdPwuiErcA/vpPFD/f9b+8PI8KvwzMvAoAD/QIVGoeoVdbGfl8t8YKwBsAzgdfoI/MbY
naa+1dy646Ehb/KwfxpPluWUs4H62BPG+BrcXSSI6r649T9CvsmXbLXu72XLQ6Zlv4UqE1UpZHn0
cu0Lp0mYl6nrVlcuKqAVwrSYnPqO+Ip6yDYYn6udkbuWTMJ9B61e3MAUhV30cP+6uFBjlgIdo0As
yYUJ2nRyTqO5Top2MHdadVj5dPojtnrWZU4EyAH9+dUahkzndgji2RBmHSYNgan34NGnR6AUc6xb
Pwtnz10Dwji5wbVH/4lciauSKyTshyFF+hmMJ9ESO0F228LTVanwOdDAztdScUb9Kh4wXNkBSgkI
0IYuHzqhfo5PgV8LuYpJdwNdb60Z9sKnNtBjAKqliJ96h16PDnBn/1HnqV2hTpJ0ojE8EUtVvTm4
mbUxrDt6OvOiZ1zlfevp8DhBlWPG112RgaKqn47npWPHhDb+n9hLNgZ+kp/MaxbCSzZpUYvn12hF
4QXHRlhIF1nBvO6NwPdbY8SB+2P+Hn17JuGutJEDi65PG14Qpa8/i9JQlT3/AoKKgQQjEu3VuFZO
fIfCAhDO4eLVw0S44w/q+HJQQIfRD75Hoz1cj7IMVrrBGUiJB2JZQUtzZntRzraKDl51A8yUwvUh
qfJjxZUWR7WJoP0/Osav8bWAXNf38xbUW3zXs4Qbscxy+i+ZFKSlDwAFohv4uX57MHpcu0501gEc
1MQwFgiJev+SP+Z784RzFJ+23Cz+TeBCEVVk53oK8p3D5O43/y5DFhB/7g7jDE3hRO8x9fbjMLn4
q+k8tMTiGn9tUyaC/BiPsSOKPCmHQyPBffEnNFrSvPHZMMKESWselp3R3eZorpL1qlfQXP9CNw72
mqL2DPc2Yy5NpLrH8kq31c3SzZSAyRKsb6hq7+tT2EJ1C/IRGrYwGngMzK/Rz67MM5Hn9sU7/oRQ
4akVtaI70SSDGgM89ehSey2hkxYWgQh+G+MoktmywaIzL7LaeqL8Ld5d3yvX/66mFeRDhIkyGg+V
BAt4ONJK0nRyBIovv5/3HlqXG1vaQh0QrEnJeBljTG2P1IzI5p/gRB/SO5qpnUZz8MrDzF/4UYxY
sTfyaprQsfhF08r/EPCPis52+nxAXSYyo/dEjS/TydnHEZ+R5ZjnHbCNy7FUo4tuVUVgxeTjj5yX
iKp7MKRo5HK/d9FbDRl4PBhwsw/uwgnY1KYenhxbV52YAqM364WtxtgKN8ppGYSMSizCe9xHTtmS
jXW/Yd070wFlJg8drYNW357qi9aveu4N/sZtnVPdr0o3tI+zXjLUMmB9uFG7YN10Foympl0rUcbJ
oJGOXU7YNEEDjFuAbj0VrAvARG43bt8YLC38cpvLFFdZp7+i8DUkjZiuA5Ow6a7GAt+ZKo2B0gg9
k/dwITmapokzOSENxb9Mp1OIPrjbENVIzR601Ynf3mJYhrc+LESCYcLb8KDPEym2wnhlXJIoeUsP
PHU/Fa1kSsVB51+ZvYbCTcnz0hQWvaXFMLPlpDI1qDJDSiOgTdZiiyFi2W0aQk281R8PpAHuf5KL
dc2iElVXrSAoxAF/4kwzi6apDLdgWK1e8CvpIGD7OUNCHfaSHWoBCnnpdYJa6LCfjwg0pSJDT7pN
2vduN04ooVxInT7t2bc+/QRgCeGiuscpfjHNOyw5uaOq+KmftCQ4OG9NU+VWQG3eBPZIZLyFfA7a
RrNJxkgCwzg7QgHI6Q+iEI+q9YzayPLCo+zsloIjw6d7QwGyuRvNCOKRWcYCZsY06+ckiCnMQBO1
RGl5ETU2DYDp1rx9fQajcutmS1mpkcpl0B9lPMbcFaLV+S6JV9YGrOYwS40NpB/0bRNvjlpJj1NB
nTRSDcMqZpYYkqAumrMqUIbsB6ddZcrYVq5EK5EgTRtpGd8qKdFsKmWZKTZwzN6nPXKvtyqyVUX+
cWGPsA39Spwtl2TjBVOB15AjKl07i2d81fUPzzKHQg+1UkcK+fyechv36BkJn3CegnYwMJd//X3Z
ec0RzAeJBGag6tv3ch8iBEYbSnyKqxHIZidz4sPUl7b6icVy0cnJUE87nMWuD6SbZUrq7AgzUwAw
MUP2RjoqcttnTD9Kuz0+iEFz0GBtH/KeJLX35hYrjdvyNDvUcJxe934AWqjDuywSgGpumkoN5M0M
mNDPXCu4jk9O9j4ul5/MjhigSpYSJ2GEnCe7tm2UiXXtOuUf9rlQ22MUg6Bpulxq1LdIbAJY8Tx2
SH0EcYwIE79z1syfM0ZbRlXDIB/CE+IW5MXQmx+lwifaixd1omRKPKlt9FkyWNbfMUMGmGJHXQm9
yXvE20WnEHzUlr9nQXM17Heum2VptvEHuqpR7F4JvtMxeMeklYNTNOy8ohAn0F6nShY9EPTlserY
kox3eh891uU+nnAE7DRMxOCJ423NMzbhrrqVzII3Dgq4Qnk6f9yE4uiH7qAzWiJvvjUGiruZe+Bv
at0i+4plHgnlewU6nALn5P16H6A6oYnge+BIxdBSh2stSzqE7y4zkeNTUCjNlEahoOcHt7tLQxs5
fypVFVr2x/MMAEx2ebzgmuq1egENaf7G6h0UMVLx6kSxlGj/sObOFJReozyMQgHX3riHcQCxjBf3
eVKdJzTFYMktUMBgmtdPpmfUmgLnBQsUlsxTcph4TW9cmaT3iPKJb4IqW763of12WeiYgNP0ucec
X79oMCLrxOrwAD6RiWOZ9H7gnWEMN/Kfq5OiT2OkBq5sz5jjs/b0iuZJadkuxeYtW8WNh0qrF2gC
p2q7Xv5yWQEVZIJVBbhUBFRHlFk+U2lbrCTkG6rJ6m/Boaffu+PI6oRGXShR3wDrECGrOCO/4WPf
T+kf4ojxjhwyVJFmmFsHfLVDwZI4MCfyhZckGcK77A5A65I79hjZnuetEV/wW91ZW/5IlbGMEFXR
chVHGxWMKv08kJqadvHAdUhgXzogZ/jZ8I5nVt+3zFdZJ7nexE6YvlVaWH+sOjCerrX9im8F8S1L
034xaWZhcOfRU2gDSFcqDgjesShifsvLcljHgVcsvIwk5aMbcgo4Z8r6g9qY3IdBHTwGv5a6sOuS
3ORngHVk9IquIiy3Y58fFGqPlDsoBRd1+KAJz8CIzOGSs1e0cRPlIhp1i0IM50IFFr8TaB9ZXLkS
lZelgXv+jZ2n8k0HMg6luD/WVk0F139+8cbZZZ3Ek4NAsySvsMYcgCLFAyKg7jtXrjeNsw6kbm3H
y9fRUPK6+1MUPg9S5e7s/v9vtUxy3XJab+tfv38TyOXpskfYjHCAFTSbEavkhxra+bdkL5kZCzkr
ttV8m+CZAGtVabd7Y41ZaZ7CxylNS9u9dN3pdxud+roWPFwpyiIV7dV3LkSCN9nJ5bK/HBW7IE38
3DGMjXowjxGok1uemFoJjoz10huvXfhcYUSkOt6TBxtNhP0dHETss9ZiHOkDxDVWskK70kVAU8+H
MPgDZ0YfHXEdeVt/QvTFzBALrnduW9xOiMjQ6vzy8DQLOfctIs2+mvoggYOausjCtIYPi1kNGojO
5xjrOOxlLaTLgMUCbHmBdocuzn8Iado0XzAlTDI9rTeiMO9+uEc6vRQUd7aIx9r64n1O1wWs9Xm0
FzdO5WZN5vEfN3qlAjPduAQXECALvIp/5J6vQbv5gbRznJtXem2VFYRo8v3GnKJVN0/0QLWyqlRi
CyP2eHDA6KxoFOqW2bDCUYPrkDg2J5OiqwWvC+FTYOA4prstTPH22e1EsmMAtgqLDSBS9zfPo9FR
36uPDZAB2ndJdEqVJ+ky1DRgxKLHsmS5+RjOCUOtnZQK43CtceUj/moglbuzC7/30M3MD7uHvWHb
2ThiuFfljmpop7bFeaDyDu77s+i1h1uQe88=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
K3gmSOM7POFFC4Vp1wqdf/cLg+XFdquji8tynMaryJILZOozcHCJ8IbqNKWgRNMEfGkRM2IKYFsN
LRP6C817pg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
bgc2eKb8e8mC+Ugzf9NNufWY5ukUVeu8sNBuXX+VvLi2VCKfcf3/EbTbiETssKlazlqhEXTv2s1+
nLSgeAOQvsKkDmL6vWoF99ZY/TQhHgYMpSRuVYu/W0VO5yRCMlfOFd3J5FV0gEpYBeDF7QfHtlD8
tP44XxUa6jVzW5cL0vY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rAjgbHi5JFX9IZ8UdNgm2jLu+6hdXXnzmZy74gEMcsM2afVcE/vxipf6lcP3MG4z2i+EaLXX6pZf
jh34kSX7UYtVSFFtT8a3UxfX9uYvIUu1wDgKCcRNgnGwj35CE5JxC9dAhOddTbOTiw8vSEvUcg4L
TsB1Mxlbe2kxOuYzINWIcFpy8H+0Un5HAiFj2FXxf8GTwCiEQfGtb5R2kRKrQDxFu1LhtnURVitx
0D2bTp7YacAS0/1na7FAYgeadwKdc7mLjY7wv+0QEak2UsmYNsjdlVBoF2vW0IY1rD48azik/gky
GIL4tYgd0YqZtHWyQrBOsM38Z43VNKB0OGykzg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
2rwaGoQVBHpsVMi+VvJ+TcNYf6llQroavWPRdy680OGFIjv+Y+tlxOfqnqj7BD9BYfNn6PqoBSj8
UaRlTYK78WKFJcSSOkMUwQJkNuYjFpUVrnjSAmnaU3u/SfrqQ4eTMwTapwDbrc4qtKG5nlHj12ea
/7AMCgF8piF8Jf1kTCQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
drxCTC0qG5mm+tXdqjy3tcDXmIxtaglEAH3R2X+gDx3cCCwNYdPeCJWZrBioWo38u7rDw7K/6+4h
TgdQQwGFEZa37VPCDg9Frm4ZAAkUWLoa2prtIfoneHNVWIrUk94S8N28EL+B+g49xcq4suOn+OGv
gqNpbQhFCSXD/Mv/31oa/qOERDeXIxfmZo4nDIvZm6Q0ELswuYX7/cyxOxyjRPinhjWw7GY1l5E8
IaUHclQ0R1bZzuLRUEZ7+/tqE/6GlxyIRHUv0uafykZ0WSLiOBG5fFJ7T2+hnmovJoZRpkhyhCZa
CYvFA4xhe75T3lgbgCeyfJs47UZ/tAtfPqU5hw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12224)
`protect data_block
tq8Yf1MfsjaegmCxm7EgtgYvbd8DhPzhjDmYQLWbfOhwYLBzb1geWcSL6aEl8K1bBQnSOdD6CDqw
JNnX4HOxChnJ4poEi8eCPHVxAkXtSM4sMmYoO2viNhZngBzUkKS99Y6xk1MCMyi3hBvD+W2454QB
/PXcezEXjG3tUV/CfzPLaDYOouMAoyWGWRpfAOmbaQAmHNUfSZ24fUedeqEyIdSczlk048VUE4Ie
Yw01T9nPZ1sg9FZ8Iy/RLQdZt7N3uwu1GrJdhRcLzItDtM6TEbiiLtdwwDcHQMfFqIPGSdMlQZkc
Lp+qlMIK1eTsFbpr0fSqS5IxBACYyldd4HQ30bx00n91+cdtTEFyejDImCFI0iZHSLSNRVtqryGL
5c2MlWmykSqSrbiiZCaX7MbMnDi1eVi84w849Rc+1JRWM9uNI4Rkvtn5Yx7+LBqY70bHx+WWvnb8
Qa+riHOci5sTRmQVaOv02qu5Pta5O8C08t+rJ+jEPHxTLI/STdNbkn7u/XuMR3w5xUB4/JxT11Ry
5sUmFMBMfgQN6vB/Al51sQDFszvSSGQkgZe2n7NPZJGwgP0yIDloVxE4L3lAuG1N4muCT4T/nrDS
I7Oec2LMl0bO415te6uBT/EU+zmKI6FVjepwilADKs3JPKadhVLNsgIh9Z2VuLVuVUU4Kqp0NpNk
tbNO4TlShZ9tVtl1AYccv0lDUWsb56ir85kZwsSbJwbULQ3Te8rbNtCD0/zFG9l5e+crV1OEKDCe
hgNncILgNguooonxHLgP7XPVs8EUcPuYITuWa9aVKdbV22smOOzdXZQ87XlQyoVSiQ/SH/F3AV7+
LRgVYtXpEfky6m9Zk77tuP+WIX2xUXVE5nhlmyxZ2/zidXObZupHjqabBZQx3xa5ve1j78UCWqHh
UqzvhYVZJY1pMtZUxw4CSbZTggrhAaLQgWJ9ufZoBqmuDy7Di77wevWhy670RCjjmGD+573ZQ83i
DHb5hOIPuHJnPgjB7Q4L7ju8FK2neQ74M3k23zMfuy/81fPMrqp/E1rmto8awRbzEmzAZVHMRYFK
fJYgf17eaEYoeu1uWyVP8R991wsqUmHs5p3IC0aLKAF+Kbx/x2YYHF39/CFr6k5QF0fV+QRuWHTX
rlEW4cnwZxyDIv1PkkPmM25B8zx+UX3MzMmvWJu6ARHhj0xuAaFQ/Xk8eBw+72GJYohwbKTHy4vT
E1paOUvb3i+UFB2eis3zl7YhOBWPURxptJpqabcIpJ3T4S5lswKVrNMbnFGJWoroFWTI3gxaHHba
pXUhaSENhxCptdSh0a7gi08zomGtjTaVDqaRZvctKL6Q0zEkeiBU/qEGIQPvi6LmzOj+3jQBSp9N
le/2TOXQyNouE+FBN1rxVZkUsbfFA8O1W3OeiFddaKmb2f1FIlvhhvR+DnoK56X4wgjpU/xrX1c+
g7BV1gL+YdvAqzEvOq1UtGlM+xGP2JK4gapVEACDJmodCeTPiLguRjklF0VZxMTd9gH7fu7FaDQV
N4L0k/KWlWg06Z6BoQ5wCeDKUFnNslW6+/TuYAlHCRx8wBtdfND8DmHSUAApx9TkJQfawS2jNX6D
hQbWfeo9F0FTMv/DAuSYbTHcOuHkPacXSD657bkcdvICvHV8textYNFWvqxcwit11uHxNC1df5AF
ITdX912zoLkp0wLOP36zf9OUHavSJlDMLci+a7ukh+oFkhukA1McsTlcbYji6MjevKB6A4bH5MLE
JbYJ6vRT4rZmUndepTV+QDQFW+17OA9/hjGi1Le7vyYqc3JY82I2o8FqF+H3mMiaVNvlxiijnfDn
mF0uv1gzJ/+uBucI72miJRcd98UCFYIQOuY8GUVVvqtPx9M2rqiYZN6zu6h1kypdHhMdEWtb87F7
lJ15wnvR7E/87JUmUUawq9FS3DgKokJMHLZf++vOBDDrqG/fIKW+n/e1vv1KTPk+rRMk1RDTPUO3
75y0bRMiGMOypkNJ8iNBw7IUl37lm0H350REGbCJq8y938nZkGg1HMuw/lF7iwO4ZCbdflzspauz
2D8axtrnt7uYVerw9T9huePwnPWKldI/WmRCwcA/busiR8tphv90A+kNyJd04JhBXo60JXLVYfn1
ASvsiqkpGiCdoIm5sB4HMIBKJQuwwII9EHLkYSGI/Unl9UsLGT2XbJNVudmkCb5Oz0+sYcas9BHT
zOe8GUSR/OlLLpg0VmOg+osBebyS+LON7ofVJqX28u0+OXg6Y30kngHA43SqOO1W9Zitkg5JL/Pn
kkk1Ph9M2PTgFeu+ov+h3nJQzGwc5zt/8snUzx/jbefdCW9icLW+OA9drBDdFKbnBdAb5Cd+6v1c
lHF1YnJgVQi33Q8SFgGwSKMxDwkng7tenBHxNJESSifZlB9tsWqkYdUzV4C3gO4E5Dyv70QRH9B6
aUdQeT2Pk/vOkvJFXq7vmEHn5FSbIes6UArPAkj5zcBFQww8hT4/BrRVgBc2HP+03KFqIY1dx77B
gn/kTWDZgo3qxvZTjqFSeeym50/jjaE9iCdRG/znRhpwlEmp9j4ZAr0ss3q3DuodqrQY2vnzvMH+
ML0QdAtMZ9o8/s2jpPZSR7HK2+YGvo5whMBNiaSE6I4MXATpBky8YkTdJvpZLyOn2+ux+ok7j8D/
iVxRdvcwha3T/pEk4LNNXnVj8xB0qHpHBVNnj8tsFm6x+cCatPEJHOs2shrvPpdNWEDgqzeUrWOI
bF/y/K00WlzXdRc0O7imEBFDTP64bw8GADPItEf+B+IikZm3BWSxsA2foe+j7xOygDhHzMs5auoZ
GWD+grZGAlHT1nH6Uj/SQ6KbY1+hWuiMupL3lzdLenj9clr48+GUBTfKTb5itZ6wEmwgSD0HF3Sz
jaq0MjmrPjwP258lJjYBkeOPUORxlRpgP7w88voqIi/h+2acoiOAEg49E2ddcWe+8GRlhEbCLQQA
0Gtd6IyXn3g3wNS5FStwnzvkqyhKUbOFt1SCq8MmwdcTMW4aHsPD0YfkAPslfZPQ4NFch0BNwVJY
h8wdHmKt/5R63gPvFPUSakUIsPkKYuuAEz8Vg7O84Mu8R/xYsn9VBwBjnFf6hcv8WBy385daV2JM
xg4nLasLimHnQMJLlVgpNhW3c3pVbydIJRu3n/UGHCHvzae4OULz0rmCnwRByHk5T6ksIYKf0X20
5iukvSTN7hb6Qt3oVuz12G+dkLlg7JGCiwJPHSLEqkKIjx6yLqNnuHWEknGI3GpPYLffo9tezgLZ
BJztjNkQqbI7v0s15CU+M/djjsWaAA4SkZ+w+TbPRBrgvqvPjqVT2YZ4RwZIrymYZhcG+HLwkk8I
qeAVraGbN/lCCBonsjOob0UsuH2+MHeqNHR9fwxZNT6QtmVUmfAXfZz5hrrTe0/XA4giW69c5vbq
6f4G39wfbGukzuCIue9rkkLVQImg57j2SkcSGDGhE9U1M2j2Ml5AuvSR509GIZwl43ZCwaHqa+E2
wW29ZJzn4p4A1W6zMBxpPbB5JmVwtGW31J36rkIxGiqZV8+y8UlIE/FcCImfzaClsMT50HH51qxj
yFsPLGoOJRUZIM4Gx3dn781wKGZlTeY/JVzWDl6g/Ln7Se7SWA1kkR8xdnL1sUUutCry4ThZ1YNC
+ZTc65arGz+YGLZBHGPxu2GV2w57V/FZM+FRWaE4PFjuywlp2Vn0g/QJ8u7EW5NRr5shLzTbAsQs
SSN9nwEInGR2iHezGk1Qit78J0woa3HROyfs6d3Sn2nGYFsMcuh9LjWCkvp8pb+TNwHA/0gXFFvJ
xCJs4mz/yCcofJaQjda/m24N3FzyBJH7pWr8wehNnUsUbEsy/9OEHrPc0ZPR6MEzeISSgbLr75bf
3JXCpNCI2uZpqS6ggqK+jwE+ycyQW1OFNKigr29wkbGni9atYUHYO6cNt0QQsZGcpMo6J3dnD8N1
OFwwXGHhKrIdk+UDQAYjoZAW/M3ET4xKBqISeGKrjx7DKW5nxUmCMyBfrAgNKrktYZdmQcf4tk2H
AEjjBMQDa1iXpNW/cCGXe8CIE1bZeRH1ldGLZ3QVis2mtBX7w9Q3mWcmZ0zPgi5rAwwNXO0TM9lt
PCBxuOBmuSzQTsrP5oG26dijNyK1TmUnz2FHz8s9G/EJiXdLflBJR27xW62pYCMQ3JS3a/a/p7aM
epsQ/VAyhA1t8d9luN+D10O3g6hwlnUzaweai6IlcHo8KHi0880adI0d6HOZcy6nkiozsS6X4Cbw
sVbh6fBzE9oubhNNQB1mRat8j0e+apaZBucXofuWALsmmA2n7QwZ3I4+vTH/UBoRnQyvLrNFDtKT
soqSr+DcgiMsTbl8VgppwdNvtNtHsN0QEcV8+Ou9X/T1AmAyim+ecfN8dYC+VWU4pt92K7VvDfuE
wuyFtk3yIQPVrKCdedalT1Sy9isZzfw6fiGpKyHSzaWsrmhlGyqLM50jr6CD8WEpT51mkM+JgW04
NCTkZArkSRjUQNcpupmftsFJBUYhftSW8V8ouIS0EdGptLNsQUo4hcCeFDyo54JzV5uKq7XKiXm3
eV4YJvdyW/r8q/LS0jAUS+Df1S3oUKsvef3dPreiygv4X0Grh9KLDV7L+OeyDC4Y05YSz39K+oOz
fByQs2sgb+mYrb1BGvdq3RxjnCoCCtKr+oALubZ01YCA8cLgM0H8Lwucyqab/Ul1d0GD9++/fN42
JfM2F0g7VDCedHFkMHYcRSxV2aGHTiPXi2tWrlC9u9Q6jG8itjhXVxsZT4yn6KwhfmhVeCL9MxuL
JSPUAnlZm+oCWrA3zhuJX7aT49EVkBxBJ/knkc/brlqt1wrVxNJ7OvunfS7XE6KPgCb7ipbVQaVk
eTXuJ2sVB86SxGT6xibUqNKHVe9a+5pohnwnSDaHzPMrmcu3Odi69YskgmgF/W95yVjRd9+Kvi1+
9UAmJYH/gjL5+bWBlc8ddmmujaQETBExisrvmpmW/8nq6FGjAXmyz4O46tQIHbCiCH7ypdoTUq/Z
xYVNtsJujD00+HR7cCJvOVZF1TGr1yCGUGOwQsutXMyjXhd0N832zUxEtOe+NCn7D4sV+3/aQZQU
1Pl4CuVmR+HMlMhQRPGhvKH+dLVt5OW6vgB7JU58DVfxKImBG/BeiH3NJLdHIwkggoJgHpsazT2p
5mp8+1Vt/DgRx9HrNQCd/OJPxarrzHSSYzz4S8AM+uHwQGeMgHCOu8QG4ZQavqlo+e3Q1roBKxrJ
KquhFXDp17kHs88BJPlhI2snacVcLip4ujAowMQvJIh2ey9ljBFirqULyz2emTida/Tu+xQhSAmO
BZ1h27iA6bfIQn2PXVaPkcinxH7HivsA8AfrusSDNWooSZAhbBnKAgGYg+NfXrZBsc7rie2weEMn
EQeXhfjYVr8vBTrnArnJT7NNi8QIPHNJp9zO0sgX0IkbNqALIWufGrDSCWV9gchEdZRvp2wHym0D
fs1WvNQEiTn3rDZaGeWtpBwwmNtAjoSAxAJCrz9J4w4UX8FmAdrEkXfphiBabRbdq77js2uPyob+
vv0VRvDi9Vu6PJ40wVmoMbKXlHWJt+ax7hDZsnw4T7lhOPvBYmfeKvtZMaud/gdLK4CQvLEHWDPp
6cGTWO7hyhqEUSdvS6Ffuhb/Sfceib5IDM3Ri6kaD+6jS638cZZxVmPO+rIAH2VHElaMYE+IG68Z
vPhwuQtJr78o0fKDJz/b/SOk2Crk2BJeiRzTEb4OTR+MAsGfpAwJhFdOh05zAIFz9QIalfsNfZFb
LVjTbRcWUksl1JMqiN/yJj7eBwnVPK68apzSK/BR4dg6gydtgY3ao+/os/65Z6RAjJ7EQ++qFbBI
yMq1aMqkHSQruv0h8QAlLWLteTPATbjQDpQ9T6SRr2QDJtV8CfsbDyoxrGpPb2L1uvk8HDb21nV1
DPBQawwJZtX2ddJjEAGlzAXCI/7enwdkLnZ6TA+kH4Ixg+7wS1LFd0z1caBSeio7uWq2dZj5cxQg
EeLOMXuVmbTmV4wjwt7yvayN0yZSRGJaZNgsirOO8QlBbcxtQ6fKl9rxZP2L4uL9ppQK12TiGYPN
ftk0CuIpZ4JqP9oS2XYBI9IGXKoOk9xKfHLHBi8FzyxQ/RUD583laqwpka4ateAlXi/CED/AzoRA
QsFYHyJTtcc56tT/LaWqbQPOW8QyNU0ZcyRYb4lzyoxW2AcyMwGDyc1057TCyfp5RDTzqC23yGta
+AfbK7jFYTraOVQbZCZRbyowdWZijIuT1jwM24fK3XHhImLG8SxUmD0DeqIzvEPEahmx8AykG63h
clbBlUyQprpbPMoKismt5x97Sf3MDl+iUFcdkdioOQkQYcuzsGMpy4E3yf6pKbDAzuLSil0wsOQ+
K0XfBpoMTTPjguX+bIrl/EsfWLX6OWMYZE4Xchoa0myThgC3ehkedWwBm3OAf///030IqC1t1N+M
+f29daNrbnZaNRyaYBH3oa91vKTIiQ47kcjlUx7XdfuxCezycVjRrQpyd1HWedrfmhhZrswzy2mq
mygKdjpRejG4f7dotHH36S447D/pKE3gGTLsAj/03e8mGtlFU7nSWuvzFiW5RJ0w4xoSkygG/8Cq
LgM/kP/2+iBMUbd2MgPcnbrYKz62cByg40hBUbuZ8q+Tu9/WEQ+oqnNc+wA59fbOhF23972Y9L1P
MRxI6jU7xmXDORpKsEGXC/GEaR9JflY0fv+tiWcTU4xZvQ+Sy8Lxr0sjk176SWtCzsvrHBu7Qw7k
WRL+zg1rnKsw4JQLnWN1uGe2PEe8oBRSbEEImwkfokjy9XEjYia6Ygdx/sdSWkKqUI1dndpCSow9
E22aZ2J4ZfhbP6ATLZLjCyz7lgLMLb9NXqtZCd1jVdk5EeT0Nt6Y3Kdmj/tkclHTEe6U1QbC52uS
wCJCJs7PpVq5IEPeROgb5Gfa8rZKUcQQRDoYneZWbXz7d1hLJkjjgNr/5RF8fqNto1T5NhWcVdYk
ududmXmJvaxEWmcpll02Hx3roAOtvuAzhXGjF8IMEEcwEA+xJU8xv72pfev0Nt05Qc/utVyc6oxE
PEQBJZO1t5b7jfUSCLWzrn3HuyD3K8wCk6A6pl2GnR2BGIxh158YUEI0NKsTJVdLHY8Kcu0uBnSK
wjrv1IGKxs+qA408Lozfz4V3B0Mm4JjLqrF367wDaouTdjg4uk05zGvWeqUcHUYnt5cI+3VzWRoU
D22jDcRaYL80vklHYtgKma7EHrIiIr9wJAEyHHCyt7boH7hToDB52EWak8z2YN0FrotJacLpiXCX
ZCDszoWTBQ021z8XStwt6ce0IZLQ4FpRINCDqH5Q+t5nGu70iH0HVcK76gIGai7P0RccJnbLayfH
TE6tKnxQF/acln0gmZsFuRwXSo6skO/3VZ98TftTo09xQfK/4iCojdXIwYllJVm+saMSdC6cNkQh
h6xrIa7d7ZtNwjDATTKKg+4qDxFsLBC+axgzvTii3i0y6a+P7CfzXpW70/Kw5V+KyMlm9/nUo1oo
ueSA5OpKYLSdM+7Yq8F1kMmnV84sliPHzYej6oZEy6Gbv1mkBfeCKpNZpeo0pzVsOlB7buSSQTxu
JCNiWBKHbl9cORT1jLmZSHr57wmr7LZN0i4GAnuxYEilpAMFU0vi1MHJFu6mf9N6tUqDRXFGFkQl
lo72N51s2GsrTqAMwIKrPH0NvxsE8FXenetcv5mCDN/auT8l7Vet3W559ALdbuqP9IBALk+plm7k
u8A8rEZZ3wS+ZFqhYI0S73SLoUyF9vwzxpmQSjopX+lVLT7l4TpJ9f1K5avCtd1scikjIs+T3FDJ
nEb4ZECFjSOgC3ceKkLNAdV27R979bCbTAf+Uo7PJsQyzP86Dz2gO3j8TVyTeML30pwZPz/mr4KK
ZNC8DGbyR/IABTTXFm8W3v/YHLgDfE3VyE42w0UJaHvA7y9qIOrn2PblTrJoeiJKWTqM95pvFg84
K5+wI8+AfgUJ6PzSVly5/lCPDSn/XjMqnU2vDS43/1WFNCH54SefAMpJx4SuMvs1UZ18cHkYykSz
GD7m0TuETxgQRqhEvxH02imH8H34J/wHiF3PPpBucTOFiJXMQt5YEE+VeyjzjwRsBvc4JkkiYX9Q
e4SeZ8h5NNCpyib2abA4DURPaI4hyEyvcaMFjpczQdirwqrewaE5c0ymEN5IM1pQNk1UQsvX7Q1V
sQU/OSulvtmck1kIq/9+kni/5fthHd78a0EvBlXBhBAzP8QzyHF1BRMWGN9ewpvdGRHWtqdnMAzP
v6L14K+F6aF6sr7u4ntweod/X057ebruORYxor6CkdqeI7UXf2+2sHdopOzRDz6qFVHVGrzaOILH
YqhmJp1i04UJ4iL1ZxIQzY4A99jALm5mvpwqEIbaHw0MI3kfBE1HKEvphbaDBu31tkl+r6ALPj99
D4NKBLY5fXWbL8QkX8T1skaolhuvhbkBYmZAUdLHALnUGoi8bEGSaTQjben1mXoKHw8kQ1KfZUGB
4OmAZOerse0c3kCbi5bmJ+kbbLJeTbVE0tsxwKGZRRhhgm88bhoZkG5zhUQOAh+l7+NAiyejxqQM
uumr6Ri8r2iUr7dfpgz8nGfiHwK/yxWydFZvLaGN/nEgjeHLvYXS8cDaMgaO8Jss3FiQskItPc5S
wivgqIUjvUZ5Uc5mULk5rnyXn9K8QivYl4VOWpjYtJcHo+SzQtBb8502CZ7+s/rd19PMyEGUsUty
rwZuornGxOMsSG5h1bWw8E46VttPD4Vz5qA4WZU8YcPmH5i19jfsnkU+Iz3uMSL7F7w01E9j8noQ
bXt3tCwFMVGfsH1gTp+Ivt9CE6LGiZ7dW+ZLjpO9ggRcv8CKV7iFrH0iFDdeg9Bpj/Kijg39vgTO
3hnOwqLWYnLovN+sRdiAk9DuLrp32haVuTO1p0V9GtTd+Kdn/7WkIpLVw3HeF7Vr5utihhLrHlBE
zzTq2jnyNgCcCkRbeJ+u3hROLIqq/jqxG1I3z098E4FxlmuqOPoilsPYzkYTd4xTjVHYSvqO/8m/
vZJh6R1Kutb/7XTXdzo13PQ0MiZUer0GjL9CbhRCBvCGDV2aZ+VMUbyOn1m278jeoVpZyiMX+8j6
CYLGieFZO+h1xNuMfHpGnC2VeCHUXcyKuxzaA24bPqJGRp1iAYPvKKBEgausvn2ntJ9tluKv6mia
Jdf7ftF8sdjFuJ3FVrZ8jibD0vu2xCJKArC61eXKCVzByzZdhwGnl4YCqB4Ct7zyjkwKQNDgWxSg
H2oQo8QoV709IuiuSSpr7wIieXOmSY02a/wWjxYyc7krDuWupx0Eku4aeJeQnSwusr90txvRvoLZ
0YdLGtEgQ/RHR1HwogyFVPxxJb3NgSRLBAZNppsC/X716I4J2wEhahLoOyveVFhs60LoSSgwfrXm
9kvqLG+WV/89g/U2BGg7e4siL6EgXX+5gytt3fsaFZimDwxkptkyIt6yrtwpQEiRt+WqencaY6/E
1jv9yAK0tkOIlBLIvugBhtAdls8GktgLSyck9dhhRPFE44qFeYEcIMNwbTXbIetEWAmBrrRTlmfG
Kv4xMUTDTcNNCRA+Rw9790mjSP/6aTI5MgPCNYvnrUaDKyoeUu390Nx6zOmWvLTb6p9IkR/6apBG
DjdU1zpQFliIP3EQtPnvJqmX3rRJbdW14wPdVY2rPgcYO48/t14i+DW2NAPk8WFiZ112HBg/WlgO
4Wb/03BF2rRcdFrOWexvokdcwzB5an9uUqeydFtbAzfbPAkTaoDhDhGBZXFwMH/kMQMgd01tkWR8
S8wJ3Q+3mgM1/MSSxhPK9ZLEc8fgO2YAXFqP8pSu8fJ7mAKOkAoXB77VIwKjO8lLKXq5cTJIIDvd
sx3K1QVlhhNODdufMJOlfU62OQ5FyWgxVK7lGP1uR/PH/Ds9QTH+/kEW159rJRMQek2HlT+JOQlv
3am19WSJMhGBqBKGT4lzh0K9SEtT+/fvFM4HEkLinJnkfei0HgCgBX+WiYyT727S66MmTm9qcCkU
FTjbde0bsZqyFVvWYckXRxC3/3oDCr9lRc6uOBMILLVPH2bFRpu84XS4A54Pyn0vTMHSJRWU+pp0
lpGl7TOsfqJ6oUwdBvCfjP7cNmjff6OL90aEA4wQaVBtK6AjM5gdPeWMwdxyfXvQfXfd0l2R8G8s
HXk1xhdXKmD5Zu9G/V7QZY9gaoPXlP8mwdXwzwllUrmpgXkBk4DkGzzKb2KakRWErTDZalVRhU/O
m9FzpgCXKdoVWWnuy5lRZRchKQNGDwpZgwJVrnhoQP8nzU/9NasB5O+DTNB5q9UJ734ZIfaWhDQ8
f66/33d8AozeL9ASqRvAhTeYX3LvYHQuUGmzo0TgJRSMuUbpa0JUAt7fCtA58ScX9Tgk1+bpAnvx
1c0AxxAoLWPI8cQbERtIRzZyLm7Z5vhI4YN5VJNiry7n3QO2pHke345zqMmQ5oCoMkXkaUUP2WwJ
uHzvG3k9hizRPA3YMlXbTzjHT4YKMsmCbHyiSS28JZRyokQUcPJWBuznk38Agb/EbVA8LlRoFeJS
p+OC1erZMxgJ4ZB7wR8luYyePMYAFgSG5S3UsFYMg3ayY+6zHMtp4h+wlk/JPjfMfO1G1p6iG2gd
/li/RnxbOIl73Yfvt8wrQQKFXoaasA/dOM/zvxCE/8xv//e9EhGNMozngJkqM/wY1rwmeK4PL4Fz
W6jkWS29nJBd8ypZPfglTYCI1djd0v3xIbOra4puIAFblX+K1bpsKFQcfliNshqoG0dcXFGxPG6O
KTIUIXdtY25HInOkyoY96QlKHPe7VsyFWE+em+21ALQw9wLLdY17tJAf7XhIortRCu+Dzjg5ombY
i1PnrlCmgsrV5u5oSOhoPCDFUTlc8LeZnjeR3DWGju/N6NLp2bUDVNZfUuxkL2rap9XsPlnc75wY
lXA8VQe0ykq+HeHRQks6g/ehxRrRDLpzdZf4AGN3K0WBo2MwtAuagrXc1BwZEkRv71HbkzT03C/U
i3xIMgA1Wmb1IbPQcDvujfpy3OMLJb4fHZ97IAawy+wbA4eiPLPa3EhZg/17JUy1HXBOeuNjox7x
UkZH8/QTHQ9imTL7kWeuuApUL6AIXvMGAOw7rTbXL04V/Hq0Tm5TiVdJOx5GQRANsSj9OFLRYTow
OqUz5uurEXjhjqCCfPJpcTvzkzvcJ1vxhnQF8rTPlQaw5Pkk9U1PupBJzl36Z1ICITmDX1/Hj8WU
aG7drTS5hmHZOwMtoCxIFCqI7Nc8RnM6YyzyLXbWARNArBCl/5SLoeLUnju03Q7cOlNx+GE4ihUb
So3inE4xfo5hp38eZVB/+lQ4pHkiAzL76TP3XBpErLEdbzCE86HPyQnzdLLK99uCWoVtG6jzf5g+
upknnQbn/J8n2OsHOMwFLvFB4uYaMhMAYxVzKMFFCObJGG8wfL7Rw+8sQ2qvAT9J88XQmJKSJXR6
v2GORPXScxsyzaQiK8U3edG0WD4Nu/LKvRQwPjVfN1svuUulEVTp3besPLGRAUc/yFVYQ+4WqGHZ
R/R01YlD7xoGxkVkZSLWBmKyPPZBRMGqLa3LyvRVZmbV2ZKjjcAumQJfQFAuhmUAbf/io7/LHA7F
SPWJNXhjiZXccGffAMwdGrQ9CzCSYl0jeLsMjvTlHkTrBJFxaGznEXRidwdovjT6U5BIf5R4Sxmi
tdp4xrK6hLUBV0SLBgd0dX8tMEW4NCerT/kZU5Csn5YwKCVHEq0aWqIr/BdV9TqJbBWNCkfHGTav
wS+BO3HfdAmvnal8NWxxtDabvh4XTeE1AB2GHLWp/nJ3oQEEPdu4SouU2icgxvWPsBAq7GdsdW/w
CHyc5lj1TiQIXxHC6QTbBpkWhx7k3ZOHUcyzb+NmaNIUcyw7/ewIjpGC3Jae+d5qb0YOQ/zV3KCK
cAIdk0vff0H6joOV3GXyzE3eJfEiPU7G5jIfzFtSnXbMjIlurYmtqwHnaNdx3/GB8plCFpl3y6CY
Gfjz4t0RZ+hYafCAGlRcdFMIDGIaCL3EoyvHeI7p/LUpMHol3+HCTps7nQ3j2eof91lJ4Xye1LtC
E6JEstNagTWfEhJB+KAQKXUrH0jjqoYlw2fwdjZuBUUjFX3Ft2sBNflIxWDPFBHWD3uwBoSG8fT1
Y7Km5P70QnhhgThYtbIVyR2U4jfyJeY5ItqpvqSTk5Eya3e7gNqWd7l90Ih8iTQ04hnYofq+tPRG
uEdcM46F7CGg4Dr7r5nvFbVilCFim9S9NkBW/ukGCNcp3zyHhFK5BF5I8GF0cV+sqvCyOvf+2HJx
RODL/u785eNBA/f9dV1fnZKPiRvI5hfSjPP0PZi83Zm9V2Jz1Tu2uSFHOy40WqUHF77F27EimUZH
B1wLgRCsUdPwuiErcA/vpPFD/f9b+8PI8KvwzMvAoAD/QIVGoeoVdbGfl8t8YKwBsAzgdfoI/MbY
naa+1dy646Ehb/KwfxpPluWUs4H62BPG+BrcXSSI6r649T9CvsmXbLXu72XLQ6Zlv4UqE1UpZHn0
cu0Lp0mYl6nrVlcuKqAVwrSYnPqO+Ip6yDYYn6udkbuWTMJ9B61e3MAUhV30cP+6uFBjlgIdo0As
yYUJ2nRyTqO5Top2MHdadVj5dPojtnrWZU4EyAH9+dUahkzndgji2RBmHSYNgan34NGnR6AUc6xb
Pwtnz10Dwji5wbVH/4lciauSKyTshyFF+hmMJ9ESO0F228LTVanwOdDAztdScUb9Kh4wXNkBSgkI
0IYuHzqhfo5PgV8LuYpJdwNdb60Z9sKnNtBjAKqliJ96h16PDnBn/1HnqV2hTpJ0ojE8EUtVvTm4
mbUxrDt6OvOiZ1zlfevp8DhBlWPG112RgaKqn47npWPHhDb+n9hLNgZ+kp/MaxbCSzZpUYvn12hF
4QXHRlhIF1nBvO6NwPdbY8SB+2P+Hn17JuGutJEDi65PG14Qpa8/i9JQlT3/AoKKgQQjEu3VuFZO
fIfCAhDO4eLVw0S44w/q+HJQQIfRD75Hoz1cj7IMVrrBGUiJB2JZQUtzZntRzraKDl51A8yUwvUh
qfJjxZUWR7WJoP0/Osav8bWAXNf38xbUW3zXs4Qbscxy+i+ZFKSlDwAFohv4uX57MHpcu0501gEc
1MQwFgiJev+SP+Z784RzFJ+23Cz+TeBCEVVk53oK8p3D5O43/y5DFhB/7g7jDE3hRO8x9fbjMLn4
q+k8tMTiGn9tUyaC/BiPsSOKPCmHQyPBffEnNFrSvPHZMMKESWselp3R3eZorpL1qlfQXP9CNw72
mqL2DPc2Yy5NpLrH8kq31c3SzZSAyRKsb6hq7+tT2EJ1C/IRGrYwGngMzK/Rz67MM5Hn9sU7/oRQ
4akVtaI70SSDGgM89ehSey2hkxYWgQh+G+MoktmywaIzL7LaeqL8Ld5d3yvX/66mFeRDhIkyGg+V
BAt4ONJK0nRyBIovv5/3HlqXG1vaQh0QrEnJeBljTG2P1IzI5p/gRB/SO5qpnUZz8MrDzF/4UYxY
sTfyaprQsfhF08r/EPCPis52+nxAXSYyo/dEjS/TydnHEZ+R5ZjnHbCNy7FUo4tuVUVgxeTjj5yX
iKp7MKRo5HK/d9FbDRl4PBhwsw/uwgnY1KYenhxbV52YAqM364WtxtgKN8ppGYSMSizCe9xHTtmS
jXW/Yd070wFlJg8drYNW357qi9aveu4N/sZtnVPdr0o3tI+zXjLUMmB9uFG7YN10Foympl0rUcbJ
oJGOXU7YNEEDjFuAbj0VrAvARG43bt8YLC38cpvLFFdZp7+i8DUkjZiuA5Ow6a7GAt+ZKo2B0gg9
k/dwITmapokzOSENxb9Mp1OIPrjbENVIzR601Ynf3mJYhrc+LESCYcLb8KDPEym2wnhlXJIoeUsP
PHU/Fa1kSsVB51+ZvYbCTcnz0hQWvaXFMLPlpDI1qDJDSiOgTdZiiyFi2W0aQk281R8PpAHuf5KL
dc2iElVXrSAoxAF/4kwzi6apDLdgWK1e8CvpIGD7OUNCHfaSHWoBCnnpdYJa6LCfjwg0pSJDT7pN
2vduN04ooVxInT7t2bc+/QRgCeGiuscpfjHNOyw5uaOq+KmftCQ4OG9NU+VWQG3eBPZIZLyFfA7a
RrNJxkgCwzg7QgHI6Q+iEI+q9YzayPLCo+zsloIjw6d7QwGyuRvNCOKRWcYCZsY06+ckiCnMQBO1
RGl5ETU2DYDp1rx9fQajcutmS1mpkcpl0B9lPMbcFaLV+S6JV9YGrOYwS40NpB/0bRNvjlpJj1NB
nTRSDcMqZpYYkqAumrMqUIbsB6ddZcrYVq5EK5EgTRtpGd8qKdFsKmWZKTZwzN6nPXKvtyqyVUX+
cWGPsA39Spwtl2TjBVOB15AjKl07i2d81fUPzzKHQg+1UkcK+fyechv36BkJn3CegnYwMJd//X3Z
ec0RzAeJBGag6tv3ch8iBEYbSnyKqxHIZidz4sPUl7b6icVy0cnJUE87nMWuD6SbZUrq7AgzUwAw
MUP2RjoqcttnTD9Kuz0+iEFz0GBtH/KeJLX35hYrjdvyNDvUcJxe934AWqjDuywSgGpumkoN5M0M
mNDPXCu4jk9O9j4ul5/MjhigSpYSJ2GEnCe7tm2UiXXtOuUf9rlQ22MUg6Bpulxq1LdIbAJY8Tx2
SH0EcYwIE79z1syfM0ZbRlXDIB/CE+IW5MXQmx+lwifaixd1omRKPKlt9FkyWNbfMUMGmGJHXQm9
yXvE20WnEHzUlr9nQXM17Heum2VptvEHuqpR7F4JvtMxeMeklYNTNOy8ohAn0F6nShY9EPTlserY
kox3eh891uU+nnAE7DRMxOCJ423NMzbhrrqVzII3Dgq4Qnk6f9yE4uiH7qAzWiJvvjUGiruZe+Bv
at0i+4plHgnlewU6nALn5P16H6A6oYnge+BIxdBSh2stSzqE7y4zkeNTUCjNlEahoOcHt7tLQxs5
fypVFVr2x/MMAEx2ebzgmuq1egENaf7G6h0UMVLx6kSxlGj/sObOFJReozyMQgHX3riHcQCxjBf3
eVKdJzTFYMktUMBgmtdPpmfUmgLnBQsUlsxTcph4TW9cmaT3iPKJb4IqW763of12WeiYgNP0ucec
X79oMCLrxOrwAD6RiWOZ9H7gnWEMN/Kfq5OiT2OkBq5sz5jjs/b0iuZJadkuxeYtW8WNh0qrF2gC
p2q7Xv5yWQEVZIJVBbhUBFRHlFk+U2lbrCTkG6rJ6m/Boaffu+PI6oRGXShR3wDrECGrOCO/4WPf
T+kf4ojxjhwyVJFmmFsHfLVDwZI4MCfyhZckGcK77A5A65I79hjZnuetEV/wW91ZW/5IlbGMEFXR
chVHGxWMKv08kJqadvHAdUhgXzogZ/jZ8I5nVt+3zFdZJ7nexE6YvlVaWH+sOjCerrX9im8F8S1L
034xaWZhcOfRU2gDSFcqDgjesShifsvLcljHgVcsvIwk5aMbcgo4Z8r6g9qY3IdBHTwGv5a6sOuS
3ORngHVk9IquIiy3Y58fFGqPlDsoBRd1+KAJz8CIzOGSs1e0cRPlIhp1i0IM50IFFr8TaB9ZXLkS
lZelgXv+jZ2n8k0HMg6luD/WVk0F139+8cbZZZ3Ek4NAsySvsMYcgCLFAyKg7jtXrjeNsw6kbm3H
y9fRUPK6+1MUPg9S5e7s/v9vtUxy3XJab+tfv38TyOXpskfYjHCAFTSbEavkhxra+bdkL5kZCzkr
ttV8m+CZAGtVabd7Y41ZaZ7CxylNS9u9dN3pdxud+roWPFwpyiIV7dV3LkSCN9nJ5bK/HBW7IE38
3DGMjXowjxGok1uemFoJjoz10huvXfhcYUSkOt6TBxtNhP0dHETss9ZiHOkDxDVWskK70kVAU8+H
MPgDZ0YfHXEdeVt/QvTFzBALrnduW9xOiMjQ6vzy8DQLOfctIs2+mvoggYOausjCtIYPi1kNGojO
5xjrOOxlLaTLgMUCbHmBdocuzn8Iado0XzAlTDI9rTeiMO9+uEc6vRQUd7aIx9r64n1O1wWs9Xm0
FzdO5WZN5vEfN3qlAjPduAQXECALvIp/5J6vQbv5gbRznJtXem2VFYRo8v3GnKJVN0/0QLWyqlRi
CyP2eHDA6KxoFOqW2bDCUYPrkDg2J5OiqwWvC+FTYOA4prstTPH22e1EsmMAtgqLDSBS9zfPo9FR
36uPDZAB2ndJdEqVJ+ky1DRgxKLHsmS5+RjOCUOtnZQK43CtceUj/moglbuzC7/30M3MD7uHvWHb
2ThiuFfljmpop7bFeaDyDu77s+i1h1uQe88=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
K3gmSOM7POFFC4Vp1wqdf/cLg+XFdquji8tynMaryJILZOozcHCJ8IbqNKWgRNMEfGkRM2IKYFsN
LRP6C817pg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
bgc2eKb8e8mC+Ugzf9NNufWY5ukUVeu8sNBuXX+VvLi2VCKfcf3/EbTbiETssKlazlqhEXTv2s1+
nLSgeAOQvsKkDmL6vWoF99ZY/TQhHgYMpSRuVYu/W0VO5yRCMlfOFd3J5FV0gEpYBeDF7QfHtlD8
tP44XxUa6jVzW5cL0vY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rAjgbHi5JFX9IZ8UdNgm2jLu+6hdXXnzmZy74gEMcsM2afVcE/vxipf6lcP3MG4z2i+EaLXX6pZf
jh34kSX7UYtVSFFtT8a3UxfX9uYvIUu1wDgKCcRNgnGwj35CE5JxC9dAhOddTbOTiw8vSEvUcg4L
TsB1Mxlbe2kxOuYzINWIcFpy8H+0Un5HAiFj2FXxf8GTwCiEQfGtb5R2kRKrQDxFu1LhtnURVitx
0D2bTp7YacAS0/1na7FAYgeadwKdc7mLjY7wv+0QEak2UsmYNsjdlVBoF2vW0IY1rD48azik/gky
GIL4tYgd0YqZtHWyQrBOsM38Z43VNKB0OGykzg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
2rwaGoQVBHpsVMi+VvJ+TcNYf6llQroavWPRdy680OGFIjv+Y+tlxOfqnqj7BD9BYfNn6PqoBSj8
UaRlTYK78WKFJcSSOkMUwQJkNuYjFpUVrnjSAmnaU3u/SfrqQ4eTMwTapwDbrc4qtKG5nlHj12ea
/7AMCgF8piF8Jf1kTCQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
drxCTC0qG5mm+tXdqjy3tcDXmIxtaglEAH3R2X+gDx3cCCwNYdPeCJWZrBioWo38u7rDw7K/6+4h
TgdQQwGFEZa37VPCDg9Frm4ZAAkUWLoa2prtIfoneHNVWIrUk94S8N28EL+B+g49xcq4suOn+OGv
gqNpbQhFCSXD/Mv/31oa/qOERDeXIxfmZo4nDIvZm6Q0ELswuYX7/cyxOxyjRPinhjWw7GY1l5E8
IaUHclQ0R1bZzuLRUEZ7+/tqE/6GlxyIRHUv0uafykZ0WSLiOBG5fFJ7T2+hnmovJoZRpkhyhCZa
CYvFA4xhe75T3lgbgCeyfJs47UZ/tAtfPqU5hw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12224)
`protect data_block
tq8Yf1MfsjaegmCxm7EgtgYvbd8DhPzhjDmYQLWbfOhwYLBzb1geWcSL6aEl8K1bBQnSOdD6CDqw
JNnX4HOxChnJ4poEi8eCPHVxAkXtSM4sMmYoO2viNhZngBzUkKS99Y6xk1MCMyi3hBvD+W2454QB
/PXcezEXjG3tUV/CfzPLaDYOouMAoyWGWRpfAOmbaQAmHNUfSZ24fUedeqEyIdSczlk048VUE4Ie
Yw01T9nPZ1sg9FZ8Iy/RLQdZt7N3uwu1GrJdhRcLzItDtM6TEbiiLtdwwDcHQMfFqIPGSdMlQZkc
Lp+qlMIK1eTsFbpr0fSqS5IxBACYyldd4HQ30bx00n91+cdtTEFyejDImCFI0iZHSLSNRVtqryGL
5c2MlWmykSqSrbiiZCaX7MbMnDi1eVi84w849Rc+1JRWM9uNI4Rkvtn5Yx7+LBqY70bHx+WWvnb8
Qa+riHOci5sTRmQVaOv02qu5Pta5O8C08t+rJ+jEPHxTLI/STdNbkn7u/XuMR3w5xUB4/JxT11Ry
5sUmFMBMfgQN6vB/Al51sQDFszvSSGQkgZe2n7NPZJGwgP0yIDloVxE4L3lAuG1N4muCT4T/nrDS
I7Oec2LMl0bO415te6uBT/EU+zmKI6FVjepwilADKs3JPKadhVLNsgIh9Z2VuLVuVUU4Kqp0NpNk
tbNO4TlShZ9tVtl1AYccv0lDUWsb56ir85kZwsSbJwbULQ3Te8rbNtCD0/zFG9l5e+crV1OEKDCe
hgNncILgNguooonxHLgP7XPVs8EUcPuYITuWa9aVKdbV22smOOzdXZQ87XlQyoVSiQ/SH/F3AV7+
LRgVYtXpEfky6m9Zk77tuP+WIX2xUXVE5nhlmyxZ2/zidXObZupHjqabBZQx3xa5ve1j78UCWqHh
UqzvhYVZJY1pMtZUxw4CSbZTggrhAaLQgWJ9ufZoBqmuDy7Di77wevWhy670RCjjmGD+573ZQ83i
DHb5hOIPuHJnPgjB7Q4L7ju8FK2neQ74M3k23zMfuy/81fPMrqp/E1rmto8awRbzEmzAZVHMRYFK
fJYgf17eaEYoeu1uWyVP8R991wsqUmHs5p3IC0aLKAF+Kbx/x2YYHF39/CFr6k5QF0fV+QRuWHTX
rlEW4cnwZxyDIv1PkkPmM25B8zx+UX3MzMmvWJu6ARHhj0xuAaFQ/Xk8eBw+72GJYohwbKTHy4vT
E1paOUvb3i+UFB2eis3zl7YhOBWPURxptJpqabcIpJ3T4S5lswKVrNMbnFGJWoroFWTI3gxaHHba
pXUhaSENhxCptdSh0a7gi08zomGtjTaVDqaRZvctKL6Q0zEkeiBU/qEGIQPvi6LmzOj+3jQBSp9N
le/2TOXQyNouE+FBN1rxVZkUsbfFA8O1W3OeiFddaKmb2f1FIlvhhvR+DnoK56X4wgjpU/xrX1c+
g7BV1gL+YdvAqzEvOq1UtGlM+xGP2JK4gapVEACDJmodCeTPiLguRjklF0VZxMTd9gH7fu7FaDQV
N4L0k/KWlWg06Z6BoQ5wCeDKUFnNslW6+/TuYAlHCRx8wBtdfND8DmHSUAApx9TkJQfawS2jNX6D
hQbWfeo9F0FTMv/DAuSYbTHcOuHkPacXSD657bkcdvICvHV8textYNFWvqxcwit11uHxNC1df5AF
ITdX912zoLkp0wLOP36zf9OUHavSJlDMLci+a7ukh+oFkhukA1McsTlcbYji6MjevKB6A4bH5MLE
JbYJ6vRT4rZmUndepTV+QDQFW+17OA9/hjGi1Le7vyYqc3JY82I2o8FqF+H3mMiaVNvlxiijnfDn
mF0uv1gzJ/+uBucI72miJRcd98UCFYIQOuY8GUVVvqtPx9M2rqiYZN6zu6h1kypdHhMdEWtb87F7
lJ15wnvR7E/87JUmUUawq9FS3DgKokJMHLZf++vOBDDrqG/fIKW+n/e1vv1KTPk+rRMk1RDTPUO3
75y0bRMiGMOypkNJ8iNBw7IUl37lm0H350REGbCJq8y938nZkGg1HMuw/lF7iwO4ZCbdflzspauz
2D8axtrnt7uYVerw9T9huePwnPWKldI/WmRCwcA/busiR8tphv90A+kNyJd04JhBXo60JXLVYfn1
ASvsiqkpGiCdoIm5sB4HMIBKJQuwwII9EHLkYSGI/Unl9UsLGT2XbJNVudmkCb5Oz0+sYcas9BHT
zOe8GUSR/OlLLpg0VmOg+osBebyS+LON7ofVJqX28u0+OXg6Y30kngHA43SqOO1W9Zitkg5JL/Pn
kkk1Ph9M2PTgFeu+ov+h3nJQzGwc5zt/8snUzx/jbefdCW9icLW+OA9drBDdFKbnBdAb5Cd+6v1c
lHF1YnJgVQi33Q8SFgGwSKMxDwkng7tenBHxNJESSifZlB9tsWqkYdUzV4C3gO4E5Dyv70QRH9B6
aUdQeT2Pk/vOkvJFXq7vmEHn5FSbIes6UArPAkj5zcBFQww8hT4/BrRVgBc2HP+03KFqIY1dx77B
gn/kTWDZgo3qxvZTjqFSeeym50/jjaE9iCdRG/znRhpwlEmp9j4ZAr0ss3q3DuodqrQY2vnzvMH+
ML0QdAtMZ9o8/s2jpPZSR7HK2+YGvo5whMBNiaSE6I4MXATpBky8YkTdJvpZLyOn2+ux+ok7j8D/
iVxRdvcwha3T/pEk4LNNXnVj8xB0qHpHBVNnj8tsFm6x+cCatPEJHOs2shrvPpdNWEDgqzeUrWOI
bF/y/K00WlzXdRc0O7imEBFDTP64bw8GADPItEf+B+IikZm3BWSxsA2foe+j7xOygDhHzMs5auoZ
GWD+grZGAlHT1nH6Uj/SQ6KbY1+hWuiMupL3lzdLenj9clr48+GUBTfKTb5itZ6wEmwgSD0HF3Sz
jaq0MjmrPjwP258lJjYBkeOPUORxlRpgP7w88voqIi/h+2acoiOAEg49E2ddcWe+8GRlhEbCLQQA
0Gtd6IyXn3g3wNS5FStwnzvkqyhKUbOFt1SCq8MmwdcTMW4aHsPD0YfkAPslfZPQ4NFch0BNwVJY
h8wdHmKt/5R63gPvFPUSakUIsPkKYuuAEz8Vg7O84Mu8R/xYsn9VBwBjnFf6hcv8WBy385daV2JM
xg4nLasLimHnQMJLlVgpNhW3c3pVbydIJRu3n/UGHCHvzae4OULz0rmCnwRByHk5T6ksIYKf0X20
5iukvSTN7hb6Qt3oVuz12G+dkLlg7JGCiwJPHSLEqkKIjx6yLqNnuHWEknGI3GpPYLffo9tezgLZ
BJztjNkQqbI7v0s15CU+M/djjsWaAA4SkZ+w+TbPRBrgvqvPjqVT2YZ4RwZIrymYZhcG+HLwkk8I
qeAVraGbN/lCCBonsjOob0UsuH2+MHeqNHR9fwxZNT6QtmVUmfAXfZz5hrrTe0/XA4giW69c5vbq
6f4G39wfbGukzuCIue9rkkLVQImg57j2SkcSGDGhE9U1M2j2Ml5AuvSR509GIZwl43ZCwaHqa+E2
wW29ZJzn4p4A1W6zMBxpPbB5JmVwtGW31J36rkIxGiqZV8+y8UlIE/FcCImfzaClsMT50HH51qxj
yFsPLGoOJRUZIM4Gx3dn781wKGZlTeY/JVzWDl6g/Ln7Se7SWA1kkR8xdnL1sUUutCry4ThZ1YNC
+ZTc65arGz+YGLZBHGPxu2GV2w57V/FZM+FRWaE4PFjuywlp2Vn0g/QJ8u7EW5NRr5shLzTbAsQs
SSN9nwEInGR2iHezGk1Qit78J0woa3HROyfs6d3Sn2nGYFsMcuh9LjWCkvp8pb+TNwHA/0gXFFvJ
xCJs4mz/yCcofJaQjda/m24N3FzyBJH7pWr8wehNnUsUbEsy/9OEHrPc0ZPR6MEzeISSgbLr75bf
3JXCpNCI2uZpqS6ggqK+jwE+ycyQW1OFNKigr29wkbGni9atYUHYO6cNt0QQsZGcpMo6J3dnD8N1
OFwwXGHhKrIdk+UDQAYjoZAW/M3ET4xKBqISeGKrjx7DKW5nxUmCMyBfrAgNKrktYZdmQcf4tk2H
AEjjBMQDa1iXpNW/cCGXe8CIE1bZeRH1ldGLZ3QVis2mtBX7w9Q3mWcmZ0zPgi5rAwwNXO0TM9lt
PCBxuOBmuSzQTsrP5oG26dijNyK1TmUnz2FHz8s9G/EJiXdLflBJR27xW62pYCMQ3JS3a/a/p7aM
epsQ/VAyhA1t8d9luN+D10O3g6hwlnUzaweai6IlcHo8KHi0880adI0d6HOZcy6nkiozsS6X4Cbw
sVbh6fBzE9oubhNNQB1mRat8j0e+apaZBucXofuWALsmmA2n7QwZ3I4+vTH/UBoRnQyvLrNFDtKT
soqSr+DcgiMsTbl8VgppwdNvtNtHsN0QEcV8+Ou9X/T1AmAyim+ecfN8dYC+VWU4pt92K7VvDfuE
wuyFtk3yIQPVrKCdedalT1Sy9isZzfw6fiGpKyHSzaWsrmhlGyqLM50jr6CD8WEpT51mkM+JgW04
NCTkZArkSRjUQNcpupmftsFJBUYhftSW8V8ouIS0EdGptLNsQUo4hcCeFDyo54JzV5uKq7XKiXm3
eV4YJvdyW/r8q/LS0jAUS+Df1S3oUKsvef3dPreiygv4X0Grh9KLDV7L+OeyDC4Y05YSz39K+oOz
fByQs2sgb+mYrb1BGvdq3RxjnCoCCtKr+oALubZ01YCA8cLgM0H8Lwucyqab/Ul1d0GD9++/fN42
JfM2F0g7VDCedHFkMHYcRSxV2aGHTiPXi2tWrlC9u9Q6jG8itjhXVxsZT4yn6KwhfmhVeCL9MxuL
JSPUAnlZm+oCWrA3zhuJX7aT49EVkBxBJ/knkc/brlqt1wrVxNJ7OvunfS7XE6KPgCb7ipbVQaVk
eTXuJ2sVB86SxGT6xibUqNKHVe9a+5pohnwnSDaHzPMrmcu3Odi69YskgmgF/W95yVjRd9+Kvi1+
9UAmJYH/gjL5+bWBlc8ddmmujaQETBExisrvmpmW/8nq6FGjAXmyz4O46tQIHbCiCH7ypdoTUq/Z
xYVNtsJujD00+HR7cCJvOVZF1TGr1yCGUGOwQsutXMyjXhd0N832zUxEtOe+NCn7D4sV+3/aQZQU
1Pl4CuVmR+HMlMhQRPGhvKH+dLVt5OW6vgB7JU58DVfxKImBG/BeiH3NJLdHIwkggoJgHpsazT2p
5mp8+1Vt/DgRx9HrNQCd/OJPxarrzHSSYzz4S8AM+uHwQGeMgHCOu8QG4ZQavqlo+e3Q1roBKxrJ
KquhFXDp17kHs88BJPlhI2snacVcLip4ujAowMQvJIh2ey9ljBFirqULyz2emTida/Tu+xQhSAmO
BZ1h27iA6bfIQn2PXVaPkcinxH7HivsA8AfrusSDNWooSZAhbBnKAgGYg+NfXrZBsc7rie2weEMn
EQeXhfjYVr8vBTrnArnJT7NNi8QIPHNJp9zO0sgX0IkbNqALIWufGrDSCWV9gchEdZRvp2wHym0D
fs1WvNQEiTn3rDZaGeWtpBwwmNtAjoSAxAJCrz9J4w4UX8FmAdrEkXfphiBabRbdq77js2uPyob+
vv0VRvDi9Vu6PJ40wVmoMbKXlHWJt+ax7hDZsnw4T7lhOPvBYmfeKvtZMaud/gdLK4CQvLEHWDPp
6cGTWO7hyhqEUSdvS6Ffuhb/Sfceib5IDM3Ri6kaD+6jS638cZZxVmPO+rIAH2VHElaMYE+IG68Z
vPhwuQtJr78o0fKDJz/b/SOk2Crk2BJeiRzTEb4OTR+MAsGfpAwJhFdOh05zAIFz9QIalfsNfZFb
LVjTbRcWUksl1JMqiN/yJj7eBwnVPK68apzSK/BR4dg6gydtgY3ao+/os/65Z6RAjJ7EQ++qFbBI
yMq1aMqkHSQruv0h8QAlLWLteTPATbjQDpQ9T6SRr2QDJtV8CfsbDyoxrGpPb2L1uvk8HDb21nV1
DPBQawwJZtX2ddJjEAGlzAXCI/7enwdkLnZ6TA+kH4Ixg+7wS1LFd0z1caBSeio7uWq2dZj5cxQg
EeLOMXuVmbTmV4wjwt7yvayN0yZSRGJaZNgsirOO8QlBbcxtQ6fKl9rxZP2L4uL9ppQK12TiGYPN
ftk0CuIpZ4JqP9oS2XYBI9IGXKoOk9xKfHLHBi8FzyxQ/RUD583laqwpka4ateAlXi/CED/AzoRA
QsFYHyJTtcc56tT/LaWqbQPOW8QyNU0ZcyRYb4lzyoxW2AcyMwGDyc1057TCyfp5RDTzqC23yGta
+AfbK7jFYTraOVQbZCZRbyowdWZijIuT1jwM24fK3XHhImLG8SxUmD0DeqIzvEPEahmx8AykG63h
clbBlUyQprpbPMoKismt5x97Sf3MDl+iUFcdkdioOQkQYcuzsGMpy4E3yf6pKbDAzuLSil0wsOQ+
K0XfBpoMTTPjguX+bIrl/EsfWLX6OWMYZE4Xchoa0myThgC3ehkedWwBm3OAf///030IqC1t1N+M
+f29daNrbnZaNRyaYBH3oa91vKTIiQ47kcjlUx7XdfuxCezycVjRrQpyd1HWedrfmhhZrswzy2mq
mygKdjpRejG4f7dotHH36S447D/pKE3gGTLsAj/03e8mGtlFU7nSWuvzFiW5RJ0w4xoSkygG/8Cq
LgM/kP/2+iBMUbd2MgPcnbrYKz62cByg40hBUbuZ8q+Tu9/WEQ+oqnNc+wA59fbOhF23972Y9L1P
MRxI6jU7xmXDORpKsEGXC/GEaR9JflY0fv+tiWcTU4xZvQ+Sy8Lxr0sjk176SWtCzsvrHBu7Qw7k
WRL+zg1rnKsw4JQLnWN1uGe2PEe8oBRSbEEImwkfokjy9XEjYia6Ygdx/sdSWkKqUI1dndpCSow9
E22aZ2J4ZfhbP6ATLZLjCyz7lgLMLb9NXqtZCd1jVdk5EeT0Nt6Y3Kdmj/tkclHTEe6U1QbC52uS
wCJCJs7PpVq5IEPeROgb5Gfa8rZKUcQQRDoYneZWbXz7d1hLJkjjgNr/5RF8fqNto1T5NhWcVdYk
ududmXmJvaxEWmcpll02Hx3roAOtvuAzhXGjF8IMEEcwEA+xJU8xv72pfev0Nt05Qc/utVyc6oxE
PEQBJZO1t5b7jfUSCLWzrn3HuyD3K8wCk6A6pl2GnR2BGIxh158YUEI0NKsTJVdLHY8Kcu0uBnSK
wjrv1IGKxs+qA408Lozfz4V3B0Mm4JjLqrF367wDaouTdjg4uk05zGvWeqUcHUYnt5cI+3VzWRoU
D22jDcRaYL80vklHYtgKma7EHrIiIr9wJAEyHHCyt7boH7hToDB52EWak8z2YN0FrotJacLpiXCX
ZCDszoWTBQ021z8XStwt6ce0IZLQ4FpRINCDqH5Q+t5nGu70iH0HVcK76gIGai7P0RccJnbLayfH
TE6tKnxQF/acln0gmZsFuRwXSo6skO/3VZ98TftTo09xQfK/4iCojdXIwYllJVm+saMSdC6cNkQh
h6xrIa7d7ZtNwjDATTKKg+4qDxFsLBC+axgzvTii3i0y6a+P7CfzXpW70/Kw5V+KyMlm9/nUo1oo
ueSA5OpKYLSdM+7Yq8F1kMmnV84sliPHzYej6oZEy6Gbv1mkBfeCKpNZpeo0pzVsOlB7buSSQTxu
JCNiWBKHbl9cORT1jLmZSHr57wmr7LZN0i4GAnuxYEilpAMFU0vi1MHJFu6mf9N6tUqDRXFGFkQl
lo72N51s2GsrTqAMwIKrPH0NvxsE8FXenetcv5mCDN/auT8l7Vet3W559ALdbuqP9IBALk+plm7k
u8A8rEZZ3wS+ZFqhYI0S73SLoUyF9vwzxpmQSjopX+lVLT7l4TpJ9f1K5avCtd1scikjIs+T3FDJ
nEb4ZECFjSOgC3ceKkLNAdV27R979bCbTAf+Uo7PJsQyzP86Dz2gO3j8TVyTeML30pwZPz/mr4KK
ZNC8DGbyR/IABTTXFm8W3v/YHLgDfE3VyE42w0UJaHvA7y9qIOrn2PblTrJoeiJKWTqM95pvFg84
K5+wI8+AfgUJ6PzSVly5/lCPDSn/XjMqnU2vDS43/1WFNCH54SefAMpJx4SuMvs1UZ18cHkYykSz
GD7m0TuETxgQRqhEvxH02imH8H34J/wHiF3PPpBucTOFiJXMQt5YEE+VeyjzjwRsBvc4JkkiYX9Q
e4SeZ8h5NNCpyib2abA4DURPaI4hyEyvcaMFjpczQdirwqrewaE5c0ymEN5IM1pQNk1UQsvX7Q1V
sQU/OSulvtmck1kIq/9+kni/5fthHd78a0EvBlXBhBAzP8QzyHF1BRMWGN9ewpvdGRHWtqdnMAzP
v6L14K+F6aF6sr7u4ntweod/X057ebruORYxor6CkdqeI7UXf2+2sHdopOzRDz6qFVHVGrzaOILH
YqhmJp1i04UJ4iL1ZxIQzY4A99jALm5mvpwqEIbaHw0MI3kfBE1HKEvphbaDBu31tkl+r6ALPj99
D4NKBLY5fXWbL8QkX8T1skaolhuvhbkBYmZAUdLHALnUGoi8bEGSaTQjben1mXoKHw8kQ1KfZUGB
4OmAZOerse0c3kCbi5bmJ+kbbLJeTbVE0tsxwKGZRRhhgm88bhoZkG5zhUQOAh+l7+NAiyejxqQM
uumr6Ri8r2iUr7dfpgz8nGfiHwK/yxWydFZvLaGN/nEgjeHLvYXS8cDaMgaO8Jss3FiQskItPc5S
wivgqIUjvUZ5Uc5mULk5rnyXn9K8QivYl4VOWpjYtJcHo+SzQtBb8502CZ7+s/rd19PMyEGUsUty
rwZuornGxOMsSG5h1bWw8E46VttPD4Vz5qA4WZU8YcPmH5i19jfsnkU+Iz3uMSL7F7w01E9j8noQ
bXt3tCwFMVGfsH1gTp+Ivt9CE6LGiZ7dW+ZLjpO9ggRcv8CKV7iFrH0iFDdeg9Bpj/Kijg39vgTO
3hnOwqLWYnLovN+sRdiAk9DuLrp32haVuTO1p0V9GtTd+Kdn/7WkIpLVw3HeF7Vr5utihhLrHlBE
zzTq2jnyNgCcCkRbeJ+u3hROLIqq/jqxG1I3z098E4FxlmuqOPoilsPYzkYTd4xTjVHYSvqO/8m/
vZJh6R1Kutb/7XTXdzo13PQ0MiZUer0GjL9CbhRCBvCGDV2aZ+VMUbyOn1m278jeoVpZyiMX+8j6
CYLGieFZO+h1xNuMfHpGnC2VeCHUXcyKuxzaA24bPqJGRp1iAYPvKKBEgausvn2ntJ9tluKv6mia
Jdf7ftF8sdjFuJ3FVrZ8jibD0vu2xCJKArC61eXKCVzByzZdhwGnl4YCqB4Ct7zyjkwKQNDgWxSg
H2oQo8QoV709IuiuSSpr7wIieXOmSY02a/wWjxYyc7krDuWupx0Eku4aeJeQnSwusr90txvRvoLZ
0YdLGtEgQ/RHR1HwogyFVPxxJb3NgSRLBAZNppsC/X716I4J2wEhahLoOyveVFhs60LoSSgwfrXm
9kvqLG+WV/89g/U2BGg7e4siL6EgXX+5gytt3fsaFZimDwxkptkyIt6yrtwpQEiRt+WqencaY6/E
1jv9yAK0tkOIlBLIvugBhtAdls8GktgLSyck9dhhRPFE44qFeYEcIMNwbTXbIetEWAmBrrRTlmfG
Kv4xMUTDTcNNCRA+Rw9790mjSP/6aTI5MgPCNYvnrUaDKyoeUu390Nx6zOmWvLTb6p9IkR/6apBG
DjdU1zpQFliIP3EQtPnvJqmX3rRJbdW14wPdVY2rPgcYO48/t14i+DW2NAPk8WFiZ112HBg/WlgO
4Wb/03BF2rRcdFrOWexvokdcwzB5an9uUqeydFtbAzfbPAkTaoDhDhGBZXFwMH/kMQMgd01tkWR8
S8wJ3Q+3mgM1/MSSxhPK9ZLEc8fgO2YAXFqP8pSu8fJ7mAKOkAoXB77VIwKjO8lLKXq5cTJIIDvd
sx3K1QVlhhNODdufMJOlfU62OQ5FyWgxVK7lGP1uR/PH/Ds9QTH+/kEW159rJRMQek2HlT+JOQlv
3am19WSJMhGBqBKGT4lzh0K9SEtT+/fvFM4HEkLinJnkfei0HgCgBX+WiYyT727S66MmTm9qcCkU
FTjbde0bsZqyFVvWYckXRxC3/3oDCr9lRc6uOBMILLVPH2bFRpu84XS4A54Pyn0vTMHSJRWU+pp0
lpGl7TOsfqJ6oUwdBvCfjP7cNmjff6OL90aEA4wQaVBtK6AjM5gdPeWMwdxyfXvQfXfd0l2R8G8s
HXk1xhdXKmD5Zu9G/V7QZY9gaoPXlP8mwdXwzwllUrmpgXkBk4DkGzzKb2KakRWErTDZalVRhU/O
m9FzpgCXKdoVWWnuy5lRZRchKQNGDwpZgwJVrnhoQP8nzU/9NasB5O+DTNB5q9UJ734ZIfaWhDQ8
f66/33d8AozeL9ASqRvAhTeYX3LvYHQuUGmzo0TgJRSMuUbpa0JUAt7fCtA58ScX9Tgk1+bpAnvx
1c0AxxAoLWPI8cQbERtIRzZyLm7Z5vhI4YN5VJNiry7n3QO2pHke345zqMmQ5oCoMkXkaUUP2WwJ
uHzvG3k9hizRPA3YMlXbTzjHT4YKMsmCbHyiSS28JZRyokQUcPJWBuznk38Agb/EbVA8LlRoFeJS
p+OC1erZMxgJ4ZB7wR8luYyePMYAFgSG5S3UsFYMg3ayY+6zHMtp4h+wlk/JPjfMfO1G1p6iG2gd
/li/RnxbOIl73Yfvt8wrQQKFXoaasA/dOM/zvxCE/8xv//e9EhGNMozngJkqM/wY1rwmeK4PL4Fz
W6jkWS29nJBd8ypZPfglTYCI1djd0v3xIbOra4puIAFblX+K1bpsKFQcfliNshqoG0dcXFGxPG6O
KTIUIXdtY25HInOkyoY96QlKHPe7VsyFWE+em+21ALQw9wLLdY17tJAf7XhIortRCu+Dzjg5ombY
i1PnrlCmgsrV5u5oSOhoPCDFUTlc8LeZnjeR3DWGju/N6NLp2bUDVNZfUuxkL2rap9XsPlnc75wY
lXA8VQe0ykq+HeHRQks6g/ehxRrRDLpzdZf4AGN3K0WBo2MwtAuagrXc1BwZEkRv71HbkzT03C/U
i3xIMgA1Wmb1IbPQcDvujfpy3OMLJb4fHZ97IAawy+wbA4eiPLPa3EhZg/17JUy1HXBOeuNjox7x
UkZH8/QTHQ9imTL7kWeuuApUL6AIXvMGAOw7rTbXL04V/Hq0Tm5TiVdJOx5GQRANsSj9OFLRYTow
OqUz5uurEXjhjqCCfPJpcTvzkzvcJ1vxhnQF8rTPlQaw5Pkk9U1PupBJzl36Z1ICITmDX1/Hj8WU
aG7drTS5hmHZOwMtoCxIFCqI7Nc8RnM6YyzyLXbWARNArBCl/5SLoeLUnju03Q7cOlNx+GE4ihUb
So3inE4xfo5hp38eZVB/+lQ4pHkiAzL76TP3XBpErLEdbzCE86HPyQnzdLLK99uCWoVtG6jzf5g+
upknnQbn/J8n2OsHOMwFLvFB4uYaMhMAYxVzKMFFCObJGG8wfL7Rw+8sQ2qvAT9J88XQmJKSJXR6
v2GORPXScxsyzaQiK8U3edG0WD4Nu/LKvRQwPjVfN1svuUulEVTp3besPLGRAUc/yFVYQ+4WqGHZ
R/R01YlD7xoGxkVkZSLWBmKyPPZBRMGqLa3LyvRVZmbV2ZKjjcAumQJfQFAuhmUAbf/io7/LHA7F
SPWJNXhjiZXccGffAMwdGrQ9CzCSYl0jeLsMjvTlHkTrBJFxaGznEXRidwdovjT6U5BIf5R4Sxmi
tdp4xrK6hLUBV0SLBgd0dX8tMEW4NCerT/kZU5Csn5YwKCVHEq0aWqIr/BdV9TqJbBWNCkfHGTav
wS+BO3HfdAmvnal8NWxxtDabvh4XTeE1AB2GHLWp/nJ3oQEEPdu4SouU2icgxvWPsBAq7GdsdW/w
CHyc5lj1TiQIXxHC6QTbBpkWhx7k3ZOHUcyzb+NmaNIUcyw7/ewIjpGC3Jae+d5qb0YOQ/zV3KCK
cAIdk0vff0H6joOV3GXyzE3eJfEiPU7G5jIfzFtSnXbMjIlurYmtqwHnaNdx3/GB8plCFpl3y6CY
Gfjz4t0RZ+hYafCAGlRcdFMIDGIaCL3EoyvHeI7p/LUpMHol3+HCTps7nQ3j2eof91lJ4Xye1LtC
E6JEstNagTWfEhJB+KAQKXUrH0jjqoYlw2fwdjZuBUUjFX3Ft2sBNflIxWDPFBHWD3uwBoSG8fT1
Y7Km5P70QnhhgThYtbIVyR2U4jfyJeY5ItqpvqSTk5Eya3e7gNqWd7l90Ih8iTQ04hnYofq+tPRG
uEdcM46F7CGg4Dr7r5nvFbVilCFim9S9NkBW/ukGCNcp3zyHhFK5BF5I8GF0cV+sqvCyOvf+2HJx
RODL/u785eNBA/f9dV1fnZKPiRvI5hfSjPP0PZi83Zm9V2Jz1Tu2uSFHOy40WqUHF77F27EimUZH
B1wLgRCsUdPwuiErcA/vpPFD/f9b+8PI8KvwzMvAoAD/QIVGoeoVdbGfl8t8YKwBsAzgdfoI/MbY
naa+1dy646Ehb/KwfxpPluWUs4H62BPG+BrcXSSI6r649T9CvsmXbLXu72XLQ6Zlv4UqE1UpZHn0
cu0Lp0mYl6nrVlcuKqAVwrSYnPqO+Ip6yDYYn6udkbuWTMJ9B61e3MAUhV30cP+6uFBjlgIdo0As
yYUJ2nRyTqO5Top2MHdadVj5dPojtnrWZU4EyAH9+dUahkzndgji2RBmHSYNgan34NGnR6AUc6xb
Pwtnz10Dwji5wbVH/4lciauSKyTshyFF+hmMJ9ESO0F228LTVanwOdDAztdScUb9Kh4wXNkBSgkI
0IYuHzqhfo5PgV8LuYpJdwNdb60Z9sKnNtBjAKqliJ96h16PDnBn/1HnqV2hTpJ0ojE8EUtVvTm4
mbUxrDt6OvOiZ1zlfevp8DhBlWPG112RgaKqn47npWPHhDb+n9hLNgZ+kp/MaxbCSzZpUYvn12hF
4QXHRlhIF1nBvO6NwPdbY8SB+2P+Hn17JuGutJEDi65PG14Qpa8/i9JQlT3/AoKKgQQjEu3VuFZO
fIfCAhDO4eLVw0S44w/q+HJQQIfRD75Hoz1cj7IMVrrBGUiJB2JZQUtzZntRzraKDl51A8yUwvUh
qfJjxZUWR7WJoP0/Osav8bWAXNf38xbUW3zXs4Qbscxy+i+ZFKSlDwAFohv4uX57MHpcu0501gEc
1MQwFgiJev+SP+Z784RzFJ+23Cz+TeBCEVVk53oK8p3D5O43/y5DFhB/7g7jDE3hRO8x9fbjMLn4
q+k8tMTiGn9tUyaC/BiPsSOKPCmHQyPBffEnNFrSvPHZMMKESWselp3R3eZorpL1qlfQXP9CNw72
mqL2DPc2Yy5NpLrH8kq31c3SzZSAyRKsb6hq7+tT2EJ1C/IRGrYwGngMzK/Rz67MM5Hn9sU7/oRQ
4akVtaI70SSDGgM89ehSey2hkxYWgQh+G+MoktmywaIzL7LaeqL8Ld5d3yvX/66mFeRDhIkyGg+V
BAt4ONJK0nRyBIovv5/3HlqXG1vaQh0QrEnJeBljTG2P1IzI5p/gRB/SO5qpnUZz8MrDzF/4UYxY
sTfyaprQsfhF08r/EPCPis52+nxAXSYyo/dEjS/TydnHEZ+R5ZjnHbCNy7FUo4tuVUVgxeTjj5yX
iKp7MKRo5HK/d9FbDRl4PBhwsw/uwgnY1KYenhxbV52YAqM364WtxtgKN8ppGYSMSizCe9xHTtmS
jXW/Yd070wFlJg8drYNW357qi9aveu4N/sZtnVPdr0o3tI+zXjLUMmB9uFG7YN10Foympl0rUcbJ
oJGOXU7YNEEDjFuAbj0VrAvARG43bt8YLC38cpvLFFdZp7+i8DUkjZiuA5Ow6a7GAt+ZKo2B0gg9
k/dwITmapokzOSENxb9Mp1OIPrjbENVIzR601Ynf3mJYhrc+LESCYcLb8KDPEym2wnhlXJIoeUsP
PHU/Fa1kSsVB51+ZvYbCTcnz0hQWvaXFMLPlpDI1qDJDSiOgTdZiiyFi2W0aQk281R8PpAHuf5KL
dc2iElVXrSAoxAF/4kwzi6apDLdgWK1e8CvpIGD7OUNCHfaSHWoBCnnpdYJa6LCfjwg0pSJDT7pN
2vduN04ooVxInT7t2bc+/QRgCeGiuscpfjHNOyw5uaOq+KmftCQ4OG9NU+VWQG3eBPZIZLyFfA7a
RrNJxkgCwzg7QgHI6Q+iEI+q9YzayPLCo+zsloIjw6d7QwGyuRvNCOKRWcYCZsY06+ckiCnMQBO1
RGl5ETU2DYDp1rx9fQajcutmS1mpkcpl0B9lPMbcFaLV+S6JV9YGrOYwS40NpB/0bRNvjlpJj1NB
nTRSDcMqZpYYkqAumrMqUIbsB6ddZcrYVq5EK5EgTRtpGd8qKdFsKmWZKTZwzN6nPXKvtyqyVUX+
cWGPsA39Spwtl2TjBVOB15AjKl07i2d81fUPzzKHQg+1UkcK+fyechv36BkJn3CegnYwMJd//X3Z
ec0RzAeJBGag6tv3ch8iBEYbSnyKqxHIZidz4sPUl7b6icVy0cnJUE87nMWuD6SbZUrq7AgzUwAw
MUP2RjoqcttnTD9Kuz0+iEFz0GBtH/KeJLX35hYrjdvyNDvUcJxe934AWqjDuywSgGpumkoN5M0M
mNDPXCu4jk9O9j4ul5/MjhigSpYSJ2GEnCe7tm2UiXXtOuUf9rlQ22MUg6Bpulxq1LdIbAJY8Tx2
SH0EcYwIE79z1syfM0ZbRlXDIB/CE+IW5MXQmx+lwifaixd1omRKPKlt9FkyWNbfMUMGmGJHXQm9
yXvE20WnEHzUlr9nQXM17Heum2VptvEHuqpR7F4JvtMxeMeklYNTNOy8ohAn0F6nShY9EPTlserY
kox3eh891uU+nnAE7DRMxOCJ423NMzbhrrqVzII3Dgq4Qnk6f9yE4uiH7qAzWiJvvjUGiruZe+Bv
at0i+4plHgnlewU6nALn5P16H6A6oYnge+BIxdBSh2stSzqE7y4zkeNTUCjNlEahoOcHt7tLQxs5
fypVFVr2x/MMAEx2ebzgmuq1egENaf7G6h0UMVLx6kSxlGj/sObOFJReozyMQgHX3riHcQCxjBf3
eVKdJzTFYMktUMBgmtdPpmfUmgLnBQsUlsxTcph4TW9cmaT3iPKJb4IqW763of12WeiYgNP0ucec
X79oMCLrxOrwAD6RiWOZ9H7gnWEMN/Kfq5OiT2OkBq5sz5jjs/b0iuZJadkuxeYtW8WNh0qrF2gC
p2q7Xv5yWQEVZIJVBbhUBFRHlFk+U2lbrCTkG6rJ6m/Boaffu+PI6oRGXShR3wDrECGrOCO/4WPf
T+kf4ojxjhwyVJFmmFsHfLVDwZI4MCfyhZckGcK77A5A65I79hjZnuetEV/wW91ZW/5IlbGMEFXR
chVHGxWMKv08kJqadvHAdUhgXzogZ/jZ8I5nVt+3zFdZJ7nexE6YvlVaWH+sOjCerrX9im8F8S1L
034xaWZhcOfRU2gDSFcqDgjesShifsvLcljHgVcsvIwk5aMbcgo4Z8r6g9qY3IdBHTwGv5a6sOuS
3ORngHVk9IquIiy3Y58fFGqPlDsoBRd1+KAJz8CIzOGSs1e0cRPlIhp1i0IM50IFFr8TaB9ZXLkS
lZelgXv+jZ2n8k0HMg6luD/WVk0F139+8cbZZZ3Ek4NAsySvsMYcgCLFAyKg7jtXrjeNsw6kbm3H
y9fRUPK6+1MUPg9S5e7s/v9vtUxy3XJab+tfv38TyOXpskfYjHCAFTSbEavkhxra+bdkL5kZCzkr
ttV8m+CZAGtVabd7Y41ZaZ7CxylNS9u9dN3pdxud+roWPFwpyiIV7dV3LkSCN9nJ5bK/HBW7IE38
3DGMjXowjxGok1uemFoJjoz10huvXfhcYUSkOt6TBxtNhP0dHETss9ZiHOkDxDVWskK70kVAU8+H
MPgDZ0YfHXEdeVt/QvTFzBALrnduW9xOiMjQ6vzy8DQLOfctIs2+mvoggYOausjCtIYPi1kNGojO
5xjrOOxlLaTLgMUCbHmBdocuzn8Iado0XzAlTDI9rTeiMO9+uEc6vRQUd7aIx9r64n1O1wWs9Xm0
FzdO5WZN5vEfN3qlAjPduAQXECALvIp/5J6vQbv5gbRznJtXem2VFYRo8v3GnKJVN0/0QLWyqlRi
CyP2eHDA6KxoFOqW2bDCUYPrkDg2J5OiqwWvC+FTYOA4prstTPH22e1EsmMAtgqLDSBS9zfPo9FR
36uPDZAB2ndJdEqVJ+ky1DRgxKLHsmS5+RjOCUOtnZQK43CtceUj/moglbuzC7/30M3MD7uHvWHb
2ThiuFfljmpop7bFeaDyDu77s+i1h1uQe88=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
K3gmSOM7POFFC4Vp1wqdf/cLg+XFdquji8tynMaryJILZOozcHCJ8IbqNKWgRNMEfGkRM2IKYFsN
LRP6C817pg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
bgc2eKb8e8mC+Ugzf9NNufWY5ukUVeu8sNBuXX+VvLi2VCKfcf3/EbTbiETssKlazlqhEXTv2s1+
nLSgeAOQvsKkDmL6vWoF99ZY/TQhHgYMpSRuVYu/W0VO5yRCMlfOFd3J5FV0gEpYBeDF7QfHtlD8
tP44XxUa6jVzW5cL0vY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rAjgbHi5JFX9IZ8UdNgm2jLu+6hdXXnzmZy74gEMcsM2afVcE/vxipf6lcP3MG4z2i+EaLXX6pZf
jh34kSX7UYtVSFFtT8a3UxfX9uYvIUu1wDgKCcRNgnGwj35CE5JxC9dAhOddTbOTiw8vSEvUcg4L
TsB1Mxlbe2kxOuYzINWIcFpy8H+0Un5HAiFj2FXxf8GTwCiEQfGtb5R2kRKrQDxFu1LhtnURVitx
0D2bTp7YacAS0/1na7FAYgeadwKdc7mLjY7wv+0QEak2UsmYNsjdlVBoF2vW0IY1rD48azik/gky
GIL4tYgd0YqZtHWyQrBOsM38Z43VNKB0OGykzg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
2rwaGoQVBHpsVMi+VvJ+TcNYf6llQroavWPRdy680OGFIjv+Y+tlxOfqnqj7BD9BYfNn6PqoBSj8
UaRlTYK78WKFJcSSOkMUwQJkNuYjFpUVrnjSAmnaU3u/SfrqQ4eTMwTapwDbrc4qtKG5nlHj12ea
/7AMCgF8piF8Jf1kTCQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
drxCTC0qG5mm+tXdqjy3tcDXmIxtaglEAH3R2X+gDx3cCCwNYdPeCJWZrBioWo38u7rDw7K/6+4h
TgdQQwGFEZa37VPCDg9Frm4ZAAkUWLoa2prtIfoneHNVWIrUk94S8N28EL+B+g49xcq4suOn+OGv
gqNpbQhFCSXD/Mv/31oa/qOERDeXIxfmZo4nDIvZm6Q0ELswuYX7/cyxOxyjRPinhjWw7GY1l5E8
IaUHclQ0R1bZzuLRUEZ7+/tqE/6GlxyIRHUv0uafykZ0WSLiOBG5fFJ7T2+hnmovJoZRpkhyhCZa
CYvFA4xhe75T3lgbgCeyfJs47UZ/tAtfPqU5hw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12224)
`protect data_block
tq8Yf1MfsjaegmCxm7EgtgYvbd8DhPzhjDmYQLWbfOhwYLBzb1geWcSL6aEl8K1bBQnSOdD6CDqw
JNnX4HOxChnJ4poEi8eCPHVxAkXtSM4sMmYoO2viNhZngBzUkKS99Y6xk1MCMyi3hBvD+W2454QB
/PXcezEXjG3tUV/CfzPLaDYOouMAoyWGWRpfAOmbaQAmHNUfSZ24fUedeqEyIdSczlk048VUE4Ie
Yw01T9nPZ1sg9FZ8Iy/RLQdZt7N3uwu1GrJdhRcLzItDtM6TEbiiLtdwwDcHQMfFqIPGSdMlQZkc
Lp+qlMIK1eTsFbpr0fSqS5IxBACYyldd4HQ30bx00n91+cdtTEFyejDImCFI0iZHSLSNRVtqryGL
5c2MlWmykSqSrbiiZCaX7MbMnDi1eVi84w849Rc+1JRWM9uNI4Rkvtn5Yx7+LBqY70bHx+WWvnb8
Qa+riHOci5sTRmQVaOv02qu5Pta5O8C08t+rJ+jEPHxTLI/STdNbkn7u/XuMR3w5xUB4/JxT11Ry
5sUmFMBMfgQN6vB/Al51sQDFszvSSGQkgZe2n7NPZJGwgP0yIDloVxE4L3lAuG1N4muCT4T/nrDS
I7Oec2LMl0bO415te6uBT/EU+zmKI6FVjepwilADKs3JPKadhVLNsgIh9Z2VuLVuVUU4Kqp0NpNk
tbNO4TlShZ9tVtl1AYccv0lDUWsb56ir85kZwsSbJwbULQ3Te8rbNtCD0/zFG9l5e+crV1OEKDCe
hgNncILgNguooonxHLgP7XPVs8EUcPuYITuWa9aVKdbV22smOOzdXZQ87XlQyoVSiQ/SH/F3AV7+
LRgVYtXpEfky6m9Zk77tuP+WIX2xUXVE5nhlmyxZ2/zidXObZupHjqabBZQx3xa5ve1j78UCWqHh
UqzvhYVZJY1pMtZUxw4CSbZTggrhAaLQgWJ9ufZoBqmuDy7Di77wevWhy670RCjjmGD+573ZQ83i
DHb5hOIPuHJnPgjB7Q4L7ju8FK2neQ74M3k23zMfuy/81fPMrqp/E1rmto8awRbzEmzAZVHMRYFK
fJYgf17eaEYoeu1uWyVP8R991wsqUmHs5p3IC0aLKAF+Kbx/x2YYHF39/CFr6k5QF0fV+QRuWHTX
rlEW4cnwZxyDIv1PkkPmM25B8zx+UX3MzMmvWJu6ARHhj0xuAaFQ/Xk8eBw+72GJYohwbKTHy4vT
E1paOUvb3i+UFB2eis3zl7YhOBWPURxptJpqabcIpJ3T4S5lswKVrNMbnFGJWoroFWTI3gxaHHba
pXUhaSENhxCptdSh0a7gi08zomGtjTaVDqaRZvctKL6Q0zEkeiBU/qEGIQPvi6LmzOj+3jQBSp9N
le/2TOXQyNouE+FBN1rxVZkUsbfFA8O1W3OeiFddaKmb2f1FIlvhhvR+DnoK56X4wgjpU/xrX1c+
g7BV1gL+YdvAqzEvOq1UtGlM+xGP2JK4gapVEACDJmodCeTPiLguRjklF0VZxMTd9gH7fu7FaDQV
N4L0k/KWlWg06Z6BoQ5wCeDKUFnNslW6+/TuYAlHCRx8wBtdfND8DmHSUAApx9TkJQfawS2jNX6D
hQbWfeo9F0FTMv/DAuSYbTHcOuHkPacXSD657bkcdvICvHV8textYNFWvqxcwit11uHxNC1df5AF
ITdX912zoLkp0wLOP36zf9OUHavSJlDMLci+a7ukh+oFkhukA1McsTlcbYji6MjevKB6A4bH5MLE
JbYJ6vRT4rZmUndepTV+QDQFW+17OA9/hjGi1Le7vyYqc3JY82I2o8FqF+H3mMiaVNvlxiijnfDn
mF0uv1gzJ/+uBucI72miJRcd98UCFYIQOuY8GUVVvqtPx9M2rqiYZN6zu6h1kypdHhMdEWtb87F7
lJ15wnvR7E/87JUmUUawq9FS3DgKokJMHLZf++vOBDDrqG/fIKW+n/e1vv1KTPk+rRMk1RDTPUO3
75y0bRMiGMOypkNJ8iNBw7IUl37lm0H350REGbCJq8y938nZkGg1HMuw/lF7iwO4ZCbdflzspauz
2D8axtrnt7uYVerw9T9huePwnPWKldI/WmRCwcA/busiR8tphv90A+kNyJd04JhBXo60JXLVYfn1
ASvsiqkpGiCdoIm5sB4HMIBKJQuwwII9EHLkYSGI/Unl9UsLGT2XbJNVudmkCb5Oz0+sYcas9BHT
zOe8GUSR/OlLLpg0VmOg+osBebyS+LON7ofVJqX28u0+OXg6Y30kngHA43SqOO1W9Zitkg5JL/Pn
kkk1Ph9M2PTgFeu+ov+h3nJQzGwc5zt/8snUzx/jbefdCW9icLW+OA9drBDdFKbnBdAb5Cd+6v1c
lHF1YnJgVQi33Q8SFgGwSKMxDwkng7tenBHxNJESSifZlB9tsWqkYdUzV4C3gO4E5Dyv70QRH9B6
aUdQeT2Pk/vOkvJFXq7vmEHn5FSbIes6UArPAkj5zcBFQww8hT4/BrRVgBc2HP+03KFqIY1dx77B
gn/kTWDZgo3qxvZTjqFSeeym50/jjaE9iCdRG/znRhpwlEmp9j4ZAr0ss3q3DuodqrQY2vnzvMH+
ML0QdAtMZ9o8/s2jpPZSR7HK2+YGvo5whMBNiaSE6I4MXATpBky8YkTdJvpZLyOn2+ux+ok7j8D/
iVxRdvcwha3T/pEk4LNNXnVj8xB0qHpHBVNnj8tsFm6x+cCatPEJHOs2shrvPpdNWEDgqzeUrWOI
bF/y/K00WlzXdRc0O7imEBFDTP64bw8GADPItEf+B+IikZm3BWSxsA2foe+j7xOygDhHzMs5auoZ
GWD+grZGAlHT1nH6Uj/SQ6KbY1+hWuiMupL3lzdLenj9clr48+GUBTfKTb5itZ6wEmwgSD0HF3Sz
jaq0MjmrPjwP258lJjYBkeOPUORxlRpgP7w88voqIi/h+2acoiOAEg49E2ddcWe+8GRlhEbCLQQA
0Gtd6IyXn3g3wNS5FStwnzvkqyhKUbOFt1SCq8MmwdcTMW4aHsPD0YfkAPslfZPQ4NFch0BNwVJY
h8wdHmKt/5R63gPvFPUSakUIsPkKYuuAEz8Vg7O84Mu8R/xYsn9VBwBjnFf6hcv8WBy385daV2JM
xg4nLasLimHnQMJLlVgpNhW3c3pVbydIJRu3n/UGHCHvzae4OULz0rmCnwRByHk5T6ksIYKf0X20
5iukvSTN7hb6Qt3oVuz12G+dkLlg7JGCiwJPHSLEqkKIjx6yLqNnuHWEknGI3GpPYLffo9tezgLZ
BJztjNkQqbI7v0s15CU+M/djjsWaAA4SkZ+w+TbPRBrgvqvPjqVT2YZ4RwZIrymYZhcG+HLwkk8I
qeAVraGbN/lCCBonsjOob0UsuH2+MHeqNHR9fwxZNT6QtmVUmfAXfZz5hrrTe0/XA4giW69c5vbq
6f4G39wfbGukzuCIue9rkkLVQImg57j2SkcSGDGhE9U1M2j2Ml5AuvSR509GIZwl43ZCwaHqa+E2
wW29ZJzn4p4A1W6zMBxpPbB5JmVwtGW31J36rkIxGiqZV8+y8UlIE/FcCImfzaClsMT50HH51qxj
yFsPLGoOJRUZIM4Gx3dn781wKGZlTeY/JVzWDl6g/Ln7Se7SWA1kkR8xdnL1sUUutCry4ThZ1YNC
+ZTc65arGz+YGLZBHGPxu2GV2w57V/FZM+FRWaE4PFjuywlp2Vn0g/QJ8u7EW5NRr5shLzTbAsQs
SSN9nwEInGR2iHezGk1Qit78J0woa3HROyfs6d3Sn2nGYFsMcuh9LjWCkvp8pb+TNwHA/0gXFFvJ
xCJs4mz/yCcofJaQjda/m24N3FzyBJH7pWr8wehNnUsUbEsy/9OEHrPc0ZPR6MEzeISSgbLr75bf
3JXCpNCI2uZpqS6ggqK+jwE+ycyQW1OFNKigr29wkbGni9atYUHYO6cNt0QQsZGcpMo6J3dnD8N1
OFwwXGHhKrIdk+UDQAYjoZAW/M3ET4xKBqISeGKrjx7DKW5nxUmCMyBfrAgNKrktYZdmQcf4tk2H
AEjjBMQDa1iXpNW/cCGXe8CIE1bZeRH1ldGLZ3QVis2mtBX7w9Q3mWcmZ0zPgi5rAwwNXO0TM9lt
PCBxuOBmuSzQTsrP5oG26dijNyK1TmUnz2FHz8s9G/EJiXdLflBJR27xW62pYCMQ3JS3a/a/p7aM
epsQ/VAyhA1t8d9luN+D10O3g6hwlnUzaweai6IlcHo8KHi0880adI0d6HOZcy6nkiozsS6X4Cbw
sVbh6fBzE9oubhNNQB1mRat8j0e+apaZBucXofuWALsmmA2n7QwZ3I4+vTH/UBoRnQyvLrNFDtKT
soqSr+DcgiMsTbl8VgppwdNvtNtHsN0QEcV8+Ou9X/T1AmAyim+ecfN8dYC+VWU4pt92K7VvDfuE
wuyFtk3yIQPVrKCdedalT1Sy9isZzfw6fiGpKyHSzaWsrmhlGyqLM50jr6CD8WEpT51mkM+JgW04
NCTkZArkSRjUQNcpupmftsFJBUYhftSW8V8ouIS0EdGptLNsQUo4hcCeFDyo54JzV5uKq7XKiXm3
eV4YJvdyW/r8q/LS0jAUS+Df1S3oUKsvef3dPreiygv4X0Grh9KLDV7L+OeyDC4Y05YSz39K+oOz
fByQs2sgb+mYrb1BGvdq3RxjnCoCCtKr+oALubZ01YCA8cLgM0H8Lwucyqab/Ul1d0GD9++/fN42
JfM2F0g7VDCedHFkMHYcRSxV2aGHTiPXi2tWrlC9u9Q6jG8itjhXVxsZT4yn6KwhfmhVeCL9MxuL
JSPUAnlZm+oCWrA3zhuJX7aT49EVkBxBJ/knkc/brlqt1wrVxNJ7OvunfS7XE6KPgCb7ipbVQaVk
eTXuJ2sVB86SxGT6xibUqNKHVe9a+5pohnwnSDaHzPMrmcu3Odi69YskgmgF/W95yVjRd9+Kvi1+
9UAmJYH/gjL5+bWBlc8ddmmujaQETBExisrvmpmW/8nq6FGjAXmyz4O46tQIHbCiCH7ypdoTUq/Z
xYVNtsJujD00+HR7cCJvOVZF1TGr1yCGUGOwQsutXMyjXhd0N832zUxEtOe+NCn7D4sV+3/aQZQU
1Pl4CuVmR+HMlMhQRPGhvKH+dLVt5OW6vgB7JU58DVfxKImBG/BeiH3NJLdHIwkggoJgHpsazT2p
5mp8+1Vt/DgRx9HrNQCd/OJPxarrzHSSYzz4S8AM+uHwQGeMgHCOu8QG4ZQavqlo+e3Q1roBKxrJ
KquhFXDp17kHs88BJPlhI2snacVcLip4ujAowMQvJIh2ey9ljBFirqULyz2emTida/Tu+xQhSAmO
BZ1h27iA6bfIQn2PXVaPkcinxH7HivsA8AfrusSDNWooSZAhbBnKAgGYg+NfXrZBsc7rie2weEMn
EQeXhfjYVr8vBTrnArnJT7NNi8QIPHNJp9zO0sgX0IkbNqALIWufGrDSCWV9gchEdZRvp2wHym0D
fs1WvNQEiTn3rDZaGeWtpBwwmNtAjoSAxAJCrz9J4w4UX8FmAdrEkXfphiBabRbdq77js2uPyob+
vv0VRvDi9Vu6PJ40wVmoMbKXlHWJt+ax7hDZsnw4T7lhOPvBYmfeKvtZMaud/gdLK4CQvLEHWDPp
6cGTWO7hyhqEUSdvS6Ffuhb/Sfceib5IDM3Ri6kaD+6jS638cZZxVmPO+rIAH2VHElaMYE+IG68Z
vPhwuQtJr78o0fKDJz/b/SOk2Crk2BJeiRzTEb4OTR+MAsGfpAwJhFdOh05zAIFz9QIalfsNfZFb
LVjTbRcWUksl1JMqiN/yJj7eBwnVPK68apzSK/BR4dg6gydtgY3ao+/os/65Z6RAjJ7EQ++qFbBI
yMq1aMqkHSQruv0h8QAlLWLteTPATbjQDpQ9T6SRr2QDJtV8CfsbDyoxrGpPb2L1uvk8HDb21nV1
DPBQawwJZtX2ddJjEAGlzAXCI/7enwdkLnZ6TA+kH4Ixg+7wS1LFd0z1caBSeio7uWq2dZj5cxQg
EeLOMXuVmbTmV4wjwt7yvayN0yZSRGJaZNgsirOO8QlBbcxtQ6fKl9rxZP2L4uL9ppQK12TiGYPN
ftk0CuIpZ4JqP9oS2XYBI9IGXKoOk9xKfHLHBi8FzyxQ/RUD583laqwpka4ateAlXi/CED/AzoRA
QsFYHyJTtcc56tT/LaWqbQPOW8QyNU0ZcyRYb4lzyoxW2AcyMwGDyc1057TCyfp5RDTzqC23yGta
+AfbK7jFYTraOVQbZCZRbyowdWZijIuT1jwM24fK3XHhImLG8SxUmD0DeqIzvEPEahmx8AykG63h
clbBlUyQprpbPMoKismt5x97Sf3MDl+iUFcdkdioOQkQYcuzsGMpy4E3yf6pKbDAzuLSil0wsOQ+
K0XfBpoMTTPjguX+bIrl/EsfWLX6OWMYZE4Xchoa0myThgC3ehkedWwBm3OAf///030IqC1t1N+M
+f29daNrbnZaNRyaYBH3oa91vKTIiQ47kcjlUx7XdfuxCezycVjRrQpyd1HWedrfmhhZrswzy2mq
mygKdjpRejG4f7dotHH36S447D/pKE3gGTLsAj/03e8mGtlFU7nSWuvzFiW5RJ0w4xoSkygG/8Cq
LgM/kP/2+iBMUbd2MgPcnbrYKz62cByg40hBUbuZ8q+Tu9/WEQ+oqnNc+wA59fbOhF23972Y9L1P
MRxI6jU7xmXDORpKsEGXC/GEaR9JflY0fv+tiWcTU4xZvQ+Sy8Lxr0sjk176SWtCzsvrHBu7Qw7k
WRL+zg1rnKsw4JQLnWN1uGe2PEe8oBRSbEEImwkfokjy9XEjYia6Ygdx/sdSWkKqUI1dndpCSow9
E22aZ2J4ZfhbP6ATLZLjCyz7lgLMLb9NXqtZCd1jVdk5EeT0Nt6Y3Kdmj/tkclHTEe6U1QbC52uS
wCJCJs7PpVq5IEPeROgb5Gfa8rZKUcQQRDoYneZWbXz7d1hLJkjjgNr/5RF8fqNto1T5NhWcVdYk
ududmXmJvaxEWmcpll02Hx3roAOtvuAzhXGjF8IMEEcwEA+xJU8xv72pfev0Nt05Qc/utVyc6oxE
PEQBJZO1t5b7jfUSCLWzrn3HuyD3K8wCk6A6pl2GnR2BGIxh158YUEI0NKsTJVdLHY8Kcu0uBnSK
wjrv1IGKxs+qA408Lozfz4V3B0Mm4JjLqrF367wDaouTdjg4uk05zGvWeqUcHUYnt5cI+3VzWRoU
D22jDcRaYL80vklHYtgKma7EHrIiIr9wJAEyHHCyt7boH7hToDB52EWak8z2YN0FrotJacLpiXCX
ZCDszoWTBQ021z8XStwt6ce0IZLQ4FpRINCDqH5Q+t5nGu70iH0HVcK76gIGai7P0RccJnbLayfH
TE6tKnxQF/acln0gmZsFuRwXSo6skO/3VZ98TftTo09xQfK/4iCojdXIwYllJVm+saMSdC6cNkQh
h6xrIa7d7ZtNwjDATTKKg+4qDxFsLBC+axgzvTii3i0y6a+P7CfzXpW70/Kw5V+KyMlm9/nUo1oo
ueSA5OpKYLSdM+7Yq8F1kMmnV84sliPHzYej6oZEy6Gbv1mkBfeCKpNZpeo0pzVsOlB7buSSQTxu
JCNiWBKHbl9cORT1jLmZSHr57wmr7LZN0i4GAnuxYEilpAMFU0vi1MHJFu6mf9N6tUqDRXFGFkQl
lo72N51s2GsrTqAMwIKrPH0NvxsE8FXenetcv5mCDN/auT8l7Vet3W559ALdbuqP9IBALk+plm7k
u8A8rEZZ3wS+ZFqhYI0S73SLoUyF9vwzxpmQSjopX+lVLT7l4TpJ9f1K5avCtd1scikjIs+T3FDJ
nEb4ZECFjSOgC3ceKkLNAdV27R979bCbTAf+Uo7PJsQyzP86Dz2gO3j8TVyTeML30pwZPz/mr4KK
ZNC8DGbyR/IABTTXFm8W3v/YHLgDfE3VyE42w0UJaHvA7y9qIOrn2PblTrJoeiJKWTqM95pvFg84
K5+wI8+AfgUJ6PzSVly5/lCPDSn/XjMqnU2vDS43/1WFNCH54SefAMpJx4SuMvs1UZ18cHkYykSz
GD7m0TuETxgQRqhEvxH02imH8H34J/wHiF3PPpBucTOFiJXMQt5YEE+VeyjzjwRsBvc4JkkiYX9Q
e4SeZ8h5NNCpyib2abA4DURPaI4hyEyvcaMFjpczQdirwqrewaE5c0ymEN5IM1pQNk1UQsvX7Q1V
sQU/OSulvtmck1kIq/9+kni/5fthHd78a0EvBlXBhBAzP8QzyHF1BRMWGN9ewpvdGRHWtqdnMAzP
v6L14K+F6aF6sr7u4ntweod/X057ebruORYxor6CkdqeI7UXf2+2sHdopOzRDz6qFVHVGrzaOILH
YqhmJp1i04UJ4iL1ZxIQzY4A99jALm5mvpwqEIbaHw0MI3kfBE1HKEvphbaDBu31tkl+r6ALPj99
D4NKBLY5fXWbL8QkX8T1skaolhuvhbkBYmZAUdLHALnUGoi8bEGSaTQjben1mXoKHw8kQ1KfZUGB
4OmAZOerse0c3kCbi5bmJ+kbbLJeTbVE0tsxwKGZRRhhgm88bhoZkG5zhUQOAh+l7+NAiyejxqQM
uumr6Ri8r2iUr7dfpgz8nGfiHwK/yxWydFZvLaGN/nEgjeHLvYXS8cDaMgaO8Jss3FiQskItPc5S
wivgqIUjvUZ5Uc5mULk5rnyXn9K8QivYl4VOWpjYtJcHo+SzQtBb8502CZ7+s/rd19PMyEGUsUty
rwZuornGxOMsSG5h1bWw8E46VttPD4Vz5qA4WZU8YcPmH5i19jfsnkU+Iz3uMSL7F7w01E9j8noQ
bXt3tCwFMVGfsH1gTp+Ivt9CE6LGiZ7dW+ZLjpO9ggRcv8CKV7iFrH0iFDdeg9Bpj/Kijg39vgTO
3hnOwqLWYnLovN+sRdiAk9DuLrp32haVuTO1p0V9GtTd+Kdn/7WkIpLVw3HeF7Vr5utihhLrHlBE
zzTq2jnyNgCcCkRbeJ+u3hROLIqq/jqxG1I3z098E4FxlmuqOPoilsPYzkYTd4xTjVHYSvqO/8m/
vZJh6R1Kutb/7XTXdzo13PQ0MiZUer0GjL9CbhRCBvCGDV2aZ+VMUbyOn1m278jeoVpZyiMX+8j6
CYLGieFZO+h1xNuMfHpGnC2VeCHUXcyKuxzaA24bPqJGRp1iAYPvKKBEgausvn2ntJ9tluKv6mia
Jdf7ftF8sdjFuJ3FVrZ8jibD0vu2xCJKArC61eXKCVzByzZdhwGnl4YCqB4Ct7zyjkwKQNDgWxSg
H2oQo8QoV709IuiuSSpr7wIieXOmSY02a/wWjxYyc7krDuWupx0Eku4aeJeQnSwusr90txvRvoLZ
0YdLGtEgQ/RHR1HwogyFVPxxJb3NgSRLBAZNppsC/X716I4J2wEhahLoOyveVFhs60LoSSgwfrXm
9kvqLG+WV/89g/U2BGg7e4siL6EgXX+5gytt3fsaFZimDwxkptkyIt6yrtwpQEiRt+WqencaY6/E
1jv9yAK0tkOIlBLIvugBhtAdls8GktgLSyck9dhhRPFE44qFeYEcIMNwbTXbIetEWAmBrrRTlmfG
Kv4xMUTDTcNNCRA+Rw9790mjSP/6aTI5MgPCNYvnrUaDKyoeUu390Nx6zOmWvLTb6p9IkR/6apBG
DjdU1zpQFliIP3EQtPnvJqmX3rRJbdW14wPdVY2rPgcYO48/t14i+DW2NAPk8WFiZ112HBg/WlgO
4Wb/03BF2rRcdFrOWexvokdcwzB5an9uUqeydFtbAzfbPAkTaoDhDhGBZXFwMH/kMQMgd01tkWR8
S8wJ3Q+3mgM1/MSSxhPK9ZLEc8fgO2YAXFqP8pSu8fJ7mAKOkAoXB77VIwKjO8lLKXq5cTJIIDvd
sx3K1QVlhhNODdufMJOlfU62OQ5FyWgxVK7lGP1uR/PH/Ds9QTH+/kEW159rJRMQek2HlT+JOQlv
3am19WSJMhGBqBKGT4lzh0K9SEtT+/fvFM4HEkLinJnkfei0HgCgBX+WiYyT727S66MmTm9qcCkU
FTjbde0bsZqyFVvWYckXRxC3/3oDCr9lRc6uOBMILLVPH2bFRpu84XS4A54Pyn0vTMHSJRWU+pp0
lpGl7TOsfqJ6oUwdBvCfjP7cNmjff6OL90aEA4wQaVBtK6AjM5gdPeWMwdxyfXvQfXfd0l2R8G8s
HXk1xhdXKmD5Zu9G/V7QZY9gaoPXlP8mwdXwzwllUrmpgXkBk4DkGzzKb2KakRWErTDZalVRhU/O
m9FzpgCXKdoVWWnuy5lRZRchKQNGDwpZgwJVrnhoQP8nzU/9NasB5O+DTNB5q9UJ734ZIfaWhDQ8
f66/33d8AozeL9ASqRvAhTeYX3LvYHQuUGmzo0TgJRSMuUbpa0JUAt7fCtA58ScX9Tgk1+bpAnvx
1c0AxxAoLWPI8cQbERtIRzZyLm7Z5vhI4YN5VJNiry7n3QO2pHke345zqMmQ5oCoMkXkaUUP2WwJ
uHzvG3k9hizRPA3YMlXbTzjHT4YKMsmCbHyiSS28JZRyokQUcPJWBuznk38Agb/EbVA8LlRoFeJS
p+OC1erZMxgJ4ZB7wR8luYyePMYAFgSG5S3UsFYMg3ayY+6zHMtp4h+wlk/JPjfMfO1G1p6iG2gd
/li/RnxbOIl73Yfvt8wrQQKFXoaasA/dOM/zvxCE/8xv//e9EhGNMozngJkqM/wY1rwmeK4PL4Fz
W6jkWS29nJBd8ypZPfglTYCI1djd0v3xIbOra4puIAFblX+K1bpsKFQcfliNshqoG0dcXFGxPG6O
KTIUIXdtY25HInOkyoY96QlKHPe7VsyFWE+em+21ALQw9wLLdY17tJAf7XhIortRCu+Dzjg5ombY
i1PnrlCmgsrV5u5oSOhoPCDFUTlc8LeZnjeR3DWGju/N6NLp2bUDVNZfUuxkL2rap9XsPlnc75wY
lXA8VQe0ykq+HeHRQks6g/ehxRrRDLpzdZf4AGN3K0WBo2MwtAuagrXc1BwZEkRv71HbkzT03C/U
i3xIMgA1Wmb1IbPQcDvujfpy3OMLJb4fHZ97IAawy+wbA4eiPLPa3EhZg/17JUy1HXBOeuNjox7x
UkZH8/QTHQ9imTL7kWeuuApUL6AIXvMGAOw7rTbXL04V/Hq0Tm5TiVdJOx5GQRANsSj9OFLRYTow
OqUz5uurEXjhjqCCfPJpcTvzkzvcJ1vxhnQF8rTPlQaw5Pkk9U1PupBJzl36Z1ICITmDX1/Hj8WU
aG7drTS5hmHZOwMtoCxIFCqI7Nc8RnM6YyzyLXbWARNArBCl/5SLoeLUnju03Q7cOlNx+GE4ihUb
So3inE4xfo5hp38eZVB/+lQ4pHkiAzL76TP3XBpErLEdbzCE86HPyQnzdLLK99uCWoVtG6jzf5g+
upknnQbn/J8n2OsHOMwFLvFB4uYaMhMAYxVzKMFFCObJGG8wfL7Rw+8sQ2qvAT9J88XQmJKSJXR6
v2GORPXScxsyzaQiK8U3edG0WD4Nu/LKvRQwPjVfN1svuUulEVTp3besPLGRAUc/yFVYQ+4WqGHZ
R/R01YlD7xoGxkVkZSLWBmKyPPZBRMGqLa3LyvRVZmbV2ZKjjcAumQJfQFAuhmUAbf/io7/LHA7F
SPWJNXhjiZXccGffAMwdGrQ9CzCSYl0jeLsMjvTlHkTrBJFxaGznEXRidwdovjT6U5BIf5R4Sxmi
tdp4xrK6hLUBV0SLBgd0dX8tMEW4NCerT/kZU5Csn5YwKCVHEq0aWqIr/BdV9TqJbBWNCkfHGTav
wS+BO3HfdAmvnal8NWxxtDabvh4XTeE1AB2GHLWp/nJ3oQEEPdu4SouU2icgxvWPsBAq7GdsdW/w
CHyc5lj1TiQIXxHC6QTbBpkWhx7k3ZOHUcyzb+NmaNIUcyw7/ewIjpGC3Jae+d5qb0YOQ/zV3KCK
cAIdk0vff0H6joOV3GXyzE3eJfEiPU7G5jIfzFtSnXbMjIlurYmtqwHnaNdx3/GB8plCFpl3y6CY
Gfjz4t0RZ+hYafCAGlRcdFMIDGIaCL3EoyvHeI7p/LUpMHol3+HCTps7nQ3j2eof91lJ4Xye1LtC
E6JEstNagTWfEhJB+KAQKXUrH0jjqoYlw2fwdjZuBUUjFX3Ft2sBNflIxWDPFBHWD3uwBoSG8fT1
Y7Km5P70QnhhgThYtbIVyR2U4jfyJeY5ItqpvqSTk5Eya3e7gNqWd7l90Ih8iTQ04hnYofq+tPRG
uEdcM46F7CGg4Dr7r5nvFbVilCFim9S9NkBW/ukGCNcp3zyHhFK5BF5I8GF0cV+sqvCyOvf+2HJx
RODL/u785eNBA/f9dV1fnZKPiRvI5hfSjPP0PZi83Zm9V2Jz1Tu2uSFHOy40WqUHF77F27EimUZH
B1wLgRCsUdPwuiErcA/vpPFD/f9b+8PI8KvwzMvAoAD/QIVGoeoVdbGfl8t8YKwBsAzgdfoI/MbY
naa+1dy646Ehb/KwfxpPluWUs4H62BPG+BrcXSSI6r649T9CvsmXbLXu72XLQ6Zlv4UqE1UpZHn0
cu0Lp0mYl6nrVlcuKqAVwrSYnPqO+Ip6yDYYn6udkbuWTMJ9B61e3MAUhV30cP+6uFBjlgIdo0As
yYUJ2nRyTqO5Top2MHdadVj5dPojtnrWZU4EyAH9+dUahkzndgji2RBmHSYNgan34NGnR6AUc6xb
Pwtnz10Dwji5wbVH/4lciauSKyTshyFF+hmMJ9ESO0F228LTVanwOdDAztdScUb9Kh4wXNkBSgkI
0IYuHzqhfo5PgV8LuYpJdwNdb60Z9sKnNtBjAKqliJ96h16PDnBn/1HnqV2hTpJ0ojE8EUtVvTm4
mbUxrDt6OvOiZ1zlfevp8DhBlWPG112RgaKqn47npWPHhDb+n9hLNgZ+kp/MaxbCSzZpUYvn12hF
4QXHRlhIF1nBvO6NwPdbY8SB+2P+Hn17JuGutJEDi65PG14Qpa8/i9JQlT3/AoKKgQQjEu3VuFZO
fIfCAhDO4eLVw0S44w/q+HJQQIfRD75Hoz1cj7IMVrrBGUiJB2JZQUtzZntRzraKDl51A8yUwvUh
qfJjxZUWR7WJoP0/Osav8bWAXNf38xbUW3zXs4Qbscxy+i+ZFKSlDwAFohv4uX57MHpcu0501gEc
1MQwFgiJev+SP+Z784RzFJ+23Cz+TeBCEVVk53oK8p3D5O43/y5DFhB/7g7jDE3hRO8x9fbjMLn4
q+k8tMTiGn9tUyaC/BiPsSOKPCmHQyPBffEnNFrSvPHZMMKESWselp3R3eZorpL1qlfQXP9CNw72
mqL2DPc2Yy5NpLrH8kq31c3SzZSAyRKsb6hq7+tT2EJ1C/IRGrYwGngMzK/Rz67MM5Hn9sU7/oRQ
4akVtaI70SSDGgM89ehSey2hkxYWgQh+G+MoktmywaIzL7LaeqL8Ld5d3yvX/66mFeRDhIkyGg+V
BAt4ONJK0nRyBIovv5/3HlqXG1vaQh0QrEnJeBljTG2P1IzI5p/gRB/SO5qpnUZz8MrDzF/4UYxY
sTfyaprQsfhF08r/EPCPis52+nxAXSYyo/dEjS/TydnHEZ+R5ZjnHbCNy7FUo4tuVUVgxeTjj5yX
iKp7MKRo5HK/d9FbDRl4PBhwsw/uwgnY1KYenhxbV52YAqM364WtxtgKN8ppGYSMSizCe9xHTtmS
jXW/Yd070wFlJg8drYNW357qi9aveu4N/sZtnVPdr0o3tI+zXjLUMmB9uFG7YN10Foympl0rUcbJ
oJGOXU7YNEEDjFuAbj0VrAvARG43bt8YLC38cpvLFFdZp7+i8DUkjZiuA5Ow6a7GAt+ZKo2B0gg9
k/dwITmapokzOSENxb9Mp1OIPrjbENVIzR601Ynf3mJYhrc+LESCYcLb8KDPEym2wnhlXJIoeUsP
PHU/Fa1kSsVB51+ZvYbCTcnz0hQWvaXFMLPlpDI1qDJDSiOgTdZiiyFi2W0aQk281R8PpAHuf5KL
dc2iElVXrSAoxAF/4kwzi6apDLdgWK1e8CvpIGD7OUNCHfaSHWoBCnnpdYJa6LCfjwg0pSJDT7pN
2vduN04ooVxInT7t2bc+/QRgCeGiuscpfjHNOyw5uaOq+KmftCQ4OG9NU+VWQG3eBPZIZLyFfA7a
RrNJxkgCwzg7QgHI6Q+iEI+q9YzayPLCo+zsloIjw6d7QwGyuRvNCOKRWcYCZsY06+ckiCnMQBO1
RGl5ETU2DYDp1rx9fQajcutmS1mpkcpl0B9lPMbcFaLV+S6JV9YGrOYwS40NpB/0bRNvjlpJj1NB
nTRSDcMqZpYYkqAumrMqUIbsB6ddZcrYVq5EK5EgTRtpGd8qKdFsKmWZKTZwzN6nPXKvtyqyVUX+
cWGPsA39Spwtl2TjBVOB15AjKl07i2d81fUPzzKHQg+1UkcK+fyechv36BkJn3CegnYwMJd//X3Z
ec0RzAeJBGag6tv3ch8iBEYbSnyKqxHIZidz4sPUl7b6icVy0cnJUE87nMWuD6SbZUrq7AgzUwAw
MUP2RjoqcttnTD9Kuz0+iEFz0GBtH/KeJLX35hYrjdvyNDvUcJxe934AWqjDuywSgGpumkoN5M0M
mNDPXCu4jk9O9j4ul5/MjhigSpYSJ2GEnCe7tm2UiXXtOuUf9rlQ22MUg6Bpulxq1LdIbAJY8Tx2
SH0EcYwIE79z1syfM0ZbRlXDIB/CE+IW5MXQmx+lwifaixd1omRKPKlt9FkyWNbfMUMGmGJHXQm9
yXvE20WnEHzUlr9nQXM17Heum2VptvEHuqpR7F4JvtMxeMeklYNTNOy8ohAn0F6nShY9EPTlserY
kox3eh891uU+nnAE7DRMxOCJ423NMzbhrrqVzII3Dgq4Qnk6f9yE4uiH7qAzWiJvvjUGiruZe+Bv
at0i+4plHgnlewU6nALn5P16H6A6oYnge+BIxdBSh2stSzqE7y4zkeNTUCjNlEahoOcHt7tLQxs5
fypVFVr2x/MMAEx2ebzgmuq1egENaf7G6h0UMVLx6kSxlGj/sObOFJReozyMQgHX3riHcQCxjBf3
eVKdJzTFYMktUMBgmtdPpmfUmgLnBQsUlsxTcph4TW9cmaT3iPKJb4IqW763of12WeiYgNP0ucec
X79oMCLrxOrwAD6RiWOZ9H7gnWEMN/Kfq5OiT2OkBq5sz5jjs/b0iuZJadkuxeYtW8WNh0qrF2gC
p2q7Xv5yWQEVZIJVBbhUBFRHlFk+U2lbrCTkG6rJ6m/Boaffu+PI6oRGXShR3wDrECGrOCO/4WPf
T+kf4ojxjhwyVJFmmFsHfLVDwZI4MCfyhZckGcK77A5A65I79hjZnuetEV/wW91ZW/5IlbGMEFXR
chVHGxWMKv08kJqadvHAdUhgXzogZ/jZ8I5nVt+3zFdZJ7nexE6YvlVaWH+sOjCerrX9im8F8S1L
034xaWZhcOfRU2gDSFcqDgjesShifsvLcljHgVcsvIwk5aMbcgo4Z8r6g9qY3IdBHTwGv5a6sOuS
3ORngHVk9IquIiy3Y58fFGqPlDsoBRd1+KAJz8CIzOGSs1e0cRPlIhp1i0IM50IFFr8TaB9ZXLkS
lZelgXv+jZ2n8k0HMg6luD/WVk0F139+8cbZZZ3Ek4NAsySvsMYcgCLFAyKg7jtXrjeNsw6kbm3H
y9fRUPK6+1MUPg9S5e7s/v9vtUxy3XJab+tfv38TyOXpskfYjHCAFTSbEavkhxra+bdkL5kZCzkr
ttV8m+CZAGtVabd7Y41ZaZ7CxylNS9u9dN3pdxud+roWPFwpyiIV7dV3LkSCN9nJ5bK/HBW7IE38
3DGMjXowjxGok1uemFoJjoz10huvXfhcYUSkOt6TBxtNhP0dHETss9ZiHOkDxDVWskK70kVAU8+H
MPgDZ0YfHXEdeVt/QvTFzBALrnduW9xOiMjQ6vzy8DQLOfctIs2+mvoggYOausjCtIYPi1kNGojO
5xjrOOxlLaTLgMUCbHmBdocuzn8Iado0XzAlTDI9rTeiMO9+uEc6vRQUd7aIx9r64n1O1wWs9Xm0
FzdO5WZN5vEfN3qlAjPduAQXECALvIp/5J6vQbv5gbRznJtXem2VFYRo8v3GnKJVN0/0QLWyqlRi
CyP2eHDA6KxoFOqW2bDCUYPrkDg2J5OiqwWvC+FTYOA4prstTPH22e1EsmMAtgqLDSBS9zfPo9FR
36uPDZAB2ndJdEqVJ+ky1DRgxKLHsmS5+RjOCUOtnZQK43CtceUj/moglbuzC7/30M3MD7uHvWHb
2ThiuFfljmpop7bFeaDyDu77s+i1h1uQe88=
`protect end_protected
|
--!
--! Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! @brief Access to debug port of CPUs through the DMI registers.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
library ambalib;
use ambalib.types_amba4.all;
library riverlib;
use riverlib.river_cfg.all;
use riverlib.types_river.all;
entity dmi_regs is
generic (
async_reset : boolean := false;
cpu_available : integer := 1
);
port
(
clk : in std_logic;
nrst : in std_logic;
-- port[0] connected to JTAG TAP has access to AXI master interface (SBA registers)
i_dmi_jtag_req_valid : in std_logic;
o_dmi_jtag_req_ready : out std_logic;
i_dmi_jtag_write : in std_logic;
i_dmi_jtag_addr : in std_logic_vector(6 downto 0);
i_dmi_jtag_wdata : in std_logic_vector(31 downto 0);
o_dmi_jtag_resp_valid : out std_logic;
i_dmi_jtag_resp_ready : in std_logic;
o_dmi_jtag_rdata : out std_logic_vector(31 downto 0);
-- port[1] connected to DSU doesn't have access to AXI master interface
i_dmi_dsu_req_valid : in std_logic;
o_dmi_dsu_req_ready : out std_logic;
i_dmi_dsu_write : in std_logic;
i_dmi_dsu_addr : in std_logic_vector(6 downto 0);
i_dmi_dsu_wdata : in std_logic_vector(31 downto 0);
o_dmi_dsu_resp_valid : out std_logic;
i_dmi_dsu_resp_ready : in std_logic;
o_dmi_dsu_rdata : out std_logic_vector(31 downto 0);
-- Common signals
o_hartsel : out std_logic_vector(CFG_LOG2_CPU_MAX-1 downto 0);
o_dmstat : out std_logic_vector(1 downto 0);
o_ndmreset : out std_logic; -- non-debug module reset
o_cfg : out axi4_master_config_type;
i_xmsti : in axi4_master_in_type;
o_xmsto : out axi4_master_out_type;
o_dporti : out dport_in_vector;
i_dporto : in dport_out_vector
);
end;
architecture arch_dmi_regs of dmi_regs is
constant xconfig : axi4_master_config_type := (
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES,
vid => VENDOR_GNSSSENSOR,
did => RISCV_RIVER_DMI
);
constant HARTSELLEN : integer := CFG_LOG2_CPU_MAX;
constant HART_AVAILABLE_MASK : std_logic_vector(HARTSELLEN-1 downto 0) :=
conv_std_logic_vector(2**log2(cpu_available) - 1, HARTSELLEN);
type state_type is (
Idle,
DmiRequest,
AbstractCommand,
DportRequest,
DportResponse,
DportPostexec,
DportBroadbandRequest,
DportBroadbandResponse,
Dma_AR,
Dma_R,
Dma_AW,
Dma_W,
Dma_B,
DmiResponse
);
type registers is record
state : state_type;
dmstat : std_logic_vector(1 downto 0);
hartsel : std_logic_vector(HARTSELLEN-1 downto 0);
ndmreset : std_logic; -- non-debug module reset
resumeack : std_logic;
halt_after_reset : std_logic;
addr : std_logic_vector(CFG_DPORT_ADDR_BITS-1 downto 0);
rdata : std_logic_vector(63 downto 0);
wdata : std_logic_vector(63 downto 0);
wstrb : std_logic_vector(7 downto 0);
memdata : std_logic_vector(63 downto 0);
arg0 : std_logic_vector(63 downto 0);
command : std_logic_vector(31 downto 0);
autoexecdata : std_logic_vector(CFG_DATA_REG_TOTAL-1 downto 0);
autoexecprogbuf : std_logic_vector(CFG_PROGBUF_REG_TOTAL-1 downto 0);
transfer : std_logic;
write : std_logic;
postexec : std_logic;
jtag_dsu : std_logic;
broadband_req : std_logic_vector(CFG_TOTAL_CPU_MAX-1 downto 0);
sberror : std_logic_vector(2 downto 0);
sbreadonaddr : std_logic;
sbaccess : std_logic_vector(2 downto 0);
sbautoincrement : std_logic;
sbreadondata : std_logic;
sbaddress : std_logic_vector(63 downto 0);
end record;
constant R_RESET : registers := (
Idle, -- state
"00", -- dmstat
(others => '0'), -- hartsel
'0', -- ndmreset
'0', -- resumeack
'0', -- halt_after_reset
(others => '0'), -- addr
(others => '0'), -- rdata
(others => '0'), -- wdata
(others => '0'), -- wstrb
(others => '0'), -- memdata
(others => '0'), -- arg0
(others => '0'), -- command
(others => '0'), -- autoexecdata
(others => '0'), -- autoexecprogbuf
'0', -- transfer
'0', -- write
'0', -- postexec
'0', -- jtag_dsu
(others => '0'), -- broadband_req
(others => '0'), -- sberror
'0', -- sbreadonaddr
(others => '0'), -- sbaccess
'0', -- sbautoincrement
'0', -- sbreadondata
(others => '0') -- sbaddress
);
constant h004_DATA0 : std_logic_vector(11 downto 0) := X"004";
constant h005_DATA1 : std_logic_vector(11 downto 0) := X"005";
constant h010_DMCONTROL : std_logic_vector(11 downto 0) := X"010";
constant h011_DMSTATUS : std_logic_vector(11 downto 0) := X"011";
constant h016_ABSTRACTCS : std_logic_vector(11 downto 0) := X"016";
constant h017_COMMAND : std_logic_vector(11 downto 0) := X"017";
constant h018_ABSTRACTAUTO : std_logic_vector(11 downto 0) := X"018";
constant h02n_PROGBUFn : std_logic_vector(11 downto 0) := X"020";
constant h038_SBCS : std_logic_vector(11 downto 0) := X"038";
constant h039_SBADDRESS0 : std_logic_vector(11 downto 0) := X"039";
constant h03A_SBADDRESS1 : std_logic_vector(11 downto 0) := X"03A";
constant h03C_SBDATA0 : std_logic_vector(11 downto 0) := X"03C";
constant h03D_SBDATA1 : std_logic_vector(11 downto 0) := X"03D";
constant h040_HALTSUM0 : std_logic_vector(11 downto 0) := X"040";
signal r, rin: registers;
begin
comblogic : process(nrst,
i_dmi_jtag_req_valid, i_dmi_jtag_write, i_dmi_jtag_addr, i_dmi_jtag_wdata, i_dmi_jtag_resp_ready,
i_dmi_dsu_req_valid, i_dmi_dsu_write, i_dmi_dsu_addr, i_dmi_dsu_wdata, i_dmi_dsu_resp_ready,
i_xmsti, i_dporto, r)
variable v : registers;
variable v_dmi_jtag_req_ready : std_logic;
variable v_dmi_dsu_req_ready : std_logic;
variable v_dmi_jtag_resp_valid : std_logic;
variable v_dmi_dsu_resp_valid : std_logic;
variable vdporti : dport_in_vector;
variable v_ar_valid : std_logic;
variable v_aw_valid : std_logic;
variable v_w_valid : std_logic;
variable vxmsto : axi4_master_out_type;
variable hsel : integer range 0 to CFG_TOTAL_CPU_MAX-1;
variable v_axi_ready : std_logic;
variable vb_haltsum : std_logic_vector(CFG_TOTAL_CPU_MAX-1 downto 0);
variable sbaidx3 : integer range 0 to 7;
variable sbaidx2 : integer range 0 to 3;
variable sbaidx1 : integer range 0 to 1;
begin
v := r;
v_dmi_jtag_req_ready := '0';
v_dmi_dsu_req_ready := '0';
v_dmi_jtag_resp_valid := '0';
v_dmi_dsu_resp_valid := '0';
vdporti := (others => dport_in_none);
vxmsto := axi4_master_out_none;
v_ar_valid := '0';
v_aw_valid := '0';
v_w_valid := '0';
hsel := conv_integer(r.hartsel);
sbaidx3 := conv_integer(r.sbaddress(2 downto 0));
sbaidx2 := conv_integer(r.sbaddress(2 downto 1));
sbaidx1 := conv_integer(r.sbaddress(2 downto 2));
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
vb_haltsum(n) := i_dporto(n).halted;
end loop;
case r.state is
when Idle =>
v.addr := (others => '0');
v.wdata := (others => '0');
v.rdata := (others => '0');
v.transfer := '0';
v.postexec := '0';
if i_dmi_jtag_req_valid = '1' then
v.jtag_dsu := '0';
v_dmi_jtag_req_ready := '1';
v.write := i_dmi_jtag_write;
v.addr(6 downto 0) := i_dmi_jtag_addr;
v.wdata(31 downto 0) := i_dmi_jtag_wdata;
v.state := DmiRequest;
elsif i_dmi_dsu_req_valid = '1' then
v.jtag_dsu := '1';
v_dmi_dsu_req_ready := '1';
v.write := i_dmi_dsu_write;
v.addr(6 downto 0) := i_dmi_dsu_addr;
v.wdata(31 downto 0) := i_dmi_dsu_wdata;
v.state := DmiRequest;
end if;
when DmiRequest =>
v.state := DmiResponse; -- default no dport transfer
if r.addr(11 downto 0) = h004_DATA0 then
v.rdata(31 downto 0) := r.arg0(31 downto 0);
if r.write = '1' then
v.arg0(31 downto 0) := r.wdata(31 downto 0);
end if;
if r.autoexecdata(0) = '1'then
v.state := AbstractCommand;
end if;
elsif r.addr(11 downto 0) = h005_DATA1 then
v.rdata(31 downto 0) := r.arg0(63 downto 32);
if r.write = '1' then
v.arg0(63 downto 32) := r.wdata(31 downto 0);
end if;
if r.autoexecdata(1) = '1' then
v.state := AbstractCommand;
end if;
elsif r.addr(11 downto 0) = h010_DMCONTROL then
v.rdata(16+HARTSELLEN-1 downto 16) := r.hartsel;
v.rdata(1) := r.ndmreset;
v.rdata(0) := '1'; -- dmactive: 1=module functional normally
if r.write = '1' then
-- Access to CSR only on writing
v.hartsel := r.wdata(16+HARTSELLEN-1 downto 16) and HART_AVAILABLE_MASK; -- hartsello
v.ndmreset := r.wdata(1); -- ndmreset
v.resumeack := not r.wdata(31) and r.wdata(30) and i_dporto(conv_integer(v.hartsel)).halted;
if r.ndmreset = '1' and r.wdata(1) = '0' and r.halt_after_reset = '1' then
v.state := DportRequest;
v.addr(13 downto 0) := "00" & CSR_runcontrol;
v.wdata := (others => '0');
v.wdata(31) := '1'; -- haltreq:
elsif r.wdata(1) = '1' then -- ndmreset
-- do not make DPort request the CPU will be resetted and cannot respond
v.halt_after_reset := r.wdata(31); -- haltreq
elsif (r.wdata(31) or r.wdata(30)) = '1' then
v.state := DportRequest;
v.addr(13 downto 0) := "00" & CSR_runcontrol;
end if;
end if;
elsif r.addr(11 downto 0) = h011_DMSTATUS then
v.rdata(17) := r.resumeack; -- allresumeack
v.rdata(16) := r.resumeack; -- anyresumeack
v.rdata(15) := not i_dporto(hsel).available; -- allnonexistent
v.rdata(14) := not i_dporto(hsel).available; -- anynonexistent
v.rdata(13) := not i_dporto(hsel).available; -- allunavail
v.rdata(12) := not i_dporto(hsel).available; -- anyunavail
v.rdata(11) := not i_dporto(hsel).halted and i_dporto(hsel).available; -- allrunning:
v.rdata(10) := not i_dporto(hsel).halted and i_dporto(hsel).available; -- anyrunning:
v.rdata(9) := i_dporto(hsel).halted and i_dporto(hsel).available; -- allhalted:
v.rdata(8) := i_dporto(hsel).halted and i_dporto(hsel).available; -- anyhalted:
v.rdata(7) := '1'; -- authenticated:
v.rdata(3 downto 0) := X"2"; -- version: dbg spec v0.13
elsif r.addr(11 downto 0) = h016_ABSTRACTCS then
v.state := DportRequest;
v.addr(13 downto 0) := "00" & CSR_abstractcs;
elsif r.addr(11 downto 0) = h017_COMMAND then
if r.write = '1' then
v.command := r.wdata(31 downto 0); -- original value for auto repeat
v.state := AbstractCommand;
end if;
elsif r.addr(11 downto 0) = h018_ABSTRACTAUTO then
v.rdata(CFG_DATA_REG_TOTAL-1 downto 0) := r.autoexecdata;
v.rdata(16+CFG_PROGBUF_REG_TOTAL-1 downto 16) := r.autoexecprogbuf;
if r.write = '1' then
v.autoexecdata := r.wdata(CFG_DATA_REG_TOTAL-1 downto 0);
v.autoexecprogbuf := r.wdata(16+CFG_PROGBUF_REG_TOTAL-1 downto 16);
end if;
elsif r.addr(11 downto 4) = h02n_PROGBUFn(11 downto 4) then -- PROGBUF0..PROGBUF15
v.addr(13 downto 0) := "00" & CSR_progbuf;
v.wdata(35 downto 32) := r.addr(3 downto 0);
v.broadband_req := (others => '1'); -- to all Harts
v.state := DportBroadbandRequest;
elsif r.addr(11 downto 0) = h038_SBCS then
v.rdata(31 downto 29) := "001"; -- sbversion: 1=current spec
if (r.state = Dma_AR) or (r.state = Dma_R)
or (r.state = Dma_AW) or (r.state = Dma_W) or (r.state = Dma_B) then
v.rdata(21) := '1'; -- sbbusy
end if;
v.rdata(20) := r.sbreadonaddr; -- when 1 auto-read on write to sbaddress0
v.rdata(19 downto 17) := r.sbaccess; -- 2=32; 3=64 bits
v.rdata(16) := r.sbautoincrement; -- increment after each system access
v.rdata(15) := r.sbreadondata; -- when 1 every auto-read on read from sbdata0
v.rdata(14 downto 12) := r.sberror; -- 1=timeout; 2=bad address; 3=unalignment;4=wrong size
v.rdata(11 downto 5) := conv_std_logic_vector(64,7); -- system bus width in bits
v.rdata(3) := '1'; -- sbaccess64 - supported 64-bit access
v.rdata(2) := '1'; -- sbaccess32 - supported 32-bit access
v.rdata(1) := '1'; -- sbaccess16 - supported 16-bit access
v.rdata(0) := '1'; -- sbaccess8 - supported 8-bit access
if r.write = '1' then
v.sbreadonaddr := r.wdata(20);
v.sbaccess := r.wdata(19 downto 17);
v.sbautoincrement := r.wdata(16);
v.sbreadondata := r.wdata(15);
if r.wdata(12) = '1' then
v.sberror := (others => '0');
end if;
end if;
elsif r.addr(11 downto 0) = h039_SBADDRESS0 then
v.rdata(31 downto 0) := r.sbaddress(31 downto 0);
if r.write = '1' then
v.sbaddress(31 downto 0) := r.wdata(31 downto 0);
if r.sbreadonaddr = '1' then
v.state := Dma_AR;
end if;
end if;
elsif r.addr(11 downto 0) = h03A_SBADDRESS1 then
v.rdata(31 downto 0) := r.sbaddress(63 downto 32);
if r.write = '1' then
v.sbaddress(63 downto 32) := r.wdata(31 downto 0);
end if;
elsif r.addr(11 downto 0) = h03C_SBDATA0 then
v.rdata(31 downto 0) := r.memdata(31 downto 0);
if r.write = '0' then
v.state := Dma_AR;
else
v.state := Dma_AW;
v.memdata := (others => '0');
v.wstrb := (others => '0');
case r.sbaccess is
when "000" => -- 8-bits access
v.memdata(8*sbaidx3+7 downto 8*sbaidx3) := r.wdata(7 downto 0);
v.wstrb(sbaidx3) := '1';
when "001" => -- 16-bits access
v.memdata(16*sbaidx2+15 downto 16*sbaidx2) := r.wdata(15 downto 0);
v.wstrb(2*sbaidx2+1 downto 2*sbaidx2) := "11";
when "010" => -- 32-bits access
v.memdata(32*sbaidx1+31 downto 32*sbaidx1) := r.wdata(31 downto 0);
v.wstrb(4*sbaidx1+3 downto 4*sbaidx1) := X"F";
when others =>
v.memdata := r.wdata;
v.wstrb := X"FF";
end case;
end if;
elsif r.addr(11 downto 0) = h03D_SBDATA1 then
v.rdata(31 downto 0) := r.memdata(63 downto 32);
if r.write = '0' then
v.memdata(63 downto 32) := r.wdata(31 downto 0);
end if;
elsif r.addr(11 downto 0) = h040_HALTSUM0 then
v.rdata(CFG_TOTAL_CPU_MAX-1 downto 0) := vb_haltsum;
end if;
when AbstractCommand =>
v.state := DmiResponse; -- no transfer or not implemented command type
if r.command(31 downto 24) = X"00" then -- cmdtype: 0=register access
v.wdata := r.arg0;
v.addr(13 downto 0) := r.command(13 downto 0); -- regno:
v.write := r.command(16); -- write:
v.transfer := r.command(17); -- transfer
v.postexec := r.command(18); -- postexec:
if r.command(19) = '1' then -- aarpostincrement
v.command(13 downto 0) := r.command(13 downto 0) + 1;
end if;
if r.command(16) = '0' or r.command(17) = '1' then
-- read operation or write with transfer
v.state := DportRequest;
end if;
end if;
when DportRequest =>
vdporti(hsel).req_valid := '1';
vdporti(hsel).addr := r.addr;
vdporti(hsel).write := r.write;
vdporti(hsel).wdata := r.wdata;
if i_dporto(hsel).req_ready = '1' then
v.state := DportResponse;
end if;
when DportResponse =>
vdporti(hsel).resp_ready := '1';
if i_dporto(hsel).resp_valid = '1' then
v.state := DmiResponse;
v.rdata := i_dporto(hsel).rdata;
if r.write = '0' and r.transfer = '1' then
v.arg0 := i_dporto(hsel).rdata;
end if;
if r.postexec = '1' then
v.state := DportPostexec;
end if;
end if;
when DportPostexec =>
v.write := '1';
v.postexec := '0';
v.transfer := '0';
v.addr(13 downto 0) := "00" & CSR_runcontrol;
v.wdata := (others => '0');
v.wdata(27) := '1'; -- req_progbuf: request to execute progbuf
v.state := DportRequest;
when DportBroadbandRequest =>
for i in 0 to CFG_TOTAL_CPU_MAX-1 loop
vdporti(i).req_valid := r.broadband_req(i);
vdporti(i).wdata := r.wdata;
vdporti(i).addr := r.addr;
vdporti(i).write := r.write;
if i_dporto(i).req_ready = '1' then
v.broadband_req(i) := '0';
end if;
end loop;
if or_reduce(r.broadband_req) = '0' then
v.broadband_req := (others => '1');
v.state := DportBroadbandResponse;
end if;
when DportBroadbandResponse =>
for i in 0 to CFG_TOTAL_CPU_MAX-1 loop
vdporti(i).resp_ready := r.broadband_req(i);
if i_dporto(i).resp_valid = '1' then
v.broadband_req(i) := '0';
end if;
end loop;
if or_reduce(r.broadband_req) = '0' then
if r.postexec = '1' then
v.state := DportPostexec;
else
v.state := DmiResponse;
end if;
end if;
when Dma_AR =>
v_ar_valid := '1';
if i_xmsti.ar_ready = '1' then
v.state := Dma_R;
end if;
when Dma_R =>
case r.sbaccess is
when "000" => -- 8-bits access
v.memdata(7 downto 0) := i_xmsti.r_data(8*sbaidx3+7 downto 8*sbaidx3);
when "001" => -- 16-bits access
v.memdata(15 downto 0) := i_xmsti.r_data(16*sbaidx2+15 downto 16*sbaidx2);
when "010" => -- 32-bits access
v.memdata(31 downto 0) := i_xmsti.r_data(32*sbaidx1+31 downto 32*sbaidx1);
when others =>
v.memdata := i_xmsti.r_data;
end case;
if i_xmsti.r_valid = '1' then
v.state := DmiResponse;
if i_xmsti.r_resp(1) = '1' then
v.sberror := "010"; -- Bad address was accessed
end if;
if r.sbautoincrement = '1' then
v.sbaddress := r.sbaddress + XSizeToBytes(sbaidx3);
end if;
end if;
when Dma_AW =>
v_aw_valid := '1';
if i_xmsti.aw_ready = '1' then
v.state := Dma_W;
end if;
when Dma_W =>
v_w_valid := '1';
if i_xmsti.w_ready = '1' then
v.state := Dma_B;
end if;
when Dma_B =>
if i_xmsti.b_valid = '1' then
v.state := DmiResponse;
if i_xmsti.b_resp(1) = '1' then
v.sberror := "010"; -- Bad address was accessed
end if;
if r.sbautoincrement = '1' then
v.sbaddress := r.sbaddress + XSizeToBytes(sbaidx3);
end if;
end if;
when DmiResponse =>
v_dmi_jtag_resp_valid := not r.jtag_dsu;
v_dmi_dsu_resp_valid := r.jtag_dsu;
if (not r.jtag_dsu and i_dmi_jtag_resp_ready) = '1' or
(r.jtag_dsu and i_dmi_dsu_resp_ready) = '1' then
v.state := Idle;
end if;
when others =>
end case;
if not async_reset and nrst = '0' then
v := R_RESET;
end if;
vxmsto.ar_valid := v_ar_valid;
vxmsto.ar_bits.addr := r.sbaddress(CFG_SYSBUS_ADDR_BITS-1 downto 0);
vxmsto.ar_bits.size := r.sbaccess;
vxmsto.r_ready := '1';
vxmsto.aw_valid := v_aw_valid;
vxmsto.aw_bits.addr := r.sbaddress(CFG_SYSBUS_ADDR_BITS-1 downto 0);
vxmsto.aw_bits.size := r.sbaccess;
vxmsto.w_valid := v_w_valid;
vxmsto.w_data := r.memdata(CFG_SYSBUS_DATA_BITS-1 downto 0);
vxmsto.w_strb := r.wstrb(CFG_SYSBUS_DATA_BYTES-1 downto 0);
vxmsto.w_last := '1';
vxmsto.b_ready := '1';
rin <= v;
o_dmi_jtag_req_ready <= v_dmi_jtag_req_ready;
o_dmi_jtag_resp_valid <= v_dmi_jtag_resp_valid;
o_dmi_jtag_rdata <= r.rdata(31 downto 0);
o_dmi_dsu_req_ready <= v_dmi_dsu_req_ready;
o_dmi_dsu_resp_valid <= v_dmi_dsu_resp_valid;
o_dmi_dsu_rdata <= r.rdata(31 downto 0);
o_dporti <= vdporti;
o_xmsto <= vxmsto;
end process;
o_cfg <= xconfig;
o_hartsel <= r.hartsel;
o_ndmreset <= r.ndmreset;
o_dmstat <= r.dmstat;
-- registers:
regs : process(clk, nrst)
begin
if async_reset and nrst = '0' then
r <= R_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1084.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01084ent IS
END c06s05b00x00p02n01i01084ent;
ARCHITECTURE c06s05b00x00p02n01i01084arch OF c06s05b00x00p02n01i01084ent IS
BEGIN
TESTING: PROCESS
type FIVE is range 1 to 5;
type A51 is array (FIVE) of BOOLEAN;
type A53 is array (FIVE) of A51;
variable V51: A51 ;
variable V53: A53 ;
BEGIN
V51(2 downto 1, 3 to 4) := V51(2 downto 1, 3 to 4);
-- SYNTAX ERROR: NO MULTIPLE DISCRETE RANGES IN SLICE NAMES
assert FALSE
report "***FAILED TEST: c06s05b00x00p02n01i01084 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01084arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1084.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01084ent IS
END c06s05b00x00p02n01i01084ent;
ARCHITECTURE c06s05b00x00p02n01i01084arch OF c06s05b00x00p02n01i01084ent IS
BEGIN
TESTING: PROCESS
type FIVE is range 1 to 5;
type A51 is array (FIVE) of BOOLEAN;
type A53 is array (FIVE) of A51;
variable V51: A51 ;
variable V53: A53 ;
BEGIN
V51(2 downto 1, 3 to 4) := V51(2 downto 1, 3 to 4);
-- SYNTAX ERROR: NO MULTIPLE DISCRETE RANGES IN SLICE NAMES
assert FALSE
report "***FAILED TEST: c06s05b00x00p02n01i01084 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01084arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1084.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01084ent IS
END c06s05b00x00p02n01i01084ent;
ARCHITECTURE c06s05b00x00p02n01i01084arch OF c06s05b00x00p02n01i01084ent IS
BEGIN
TESTING: PROCESS
type FIVE is range 1 to 5;
type A51 is array (FIVE) of BOOLEAN;
type A53 is array (FIVE) of A51;
variable V51: A51 ;
variable V53: A53 ;
BEGIN
V51(2 downto 1, 3 to 4) := V51(2 downto 1, 3 to 4);
-- SYNTAX ERROR: NO MULTIPLE DISCRETE RANGES IN SLICE NAMES
assert FALSE
report "***FAILED TEST: c06s05b00x00p02n01i01084 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01084arch;
|
--! @file rf_blocks_pkg.vhd
--! @brief Package containing all basic elements in BoostDSP
--! @author Scott Teal (Scott@Teals.org)
--! @date 2013-11-04
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use work.fixed_pkg.all;
use work.util_pkg.all;
package rf_blocks_pkg is
--! Direct Digital Synthesizer. Generates 2 sinusoidal waves 90 degrees out of
--! phase with each other. Frequency is determined by freq, which should be
--! some value between 0 and 1. Realistically, this value will only be between
--! 0 and 0.5, where i_out[n] = cos(2*pi*freq*n) and q_out[n]
--! = sin(2*pi*freq*n).
component dds is
port (
clk : in std_logic; --! Clock line
rst : in std_logic; --! Reset line
freq : in ufixed; --! Frequency input
phase : in ufixed; --! Additional phase offset
i_out : out sfixed; --! I Sinusoidal output
q_out : out sfixed --! Q Sinusoidal output
);
end component dds;
--! Polyphase Direct Digital Synthesizer. For each phase channel, generates
--! 2 sinusoidal waves 90 degrees out of phase with each other. Frequency is
--! determined by freq, which should be some value between 0 and 1.
component poly_dds is
port (
clk : in std_logic; --! Clock line
rst : in std_logic; --! Reset line
freq : in ufixed; --! Frequency input
phase : in ufixed; --! Additional phase offset
i_out : out sfixed_vector; --! I Sinusoidal output vector
q_out : out sfixed_vector --! Q Sinusoidal output vector
);
end component;
component frame_tx is
port (
clk : in std_logic; --! System clock
rst : in std_logic; --! System reset
frame_size : in unsigned; --! Size of frame to transmit
clks_per_symbol : in unsigned; --! Clock cycles per symbol transmitted
start : in std_logic; --! Strobe high to start transmitting.
abort : in std_logic; --! Strobe high to abort transmitting.
frame_tx_complete : out std_logic; --! High when not transmitting.
buffer_addr : in std_logic_vector; --! Address to read/write to.
buffer_we : in std_logic; --! High when write, low when read.
buffer_write_data : in std_logic_vector; --! Data to write.
buffer_read_data : out std_logic_vector; --! Data read from address.
buffer_strobe : in std_logic; --! Strobe high to cycle bus.
buffer_done : out std_logic; --! Strobe high when read/write complete.
symbol_out : out std_logic_vector --! Symbol output
);
end component;
end package;
package body rf_blocks_pkg is
end package body;
|
library ieee;
use ieee.std_logic_1164.all;
entity repro is
end;
architecture behav of repro is
type t_axilite_write_address_channel is record
--DUT inputs
awaddr : std_logic_vector;
awvalid : std_logic;
awprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
awready : std_logic;
end record;
type t_axilite_write_data_channel is record
--DUT inputs
wdata : std_logic_vector;
wstrb : std_logic_vector;
wvalid : std_logic;
--DUT outputs
wready : std_logic;
end record;
type t_axilite_write_response_channel is record
--DUT inputs
bready : std_logic;
--DUT outputs
bresp : std_logic_vector(1 downto 0);
bvalid : std_logic;
end record;
type t_axilite_read_address_channel is record
--DUT inputs
araddr : std_logic_vector;
arvalid : std_logic;
arprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
arready : std_logic;
end record;
type t_axilite_read_data_channel is record
--DUT inputs
rready : std_logic;
--DUT outputs
rdata : std_logic_vector;
rresp : std_logic_vector(1 downto 0);
rvalid : std_logic;
end record;
type t_axilite_if is record
write_address_channel : t_axilite_write_address_channel;
write_data_channel : t_axilite_write_data_channel;
write_response_channel : t_axilite_write_response_channel;
read_address_channel : t_axilite_read_address_channel;
read_data_channel : t_axilite_read_data_channel;
end record;
function get_w return natural is
begin
return 32;
end get_w;
begin
process
constant addr_width : natural := get_w;
constant data_width : natural := get_w;
variable init_if : t_axilite_if
( write_address_channel( awaddr( addr_width -1 downto 0)),
write_data_channel( wdata( data_width -1 downto 0),
wstrb(( data_width/8) -1 downto 0)),
read_address_channel( araddr( addr_width -1 downto 0)),
read_data_channel( rdata( data_width -1 downto 0)));
begin
wait;
end process;
end behav;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:55:36 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_vga_laplacian_fusion_0_0 -prefix
-- system_vga_laplacian_fusion_0_0_ system_vga_laplacian_fusion_0_0_stub.vhdl
-- Design : system_vga_laplacian_fusion_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_laplacian_fusion_0_0 is
Port (
clk_25 : in STD_LOGIC;
rgb_blur_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_pass_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_blur_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_pass_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_out : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_vga_laplacian_fusion_0_0;
architecture stub of system_vga_laplacian_fusion_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_25,rgb_blur_0[23:0],rgb_pass_0[23:0],rgb_blur_1[23:0],rgb_pass_1[23:0],rgb_out[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_laplacian_fusion,Vivado 2016.4";
begin
end;
|
-- file_pixel_gen.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity file_pixel_gen is
generic (
WIDTH : integer;
HEIGHT : integer
);
port (
CLK : in std_logic;
RST : in std_logic;
R : out std_logic_vector(7 downto 0);
G : out std_logic_vector(7 downto 0);
B : out std_logic_vector(7 downto 0);
PX_REQ : in std_logic
);
end entity;
architecture plain_numbers of file_pixel_gen is
begin
read_file : process(CLK, RST, PX_REQ)
file infile : text;
variable l : line;
variable vr : integer;
variable vg : integer;
variable vb : integer;
procedure read_pixel is
begin
readline(infile, l);
read(l, vr);
read(l, vg);
read(l, vb);
R <= conv_std_logic_vector(vr, 8);
G <= conv_std_logic_vector(vg, 8);
B <= conv_std_logic_vector(vb, 8);
end procedure;
begin
if rising_edge(CLK) then
if RST = '1' or endfile(infile) then
file_close(infile);
file_open(infile, "input_file.txt", READ_MODE);
read_pixel;
elsif PX_REQ = '1' then
read_pixel;
end if;
end if;
end process;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity mist1032sa_uart_transmitter is
generic(
BAUDRATE_FIXED : vl_logic := Hi1;
BAUDRATE_COUNTER: vl_logic_vector(0 to 19) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1, Hi1, Hi0, Hi1, Hi1, Hi0, Hi0)
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iEXTBAUD_COUNT : in vl_logic_vector(19 downto 0);
iTX_REQ : in vl_logic;
oTX_BUSY : out vl_logic;
iTX_DATA : in vl_logic_vector(7 downto 0);
oUART_TXD : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of BAUDRATE_FIXED : constant is 1;
attribute mti_svvh_generic_type of BAUDRATE_COUNTER : constant is 1;
end mist1032sa_uart_transmitter;
|
entity bug is
end;
use work.pkg.all;
architecture behav of bug is
begin
p: process
variable rec : rec_t;
begin
wait;
end process;
end behav;
|
entity bug is
end;
use work.pkg.all;
architecture behav of bug is
begin
p: process
variable rec : rec_t;
begin
wait;
end process;
end behav;
|
entity bug is
end;
use work.pkg.all;
architecture behav of bug is
begin
p: process
variable rec : rec_t;
begin
wait;
end process;
end behav;
|
----------------------------------------------------------------------
-- brdLexSwx (for Trenz TEM0001 Board)
----------------------------------------------------------------------
-- (c) 2019 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end brdLexSwx;
----------------------------------------------------------------------
architecture rtl of brdLexSwx is
begin
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
o_lex <= '0';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
o_pbx <= '1';
end rtl; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Gabbe
--
-- Create Date: 09:40:15 09/17/2014
-- Design Name:
-- Module Name: comp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity comp is
port(
clk : in std_logic;
rstn : in std_logic; -- active low
i_hash_0, i_hash_1, i_hash_2, i_hash_3 : in unsigned(31 downto 0); -- hash from md5
i_cmp_hash : in std_logic_vector(127 downto 0); -- hash we are going to crack
i_start : in std_logic; -- 1 when we should read i_cmp_hash
o_equal : out std_logic -- 1 if we found the matching hash, else 0
);
end comp;
architecture Behavioral of comp is
-- the register signals --
signal cmp_hash_c, cmp_hash_n : std_logic_vector(127 downto 0);
-- for delaying equal signal, to controller --
--signal eq_c, eq_n : std_logic;
begin
-- the only signals which are clocked in this block are the register signals --
clk_proc: process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
cmp_hash_c <= (others => '0');
--eq_c <= '0';
else
cmp_hash_c <= cmp_hash_n;
--eq_c <= eq_n;
end if;
end if;
end process;
-- data path --
data_proc: process(i_start, i_cmp_hash, i_hash_0, i_hash_1, i_hash_2, i_hash_3, cmp_hash_c)--, eq_c)
-- the i_hash_1-3 have to be converted to little endian --
variable little_endian_0, little_endian_1, little_endian_2, little_endian_3 : unsigned(31 downto 0);
begin
-- defaults --
--eq_n <= eq_c;
-- converts the md5-hashes to little endian --
little_endian_0 := i_hash_0(7 downto 0) & i_hash_0(15 downto 8) & i_hash_0(23 downto 16) & i_hash_0(31 downto 24);
little_endian_1 := i_hash_1(7 downto 0) & i_hash_1(15 downto 8) & i_hash_1(23 downto 16) & i_hash_1(31 downto 24);
little_endian_2 := i_hash_2(7 downto 0) & i_hash_2(15 downto 8) & i_hash_2(23 downto 16) & i_hash_2(31 downto 24);
little_endian_3 := i_hash_3(7 downto 0) & i_hash_3(15 downto 8) & i_hash_3(23 downto 16) & i_hash_3(31 downto 24);
-- sets the register value --
if i_start = '1' then
cmp_hash_n <= i_cmp_hash;
else
cmp_hash_n <= cmp_hash_c;
end if;
-- have we found a matching hash or not? --
if (little_endian_0 & little_endian_1 & little_endian_2 & little_endian_3) = unsigned(cmp_hash_c) then
--eq_n <= '1';
o_equal <= '1'; --TEST
else
--eq_n <= '0';
o_equal <= '0'; --TEST
end if;
end process;
--o_equal <= eq_c;
end Behavioral;
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: RX core
-- # Outputs are synchronous to wb_clk_i
-- ####################################
-- # Adress Map:
-- # Adr[3:0]:
-- # 0x0 : RX Enable Mask
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wb_rx_core is
generic (
g_NUM_RX : integer range 1 to 32 := 1
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- RX IN
rx_clk_i : in std_logic;
rx_serdes_clk_i : in std_logic;
rx_data_i : in std_logic_vector(g_NUM_RX-1 downto 0);
trig_tag_i : in std_logic_vector(31 downto 0);
-- RX OUT (sync to sys_clk)
rx_valid_o : out std_logic;
rx_data_o : out std_logic_vector(31 downto 0);
busy_o : out std_logic;
debug_o : out std_logic_vector(31 downto 0)
);
end wb_rx_core;
architecture behavioral of wb_rx_core is
function log2_ceil(val : integer) return natural is
variable result : natural;
begin
for i in 0 to g_NUM_RX-1 loop
if (val <= (2 ** i)) then
result := i;
exit;
end if;
end loop;
return result;
end function;
constant c_ALL_ZEROS : std_logic_vector(g_NUM_RX-1 downto 0) := (others => '0');
component rr_arbiter
generic (
g_CHANNELS : integer := g_NUM_RX
);
port (
-- sys connect
clk_i : in std_logic;
rst_i : in std_logic;
-- requests
req_i : in std_logic_vector(g_CHANNELS-1 downto 0);
-- grants
gnt_o : out std_logic_vector(g_CHANNELS-1 downto 0)
);
end component rr_arbiter;
component fei4_rx_channel
port (
-- Sys connect
rst_n_i : in std_logic;
clk_160_i : in std_logic;
clk_640_i : in std_logic;
enable_i : in std_logic;
-- Input
rx_data_i : in std_logic;
trig_tag_i : in std_logic_vector(31 downto 0);
-- Output
rx_data_o : out std_logic_vector(25 downto 0);
rx_valid_o : out std_logic;
rx_stat_o : out std_logic_vector(7 downto 0);
rx_data_raw_o : out std_logic_vector(7 downto 0)
);
end component;
COMPONENT rx_channel_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
type rx_data_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(25 downto 0);
type rx_data_fifo_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(31 downto 0);
type rx_stat_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(7 downto 0);
signal rx_data : rx_data_array;
signal rx_valid : std_logic_vector(g_NUM_RX-1 downto 0);
signal rx_stat : rx_stat_array;
signal rx_data_raw : rx_stat_array;
signal rx_fifo_dout :rx_data_fifo_array;
signal rx_fifo_din : rx_data_fifo_array;
signal rx_fifo_full : std_logic_vector(g_NUM_RX-1 downto 0);
signal rx_fifo_empty : std_logic_vector(g_NUM_RX-1 downto 0);
signal rx_fifo_rden : std_logic_vector(g_NUM_RX-1 downto 0);
signal rx_fifo_rden_t : std_logic_vector(g_NUM_RX-1 downto 0);
signal rx_fifo_wren : std_logic_vector(g_NUM_RX-1 downto 0);
signal rx_enable : std_logic_vector(31 downto 0);
signal channel : integer range 0 to g_NUM_RX-1;
signal debug : std_logic_vector(31 downto 0);
begin
debug_o <= debug;
debug(7 downto 0) <= rx_stat(0);
debug(15 downto 8) <= rx_data_raw(0);
debug(16) <= rx_valid(0);
wb_proc: process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_dat_o <= (others => '0');
wb_ack_o <= '0';
rx_enable <= (others => '0');
wb_stall_o <= '0';
elsif rising_edge(wb_clk_i) then
wb_ack_o <= '0';
if (wb_cyc_i = '1' and wb_stb_i = '1') then
if (wb_we_i = '1') then
if (wb_adr_i(3 downto 0) = x"0") then -- Set enable mask
wb_ack_o <= '1';
rx_enable <= wb_dat_i;
else
wb_ack_o <= '1';
end if;
else
if (wb_adr_i(3 downto 0) = x"0") then -- Read enable mask
wb_dat_o <= rx_enable;
wb_ack_o <= '1';
else
wb_dat_o <= x"DEADBEEF";
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end process wb_proc;
-- Arbiter
cmp_rr_arbiter : rr_arbiter port map (
clk_i => wb_clk_i,
rst_i => not rst_n_i,
req_i => not rx_fifo_empty,
gnt_o => rx_fifo_rden_t
);
--rx_valid_o <= '0' when (unsigned(rx_fifo_rden) = 0 or ((rx_fifo_rden and rx_fifo_empty) = rx_fifo_rden)) else '1';
--rx_data_o <= x"DEADBEEF" when (unsigned(rx_fifo_rden) = 0) else rx_fifo_dout(log2_ceil(to_integer(unsigned(rx_fifo_rden))));
reg_proc : process(wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
rx_fifo_rden <= (others => '0');
rx_valid_o <= '0';
channel <= 0;
elsif rising_edge(wb_clk_i) then
rx_fifo_rden <= rx_fifo_rden_t;
channel <= log2_ceil(to_integer(unsigned(rx_fifo_rden_t)));
if (unsigned(rx_fifo_rden) = 0 or ((rx_fifo_rden and rx_fifo_empty) = rx_fifo_rden)) then
rx_valid_o <= '0';
rx_data_o <= x"DEADBEEF";
else
rx_valid_o <= '1';
rx_data_o <= rx_fifo_dout(channel);
end if;
end if;
end process reg_proc;
-- Generate Rx Channels
busy_o <= '0' when (rx_fifo_full = c_ALL_ZEROS) else '1';
rx_channels: for I in 0 to g_NUM_RX-1 generate
begin
cmp_fei4_rx_channel: fei4_rx_channel PORT MAP(
rst_n_i => rst_n_i,
clk_160_i => rx_clk_i,
clk_640_i => rx_serdes_clk_i,
enable_i => rx_enable(I),
rx_data_i => rx_data_i(I),
trig_tag_i => trig_tag_i,
rx_data_o => rx_data(I),
rx_valid_o => rx_valid(I),
rx_stat_o => rx_stat(I),
rx_data_raw_o => rx_data_raw(I)
);
rx_fifo_din(I) <= STD_LOGIC_VECTOR(TO_UNSIGNED(I,6)) & rx_data(I);
rx_fifo_wren(I) <= rx_valid(I) and rx_enable(I);
cmp_rx_channel_fifo : rx_channel_fifo PORT MAP (
rst => not rst_n_i,
wr_clk => rx_clk_i,
rd_clk => wb_clk_i,
din => rx_fifo_din(I),
wr_en => rx_fifo_wren(I),
rd_en => rx_fifo_rden(I),
dout => rx_fifo_dout(I),
full => rx_fifo_full(I),
empty => rx_fifo_empty(I)
);
end generate;
end behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY design_1_axi_gpio_1_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_1_axi_gpio_1_0;
ARCHITECTURE design_1_axi_gpio_1_0_arch OF design_1_axi_gpio_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_gpio_1_0_arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity S_R_flipflop is
port ( s, r : in bit; q, q_n : out bit );
begin
check : assert not (s = '1' and r = '1')
report "Incorrect use of S_R_flip_flop: s and r both '1'";
end entity S_R_flipflop;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity S_R_flipflop is
port ( s, r : in bit; q, q_n : out bit );
begin
check : assert not (s = '1' and r = '1')
report "Incorrect use of S_R_flip_flop: s and r both '1'";
end entity S_R_flipflop;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity S_R_flipflop is
port ( s, r : in bit; q, q_n : out bit );
begin
check : assert not (s = '1' and r = '1')
report "Incorrect use of S_R_flip_flop: s and r both '1'";
end entity S_R_flipflop;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_214 is
port (
result : out std_logic_vector(7 downto 0);
in_a : in std_logic_vector(7 downto 0);
in_b : in std_logic_vector(7 downto 0)
);
end add_214;
architecture augh of add_214 is
signal carry_inA : std_logic_vector(9 downto 0);
signal carry_inB : std_logic_vector(9 downto 0);
signal carry_res : std_logic_vector(9 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(8 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_214 is
port (
result : out std_logic_vector(7 downto 0);
in_a : in std_logic_vector(7 downto 0);
in_b : in std_logic_vector(7 downto 0)
);
end add_214;
architecture augh of add_214 is
signal carry_inA : std_logic_vector(9 downto 0);
signal carry_inB : std_logic_vector(9 downto 0);
signal carry_res : std_logic_vector(9 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(8 downto 1);
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
AmpK8acAnD+gexoyLhzVs+yuz1JrRiaGO36PIldV1PGgrz7oI7p/NFEh0dcFNVJhFLWQcLGjeFqd
eYYIp6mhCg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Nxg0/rxSYKOIBdHau5iJENsPKzYno34okH0CYmsZbSPwzBaeaB8CwNA2dJoe6WbJfzb2O5IU2xBq
1FYJ4/QIBv+z0bLmAmFpk9nrM0DZODVOHkV+O+IeDWdb0Q/AqwLkcTSXSJBpKJF8cJUdUuMjFSug
yvL70bAXDHDTkSfcB3w=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ApRdAWoHN+sxNEmRjP8hKv0QMUgQW1v0DMb2D79dX/oCbHgZjK/tPNKh51UOrdVntEwpaueAGzKQ
7pI/ffqfUIUQzoKemwgGgFuEGRaJhFbGV4wQ9Eb7E0bf44qxDkmrponDak4rAsImFdUxzQdhb9wh
6FetF6FZpmL+aJnfxYVSf4jKChMurTP2vrSmcLo8+KySmT2jym0GiU6Ti3ZTpvmNq6zEf1QK7Swc
j96FiO1bK2sYPK6NXBIwcquj2cPIcKmV0pT17bgCwFCRqrICoCh7wSKBQZ5r8Z8rfx9ExSfQcA/4
KHISIIOnJItF/BQoYRO2Z9Nla5GT6fUUQkmZtg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oFVCSTsbVBsMphDlr6ZpaYD5CNICBjtvOaEq6bb0lBPIul1SQsJrM5rx7Q2GBVX96S8RQbtDmJzF
2G7J4+R9kZTXAdEmYiVodu4Ilu88mANYOv+KOYzfLEPbDw4AC/0oluRYMisaqligemurg3iPeTor
NIywBnsPkv/0dsHzFWs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
GD+PYS8JciSvOjM8CTWA+/6Ta7iVRPOw+SjPfH9W1K0MpLLfg/mQDGtAWke49T9nCEZZ3letJtJj
TTIbZktXRnl5OHVQ/0Xgw3yljTo/vj4vF59Uzgththr8zy1BQjLc9b4P/qXhmvC5kIXPURzclzPQ
OxWS6yoVfR/YxT8pEumNn5JG0WD9YQ4sEQyLPsL+dgPH6431NmcdTac8hnKSpBRPTPl9Xo46b8yL
a3DnVtwDufJryEYouKyaaziXHytCZ5KbT9sB55YSabfGK36yMYCmZmBblKjnO8iAy9HRz3qU0WL6
yKXVIVtCT31uuuUjxte5j402P7vu3TSzfoJNyQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10992)
`protect data_block
f/Fbp4LkeVm9THDHbzqs7/KzSPt1ycAbb61I6TUfuWgIEuGXqT6W3odS2Pj0MKrizmsmNewExjam
e+J2Jj/JVZ/317mBPEUdMYZxwY/TYA7QDqmRcHKNuemXLLPsQf1wJUSAG8me1crAORX5e6l9pf1P
K0/dUenwLWCGTgd/2KHjWgMZEM6vAVtqETKfUVT4d+zwZzDM16szYx4DO0R4b9qKRZeddtloJ9ay
jFgl01IR6j8EWxGye/MRZkWobpRTOhdohqRDLicgJyW/dD1u5yWhLaK1RkOcgERqHRBQj09vYBZ9
cusK94LErB5t0o4PSnNbM+xUk8a4IRz58cDJ5jFuJstxaxDR9ZcULX5qScL2Pa68M/JpJamT02iB
up9Zqfn5taQ4kiF0nRJORzYY+baUJgPtx/PlPvTIAn13oBGxopaq5bfh0pOLA4Zo8cAdrYUvLpt1
Vow8oQKUFIjLVRyTtYPfz3YjbqTsl1N8efMbR9Hu2Dm/lHhPL3TIFiLRs8umk+608RtPhVMcXy0y
Lsvv7nOClCj6cbbOq2uaBpNM+XLWlZ59j/L1WzDWmcZFn6FVewHFyCHSX5ymq8quKGdJz1RrMLoV
xkR/OetZH9Yy8EXJUkCLhNnDF4PL9yxvCCdIL1lkSjqIGSrbIzjPBYWakLFYoZM6kz1TbmxbqaEv
TF7F2Zk8uvE9NM6e0sneG7goQFxI2dcY5iwSpJPuqTx1SXeGzjoT2ylsySDpJhXreLqVd4PL8Yxj
i56VdgHU5jFXd+3czaYmt+tvn/KFnT2vodibLB1/r+nvRzX14TotKQi/xqP3VhGuJ4Tedtt+07yi
1r8ASnvabkCNO+zAsNg5x07e/FEKsKnpQGPShe8D/z37k7PEaFTfldKqKe2Ez4Zmz4cJropE1F+4
rM2ZX5dq5peH+oD9PCuXuNg1pplejVYq+OPuoX5fuOHlVVKkGWmdcPsfTjG1E2cBB5rXrPiAFG+v
bMFHJeRKWXRGRF65q1lr80VGsqgVT32WjBisQwMW13bnMn0fS0gGtRAYWvGd2CFTDDRxH+XNliVM
m60I4+GpxO0s0P/O7l3FoFFpXy+9Y9oV2g+5vUPIJbadkvJ/TcU2rmZBCBD/O/nyUE1ngV3mDqGm
9I+SArK+TK/FlF5+FlAjoKfTsE3o9SBPApggiuanM75jP/GF3I3XAk6xR+J3v9etZJRh7WzMq7LT
WXL3kaxIfHCfAnDwcgRYqAmHBZilXqJqnaypCkjFdeyZ7rAnv8FL18WOD7FAG+XvzzXjcgwzsWs5
3kDRbWFhHN8JRhCTlxfqTVbpMzskA6MhZGzQKzVOt1p5oQ/Zl8KKqBpZjfCuFquAV0ute8ZRvl0I
zTsG0o7SJ0QQvemjDrdbUQ+/+2GO3P8T3s4AX5jFqI4Sx9PexGVpedrYyKp0SKht1FIf1k8Ui9FA
loHbkM+AUUB9E5T/yf/4q4LPTCZQXRL2hkRcAzgxIZ/Z/p8wR2NfsNmc07ShU8niYgG17hjzLFgx
HHOd36vG9VWKy6TJdhWNHa8C5AJdVz0ezYUzDajZ6zKWtpw3dvRpXH0PKZWmBxLp1uOZidd2bhCV
LY6+fCTMb5b4XnZdpWAng/issCNkgUjtyGy5AazySw/zD7I8ckO1iwscbfDZJDIXI9S2Lm+PCT8s
2wxhyPGIlyuXUbyC/d/hNklbDgOIsNkTxg6OlH2tC9+1ES9QEVFJQjX9N6tv3KRwSQks98luQEhX
ca9C6qruOg5FZUZePCWhHywo7OXIf+fvWhV7pvQkCfIDVtPEc0np+OOZGnrFKW60CG2il5HesgiX
1J0ihBOApDwAQMO5dHl3ry2XVuE6+Wd6GagwQPYzdrYU0vOhiCuP2N5mWjz+tYmJHFNRLWvUXTMC
XsfcecRir3ZfsNNE+jbHhKcd5rtrmFqX8Ceim3JKSyWyFU6bphZ0mheuIln5tjBgTHWi/4VZ85Pv
q861VQUTc/pZYYvVWXncwY56mIgGCJfyTsv94tJREFPq+V6y1P/gVBurNGxrTRdkZv0+Y3QYjB6/
ryaXsr5/9+/2hdRP3BMTXeZYLm5zhSdaJ85+w3C5fUEY9ozHPl958mh267hHeD/RtfuVYWjJ9TNe
eN5ZxRqrIqkj4jJBvJtL2wdZ0/TD0C0wtTxIT3SktxItnyswd3OCzGIUADQ8SbtDjA7hpQTd/2x2
EflhIomFLAsZecFnRKNSplC3wDmtp7s5i0YQqJLMBKcDvh3ADYr2x/Ttivi7+RWMkfH2wr3tl03O
q32kYajklrCyDxx5405GbQH8fiYKOVTsj6UPk3sku883ZI9piX/JMCZdzS+GXWk0vvKtr9IHtD/n
95SKbCS6Kuo18nfiGRQqCXsaZBCOnmEyeJEhkoPQGbLlbeEKBb5yGXafp/aUV/6HUTwLBYxsCm63
N3tlKhuw3aUhu4ud57ao3LpvVLRxNW2Wfon/O8sqH1yu9JM1AbZdKzjf1KuwKO6uEe+2m4A8p+IK
64iuCIe8sXaMdFf/dXZBK+QnEZufcdGbKjW8BwzIKC7pj8CHVrvBpQKkDLVCP9fgmj8+loCogpln
lYfWrYiKBdoTakf7o1MD7TLm4eY1u3+DObDBI95N0DtpRSTkdm+g5NlXESMxW5k/RAsowfbxgT+X
QlJfEBIUitQyERBZHwD2nAc3aCWdZDhPax7gothJKle+iTkgE0lZDHT8gc/LOa7IkqEnZnnTs5Tb
QSTOOco6pn8F0It3dthq5YWF/nS6m31ETyoeKnwLMGK2zLnb4GwTOdjRM8s5Mbmp9ZwjCnarJI/P
Bk1ZM/KJVrB/2AG961fzhmz1jabgacd0kuU1lQTaYHvNnEjQWgXO74emunYszRCPSb2HvCiTOg6y
9DKkmE1fC/MwxGG0XNOaMOnStEW6gvlz6Eyno7ms7M6MCh0TLqw4J1NtRPTdRHbSCILCTi8UoHDM
AbHwu3B0O5mZPg22uaIjlypcV9/AyZuk4aDinajCHuDYIXh9y4Nhph91JKd8GExGzsXa7/JX1m65
DPjZVZAZeAYHPrtPySB4grbX5iWdY1uIQFRsdRgJ6Z3VtWDN6Se0jfd0IiadXtZMt7pRcxJaozrt
CtDFvlQXCvDQkZk7mRg9Ixd9lXWBkaKPEMxgO9j19G+K9U1U0xztHbAlC0GyzuYiAkIHPODTgrmg
qUv12GkLqCPODSS08QRoPtCC7tyevIj8V2Iknd41c7unzyp+fl2plTPnv17Cv5pOV/yY3aAhYecI
MJR7LQt3EiUyh7YE6sz+fNXfVPxRk86brfMQaoPaDc9HABd7DBNgVxAajtSHvU18Sh4JSpiviXrr
mfl5Hn507c5fP3dg3pLs2GpZ8fAtYOHFdQk6th/cXaqwxtKXKtEDees82KXHZLOig66wNf6GDQPE
8QLttPOtuxT0Nrp7cnt8gnPeaztx8sRSR0C7XO37YDuLUyrWVxWcQMbizuwyOhnnLDnFO03j8J2X
ODjbjn5FM6xnhfOBMjYQOOdbWNwmyJdOVQjR+ggKxY/dCGBUIk0jG0BsUwR3WDvMDqnWo2V/RLMT
ZVU2FUDuJKpTNmbokp0krCvVhQeEAysQ76yoz91gJATaHA17u51fllVOetfjbcs7XEzT49UsyOJc
VpfBBiEdpDo1xeDugkiKEdnaGRNv34Rs9a8VBYZ1NoMiRXqmJiMoD5mfI+vlQYDqDjMFUNewXrXV
K5pejBiQ1+Sob02kWClkSq4gVfOdY5ZiHPlPin1a5v19xQjBC47bxTvtwmV5PNHQ6EntjAmB3gyZ
VbVZhraeaYWAQ5olwlAXuLZ0adywF/jthwvCdvXeDjg5MUeG3iom6Vj0ABCcxe92rW0pmH65xRnE
/ROEMaj0F8Eu+eliHKnqGK318mayVtLO7P8WiPfqYUKVMb4T+1b3C60v4wDR/Ig0X5Mc0xX5vzbw
XRnQqVgLjVUp/VJSkTjB0wLsde8vjYCK41HbnYQ9Sgi5tcN3XjRDeI35kQFOYEjUAakb+PYG2tpr
1flcjr/9ctBCsb1MU3Z4KHqWuuvw2hmvmYz2RrveksbRGPcnePD8ddMLWSjZqaYED6istXyUxwRQ
5dUAuvbeQ0zzy8IDivjMUdVadDbg+33KzTvpkX6VuGT/YXMXseGogBqfb9cSggAg6VQdL8I2Wxnr
5HS/P2wcaE4KKe34Yj5NDtP/qByntjSz5ZAp6ntPqkX9jqN2/kirB90Rsgmn5jIpx2BnzTJqEJ3B
zIwIOsA0XdKg/h8SbdqVPIriGkSHSwhO8BPxJyiG6jsAz+R9JDn584lWJX7L9fe8Z0E832ZcMq47
5LIfa7Uh6XVRNDIrC3sC9rY1o/Z6sL51hgB0wa8gNdE4CUfC3GKtoXHLErVLLeaqcqTRPB11un9f
oXXz07rcWeaucz5jYKPMRjvEZOECErkxBEPaRbGolBxyc9aTJJjKdJoQbF12V8zxHMzDdkGubEN4
UOTPcZk5AaswA5e40bHxItpC6h5igtIvzvgd9Ck5u9AABhvcmqvmQCS9xx7JYVNonF9H5gNaMtI/
LhRpty/NbJSZgn8C9eEAobXl1c3n2tB7zRxUNiw7VYsq/l7Out+P/WkdqwnT3WaDTzy9q/NfKpJu
Y49TKPTQSVZ7yKeuDbia+lS5HRA106gh+gM081xYSr1unljdricFlR4VX5Bnbj6VgM/DQ4dZMZds
zsUSInuEpQ8YML4dT9pw3PBF6qF1VAk8ElDeVVeGFViSupRdVdN7LzlfFXk7RgneTSEBH6h4qA3S
fJhZF+9MK8dEtul40oJb+rzVwqhs2Oo4F6mPTY4CfTEvGAxrB7beCTHZserzeSQ25hSRFFT6ZyIq
6+KN/gtxV0nj1uk4E9yJtnIhrSUK+H1MxkQUsk9B+BRsexuQoZTtdK3bkwxFCf2WyBaLFm/IYrDQ
dAtIuFajYkwsEkpDKCmxhUisecgkqAY6DxRwaQu8njgFKbxokiG0wf+z7RVcSp3nPkDxSRie+sfB
yJe7W4Bt28LIF+uzIsPNQp0tgip+J8DqSoQ9RIYNKeMflVWYKwV3muJhUK5+PuywCxd84ljkkwRi
BxeBSCv96ZGffi+b18C39+ViXGizhMsIPnxJn7KKc78FYXgP9B92I0MJlQiGNOeKWaRlpigpGYZE
67X58vDfrQH3nMmmQe0oaE7H8NaSQJAunqUXx9QZ8T9HR4lTCKx4j2Fy0YpcC1gg+ZAZYasT/BPB
r8HiDJPZkx02ljpu6Gy+tAghcfUMo6xVXH2Pbw4utc551iZgZ1isKtdfJ1RQKERZSCHhSAHnTPTu
vtwvuPeNYh3oRoceCjHyEoQryFFW65p9X7YZoZfAYW/jMtChV6n8sEa7l0/iUm9wGNkq3dOcLz2+
WoNG1B8yhmurmDVuaERx5NC3nL/dnMEg5ylTQ0e0vOcCNpLCHpKCSuHKgZylEkJdhYJqOf1N9kg5
19dE3I/OCwUPfLdJgZeUPy157ZwMYyn8DW2CaRfTeO/VEXVpQhwunaOASu9gqBK4pcMbeHtMLDr7
oz9qyaqx7fnAVMrjOq68K8upg0P7GuUehRrhyOqVTWbbn0d2TpKuKcYOyXkF+EESKZSRQm7ElHbE
hNp1xRL0loNiDlCH5ALeCDAsvul1XnpGczCKmkvdUOOGSSPa39CwRD9L2dS/Aodv77kLqRj5Xw7W
n7UDvRE8Hu0ElYXyWEYbd09RGYF0Y2LqpFheKqijHtefwpr+VP6xfsn2krT0sEuQJEpWEAy+ixMx
j35D82DXQ/rwAg7tOjyBYZw6K6Ya4ejI8MuyBFaQzDsQwUDoN7fjNZ41ZyfB/Uq/+vqxQSabjJH4
7YYBebw6qwNyEHrb1S/e0L3Fmjz1VcZM91A9pkBQyQEqB49qHoXSxTIQYj+Rby6RFjG7LJeRaGB+
kDkPK3l+MNDJ7nUqyjSMwx06iDRw3XvjJ1AQad1UZndzMQW9U5UOp87bmaeKGX0EeJcFSt67CCPt
iI9DkQ0ep9JFmrQ8k31XDmaVMBhJaY3WEx1CulJMr6kGFCx8AO8SZz/Uj0dDP23NV9+ObxFJkAmg
wOGLlRhbL08+nmFzQIP8oiAiPxJGywCfe5U3p/tpCUam1+5e2e6079+K0FeRhfntztKscLQ9FYpL
LKnC6q3yxdBvgbT+czhHnF55m8SsKbCPE2kMoG4MwDUPy4dn9n8PSh9p5WhD0T9kOyiMs6V9Awn6
u4rhrLE5sFZGYHHINbJ2214P/EQ4AYEvwos+eMIuVp4ekSYvJkfHME0EQembQlvkI+EqE6yU2//Y
rRXGSscq8NDHA5/R8CgsbJa3WuQDkz/ApGnQ5CZuKOmwhE/vbdcb1NWVMkgmoBdgVx3EpnAQJePP
znfiW+GyTeB5vD5H5u8NXBhLmcuUGCYLzaS6y2upk6PId/g7yyNcfwSMopEju/Ru0xtsqDagXWVH
0fQq0hog3t4EGockYK5zD6VJGypPgBIFByHiGvO2M3VJ9ZEDIWy9O72J5UDgFfnWg6Ptl+2oxdqY
LEC+BRrzIF26EU9Iwoltk5jxrRwraZ/bL6uFRBUFbBdf7fullfYcIuKiAnY3LL24mpvox4T/TgDA
7HPNahx/6S8xJAyfNQd7rfrwE8ugSLBOE1fywaFXDlVCTVT1UhCu/IvkZA7yqOQn5ic3QR5EExuN
8QUo6CFlk/dHdMTkjhryg29fJ2a7wduZEP1o9NL2GMzwZlvE3IcXNxcWD/LPHBFfRKUyj7xnbl0g
eD9MNSI7pViYTz9lsr37cAOtzIi9vo5TPPm3QJZhSvA8ofWkhrbhR0GUF4RatbYd6iqax5fTUdxH
XbZif9v7TbIhM3U6I67VUetEouY1euPG1bcWS+T8rLpKxbz+EWITX1DNHSC6NyH7wxClHu72Z09D
qD1e+XVwFkOO+CvTEkXDBsbYuWoUv885GRNS4Sdc1rol0B2iADyGMj3HMzYzHJXM522nPvY8CQ1h
5C18lNRpB0a2nAJZ0Ieq3zAcAX2eMuXQGMFfQtk0+VMIScNwYHgP9lCS+xBMnfk/fhPdNftB6H2c
qwCZfup4p3l9oxM9kJri+5W30U4S6/jOMz6W7VYXM+D53PshEojFq66fa5n5VAZAnidO1ErDVd89
Mwrm+fhpk7S7YgjMXFBa381ButpviSVWUtL+hHxJNAyaroayX+hq205B16wjbpN3BgSdgsi0/87A
xzWaW6uqvVpMRtFc4yBaDuatTJYH8AzAxLq5BU10pWIkA7hZZyn7qVHg2ef4ZUFXvfXSf+trLJOx
BRl+5CL54gV4Gq2ICL5WWhDEAMAT6hi1LdGn1y3zEH74lcSkgbauSY7n/nzRKaTsvjKWmF5tdilx
hdAp8UBB+VpkdO9WRQappKTdV+pWEXBHAW3zwTdyjD1lWQldRuYSyi95W9w2eQWJPrIbf3Dic8g6
Y4Oj4TPq9lzVUHd7DdOFZ8hRMXMU+iFkxGpu/nLSIoyn14vgFiO+D0MNhvIAWBCU+dnoIZe8Ihcz
dSynCrZ9Z3G9lzmQlbHI/yrOCoJKUgVISq23Y+KWruL/FYtk4Y5wcGmDA7iM4UnxS0Di2GCd9MHD
8egOIcVxvTFXPZUsvrnqNDqTOondq8DAqGHj/RHXu35uYCvevGZRt0gGEp+R+fZ8/9GGTwlADvq9
EVezzpwrgswXSudTGx0qTUhODFVlrc7R1GUjNbPEc6yQSqiEHo83FrcG8zYSZkDWWuIkMah1C7uO
KoeZ4pEsFHEEj/rsZRoCrQOxjHCPuL3WLU6Yo/EolvpTkXBYLzE89T7ov0aVLZIBkvZ1a1fby0Yv
iSB3kEgxJAgpgKCs9eGh4wGxnb06NqZvoSTKkwpDsB5MdDOcoaaEGVn/lia8ZlVp75r6MG01054v
Zi0Y8f/dhUVcywVz/vhhfPFBxFM2d7q5w0ep+zOsWZTBmWaRZX1nlt0EAiwIzRrgg5sqwS4IhqvB
pfI+PXh1MbQhPxiYtCkUk13GlKdQZCmpSmgvVrkMh/psUVzOS5/kMIVq+GUbGJJYdkyI5zraqE7r
yg5JU+pLcGPnqEnNSNmCLo4qUgU/etPVsM5Q1dA8zlb2bUSK4fEejBZTz8pKFr2MR4ro3jVFHriI
Q/l3T01OGRWxlcSZN+vzmNmyUfRjtzoLhaKv30RTov9u6qP6K2vVmT4VupVYMBkO3GgkWKuWVG6R
bbZ3fRE13Ly22qcnG0WIvvbsNv9/IYjSsFmi4dZ1SaCSJW/HPSncXrLcEPB7GaF4AA7hNYmF0DKL
bxoLMgpfNm5UiSy2N4gno9XyZBGmZEuNgCl6cecTQ+IbdTOcknawNVFV/sLAdFoZfYptMSYkCth1
YE+tieeVlGL/ZPQOu+ex7mIgD/nHjO0EZs7+lN/C9/PjomJ8Bo3O/Z+UfLlcO1pY3evgVNIxPAkH
r3FtZQzOeurCstQzbUsDtA40Xw4wdIf/5+EURAiBdvATmWWPGibjgcML6+cWpAL3WVAUfJ4c+FJH
vTOgfKUqmGiQXS6MCf7lVahhhXCbenrEou17WEzqU1OAxhUqdZoLqOYGVbADb3epiWi0Paqj2zib
KVlCFaByUTm7ZmFEeNwnN89ct6qwvgyb3R4nlp0oC27pMHGrhhtxZlF+2UfeGD3XF5uy+hIxqXon
743quGnHjYtfdclm4Kt56OFy7sPGcCR2YhOeVEtRqvkz1XSA8oZ1pTVYeD7vAVPNO1Z4G5854IYo
hlhuEOQWEATdBqzj3Un+7m+HbC/VAJi+6pwROMsiN3QCKOEAZeVnzjcrKPRjLQDBZCnWoW/ZgAJx
39aDDn2Qlh6JazaHOANHBXSgaEN2SqJce+GvNNIQXO2hI8HH2KQkjh+Zo8CjIE3+6dfB3hO0/IuP
PiIGthFakXn1hqXgEZcFtz9wFP/6AluOb2SJjQCLG9GjtVsjmb402uH6snpIiVVFSgrtV05mYZUP
5HINYv+NIJDFdn0IhmdVXINX0qSzGKZQwmn69y5QFhxZ89t6RnTYOZ0PzyJSeu6f20U9nt2wHQHD
54fiBkAi/c52AWgmDFP03mcuX2g80ss8FtP+8hD+M1Zj035AWn+KMLYzhKFkYWyTS9zbotd08CQ7
DBzDP1xPYwD8P+8WoPnMJpGzGlzDpnGJiw6wJ12vr1PqVXQG32b7IqQxsK5MxsCNR3Mhw3BJAVVW
XO+QYmRgmNvKym5zwmz/fddLQAJerQLcCDR4mIjeHvDTMVv6zp+FqekYBLb+jwGnuvBmEcUXXjP5
ofdPKDPdhDiNpV49i5NqtHK1sA0jsHiQ6OEV88G34uTI0gNIqQf2UBhqXTaW0p2jd/HqI1JGtqXM
gpdlEnmJOwMFcB67I5KAPfpdaaYeyaMzYzbqgOfDyRBroCBgtaNPO+3VYrXCQ+Dz9JKObWT9033K
EQ6me0bC4wwfbZFq0hH5kyi0/AC33BDBnJmwN1t9qNLcsu5Wku3VELpaVSoVPbjblAgbydTNC3t3
aJQ63wS6EX8Iq+8u2YiH8rAzGqX5rWwhqCvaaczbdcqw6mdpeCzNjVWLqn9p8iKqSM+vpEbmwtAQ
ARKGX+qwTpV2lJIYdqhAV4GbkUt0iZE8ciAYj+v14ziMYk9k01OeyYl6tvJtw8Z/VCyQMyWOIvh5
WxHyv6p7QDeZhMpZdXwaKkXjjMZsAmVSiBf6uRc4GS97OsKuEs6zdQC5kQ9DaBuNJcyGxRDcUKYg
RT/LVCPlp3eOfCSf3NUwoe1Tk3pvWaEDqZt14Yu6T2K7mtJJDXplnYRlRYmiTc6+mfy+/vcCPSlw
bk3VwED0D815elquJ8TtEtdfVGmkU7TVG2qEeDvKXw6xqqHI837sRv1Lde0iKI9zEqoK348cUewK
JEokg0IyvhQGo1GqQMRs21PTAkLGhCsQdHmvBnaxTlQFMX1q7gP/ZZq69M+Pduy53SirGTZKW79C
m38ls60+CV1squPtvg52sqkVA8N3IJ7loXNa5gtKoY1O/qNmvkIlXofEhFNepo7fyZlwbcdoV1Tr
QTaAckKeUf0dBuP0Cp6watRLLT6pYNJxAZid0tmX2SFxxaYquX4dRai9koGDZlaPxL6IVsTwbzMm
XuT1YVGU0i9EvUvTKQKcnMg+7jrcMYC8ys43wYR3HEgTkIimtygrd/4GLT1MVCMR+AyDNJkI4B6B
OCZkisiujk3oJVErXxLUvAqvqOhJAaIEokuktNyFPYGhHVNVvPLFHgLj4i2ecq+82hWLqZOa67s1
2osOIG9f5lBBlZXVyaRu1/PiQxWd46qDMLr0qHG0dl5NAaCV6NxfibqRYTqF6OgppXcRubPGY7eN
y4K7Qc0K7QuOP1elur2W15Bia8+E9NMhmhN1yOKnpGycaqxWY5F0bXfLCriUwXefqQpPxMBab808
qhDoXxVe4fhq1w+tLylFckreNYFtd9QBWR4Snx2Ms1hUE5AT1wU4fsj6lh80LQK+qi5QxU5UukEN
1HqdyKZITi4qWBZzqMsByamWkXBaEgHFRH3HHysf4KUL+T0zHvL+rknXFQugA0EtqB30srYMFYk2
iwI9L6AwFkYJgsErQb0lCJBJy2rgvdqxjC8w6Um6tP/r1j4q7XDlgsK/lbK+XGK3hwiqpXxbsxPy
/szI6CQa1VaLK5XHWkH6VSrfjWwpNN0HEDEziAWHonNEAOfUNor6IZAUIjGWwXo4SXdeKHZg3+Bi
+m+3dm/WcT6/vvXaLpNel6Brtpl2A97w+5hE02HtnwVfKwFOvCeSpvKhqtVDXUOOCISdkQXz9k/T
PkqpL+S7fDANfP819IQNHPBHcSNxSXAan/lusDqP4Ynn/oGUI4nLyy+qJZWJnhaqk1b0RvVJSlIC
cQQubYg8oAZQS4bZXm8RwFrLrSZ76SCMk3KZKykEK8bmsCYvcgd9/op7dfqM1wIGJPn4iugQ1TIy
9IrIeOcjs/cQvc0r3XyYM9QmaNcg85qihRPhlIXCoBjpnY4inxkcVKLpAUQAfe+2c8bfpeW3n+dE
zR5bPlGeBx89P2jm83p7KWILxrXu1uQbChAEl4oaHV/Ra/o5GS4+cGHv5r0GP+FEGVLZ8iXP1Ubc
RAoRLvfjRpJFcqoDoquC6AxggvUqJzQEHqFslxo28Q7ZPNyQLupee5K9ZOzW3pAyrLDRYFMaCKk8
zVJkPIILkn9QuD5c6/Aj6ebSR/n4P9NO5QxWbH/84Mag+R5iExXf98UYXayIexj6Gu5xw7M3otWS
SVh260yEbj3Zn2KNReJq+3nVyT8q3MTJfL6jXPRHKN3bzUXyQAnJ256gGMDdZAoBdGecUzzb8qnn
0rIyiIE4ESGlaJb2XP5BQGrAx/GaAhP1N3eHFsTJFwW4PVtVRl2SsHKImlE0SS5RTW0oJN9fpxtR
7V0SdPOMkmpIkIhSUGgO82c6J9fZxPMIMgflQ+19opvYDSHBfpz3SfKM8Oii1buAj9TgSS9rp8Gw
tb6Fu5nNrX87RsIaC16dMUUTYVowdwe8qj6U+oBq4olmBE0vrpXLyCN8FELZDFaiwxmZ788mek8X
nSIPUQ4P0K/raIh45c9lFugd9M8TkXknde5JriuJzTLXtMclVbb1+5u0E6Wn4SzzW64zZhOurfta
MPWbxcQd1MGo/VOkd3ZzhwNO/hdCS8fAj6tIMn+h6ZNPzfPrNlvo/780cJswu8lrrBBnnCbvk7Q2
WJBxcjq9OiHQm31yOGWhGgWtJISxW8hT/Cvolvbwn1xq5CBdnHSTt090FxQiN9t9ltNWmwYnxOiD
dc6eDAOcIIz1tw8SYQbdM1QT/OQZjiZk4wXs8Rqo3MYiBEIAm2eQlLNaESgp152larRrV204suqY
ZVjsr1l25akhvERtLXcODnn6dbBES9Pjm7l797pfMrgq3FbsIxc4giOZNEUSiZ27kY8D+Plkt1nG
iCLWP4UjiSazuext1XYx3G9qO9Tf5ObRNYMGzrFe4pOBu6dSzKl/2eA6+xlNt1ngjwJ7h48Ex+Go
CCYOTfDCG+17DVmB45vhJETjhFrOd+BMN9ENxdrUysOnP+k25o0ejVpKvBiPTVoX6DrIAcG43TRb
W1DpeeT1TOd+QICH8Ge0DKJW3Ppd91zyzNZ1otc6+9fHRSlxfI07MetbJy64B4YEq82IBMD9dd28
2qk4hYDyq+kjCXrKME7oCBxYlTZgCKHW1e3UkuzugwPcwBOnJAc8ap1GJeEg3D19doKY6piNfPPQ
+AkcaykAijMobUxS1bOy8Tx1ISR7QQjH3KBZBscUJOZ0WGTGdqjXM5HEC+Zdxb6fIN76gvb7DwBT
ORemxLKZwcbwv3c6CYUZ+VUmPRUFJXKjtBQIfDN1anL3JZLvxtQxa5hEcfDVVIQ0EZl6D3dpOfoF
MG8/HF6FRGNuQy536oBawRuXhi6JBn6EXkVpjKHKfJvkr9Fx9u/Lgw5fw+4SRcSyLGexDUj/i4kT
i0KEpPcRr5j3UUAujAP2x48HZrajr8K8VB1m8bz9Fe3WUr2SEX2304zU8fds9tq08moX9q2AWLh3
lJ70oiU8W55fMR4Zg4vj9KGf76MaY/iR2i0ga0fOGelfi6zsi2v4cMGgWqN0s97RARSA/RoEWvGz
Z0J5gvuSm1flvx7TCTyLnZ05wVbadhJoAjRLai9Ga5p77OI8ZxNRcuA80ExCbrGzypLCbbep2ooU
lzZCGTR0fTjIYnrzU3ihpCst0LftIYRY4ZRkll57EKLtrq4euXAv2K+Eo8rXFHx4Q8CTI02YhVIS
3eotWEHvo62SBFeSAlbHAC9jjG61EN4FcN21ExXiFhnO+wFmvyfq8CSr2EEluYQpI2wMHKrVN8RN
z+qg/xQgBwiXlFdGTNxMWR9d21H9h8hhtUaSNYoO2NtgnOF6plIie7ofla2iT9mNLatXRXSfmzSE
p9sNRujNrB8Ma+V79wpYv7gSVqw3ovmN6VcsVT60CsVID7/8hSh63ECxq4sBfJezlxYsFpSU/8t5
P5VaBjUEYgTBKqooX5h5lAXn7WtC4+0SRdkY+zOVtLgigVft8+NB3xqy7C9cg101CF1+kE44RCWh
LY6XDaqyZFRxyOVLvDhd0k5giUT2j9E4OSz069K70xe9vo6qOo/vlWXyzzkMbvd6D3TGDZshQZAS
vVkwVYrjBxpJWTDcTxtMRH815cDRaKfOUqRmZxzGadIMtBhVpe9NCKD9oHIX/1MQPnjZAwccbS1+
tpAxljpbeBFDESZoJBwZMcGyNKWHyicrD5U+I4R3vMxCEFHTS4+oKt98hIXP3umoQ/E4E5tPd+wj
IUGpuOAMuyt/P4FOKh252jLgncbhE+/2aBI7sk1m6o8l9suXMejF/wIjjHzIjILpPopm2sjxoayz
CZTD39SEDkr36GheKsHu87BupINKHoobKq6Cf0D0bKbtRJ5pXqOytSKfSe6e5UkIpksWxAR/fDgx
5CkqA7ggFSTqrqYklry5X8qYshkwabLtlwKnljnujBqX/aay/cLYJ8QRkkyOzqg0kid+ctkpgXci
PYisVh07a/2dmohq3rITM/nYKaDCI+Dt2rA8Kqza5v4n/GR0ZOvECWg7nUtKbjrHQJ/KHJH1CKLC
LJ6fw6su+CZP7cvwPIwsSpTXH0hV7XvYCfdm97dvaKxomBXgfPa0lU7fAXk459/apK2PzhPkPw0w
VVHDjkPf95YuPW2ChV9hT8vZyZN5u/nsbfUyy9AfiC4pkPZNREede272qZQ/7g/nVzzbwybfMqM4
RJFureBDeBn3tnmlRZPEH2aW/vwhpHJanMa11mKsdd/tYGMSzRaMjR0veNWDB6dyb2LsWrTZ/BgH
RB63CSp6pET9OAo6xGptJDG15w5FGIfg2NjILF9cd6izyOR9X5uolGEX34r50bT8atiXHs582yIf
Z7r7RAbXq0CZ4eSvPfP0wb9aOsX9Evh5p/OR/LzN7VNZd78senrt22rlI16PChcl/CSa0DjX0U/a
NY7YLXbJ5I8hNnICRWOVCi7tIWATDO1BsHwd2pR5C59FGDqNG6POIXhgbVkjMU3IIQOunM+wPA/D
WxeiBQFP8arc1Mfad9P0qF+cS2kRwMRP1jHYPOO3KA2BkizwsEzvsZKpatq6K1Qj7mzeoUPO29ul
C6MzzSPwMMLGQXNipiXCOw4NUr9uS3agld+WUqy9LxJ1WliV5i9fCKLAmCIivYp53CaJtEVMcuvv
cYzIh7G1AlLqgqQuQQwtPs1UPy8vEDG8gjucEQs1JoLlpHmDewcSelRUxrHYqY974r9PLYs3hWTQ
aEiDDPDRkrFG22de0LPJP3qk7d5KD2UeRNT6dZKD0Mkv4JkNgGXIhMQ3T09wiGSsuffAFZX4LdWx
wYesNtaJSKsvaC/RNgccW8DK/haSsrnJUk39psQYYMCFQqA7Ox6SCrQVGszuLBTkvDKlw/c71uJs
QGZGyySS8vszzpwpoAy9F3paZIIbnY118wQ73IUoSm87sywu7UxRXhwOLgFBPK05nZyhO3PRZghq
hA1f6opK9FauxGE6S3Mqu2PoaJr3V3hRZoOdYfQLce4+wOO1uA2+/Pwpxxh7qGxdeozyy3QgfDx5
+70DwS0SzJSmzgDnupfnO/Pid3o8KwgqCAwZzAQqW0zDcj5JGLTYCaETHXkpEaiq
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
AmpK8acAnD+gexoyLhzVs+yuz1JrRiaGO36PIldV1PGgrz7oI7p/NFEh0dcFNVJhFLWQcLGjeFqd
eYYIp6mhCg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Nxg0/rxSYKOIBdHau5iJENsPKzYno34okH0CYmsZbSPwzBaeaB8CwNA2dJoe6WbJfzb2O5IU2xBq
1FYJ4/QIBv+z0bLmAmFpk9nrM0DZODVOHkV+O+IeDWdb0Q/AqwLkcTSXSJBpKJF8cJUdUuMjFSug
yvL70bAXDHDTkSfcB3w=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ApRdAWoHN+sxNEmRjP8hKv0QMUgQW1v0DMb2D79dX/oCbHgZjK/tPNKh51UOrdVntEwpaueAGzKQ
7pI/ffqfUIUQzoKemwgGgFuEGRaJhFbGV4wQ9Eb7E0bf44qxDkmrponDak4rAsImFdUxzQdhb9wh
6FetF6FZpmL+aJnfxYVSf4jKChMurTP2vrSmcLo8+KySmT2jym0GiU6Ti3ZTpvmNq6zEf1QK7Swc
j96FiO1bK2sYPK6NXBIwcquj2cPIcKmV0pT17bgCwFCRqrICoCh7wSKBQZ5r8Z8rfx9ExSfQcA/4
KHISIIOnJItF/BQoYRO2Z9Nla5GT6fUUQkmZtg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oFVCSTsbVBsMphDlr6ZpaYD5CNICBjtvOaEq6bb0lBPIul1SQsJrM5rx7Q2GBVX96S8RQbtDmJzF
2G7J4+R9kZTXAdEmYiVodu4Ilu88mANYOv+KOYzfLEPbDw4AC/0oluRYMisaqligemurg3iPeTor
NIywBnsPkv/0dsHzFWs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
GD+PYS8JciSvOjM8CTWA+/6Ta7iVRPOw+SjPfH9W1K0MpLLfg/mQDGtAWke49T9nCEZZ3letJtJj
TTIbZktXRnl5OHVQ/0Xgw3yljTo/vj4vF59Uzgththr8zy1BQjLc9b4P/qXhmvC5kIXPURzclzPQ
OxWS6yoVfR/YxT8pEumNn5JG0WD9YQ4sEQyLPsL+dgPH6431NmcdTac8hnKSpBRPTPl9Xo46b8yL
a3DnVtwDufJryEYouKyaaziXHytCZ5KbT9sB55YSabfGK36yMYCmZmBblKjnO8iAy9HRz3qU0WL6
yKXVIVtCT31uuuUjxte5j402P7vu3TSzfoJNyQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10992)
`protect data_block
f/Fbp4LkeVm9THDHbzqs7/KzSPt1ycAbb61I6TUfuWgIEuGXqT6W3odS2Pj0MKrizmsmNewExjam
e+J2Jj/JVZ/317mBPEUdMYZxwY/TYA7QDqmRcHKNuemXLLPsQf1wJUSAG8me1crAORX5e6l9pf1P
K0/dUenwLWCGTgd/2KHjWgMZEM6vAVtqETKfUVT4d+zwZzDM16szYx4DO0R4b9qKRZeddtloJ9ay
jFgl01IR6j8EWxGye/MRZkWobpRTOhdohqRDLicgJyW/dD1u5yWhLaK1RkOcgERqHRBQj09vYBZ9
cusK94LErB5t0o4PSnNbM+xUk8a4IRz58cDJ5jFuJstxaxDR9ZcULX5qScL2Pa68M/JpJamT02iB
up9Zqfn5taQ4kiF0nRJORzYY+baUJgPtx/PlPvTIAn13oBGxopaq5bfh0pOLA4Zo8cAdrYUvLpt1
Vow8oQKUFIjLVRyTtYPfz3YjbqTsl1N8efMbR9Hu2Dm/lHhPL3TIFiLRs8umk+608RtPhVMcXy0y
Lsvv7nOClCj6cbbOq2uaBpNM+XLWlZ59j/L1WzDWmcZFn6FVewHFyCHSX5ymq8quKGdJz1RrMLoV
xkR/OetZH9Yy8EXJUkCLhNnDF4PL9yxvCCdIL1lkSjqIGSrbIzjPBYWakLFYoZM6kz1TbmxbqaEv
TF7F2Zk8uvE9NM6e0sneG7goQFxI2dcY5iwSpJPuqTx1SXeGzjoT2ylsySDpJhXreLqVd4PL8Yxj
i56VdgHU5jFXd+3czaYmt+tvn/KFnT2vodibLB1/r+nvRzX14TotKQi/xqP3VhGuJ4Tedtt+07yi
1r8ASnvabkCNO+zAsNg5x07e/FEKsKnpQGPShe8D/z37k7PEaFTfldKqKe2Ez4Zmz4cJropE1F+4
rM2ZX5dq5peH+oD9PCuXuNg1pplejVYq+OPuoX5fuOHlVVKkGWmdcPsfTjG1E2cBB5rXrPiAFG+v
bMFHJeRKWXRGRF65q1lr80VGsqgVT32WjBisQwMW13bnMn0fS0gGtRAYWvGd2CFTDDRxH+XNliVM
m60I4+GpxO0s0P/O7l3FoFFpXy+9Y9oV2g+5vUPIJbadkvJ/TcU2rmZBCBD/O/nyUE1ngV3mDqGm
9I+SArK+TK/FlF5+FlAjoKfTsE3o9SBPApggiuanM75jP/GF3I3XAk6xR+J3v9etZJRh7WzMq7LT
WXL3kaxIfHCfAnDwcgRYqAmHBZilXqJqnaypCkjFdeyZ7rAnv8FL18WOD7FAG+XvzzXjcgwzsWs5
3kDRbWFhHN8JRhCTlxfqTVbpMzskA6MhZGzQKzVOt1p5oQ/Zl8KKqBpZjfCuFquAV0ute8ZRvl0I
zTsG0o7SJ0QQvemjDrdbUQ+/+2GO3P8T3s4AX5jFqI4Sx9PexGVpedrYyKp0SKht1FIf1k8Ui9FA
loHbkM+AUUB9E5T/yf/4q4LPTCZQXRL2hkRcAzgxIZ/Z/p8wR2NfsNmc07ShU8niYgG17hjzLFgx
HHOd36vG9VWKy6TJdhWNHa8C5AJdVz0ezYUzDajZ6zKWtpw3dvRpXH0PKZWmBxLp1uOZidd2bhCV
LY6+fCTMb5b4XnZdpWAng/issCNkgUjtyGy5AazySw/zD7I8ckO1iwscbfDZJDIXI9S2Lm+PCT8s
2wxhyPGIlyuXUbyC/d/hNklbDgOIsNkTxg6OlH2tC9+1ES9QEVFJQjX9N6tv3KRwSQks98luQEhX
ca9C6qruOg5FZUZePCWhHywo7OXIf+fvWhV7pvQkCfIDVtPEc0np+OOZGnrFKW60CG2il5HesgiX
1J0ihBOApDwAQMO5dHl3ry2XVuE6+Wd6GagwQPYzdrYU0vOhiCuP2N5mWjz+tYmJHFNRLWvUXTMC
XsfcecRir3ZfsNNE+jbHhKcd5rtrmFqX8Ceim3JKSyWyFU6bphZ0mheuIln5tjBgTHWi/4VZ85Pv
q861VQUTc/pZYYvVWXncwY56mIgGCJfyTsv94tJREFPq+V6y1P/gVBurNGxrTRdkZv0+Y3QYjB6/
ryaXsr5/9+/2hdRP3BMTXeZYLm5zhSdaJ85+w3C5fUEY9ozHPl958mh267hHeD/RtfuVYWjJ9TNe
eN5ZxRqrIqkj4jJBvJtL2wdZ0/TD0C0wtTxIT3SktxItnyswd3OCzGIUADQ8SbtDjA7hpQTd/2x2
EflhIomFLAsZecFnRKNSplC3wDmtp7s5i0YQqJLMBKcDvh3ADYr2x/Ttivi7+RWMkfH2wr3tl03O
q32kYajklrCyDxx5405GbQH8fiYKOVTsj6UPk3sku883ZI9piX/JMCZdzS+GXWk0vvKtr9IHtD/n
95SKbCS6Kuo18nfiGRQqCXsaZBCOnmEyeJEhkoPQGbLlbeEKBb5yGXafp/aUV/6HUTwLBYxsCm63
N3tlKhuw3aUhu4ud57ao3LpvVLRxNW2Wfon/O8sqH1yu9JM1AbZdKzjf1KuwKO6uEe+2m4A8p+IK
64iuCIe8sXaMdFf/dXZBK+QnEZufcdGbKjW8BwzIKC7pj8CHVrvBpQKkDLVCP9fgmj8+loCogpln
lYfWrYiKBdoTakf7o1MD7TLm4eY1u3+DObDBI95N0DtpRSTkdm+g5NlXESMxW5k/RAsowfbxgT+X
QlJfEBIUitQyERBZHwD2nAc3aCWdZDhPax7gothJKle+iTkgE0lZDHT8gc/LOa7IkqEnZnnTs5Tb
QSTOOco6pn8F0It3dthq5YWF/nS6m31ETyoeKnwLMGK2zLnb4GwTOdjRM8s5Mbmp9ZwjCnarJI/P
Bk1ZM/KJVrB/2AG961fzhmz1jabgacd0kuU1lQTaYHvNnEjQWgXO74emunYszRCPSb2HvCiTOg6y
9DKkmE1fC/MwxGG0XNOaMOnStEW6gvlz6Eyno7ms7M6MCh0TLqw4J1NtRPTdRHbSCILCTi8UoHDM
AbHwu3B0O5mZPg22uaIjlypcV9/AyZuk4aDinajCHuDYIXh9y4Nhph91JKd8GExGzsXa7/JX1m65
DPjZVZAZeAYHPrtPySB4grbX5iWdY1uIQFRsdRgJ6Z3VtWDN6Se0jfd0IiadXtZMt7pRcxJaozrt
CtDFvlQXCvDQkZk7mRg9Ixd9lXWBkaKPEMxgO9j19G+K9U1U0xztHbAlC0GyzuYiAkIHPODTgrmg
qUv12GkLqCPODSS08QRoPtCC7tyevIj8V2Iknd41c7unzyp+fl2plTPnv17Cv5pOV/yY3aAhYecI
MJR7LQt3EiUyh7YE6sz+fNXfVPxRk86brfMQaoPaDc9HABd7DBNgVxAajtSHvU18Sh4JSpiviXrr
mfl5Hn507c5fP3dg3pLs2GpZ8fAtYOHFdQk6th/cXaqwxtKXKtEDees82KXHZLOig66wNf6GDQPE
8QLttPOtuxT0Nrp7cnt8gnPeaztx8sRSR0C7XO37YDuLUyrWVxWcQMbizuwyOhnnLDnFO03j8J2X
ODjbjn5FM6xnhfOBMjYQOOdbWNwmyJdOVQjR+ggKxY/dCGBUIk0jG0BsUwR3WDvMDqnWo2V/RLMT
ZVU2FUDuJKpTNmbokp0krCvVhQeEAysQ76yoz91gJATaHA17u51fllVOetfjbcs7XEzT49UsyOJc
VpfBBiEdpDo1xeDugkiKEdnaGRNv34Rs9a8VBYZ1NoMiRXqmJiMoD5mfI+vlQYDqDjMFUNewXrXV
K5pejBiQ1+Sob02kWClkSq4gVfOdY5ZiHPlPin1a5v19xQjBC47bxTvtwmV5PNHQ6EntjAmB3gyZ
VbVZhraeaYWAQ5olwlAXuLZ0adywF/jthwvCdvXeDjg5MUeG3iom6Vj0ABCcxe92rW0pmH65xRnE
/ROEMaj0F8Eu+eliHKnqGK318mayVtLO7P8WiPfqYUKVMb4T+1b3C60v4wDR/Ig0X5Mc0xX5vzbw
XRnQqVgLjVUp/VJSkTjB0wLsde8vjYCK41HbnYQ9Sgi5tcN3XjRDeI35kQFOYEjUAakb+PYG2tpr
1flcjr/9ctBCsb1MU3Z4KHqWuuvw2hmvmYz2RrveksbRGPcnePD8ddMLWSjZqaYED6istXyUxwRQ
5dUAuvbeQ0zzy8IDivjMUdVadDbg+33KzTvpkX6VuGT/YXMXseGogBqfb9cSggAg6VQdL8I2Wxnr
5HS/P2wcaE4KKe34Yj5NDtP/qByntjSz5ZAp6ntPqkX9jqN2/kirB90Rsgmn5jIpx2BnzTJqEJ3B
zIwIOsA0XdKg/h8SbdqVPIriGkSHSwhO8BPxJyiG6jsAz+R9JDn584lWJX7L9fe8Z0E832ZcMq47
5LIfa7Uh6XVRNDIrC3sC9rY1o/Z6sL51hgB0wa8gNdE4CUfC3GKtoXHLErVLLeaqcqTRPB11un9f
oXXz07rcWeaucz5jYKPMRjvEZOECErkxBEPaRbGolBxyc9aTJJjKdJoQbF12V8zxHMzDdkGubEN4
UOTPcZk5AaswA5e40bHxItpC6h5igtIvzvgd9Ck5u9AABhvcmqvmQCS9xx7JYVNonF9H5gNaMtI/
LhRpty/NbJSZgn8C9eEAobXl1c3n2tB7zRxUNiw7VYsq/l7Out+P/WkdqwnT3WaDTzy9q/NfKpJu
Y49TKPTQSVZ7yKeuDbia+lS5HRA106gh+gM081xYSr1unljdricFlR4VX5Bnbj6VgM/DQ4dZMZds
zsUSInuEpQ8YML4dT9pw3PBF6qF1VAk8ElDeVVeGFViSupRdVdN7LzlfFXk7RgneTSEBH6h4qA3S
fJhZF+9MK8dEtul40oJb+rzVwqhs2Oo4F6mPTY4CfTEvGAxrB7beCTHZserzeSQ25hSRFFT6ZyIq
6+KN/gtxV0nj1uk4E9yJtnIhrSUK+H1MxkQUsk9B+BRsexuQoZTtdK3bkwxFCf2WyBaLFm/IYrDQ
dAtIuFajYkwsEkpDKCmxhUisecgkqAY6DxRwaQu8njgFKbxokiG0wf+z7RVcSp3nPkDxSRie+sfB
yJe7W4Bt28LIF+uzIsPNQp0tgip+J8DqSoQ9RIYNKeMflVWYKwV3muJhUK5+PuywCxd84ljkkwRi
BxeBSCv96ZGffi+b18C39+ViXGizhMsIPnxJn7KKc78FYXgP9B92I0MJlQiGNOeKWaRlpigpGYZE
67X58vDfrQH3nMmmQe0oaE7H8NaSQJAunqUXx9QZ8T9HR4lTCKx4j2Fy0YpcC1gg+ZAZYasT/BPB
r8HiDJPZkx02ljpu6Gy+tAghcfUMo6xVXH2Pbw4utc551iZgZ1isKtdfJ1RQKERZSCHhSAHnTPTu
vtwvuPeNYh3oRoceCjHyEoQryFFW65p9X7YZoZfAYW/jMtChV6n8sEa7l0/iUm9wGNkq3dOcLz2+
WoNG1B8yhmurmDVuaERx5NC3nL/dnMEg5ylTQ0e0vOcCNpLCHpKCSuHKgZylEkJdhYJqOf1N9kg5
19dE3I/OCwUPfLdJgZeUPy157ZwMYyn8DW2CaRfTeO/VEXVpQhwunaOASu9gqBK4pcMbeHtMLDr7
oz9qyaqx7fnAVMrjOq68K8upg0P7GuUehRrhyOqVTWbbn0d2TpKuKcYOyXkF+EESKZSRQm7ElHbE
hNp1xRL0loNiDlCH5ALeCDAsvul1XnpGczCKmkvdUOOGSSPa39CwRD9L2dS/Aodv77kLqRj5Xw7W
n7UDvRE8Hu0ElYXyWEYbd09RGYF0Y2LqpFheKqijHtefwpr+VP6xfsn2krT0sEuQJEpWEAy+ixMx
j35D82DXQ/rwAg7tOjyBYZw6K6Ya4ejI8MuyBFaQzDsQwUDoN7fjNZ41ZyfB/Uq/+vqxQSabjJH4
7YYBebw6qwNyEHrb1S/e0L3Fmjz1VcZM91A9pkBQyQEqB49qHoXSxTIQYj+Rby6RFjG7LJeRaGB+
kDkPK3l+MNDJ7nUqyjSMwx06iDRw3XvjJ1AQad1UZndzMQW9U5UOp87bmaeKGX0EeJcFSt67CCPt
iI9DkQ0ep9JFmrQ8k31XDmaVMBhJaY3WEx1CulJMr6kGFCx8AO8SZz/Uj0dDP23NV9+ObxFJkAmg
wOGLlRhbL08+nmFzQIP8oiAiPxJGywCfe5U3p/tpCUam1+5e2e6079+K0FeRhfntztKscLQ9FYpL
LKnC6q3yxdBvgbT+czhHnF55m8SsKbCPE2kMoG4MwDUPy4dn9n8PSh9p5WhD0T9kOyiMs6V9Awn6
u4rhrLE5sFZGYHHINbJ2214P/EQ4AYEvwos+eMIuVp4ekSYvJkfHME0EQembQlvkI+EqE6yU2//Y
rRXGSscq8NDHA5/R8CgsbJa3WuQDkz/ApGnQ5CZuKOmwhE/vbdcb1NWVMkgmoBdgVx3EpnAQJePP
znfiW+GyTeB5vD5H5u8NXBhLmcuUGCYLzaS6y2upk6PId/g7yyNcfwSMopEju/Ru0xtsqDagXWVH
0fQq0hog3t4EGockYK5zD6VJGypPgBIFByHiGvO2M3VJ9ZEDIWy9O72J5UDgFfnWg6Ptl+2oxdqY
LEC+BRrzIF26EU9Iwoltk5jxrRwraZ/bL6uFRBUFbBdf7fullfYcIuKiAnY3LL24mpvox4T/TgDA
7HPNahx/6S8xJAyfNQd7rfrwE8ugSLBOE1fywaFXDlVCTVT1UhCu/IvkZA7yqOQn5ic3QR5EExuN
8QUo6CFlk/dHdMTkjhryg29fJ2a7wduZEP1o9NL2GMzwZlvE3IcXNxcWD/LPHBFfRKUyj7xnbl0g
eD9MNSI7pViYTz9lsr37cAOtzIi9vo5TPPm3QJZhSvA8ofWkhrbhR0GUF4RatbYd6iqax5fTUdxH
XbZif9v7TbIhM3U6I67VUetEouY1euPG1bcWS+T8rLpKxbz+EWITX1DNHSC6NyH7wxClHu72Z09D
qD1e+XVwFkOO+CvTEkXDBsbYuWoUv885GRNS4Sdc1rol0B2iADyGMj3HMzYzHJXM522nPvY8CQ1h
5C18lNRpB0a2nAJZ0Ieq3zAcAX2eMuXQGMFfQtk0+VMIScNwYHgP9lCS+xBMnfk/fhPdNftB6H2c
qwCZfup4p3l9oxM9kJri+5W30U4S6/jOMz6W7VYXM+D53PshEojFq66fa5n5VAZAnidO1ErDVd89
Mwrm+fhpk7S7YgjMXFBa381ButpviSVWUtL+hHxJNAyaroayX+hq205B16wjbpN3BgSdgsi0/87A
xzWaW6uqvVpMRtFc4yBaDuatTJYH8AzAxLq5BU10pWIkA7hZZyn7qVHg2ef4ZUFXvfXSf+trLJOx
BRl+5CL54gV4Gq2ICL5WWhDEAMAT6hi1LdGn1y3zEH74lcSkgbauSY7n/nzRKaTsvjKWmF5tdilx
hdAp8UBB+VpkdO9WRQappKTdV+pWEXBHAW3zwTdyjD1lWQldRuYSyi95W9w2eQWJPrIbf3Dic8g6
Y4Oj4TPq9lzVUHd7DdOFZ8hRMXMU+iFkxGpu/nLSIoyn14vgFiO+D0MNhvIAWBCU+dnoIZe8Ihcz
dSynCrZ9Z3G9lzmQlbHI/yrOCoJKUgVISq23Y+KWruL/FYtk4Y5wcGmDA7iM4UnxS0Di2GCd9MHD
8egOIcVxvTFXPZUsvrnqNDqTOondq8DAqGHj/RHXu35uYCvevGZRt0gGEp+R+fZ8/9GGTwlADvq9
EVezzpwrgswXSudTGx0qTUhODFVlrc7R1GUjNbPEc6yQSqiEHo83FrcG8zYSZkDWWuIkMah1C7uO
KoeZ4pEsFHEEj/rsZRoCrQOxjHCPuL3WLU6Yo/EolvpTkXBYLzE89T7ov0aVLZIBkvZ1a1fby0Yv
iSB3kEgxJAgpgKCs9eGh4wGxnb06NqZvoSTKkwpDsB5MdDOcoaaEGVn/lia8ZlVp75r6MG01054v
Zi0Y8f/dhUVcywVz/vhhfPFBxFM2d7q5w0ep+zOsWZTBmWaRZX1nlt0EAiwIzRrgg5sqwS4IhqvB
pfI+PXh1MbQhPxiYtCkUk13GlKdQZCmpSmgvVrkMh/psUVzOS5/kMIVq+GUbGJJYdkyI5zraqE7r
yg5JU+pLcGPnqEnNSNmCLo4qUgU/etPVsM5Q1dA8zlb2bUSK4fEejBZTz8pKFr2MR4ro3jVFHriI
Q/l3T01OGRWxlcSZN+vzmNmyUfRjtzoLhaKv30RTov9u6qP6K2vVmT4VupVYMBkO3GgkWKuWVG6R
bbZ3fRE13Ly22qcnG0WIvvbsNv9/IYjSsFmi4dZ1SaCSJW/HPSncXrLcEPB7GaF4AA7hNYmF0DKL
bxoLMgpfNm5UiSy2N4gno9XyZBGmZEuNgCl6cecTQ+IbdTOcknawNVFV/sLAdFoZfYptMSYkCth1
YE+tieeVlGL/ZPQOu+ex7mIgD/nHjO0EZs7+lN/C9/PjomJ8Bo3O/Z+UfLlcO1pY3evgVNIxPAkH
r3FtZQzOeurCstQzbUsDtA40Xw4wdIf/5+EURAiBdvATmWWPGibjgcML6+cWpAL3WVAUfJ4c+FJH
vTOgfKUqmGiQXS6MCf7lVahhhXCbenrEou17WEzqU1OAxhUqdZoLqOYGVbADb3epiWi0Paqj2zib
KVlCFaByUTm7ZmFEeNwnN89ct6qwvgyb3R4nlp0oC27pMHGrhhtxZlF+2UfeGD3XF5uy+hIxqXon
743quGnHjYtfdclm4Kt56OFy7sPGcCR2YhOeVEtRqvkz1XSA8oZ1pTVYeD7vAVPNO1Z4G5854IYo
hlhuEOQWEATdBqzj3Un+7m+HbC/VAJi+6pwROMsiN3QCKOEAZeVnzjcrKPRjLQDBZCnWoW/ZgAJx
39aDDn2Qlh6JazaHOANHBXSgaEN2SqJce+GvNNIQXO2hI8HH2KQkjh+Zo8CjIE3+6dfB3hO0/IuP
PiIGthFakXn1hqXgEZcFtz9wFP/6AluOb2SJjQCLG9GjtVsjmb402uH6snpIiVVFSgrtV05mYZUP
5HINYv+NIJDFdn0IhmdVXINX0qSzGKZQwmn69y5QFhxZ89t6RnTYOZ0PzyJSeu6f20U9nt2wHQHD
54fiBkAi/c52AWgmDFP03mcuX2g80ss8FtP+8hD+M1Zj035AWn+KMLYzhKFkYWyTS9zbotd08CQ7
DBzDP1xPYwD8P+8WoPnMJpGzGlzDpnGJiw6wJ12vr1PqVXQG32b7IqQxsK5MxsCNR3Mhw3BJAVVW
XO+QYmRgmNvKym5zwmz/fddLQAJerQLcCDR4mIjeHvDTMVv6zp+FqekYBLb+jwGnuvBmEcUXXjP5
ofdPKDPdhDiNpV49i5NqtHK1sA0jsHiQ6OEV88G34uTI0gNIqQf2UBhqXTaW0p2jd/HqI1JGtqXM
gpdlEnmJOwMFcB67I5KAPfpdaaYeyaMzYzbqgOfDyRBroCBgtaNPO+3VYrXCQ+Dz9JKObWT9033K
EQ6me0bC4wwfbZFq0hH5kyi0/AC33BDBnJmwN1t9qNLcsu5Wku3VELpaVSoVPbjblAgbydTNC3t3
aJQ63wS6EX8Iq+8u2YiH8rAzGqX5rWwhqCvaaczbdcqw6mdpeCzNjVWLqn9p8iKqSM+vpEbmwtAQ
ARKGX+qwTpV2lJIYdqhAV4GbkUt0iZE8ciAYj+v14ziMYk9k01OeyYl6tvJtw8Z/VCyQMyWOIvh5
WxHyv6p7QDeZhMpZdXwaKkXjjMZsAmVSiBf6uRc4GS97OsKuEs6zdQC5kQ9DaBuNJcyGxRDcUKYg
RT/LVCPlp3eOfCSf3NUwoe1Tk3pvWaEDqZt14Yu6T2K7mtJJDXplnYRlRYmiTc6+mfy+/vcCPSlw
bk3VwED0D815elquJ8TtEtdfVGmkU7TVG2qEeDvKXw6xqqHI837sRv1Lde0iKI9zEqoK348cUewK
JEokg0IyvhQGo1GqQMRs21PTAkLGhCsQdHmvBnaxTlQFMX1q7gP/ZZq69M+Pduy53SirGTZKW79C
m38ls60+CV1squPtvg52sqkVA8N3IJ7loXNa5gtKoY1O/qNmvkIlXofEhFNepo7fyZlwbcdoV1Tr
QTaAckKeUf0dBuP0Cp6watRLLT6pYNJxAZid0tmX2SFxxaYquX4dRai9koGDZlaPxL6IVsTwbzMm
XuT1YVGU0i9EvUvTKQKcnMg+7jrcMYC8ys43wYR3HEgTkIimtygrd/4GLT1MVCMR+AyDNJkI4B6B
OCZkisiujk3oJVErXxLUvAqvqOhJAaIEokuktNyFPYGhHVNVvPLFHgLj4i2ecq+82hWLqZOa67s1
2osOIG9f5lBBlZXVyaRu1/PiQxWd46qDMLr0qHG0dl5NAaCV6NxfibqRYTqF6OgppXcRubPGY7eN
y4K7Qc0K7QuOP1elur2W15Bia8+E9NMhmhN1yOKnpGycaqxWY5F0bXfLCriUwXefqQpPxMBab808
qhDoXxVe4fhq1w+tLylFckreNYFtd9QBWR4Snx2Ms1hUE5AT1wU4fsj6lh80LQK+qi5QxU5UukEN
1HqdyKZITi4qWBZzqMsByamWkXBaEgHFRH3HHysf4KUL+T0zHvL+rknXFQugA0EtqB30srYMFYk2
iwI9L6AwFkYJgsErQb0lCJBJy2rgvdqxjC8w6Um6tP/r1j4q7XDlgsK/lbK+XGK3hwiqpXxbsxPy
/szI6CQa1VaLK5XHWkH6VSrfjWwpNN0HEDEziAWHonNEAOfUNor6IZAUIjGWwXo4SXdeKHZg3+Bi
+m+3dm/WcT6/vvXaLpNel6Brtpl2A97w+5hE02HtnwVfKwFOvCeSpvKhqtVDXUOOCISdkQXz9k/T
PkqpL+S7fDANfP819IQNHPBHcSNxSXAan/lusDqP4Ynn/oGUI4nLyy+qJZWJnhaqk1b0RvVJSlIC
cQQubYg8oAZQS4bZXm8RwFrLrSZ76SCMk3KZKykEK8bmsCYvcgd9/op7dfqM1wIGJPn4iugQ1TIy
9IrIeOcjs/cQvc0r3XyYM9QmaNcg85qihRPhlIXCoBjpnY4inxkcVKLpAUQAfe+2c8bfpeW3n+dE
zR5bPlGeBx89P2jm83p7KWILxrXu1uQbChAEl4oaHV/Ra/o5GS4+cGHv5r0GP+FEGVLZ8iXP1Ubc
RAoRLvfjRpJFcqoDoquC6AxggvUqJzQEHqFslxo28Q7ZPNyQLupee5K9ZOzW3pAyrLDRYFMaCKk8
zVJkPIILkn9QuD5c6/Aj6ebSR/n4P9NO5QxWbH/84Mag+R5iExXf98UYXayIexj6Gu5xw7M3otWS
SVh260yEbj3Zn2KNReJq+3nVyT8q3MTJfL6jXPRHKN3bzUXyQAnJ256gGMDdZAoBdGecUzzb8qnn
0rIyiIE4ESGlaJb2XP5BQGrAx/GaAhP1N3eHFsTJFwW4PVtVRl2SsHKImlE0SS5RTW0oJN9fpxtR
7V0SdPOMkmpIkIhSUGgO82c6J9fZxPMIMgflQ+19opvYDSHBfpz3SfKM8Oii1buAj9TgSS9rp8Gw
tb6Fu5nNrX87RsIaC16dMUUTYVowdwe8qj6U+oBq4olmBE0vrpXLyCN8FELZDFaiwxmZ788mek8X
nSIPUQ4P0K/raIh45c9lFugd9M8TkXknde5JriuJzTLXtMclVbb1+5u0E6Wn4SzzW64zZhOurfta
MPWbxcQd1MGo/VOkd3ZzhwNO/hdCS8fAj6tIMn+h6ZNPzfPrNlvo/780cJswu8lrrBBnnCbvk7Q2
WJBxcjq9OiHQm31yOGWhGgWtJISxW8hT/Cvolvbwn1xq5CBdnHSTt090FxQiN9t9ltNWmwYnxOiD
dc6eDAOcIIz1tw8SYQbdM1QT/OQZjiZk4wXs8Rqo3MYiBEIAm2eQlLNaESgp152larRrV204suqY
ZVjsr1l25akhvERtLXcODnn6dbBES9Pjm7l797pfMrgq3FbsIxc4giOZNEUSiZ27kY8D+Plkt1nG
iCLWP4UjiSazuext1XYx3G9qO9Tf5ObRNYMGzrFe4pOBu6dSzKl/2eA6+xlNt1ngjwJ7h48Ex+Go
CCYOTfDCG+17DVmB45vhJETjhFrOd+BMN9ENxdrUysOnP+k25o0ejVpKvBiPTVoX6DrIAcG43TRb
W1DpeeT1TOd+QICH8Ge0DKJW3Ppd91zyzNZ1otc6+9fHRSlxfI07MetbJy64B4YEq82IBMD9dd28
2qk4hYDyq+kjCXrKME7oCBxYlTZgCKHW1e3UkuzugwPcwBOnJAc8ap1GJeEg3D19doKY6piNfPPQ
+AkcaykAijMobUxS1bOy8Tx1ISR7QQjH3KBZBscUJOZ0WGTGdqjXM5HEC+Zdxb6fIN76gvb7DwBT
ORemxLKZwcbwv3c6CYUZ+VUmPRUFJXKjtBQIfDN1anL3JZLvxtQxa5hEcfDVVIQ0EZl6D3dpOfoF
MG8/HF6FRGNuQy536oBawRuXhi6JBn6EXkVpjKHKfJvkr9Fx9u/Lgw5fw+4SRcSyLGexDUj/i4kT
i0KEpPcRr5j3UUAujAP2x48HZrajr8K8VB1m8bz9Fe3WUr2SEX2304zU8fds9tq08moX9q2AWLh3
lJ70oiU8W55fMR4Zg4vj9KGf76MaY/iR2i0ga0fOGelfi6zsi2v4cMGgWqN0s97RARSA/RoEWvGz
Z0J5gvuSm1flvx7TCTyLnZ05wVbadhJoAjRLai9Ga5p77OI8ZxNRcuA80ExCbrGzypLCbbep2ooU
lzZCGTR0fTjIYnrzU3ihpCst0LftIYRY4ZRkll57EKLtrq4euXAv2K+Eo8rXFHx4Q8CTI02YhVIS
3eotWEHvo62SBFeSAlbHAC9jjG61EN4FcN21ExXiFhnO+wFmvyfq8CSr2EEluYQpI2wMHKrVN8RN
z+qg/xQgBwiXlFdGTNxMWR9d21H9h8hhtUaSNYoO2NtgnOF6plIie7ofla2iT9mNLatXRXSfmzSE
p9sNRujNrB8Ma+V79wpYv7gSVqw3ovmN6VcsVT60CsVID7/8hSh63ECxq4sBfJezlxYsFpSU/8t5
P5VaBjUEYgTBKqooX5h5lAXn7WtC4+0SRdkY+zOVtLgigVft8+NB3xqy7C9cg101CF1+kE44RCWh
LY6XDaqyZFRxyOVLvDhd0k5giUT2j9E4OSz069K70xe9vo6qOo/vlWXyzzkMbvd6D3TGDZshQZAS
vVkwVYrjBxpJWTDcTxtMRH815cDRaKfOUqRmZxzGadIMtBhVpe9NCKD9oHIX/1MQPnjZAwccbS1+
tpAxljpbeBFDESZoJBwZMcGyNKWHyicrD5U+I4R3vMxCEFHTS4+oKt98hIXP3umoQ/E4E5tPd+wj
IUGpuOAMuyt/P4FOKh252jLgncbhE+/2aBI7sk1m6o8l9suXMejF/wIjjHzIjILpPopm2sjxoayz
CZTD39SEDkr36GheKsHu87BupINKHoobKq6Cf0D0bKbtRJ5pXqOytSKfSe6e5UkIpksWxAR/fDgx
5CkqA7ggFSTqrqYklry5X8qYshkwabLtlwKnljnujBqX/aay/cLYJ8QRkkyOzqg0kid+ctkpgXci
PYisVh07a/2dmohq3rITM/nYKaDCI+Dt2rA8Kqza5v4n/GR0ZOvECWg7nUtKbjrHQJ/KHJH1CKLC
LJ6fw6su+CZP7cvwPIwsSpTXH0hV7XvYCfdm97dvaKxomBXgfPa0lU7fAXk459/apK2PzhPkPw0w
VVHDjkPf95YuPW2ChV9hT8vZyZN5u/nsbfUyy9AfiC4pkPZNREede272qZQ/7g/nVzzbwybfMqM4
RJFureBDeBn3tnmlRZPEH2aW/vwhpHJanMa11mKsdd/tYGMSzRaMjR0veNWDB6dyb2LsWrTZ/BgH
RB63CSp6pET9OAo6xGptJDG15w5FGIfg2NjILF9cd6izyOR9X5uolGEX34r50bT8atiXHs582yIf
Z7r7RAbXq0CZ4eSvPfP0wb9aOsX9Evh5p/OR/LzN7VNZd78senrt22rlI16PChcl/CSa0DjX0U/a
NY7YLXbJ5I8hNnICRWOVCi7tIWATDO1BsHwd2pR5C59FGDqNG6POIXhgbVkjMU3IIQOunM+wPA/D
WxeiBQFP8arc1Mfad9P0qF+cS2kRwMRP1jHYPOO3KA2BkizwsEzvsZKpatq6K1Qj7mzeoUPO29ul
C6MzzSPwMMLGQXNipiXCOw4NUr9uS3agld+WUqy9LxJ1WliV5i9fCKLAmCIivYp53CaJtEVMcuvv
cYzIh7G1AlLqgqQuQQwtPs1UPy8vEDG8gjucEQs1JoLlpHmDewcSelRUxrHYqY974r9PLYs3hWTQ
aEiDDPDRkrFG22de0LPJP3qk7d5KD2UeRNT6dZKD0Mkv4JkNgGXIhMQ3T09wiGSsuffAFZX4LdWx
wYesNtaJSKsvaC/RNgccW8DK/haSsrnJUk39psQYYMCFQqA7Ox6SCrQVGszuLBTkvDKlw/c71uJs
QGZGyySS8vszzpwpoAy9F3paZIIbnY118wQ73IUoSm87sywu7UxRXhwOLgFBPK05nZyhO3PRZghq
hA1f6opK9FauxGE6S3Mqu2PoaJr3V3hRZoOdYfQLce4+wOO1uA2+/Pwpxxh7qGxdeozyy3QgfDx5
+70DwS0SzJSmzgDnupfnO/Pid3o8KwgqCAwZzAQqW0zDcj5JGLTYCaETHXkpEaiq
`protect end_protected
|
entity shift2 is
end entity;
architecture test of shift2 is
begin
assert bit_vector'("11100") ror -8 = "00111"
report "ror -8 is broken" severity error;
assert bit_vector'("11100") ror -7 = "10011"
report "ror -7 is broken" severity error;
assert bit_vector'("11100") ror -6 = "11001"
report "ror -6 is broken" severity error;
assert bit_vector'("11100") ror -5 = "11100"
report "ror -5 is broken" severity error;
assert bit_vector'("11100") ror -4 = "01110"
report "ror -4 is broken" severity error;
assert bit_vector'("11100") ror -3 = "00111"
report "ror -3 is broken" severity error;
assert bit_vector'("11100") ror -2 = "10011"
report "ror -2 is broken" severity error;
assert bit_vector'("11100") ror -1 = "11001"
report "ror -1 is broken" severity error;
assert bit_vector'("11100") ror 0 = "11100"
report "ror 0 is broken" severity error;
assert bit_vector'("11100") ror 1 = "01110"
report "ror 1 is broken" severity error;
assert bit_vector'("11100") ror 2 = "00111"
report "ror 2 is broken" severity error;
assert bit_vector'("11100") ror 3 = "10011"
report "ror 3 is broken" severity error;
assert bit_vector'("11100") ror 4 = "11001"
report "ror 4 is broken" severity error;
assert bit_vector'("11100" ror 5) = "11100"
report "ror 5 is broken" severity error;
assert bit_vector'("11100") ror 6 = "01110"
report "ror 6 is broken" severity error;
assert bit_vector'("11100") ror 7 = "00111"
report "ror 7 is broken" severity error;
assert bit_vector'("11100") ror 8 = "10011"
report "ror 8 is broken" severity error;
-- ROL
assert bit_vector'("11100") rol -8 = "10011"
report "rol -8 is broken" severity error;
assert bit_vector'("11100") rol -7 = "00111"
report "rol -7 is broken" severity error;
assert bit_vector'("11100") rol -6 = "01110"
report "rol -6 is broken" severity error;
assert bit_vector'("11100" rol -5) = "11100"
report "rol -5 is broken" severity error;
assert bit_vector'("11100") rol -4 = "11001"
report "rol -4 is broken" severity error;
assert bit_vector'("11100") rol -3 = "10011"
report "rol -3 is broken" severity error;
assert bit_vector'("11100") rol -2 = "00111"
report "rol -2 is broken" severity error;
assert bit_vector'("11100") rol -1 = "01110"
report "rol -1 is broken" severity error;
assert bit_vector'("11100") rol 0 = "11100"
report "rol 0 is broken" severity error;
assert bit_vector'("11100") rol 1 = "11001"
report "rol 1 is broken" severity error;
assert bit_vector'("11100") rol 2 = "10011"
report "rol 2 is broken" severity error;
assert bit_vector'("11100") rol 3 = "00111"
report "rol 3 is broken" severity error;
assert bit_vector'("11100") rol 4 = "01110"
report "rol 4 is broken" severity error;
assert bit_vector'("11100") rol 5 = "11100"
report "rol 5 is broken" severity error;
assert bit_vector'("11100") rol 6 = "11001"
report "rol 6 is broken" severity error;
assert bit_vector'("11100") rol 7 = "10011"
report "rol 7 is broken" severity error;
assert bit_vector'("11100") rol 8 = "00111"
report "rol 8 is broken" severity error;
end architecture;
|
entity shift2 is
end entity;
architecture test of shift2 is
begin
assert bit_vector'("11100") ror -8 = "00111"
report "ror -8 is broken" severity error;
assert bit_vector'("11100") ror -7 = "10011"
report "ror -7 is broken" severity error;
assert bit_vector'("11100") ror -6 = "11001"
report "ror -6 is broken" severity error;
assert bit_vector'("11100") ror -5 = "11100"
report "ror -5 is broken" severity error;
assert bit_vector'("11100") ror -4 = "01110"
report "ror -4 is broken" severity error;
assert bit_vector'("11100") ror -3 = "00111"
report "ror -3 is broken" severity error;
assert bit_vector'("11100") ror -2 = "10011"
report "ror -2 is broken" severity error;
assert bit_vector'("11100") ror -1 = "11001"
report "ror -1 is broken" severity error;
assert bit_vector'("11100") ror 0 = "11100"
report "ror 0 is broken" severity error;
assert bit_vector'("11100") ror 1 = "01110"
report "ror 1 is broken" severity error;
assert bit_vector'("11100") ror 2 = "00111"
report "ror 2 is broken" severity error;
assert bit_vector'("11100") ror 3 = "10011"
report "ror 3 is broken" severity error;
assert bit_vector'("11100") ror 4 = "11001"
report "ror 4 is broken" severity error;
assert bit_vector'("11100" ror 5) = "11100"
report "ror 5 is broken" severity error;
assert bit_vector'("11100") ror 6 = "01110"
report "ror 6 is broken" severity error;
assert bit_vector'("11100") ror 7 = "00111"
report "ror 7 is broken" severity error;
assert bit_vector'("11100") ror 8 = "10011"
report "ror 8 is broken" severity error;
-- ROL
assert bit_vector'("11100") rol -8 = "10011"
report "rol -8 is broken" severity error;
assert bit_vector'("11100") rol -7 = "00111"
report "rol -7 is broken" severity error;
assert bit_vector'("11100") rol -6 = "01110"
report "rol -6 is broken" severity error;
assert bit_vector'("11100" rol -5) = "11100"
report "rol -5 is broken" severity error;
assert bit_vector'("11100") rol -4 = "11001"
report "rol -4 is broken" severity error;
assert bit_vector'("11100") rol -3 = "10011"
report "rol -3 is broken" severity error;
assert bit_vector'("11100") rol -2 = "00111"
report "rol -2 is broken" severity error;
assert bit_vector'("11100") rol -1 = "01110"
report "rol -1 is broken" severity error;
assert bit_vector'("11100") rol 0 = "11100"
report "rol 0 is broken" severity error;
assert bit_vector'("11100") rol 1 = "11001"
report "rol 1 is broken" severity error;
assert bit_vector'("11100") rol 2 = "10011"
report "rol 2 is broken" severity error;
assert bit_vector'("11100") rol 3 = "00111"
report "rol 3 is broken" severity error;
assert bit_vector'("11100") rol 4 = "01110"
report "rol 4 is broken" severity error;
assert bit_vector'("11100") rol 5 = "11100"
report "rol 5 is broken" severity error;
assert bit_vector'("11100") rol 6 = "11001"
report "rol 6 is broken" severity error;
assert bit_vector'("11100") rol 7 = "10011"
report "rol 7 is broken" severity error;
assert bit_vector'("11100") rol 8 = "00111"
report "rol 8 is broken" severity error;
end architecture;
|
entity shift2 is
end entity;
architecture test of shift2 is
begin
assert bit_vector'("11100") ror -8 = "00111"
report "ror -8 is broken" severity error;
assert bit_vector'("11100") ror -7 = "10011"
report "ror -7 is broken" severity error;
assert bit_vector'("11100") ror -6 = "11001"
report "ror -6 is broken" severity error;
assert bit_vector'("11100") ror -5 = "11100"
report "ror -5 is broken" severity error;
assert bit_vector'("11100") ror -4 = "01110"
report "ror -4 is broken" severity error;
assert bit_vector'("11100") ror -3 = "00111"
report "ror -3 is broken" severity error;
assert bit_vector'("11100") ror -2 = "10011"
report "ror -2 is broken" severity error;
assert bit_vector'("11100") ror -1 = "11001"
report "ror -1 is broken" severity error;
assert bit_vector'("11100") ror 0 = "11100"
report "ror 0 is broken" severity error;
assert bit_vector'("11100") ror 1 = "01110"
report "ror 1 is broken" severity error;
assert bit_vector'("11100") ror 2 = "00111"
report "ror 2 is broken" severity error;
assert bit_vector'("11100") ror 3 = "10011"
report "ror 3 is broken" severity error;
assert bit_vector'("11100") ror 4 = "11001"
report "ror 4 is broken" severity error;
assert bit_vector'("11100" ror 5) = "11100"
report "ror 5 is broken" severity error;
assert bit_vector'("11100") ror 6 = "01110"
report "ror 6 is broken" severity error;
assert bit_vector'("11100") ror 7 = "00111"
report "ror 7 is broken" severity error;
assert bit_vector'("11100") ror 8 = "10011"
report "ror 8 is broken" severity error;
-- ROL
assert bit_vector'("11100") rol -8 = "10011"
report "rol -8 is broken" severity error;
assert bit_vector'("11100") rol -7 = "00111"
report "rol -7 is broken" severity error;
assert bit_vector'("11100") rol -6 = "01110"
report "rol -6 is broken" severity error;
assert bit_vector'("11100" rol -5) = "11100"
report "rol -5 is broken" severity error;
assert bit_vector'("11100") rol -4 = "11001"
report "rol -4 is broken" severity error;
assert bit_vector'("11100") rol -3 = "10011"
report "rol -3 is broken" severity error;
assert bit_vector'("11100") rol -2 = "00111"
report "rol -2 is broken" severity error;
assert bit_vector'("11100") rol -1 = "01110"
report "rol -1 is broken" severity error;
assert bit_vector'("11100") rol 0 = "11100"
report "rol 0 is broken" severity error;
assert bit_vector'("11100") rol 1 = "11001"
report "rol 1 is broken" severity error;
assert bit_vector'("11100") rol 2 = "10011"
report "rol 2 is broken" severity error;
assert bit_vector'("11100") rol 3 = "00111"
report "rol 3 is broken" severity error;
assert bit_vector'("11100") rol 4 = "01110"
report "rol 4 is broken" severity error;
assert bit_vector'("11100") rol 5 = "11100"
report "rol 5 is broken" severity error;
assert bit_vector'("11100") rol 6 = "11001"
report "rol 6 is broken" severity error;
assert bit_vector'("11100") rol 7 = "10011"
report "rol 7 is broken" severity error;
assert bit_vector'("11100") rol 8 = "00111"
report "rol 8 is broken" severity error;
end architecture;
|
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
package standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN;
function \?<\ (L, R : BOOLEAN) return BOOLEAN;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN;
function \?>\ (L, R : BOOLEAN) return BOOLEAN;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function \?=\ (L, R : BIT) return BIT;
function \?/=\ (L, R : BIT) return BIT;
function \?<\ (L, R : BIT) return BIT;
function \?<=\ (L, R : BIT) return BIT;
function \?>\ (L, R : BIT) return BIT;
function \?>=\ (L, R : BIT) return BIT;
function MINIMUM (L, R : BIT) return BIT;
function MAXIMUM (L, R : BIT) return BIT;
function \??\ (L : BIT) return BOOLEAN;
function RISING_EDGE (signal S : BIT) return BOOLEAN;
function FALLING_EDGE (signal S : BIT) return BOOLEAN;
function MINIMUM (L, R : CHARACTER) return CHARACTER;
function MAXIMUM (L, R : CHARACTER) return CHARACTER;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MINIMUM (L, R : INTEGER) return INTEGER;
function MAXIMUM (L, R : INTEGER) return INTEGER;
function MINIMUM (L, R : REAL) return REAL;
function MAXIMUM (L, R : REAL) return REAL;
function "mod" (L, R : TIME) return TIME;
function "rem" (L, R : TIME) return TIME;
function MINIMUM (L, R : TIME) return TIME;
function MAXIMUM (L, R : TIME) return TIME;
function MINIMUM (L, R : STRING) return STRING;
function MAXIMUM (L, R : STRING) return STRING;
function MINIMUM (L : STRING) return CHARACTER;
function MAXIMUM (L : STRING) return CHARACTER;
type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
-- function "=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN_VECTOR) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN) -- return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function and_reduce (L : BIT_VECTOR) return BIT;
function or_reduce (L : BIT_VECTOR) return BIT;
function nand_reduce (L : BIT_VECTOR) return BIT;
function nor_reduce (L : BIT_VECTOR) return BIT;
function xor_reduce (L : BIT_VECTOR) return BIT;
function xnor_reduce (L : BIT_VECTOR) return BIT;
function \?=\ (L, R : BIT_VECTOR) return BIT;
function \?/=\ (L, R : BIT_VECTOR) return BIT;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MINIMUM (L : BIT_VECTOR) return BIT;
function MAXIMUM (L : BIT_VECTOR) return BIT;
function TO_STRING (VALUE : BIT_VECTOR) return STRING;
alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER;
type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN;
function "/=" (L, R : REAL_VECTOR) return BOOLEAN;
function "<" (L, R : REAL_VECTOR) return BOOLEAN;
function "<=" (L, R : REAL_VECTOR) return BOOLEAN;
function ">" (L, R : REAL_VECTOR) return BOOLEAN;
function ">=" (L, R : REAL_VECTOR) return BOOLEAN;
-- function "&" (L : REAL_VECTOR; R : REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L : REAL_VECTOR; R : REAL) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MINIMUM (L : REAL_VECTOR) return REAL;
function MAXIMUM (L : REAL_VECTOR) return REAL;
type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN;
function "/=" (L, R : TIME_VECTOR) return BOOLEAN;
function "<" (L, R : TIME_VECTOR) return BOOLEAN;
function "<=" (L, R : TIME_VECTOR) return BOOLEAN;
function ">" (L, R : TIME_VECTOR) return BOOLEAN;
function ">=" (L, R : TIME_VECTOR) return BOOLEAN;
-- function "&" (L : TIME_VECTOR; R : TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L : TIME_VECTOR; R : TIME) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MINIMUM (L : TIME_VECTOR) return TIME;
function MAXIMUM (L : TIME_VECTOR) return TIME;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
-- predefined TO_STRING operations on scalar types
function TO_STRING (VALUE : BOOLEAN) return STRING;
function TO_STRING (VALUE : BIT) return STRING;
function TO_STRING (VALUE : CHARACTER) return STRING;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING;
function TO_STRING (VALUE : INTEGER) return STRING;
function TO_STRING (VALUE : REAL) return STRING;
function TO_STRING (VALUE : TIME) return STRING;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING;
-- predefined overloaded TO_STRING operations
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING;
end package standard_additions;
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
use std.textio.all;
package body standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
function \?<\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L < R;
end function \?<\;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L <= R;
end function \?<=\;
function \?>\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L > R;
end function \?>\;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L >= R;
end function \?>=\;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BOOLEAN) return STRING is
begin
return BOOLEAN'image(VALUE);
end function TO_STRING;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = true) and (s'last_value = false));
end function rising_edge;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = false) and (s'last_value = true));
end function falling_edge;
function \?=\ (L, R : BIT) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function \?<\ (L, R : BIT) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function \?<\;
function \?<=\ (L, R : BIT) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function \?<=\;
function \?>\ (L, R : BIT) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function \?>\;
function \?>=\ (L, R : BIT) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function \?>=\;
function MINIMUM (L, R : BIT) return BIT is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT) return BIT is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BIT) return STRING is
begin
if VALUE = '1' then
return "1";
else
return "0";
end if;
end function TO_STRING;
function \??\ (L : BIT) return BOOLEAN is
begin
return L = '1';
end function \??\;
function RISING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '1') and (s'last_value = '0'));
end function rising_edge;
function FALLING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '0') and (s'last_value = '1'));
end function falling_edge;
function MINIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : CHARACTER) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := VALUE;
return result;
end function TO_STRING;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING is
begin
return SEVERITY_LEVEL'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : INTEGER) return STRING is
begin
return INTEGER'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : REAL) return REAL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL) return REAL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : REAL) return STRING is
begin
return REAL'image (VALUE);
end function TO_STRING;
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING is
begin
return to_string (VALUE, "%1." & INTEGER'image(DIGITS) & "f");
end function TO_STRING;
function "mod" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint mod rint) * 1.0 ns;
end function "mod";
function "rem" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint rem rint) * 1.0 ns;
end function "rem";
function MINIMUM (L, R : TIME) return TIME is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME) return TIME is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : TIME) return STRING is
begin
return TIME'image (VALUE);
end function TO_STRING;
function MINIMUM (L, R : STRING) return STRING is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : STRING) return STRING is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) and rv(i));
end loop;
end if;
return result;
end function "and";
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) or rv(i));
end loop;
end if;
return result;
end function "or";
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nand rv(i));
end loop;
end if;
return result;
end function "nand";
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nor rv(i));
end loop;
end if;
return result;
end function "nor";
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xor rv(i));
end loop;
end if;
return result;
end function "xor";
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xnor rv(i));
end loop;
end if;
return result;
end function "xnor";
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not (lv(i));
end loop;
return result;
end function "not";
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nand r;
end loop;
return result;
end function "nand";
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nand rv(i);
end loop;
return result;
end function "nand";
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nor r;
end loop;
return result;
end function "nor";
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nor rv(i);
end loop;
return result;
end function "nor";
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xnor r;
end loop;
return result;
end function "xnor";
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xnor rv(i);
end loop;
return result;
end function "xnor";
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'high);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sla";
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'low);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sra";
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-- function "=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN) return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return not result;
end function "nand";
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return not result;
end function "nand";
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return not result;
end function "nor";
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return not result;
end function "nor";
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return not result;
end function "xnor";
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return not result;
end function "xnor";
function and_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function \?=\ (L, R : BIT_VECTOR) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT_VECTOR) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function TO_STRING (VALUE : BIT_VECTOR) return STRING is
alias ivalue : BIT_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return "";
else
for i in ivalue'range loop
if iValue(i) = '0' then
result(i) := '0';
else
result(i) := '1';
end if;
end loop;
return result;
end if;
end function to_string;
-- alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
-- alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : BIT_VECTOR(0 to 2);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := ivalue(3*i to 3*i+2);
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
end case;
end loop;
return result;
end function to_ostring;
-- alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : BIT_VECTOR(0 to 3);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := ivalue(4*i to 4*i+3);
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
end case;
end loop;
return result;
end function to_hstring;
-- alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
-- type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: INTEGER_VECTOR; R: INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L: INTEGER_VECTOR; R: INTEGER) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: REAL_VECTOR; R: REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L: REAL_VECTOR; R: REAL) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined implicit operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: TIME_VECTOR; R: TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L: TIME_VECTOR; R: TIME) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING is
begin
return FILE_OPEN_KIND'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING is
begin
return FILE_OPEN_STATUS'image(VALUE);
end function TO_STRING;
-- USED INTERNALLY!
function justify (
value : in STRING;
justified : in SIDE := right;
field : in width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING is
variable L : LINE; -- pointer
begin
deallocate (L);
write (L => L,
VALUE => VALUE,
UNIT => UNIT);
return L.all;
end function to_string;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING is
constant czero : CHARACTER := '0'; -- zero
constant half : REAL := 0.4999999999; -- almost 0.5
-- Log10 funciton
function log10 (arg : REAL) return INTEGER is
variable i : INTEGER := 1;
begin
if ((arg = 0.0)) then
return 0;
elsif arg >= 1.0 then
while arg >= 10.0**i loop
i := i + 1;
end loop;
return (i-1);
else
while arg < 10.0**i loop
i := i - 1;
end loop;
return i;
end if;
end function log10;
-- purpose: writes a fractional real number into a line
procedure writefrc (
variable L : inout LINE; -- LINE
variable cdes : in CHARACTER;
variable precision : in INTEGER; -- number of decimal places
variable value : in REAL) is -- real value
variable rvar : REAL; -- temp variable
variable xint : INTEGER;
variable xreal : REAL;
begin
xreal := (10.0**(-precision));
write (L, '.');
rvar := value;
for i in 1 to precision loop
rvar := rvar * 10.0;
xint := INTEGER(rvar-0.49999999999); -- round
write (L, xint);
rvar := rvar - REAL(xint);
xreal := xreal * 10.0;
if (cdes = 'g') and (rvar < xreal) then
exit;
end if;
end loop;
end procedure writefrc;
-- purpose: replace the "." with a "@", and "e" with "j" to get around
-- read ("6.") and read ("2e") issues.
function subdot (
constant format : STRING)
return STRING is
variable result : STRING (format'range);
begin
for i in format'range loop
if (format(i) = '.') then
result(i) := '@'; -- Because the parser reads 6.2 as REAL
elsif (format(i) = 'e') then
result(i) := 'j'; -- Because the parser read 2e as REAL
elsif (format(i) = 'E') then
result(i) := 'J'; -- Because the parser reads 2E as REAL
else
result(i) := format(i);
end if;
end loop;
return result;
end function subdot;
-- purpose: find a . in a STRING
function isdot (
constant format : STRING)
return BOOLEAN is
begin
for i in format'range loop
if (format(i) = '@') then
return true;
end if;
end loop;
return false;
end function isdot;
variable exp : INTEGER; -- integer version of baseexp
variable bvalue : REAL; -- base value
variable roundvar, tvar : REAL; -- Rounding values
variable frcptr : INTEGER; -- integer version of number
variable fwidth, dwidth : INTEGER; -- field width and decimal width
variable dash, dot : BOOLEAN := false;
variable cdes, ddes : CHARACTER := ' ';
variable L : LINE; -- line type
begin
-- Perform the same function that "printf" does
-- examples "%6.2f" "%-7e" "%g"
if not (format(format'left) = '%') then
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end if;
L := new STRING'(subdot(format));
read (L, ddes); -- toss the '%'
case L.all(1) is
when '-' => dash := true;
when '@' => dash := true; -- in FP, a "-" and a "." are the same
when 'f' => cdes := 'f';
when 'F' => cdes := 'F';
when 'g' => cdes := 'g';
when 'G' => cdes := 'G';
when 'j' => cdes := 'e'; -- parser reads 5e as real, thus we sub j
when 'J' => cdes := 'E';
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|'8'|'9' => null;
when others =>
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end case;
if (dash or (cdes /= ' ')) then
read (L, ddes); -- toss the next character
end if;
if (cdes = ' ') then
if (isdot(L.all)) then -- if you see a . two numbers
read (L, fwidth); -- read field width
read (L, ddes); -- toss the next character .
read (L, dwidth); -- read decimal width
else
read (L, fwidth); -- read field width
dwidth := 6; -- the default decimal width is 6
end if;
read (L, cdes);
if (cdes = 'j') then
cdes := 'e'; -- because 2e reads as "REAL".
elsif (cdes = 'J') then
cdes := 'E';
end if;
else
if (cdes = 'E' or cdes = 'e') then
fwidth := 10; -- default for e and E is %10.6e
else
fwidth := 0; -- default for f and g is %0.6f
end if;
dwidth := 6;
end if;
deallocate (L); -- reclame the pointer L.
-- assert (not debug) report "Format: " & format & " "
-- & INTEGER'image(fwidth) & "." & INTEGER'image(dwidth) & cdes
-- severity note;
if (not (cdes = 'f' or cdes = 'F' or cdes = 'g' or cdes = 'G'
or cdes = 'e' or cdes = 'E')) then
report "to_string: Illegal format """ & format & '"' severity error;
return "";
end if;
if (VALUE < 0.0) then
bvalue := -value;
write (L, '-');
else
bvalue := value;
end if;
case cdes is
when 'e' | 'E' => -- 7.000E+01
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half); -- Write a single digit.
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
writefrc (-- Write out the fraction
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
write (L, cdes); -- e or E
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then -- we need another "0".
write (L, czero);
end if;
write (L, exp);
when 'f' | 'F' => -- 70.0
exp := log10(bvalue);
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
if (exp < 0) then -- 0.X case
write (L, czero);
else -- loop because real'high > integer'high
while (exp >= 0) loop
frcptr := INTEGER(bvalue * (10.0**(-exp)) - half);
write (L, frcptr);
bvalue := bvalue - (REAL(frcptr) * (10.0**exp));
exp := exp-1;
end loop;
end if;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
when 'g' | 'G' => -- 70
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth)); -- small number
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
frcptr := INTEGER(bvalue-half);
tvar := bvalue-roundvar - REAL(frcptr); -- even smaller number
if (exp < dwidth)
and (tvar < roundvar and tvar > -roundvar) then
-- and ((bvalue-roundvar) = real(frcptr)) then
write (L, frcptr); -- Just a short integer, write it.
elsif (exp >= dwidth) or (exp < -4) then
-- in "e" format (modified)
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half);
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
if (bvalue > (10.0**(1-dwidth))) then
dwidth := dwidth - 1;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
if (cdes = 'G') then
write (L, 'E');
else
write (L, 'e');
end if;
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then
write (L, czero);
end if;
write (L, exp);
else
-- in "f" format (modified)
if (exp < 0) then
write (L, czero);
dwidth := maximum (dwidth, 4); -- if exp < -4 or > precision.
bvalue := bvalue - roundvar; -- recalculate rounding
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar;
else
write (L, frcptr); -- integer part (always small)
bvalue := bvalue - (REAL(frcptr));
dwidth := dwidth - exp - 1;
end if;
if (bvalue > roundvar) then
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
end if;
when others => return "";
end case;
-- You don't truncate real numbers.
-- if (dot) then -- truncate
-- if (L.all'length > fwidth) then
-- return justify (value => L.all (1 to fwidth),
-- justified => RIGHT,
-- field => fwidth);
-- else
-- return justify (value => L.all,
-- justified => RIGHT,
-- field => fwidth);
-- end if;
if (dash) then -- fill to fwidth
return justify (value => L.all,
justified => left,
field => fwidth);
else
return justify (value => L.all,
justified => right,
field => fwidth);
end if;
end function to_string;
end package body standard_additions;
|
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
package standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN;
function \?<\ (L, R : BOOLEAN) return BOOLEAN;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN;
function \?>\ (L, R : BOOLEAN) return BOOLEAN;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function \?=\ (L, R : BIT) return BIT;
function \?/=\ (L, R : BIT) return BIT;
function \?<\ (L, R : BIT) return BIT;
function \?<=\ (L, R : BIT) return BIT;
function \?>\ (L, R : BIT) return BIT;
function \?>=\ (L, R : BIT) return BIT;
function MINIMUM (L, R : BIT) return BIT;
function MAXIMUM (L, R : BIT) return BIT;
function \??\ (L : BIT) return BOOLEAN;
function RISING_EDGE (signal S : BIT) return BOOLEAN;
function FALLING_EDGE (signal S : BIT) return BOOLEAN;
function MINIMUM (L, R : CHARACTER) return CHARACTER;
function MAXIMUM (L, R : CHARACTER) return CHARACTER;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MINIMUM (L, R : INTEGER) return INTEGER;
function MAXIMUM (L, R : INTEGER) return INTEGER;
function MINIMUM (L, R : REAL) return REAL;
function MAXIMUM (L, R : REAL) return REAL;
function "mod" (L, R : TIME) return TIME;
function "rem" (L, R : TIME) return TIME;
function MINIMUM (L, R : TIME) return TIME;
function MAXIMUM (L, R : TIME) return TIME;
function MINIMUM (L, R : STRING) return STRING;
function MAXIMUM (L, R : STRING) return STRING;
function MINIMUM (L : STRING) return CHARACTER;
function MAXIMUM (L : STRING) return CHARACTER;
type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
-- function "=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN_VECTOR) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN) -- return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function and_reduce (L : BIT_VECTOR) return BIT;
function or_reduce (L : BIT_VECTOR) return BIT;
function nand_reduce (L : BIT_VECTOR) return BIT;
function nor_reduce (L : BIT_VECTOR) return BIT;
function xor_reduce (L : BIT_VECTOR) return BIT;
function xnor_reduce (L : BIT_VECTOR) return BIT;
function \?=\ (L, R : BIT_VECTOR) return BIT;
function \?/=\ (L, R : BIT_VECTOR) return BIT;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MINIMUM (L : BIT_VECTOR) return BIT;
function MAXIMUM (L : BIT_VECTOR) return BIT;
function TO_STRING (VALUE : BIT_VECTOR) return STRING;
alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER;
type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN;
function "/=" (L, R : REAL_VECTOR) return BOOLEAN;
function "<" (L, R : REAL_VECTOR) return BOOLEAN;
function "<=" (L, R : REAL_VECTOR) return BOOLEAN;
function ">" (L, R : REAL_VECTOR) return BOOLEAN;
function ">=" (L, R : REAL_VECTOR) return BOOLEAN;
-- function "&" (L : REAL_VECTOR; R : REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L : REAL_VECTOR; R : REAL) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MINIMUM (L : REAL_VECTOR) return REAL;
function MAXIMUM (L : REAL_VECTOR) return REAL;
type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN;
function "/=" (L, R : TIME_VECTOR) return BOOLEAN;
function "<" (L, R : TIME_VECTOR) return BOOLEAN;
function "<=" (L, R : TIME_VECTOR) return BOOLEAN;
function ">" (L, R : TIME_VECTOR) return BOOLEAN;
function ">=" (L, R : TIME_VECTOR) return BOOLEAN;
-- function "&" (L : TIME_VECTOR; R : TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L : TIME_VECTOR; R : TIME) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MINIMUM (L : TIME_VECTOR) return TIME;
function MAXIMUM (L : TIME_VECTOR) return TIME;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
-- predefined TO_STRING operations on scalar types
function TO_STRING (VALUE : BOOLEAN) return STRING;
function TO_STRING (VALUE : BIT) return STRING;
function TO_STRING (VALUE : CHARACTER) return STRING;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING;
function TO_STRING (VALUE : INTEGER) return STRING;
function TO_STRING (VALUE : REAL) return STRING;
function TO_STRING (VALUE : TIME) return STRING;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING;
-- predefined overloaded TO_STRING operations
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING;
end package standard_additions;
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
use std.textio.all;
package body standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
function \?<\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L < R;
end function \?<\;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L <= R;
end function \?<=\;
function \?>\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L > R;
end function \?>\;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L >= R;
end function \?>=\;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BOOLEAN) return STRING is
begin
return BOOLEAN'image(VALUE);
end function TO_STRING;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = true) and (s'last_value = false));
end function rising_edge;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = false) and (s'last_value = true));
end function falling_edge;
function \?=\ (L, R : BIT) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function \?<\ (L, R : BIT) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function \?<\;
function \?<=\ (L, R : BIT) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function \?<=\;
function \?>\ (L, R : BIT) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function \?>\;
function \?>=\ (L, R : BIT) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function \?>=\;
function MINIMUM (L, R : BIT) return BIT is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT) return BIT is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BIT) return STRING is
begin
if VALUE = '1' then
return "1";
else
return "0";
end if;
end function TO_STRING;
function \??\ (L : BIT) return BOOLEAN is
begin
return L = '1';
end function \??\;
function RISING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '1') and (s'last_value = '0'));
end function rising_edge;
function FALLING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '0') and (s'last_value = '1'));
end function falling_edge;
function MINIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : CHARACTER) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := VALUE;
return result;
end function TO_STRING;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING is
begin
return SEVERITY_LEVEL'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : INTEGER) return STRING is
begin
return INTEGER'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : REAL) return REAL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL) return REAL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : REAL) return STRING is
begin
return REAL'image (VALUE);
end function TO_STRING;
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING is
begin
return to_string (VALUE, "%1." & INTEGER'image(DIGITS) & "f");
end function TO_STRING;
function "mod" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint mod rint) * 1.0 ns;
end function "mod";
function "rem" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint rem rint) * 1.0 ns;
end function "rem";
function MINIMUM (L, R : TIME) return TIME is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME) return TIME is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : TIME) return STRING is
begin
return TIME'image (VALUE);
end function TO_STRING;
function MINIMUM (L, R : STRING) return STRING is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : STRING) return STRING is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) and rv(i));
end loop;
end if;
return result;
end function "and";
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) or rv(i));
end loop;
end if;
return result;
end function "or";
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nand rv(i));
end loop;
end if;
return result;
end function "nand";
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nor rv(i));
end loop;
end if;
return result;
end function "nor";
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xor rv(i));
end loop;
end if;
return result;
end function "xor";
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xnor rv(i));
end loop;
end if;
return result;
end function "xnor";
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not (lv(i));
end loop;
return result;
end function "not";
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nand r;
end loop;
return result;
end function "nand";
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nand rv(i);
end loop;
return result;
end function "nand";
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nor r;
end loop;
return result;
end function "nor";
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nor rv(i);
end loop;
return result;
end function "nor";
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xnor r;
end loop;
return result;
end function "xnor";
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xnor rv(i);
end loop;
return result;
end function "xnor";
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'high);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sla";
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'low);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sra";
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-- function "=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN) return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return not result;
end function "nand";
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return not result;
end function "nand";
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return not result;
end function "nor";
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return not result;
end function "nor";
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return not result;
end function "xnor";
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return not result;
end function "xnor";
function and_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function \?=\ (L, R : BIT_VECTOR) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT_VECTOR) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function TO_STRING (VALUE : BIT_VECTOR) return STRING is
alias ivalue : BIT_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return "";
else
for i in ivalue'range loop
if iValue(i) = '0' then
result(i) := '0';
else
result(i) := '1';
end if;
end loop;
return result;
end if;
end function to_string;
-- alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
-- alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : BIT_VECTOR(0 to 2);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := ivalue(3*i to 3*i+2);
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
end case;
end loop;
return result;
end function to_ostring;
-- alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : BIT_VECTOR(0 to 3);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := ivalue(4*i to 4*i+3);
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
end case;
end loop;
return result;
end function to_hstring;
-- alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
-- type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: INTEGER_VECTOR; R: INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L: INTEGER_VECTOR; R: INTEGER) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: REAL_VECTOR; R: REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L: REAL_VECTOR; R: REAL) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined implicit operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: TIME_VECTOR; R: TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L: TIME_VECTOR; R: TIME) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING is
begin
return FILE_OPEN_KIND'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING is
begin
return FILE_OPEN_STATUS'image(VALUE);
end function TO_STRING;
-- USED INTERNALLY!
function justify (
value : in STRING;
justified : in SIDE := right;
field : in width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING is
variable L : LINE; -- pointer
begin
deallocate (L);
write (L => L,
VALUE => VALUE,
UNIT => UNIT);
return L.all;
end function to_string;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING is
constant czero : CHARACTER := '0'; -- zero
constant half : REAL := 0.4999999999; -- almost 0.5
-- Log10 funciton
function log10 (arg : REAL) return INTEGER is
variable i : INTEGER := 1;
begin
if ((arg = 0.0)) then
return 0;
elsif arg >= 1.0 then
while arg >= 10.0**i loop
i := i + 1;
end loop;
return (i-1);
else
while arg < 10.0**i loop
i := i - 1;
end loop;
return i;
end if;
end function log10;
-- purpose: writes a fractional real number into a line
procedure writefrc (
variable L : inout LINE; -- LINE
variable cdes : in CHARACTER;
variable precision : in INTEGER; -- number of decimal places
variable value : in REAL) is -- real value
variable rvar : REAL; -- temp variable
variable xint : INTEGER;
variable xreal : REAL;
begin
xreal := (10.0**(-precision));
write (L, '.');
rvar := value;
for i in 1 to precision loop
rvar := rvar * 10.0;
xint := INTEGER(rvar-0.49999999999); -- round
write (L, xint);
rvar := rvar - REAL(xint);
xreal := xreal * 10.0;
if (cdes = 'g') and (rvar < xreal) then
exit;
end if;
end loop;
end procedure writefrc;
-- purpose: replace the "." with a "@", and "e" with "j" to get around
-- read ("6.") and read ("2e") issues.
function subdot (
constant format : STRING)
return STRING is
variable result : STRING (format'range);
begin
for i in format'range loop
if (format(i) = '.') then
result(i) := '@'; -- Because the parser reads 6.2 as REAL
elsif (format(i) = 'e') then
result(i) := 'j'; -- Because the parser read 2e as REAL
elsif (format(i) = 'E') then
result(i) := 'J'; -- Because the parser reads 2E as REAL
else
result(i) := format(i);
end if;
end loop;
return result;
end function subdot;
-- purpose: find a . in a STRING
function isdot (
constant format : STRING)
return BOOLEAN is
begin
for i in format'range loop
if (format(i) = '@') then
return true;
end if;
end loop;
return false;
end function isdot;
variable exp : INTEGER; -- integer version of baseexp
variable bvalue : REAL; -- base value
variable roundvar, tvar : REAL; -- Rounding values
variable frcptr : INTEGER; -- integer version of number
variable fwidth, dwidth : INTEGER; -- field width and decimal width
variable dash, dot : BOOLEAN := false;
variable cdes, ddes : CHARACTER := ' ';
variable L : LINE; -- line type
begin
-- Perform the same function that "printf" does
-- examples "%6.2f" "%-7e" "%g"
if not (format(format'left) = '%') then
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end if;
L := new STRING'(subdot(format));
read (L, ddes); -- toss the '%'
case L.all(1) is
when '-' => dash := true;
when '@' => dash := true; -- in FP, a "-" and a "." are the same
when 'f' => cdes := 'f';
when 'F' => cdes := 'F';
when 'g' => cdes := 'g';
when 'G' => cdes := 'G';
when 'j' => cdes := 'e'; -- parser reads 5e as real, thus we sub j
when 'J' => cdes := 'E';
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|'8'|'9' => null;
when others =>
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end case;
if (dash or (cdes /= ' ')) then
read (L, ddes); -- toss the next character
end if;
if (cdes = ' ') then
if (isdot(L.all)) then -- if you see a . two numbers
read (L, fwidth); -- read field width
read (L, ddes); -- toss the next character .
read (L, dwidth); -- read decimal width
else
read (L, fwidth); -- read field width
dwidth := 6; -- the default decimal width is 6
end if;
read (L, cdes);
if (cdes = 'j') then
cdes := 'e'; -- because 2e reads as "REAL".
elsif (cdes = 'J') then
cdes := 'E';
end if;
else
if (cdes = 'E' or cdes = 'e') then
fwidth := 10; -- default for e and E is %10.6e
else
fwidth := 0; -- default for f and g is %0.6f
end if;
dwidth := 6;
end if;
deallocate (L); -- reclame the pointer L.
-- assert (not debug) report "Format: " & format & " "
-- & INTEGER'image(fwidth) & "." & INTEGER'image(dwidth) & cdes
-- severity note;
if (not (cdes = 'f' or cdes = 'F' or cdes = 'g' or cdes = 'G'
or cdes = 'e' or cdes = 'E')) then
report "to_string: Illegal format """ & format & '"' severity error;
return "";
end if;
if (VALUE < 0.0) then
bvalue := -value;
write (L, '-');
else
bvalue := value;
end if;
case cdes is
when 'e' | 'E' => -- 7.000E+01
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half); -- Write a single digit.
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
writefrc (-- Write out the fraction
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
write (L, cdes); -- e or E
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then -- we need another "0".
write (L, czero);
end if;
write (L, exp);
when 'f' | 'F' => -- 70.0
exp := log10(bvalue);
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
if (exp < 0) then -- 0.X case
write (L, czero);
else -- loop because real'high > integer'high
while (exp >= 0) loop
frcptr := INTEGER(bvalue * (10.0**(-exp)) - half);
write (L, frcptr);
bvalue := bvalue - (REAL(frcptr) * (10.0**exp));
exp := exp-1;
end loop;
end if;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
when 'g' | 'G' => -- 70
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth)); -- small number
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
frcptr := INTEGER(bvalue-half);
tvar := bvalue-roundvar - REAL(frcptr); -- even smaller number
if (exp < dwidth)
and (tvar < roundvar and tvar > -roundvar) then
-- and ((bvalue-roundvar) = real(frcptr)) then
write (L, frcptr); -- Just a short integer, write it.
elsif (exp >= dwidth) or (exp < -4) then
-- in "e" format (modified)
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half);
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
if (bvalue > (10.0**(1-dwidth))) then
dwidth := dwidth - 1;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
if (cdes = 'G') then
write (L, 'E');
else
write (L, 'e');
end if;
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then
write (L, czero);
end if;
write (L, exp);
else
-- in "f" format (modified)
if (exp < 0) then
write (L, czero);
dwidth := maximum (dwidth, 4); -- if exp < -4 or > precision.
bvalue := bvalue - roundvar; -- recalculate rounding
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar;
else
write (L, frcptr); -- integer part (always small)
bvalue := bvalue - (REAL(frcptr));
dwidth := dwidth - exp - 1;
end if;
if (bvalue > roundvar) then
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
end if;
when others => return "";
end case;
-- You don't truncate real numbers.
-- if (dot) then -- truncate
-- if (L.all'length > fwidth) then
-- return justify (value => L.all (1 to fwidth),
-- justified => RIGHT,
-- field => fwidth);
-- else
-- return justify (value => L.all,
-- justified => RIGHT,
-- field => fwidth);
-- end if;
if (dash) then -- fill to fwidth
return justify (value => L.all,
justified => left,
field => fwidth);
else
return justify (value => L.all,
justified => right,
field => fwidth);
end if;
end function to_string;
end package body standard_additions;
|
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
package standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN;
function \?<\ (L, R : BOOLEAN) return BOOLEAN;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN;
function \?>\ (L, R : BOOLEAN) return BOOLEAN;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function \?=\ (L, R : BIT) return BIT;
function \?/=\ (L, R : BIT) return BIT;
function \?<\ (L, R : BIT) return BIT;
function \?<=\ (L, R : BIT) return BIT;
function \?>\ (L, R : BIT) return BIT;
function \?>=\ (L, R : BIT) return BIT;
function MINIMUM (L, R : BIT) return BIT;
function MAXIMUM (L, R : BIT) return BIT;
function \??\ (L : BIT) return BOOLEAN;
function RISING_EDGE (signal S : BIT) return BOOLEAN;
function FALLING_EDGE (signal S : BIT) return BOOLEAN;
function MINIMUM (L, R : CHARACTER) return CHARACTER;
function MAXIMUM (L, R : CHARACTER) return CHARACTER;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MINIMUM (L, R : INTEGER) return INTEGER;
function MAXIMUM (L, R : INTEGER) return INTEGER;
function MINIMUM (L, R : REAL) return REAL;
function MAXIMUM (L, R : REAL) return REAL;
function "mod" (L, R : TIME) return TIME;
function "rem" (L, R : TIME) return TIME;
function MINIMUM (L, R : TIME) return TIME;
function MAXIMUM (L, R : TIME) return TIME;
function MINIMUM (L, R : STRING) return STRING;
function MAXIMUM (L, R : STRING) return STRING;
function MINIMUM (L : STRING) return CHARACTER;
function MAXIMUM (L : STRING) return CHARACTER;
type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
-- function "=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN_VECTOR) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN) -- return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function and_reduce (L : BIT_VECTOR) return BIT;
function or_reduce (L : BIT_VECTOR) return BIT;
function nand_reduce (L : BIT_VECTOR) return BIT;
function nor_reduce (L : BIT_VECTOR) return BIT;
function xor_reduce (L : BIT_VECTOR) return BIT;
function xnor_reduce (L : BIT_VECTOR) return BIT;
function \?=\ (L, R : BIT_VECTOR) return BIT;
function \?/=\ (L, R : BIT_VECTOR) return BIT;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MINIMUM (L : BIT_VECTOR) return BIT;
function MAXIMUM (L : BIT_VECTOR) return BIT;
function TO_STRING (VALUE : BIT_VECTOR) return STRING;
alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER;
type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN;
function "/=" (L, R : REAL_VECTOR) return BOOLEAN;
function "<" (L, R : REAL_VECTOR) return BOOLEAN;
function "<=" (L, R : REAL_VECTOR) return BOOLEAN;
function ">" (L, R : REAL_VECTOR) return BOOLEAN;
function ">=" (L, R : REAL_VECTOR) return BOOLEAN;
-- function "&" (L : REAL_VECTOR; R : REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L : REAL_VECTOR; R : REAL) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MINIMUM (L : REAL_VECTOR) return REAL;
function MAXIMUM (L : REAL_VECTOR) return REAL;
type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN;
function "/=" (L, R : TIME_VECTOR) return BOOLEAN;
function "<" (L, R : TIME_VECTOR) return BOOLEAN;
function "<=" (L, R : TIME_VECTOR) return BOOLEAN;
function ">" (L, R : TIME_VECTOR) return BOOLEAN;
function ">=" (L, R : TIME_VECTOR) return BOOLEAN;
-- function "&" (L : TIME_VECTOR; R : TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L : TIME_VECTOR; R : TIME) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MINIMUM (L : TIME_VECTOR) return TIME;
function MAXIMUM (L : TIME_VECTOR) return TIME;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
-- predefined TO_STRING operations on scalar types
function TO_STRING (VALUE : BOOLEAN) return STRING;
function TO_STRING (VALUE : BIT) return STRING;
function TO_STRING (VALUE : CHARACTER) return STRING;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING;
function TO_STRING (VALUE : INTEGER) return STRING;
function TO_STRING (VALUE : REAL) return STRING;
function TO_STRING (VALUE : TIME) return STRING;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING;
-- predefined overloaded TO_STRING operations
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING;
end package standard_additions;
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
use std.textio.all;
package body standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
function \?<\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L < R;
end function \?<\;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L <= R;
end function \?<=\;
function \?>\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L > R;
end function \?>\;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L >= R;
end function \?>=\;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BOOLEAN) return STRING is
begin
return BOOLEAN'image(VALUE);
end function TO_STRING;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = true) and (s'last_value = false));
end function rising_edge;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = false) and (s'last_value = true));
end function falling_edge;
function \?=\ (L, R : BIT) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function \?<\ (L, R : BIT) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function \?<\;
function \?<=\ (L, R : BIT) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function \?<=\;
function \?>\ (L, R : BIT) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function \?>\;
function \?>=\ (L, R : BIT) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function \?>=\;
function MINIMUM (L, R : BIT) return BIT is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT) return BIT is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BIT) return STRING is
begin
if VALUE = '1' then
return "1";
else
return "0";
end if;
end function TO_STRING;
function \??\ (L : BIT) return BOOLEAN is
begin
return L = '1';
end function \??\;
function RISING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '1') and (s'last_value = '0'));
end function rising_edge;
function FALLING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '0') and (s'last_value = '1'));
end function falling_edge;
function MINIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : CHARACTER) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := VALUE;
return result;
end function TO_STRING;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING is
begin
return SEVERITY_LEVEL'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : INTEGER) return STRING is
begin
return INTEGER'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : REAL) return REAL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL) return REAL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : REAL) return STRING is
begin
return REAL'image (VALUE);
end function TO_STRING;
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING is
begin
return to_string (VALUE, "%1." & INTEGER'image(DIGITS) & "f");
end function TO_STRING;
function "mod" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint mod rint) * 1.0 ns;
end function "mod";
function "rem" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint rem rint) * 1.0 ns;
end function "rem";
function MINIMUM (L, R : TIME) return TIME is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME) return TIME is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : TIME) return STRING is
begin
return TIME'image (VALUE);
end function TO_STRING;
function MINIMUM (L, R : STRING) return STRING is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : STRING) return STRING is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) and rv(i));
end loop;
end if;
return result;
end function "and";
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) or rv(i));
end loop;
end if;
return result;
end function "or";
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nand rv(i));
end loop;
end if;
return result;
end function "nand";
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nor rv(i));
end loop;
end if;
return result;
end function "nor";
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xor rv(i));
end loop;
end if;
return result;
end function "xor";
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xnor rv(i));
end loop;
end if;
return result;
end function "xnor";
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not (lv(i));
end loop;
return result;
end function "not";
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nand r;
end loop;
return result;
end function "nand";
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nand rv(i);
end loop;
return result;
end function "nand";
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nor r;
end loop;
return result;
end function "nor";
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nor rv(i);
end loop;
return result;
end function "nor";
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xnor r;
end loop;
return result;
end function "xnor";
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xnor rv(i);
end loop;
return result;
end function "xnor";
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'high);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sla";
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'low);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sra";
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-- function "=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN) return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return not result;
end function "nand";
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return not result;
end function "nand";
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return not result;
end function "nor";
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return not result;
end function "nor";
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return not result;
end function "xnor";
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return not result;
end function "xnor";
function and_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function \?=\ (L, R : BIT_VECTOR) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT_VECTOR) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function TO_STRING (VALUE : BIT_VECTOR) return STRING is
alias ivalue : BIT_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return "";
else
for i in ivalue'range loop
if iValue(i) = '0' then
result(i) := '0';
else
result(i) := '1';
end if;
end loop;
return result;
end if;
end function to_string;
-- alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
-- alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : BIT_VECTOR(0 to 2);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := ivalue(3*i to 3*i+2);
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
end case;
end loop;
return result;
end function to_ostring;
-- alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : BIT_VECTOR(0 to 3);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := ivalue(4*i to 4*i+3);
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
end case;
end loop;
return result;
end function to_hstring;
-- alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
-- type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: INTEGER_VECTOR; R: INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L: INTEGER_VECTOR; R: INTEGER) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: REAL_VECTOR; R: REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L: REAL_VECTOR; R: REAL) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined implicit operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: TIME_VECTOR; R: TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L: TIME_VECTOR; R: TIME) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING is
begin
return FILE_OPEN_KIND'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING is
begin
return FILE_OPEN_STATUS'image(VALUE);
end function TO_STRING;
-- USED INTERNALLY!
function justify (
value : in STRING;
justified : in SIDE := right;
field : in width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING is
variable L : LINE; -- pointer
begin
deallocate (L);
write (L => L,
VALUE => VALUE,
UNIT => UNIT);
return L.all;
end function to_string;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING is
constant czero : CHARACTER := '0'; -- zero
constant half : REAL := 0.4999999999; -- almost 0.5
-- Log10 funciton
function log10 (arg : REAL) return INTEGER is
variable i : INTEGER := 1;
begin
if ((arg = 0.0)) then
return 0;
elsif arg >= 1.0 then
while arg >= 10.0**i loop
i := i + 1;
end loop;
return (i-1);
else
while arg < 10.0**i loop
i := i - 1;
end loop;
return i;
end if;
end function log10;
-- purpose: writes a fractional real number into a line
procedure writefrc (
variable L : inout LINE; -- LINE
variable cdes : in CHARACTER;
variable precision : in INTEGER; -- number of decimal places
variable value : in REAL) is -- real value
variable rvar : REAL; -- temp variable
variable xint : INTEGER;
variable xreal : REAL;
begin
xreal := (10.0**(-precision));
write (L, '.');
rvar := value;
for i in 1 to precision loop
rvar := rvar * 10.0;
xint := INTEGER(rvar-0.49999999999); -- round
write (L, xint);
rvar := rvar - REAL(xint);
xreal := xreal * 10.0;
if (cdes = 'g') and (rvar < xreal) then
exit;
end if;
end loop;
end procedure writefrc;
-- purpose: replace the "." with a "@", and "e" with "j" to get around
-- read ("6.") and read ("2e") issues.
function subdot (
constant format : STRING)
return STRING is
variable result : STRING (format'range);
begin
for i in format'range loop
if (format(i) = '.') then
result(i) := '@'; -- Because the parser reads 6.2 as REAL
elsif (format(i) = 'e') then
result(i) := 'j'; -- Because the parser read 2e as REAL
elsif (format(i) = 'E') then
result(i) := 'J'; -- Because the parser reads 2E as REAL
else
result(i) := format(i);
end if;
end loop;
return result;
end function subdot;
-- purpose: find a . in a STRING
function isdot (
constant format : STRING)
return BOOLEAN is
begin
for i in format'range loop
if (format(i) = '@') then
return true;
end if;
end loop;
return false;
end function isdot;
variable exp : INTEGER; -- integer version of baseexp
variable bvalue : REAL; -- base value
variable roundvar, tvar : REAL; -- Rounding values
variable frcptr : INTEGER; -- integer version of number
variable fwidth, dwidth : INTEGER; -- field width and decimal width
variable dash, dot : BOOLEAN := false;
variable cdes, ddes : CHARACTER := ' ';
variable L : LINE; -- line type
begin
-- Perform the same function that "printf" does
-- examples "%6.2f" "%-7e" "%g"
if not (format(format'left) = '%') then
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end if;
L := new STRING'(subdot(format));
read (L, ddes); -- toss the '%'
case L.all(1) is
when '-' => dash := true;
when '@' => dash := true; -- in FP, a "-" and a "." are the same
when 'f' => cdes := 'f';
when 'F' => cdes := 'F';
when 'g' => cdes := 'g';
when 'G' => cdes := 'G';
when 'j' => cdes := 'e'; -- parser reads 5e as real, thus we sub j
when 'J' => cdes := 'E';
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|'8'|'9' => null;
when others =>
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end case;
if (dash or (cdes /= ' ')) then
read (L, ddes); -- toss the next character
end if;
if (cdes = ' ') then
if (isdot(L.all)) then -- if you see a . two numbers
read (L, fwidth); -- read field width
read (L, ddes); -- toss the next character .
read (L, dwidth); -- read decimal width
else
read (L, fwidth); -- read field width
dwidth := 6; -- the default decimal width is 6
end if;
read (L, cdes);
if (cdes = 'j') then
cdes := 'e'; -- because 2e reads as "REAL".
elsif (cdes = 'J') then
cdes := 'E';
end if;
else
if (cdes = 'E' or cdes = 'e') then
fwidth := 10; -- default for e and E is %10.6e
else
fwidth := 0; -- default for f and g is %0.6f
end if;
dwidth := 6;
end if;
deallocate (L); -- reclame the pointer L.
-- assert (not debug) report "Format: " & format & " "
-- & INTEGER'image(fwidth) & "." & INTEGER'image(dwidth) & cdes
-- severity note;
if (not (cdes = 'f' or cdes = 'F' or cdes = 'g' or cdes = 'G'
or cdes = 'e' or cdes = 'E')) then
report "to_string: Illegal format """ & format & '"' severity error;
return "";
end if;
if (VALUE < 0.0) then
bvalue := -value;
write (L, '-');
else
bvalue := value;
end if;
case cdes is
when 'e' | 'E' => -- 7.000E+01
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half); -- Write a single digit.
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
writefrc (-- Write out the fraction
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
write (L, cdes); -- e or E
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then -- we need another "0".
write (L, czero);
end if;
write (L, exp);
when 'f' | 'F' => -- 70.0
exp := log10(bvalue);
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
if (exp < 0) then -- 0.X case
write (L, czero);
else -- loop because real'high > integer'high
while (exp >= 0) loop
frcptr := INTEGER(bvalue * (10.0**(-exp)) - half);
write (L, frcptr);
bvalue := bvalue - (REAL(frcptr) * (10.0**exp));
exp := exp-1;
end loop;
end if;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
when 'g' | 'G' => -- 70
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth)); -- small number
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
frcptr := INTEGER(bvalue-half);
tvar := bvalue-roundvar - REAL(frcptr); -- even smaller number
if (exp < dwidth)
and (tvar < roundvar and tvar > -roundvar) then
-- and ((bvalue-roundvar) = real(frcptr)) then
write (L, frcptr); -- Just a short integer, write it.
elsif (exp >= dwidth) or (exp < -4) then
-- in "e" format (modified)
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half);
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
if (bvalue > (10.0**(1-dwidth))) then
dwidth := dwidth - 1;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
if (cdes = 'G') then
write (L, 'E');
else
write (L, 'e');
end if;
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then
write (L, czero);
end if;
write (L, exp);
else
-- in "f" format (modified)
if (exp < 0) then
write (L, czero);
dwidth := maximum (dwidth, 4); -- if exp < -4 or > precision.
bvalue := bvalue - roundvar; -- recalculate rounding
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar;
else
write (L, frcptr); -- integer part (always small)
bvalue := bvalue - (REAL(frcptr));
dwidth := dwidth - exp - 1;
end if;
if (bvalue > roundvar) then
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
end if;
when others => return "";
end case;
-- You don't truncate real numbers.
-- if (dot) then -- truncate
-- if (L.all'length > fwidth) then
-- return justify (value => L.all (1 to fwidth),
-- justified => RIGHT,
-- field => fwidth);
-- else
-- return justify (value => L.all,
-- justified => RIGHT,
-- field => fwidth);
-- end if;
if (dash) then -- fill to fwidth
return justify (value => L.all,
justified => left,
field => fwidth);
else
return justify (value => L.all,
justified => right,
field => fwidth);
end if;
end function to_string;
end package body standard_additions;
|
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
package standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN;
function \?<\ (L, R : BOOLEAN) return BOOLEAN;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN;
function \?>\ (L, R : BOOLEAN) return BOOLEAN;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function \?=\ (L, R : BIT) return BIT;
function \?/=\ (L, R : BIT) return BIT;
function \?<\ (L, R : BIT) return BIT;
function \?<=\ (L, R : BIT) return BIT;
function \?>\ (L, R : BIT) return BIT;
function \?>=\ (L, R : BIT) return BIT;
function MINIMUM (L, R : BIT) return BIT;
function MAXIMUM (L, R : BIT) return BIT;
function \??\ (L : BIT) return BOOLEAN;
function RISING_EDGE (signal S : BIT) return BOOLEAN;
function FALLING_EDGE (signal S : BIT) return BOOLEAN;
function MINIMUM (L, R : CHARACTER) return CHARACTER;
function MAXIMUM (L, R : CHARACTER) return CHARACTER;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MINIMUM (L, R : INTEGER) return INTEGER;
function MAXIMUM (L, R : INTEGER) return INTEGER;
function MINIMUM (L, R : REAL) return REAL;
function MAXIMUM (L, R : REAL) return REAL;
function "mod" (L, R : TIME) return TIME;
function "rem" (L, R : TIME) return TIME;
function MINIMUM (L, R : TIME) return TIME;
function MAXIMUM (L, R : TIME) return TIME;
function MINIMUM (L, R : STRING) return STRING;
function MAXIMUM (L, R : STRING) return STRING;
function MINIMUM (L : STRING) return CHARACTER;
function MAXIMUM (L : STRING) return CHARACTER;
type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
-- function "=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN_VECTOR) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN) -- return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function and_reduce (L : BIT_VECTOR) return BIT;
function or_reduce (L : BIT_VECTOR) return BIT;
function nand_reduce (L : BIT_VECTOR) return BIT;
function nor_reduce (L : BIT_VECTOR) return BIT;
function xor_reduce (L : BIT_VECTOR) return BIT;
function xnor_reduce (L : BIT_VECTOR) return BIT;
function \?=\ (L, R : BIT_VECTOR) return BIT;
function \?/=\ (L, R : BIT_VECTOR) return BIT;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MINIMUM (L : BIT_VECTOR) return BIT;
function MAXIMUM (L : BIT_VECTOR) return BIT;
function TO_STRING (VALUE : BIT_VECTOR) return STRING;
alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER;
type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN;
function "/=" (L, R : REAL_VECTOR) return BOOLEAN;
function "<" (L, R : REAL_VECTOR) return BOOLEAN;
function "<=" (L, R : REAL_VECTOR) return BOOLEAN;
function ">" (L, R : REAL_VECTOR) return BOOLEAN;
function ">=" (L, R : REAL_VECTOR) return BOOLEAN;
-- function "&" (L : REAL_VECTOR; R : REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L : REAL_VECTOR; R : REAL) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MINIMUM (L : REAL_VECTOR) return REAL;
function MAXIMUM (L : REAL_VECTOR) return REAL;
type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN;
function "/=" (L, R : TIME_VECTOR) return BOOLEAN;
function "<" (L, R : TIME_VECTOR) return BOOLEAN;
function "<=" (L, R : TIME_VECTOR) return BOOLEAN;
function ">" (L, R : TIME_VECTOR) return BOOLEAN;
function ">=" (L, R : TIME_VECTOR) return BOOLEAN;
-- function "&" (L : TIME_VECTOR; R : TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L : TIME_VECTOR; R : TIME) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MINIMUM (L : TIME_VECTOR) return TIME;
function MAXIMUM (L : TIME_VECTOR) return TIME;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
-- predefined TO_STRING operations on scalar types
function TO_STRING (VALUE : BOOLEAN) return STRING;
function TO_STRING (VALUE : BIT) return STRING;
function TO_STRING (VALUE : CHARACTER) return STRING;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING;
function TO_STRING (VALUE : INTEGER) return STRING;
function TO_STRING (VALUE : REAL) return STRING;
function TO_STRING (VALUE : TIME) return STRING;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING;
-- predefined overloaded TO_STRING operations
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING;
end package standard_additions;
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
use std.textio.all;
package body standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
function \?<\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L < R;
end function \?<\;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L <= R;
end function \?<=\;
function \?>\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L > R;
end function \?>\;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L >= R;
end function \?>=\;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BOOLEAN) return STRING is
begin
return BOOLEAN'image(VALUE);
end function TO_STRING;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = true) and (s'last_value = false));
end function rising_edge;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = false) and (s'last_value = true));
end function falling_edge;
function \?=\ (L, R : BIT) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function \?<\ (L, R : BIT) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function \?<\;
function \?<=\ (L, R : BIT) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function \?<=\;
function \?>\ (L, R : BIT) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function \?>\;
function \?>=\ (L, R : BIT) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function \?>=\;
function MINIMUM (L, R : BIT) return BIT is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT) return BIT is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BIT) return STRING is
begin
if VALUE = '1' then
return "1";
else
return "0";
end if;
end function TO_STRING;
function \??\ (L : BIT) return BOOLEAN is
begin
return L = '1';
end function \??\;
function RISING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '1') and (s'last_value = '0'));
end function rising_edge;
function FALLING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '0') and (s'last_value = '1'));
end function falling_edge;
function MINIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : CHARACTER) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := VALUE;
return result;
end function TO_STRING;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING is
begin
return SEVERITY_LEVEL'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : INTEGER) return STRING is
begin
return INTEGER'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : REAL) return REAL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL) return REAL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : REAL) return STRING is
begin
return REAL'image (VALUE);
end function TO_STRING;
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING is
begin
return to_string (VALUE, "%1." & INTEGER'image(DIGITS) & "f");
end function TO_STRING;
function "mod" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint mod rint) * 1.0 ns;
end function "mod";
function "rem" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint rem rint) * 1.0 ns;
end function "rem";
function MINIMUM (L, R : TIME) return TIME is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME) return TIME is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : TIME) return STRING is
begin
return TIME'image (VALUE);
end function TO_STRING;
function MINIMUM (L, R : STRING) return STRING is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : STRING) return STRING is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) and rv(i));
end loop;
end if;
return result;
end function "and";
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) or rv(i));
end loop;
end if;
return result;
end function "or";
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nand rv(i));
end loop;
end if;
return result;
end function "nand";
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nor rv(i));
end loop;
end if;
return result;
end function "nor";
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xor rv(i));
end loop;
end if;
return result;
end function "xor";
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xnor rv(i));
end loop;
end if;
return result;
end function "xnor";
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not (lv(i));
end loop;
return result;
end function "not";
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nand r;
end loop;
return result;
end function "nand";
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nand rv(i);
end loop;
return result;
end function "nand";
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nor r;
end loop;
return result;
end function "nor";
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nor rv(i);
end loop;
return result;
end function "nor";
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xnor r;
end loop;
return result;
end function "xnor";
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xnor rv(i);
end loop;
return result;
end function "xnor";
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'high);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sla";
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'low);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sra";
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-- function "=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN) return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return not result;
end function "nand";
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return not result;
end function "nand";
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return not result;
end function "nor";
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return not result;
end function "nor";
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return not result;
end function "xnor";
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return not result;
end function "xnor";
function and_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function \?=\ (L, R : BIT_VECTOR) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT_VECTOR) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function TO_STRING (VALUE : BIT_VECTOR) return STRING is
alias ivalue : BIT_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return "";
else
for i in ivalue'range loop
if iValue(i) = '0' then
result(i) := '0';
else
result(i) := '1';
end if;
end loop;
return result;
end if;
end function to_string;
-- alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
-- alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : BIT_VECTOR(0 to 2);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := ivalue(3*i to 3*i+2);
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
end case;
end loop;
return result;
end function to_ostring;
-- alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : BIT_VECTOR(0 to 3);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := ivalue(4*i to 4*i+3);
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
end case;
end loop;
return result;
end function to_hstring;
-- alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
-- type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: INTEGER_VECTOR; R: INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L: INTEGER_VECTOR; R: INTEGER) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: REAL_VECTOR; R: REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L: REAL_VECTOR; R: REAL) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined implicit operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: TIME_VECTOR; R: TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L: TIME_VECTOR; R: TIME) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING is
begin
return FILE_OPEN_KIND'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING is
begin
return FILE_OPEN_STATUS'image(VALUE);
end function TO_STRING;
-- USED INTERNALLY!
function justify (
value : in STRING;
justified : in SIDE := right;
field : in width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING is
variable L : LINE; -- pointer
begin
deallocate (L);
write (L => L,
VALUE => VALUE,
UNIT => UNIT);
return L.all;
end function to_string;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING is
constant czero : CHARACTER := '0'; -- zero
constant half : REAL := 0.4999999999; -- almost 0.5
-- Log10 funciton
function log10 (arg : REAL) return INTEGER is
variable i : INTEGER := 1;
begin
if ((arg = 0.0)) then
return 0;
elsif arg >= 1.0 then
while arg >= 10.0**i loop
i := i + 1;
end loop;
return (i-1);
else
while arg < 10.0**i loop
i := i - 1;
end loop;
return i;
end if;
end function log10;
-- purpose: writes a fractional real number into a line
procedure writefrc (
variable L : inout LINE; -- LINE
variable cdes : in CHARACTER;
variable precision : in INTEGER; -- number of decimal places
variable value : in REAL) is -- real value
variable rvar : REAL; -- temp variable
variable xint : INTEGER;
variable xreal : REAL;
begin
xreal := (10.0**(-precision));
write (L, '.');
rvar := value;
for i in 1 to precision loop
rvar := rvar * 10.0;
xint := INTEGER(rvar-0.49999999999); -- round
write (L, xint);
rvar := rvar - REAL(xint);
xreal := xreal * 10.0;
if (cdes = 'g') and (rvar < xreal) then
exit;
end if;
end loop;
end procedure writefrc;
-- purpose: replace the "." with a "@", and "e" with "j" to get around
-- read ("6.") and read ("2e") issues.
function subdot (
constant format : STRING)
return STRING is
variable result : STRING (format'range);
begin
for i in format'range loop
if (format(i) = '.') then
result(i) := '@'; -- Because the parser reads 6.2 as REAL
elsif (format(i) = 'e') then
result(i) := 'j'; -- Because the parser read 2e as REAL
elsif (format(i) = 'E') then
result(i) := 'J'; -- Because the parser reads 2E as REAL
else
result(i) := format(i);
end if;
end loop;
return result;
end function subdot;
-- purpose: find a . in a STRING
function isdot (
constant format : STRING)
return BOOLEAN is
begin
for i in format'range loop
if (format(i) = '@') then
return true;
end if;
end loop;
return false;
end function isdot;
variable exp : INTEGER; -- integer version of baseexp
variable bvalue : REAL; -- base value
variable roundvar, tvar : REAL; -- Rounding values
variable frcptr : INTEGER; -- integer version of number
variable fwidth, dwidth : INTEGER; -- field width and decimal width
variable dash, dot : BOOLEAN := false;
variable cdes, ddes : CHARACTER := ' ';
variable L : LINE; -- line type
begin
-- Perform the same function that "printf" does
-- examples "%6.2f" "%-7e" "%g"
if not (format(format'left) = '%') then
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end if;
L := new STRING'(subdot(format));
read (L, ddes); -- toss the '%'
case L.all(1) is
when '-' => dash := true;
when '@' => dash := true; -- in FP, a "-" and a "." are the same
when 'f' => cdes := 'f';
when 'F' => cdes := 'F';
when 'g' => cdes := 'g';
when 'G' => cdes := 'G';
when 'j' => cdes := 'e'; -- parser reads 5e as real, thus we sub j
when 'J' => cdes := 'E';
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|'8'|'9' => null;
when others =>
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end case;
if (dash or (cdes /= ' ')) then
read (L, ddes); -- toss the next character
end if;
if (cdes = ' ') then
if (isdot(L.all)) then -- if you see a . two numbers
read (L, fwidth); -- read field width
read (L, ddes); -- toss the next character .
read (L, dwidth); -- read decimal width
else
read (L, fwidth); -- read field width
dwidth := 6; -- the default decimal width is 6
end if;
read (L, cdes);
if (cdes = 'j') then
cdes := 'e'; -- because 2e reads as "REAL".
elsif (cdes = 'J') then
cdes := 'E';
end if;
else
if (cdes = 'E' or cdes = 'e') then
fwidth := 10; -- default for e and E is %10.6e
else
fwidth := 0; -- default for f and g is %0.6f
end if;
dwidth := 6;
end if;
deallocate (L); -- reclame the pointer L.
-- assert (not debug) report "Format: " & format & " "
-- & INTEGER'image(fwidth) & "." & INTEGER'image(dwidth) & cdes
-- severity note;
if (not (cdes = 'f' or cdes = 'F' or cdes = 'g' or cdes = 'G'
or cdes = 'e' or cdes = 'E')) then
report "to_string: Illegal format """ & format & '"' severity error;
return "";
end if;
if (VALUE < 0.0) then
bvalue := -value;
write (L, '-');
else
bvalue := value;
end if;
case cdes is
when 'e' | 'E' => -- 7.000E+01
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half); -- Write a single digit.
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
writefrc (-- Write out the fraction
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
write (L, cdes); -- e or E
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then -- we need another "0".
write (L, czero);
end if;
write (L, exp);
when 'f' | 'F' => -- 70.0
exp := log10(bvalue);
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
if (exp < 0) then -- 0.X case
write (L, czero);
else -- loop because real'high > integer'high
while (exp >= 0) loop
frcptr := INTEGER(bvalue * (10.0**(-exp)) - half);
write (L, frcptr);
bvalue := bvalue - (REAL(frcptr) * (10.0**exp));
exp := exp-1;
end loop;
end if;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
when 'g' | 'G' => -- 70
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth)); -- small number
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
frcptr := INTEGER(bvalue-half);
tvar := bvalue-roundvar - REAL(frcptr); -- even smaller number
if (exp < dwidth)
and (tvar < roundvar and tvar > -roundvar) then
-- and ((bvalue-roundvar) = real(frcptr)) then
write (L, frcptr); -- Just a short integer, write it.
elsif (exp >= dwidth) or (exp < -4) then
-- in "e" format (modified)
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half);
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
if (bvalue > (10.0**(1-dwidth))) then
dwidth := dwidth - 1;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
if (cdes = 'G') then
write (L, 'E');
else
write (L, 'e');
end if;
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then
write (L, czero);
end if;
write (L, exp);
else
-- in "f" format (modified)
if (exp < 0) then
write (L, czero);
dwidth := maximum (dwidth, 4); -- if exp < -4 or > precision.
bvalue := bvalue - roundvar; -- recalculate rounding
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar;
else
write (L, frcptr); -- integer part (always small)
bvalue := bvalue - (REAL(frcptr));
dwidth := dwidth - exp - 1;
end if;
if (bvalue > roundvar) then
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
end if;
when others => return "";
end case;
-- You don't truncate real numbers.
-- if (dot) then -- truncate
-- if (L.all'length > fwidth) then
-- return justify (value => L.all (1 to fwidth),
-- justified => RIGHT,
-- field => fwidth);
-- else
-- return justify (value => L.all,
-- justified => RIGHT,
-- field => fwidth);
-- end if;
if (dash) then -- fill to fwidth
return justify (value => L.all,
justified => left,
field => fwidth);
else
return justify (value => L.all,
justified => right,
field => fwidth);
end if;
end function to_string;
end package body standard_additions;
|
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
package standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN;
function \?<\ (L, R : BOOLEAN) return BOOLEAN;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN;
function \?>\ (L, R : BOOLEAN) return BOOLEAN;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function \?=\ (L, R : BIT) return BIT;
function \?/=\ (L, R : BIT) return BIT;
function \?<\ (L, R : BIT) return BIT;
function \?<=\ (L, R : BIT) return BIT;
function \?>\ (L, R : BIT) return BIT;
function \?>=\ (L, R : BIT) return BIT;
function MINIMUM (L, R : BIT) return BIT;
function MAXIMUM (L, R : BIT) return BIT;
function \??\ (L : BIT) return BOOLEAN;
function RISING_EDGE (signal S : BIT) return BOOLEAN;
function FALLING_EDGE (signal S : BIT) return BOOLEAN;
function MINIMUM (L, R : CHARACTER) return CHARACTER;
function MAXIMUM (L, R : CHARACTER) return CHARACTER;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MINIMUM (L, R : INTEGER) return INTEGER;
function MAXIMUM (L, R : INTEGER) return INTEGER;
function MINIMUM (L, R : REAL) return REAL;
function MAXIMUM (L, R : REAL) return REAL;
function "mod" (L, R : TIME) return TIME;
function "rem" (L, R : TIME) return TIME;
function MINIMUM (L, R : TIME) return TIME;
function MAXIMUM (L, R : TIME) return TIME;
function MINIMUM (L, R : STRING) return STRING;
function MAXIMUM (L, R : STRING) return STRING;
function MINIMUM (L : STRING) return CHARACTER;
function MAXIMUM (L : STRING) return CHARACTER;
type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
-- function "=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN_VECTOR) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN) -- return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function and_reduce (L : BIT_VECTOR) return BIT;
function or_reduce (L : BIT_VECTOR) return BIT;
function nand_reduce (L : BIT_VECTOR) return BIT;
function nor_reduce (L : BIT_VECTOR) return BIT;
function xor_reduce (L : BIT_VECTOR) return BIT;
function xnor_reduce (L : BIT_VECTOR) return BIT;
function \?=\ (L, R : BIT_VECTOR) return BIT;
function \?/=\ (L, R : BIT_VECTOR) return BIT;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MINIMUM (L : BIT_VECTOR) return BIT;
function MAXIMUM (L : BIT_VECTOR) return BIT;
function TO_STRING (VALUE : BIT_VECTOR) return STRING;
alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER;
type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN;
function "/=" (L, R : REAL_VECTOR) return BOOLEAN;
function "<" (L, R : REAL_VECTOR) return BOOLEAN;
function "<=" (L, R : REAL_VECTOR) return BOOLEAN;
function ">" (L, R : REAL_VECTOR) return BOOLEAN;
function ">=" (L, R : REAL_VECTOR) return BOOLEAN;
-- function "&" (L : REAL_VECTOR; R : REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L : REAL_VECTOR; R : REAL) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MINIMUM (L : REAL_VECTOR) return REAL;
function MAXIMUM (L : REAL_VECTOR) return REAL;
type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN;
function "/=" (L, R : TIME_VECTOR) return BOOLEAN;
function "<" (L, R : TIME_VECTOR) return BOOLEAN;
function "<=" (L, R : TIME_VECTOR) return BOOLEAN;
function ">" (L, R : TIME_VECTOR) return BOOLEAN;
function ">=" (L, R : TIME_VECTOR) return BOOLEAN;
-- function "&" (L : TIME_VECTOR; R : TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L : TIME_VECTOR; R : TIME) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MINIMUM (L : TIME_VECTOR) return TIME;
function MAXIMUM (L : TIME_VECTOR) return TIME;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
-- predefined TO_STRING operations on scalar types
function TO_STRING (VALUE : BOOLEAN) return STRING;
function TO_STRING (VALUE : BIT) return STRING;
function TO_STRING (VALUE : CHARACTER) return STRING;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING;
function TO_STRING (VALUE : INTEGER) return STRING;
function TO_STRING (VALUE : REAL) return STRING;
function TO_STRING (VALUE : TIME) return STRING;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING;
-- predefined overloaded TO_STRING operations
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING;
end package standard_additions;
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
use std.textio.all;
package body standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
function \?<\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L < R;
end function \?<\;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L <= R;
end function \?<=\;
function \?>\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L > R;
end function \?>\;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L >= R;
end function \?>=\;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BOOLEAN) return STRING is
begin
return BOOLEAN'image(VALUE);
end function TO_STRING;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = true) and (s'last_value = false));
end function rising_edge;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = false) and (s'last_value = true));
end function falling_edge;
function \?=\ (L, R : BIT) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function \?<\ (L, R : BIT) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function \?<\;
function \?<=\ (L, R : BIT) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function \?<=\;
function \?>\ (L, R : BIT) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function \?>\;
function \?>=\ (L, R : BIT) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function \?>=\;
function MINIMUM (L, R : BIT) return BIT is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT) return BIT is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BIT) return STRING is
begin
if VALUE = '1' then
return "1";
else
return "0";
end if;
end function TO_STRING;
function \??\ (L : BIT) return BOOLEAN is
begin
return L = '1';
end function \??\;
function RISING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '1') and (s'last_value = '0'));
end function rising_edge;
function FALLING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '0') and (s'last_value = '1'));
end function falling_edge;
function MINIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : CHARACTER) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := VALUE;
return result;
end function TO_STRING;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING is
begin
return SEVERITY_LEVEL'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : INTEGER) return STRING is
begin
return INTEGER'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : REAL) return REAL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL) return REAL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : REAL) return STRING is
begin
return REAL'image (VALUE);
end function TO_STRING;
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING is
begin
return to_string (VALUE, "%1." & INTEGER'image(DIGITS) & "f");
end function TO_STRING;
function "mod" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint mod rint) * 1.0 ns;
end function "mod";
function "rem" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint rem rint) * 1.0 ns;
end function "rem";
function MINIMUM (L, R : TIME) return TIME is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME) return TIME is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : TIME) return STRING is
begin
return TIME'image (VALUE);
end function TO_STRING;
function MINIMUM (L, R : STRING) return STRING is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : STRING) return STRING is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) and rv(i));
end loop;
end if;
return result;
end function "and";
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) or rv(i));
end loop;
end if;
return result;
end function "or";
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nand rv(i));
end loop;
end if;
return result;
end function "nand";
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nor rv(i));
end loop;
end if;
return result;
end function "nor";
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xor rv(i));
end loop;
end if;
return result;
end function "xor";
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xnor rv(i));
end loop;
end if;
return result;
end function "xnor";
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not (lv(i));
end loop;
return result;
end function "not";
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nand r;
end loop;
return result;
end function "nand";
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nand rv(i);
end loop;
return result;
end function "nand";
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nor r;
end loop;
return result;
end function "nor";
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nor rv(i);
end loop;
return result;
end function "nor";
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xnor r;
end loop;
return result;
end function "xnor";
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xnor rv(i);
end loop;
return result;
end function "xnor";
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'high);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sla";
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'low);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sra";
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-- function "=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN) return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return not result;
end function "nand";
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return not result;
end function "nand";
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return not result;
end function "nor";
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return not result;
end function "nor";
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return not result;
end function "xnor";
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return not result;
end function "xnor";
function and_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function \?=\ (L, R : BIT_VECTOR) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT_VECTOR) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function TO_STRING (VALUE : BIT_VECTOR) return STRING is
alias ivalue : BIT_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return "";
else
for i in ivalue'range loop
if iValue(i) = '0' then
result(i) := '0';
else
result(i) := '1';
end if;
end loop;
return result;
end if;
end function to_string;
-- alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
-- alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : BIT_VECTOR(0 to 2);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := ivalue(3*i to 3*i+2);
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
end case;
end loop;
return result;
end function to_ostring;
-- alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : BIT_VECTOR(0 to 3);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := ivalue(4*i to 4*i+3);
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
end case;
end loop;
return result;
end function to_hstring;
-- alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
-- type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: INTEGER_VECTOR; R: INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L: INTEGER_VECTOR; R: INTEGER) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: REAL_VECTOR; R: REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L: REAL_VECTOR; R: REAL) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined implicit operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: TIME_VECTOR; R: TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L: TIME_VECTOR; R: TIME) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING is
begin
return FILE_OPEN_KIND'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING is
begin
return FILE_OPEN_STATUS'image(VALUE);
end function TO_STRING;
-- USED INTERNALLY!
function justify (
value : in STRING;
justified : in SIDE := right;
field : in width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING is
variable L : LINE; -- pointer
begin
deallocate (L);
write (L => L,
VALUE => VALUE,
UNIT => UNIT);
return L.all;
end function to_string;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING is
constant czero : CHARACTER := '0'; -- zero
constant half : REAL := 0.4999999999; -- almost 0.5
-- Log10 funciton
function log10 (arg : REAL) return INTEGER is
variable i : INTEGER := 1;
begin
if ((arg = 0.0)) then
return 0;
elsif arg >= 1.0 then
while arg >= 10.0**i loop
i := i + 1;
end loop;
return (i-1);
else
while arg < 10.0**i loop
i := i - 1;
end loop;
return i;
end if;
end function log10;
-- purpose: writes a fractional real number into a line
procedure writefrc (
variable L : inout LINE; -- LINE
variable cdes : in CHARACTER;
variable precision : in INTEGER; -- number of decimal places
variable value : in REAL) is -- real value
variable rvar : REAL; -- temp variable
variable xint : INTEGER;
variable xreal : REAL;
begin
xreal := (10.0**(-precision));
write (L, '.');
rvar := value;
for i in 1 to precision loop
rvar := rvar * 10.0;
xint := INTEGER(rvar-0.49999999999); -- round
write (L, xint);
rvar := rvar - REAL(xint);
xreal := xreal * 10.0;
if (cdes = 'g') and (rvar < xreal) then
exit;
end if;
end loop;
end procedure writefrc;
-- purpose: replace the "." with a "@", and "e" with "j" to get around
-- read ("6.") and read ("2e") issues.
function subdot (
constant format : STRING)
return STRING is
variable result : STRING (format'range);
begin
for i in format'range loop
if (format(i) = '.') then
result(i) := '@'; -- Because the parser reads 6.2 as REAL
elsif (format(i) = 'e') then
result(i) := 'j'; -- Because the parser read 2e as REAL
elsif (format(i) = 'E') then
result(i) := 'J'; -- Because the parser reads 2E as REAL
else
result(i) := format(i);
end if;
end loop;
return result;
end function subdot;
-- purpose: find a . in a STRING
function isdot (
constant format : STRING)
return BOOLEAN is
begin
for i in format'range loop
if (format(i) = '@') then
return true;
end if;
end loop;
return false;
end function isdot;
variable exp : INTEGER; -- integer version of baseexp
variable bvalue : REAL; -- base value
variable roundvar, tvar : REAL; -- Rounding values
variable frcptr : INTEGER; -- integer version of number
variable fwidth, dwidth : INTEGER; -- field width and decimal width
variable dash, dot : BOOLEAN := false;
variable cdes, ddes : CHARACTER := ' ';
variable L : LINE; -- line type
begin
-- Perform the same function that "printf" does
-- examples "%6.2f" "%-7e" "%g"
if not (format(format'left) = '%') then
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end if;
L := new STRING'(subdot(format));
read (L, ddes); -- toss the '%'
case L.all(1) is
when '-' => dash := true;
when '@' => dash := true; -- in FP, a "-" and a "." are the same
when 'f' => cdes := 'f';
when 'F' => cdes := 'F';
when 'g' => cdes := 'g';
when 'G' => cdes := 'G';
when 'j' => cdes := 'e'; -- parser reads 5e as real, thus we sub j
when 'J' => cdes := 'E';
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|'8'|'9' => null;
when others =>
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end case;
if (dash or (cdes /= ' ')) then
read (L, ddes); -- toss the next character
end if;
if (cdes = ' ') then
if (isdot(L.all)) then -- if you see a . two numbers
read (L, fwidth); -- read field width
read (L, ddes); -- toss the next character .
read (L, dwidth); -- read decimal width
else
read (L, fwidth); -- read field width
dwidth := 6; -- the default decimal width is 6
end if;
read (L, cdes);
if (cdes = 'j') then
cdes := 'e'; -- because 2e reads as "REAL".
elsif (cdes = 'J') then
cdes := 'E';
end if;
else
if (cdes = 'E' or cdes = 'e') then
fwidth := 10; -- default for e and E is %10.6e
else
fwidth := 0; -- default for f and g is %0.6f
end if;
dwidth := 6;
end if;
deallocate (L); -- reclame the pointer L.
-- assert (not debug) report "Format: " & format & " "
-- & INTEGER'image(fwidth) & "." & INTEGER'image(dwidth) & cdes
-- severity note;
if (not (cdes = 'f' or cdes = 'F' or cdes = 'g' or cdes = 'G'
or cdes = 'e' or cdes = 'E')) then
report "to_string: Illegal format """ & format & '"' severity error;
return "";
end if;
if (VALUE < 0.0) then
bvalue := -value;
write (L, '-');
else
bvalue := value;
end if;
case cdes is
when 'e' | 'E' => -- 7.000E+01
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half); -- Write a single digit.
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
writefrc (-- Write out the fraction
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
write (L, cdes); -- e or E
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then -- we need another "0".
write (L, czero);
end if;
write (L, exp);
when 'f' | 'F' => -- 70.0
exp := log10(bvalue);
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
if (exp < 0) then -- 0.X case
write (L, czero);
else -- loop because real'high > integer'high
while (exp >= 0) loop
frcptr := INTEGER(bvalue * (10.0**(-exp)) - half);
write (L, frcptr);
bvalue := bvalue - (REAL(frcptr) * (10.0**exp));
exp := exp-1;
end loop;
end if;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
when 'g' | 'G' => -- 70
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth)); -- small number
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
frcptr := INTEGER(bvalue-half);
tvar := bvalue-roundvar - REAL(frcptr); -- even smaller number
if (exp < dwidth)
and (tvar < roundvar and tvar > -roundvar) then
-- and ((bvalue-roundvar) = real(frcptr)) then
write (L, frcptr); -- Just a short integer, write it.
elsif (exp >= dwidth) or (exp < -4) then
-- in "e" format (modified)
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half);
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
if (bvalue > (10.0**(1-dwidth))) then
dwidth := dwidth - 1;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
if (cdes = 'G') then
write (L, 'E');
else
write (L, 'e');
end if;
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then
write (L, czero);
end if;
write (L, exp);
else
-- in "f" format (modified)
if (exp < 0) then
write (L, czero);
dwidth := maximum (dwidth, 4); -- if exp < -4 or > precision.
bvalue := bvalue - roundvar; -- recalculate rounding
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar;
else
write (L, frcptr); -- integer part (always small)
bvalue := bvalue - (REAL(frcptr));
dwidth := dwidth - exp - 1;
end if;
if (bvalue > roundvar) then
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
end if;
when others => return "";
end case;
-- You don't truncate real numbers.
-- if (dot) then -- truncate
-- if (L.all'length > fwidth) then
-- return justify (value => L.all (1 to fwidth),
-- justified => RIGHT,
-- field => fwidth);
-- else
-- return justify (value => L.all,
-- justified => RIGHT,
-- field => fwidth);
-- end if;
if (dash) then -- fill to fwidth
return justify (value => L.all,
justified => left,
field => fwidth);
else
return justify (value => L.all,
justified => right,
field => fwidth);
end if;
end function to_string;
end package body standard_additions;
|
library ieee;
use ieee.std_logic_1164.all;
library virtual_button_lib;
use virtual_button_lib.ws2812_data.all;
package ws2812_constant_colours is
constant ws2812_clear : ws2812_t := lighten_ws2812(ws2812_t'(000, 000, 000), 0.05);
constant ws2812_green : ws2812_t := lighten_ws2812(ws2812_t'(000, 128, 000), 0.05);
constant ws2812_red : ws2812_t := lighten_ws2812(ws2812_t'(128, 000, 000), 0.05);
constant ws2812_blue : ws2812_t := lighten_ws2812(ws2812_t'(000, 000, 128), 0.05);
constant ws2812_purple : ws2812_t := lighten_ws2812(ws2812_t'(128, 000, 128), 0.05);
constant ws2812_pink : ws2812_t := lighten_ws2812(ws2812_t'(255, 192, 203), 0.05);
constant ws2812_yellow : ws2812_t := lighten_ws2812(ws2812_t'(255, 255, 000), 0.05);
end;
|
architecture RTL of FIFO is
constant c_width : integer := 16;
constant C_DEPTH : integer := 512;
constant C_word : integer := 1024;
begin
end architecture RTL;
|
-----------------------------------------------------------------------------
-- LEON3 Xilinx KC705 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.l2cache.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(3 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_txclk : out std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
sfp_clock_mux : out std_logic_vector(1 downto 0);
sdcard_spi_miso : in std_logic;
sdcard_spi_mosi : out std_logic;
sdcard_spi_cs_b : out std_logic;
sdcard_spi_clk : out std_logic
);
end;
architecture rtl of leon3mp is
component ahb2mig_7series
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component ;
component ddr_dummy
port (
ddr_dq : inout std_logic_vector(63 downto 0);
ddr_dqs : inout std_logic_vector(7 downto 0);
ddr_dqs_n : inout std_logic_vector(7 downto 0);
ddr_addr : out std_logic_vector(13 downto 0);
ddr_ba : out std_logic_vector(2 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_ck_p : out std_logic_vector(0 downto 0);
ddr_ck_n : out std_logic_vector(0 downto 0);
ddr_cke : out std_logic_vector(0 downto 0);
ddr_cs_n : out std_logic_vector(0 downto 0);
ddr_dm : out std_logic_vector(7 downto 0);
ddr_odt : out std_logic_vector(0 downto 0)
);
end component ;
-- pragma translate_off
component ahbram_sim
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
fname : string := "ram.dat"
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component ;
-- pragma translate_on
component IBUFDS_GTE2
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component IDELAYCTRL
port (
RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic
);
end component;
component IODELAYE1
generic (
DELAY_SRC : string := "I";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0
);
port (
CNTVALUEOUT : out std_logic_vector(4 downto 0);
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CINVCTRL : in std_ulogic;
CLKIN : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
----- component STARTUPE2 -----
component STARTUPE2
generic (
PROG_USR : string := "FALSE";
SIM_CCLK_FREQ : real := 0.0
);
port (
CFGCLK : out std_ulogic;
CFGMCLK : out std_ulogic;
EOS : out std_ulogic;
PREQ : out std_ulogic;
CLK : in std_ulogic;
GSR : in std_ulogic;
GTS : in std_ulogic;
KEYCLEARB : in std_ulogic;
PACK : in std_ulogic;
USRCCLKO : in std_ulogic;
USRCCLKTS : in std_ulogic;
USRDONEO : in std_ulogic;
USRDONETS : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
--constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbm : integer := 16;
constant maxahbs : integer := 16;
constant maxapbs : integer := CFG_IRQ3_ENABLE+CFG_GPT_ENABLE+CFG_GRGPIO_ENABLE+CFG_AHBSTAT+CFG_AHBSTAT;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal mem_ahbsi : ahb_slv_in_type;
signal mem_ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal mem_ahbmi : ahb_mst_in_type;
signal mem_ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal ui_clk : std_ulogic;
signal clkm : std_ulogic := '0';
signal rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii : eth_in_type;
signal gmiio : eth_out_type;
signal rgmiii,rgmiii_buf : eth_in_type;
signal rgmiio : eth_out_type;
signal sgmiii : eth_sgmii_in_type;
signal sgmiio : eth_sgmii_out_type;
signal sgmiirst : std_logic;
signal ethernet_phy_int : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gtx_clk,gtx_clk_nobuf,gtx_clk90 : std_ulogic;
signal rstgtxn : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ : integer := 200000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal dsurx_int : std_logic;
signal dsutx_int : std_logic;
signal dsuctsn_int : std_logic;
signal dsurtsn_int : std_logic;
signal dsu_sel : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal io_ref : std_logic;
signal clkref : std_logic;
signal migrstn : std_logic;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_gen0 : if (CFG_MIG_7SERIES = 0) generate
clk_pad_ds : clkpad_ds generic map (tech => padtech, level => sstl, voltage => x15v) port map (clk200p, clk200n, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, open, open);
end generate;
reset_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1, syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_7SERIES = 1 else cgo.clklock;
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, '1', migrstn, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(1), dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui_break_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (button(0), dsui.break);
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.extclk <= '0';
end generate;
nouah : if CFG_AHB_UART = 0 generate
apbo(7) <= apb_none;
duo.txd <= '0';
duo.rtsn <= '0';
dui.extclk <= '0';
end generate;
sw4_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(3), '0', '1', dsu_sel);
dsutx_int <= duo.txd when dsu_sel = '1' else u1o.txd;
dui.rxd <= dsurx_int when dsu_sel = '1' else '1';
u1i.rxd <= dsurx_int when dsu_sel = '0' else '1';
dsurtsn_int <= duo.rtsn when dsu_sel = '1' else u1o.rtsn;
dui.ctsn <= dsuctsn_int when dsu_sel = '1' else '1';
u1i.ctsn <= dsuctsn_int when dsu_sel = '0' else '1';
dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, dsurx_int);
dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, dsutx_int);
dsuctsn_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsuctsn, dsuctsn_int);
dsurtsn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurtsn, dsurtsn_int);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
--nojtag : if CFG_AHB_JTAG = 0 generate apbo(CFG_NCPU+CFG_AHB_UART) <= apb_none; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 0, hirq => 1, faddr => 16#100#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo);
miso_pad : inpad generic map (tech => padtech)
port map (spi_miso, spmi.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
-- To output SPI clock use Xilinx STARTUPE2 primitive
--sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spmo.sck);
STARTUPE2_inst : STARTUPE2
generic map (
PROG_USR => "FALSE",
SIM_CCLK_FREQ => 10.0
)
port map (
CFGCLK => open ,
CFGMCLK => open ,
EOS => open ,
PREQ => open ,
CLK => '0',
GSR => '0',
GTS => '0',
KEYCLEARB => '0',
PACK => '0',
USRCCLKO => spmo.sck,
USRCCLKTS => '0',
USRDONEO => '1',
USRDONETS => '1'
);
end generate;
nospimc: if CFG_SPIMCTRL = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (spi_miso, spmi.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, '1');
--sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, '0');
end generate;
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
l2cdis : if CFG_L2_EN = 0 generate
mig_gen : if (CFG_MIG_7SERIES = 1) generate
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_7series generic map(
hindex => 4, haddr => 16#400#, hmask => 16#C00#,
pindex => 4, paddr => 4,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => rstraw,
clk_amba => clkm,
sys_clk_p => clk200p,
sys_clk_n => clk200n,
clk_ref_i => clkref,
ui_clk => clkm,
ui_clk_sync_rst => open
);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
-- pragma translate_off
mig_ahbram : ahbram_sim
generic map (
hindex => 4,
haddr => 16#400#,
hmask => 16#C00#,
tech => 0,
kbytes => 1000,
pipe => 0,
maccsz => AHBDW,
fname => "ram.srec"
)
port map(
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(4)
);
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
ddr3_addr <= (others => '0');
ddr3_ba <= (others => '0');
ddr3_ras_n <= '0';
ddr3_cas_n <= '0';
ddr3_we_n <= '0';
ddr3_reset_n <= '1';
ddr3_ck_p <= (others => '0');
ddr3_ck_n <= (others => '0');
ddr3_cke <= (others => '0');
ddr3_cs_n <= (others => '0');
ddr3_dm <= (others => '0');
ddr3_odt <= (others => '0');
--calib_done : out std_logic;
calib_done <= '1';
--ui_clk : out std_logic;
clkm <= not clkm after 5.0 ns;
--ui_clk_sync_rst : out std_logic
-- n/a
-- pragma translate_on
end generate gen_mig_model; end generate;
no_mig_gen : if (CFG_MIG_7SERIES = 0) generate
ahbram0 : ahbram
generic map (hindex => 4, haddr => 16#400#, tech => CFG_MEMTECH, kbytes => 128)
port map ( rstn, clkm, ahbsi, ahbso(4));
ddrdummy0 : ddr_dummy
port map (
ddr_dq => ddr3_dq,
ddr_dqs => ddr3_dqs_p,
ddr_dqs_n => ddr3_dqs_n,
ddr_addr => ddr3_addr,
ddr_ba => ddr3_ba,
ddr_ras_n => ddr3_ras_n,
ddr_cas_n => ddr3_cas_n,
ddr_we_n => ddr3_we_n,
ddr_reset_n => ddr3_reset_n,
ddr_ck_p => ddr3_ck_p,
ddr_ck_n => ddr3_ck_n,
ddr_cke => ddr3_cke,
ddr_cs_n => ddr3_cs_n,
ddr_dm => ddr3_dm,
ddr_odt => ddr3_odt
);
calib_done <= '1';
end generate no_mig_gen;
end generate l2cdis;
-----------------------------------------------------------------------------
-- L2 cache covering DDR3 SDRAM memory controller
-----------------------------------------------------------------------------
l2cen : if CFG_L2_EN /= 0 generate
l2c0 : l2c
generic map(hslvidx => 4, hmstidx => 0, cen => CFG_L2_PEN,
haddr => 16#400#, hmask => 16#c00#, ioaddr => 16#FF0#,
cached => CFG_L2_MAP, repl => CFG_L2_RAN, ways => CFG_L2_WAYS,
linesize => CFG_L2_LSZ, waysize => CFG_L2_SIZE,
memtech => memtech, bbuswidth => AHBDW,
bioaddr => 16#FFE#, biomask => 16#fff#,
sbus => 0, mbus => 1, arch => CFG_L2_SHARE,
ft => CFG_L2_EDAC)
port map(rst => rstn, clk => clkm, ahbsi => ahbsi, ahbso => ahbso(4),
ahbmi => mem_ahbmi, ahbmo => mem_ahbmo(0), ahbsov => mem_ahbso);
memahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => 16#FFE#,
ioen => 1, nahbm => 1, nahbs => 1)
port map (rstn, clkm, mem_ahbmi, mem_ahbmo, mem_ahbsi, mem_ahbso);
--mig_gen : if (CFG_MIG_7SERIES = 1) generate
-- gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_7series
generic map(hindex => 0, haddr => 16#400#, hmask => 16#C00#,
pindex => 4, paddr => 4,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(ddr3_dq => ddr3_dq, ddr3_dqs_p => ddr3_dqs_p, ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n, ddr3_we_n => ddr3_we_n, ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p, ddr3_ck_n => ddr3_ck_n, ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n, ddr3_dm => ddr3_dm, ddr3_odt => ddr3_odt,
ahbsi => mem_ahbsi, ahbso => mem_ahbso(0), apbi => apbi, apbo => apbo(4),
calib_done => calib_done, rst_n_syn => migrstn, rst_n_async => rstraw,
clk_amba => clkm, sys_clk_p => clk200p, sys_clk_n => clk200n, clk_ref_i => clkref,
ui_clk => clkm, ui_clk_sync_rst => open);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open);
-- end generate gen_mig;
--end generate mig_gen;
end generate l2cen;
led2_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(2), calib_done);
led3_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(3), lock);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 16#C00#, pmask => 16#C00#, pirq => 3, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G, ramdebug => 0, gmiimode => 1)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
-----------------------------------------------------------------------------
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
-- All IDELAYs in Fixed Tap Delay mode and the IDELAYCTRL primitives have
-- to be LOC'ed in the UCF file.
-----------------------------------------------------------------------------
dlyctrl0 : IDELAYCTRL port map (
RDY => OPEN,
REFCLK => io_ref,
RST => idelayctrl_reset
);
delay_rgmii_rx_ctl0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
ODATAIN => '0',
DATAOUT => rgmiii.rx_dv,
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
ODATAIN => '0',
DATAOUT => rgmiii.rxd(i),
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
end generate;
-- Generate a synchron delayed reset for Xilinx IO delay
rst1 : rstgen
generic map (acthigh => 1)
port map (rst, io_ref, lock, rstgtxn, OPEN);
process (io_ref,rstgtxn)
begin
if (rstgtxn = '0') then
idelay_reset_cnt <= (others => '0');
idelayctrl_reset <= '1';
elsif rising_edge(io_ref) then
if (idelay_reset_cnt > "1110") then
idelay_reset_cnt <= (others => '1');
idelayctrl_reset <= '0';
else
idelay_reset_cnt <= idelay_reset_cnt + 1;
idelayctrl_reset <= '1';
end if;
end if;
end process;
-- RGMII Interface
rgmii0 : rgmii generic map (pindex => 11, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 0, abits => 8, no_clk_mux => 1,
pirq => 11, use90degtxclk => 1)
port map (rstn, ethi, etho, rgmiii, rgmiio, clkm, rstn, apbi, apbo(11));
egtxc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txclk, rgmiio.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v, arch => 4)
port map (phy_rxclk, rgmiii.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 4)
port map (phy_rxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_rxctl_rxdv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1, width => 4)
port map (phy_txd, rgmiio.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txctl_txen, rgmiio.tx_en);
emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdc, rgmiio.mdc);
rgmiii.mdint <= '0'; -- No interrupt on Marvell 88E1116R PHY
erst_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_reset, rstraw);
sfp_clock_mux_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 2)
port map (sfp_clock_mux, "00");
-- GTX Clock
rgmiii.gtx_clk <= gtx_clk;
-- 125MHz input clock
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => gtrefclk_p,
IB => gtrefclk_n,
CEB => '0',
O => gtx_clk_nobuf,
ODIV2 => open
);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen_gtrefclk : clkgen
generic map (clktech, 8, 8, 0, 0, 0, 0, 0, 125000)
port map (gtx_clk_nobuf, gtx_clk_nobuf, gtx_clk, rgmiii.tx_clk_90, io_ref, open, open, cgi2, cgo2, open, open, open);
end generate;
noeth0 : if CFG_GRETH = 0 generate
-- TODO:
end generate;
----------------------------------------------------------------------
--- I2C Controller --------------------------------------------------
----------------------------------------------------------------------
--i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 4, filter => 9)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
--end generate i2cm;
----------------------------------------------------------------------
--- SPI Controller --------------------------------------------------
----------------------------------------------------------------------
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 12, paddr => 12, pmask => 16#fff#, pirq => 12,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(12), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (sdcard_spi_miso, spii.miso);
mosi_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (sdcard_spi_mosi, spio.mosi);
sck_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (sdcard_spi_clk, spio.sck);
slvsel_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (sdcard_spi_cs_b, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (level => cmos, voltage => x25v,tech => padtech)
port map (sdcard_spi_miso, spii.miso);
mosi_pad : outpad generic map (level => cmos, voltage => x25v,tech => padtech)
port map (sdcard_spi_mosi, '1');
sck_pad : outpad generic map (level => cmos, voltage => x25v,tech => padtech)
port map (sdcard_spi_clk, '0');
slvsel_pad : outpad generic map (level => cmos, voltage => x25v,tech => padtech)
port map (sdcard_spi_cs_b, '1');
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16, debug => 2)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 2 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 3 to 5 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (button(i-2), gpioi.din(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 7, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 3, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
-- pragma translate_on
test1_gen : if (testahb = false) generate
ahbram0 : ahbram generic map (hindex => 3, haddr => 16#200#,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(3));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx AC701 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
Library ieee;
Use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
ENTITY Execution IS
port(
Clk,Rst,enable : in std_logic;
OpCode : in std_logic_vector(4 downto 0);
R1_Reg1,R2_Reg1,ROut_Alu1,ROut_Mem1: in std_logic_vector(2 downto 0);
R1_dec: in std_logic_vector(15 downto 0);
R2_dec: in std_logic_vector(15 downto 0);
n : in std_logic_vector (3 downto 0);
Alu_Output_exe , Meomry_Output_exe: in std_logic_vector(15 downto 0);
Execution_Output: out std_logic_vector(15 downto 0);
Z_F: out std_logic;
NF_F: out std_logic;
V_F: out std_logic;
C_F: out std_logic
);
END Execution;
Architecture archi of Execution is
component ALU is
port (
Clk,Rst,enable : in std_logic;
OpCode : in std_logic_vector(4 downto 0);
R1: in std_logic_vector(15 downto 0);
R2: in std_logic_vector(15 downto 0);
Output: out std_logic_vector(15 downto 0);
n : in std_logic_vector (3 downto 0);
Z: out std_logic;
NF: out std_logic;
v: out std_logic;
C: out std_logic
);
end component;
component Forwarding IS
port(
R1_Reg,R2_Reg,ROut_Alu,ROut_Mem: in std_logic_vector(2 downto 0);
R1,R2: out std_logic_vector(15 downto 0);
R1_Mux,R2_Mux : out std_logic;
Alu_Output , Meomry_Output: in std_logic_vector(15 downto 0)
--Alu_Output1 , Meomry_Output1: out std_logic_vector(15 downto 0);
--WriteBackSignal : in std_logic
);
END component;
signal R1_Forward_out_signal,R2_Forward_out_signal : std_logic_vector(15 downto 0);
signal R1_signal,R2_signal : std_logic_vector(15 downto 0);
signal R1_Mux_signal,R2_Mux_signal : std_logic;
signal Execution_Output_signal : std_logic_vector(15 downto 0); --ALU output
signal Z_signal,NF_signal,V_signal,C_signal : std_logic; --flags
begin
forward_map: Forwarding port map(R1_Reg1,R2_Reg1,ROut_Alu1,ROut_Mem1,R1_Forward_out_signal,R2_Forward_out_signal,R1_Mux_signal,R2_Mux_signal,Alu_Output_exe , Meomry_Output_exe);
Alu_map: ALU port map(Clk,Rst,enable,OpCode,R1_signal,R2_signal,Execution_Output_signal,n, Z_signal,NF_signal,V_signal,C_signal);
R1_signal <= R1_Forward_out_signal when R1_Mux_signal = '1' else
R1_dec when R1_Mux_signal = '0';
R2_signal <= R2_Forward_out_signal when R2_Mux_signal = '1' else
R2_dec when R2_Mux_signal = '0';
Execution_Output <= Execution_Output_signal;
Z_F <= Z_signal;
NF_F <= NF_signal;
V_F <= V_signal;
C_F <= C_signal;
end archi; |
set vhdlList {
|
set vhdlList {
|
------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- Massarrah Tannous --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: RegF
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Presenation Code: Dr.Fortier(c)
--
-- Notes:
-- Clocked on RISING EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the rising
-- clock cycle.
--
-- Additional Comments:
-- The register latches it's data on the RISING edge
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
ENTITY Reg4R IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END Reg4R;
ARCHITECTURE Behavior OF Reg4R IS
BEGIN
PROCESS(Resetn, Clock)
BEGIN
IF Resetn = '0' THEN
OUTPUT <= (OTHERS => '0');
ELSIF ENABLE = '1' THEN
IF Clock'EVENT AND Clock = '1' THEN
OUTPUT <= INPUT;
END IF;
END IF;
END PROCESS;
END Behavior;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;
use work.picpkg.all;
entity memory_instruction is
Generic (
CONTENTS : string := "scripts/instructions.mif"
);
Port ( clk : in STD_LOGIC;
a1 : in STD_LOGIC_VECTOR (12 downto 0);
d1 : out STD_LOGIC_VECTOR (13 downto 0);
wd : in STD_LOGIC_VECTOR (13 downto 0);
we : in STD_LOGIC);
end memory_instruction;
architecture Behavioral of memory_instruction is
impure function init_mem(mif_file_name : in string) return mem_type14 is
file mif_file : text open read_mode is mif_file_name;
variable mif_line : line;
variable temp_bv : bit_vector(13 downto 0);
variable temp_mem : mem_type14;
variable i : integer := 0;
begin
for j in 0 to mem_type14'length-1 loop
if not endfile(mif_file) then
readline(mif_file, mif_line);
-- Xilinx ISE implementation fix, uncomment to enable implementation and lose the last instruction
--if not endfile(mif_file) then
read(mif_line, temp_bv);
temp_mem(j) := to_stdlogicvector(temp_bv);
--end if;
else
temp_mem(j) := (others => '0');
end if;
end loop;
return temp_mem;
end function;
signal mem : mem_type14 := init_mem(CONTENTS);
begin
process(clk, we, a1, mem)
begin
if rising_edge(clk) then
if we = '1' then
--Write
mem(to_integer(unsigned(a1(INST_MEM_SIZE - 1 downto 0)))) <= wd;
end if;
-- Set output
d1 <= mem(to_integer(unsigned(a1(INST_MEM_SIZE - 1 downto 0))));
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2017 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file signed_multiplier.vhd when simulating
-- the core, signed_multiplier. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY signed_multiplier IS
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END signed_multiplier;
ARCHITECTURE signed_multiplier_a OF signed_multiplier IS
-- synthesis translate_off
COMPONENT wrapped_signed_multiplier
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_signed_multiplier USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 32,
c_b_type => 0,
c_b_value => "10000001",
c_b_width => 32,
c_ccm_imp => 0,
c_ce_overrides_sclr => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_zero_detect => 0,
c_latency => 8,
c_model_type => 0,
c_mult_type => 1,
c_optimize_goal => 1,
c_out_high => 63,
c_out_low => 0,
c_round_output => 0,
c_round_pt => 0,
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_signed_multiplier
PORT MAP (
clk => clk,
a => a,
b => b,
p => p
);
-- synthesis translate_on
END signed_multiplier_a;
|
entity delay2 is
end entity;
architecture test of delay2 is
signal clk : bit;
begin
clock_p: process is
begin
if now < 1 us then
clk <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
else
wait;
end if;
end process;
check_p: process is
variable now_ns : integer;
begin
if now < 1 us then
wait for 0 ns;
now_ns := integer(now / ns);
case now_ns mod 10 is
when 0 =>
assert clk = '0';
when 5 =>
assert clk = '1';
when others =>
report "clk changed at unexpected time";
end case;
wait for 5 ns;
else
wait;
end if;
end process;
end architecture;
|
entity delay2 is
end entity;
architecture test of delay2 is
signal clk : bit;
begin
clock_p: process is
begin
if now < 1 us then
clk <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
else
wait;
end if;
end process;
check_p: process is
variable now_ns : integer;
begin
if now < 1 us then
wait for 0 ns;
now_ns := integer(now / ns);
case now_ns mod 10 is
when 0 =>
assert clk = '0';
when 5 =>
assert clk = '1';
when others =>
report "clk changed at unexpected time";
end case;
wait for 5 ns;
else
wait;
end if;
end process;
end architecture;
|
entity delay2 is
end entity;
architecture test of delay2 is
signal clk : bit;
begin
clock_p: process is
begin
if now < 1 us then
clk <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
else
wait;
end if;
end process;
check_p: process is
variable now_ns : integer;
begin
if now < 1 us then
wait for 0 ns;
now_ns := integer(now / ns);
case now_ns mod 10 is
when 0 =>
assert clk = '0';
when 5 =>
assert clk = '1';
when others =>
report "clk changed at unexpected time";
end case;
wait for 5 ns;
else
wait;
end if;
end process;
end architecture;
|
entity delay2 is
end entity;
architecture test of delay2 is
signal clk : bit;
begin
clock_p: process is
begin
if now < 1 us then
clk <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
else
wait;
end if;
end process;
check_p: process is
variable now_ns : integer;
begin
if now < 1 us then
wait for 0 ns;
now_ns := integer(now / ns);
case now_ns mod 10 is
when 0 =>
assert clk = '0';
when 5 =>
assert clk = '1';
when others =>
report "clk changed at unexpected time";
end case;
wait for 5 ns;
else
wait;
end if;
end process;
end architecture;
|
entity delay2 is
end entity;
architecture test of delay2 is
signal clk : bit;
begin
clock_p: process is
begin
if now < 1 us then
clk <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
else
wait;
end if;
end process;
check_p: process is
variable now_ns : integer;
begin
if now < 1 us then
wait for 0 ns;
now_ns := integer(now / ns);
case now_ns mod 10 is
when 0 =>
assert clk = '0';
when 5 =>
assert clk = '1';
when others =>
report "clk changed at unexpected time";
end case;
wait for 5 ns;
else
wait;
end if;
end process;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FSM_STFILT is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
SF_reg_move_target: in vl_logic;
SF_reg_apbwr : in vl_logic;
xfer_din_mux : in vl_logic_vector(31 downto 0);
C_reg_31 : in vl_logic;
st_filt_cnt_clr : in vl_logic;
st_filt_cnt_inc : in vl_logic;
st_filt_st_one : in vl_logic;
st_filt_st_zero : in vl_logic;
st_filt_curr_st : out vl_logic;
st_filt_next_qual: out vl_logic;
st_filt_0to1_eq : out vl_logic;
st_filt_1to0_eq : out vl_logic;
SF_reg_out : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_PPE_FSM_STFILT;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FSM_STFILT is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
SF_reg_move_target: in vl_logic;
SF_reg_apbwr : in vl_logic;
xfer_din_mux : in vl_logic_vector(31 downto 0);
C_reg_31 : in vl_logic;
st_filt_cnt_clr : in vl_logic;
st_filt_cnt_inc : in vl_logic;
st_filt_st_one : in vl_logic;
st_filt_st_zero : in vl_logic;
st_filt_curr_st : out vl_logic;
st_filt_next_qual: out vl_logic;
st_filt_0to1_eq : out vl_logic;
st_filt_1to0_eq : out vl_logic;
SF_reg_out : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_PPE_FSM_STFILT;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FSM_STFILT is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
SF_reg_move_target: in vl_logic;
SF_reg_apbwr : in vl_logic;
xfer_din_mux : in vl_logic_vector(31 downto 0);
C_reg_31 : in vl_logic;
st_filt_cnt_clr : in vl_logic;
st_filt_cnt_inc : in vl_logic;
st_filt_st_one : in vl_logic;
st_filt_st_zero : in vl_logic;
st_filt_curr_st : out vl_logic;
st_filt_next_qual: out vl_logic;
st_filt_0to1_eq : out vl_logic;
st_filt_1to0_eq : out vl_logic;
SF_reg_out : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_PPE_FSM_STFILT;
|
-------------------------------------------------------------------------------
-- Title : Vivadi DDS sin lut for SIRIUS 130M
-- Project :
-------------------------------------------------------------------------------
-- File : dds_sin_lut.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-04-15
-- Last update: 2015-04-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Temporary sine lut for SIRIUS machine with 130M ADC generated
-- through Vivado.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-15 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
-------------------------------------------------------------------------------
entity dds_sin_lut is
port (
clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end entity dds_sin_lut;
architecture str of dds_sin_lut is
component generic_rom
generic (
g_data_width : natural := 32;
g_size : natural := 16384;
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end component;
begin
cmp_sin_lut_sirius_52_203_1 : generic_rom
generic map (
g_data_width => 16,
g_size => 203,
g_init_file => "sin_lut_sirius_52_203.mif",
g_fail_if_file_not_found => true
)
port map (
rst_n_i => '1',
clk_i => clka,
a_i => addra,
q_o => douta
);
end architecture str;
|
-------------------------------------------------------------------------------
-- $Id: opb_bam.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_bam.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_bam.vhd
-- Version: v3.01a
-- Description: Bus Attachment Module, OPB to IPIC.
--
-- VHDL Standard: VHDL 93
-------------------------------------------------------------------------------
-- Structure: opb_bam
-- -- reset_mir
-- -- interrupt_control
-- -- rdpfifo_top
-- -- wrpfifo_top
-- -- opb_be_gen
-- -- brst_addr_cntr
-- -- brst_addr_cntr_reg
-- -- opb_flex_addr_cntr
-- -- write_buffer
-- -- srl_fifo3
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
--
-- FLO 10/22/02
-- ^^^^^^
-- Initial version.
-- ~~~~~~
-- FLO 12/09/02
-- ^^^^^^
-- Support now for posted writes and burst of posted writes under
-- OPB_seqAddr=1. (The latter not yet tested.)
-- ~~~~~~
-- FLO 03/21/03
-- ^^^^^^
-- Hooked up neglected connection of OPB_BE to opb_be_s0.
-- ~~~~~~
-- FLO 05/15/2003
-- ^^^^^^
-- Introduced signal OPB_seqAddr_eff to disable bursts when parameter
-- C_DEV_BURST_ENABLE is false.
-- ~~~~~~
--
-- FLO 05/27/2003
-- ^^^^^^
-- Use sln_xferack_s1 to enable other than '0' values to the
-- OPBOUT pipestage when this stage is present and there is
-- a single address range. This, in turn, allows the optimization
-- of passing ip2bus_data through to ip2bus_data_mx without
-- qualification by a CE Address-Range decode, saving a LUT per
-- data-bus bit for this case.
-- ~~~~~~
--
-- FLO 05/28/2003
-- ^^^^^^
-- Made a correction to the last change that was causing it to
-- drive sln_dbus during a write transaction.
-- Now the sln_dbus_s2 signals are separated from the other _s2 signals
-- for application of the reset when sln_xferack_s1 = '0' and this
-- reset is further qualified by bus2ip_rnw_s1.
-- ~~~~~~
-- FLO 09/10/2003
-- ^^^^^^
-- Fixed the mirror instantiation, which erroneously had the address tied low.
-- ~~~~~~
--
-- ALS 10/22/03
-- ^^^^^^
-- Creation of version v3_00_b to include read and write packet FIFOs.
-- Also modified code for direct entity instantiation.
-- ~~~~~~
-- ALS 11/18/03
-- ^^^^^^
-- Creation of version v3_01_a to modify generics and some ports to align
-- with the PLB IPIF. Added look-ahead address counter for read bursts and write
-- buffer for write bursts.
-- ~~~~~~~
--
-- ALS 04/09/04
-- ^^^^^^
-- Removed vectorization of IP2Bus signals
-- ^^^^^^
-- GAB 04/15/04
-- ^^^^^^
-- - Updated to use libraries proc_common_v2_00_a, wrpfifo_v1_01_b,
-- rdpfifo_v1_01_b, and interrupt_control_v1_00_a.
-- - Fixed issues with wrpfifo for pipeline model 0
-- - Fixed issues with wrpfifo and rdpfifo for cases when write buffer
-- was instantiated.
-- - Fixed issues with master aborts, delayed IP acknowledges.
-- - Fixed double clock wide wrce which caused an interrupt to be generated
-- when an interrupt was cleared.
-- - Improved utilization by allowing the tools to place the read mux
-- - Removed checks on postedwrinh when write buffer was instantiated because
-- the write buffer currently does not support this feature.
-- - Set MAX_USER_ADDR_RANGE minimum to 7 because opb_flex_addr_cntr.vhd expects
-- a minimum of 7 address bits to decode.
-- - Changed reset/mir to be posted write inhibited because of problems with
-- various pipeline models and single beat reads. CS,CE, etc. to reset_mir
-- would not occur because they where inhibited on the same clock cycle as
-- they were to be generated.
-- - Created abort detection logic for pipeline models 1,3, and 7 to allow the
-- ipif to properly recover from a master abort.
--
-- ~~~~~~~
-- GAB 07/07/04
-- ^^^^^^
-- - Fixed issues with dynamic switching of IP2Bus_PostedWrInh signal
-- - Optimized slave data read mux
-- - Fixed issue with Bus2IP_Burst signal when WriteBuffer was instantiated
-- - Fixed issue with Bus2IP_AddrValid when WriteBuffer was instantiated
-- ~~~~~~~
-- GAB 08/10/04
-- ^^^^^^
-- - Modified port range for IP2RFIFO_Data and WFIFO2IP_Data to be based on
-- the C_ARD_DWIDTH_ARRAY generic and not hard coded. Fixes CR191551
-- - Added synopsys translate_off/translate_on statements to exclude assert
-- statements from the synthesis process.
-- - Added assert statement to check for match of C_ARD_DWIDTH_ARRAY element
-- and fifo WR_WIDTH_BITS setting, though the mis-match of array sizes should
-- cause the simulation to error out on load.
-- ~~~~~~~
-- GAB 07/06/05
-- ^^^^^^
-- Removed xfer_abort signal from Sln_xferack logic to help improve timing.
-- ~~~~~~~
-- GAB 08/05/05
-- ^^^^^^
-- Fixed issue with IP2Bus_Postedwrinh_s2 getting reset with OPB_Select would
-- negate. IP2Bus_Postedwrinh_s2 should only negat based on UserIP.
-- ~~~~~~~
--
-- GAB 09/21/05
-- ^^^^^^
-- Fixed long timing path issue with Sln_Retry signal and cycle aborts. Modified
-- logic to suppress sln_xferack_s1 with cycle_abort for models where out-pipe was
-- included.
-- ~~~~~~~
-- GAB 10/12/05
-- ^^^^^^
-- Incorperated rev C mods into rev A to fix slow timing path with the address
-- decode. The modification simply shifts the input pipe stage for the address
-- to after the address decode. Therefore the functionality does not change
-- nor does the latency. This fix only improves pipeline 5 and 7 (i.e. any
-- with a model with a input pipeline stage).
-- ~~~~~~~
-- GAB 5/19/06
-- ^^^^^^
-- Removed unused last_wr_xferack, last_wr_xferack_d1,
-- and last_wr_xferack_d2.
-- Added bus2ip_rnw_s1 signal to SLN_XFERACK_PROC process's sinsitivity list.
-- This fixes CR231744.
-- ~~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-- -------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.all;
use opb_v20_v1_10_d.ipif_pkg.all;
use opb_v20_v1_10_d.ipif_steer;
use opb_v20_v1_10_d.family.all;
use opb_v20_v1_10_d.pselect;
use opb_v20_v1_10_d.or_muxcy;
use opb_v20_v1_10_d.reset_mir;
use opb_v20_v1_10_d.brst_addr_cntr;
use opb_v20_v1_10_d.brst_addr_cntr_reg;
use opb_v20_v1_10_d.opb_be_gen;
use opb_v20_v1_10_d.interrupt_control;
use opb_v20_v1_10_d.wrpfifo_top;
use opb_v20_v1_10_d.rdpfifo_top;
entity opb_bam is
generic
(
C_ARD_ID_ARRAY : INTEGER_ARRAY_TYPE
:= ( 0 => IPIF_INTR,
1 => IPIF_RST,
2 => USER_00
);
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= ( x"0000_0000_6000_0000", -- IPIF_INTR
x"0000_0000_6000_003F",
--
x"0000_0000_6000_0040", -- IPIF_RST
x"0000_0000_6000_0043",
--
x"0000_0000_6000_0100", -- USER_00
x"0000_0000_6000_01FF"
);
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE
:= ( 32, -- IPIF_INTR
32, -- IPIF_INTR
32 -- USER_00
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
:= ( 16, -- IPIF_INTR
1, -- IPIF_RST
8 -- USER_00
);
C_ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE
:= (
0 => (others => 0)
,1 => (others => 0)
,2 => (others => 0)
);
C_PIPELINE_MODEL : integer := 7;
-- The pipe stages are enumerated and numbered as:
-- -- ----------
-- n Pipe stage
-- -- ----------
-- 0 OPBIN
-- 1 IPIC
-- 2 OPBOUT
-- Each pipe stage is either present or absent (i.e. bypassed).
-- The pipe stage, n, is present if the (2^n)th
-- bit in C_PIPELINE_MODEL is 1.
--
C_DEV_BLK_ID : INTEGER := 1;
-- Unique block ID, assigned to the device when the system is built.
C_DEV_MIR_ENABLE : INTEGER := 0;
C_OPB_AWIDTH : INTEGER := 32;
-- width of Address Bus (in bits)
C_OPB_DWIDTH : INTEGER := 32;
-- Width of the Data Bus (in bits)
C_FAMILY : string := "virtexe";
--
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := ( 5, 1 );
--
-- There will be one interrupt signal for each entry in
-- C_IP_INTR_MODE_ARRAY. The leftmost entry will be the
-- mode for input port IP2Bus_Intr(0), the next entry
-- for IP2Bus_Intr(1), etc.
--
-- These modes are supported:
--
-- Mode Description
--
-- 1 Active-high interrupt condition.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port-- that is an interrupt condition
-- that is latched and cleared in the IP core and made available
-- to the system via the Interrupt Source Controller in
-- the Bus Attachment Module.
--
-- 2 Active-low interrupt condition.
-- Like 1, except that the interrupt condition is asserted low.
--
-- 3 Active-high pulse interrupt event.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port--whose single clock period of active-high
-- assertion is an interrupt event that is latched,
-- and cleared as a service of the Interrupt Source
-- Controller in the Bus Attachment Module.
--
-- 4 Active-low pulse interrupt event.
-- Like 3, except the interrupt-event pulse is active low.
--
-- 5 Positive-edge interrupt event.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port--whose low-to-high transition, synchronous
-- with the clock, is an interrupt event that is latched,
-- and cleared as a service of the Interrupt Source
-- Controller in the Bus Attachment Module.
--
-- 6 Negative-edge interrupt event.
-- Like 5, except that the interrupt event is a
-- high-to-low transition.
--
-- Other mode codes are reserved.
--
C_DEV_BURST_ENABLE : INTEGER := 0;
-- Burst Enable for IPIF Interface
C_INCLUDE_ADDR_CNTR : INTEGER := 0;
-- ALS added generic for read address counter
-- inclusion of read address look ahead counter and write address counter
C_INCLUDE_WR_BUF : INTEGER := 0
-- ALS: added generic for write buffer
);
port
(
-- OPB signals
OPB_select : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_RNW : in std_logic;
OPB_seqAddr : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
-- IPIC signals (address, data, acknowledges)
Bus2IP_CS : out std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
Bus2IP_CE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Data : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Bus2IP_Addr : out std_logic_vector(0 to C_OPB_AWIDTH-1);
Bus2IP_AddrValid : out std_logic;
Bus2IP_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
Bus2IP_RNW : out std_logic;
Bus2IP_Burst : out std_logic;
IP2Bus_Data : in std_logic_vector(0 to C_OPB_DWIDTH-1);
IP2Bus_Ack : in std_logic;
IP2Bus_AddrAck : in std_logic;
IP2Bus_Error : in std_logic;
IP2Bus_Retry : in std_logic;
IP2Bus_ToutSup : in std_logic;
IP2Bus_PostedWrInh : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
-- IPIC signals (Read Packet FIFO)
IP2RFIFO_Data : in std_logic_vector(0 to C_ARD_DWIDTH_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY,
IPIF_RDFIFO_DATA)) - 1) := (others => '0');
IP2RFIFO_WrMark : in std_logic := '0';
IP2RFIFO_WrRelease : in std_logic := '0';
IP2RFIFO_WrReq : in std_logic := '0';
IP2RFIFO_WrRestore : in std_logic := '0';
RFIFO2IP_AlmostFull : out std_logic;
RFIFO2IP_Full : out std_logic;
RFIFO2IP_Vacancy : out std_logic_vector(0 to bits_needed_for_vac(
find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe
(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA))) - 1);
RFIFO2IP_WrAck : out std_logic;
-- IPIC signals (Write Packet FIFO)
IP2WFIFO_RdMark : in std_logic := '0';
IP2WFIFO_RdRelease : in std_logic := '0';
IP2WFIFO_RdReq : in std_logic := '0';
IP2WFIFO_RdRestore : in std_logic := '0';
WFIFO2IP_AlmostEmpty: out std_logic;
WFIFO2IP_Data : out std_logic_vector(0 to C_ARD_DWIDTH_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY,
IPIF_WRFIFO_DATA)) - 1);
WFIFO2IP_Empty : out std_logic;
WFIFO2IP_Occupancy : out std_logic_vector(0 to bits_needed_for_occ(
find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe
(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA))) - 1);
WFIFO2IP_RdAck : out std_logic;
-- interrupts
IP2Bus_IntrEvent : in std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
IP2INTC_Irpt : out std_logic;
-- Software test breakpoint signal
Freeze : in std_logic;
Bus2IP_Freeze : out std_logic;
-- clocks and reset
OPB_Clk : in std_logic;
Bus2IP_Clk : out std_logic;
IP2Bus_Clk : in std_logic;
Reset : in std_logic;
Bus2IP_Reset : out std_logic
);
end entity opb_bam;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
architecture implementation of opb_bam is
-------------------------------------------------------------------------------
-- Function and Constant Declarations
-------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- MIR fields
--
-- 4 7 5 8 8 # bits
--
-- 0-----3 4----------10 11-----15 16-----------23 24------------31
-- +-------+-------------+---------+---------------+----------------+
-- |MAJOR | MINOR |REVISION | BLK_ID | TYPE | MIR
-- |VERSION| VERSION |(letter) | | |
-- +-------+-------------+---------+---------------+----------------+
-- 0 = a
-- 1 = b
-- etc.
--
-- \ | /
-- \ | /
-- \ | /
-- \ | /
-- \ | /
-- \ | /
--
-- v1_03_c (aka V1.3c)
----------------------------------------------------------------------------
-- constant MIR_MAJOR_VERSION : INTEGER range 0 to 15 := 1;
-- constant MIR_MINOR_VERSION : INTEGER range 0 to 127:= 0;
-- constant MIR_REVISION : INTEGER := 0;
-- ALS - modified MIR_MAJOR_VERSION to 3 and MIR_MINOR_VERSION to 1
constant MIR_MAJOR_VERSION : INTEGER range 0 to 15 := 3;
constant MIR_MINOR_VERSION : INTEGER range 0 to 127:= 1;
constant MIR_REVISION : INTEGER range 0 to 25 := 0;
constant MIR_TYPE : INTEGER := 1;
-- Always '1' for OPB ipif interface type
-- ToDo, stays same for bus_attach?
constant NUM_ARDS : integer := C_ARD_ID_ARRAY'length;
constant NUM_CES : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant WRBUF_DEPTH : integer := 16;
constant INCLUDE_OPBIN_PSTAGE : boolean := (C_PIPELINE_MODEL/1) mod 2 = 1;
constant INCLUDE_IPIC_PSTAGE : boolean := (C_PIPELINE_MODEL/2) mod 2 = 1;
constant INCLUDE_OPBOUT_PSTAGE : boolean := (C_PIPELINE_MODEL/4) mod 2 = 1;
constant INCLUDE_RESET_MIR : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_RST);
constant INCLUDE_INTR : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_INTR);
constant INCLUDE_ADDR_CNTR : boolean
:= (C_INCLUDE_ADDR_CNTR=1 and C_DEV_BURST_ENABLE=1)
or (C_INCLUDE_ADDR_CNTR=1 and C_INCLUDE_WR_BUF=1);
-- ALS - added boolean constants for Read and Write Packet FIFOs
constant INCLUDE_RDFIFO : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA);
constant INCLUDE_WRFIFO : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA);
-- Set SINGLE_CE if the only attached element is a user IP with only 1 CE.
constant SINGLE_CE : boolean := C_ARD_ID_ARRAY'length = 1
and C_ARD_NUM_CE_ARRAY(0) = 1
and C_ARD_ID_ARRAY(0) /= IPIF_RST;
-- constant ZERO_SLV : std_logic_vector(0 to 199) := (others => '0');
constant VIRTEX_II : boolean := derived(C_FAMILY, virtex2);
---------------------------------------------------------------------------
-- Function bo2sl
---------------------------------------------------------------------------
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl_table : bo2sl_type := ('0', '1');
function bo2sl(b: boolean) return std_logic is
begin
return bo2sl_table(b);
end bo2sl;
---------------------------------------------------------------------------
-- Function num_common_high_order_addr_bits
---------------------------------------------------------------------------
----------------------------------------------------------------------------
-- This function returns the number of high-order address bits
-- that can be commonly decoded across all address pairs passed in as
-- the argument ara. Note: only the C_OPB_AWIDTH rightmost bits of an entry
-- in ara are considered to make up the address.
----------------------------------------------------------------------------
function num_common_high_order_addr_bits(ara: SLV64_ARRAY_TYPE)
return integer is
variable n : integer := C_OPB_AWIDTH;
-- Maximum number of common high-order bits for
-- the ranges starting at an index less than i.
variable i, j: integer;
variable old_base: std_logic_vector(0 to C_OPB_AWIDTH-1)
:= ara(0)( ara(0)'length-C_OPB_AWIDTH
to ara(0)'length-1
);
variable new_base, new_high: std_logic_vector(0 to C_OPB_AWIDTH-1);
begin
i := 0;
while i < ara'length loop
new_base := ara(i )(ara(0)'length-C_OPB_AWIDTH to ara(0)'length-1);
new_high := ara(i+1)(ara(0)'length-C_OPB_AWIDTH to ara(0)'length-1);
j := 0;
while j < n -- Limited by earlier value.
and new_base(j) = old_base(j) -- High-order addr diff found
-- with a previous range.
and (new_base(j) xor new_high(j))='0' -- Addr-range boundary found
-- for current range.
loop
j := j+1;
end loop;
n := j;
i := i+2;
end loop;
return n;
end num_common_high_order_addr_bits;
constant K_DEV_ADDR_DECODE_WIDTH
: integer
:= num_common_high_order_addr_bits(C_ARD_ADDR_RANGE_ARRAY);
---------------------------------------------------------------------------
-- Function cs_index_or_maxint
---------------------------------------------------------------------------
function cs_index_or_maxint(C_ARD_ID_ARRAY:INTEGER_ARRAY_TYPE; ID:INTEGER)
return integer is
begin
if find_ard_id(C_ARD_ID_ARRAY, ID) then
return get_id_index(C_ARD_ID_ARRAY, ID);
else
return integer'high;
end if;
end cs_index_or_maxint;
constant RESET_MIR_CS_IDX : natural
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_RST);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_RESET_MIR is false.
constant INTR_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_INTR);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_INTR is false.
-- ALS - added read and write packet FIFOs indices
constant RDFIFO_DATA_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_RDPFIFO is false.
constant RDFIFO_REG_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_RDFIFO_REG);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_RDPFIFO is false.
constant WRFIFO_DATA_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_WRPFIFO is false.
constant WRFIFO_REG_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_WRFIFO_REG);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_WRPFIFO is false.
---------------------------------------------------------------------------
-- Function ce_index_or_maxint
---------------------------------------------------------------------------
function ce_index_or_maxint(C_ARD_ID_ARRAY: INTEGER_ARRAY_TYPE; IDX: integer)
return integer is
begin
if IDX < NUM_ARDS then
return calc_start_ce_index(C_ARD_NUM_CE_ARRAY, IDX);
else
return integer'high;
end if;
end ce_index_or_maxint;
constant RESET_MIR_CE_IDX : natural
:=ce_index_or_maxint(C_ARD_ID_ARRAY,
RESET_MIR_CS_IDX);
constant INTR_CE_LO : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
INTR_CS_IDX);
-- ALS - added constants for read and write FIFOS
constant RFIFO_REG_CE_LO : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
RDFIFO_REG_CS_IDX);
constant RFIFO_DATA_CE : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
RDFIFO_DATA_CS_IDX);
constant WFIFO_REG_CE_LO : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
WRFIFO_REG_CS_IDX);
constant WFIFO_DATA_CE : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
WRFIFO_DATA_CS_IDX);
---------------------------------------------------------------------------
-- Function ce_hi_avoiding_bounds_error (was intr_ce_hi_avoiding_bounds_error)
-- ALS - modified this function to be usable by the FIFO Register CEs
---------------------------------------------------------------------------
function ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY: INTEGER_ARRAY_TYPE;
CS_IDX: integer
) return integer is
begin
if CS_IDX < NUM_ARDS then
return calc_start_ce_index(C_ARD_NUM_CE_ARRAY, CS_IDX)
+ C_ARD_NUM_CE_ARRAY(CS_IDX) - 1;
else
return integer'high;
end if;
end ce_hi_avoiding_bounds_error;
constant INTR_CE_HI : natural
:= ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY,
INTR_CS_IDX
);
-- ALS - added constant for read/write FIFO register CE high
constant RFIFO_REG_CE_HI : natural
:= ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY,
RDFIFO_REG_CS_IDX
);
constant WFIFO_REG_CE_HI : natural
:= ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY,
WRFIFO_REG_CS_IDX
);
---------------------------------------------------------------------------
-- Function number_CEs_for
---------------------------------------------------------------------------
function number_CEs_for(ard_id: integer) return integer is
variable id_included: boolean;
begin
id_included := find_ard_id(C_ARD_ID_ARRAY, ard_id);
if id_included then
return C_ARD_NUM_CE_ARRAY(get_id_index(C_ARD_ID_ARRAY, ard_id));
else return 0;
end if;
end number_CEs_for;
----------------------------------------------------------------------------
-- Constant zero std_logic_vector large enough for any needed use.
----------------------------------------------------------------------------
constant ZSLV : std_logic_vector(0 to 255) := (others => '0');
---------------------------------------------------------------------------
-- Function num_decode_bits
---------------------------------------------------------------------------
----------------------------------------------------------------------------
-- This function returns the number of address bits that need to be
-- decoded to find a "hit" in the address range defined by
-- the idx'th pair of base_address/high_address in c_ard_addr_range_array.
-- Only the rightmost numbits are considered and the result is the
-- number of leftmost bits within this field that need to be decoded.
----------------------------------------------------------------------------
function num_decode_bits(ard_addr_range_array : SLV64_ARRAY_TYPE;
numbits : natural;
idx : natural)
return integer is
constant SZ : natural := ard_addr_range_array(0)'length;
constant ADDR_XOR : std_logic_vector(0 to numbits-1)
:= ard_addr_range_array(2*idx )(SZ-numbits to SZ-1) -- base
xor ard_addr_range_array(2*idx+1)(SZ-numbits to SZ-1); -- high
begin
for i in 0 to numbits-1 loop
if ADDR_XOR(i)='1' then return i;
end if;
end loop;
return(numbits);
end function num_decode_bits;
---------------------------------------------------------------------------
-- Function encoded_size_is_1
---------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Returns whether bit n of the encoded representation of the data size
-- for address range ar is a 1
--
-- DSIZE Encoded value
-- 8 001
-- 16 010
-- 32 011
-- 64 100
-- 128 101
-- Others not supported
--------------------------------------------------------------------------
function encoded_size_is_1(ar, n: natural) return boolean is
begin
case n is
-- high-order bit
when 0 => return C_ARD_DWIDTH_ARRAY(ar) = 64 or
C_ARD_DWIDTH_ARRAY(ar) =128;
-- middle bit
when 1 => return C_ARD_DWIDTH_ARRAY(ar) = 16 or
C_ARD_DWIDTH_ARRAY(ar) = 32;
-- low-order bit
when 2 => return C_ARD_DWIDTH_ARRAY(ar) = 8 or
C_ARD_DWIDTH_ARRAY(ar) = 32 or
C_ARD_DWIDTH_ARRAY(ar) =128;
-- default for unsupported values
when others => return false;
end case;
end encoded_size_is_1;
---------------------------------------------------------------------------
-- Function num_cs_for_bit
---------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Returns the number of CS signals that need to be or'ed to give
-- bit n of the encoded size.
----------------------------------------------------------------------------
function num_cs_for_bit(n: natural) return natural is
variable r: natural;
begin
r := 0;
for k in 0 to NUM_ARDS-1 loop
if encoded_size_is_1(k, n) then r := r+1; end if;
end loop;
return r;
end num_cs_for_bit;
---------------------------------------------------------------------------
-- Function eff_ip2bus_val
---------------------------------------------------------------------------
-- ALS - modified to include read and write packet fifos
function eff_ip2bus_val(i : integer;
rst : std_logic;
intr : std_logic;
wrfifo : std_logic;
rdfifo : std_logic;
user : std_logic
) return std_logic is
begin
if C_ARD_ID_ARRAY(i) = IPIF_RST then return rst;
elsif C_ARD_ID_ARRAY(i) = IPIF_INTR then return intr;
elsif C_ARD_ID_ARRAY(i) = IPIF_WRFIFO_REG or
C_ARD_ID_ARRAY(i) = IPIF_WRFIFO_DATA then return wrfifo;
elsif C_ARD_ID_ARRAY(i) = IPIF_RDFIFO_REG or
C_ARD_ID_ARRAY(i) = IPIF_RDFIFO_DATA then return rdfifo;
else return user;
end if;
end eff_ip2bus_val;
---------------------------------------------------------------------------
-- ALS: added function get_max_addr_range
-- Function get_max_addr_range
-- This function parses the ARD_ADDR_RANGE_ARRAY to determine which
-- baseaddr/highaddr pair spans the greatest address range. This is then
-- used to size the burst address counter
---------------------------------------------------------------------------
function get_max_user_addr_range(bus_awidth:integer) return integer is
variable max_range : integer := 0;
variable curr_range : integer := 0;
begin
for i in 0 to C_ARD_ADDR_RANGE_ARRAY'length/2-1 loop
if C_ARD_ID_ARRAY(i) = IPIF_RST or
C_ARD_ID_ARRAY(i) = IPIF_INTR or
C_ARD_ID_ARRAY(i) = IPIF_WRFIFO_REG or
C_ARD_ID_ARRAY(i) = IPIF_WRFIFO_DATA or
C_ARD_ID_ARRAY(i) = IPIF_RDFIFO_REG or
C_ARD_ID_ARRAY(i) = IPIF_RDFIFO_DATA then
max_range := max_range;
else
-- addr_bits function returns number of address bits that are equal
-- between baseaddr and highaddr, so the address range is the
-- bus width minus the address bits
curr_range := bus_awidth - num_decode_bits(C_ARD_ADDR_RANGE_ARRAY,
C_OPB_AWIDTH,
i);
if curr_range >= max_range then
max_range := curr_range;
else
max_range := max_range;
end if;
end if;
end loop;
return max_range;
end get_max_user_addr_range;
-- opb_flex_addr_cntr requires a minimum range of 7 (or 0 to 6)
-- constant MAX_USER_ADDR_RANGE : integer := get_max_user_addr_range(C_OPB_AWIDTH); --GB
constant MAX_USER_ADDR_RANGE : integer := max2(7,get_max_user_addr_range(C_OPB_AWIDTH)); --GB
------------------------------------------------------------------------------
-- Signal declarations
------------------------------------------------------------------------------
signal bus2ip_clk_i : std_logic;
signal bus2ip_reset_i : std_logic;
signal opb_select_s0 : std_logic;
signal opb_select_s0_d1 : std_logic;
signal opb_rnw_s0 : std_logic;
signal opb_seqaddr_s0 : std_logic;
signal opb_seqaddr_s0_d1 : std_logic;
signal bus2ip_burst_s1 : std_logic;
signal bus2ip_burst_s1_d1 : std_logic;
signal opb_seqaddr_d1 : std_logic;
signal opb_abus_s0 : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal opb_dbus_s0 : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal opb_be_s0 : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal bus2ip_rnw_s1 : std_logic;
signal bus2ip_be_s0 : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal bus2ip_be_s1 : std_logic_vector(0 to C_OPB_DWIDTH/8-1) := (others => '0');
signal bus2ip_cs_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_s0_d1 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_s1 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_hit_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_hit : std_logic_vector(0 to NUM_ARDS-1); -- GAB 10/12/05
signal bus2ip_cs_hit_s0_d1 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_enable_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_ce_s0 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_ce_s1 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_rdce_s0 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_rdce_s1 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_wrce_s0 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_wrce_s1 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_addr_s0 : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal bus2ip_addr_s1 : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal bus2ip_addrvalid_s1 : std_logic;
signal bus2ip_data_s0 : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal bus2ip_data_s1 : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal devicesel_s0 : std_logic;
signal devicesel : std_logic; -- GAB 10/12/05
-- ALS - added address counter signals
signal address_load : std_logic;
signal opb_addr_cntr_out : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal next_opb_addr_cntr_out : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal next_steer_addr_cntr_out : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal steer_addr_cntr_out : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal opb_be_cntr_out : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal opb_be_cntr_steer : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
-- ALS - added bus2ip_rdreq and bus2ip_wrreq and signals to support their
-- generation
signal rdreq : std_logic;
signal rdreq_hold : std_logic;
signal rdreq_hold_rst : std_logic;
signal bus2ip_rdreq_s0 : std_logic;
signal bus2ip_rdreq_s1 : std_logic;
signal Bus2IP_RdReq : std_logic; --REMOVE IF THIS BECOMES A PORT
signal wrreq : std_logic;
signal wrreq_hold : std_logic;
signal wrreq_hold_rst : std_logic;
signal bus2ip_wrreq_s0 : std_logic;
signal bus2ip_wrreq_s1 : std_logic;
signal Bus2IP_WrReq : std_logic; --REMOVE IF THIS BECOMES A PORT
-- ALS added write buffer signals
signal wrbuf_data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal wrbuf_be : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal wrbuf_burst : std_logic;
signal wrbuf_xferack : std_logic;
signal wrbuf_errack : std_logic;
signal wrbuf_retry : std_logic;
signal wrbuf_cs : std_logic_vector(0 to NUM_ARDS-1);
signal wrbuf_rnw : std_logic;
signal wrbuf_ce : std_logic_vector(0 to NUM_CES-1);
signal wrbuf_wrce : std_logic_vector(0 to NUM_CES-1);
signal wrbuf_rdce : std_logic_vector(0 to NUM_CES-1);
signal wrbuf_empty : std_logic;
signal wrbuf_addrcntr_en : std_logic;
signal wrbuf_addrcntr_rst : std_logic;
signal wrbuf_addrvalid : std_logic;
signal ipic_pstage_ce : std_logic;
signal wrdata_ack : std_logic;
signal wrbuf_addrack : std_logic;
-- ALS added transfer start and done signals
signal opb_xfer_done : std_logic;
signal opb_xfer_start : std_logic;
constant NUM_ENCODED_SIZE_BITS : natural := 3;
type OR_CSES_PER_BIT_TABLE_TYPE is array(0 to NUM_ENCODED_SIZE_BITS-1) of
std_logic_vector(0 to NUM_ARDS-1);
signal cs_to_or_for_dsize_bit : OR_CSES_PER_BIT_TABLE_TYPE;
signal encoded_dsize_s0 : std_logic_vector(0
to NUM_ENCODED_SIZE_BITS-1);
signal encoded_dsize_s1 : std_logic_vector(0
to NUM_ENCODED_SIZE_BITS-1);
signal ip2bus_data_mx : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal sln_dbus_s1 : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal sln_dbus_s2 : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal ipic_xferack : std_logic;
signal sln_xferack_s1 : std_logic;
signal sln_xferack_s1_d1 : std_logic;
signal sln_xferack_s1_d2 : std_logic;
signal sln_xferack_s2 : std_logic;
signal sln_retry_s1 : std_logic;
signal sln_retry_s1_d1 : std_logic;
signal sln_retry_s1_d2 : std_logic;
signal sln_retry_s2 : std_logic;
signal sln_errack_s1 : std_logic;
signal sln_errack_s2 : std_logic;
signal sln_toutsup_s1 : std_logic;
signal sln_toutsup_s2 : std_logic;
signal reset2bus_data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal reset2bus_ack : std_logic;
signal reset2bus_error : std_logic;
signal reset2bus_retry : std_logic;
signal reset2bus_toutsup : std_logic;
signal reset2bus_postedwrinh : std_logic;
-- interrupt signals
signal intr2bus_data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal intr2bus_rdack : std_logic;
signal intr2bus_wrack : std_logic;
signal intr2bus_ack : std_logic;
signal intr2bus_error : std_logic;
signal intr2bus_retry : std_logic;
signal intr2bus_toutsup : std_logic;
signal intr2bus_postedwrinh : std_logic;
-- FIFO signals
signal rfifo_error : std_logic;
signal rfifo_rdack : std_logic;
signal rfifo_retry : std_logic;
signal rfifo_toutsup : std_logic;
signal rfifo_wrack : std_logic;
signal rdfifo_ack : std_logic;
signal rdfifo2bus_data : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal rdfifo2intr_deadlock : std_logic;
signal wfifo_error : std_logic;
signal wfifo_rdack : std_logic;
signal wfifo_retry : std_logic;
signal wfifo_toutsup : std_logic;
signal wfifo_wrack : std_logic;
signal wrfifo_ack : std_logic;
signal wrfifo2bus_data : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal wrfifo2intr_deadlock : std_logic;
signal new_pw_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal new_pw_s0_d1 : std_logic_vector(0 to NUM_ARDS-1);
signal inh_cs_when_pw : std_logic_vector(0 to NUM_ARDS-1);
signal inh_cs_wnot_pw : std_logic;
signal inh_xferack_when_pw : std_logic;
signal inh_xferack_when_burst_rd: std_logic;
signal last_xferack : std_logic;
signal last_xferack_s0 : std_logic;
signal last_xferack_d1 : std_logic;
signal last_xferack_d1_s0 : std_logic;
signal last_xferack_d2 : std_logic;
signal last_pw_xferack : std_logic;
signal last_pw_xferack_d1 : std_logic;
signal last_pw_xferack_d2 : std_logic;
-- signal last_wr_xferack : std_logic;
-- signal last_wr_xferack_d1 : std_logic;
-- signal last_wr_xferack_d2 : std_logic;
signal last_burstrd_xferack : std_logic;
signal last_burstrd_xferack_d1 : std_logic;
signal last_burstrd_xferack_d2 : std_logic;
signal OPB_seqAddr_eff : std_logic;
signal postedwr_s0 : std_logic;
signal postedwrack_s2 : std_logic;
signal cycle_abort : std_logic;
signal cycle_abort_d1 : std_logic;
signal xfer_abort : std_logic;
signal cycle_active : std_logic;
signal ip2bus_postedwrinh_s1 : std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
signal ip2bus_postedwrinh_s2 : std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
signal ip2bus_postedwrinh_s2_d1 : std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
signal ip2bus_postedwrinh_s2_d2 : std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
signal ip2bus_xferack : std_logic;
-------------------------------------------------------------------------------
begin
OPB_seqAddr_eff <= OPB_seqAddr and bo2sl(C_DEV_BURST_ENABLE=1);
bus2ip_clk_i <= OPB_Clk;
Bus2IP_Clk <= OPB_Clk;
Bus2IP_Freeze <= Freeze;
reset2bus_postedwrinh <= '1'; --GB
intr2bus_postedwrinh <= '1';
---------------------------------------------------------------------------
-- Pipeline Stage 0
---------------------------------------------------------------------------
GEN_PSTAGE0: if INCLUDE_OPBIN_PSTAGE generate
begin
PROC_PSTAGE0 : process(bus2ip_clk_i)
begin
--------------------------------------------------------------------
-- Sigs that need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if Reset = '1' then
opb_select_s0 <= '0';
bus2ip_cs_hit_s0 <= (others => '0'); -- GAB 10/12/05
else
opb_select_s0 <= OPB_select;
bus2ip_cs_hit_s0 <= bus2ip_cs_hit; -- GAB 10/12/05
end if;
end if;
--------------------------------------------------------------------
-- Sigs that do not need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
opb_rnw_s0 <= OPB_RNW;
opb_seqaddr_s0 <= OPB_seqAddr_eff;
opb_abus_s0 <= OPB_ABus;
opb_dbus_s0 <= OPB_DBus;
opb_be_s0 <= OPB_BE;
last_xferack_s0 <= last_xferack;
last_xferack_d1_s0 <= last_xferack_d1;
end if;
end process;
end generate;
--
GEN_BYPASS0: if not INCLUDE_OPBIN_PSTAGE generate
begin
opb_select_s0 <= OPB_select;
opb_rnw_s0 <= OPB_RNW;
opb_seqaddr_s0 <= OPB_seqAddr_eff;
opb_abus_s0 <= OPB_ABus;
opb_dbus_s0 <= OPB_DBus;
opb_be_s0 <= OPB_BE;
last_xferack_s0 <= last_xferack;
last_xferack_d1_s0 <= last_xferack_d1;
bus2ip_cs_hit_s0 <= bus2ip_cs_hit; -- GAB 10/12/05
end generate;
---------------------------------------------------------------------------
-- Pipeline Stage 1
---------------------------------------------------------------------------
GEN_PSTAGE1: if INCLUDE_IPIC_PSTAGE generate
begin
-- RdReq and WrReq need to be registered for this stage independent
-- of write buffer inclusion
PROC_PSTAGE1_RDWR_REQ : process(bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if Reset = '1' then
-- ALS - added bus2ip_rdreq and bus2ip_wrreq
bus2ip_rdreq_s1 <= '0';
bus2ip_wrreq_s1 <= '0';
encoded_dsize_s1 <= (others => '0');
else
bus2ip_rdreq_s1 <= bus2ip_rdreq_s0;
bus2ip_wrreq_s1 <= bus2ip_wrreq_s0;
encoded_dsize_s1 <= encoded_dsize_s0;
end if;
end if;
end process PROC_PSTAGE1_RDWR_REQ;
-- Write Buffer takes place of IPIC PSTAGE for the remaining signals
-- register in this stage only if Write Buffer is not included
WRBUF_IPIC_PSTAGE_GEN: if C_INCLUDE_WR_BUF = 1 generate
bus2ip_cs_s1 <= wrbuf_cs;
bus2ip_ce_s1 <= wrbuf_ce;
bus2ip_wrce_s1 <= wrbuf_wrce;
bus2ip_rdce_s1 <= wrbuf_rdce;
bus2ip_data_s1 <= wrbuf_data;
bus2ip_rnw_s1 <= wrbuf_rnw;
bus2ip_burst_s1 <= wrbuf_burst;
bus2ip_addrvalid_s1 <= wrbuf_addrvalid;
bus2ip_be_s1 <= wrbuf_be;
bus2ip_addr_s1 <= opb_addr_cntr_out;
end generate WRBUF_IPIC_PSTAGE_GEN;
NOWRBUF_IPIC_PSTAGE_GEN: if C_INCLUDE_WR_BUF = 0 generate
begin
PROC_PSTAGE1 : process(bus2ip_clk_i)
begin
--------------------------------------------------------------------
-- Sigs that need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if Reset = '1' then
bus2ip_cs_s1 <= (others => '0');
bus2ip_ce_s1 <= (others => '0');
bus2ip_rdce_s1 <= (others => '0');
bus2ip_wrce_s1 <= (others => '0');
bus2ip_addrvalid_s1 <= '0';
else
bus2ip_cs_s1 <= wrbuf_cs;
bus2ip_ce_s1 <= wrbuf_ce;
bus2ip_wrce_s1 <= wrbuf_wrce;
bus2ip_rdce_s1 <= wrbuf_rdce;
bus2ip_addrvalid_s1 <= wrbuf_addrvalid;
end if;
end if;
--------------------------------------------------------------------
-- Sigs that do not need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
bus2ip_data_s1 <= wrbuf_data;
bus2ip_rnw_s1 <= wrbuf_rnw;
bus2ip_burst_s1 <= wrbuf_burst;
end if;
end process PROC_PSTAGE1;
-- If the address counter is included, it represents the S1 register stage
-- It is just necessary to register the BEs
-- If the address counter is not included, create the register stage for both
-- the address and the BEs
ADDRCNT_IPIC_STAGE: if INCLUDE_ADDR_CNTR generate
bus2ip_addr_s1 <= opb_addr_cntr_out;
ADDRCNT_IPIC_REG_PROC : process(bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
bus2ip_be_s1 <= wrbuf_be; -- BEs output from steering logic
end if;
end process ADDRCNT_IPIC_REG_PROC;
end generate ADDRCNT_IPIC_STAGE;
NOADDRCNT_IPIC_STAGE: if not(INCLUDE_ADDR_CNTR) generate
NOADDRCNT_IPIC_REG_PROC : process(bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
bus2ip_addr_s1 <= opb_addr_cntr_out;
bus2ip_be_s1 <= wrbuf_be; -- BEs output from steering logic
end if;
end process NOADDRCNT_IPIC_REG_PROC;
end generate NOADDRCNT_IPIC_STAGE;
end generate NOWRBUF_IPIC_PSTAGE_GEN;
end generate GEN_PSTAGE1;
--
GEN_BYPASS1: if not INCLUDE_IPIC_PSTAGE generate
begin
bus2ip_cs_s1 <= wrbuf_cs;
bus2ip_ce_s1 <= wrbuf_ce;
bus2ip_wrce_s1 <= wrbuf_wrce;
bus2ip_data_s1 <= wrbuf_data;
bus2ip_rnw_s1 <= wrbuf_rnw;
bus2ip_burst_s1 <= wrbuf_burst;
bus2ip_addrvalid_s1 <= wrbuf_addrvalid;
encoded_dsize_s1 <= encoded_dsize_s0;
bus2ip_rdce_s1 <= wrbuf_rdce;
bus2ip_addr_s1 <= opb_addr_cntr_out;
bus2ip_be_s1 <= wrbuf_be;
-- ALS - added bus2ip_rdreq and bus2ip_wrreq
bus2ip_rdreq_s1 <= bus2ip_rdreq_s0;
bus2ip_wrreq_s1 <= bus2ip_wrreq_s0;
end generate GEN_BYPASS1;
Bus2IP_CS <= bus2ip_cs_s1;
Bus2IP_CE <= bus2ip_ce_s1;
Bus2IP_RdCE <= bus2ip_rdce_s1;
Bus2IP_WrCE <= bus2ip_wrce_s1;
Bus2IP_Addr <= bus2ip_addr_s1;
Bus2IP_Data <= bus2ip_data_s1;
Bus2IP_BE <= bus2ip_be_s1;
Bus2IP_RNW <= bus2ip_rnw_s1;
Bus2IP_Burst <= bus2ip_burst_s1 and or_reduce(bus2ip_cs_s1);
Bus2IP_AddrValid <= bus2ip_addrvalid_s1;
-- ALS - added Bus2IP_RdReq and Bus2IP_WrReq
-- ToDo - determine if these should be ports
Bus2IP_RdReq <= bus2ip_rdreq_s1;
Bus2IP_WrReq <= bus2ip_wrreq_s1;
ip2bus_postedwrinh_s1 <= IP2Bus_PostedWrInh; --GB
---------------------------------------------------------------------------
-- Pipeline Stage 2
---------------------------------------------------------------------------
GEN_PSTAGE2: if INCLUDE_OPBOUT_PSTAGE generate
begin
PROC_PSTAGE2 : process(bus2ip_clk_i)
begin
--------------------------------------------------------------------
-- Sigs that need to be reset by OPB_Select
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if OPB_Select = '0' then
sln_xferack_s2 <= '0';
sln_errack_s2 <= '0';
sln_retry_s2 <= '0';
sln_toutsup_s2 <= '0';
-- ip2bus_postedwrinh_s2 <= (others => '0'); --GB
else
sln_xferack_s2 <= sln_xferack_s1 and not cycle_abort ;
sln_retry_s2 <= sln_retry_s1 ;
sln_errack_s2 <= sln_errack_s1 ;
sln_toutsup_s2 <= sln_toutsup_s1;
-- ip2bus_postedwrinh_s2 <= ip2bus_postedwrinh_s1; --GB
end if;
end if;
--------------------------------------------------------------------
-- Sigs that need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if (Reset or not (sln_xferack_s1 and bus2ip_rnw_s1)) = '1' then
sln_dbus_s2 <= (others => '0');
else
sln_dbus_s2 <= sln_dbus_s1;
end if;
end if;
--------------------------------------------------------------------
-- Sigs that do not need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
postedwrack_s2 <= postedwr_s0;
ip2bus_postedwrinh_s2 <= ip2bus_postedwrinh_s1; --GB
end if;
end process;
end generate;
--
GEN_BYPASS2: if not INCLUDE_OPBOUT_PSTAGE generate
begin
sln_dbus_s2 <= sln_dbus_s1;
sln_xferack_s2 <= sln_xferack_s1 and OPB_Select;
sln_retry_s2 <= sln_retry_s1 and OPB_Select;
sln_errack_s2 <= sln_errack_s1 and OPB_Select;
sln_toutsup_s2 <= sln_toutsup_s1 and OPB_Select;
postedwrack_s2 <= postedwr_s0;
ip2bus_postedwrinh_s2 <= ip2bus_postedwrinh_s1; --GB
end generate;
Sln_Dbus <= sln_dbus_s2;
Sln_xferAck <= sln_xferack_s2 and OPB_Select; --GB
Sln_retry <= sln_retry_s2 and OPB_Select; --GB
-- Sln_xferAck <= sln_xferack_s2 and OPB_Select and not(xfer_abort); --GB
-- Sln_retry <= (sln_retry_s2 or cycle_abort) and OPB_Select; --GB
Sln_errAck <= sln_errack_s2 and OPB_Select;
Sln_toutSup <= sln_toutsup_s2;
-----------------------------------------------------------------------------
-- Extend burst signal by 1 clock
-----------------------------------------------------------------------------
BURST_EXTEND_PROCESS: process (bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i = '1' then
opb_seqaddr_s0_d1 <= opb_seqaddr_s0;
end if;
end process;
------------------------------------------------------------------------------
-- Generation of devicesel_s0
-----------------------------------------------------------------------------
DEVICESEL_S0_I: entity opb_v20_v1_10_d.pselect
generic map (
C_AB => K_DEV_ADDR_DECODE_WIDTH,
C_AW => C_OPB_AWIDTH,
C_BAR => C_ARD_ADDR_RANGE_ARRAY(0)
( C_ARD_ADDR_RANGE_ARRAY(0)'length-C_OPB_AWIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length-1
)
)
port map (
-- A => opb_abus_s0, -- GAB 10/12/05
-- AValid => opb_select_s0, -- GAB 10/12/05
-- CS => devicesel_s0 -- GAB 10/12/05
A => OPB_abus, -- GAB 10/12/05
AValid => OPB_select, -- GAB 10/12/05
CS => devicesel -- GAB 10/12/05
);
------------------------------------------------------------------------------
-- Determination of clock periods on which IPIC transactions are blocked
-- from starting, either because
-- (1) an acknowledged IPIC transaction is finishing and being cleared
-- from the pipeline, or
-- (2) the posted-write pipeline is filling.
-----------------------------------------------------------------------------
DELAYS_FOR_BLK_PROC : process (OPB_Clk) is
begin
if OPB_Clk'event and OPB_Clk='1' then
sln_xferack_s1_d1 <= sln_xferack_s1;
sln_xferack_s1_d2 <= sln_xferack_s1_d1;
sln_retry_s1_d1 <= sln_retry_s1;
sln_retry_s1_d2 <= sln_retry_s1_d1;
opb_select_s0_d1 <= opb_select_s0;
new_pw_s0_d1 <= new_pw_s0;
opb_seqaddr_d1 <= OPB_seqAddr_eff;
-- last_wr_xferack_d1 <= last_wr_xferack;
-- last_wr_xferack_d2 <= last_wr_xferack_d1;
last_burstrd_xferack_d1 <= last_burstrd_xferack;
last_burstrd_xferack_d2 <= last_burstrd_xferack_d1;
bus2ip_cs_hit_s0_d1 <= bus2ip_cs_hit_s0;
ip2bus_postedwrinh_s2_d1 <= ip2bus_postedwrinh_s2;
ip2bus_postedwrinh_s2_d2 <= ip2bus_postedwrinh_s2_d1;
end if;
end process;
--ToDo, can bus2ip_clk_i be used on the above, as below?
DX_FFS_PROC : process (bus2ip_clk_i) is
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
last_xferack_d1 <= last_xferack;
last_xferack_d2 <= last_xferack_d1;
last_pw_xferack_d1 <= last_pw_xferack;
last_pw_xferack_d2 <= last_pw_xferack_d1;
end if;
end process;
-- Code below works with Write buffer included
-- inh_cs_wnot_pw <= bo2sl(
-- not (opb_rnw_s0='1' and OPB_seqAddr_s0='1')
-- -- Do not
-- and -- inhibit when a burst read
-- (
-- (sln_xferack_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE or INCLUDE_OPBOUT_PSTAGE))
--
--
-- or (sln_xferack_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE and INCLUDE_OPBOUT_PSTAGE))
--
--
-- or (sln_retry_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE or INCLUDE_OPBOUT_PSTAGE))
--
-- or (sln_retry_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE and INCLUDE_OPBOUT_PSTAGE))
-- )
-- );
--
-- -- ABove works when burst enable, pipeline model 2, no writebuffer, doing back to back write/reads
-- -- But causes interrupts/ pfifo tests to fail
--
--
-- original code
INH_CS_NOWRBUF_GEN : if C_INCLUDE_WR_BUF = 0 generate
inh_cs_wnot_pw <= bo2sl
(
-- Do not inhibit when a burst read
not (opb_rnw_s0='1' and opb_seqaddr_s0='1')
and
(
(sln_xferack_s1='1' and (INCLUDE_IPIC_PSTAGE))
or
(sln_xferack_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE
or INCLUDE_OPBOUT_PSTAGE))
or
(sln_xferack_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE
and INCLUDE_OPBOUT_PSTAGE))
or
(sln_retry_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE
or INCLUDE_OPBOUT_PSTAGE))
or
(sln_retry_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE
and INCLUDE_OPBOUT_PSTAGE))
)
);
end generate;
INH_CS_WRBUF_GEN : if C_INCLUDE_WR_BUF = 1 generate
inh_cs_wnot_pw <= bo2sl
(
-- Do not inhibit when a burst read
not (opb_rnw_s0='1' and opb_seqaddr_s0_d1='1')
and
(
(sln_xferack_s1='1' and (INCLUDE_IPIC_PSTAGE))
or
(sln_xferack_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE
or INCLUDE_OPBOUT_PSTAGE))
or
(sln_xferack_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE
and INCLUDE_OPBOUT_PSTAGE))
)
);
end generate;
-- GB - Removed check of postedwrinh when write buffer is instantiated. Write buffer
-- logic does not have postedwrinh implemented yet and this was causing a problem
-- with some of the configurations. When the write buffer is instantiated the
-- postedwrinh signal is ignored.
GEN_INH_CS_WPW_NO_WRBUF : if C_INCLUDE_WR_BUF = 0 generate
INH_CS_WHEN_PW_GEN: for i in 0 to NUM_ARDS-1 generate
begin
new_pw_s0(i) <= ((bus2ip_cs_hit_s0(i) and not bus2ip_cs_hit_s0_d1(i))
or (last_xferack_d1_s0 and opb_select_s0))
and not opb_rnw_s0
and not eff_ip2bus_val(
i => i,
rst => reset2bus_postedwrinh,
intr => intr2bus_postedwrinh,
wrfifo => '0',
rdfifo => '0',
user => ip2bus_postedwrinh(i));
inh_cs_when_pw(i) <= bo2sl(
(new_pw_s0(i)='1' and (INCLUDE_OPBIN_PSTAGE or
INCLUDE_OPBOUT_PSTAGE))
or
(new_pw_s0_d1(i)='1' and (INCLUDE_OPBIN_PSTAGE and
INCLUDE_OPBOUT_PSTAGE))
);
end generate;
end generate GEN_INH_CS_WPW_NO_WRBUF;
GEN_INH_CS_WPW_WRBUF : if C_INCLUDE_WR_BUF = 1 generate --GB
INH_CS_WHEN_PW_GEN: for i in 0 to NUM_ARDS-1 generate
begin
new_pw_s0(i) <= ((bus2ip_cs_hit_s0(i) and not bus2ip_cs_hit_s0_d1(i))
or (last_xferack_d1_s0 and opb_select_s0))
and not opb_rnw_s0;
inh_cs_when_pw(i) <= bo2sl(
(new_pw_s0(i)='1' and (INCLUDE_OPBIN_PSTAGE or
INCLUDE_OPBOUT_PSTAGE))
or (new_pw_s0_d1(i)='1' and (INCLUDE_OPBIN_PSTAGE and
INCLUDE_OPBOUT_PSTAGE))
);
end generate;
end generate GEN_INH_CS_WPW_WRBUF;
-- GB - Removed check of postedwrinh when write buffer is instantiated. Write buffer
-- logic does not have postedwrinh implemented yet and this was causing a problem
-- with some of the configurations. When the write buffer is instantiated the
-- postedwrinh signal is ignored.
GEN_PWI_PROC_NO_WRBUF : if C_INCLUDE_WR_BUF = 0 generate
POSTEDWRINH_PROC: process(reset2bus_postedwrinh, intr2bus_postedwrinh,
ip2bus_postedwrinh, bus2ip_cs_hit_s0,
opb_rnw_s0)
variable r : std_logic;
begin
r := '0';
for i in 0 to NUM_ARDS-1 loop
r := r or ( bus2ip_cs_hit_s0(i)
and not eff_ip2bus_val(
i => i,
rst => reset2bus_postedwrinh,
intr => intr2bus_postedwrinh,
wrfifo => '0',
rdfifo => '0',
user => ip2bus_postedwrinh(i)
)
);
end loop;
postedwr_s0 <= bo2sl(r='1' and not opb_rnw_s0='1'); --and C_DEV_BURST_ENABLE=1);--GB
end process;
end generate GEN_PWI_PROC_NO_WRBUF;
GEN_PWI_PROC_WRBUF : if C_INCLUDE_WR_BUF = 1 generate --GB
POSTEDWRINH_PROC: process(reset2bus_postedwrinh, intr2bus_postedwrinh,
bus2ip_cs_hit_s0, opb_rnw_s0)
variable r : std_logic;
begin
r := '0';
for i in 0 to NUM_ARDS-1 loop
r := r or bus2ip_cs_hit_s0(i);
end loop;
postedwr_s0 <= bo2sl(r='1' and not opb_rnw_s0='1' and C_DEV_BURST_ENABLE=1);
end process;
end generate GEN_PWI_PROC_WRBUF;
last_xferack <= sln_xferack_s2
and not OPB_seqAddr_eff
and not(last_xferack_d1);
last_burstrd_xferack <= sln_xferack_s2
and (not OPB_seqAddr_eff and opb_seqaddr_d1) -- falling edge of burst
and not(last_xferack_d1);
inh_xferack_when_burst_rd <= not(or_reduce(new_pw_s0)) and
( (last_burstrd_xferack and bo2sl(INCLUDE_OPBOUT_PSTAGE))
or (last_burstrd_xferack_d1 and bo2sl(INCLUDE_OPBIN_PSTAGE or
INCLUDE_IPIC_PSTAGE))
or (last_burstrd_xferack_d2 and bo2sl(INCLUDE_OPBIN_PSTAGE and
INCLUDE_IPIC_PSTAGE)) );
last_pw_xferack <= sln_xferack_s2 and not OPB_seqAddr_eff and postedwrack_s2;
inh_xferack_when_pw <=
bo2sl((last_pw_xferack='1' and (INCLUDE_OPBOUT_PSTAGE))
or
(last_pw_xferack_d1='1' and (INCLUDE_OPBIN_PSTAGE or
INCLUDE_IPIC_PSTAGE))
or (last_pw_xferack_d2='1' and (INCLUDE_OPBIN_PSTAGE and
INCLUDE_IPIC_PSTAGE)) );
-----------------------------------------------------------------------------
-- ALS: added register to extend burst signal 1 clock
-----------------------------------------------------------------------------
BUS2IP_BURST_EXTEND_PROCESS: process (bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i = '1' then
bus2ip_burst_s1_d1 <= bus2ip_burst_s1;
end if;
end process BUS2IP_BURST_EXTEND_PROCESS;
-----------------------------------------------------------------------------
-- Start and end of transaction detection
-----------------------------------------------------------------------------
opb_xfer_done <= (last_xferack
or sln_retry_s2
-- detected master abort (required for some pipe models)
or (xfer_abort )
-- master abort
or (not(opb_select_s0) and (opb_select_s0_d1) ) );
-- Not being used
-- XFER_DONE_REG_I: FDR
-- port map (
-- Q => opb_xfer_done_d1, --[out]
-- C => bus2ip_clk_i, --[in]
-- D => opb_xfer_done, --[in]
-- R => bus2ip_reset_i --[in]
-- );
-- New xfer starts when any CS is asserted and on the next clock
-- after xfer done if select is still asserted, or on the rising edge
-- of select
opb_xfer_start <= (or_reduce(bus2ip_cs_hit_s0) and not xfer_abort and --GB
( (opb_select_s0 and last_xferack_d1_s0)
or (opb_select_s0 and not(opb_select_s0_d1)) ) );
------------------------------------------------------------------------------
-- ALS: added address counter and BE generator
-- Generation of address counter and BE generator
-- When the IPIC pipe stage is included, a registered counter is used. The counter
-- register acts as the IPIC pipe stage register. The CE
-- generation logic needs the next address count so that the output CEs are
-- in alignment with the address
-- When the IPIC pipe stage is not included, a direct path counter is used.
-- The next address count is the same as the address count and the output CEs
-- will align with the address.
-- Steer address counter generates the addresses on each IP2Bus Ack
-- for use in generating the byte enables
------------------------------------------------------------------------------
ADDRCNT_BE_GEN: if INCLUDE_ADDR_CNTR or C_INCLUDE_WR_BUF = 1 generate
signal byte_xfer : std_logic;
signal hw_xfer : std_logic;
signal fw_xfer : std_logic;
signal addrcntr_en : std_logic;
signal steeraddr_cnt_en : std_logic;
begin
addrcntr_en <= IP2Bus_AddrAck
and wrbuf_addrcntr_en
and bus2ip_burst_s1;
steeraddr_cnt_en <= IP2Bus_Ack and bus2ip_burst_s1;
address_load <= opb_xfer_start and wrbuf_empty;
BE_GEN_I: entity opb_v20_v1_10_d.opb_be_gen
generic map (
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_INCLUDE_WR_BUF => C_INCLUDE_WR_BUF
)
port map (
Bus_clk => bus2ip_clk_i,
Address_in => next_steer_addr_cntr_out,
BE_in => opb_be_s0,
Load_BE => address_load,
Rst_BE => bus2ip_reset_i,
BE_out => opb_be_cntr_out,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer
);
DIRECTPATH_CNTR_GEN: if not(INCLUDE_IPIC_PSTAGE) and C_INCLUDE_WR_BUF=0 generate
-- since no IPIC pipe stage, use direct path cntr so that there is not
-- a clock delay for loading the address
signal addr_cntr_load : std_logic;
begin
addr_cntr_load <= not((or_reduce(bus2ip_cs_hit_s0))) or opb_xfer_done;
BUS2IPADDR_CNTR_I: entity opb_v20_v1_10_d.brst_addr_cntr
generic map (
C_CNTR_WIDTH => MAX_USER_ADDR_RANGE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH )
port map (
Address_in => opb_abus_s0,
Addr_load => addr_cntr_load,
Addr_CntEn => addrcntr_en,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer,
Address_out => opb_addr_cntr_out,
OPB_Clk => bus2ip_clk_i);
-- since directpath cntr, next count value is the same as the count value
next_opb_addr_cntr_out <= opb_addr_cntr_out;
STEERADDR_CNTR_I: entity opb_v20_v1_10_d.brst_addr_cntr
generic map (
C_CNTR_WIDTH => MAX_USER_ADDR_RANGE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH )
port map (
Address_in => opb_abus_s0,
Addr_load => addr_cntr_load,
Addr_CntEn => steeraddr_cnt_en,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer,
Address_out => steer_addr_cntr_out,
OPB_Clk => bus2ip_clk_i);
-- since directpath cntr, next count value is the same as the count value
next_steer_addr_cntr_out <= steer_addr_cntr_out;
end generate DIRECTPATH_CNTR_GEN;
REG_CNTR_GEN: if INCLUDE_IPIC_PSTAGE or C_INCLUDE_WR_BUF = 1 generate
-- since IPIC pipe stage, use registered counter. This will act as the pipe stage
-- for the address. The CEs will use the un-registered counter address so that
-- they align with the address after going through the pipe stage
BUS2IPADDR_CNTR_I: entity opb_v20_v1_10_d.brst_addr_cntr_reg
generic map (
C_CNTR_WIDTH => MAX_USER_ADDR_RANGE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH)
port map (
Bus_reset => bus2ip_reset_i,
Bus_clk => bus2ip_clk_i,
Xfer_done => opb_xfer_done,
RNW => wrbuf_rnw,
Addr_Load => address_load,
Addr_Cnt_en => addrcntr_en,
Addr_Cnt_rst => wrbuf_addrcntr_rst,
Address_In => opb_abus_s0,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer,
Next_address_out => next_opb_addr_cntr_out,
Address_Out => opb_addr_cntr_out
);
STEERADDR_CNTR_I: entity opb_v20_v1_10_d.brst_addr_cntr_reg
generic map (
C_CNTR_WIDTH => MAX_USER_ADDR_RANGE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH)
port map (
Bus_reset => bus2ip_reset_i,
Bus_clk => bus2ip_clk_i,
Xfer_done => opb_xfer_done,
RNW => wrbuf_rnw,
Addr_Load => address_load,
Addr_Cnt_en => steeraddr_cnt_en,
Addr_Cnt_rst => bus2ip_reset_i,
Address_In => opb_abus_s0,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer,
Next_address_out => next_steer_addr_cntr_out,
Address_Out => steer_addr_cntr_out
);
end generate REG_CNTR_GEN;
end generate ADDRCNT_BE_GEN;
NO_ADDRCNT_BE_GEN: if not(INCLUDE_ADDR_CNTR) and C_INCLUDE_WR_BUF = 0 generate
next_opb_addr_cntr_out <= opb_abus_s0;
opb_addr_cntr_out <= opb_abus_s0;
next_steer_addr_cntr_out<= opb_abus_s0;
steer_addr_cntr_out <= opb_abus_s0;
opb_be_cntr_out <= opb_be_s0;
address_load <= '1';
end generate NO_ADDRCNT_BE_GEN;
-----------------------------------------------------------------------------
-- Generation of Write Buffer
-----------------------------------------------------------------------------
WRITE_BUFFER_GEN: if C_INCLUDE_WR_BUF = 1 generate
begin
wrbuf_addrack <= IP2Bus_AddrAck;
wrdata_ack <= '1' when (ipic_xferack='1' and wrbuf_rnw='0')
else '0';
WRITE_BUF: entity opb_v20_v1_10_d.write_buffer
generic map ( C_INCLUDE_OPBIN_PSTAGE => INCLUDE_OPBIN_PSTAGE,
C_INCLUDE_IPIC_PSTAGE => INCLUDE_IPIC_PSTAGE,
C_INCLUDE_OPBOUT_PSTAGE => INCLUDE_OPBOUT_PSTAGE,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_WRBUF_DEPTH => WRBUF_DEPTH,
C_NUM_CES => NUM_CES,
C_NUM_ARDS => NUM_ARDS
)
port map (
Bus_reset => bus2ip_reset_i,
Bus_clk => bus2ip_clk_i,
Data_in => bus2ip_data_s0,
CE => bus2ip_ce_s0,
Wr_CE => bus2ip_wrce_s0,
Rd_CE => bus2ip_rdce_s0,
RNW => opb_rnw_s0,
CS_hit => bus2ip_cs_hit_s0,
CS => bus2ip_cs_s0,
CS_enable => bus2ip_cs_enable_s0,
Burst => opb_seqaddr_s0,
Xfer_start => opb_xfer_start,
Xfer_done => opb_xfer_done,
Addr_ack => wrbuf_addrack,
Wrdata_ack => wrdata_ack,
WrBuf_data => wrbuf_data,
WrBuf_burst => wrbuf_burst,
WrBuf_xferack => wrbuf_xferack,
WrBuf_errack => wrbuf_errack,
WrBuf_retry => wrbuf_retry,
WrBuf_CS => wrbuf_cs,
WrBuf_RNW => wrbuf_rnw,
WrBuf_CE => wrbuf_ce,
WrBuf_WrCE => wrbuf_wrce,
WrBuf_RdCE => wrbuf_rdce,
WrBuf_Empty => wrbuf_empty,
WrBuf_AddrCnt_en => wrbuf_addrcntr_en,
WrBuf_AddrCntr_rst => wrbuf_addrcntr_rst,
WrBuf_AddrValid => wrbuf_addrvalid,
IPIC_Pstage_CE => ipic_pstage_ce
);
-- inclusion of write buffer requires the BEs to be registered
BE_REG_PROC : process(bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if bus2ip_reset_i = '1' then
wrbuf_be <= (others => '0');
else
wrbuf_be <= opb_be_cntr_steer;
end if;
end if;
end process BE_REG_PROC;
end generate WRITE_BUFFER_GEN;
NO_WRITE_BUFFER_GEN: if C_INCLUDE_WR_BUF = 0 generate
begin
wrbuf_data <= bus2ip_data_s0;
wrbuf_burst <= opb_seqaddr_s0;
wrbuf_xferack <= '0';
wrbuf_errack <= '0';
wrbuf_retry <= '0';
wrbuf_cs <= bus2ip_cs_s0;
wrbuf_rnw <= opb_rnw_s0;
wrbuf_ce <= bus2ip_ce_s0;
wrbuf_wrce <= bus2ip_wrce_s0;
wrbuf_rdce <= bus2ip_rdce_s0;
wrbuf_empty <= '1';
wrbuf_addrcntr_en <= '1';
wrbuf_addrcntr_rst <= '0';
wrbuf_addrvalid <= or_reduce(bus2ip_ce_s0);
wrbuf_be <= opb_be_cntr_steer;
ipic_pstage_ce <= '1';
end generate NO_WRITE_BUFFER_GEN;
------------------------------------------------------------------------------
-- Generation of per-address-range mechanism.
------------------------------------------------------------------------------
PER_AR_GEN: for i in 0 to NUM_ARDS-1 generate
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,i);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= log2(C_ARD_NUM_CE_ARRAY(i));
constant OFFSET : integer
:= log2(C_ARD_DWIDTH_ARRAY(i)/8);
-- OFFSET gives the number of address bits corresponding to the
-- DWIDTH of the address range, e.g. zero for bytes, 1 for
-- doublets, 2 for quadlets, 3 for octlets, etc.
begin
--------------------------------------------------------------------------
-- CS decoders
--------------------------------------------------------------------------
CS_I: entity opb_v20_v1_10_d.pselect
generic map (
C_AB => - K_DEV_ADDR_DECODE_WIDTH
+ num_decode_bits(C_ARD_ADDR_RANGE_ARRAY,
C_OPB_AWIDTH,
i),
C_AW => C_OPB_AWIDTH - K_DEV_ADDR_DECODE_WIDTH,
C_BAR => C_ARD_ADDR_RANGE_ARRAY(i*2)
( C_ARD_ADDR_RANGE_ARRAY(0)'length
- C_OPB_AWIDTH
+ K_DEV_ADDR_DECODE_WIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length-1
)
)
port map (
-- A => opb_abus_s0(K_DEV_ADDR_DECODE_WIDTH to C_OPB_AWIDTH-1),
-- AValid => devicesel_s0, --NEW GB
-- CS => bus2ip_cs_hit_s0(i)
A => opb_abus(K_DEV_ADDR_DECODE_WIDTH to C_OPB_AWIDTH-1), -- GAB 10/12/05
AValid => devicesel, -- GAB 10/12/05
CS => bus2ip_cs_hit(i) -- GAB 10/12/05
);
--
-- ToDo, pselect above and AND gate below can
-- be optimized later with a special pselect that
-- has outputs for both bus2ip_cs_s0 and bus2ip_cs_hit_s0.
--
-- GB - Removed check of postedwrinh when write buffer is instantiated. Write buffer
-- logic does not have postedwrinh implemented yet and this was causing a problem
-- with some of the configurations. When the write buffer is instantiated the
-- postedwrinh signal is ignored.
-- bus2ip_cs_enable_s0(i) <= not inh_cs_wnot_pw --GB
--
-- when C_DEV_BURST_ENABLE=0 or
--
-- (opb_seqaddr_s0 = '0'and opb_seqaddr_s0_d1 = '0') or
-- opb_rnw_s0 = '1' or
-- eff_ip2bus_val(
-- i =>i,
-- rst =>reset2bus_postedwrinh,
-- intr=>intr2bus_postedwrinh,
-- wrfifo=>'0',
-- rdfifo=>'0',
-- user=> ip2bus_postedwrinh(i)
-- --user=>ip2bus_postedwrinh
-- )='1'
-- else
-- not inh_cs_when_pw(i);
GEN_CS_ENABLE_NOWRBUF : if C_INCLUDE_WR_BUF = 0 generate --GB
bus2ip_cs_enable_s0(i) <= not(inh_cs_wnot_pw)
when opb_rnw_s0 = '1'
or eff_ip2bus_val(
i => i,
rst => reset2bus_postedwrinh,
intr => intr2bus_postedwrinh,
wrfifo => '0',
rdfifo => '0',
-- user => ip2bus_postedwrinh(i)
user => (ip2bus_postedwrinh_s2_d1(i)
and bo2sl(INCLUDE_OPBIN_PSTAGE))
or (ip2bus_postedwrinh_s2(i)
and bo2sl(not INCLUDE_OPBIN_PSTAGE))
)='1'
else not(inh_cs_when_pw(i));
end generate GEN_CS_ENABLE_NOWRBUF;
GEN_CS_ENABLE_WRBUF : if C_INCLUDE_WR_BUF = 1 generate --GB
bus2ip_cs_enable_s0(i) <= not inh_cs_wnot_pw
when C_DEV_BURST_ENABLE=0
or (opb_seqaddr_s0 = '0'
and opb_seqaddr_s0_d1 = '0')
or opb_rnw_s0 = '1'
else not inh_cs_when_pw(i);
end generate GEN_CS_ENABLE_WRBUF;
bus2ip_cs_s0(i) <= bus2ip_cs_hit_s0(i) and bus2ip_cs_enable_s0(i);
-------------------------------------------------------------------------
-- Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(i) - 1 generate
begin
----------------------------------------------------------------------
-- CE decoders
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1)
:= std_logic_vector(TO_UNSIGNED(j, CE_ADDR_SIZE));
begin
CE_I : entity opb_v20_v1_10_d.pselect
generic map (
C_AB => CE_ADDR_SIZE,
C_AW => CE_ADDR_SIZE,
C_BAR => BAR
)
port map (
A => next_opb_addr_cntr_out(C_OPB_AWIDTH - OFFSET - CE_ADDR_SIZE to
C_OPB_AWIDTH - OFFSET - 1),
AValid => bus2ip_cs_s0(i),
CS => bus2ip_ce_s0(CE_INDEX_START+j)
);
end generate;
--
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
bus2ip_ce_s0(CE_INDEX_START+j) <= bus2ip_cs_s0(i);
end generate;
--
----------------------------------------------------------------------
-- RdCE decoders
----------------------------------------------------------------------
bus2ip_rdce_s0(CE_INDEX_START+j) <=
bus2ip_ce_s0(CE_INDEX_START+j) and opb_rnw_s0;
----------------------------------------------------------------------
-- WrCE decoders
----------------------------------------------------------------------
bus2ip_wrce_s0(CE_INDEX_START+j) <=
bus2ip_ce_s0(CE_INDEX_START+j) and not opb_rnw_s0;
----------------------------------------------------------------------
end generate PER_CE_GEN;
end generate PER_AR_GEN;
------------------------------------------------------------------------
-- Master Abort Detection --GB
------------------------------------------------------------------------
-- This process detects when an abort occurs from the master.
-- and is used to gate off sln_xferack and sln_retry from the bus
--
GEN_ABORTS_FOR_1_3_7 : if (INCLUDE_OPBIN_PSTAGE and not (INCLUDE_OPBOUT_PSTAGE))
or (INCLUDE_OPBIN_PSTAGE and INCLUDE_IPIC_PSTAGE) generate
ABORT_DET : process(bus2ip_clk_i)
begin
if(bus2ip_clk_i'EVENT and bus2ip_clk_i='1')then
if(Reset = '1' or last_xferack_d1 = '1'
or or_reduce(bus2ip_cs_hit_s0) = '0' or sln_retry_s2 = '1')then
cycle_active <= '0';
elsif(or_reduce(bus2ip_cs_hit_s0) = '1' and sln_retry_s2 = '0')then
cycle_active <= '1';
end if;
cycle_abort_d1 <= cycle_abort;
end if;
end process ABORT_DET;
cycle_abort <= '1' when ( cycle_active = '1'
and or_reduce(bus2ip_cs_hit_s0) = '0'
and last_xferack_d1 = '0')
else '0';
GEN_XFERABORT_FOR_1_3 : if INCLUDE_OPBIN_PSTAGE and not(INCLUDE_OPBOUT_PSTAGE) generate
xfer_abort <= cycle_abort or cycle_abort_d1;
end generate;
GEN_XFERABORT_FOR_REST : if not(INCLUDE_OPBIN_PSTAGE) or INCLUDE_OPBOUT_PSTAGE generate
xfer_abort <= cycle_abort;
end generate;
end generate GEN_ABORTS_FOR_1_3_7;
-- Abort logic is not needed for pipeline models 0,2,4,5, and 6
GEN_NOABORTS_FOR_REST : if not(INCLUDE_OPBIN_PSTAGE)
or (not(INCLUDE_IPIC_PSTAGE) and INCLUDE_OPBOUT_PSTAGE) generate
begin
xfer_abort <= '0';
cycle_abort <= '0';
end generate GEN_NOABORTS_FOR_REST;
------------------------------------------------------------------------------
-- This process selects the set of CS signals that activate a given bit of the
-- encoded size.
------------------------------------------------------------------------------
ENCODE_SIZE_BIT_SEL_PROC : process (bus2ip_cs_s0)
type NAT_ARRAY_TYPE is array(natural range <>) of natural;
variable next_bit : NAT_ARRAY_TYPE(0 to 2);
begin
next_bit := (others => 0);
for i in 0 to NUM_ARDS-1 loop
for j in 0 to NUM_ENCODED_SIZE_BITS-1 loop
if encoded_size_is_1(i,j) then
cs_to_or_for_dsize_bit(j)(next_bit(j)) <= bus2ip_cs_s0(i);
next_bit(j) := next_bit(j)+1;
end if;
end loop;
end loop;
end process;
------------------------------------------------------------------------------
-- This generates the encoded data size as a function of the address range
-- being addressed.
------------------------------------------------------------------------------
ENCODED_SIZE_CS_OR_GEN : for i in 0 to NUM_ENCODED_SIZE_BITS-1 generate
begin
----------------------------------------------------------------------------
-- If no address range requires the bit high, then fix it low.
----------------------------------------------------------------------------
ALWAYS_LOW_GEN : if num_cs_for_bit(i) = 0 generate
encoded_dsize_s0(i) <= '0';
end generate;
----------------------------------------------------------------------------
-- If all address ranges require the bit high, then fix it high.
----------------------------------------------------------------------------
ALWAYS_HIGH_GEN: if num_cs_for_bit(i) = NUM_ARDS generate
encoded_dsize_s0(i) <= '1';
end generate;
----------------------------------------------------------------------------
-- If some address ranges require the bit high, and other address ranges
-- require it low, then OR together the CS signals for the address ranges
-- that require it high.
----------------------------------------------------------------------------
SOMETIMES_HIGH_GEN: if num_cs_for_bit(i) /= 0
and num_cs_for_bit(i) /= NUM_ARDS generate
-- instance of carry-chain OR for each bit
ENCODED_SIZE_OR : entity opb_v20_v1_10_d.or_muxcy
generic map (
C_NUM_BITS => num_cs_for_bit(i)
)
port map (
In_bus => cs_to_or_for_dsize_bit(i)(0 to num_cs_for_bit(i)-1),
Or_out => encoded_dsize_s0(i)
);
end generate;
end generate;
------------------------------------------------------------------------------
-- Steer write data from appropriate data lanes if C_ARD_DWIDTH_ARRAY has
-- mixed width values.
-- this steering module is used to steer the write data and BEs before the
-- write buffer
------------------------------------------------------------------------------
I_STEER_DATA : entity opb_v20_v1_10_d.IPIF_Steer
generic map(
C_DWIDTH => C_OPB_DWIDTH,
C_SMALLEST => get_min_dwidth(C_ARD_DWIDTH_ARRAY),
C_AWIDTH => C_OPB_AWIDTH
)
port map (
Wr_Data_In => opb_dbus_s0,
Addr => opb_abus_s0,
BE_In => opb_be_s0,
Decode_size => encoded_dsize_s0,
Wr_Data_Out => bus2ip_data_s0,
BE_Out => open,
--
-- Rd mirroring tied off, see I_MIRROR
Rd_Data_In => ZSLV(0 to C_OPB_DWIDTH-1),
Rd_Data_Out => open
);
------------------------------------------------------------------------------
-- Steer byte enables from appropriate data lanes if C_ARD_DWIDTH_ARRAY has
-- mixed width values.
-- this steering module is used to steer the byte enables output from
-- the address counter/be generator during reads
------------------------------------------------------------------------------
I_STEER_BE : entity opb_v20_v1_10_d.IPIF_Steer
generic map(
C_DWIDTH => C_OPB_DWIDTH,
C_SMALLEST => get_min_dwidth(C_ARD_DWIDTH_ARRAY),
C_AWIDTH => C_OPB_AWIDTH
)
port map (
Wr_Data_In => ZSLV(0 to C_OPB_DWIDTH-1),
Addr => next_steer_addr_cntr_out,
BE_In => opb_be_cntr_out,
Decode_size => encoded_dsize_s0,
Wr_Data_Out => open,
BE_Out => opb_be_cntr_steer,
--
-- Rd mirroring tied off, see I_MIRROR
Rd_Data_In => ZSLV(0 to C_OPB_DWIDTH-1),
Rd_Data_Out => open
);
------------------------------------------------------------------------------
-- Mirror read data to appropriate data lanes if C_ARD_DWIDTH_ARRAY has
-- mixed width values.
------------------------------------------------------------------------------
I_MIRROR : entity opb_v20_v1_10_d.IPIF_Steer
generic map(
C_DWIDTH => C_OPB_DWIDTH,
C_SMALLEST => get_min_dwidth(C_ARD_DWIDTH_ARRAY),
C_AWIDTH => C_OPB_AWIDTH
)
port map (
Rd_Data_In => ip2bus_data_mx,
Decode_size => encoded_dsize_s1,
--Addr => bus2ip_addr_s1,
Addr => steer_addr_cntr_out,
Rd_Data_Out => sln_dbus_s1,
--
-- Wr steering tied off, see I_STEER
Wr_Data_In => ZSLV(0 to C_OPB_DWIDTH-1),
BE_In => ZSLV(0 to C_OPB_DWIDTH/8-1),
Wr_Data_Out => open,
BE_Out => open
);
-- Generate for pipeline model 0, 2, 4, 6
IP2BUS_XFERACK_0_2_GEN : if not(INCLUDE_OPBIN_PSTAGE) generate
------------------------------------------------------------------------------
-- For inhibiting of posted writes IP2Bus_Ack needs to be gated off for 1
-- clocks during dynamic changes in the ip2bus_postedwrinh signal. During
-- reads and when the write buffer is instantiated simply pass IP2Bus_Ack
-- without gating it off.
------------------------------------------------------------------------------
-- GB
IP2BUS_XFERACK_PROC : process(bus2ip_cs_s1,IP2Bus_Ack,opb_rnw_s0,
ip2bus_postedwrinh_s2_d1)
variable r : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
r := r or (IP2Bus_Ack and bus2ip_cs_s1(i)
and
( (ip2bus_postedwrinh_s2_d1(i) and not(opb_rnw_s0))
or (opb_rnw_s0)
or (bo2sl(C_INCLUDE_WR_BUF=1))
));
end loop;
ip2bus_xferack <= r;
end process IP2BUS_XFERACK_PROC;
end generate;
-- Generate for pipeline model 1,3,5,and 7
IP2BUS_XFERACK_REST_GEN : if INCLUDE_OPBIN_PSTAGE generate
------------------------------------------------------------------------------
-- For inhibiting of posted writes IP2Bus_Ack needs to be gated off for 2
-- clocks during dynamic changes in the ip2bus_postedwrinh signal. During
-- reads and when the write buffer is instantiated simply pass IP2Bus_Ack
-- without gating it off.
------------------------------------------------------------------------------
-- GB
IP2BUS_XFERACK_PROC : process(bus2ip_cs_s1,IP2Bus_Ack,opb_rnw_s0,
ip2bus_postedwrinh_s2_d2)
variable r : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
r := r or (IP2Bus_Ack and bus2ip_cs_s1(i)
and
( (ip2bus_postedwrinh_s2_d2(i) and not(opb_rnw_s0))
or (opb_rnw_s0)
or (bo2sl(C_INCLUDE_WR_BUF=1))
));
end loop;
ip2bus_xferack <= r;
end process IP2BUS_XFERACK_PROC;
end generate;
------------------------------------------------------------------------------
-- Generation of sln_xferack.
-- ALS - modified to include read and write FIFOs
-- ALS - modified to include write buffer
------------------------------------------------------------------------------
IPIC_XFERACK_PROC : process (bus2ip_cs_s1, bus2ip_cs_hit_s0,
opb_rnw_s0, ip2bus_xferack,
reset2bus_ack, intr2bus_ack,
reset2bus_postedwrinh, intr2bus_postedwrinh,
wrfifo_ack, rdfifo_ack,ip2bus_postedwrinh_s2_d2,
IP2Bus_PostedWrInh) is
variable r : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
if (
-- GB - Removed check of postedwrinh when write buffer is instantiated. Write buffer
-- logic does not have postedwrinh implemented yet and this was causing a problem
-- with some of the configurations. When the write buffer is instantiated the
-- postedwrinh signal is ignored.
(bo2sl(C_INCLUDE_WR_BUF=0)
and eff_ip2bus_val(i => i,
rst => reset2bus_postedwrinh,
intr => intr2bus_postedwrinh,
wrfifo => '0',
rdfifo => '0',
user => IP2Bus_PostedWrInh(i))
)
or opb_rnw_s0
or bo2sl(C_INCLUDE_WR_BUF=1)) = '1' then
-- This is the case where transactions are reads, or writes
-- that are not posted or write buffer is included
r := r or (bus2ip_cs_s1(i)
and eff_ip2bus_val(i => i,
rst => reset2bus_ack,
intr => intr2bus_ack,
wrfifo => wrfifo_ack,
rdfifo => rdfifo_ack,
user => ip2bus_xferack --GB
));
else
-- posted writes, but no write buffer is included
r := r or bus2ip_cs_hit_s0(i);
end if;
end loop;
ipic_xferack <= r ;
end process ;
SLN_XFERACK_PROC : process (ipic_xferack, wrbuf_xferack, bus2ip_rnw_s1,
inh_xferack_when_pw , inh_xferack_when_burst_rd ) is
begin
if bus2ip_rnw_s1 = '0' then
if C_INCLUDE_WR_BUF = 1 then
sln_xferack_s1 <= wrbuf_xferack and not(inh_xferack_when_pw);
else
sln_xferack_s1 <= ipic_xferack and not (inh_xferack_when_pw);
end if;
else
sln_xferack_s1 <= ipic_xferack and not (inh_xferack_when_burst_rd);
end if;
end process SLN_XFERACK_PROC;
------------------------------------------------------------------------------
-- Generation of sln_retry.
-- ALS - modified to include read and write FIFOs
-- ALS - modified to include write buffer
------------------------------------------------------------------------------
SLN_RETRY_PROC : process (bus2ip_cs_s1, IP2Bus_Retry, reset2bus_retry,
intr2bus_retry,rfifo_retry, wfifo_retry,
wrbuf_retry, bus2ip_rnw_s1) is
variable r : std_logic;
variable ip2bus_retry_help : std_logic;
begin
if C_INCLUDE_WR_BUF = 1 and bus2ip_rnw_s1 = '0' then
-- write buffer generates Retry during write transfers
sln_retry_s1 <= wrbuf_retry;
else
r := '0';
for i in bus2ip_cs_s1'range loop
if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
ip2bus_retry_help := reset2bus_retry;
elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
ip2bus_retry_help := intr2bus_retry;
elsif INCLUDE_RDFIFO and ((i = RDFIFO_DATA_CS_IDX) or (i = RDFIFO_REG_CS_IDX)) then
ip2bus_retry_help := rfifo_retry;
elsif INCLUDE_WRFIFO and ((i = WRFIFO_DATA_CS_IDX) or (i = WRFIFO_REG_CS_IDX)) then
ip2bus_retry_help := wfifo_retry;
else
ip2bus_retry_help := IP2Bus_Retry;
end if;
r := r or (bus2ip_cs_s1(i) and ip2bus_retry_help);
end loop;
sln_retry_s1 <= r;
end if;
end process;
------------------------------------------------------------------------------
-- Generation of sln_error.
-- ALS - modified to include read and write FIFOs
-- ALS - modified to include write buffer
------------------------------------------------------------------------------
SLN_ERRACK_PROC : process (bus2ip_cs_s1, IP2Bus_Error, reset2bus_error,
intr2bus_error, rfifo_error, wfifo_error,
wrbuf_errack, bus2ip_rnw_s1) is
variable r : std_logic;
variable ip2bus_error_help : std_logic;
begin
if C_INCLUDE_WR_BUF = 1 and bus2ip_rnw_s1 = '0' then
-- write buffer generates ErrAck during write transfers
sln_errack_s1 <= wrbuf_errack;
else
r := '0';
for i in bus2ip_cs_s1'range loop
if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
ip2bus_error_help := reset2bus_error;
elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
ip2bus_error_help := intr2bus_error;
elsif INCLUDE_RDFIFO and ((i = RDFIFO_DATA_CS_IDX) or (i = RDFIFO_REG_CS_IDX)) then
ip2bus_error_help := rfifo_error;
elsif INCLUDE_WRFIFO and ((i = WRFIFO_DATA_CS_IDX) or (i = WRFIFO_REG_CS_IDX)) then
ip2bus_error_help := wfifo_error;
else
ip2bus_error_help := IP2Bus_Error;
end if;
r := r or (bus2ip_cs_s1(i) and ip2bus_error_help);
end loop;
sln_errack_s1 <= r;
end if;
end process;
------------------------------------------------------------------------------
-- Generation of sln_toutsup.
-- ALS - modified to include read and write FIFOs
------------------------------------------------------------------------------
SLN_TOUTSUP_PROC : process (bus2ip_cs_s1, IP2Bus_ToutSup, reset2bus_toutsup,
intr2bus_toutsup, rfifo_toutsup, wfifo_toutsup) is
variable r : std_logic;
variable ip2bus_toutsup_help : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
ip2bus_toutsup_help := reset2bus_toutsup;
elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
ip2bus_toutsup_help := intr2bus_toutsup;
elsif INCLUDE_RDFIFO and ((i = RDFIFO_DATA_CS_IDX) or (i = RDFIFO_REG_CS_IDX)) then
ip2bus_toutsup_help := rfifo_toutsup;
elsif INCLUDE_WRFIFO and ((i = WRFIFO_DATA_CS_IDX) or (i = WRFIFO_REG_CS_IDX)) then
ip2bus_toutsup_help := wfifo_toutsup;
else
ip2bus_toutsup_help := IP2Bus_ToutSup;
end if;
r := r or (bus2ip_cs_s1(i) and ip2bus_toutsup_help);
end loop;
sln_toutsup_s1 <= r;
end process;
------------------------------------------------------------------------------
-- Generation of ip2bus_data_mx, as a function of IP2Bus_Data
-- and bus2ip_rdce, using carry chain logic.
-- Note, internal address ranges such as RESET_MIR or Interrupt Source
-- controller are multiplexed into the appropriate "slot".
------------------------------------------------------------------------------
-- READMUX_GEN : if not SINGLE_CE generate
-- begin
-- READMUX_PROCESS: process(bus2ip_rdce_s1,
-- reset2bus_data,
-- intr2bus_data,
-- rdfifo2bus_data,
-- wrfifo2bus_data,
-- ip2bus_data)
-- begin
-- ip2bus_data_mx <= (others => '0');
-- for i in bus2ip_cs_s1'range loop
-- if bus2ip_cs_s1(i) = '1' then
-- if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
-- ip2bus_data_mx <= reset2bus_data;
-- elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
-- ip2bus_data_mx <= intr2bus_data;
-- elsif INCLUDE_RDFIFO and ((i = RDFIFO_DATA_CS_IDX)
-- or (i = RDFIFO_REG_CS_IDX)) then
-- ip2bus_data_mx <= rdfifo2bus_data;
-- elsif INCLUDE_WRFIFO and ((i = WRFIFO_DATA_CS_IDX)
-- or (i = WRFIFO_REG_CS_IDX)) then
-- ip2bus_data_mx <= wrfifo2bus_data;
-- else
-- ip2bus_data_mx <= ip2bus_data;
-- end if;
-- end if;
-- end loop;
-- end process READMUX_PROCESS;
-- end generate;
READMUX_GEN : if not SINGLE_CE generate
begin
READMUX_PROCESS: process(reset2bus_data,
intr2bus_data,
rdfifo2bus_data,
wrfifo2bus_data,
ip2bus_data)
begin
for i in ip2bus_data_mx'range loop
ip2bus_data_mx(i) <= reset2bus_data(i)
or intr2bus_data(i)
or rdfifo2bus_data(i)
or wrfifo2bus_data(i)
or ip2bus_data(i);
end loop;
end process READMUX_PROCESS;
end generate;
READMUX_SINGLE_CE_GEN : if SINGLE_CE generate
begin
ip2bus_data_mx <= ip2bus_data;
end generate;
-- PER_BIT_GEN : for i in 0 to C_OPB_DWIDTH-1 generate
-- signal cry : std_logic_vector(0 to (Bus2IP_RdCE'length + 1)/2);
-- begin
-- cry(0) <= '0';
-- PER_CE_PAIR_GEN : for j in 0 to (Bus2IP_RdCE'length + 1)/2-1 generate
-- signal ip2bus_data_rmmx0 : std_logic;
-- signal ip2bus_data_rmmx1 : std_logic;
-- signal lut_out : std_logic;
-- constant nopad : boolean
-- := (j /= (Bus2IP_RdCE'length + 1)/2-1)
-- or (Bus2IP_RdCE'length mod 2 = 0);
-- begin
-- -----------------------------------------------------------------------
-- -- ToDo, the read-back mux can be optimized to exclude any data bits
-- -- that are not present in AR with DWIDTH less than C_OPB_DWIDTH...
-- -- possibly also for bits that are known to be not implemented, e.g.
-- -- a register that doesn't use all bit positions or is write-only.
-- -----------------------------------------------------------------------
-- -- LUT (last LUT may multiplex one data bit instead of two)
-- -----------------------------------------------------------------------
---- WOPAD : if nopad generate
---- signal ip2bus_data_rmmx0 : std_logic_vector(0 to C_OPB_DWIDTH-1);
---- signal ip2bus_data_rmmx1 : std_logic_vector(0 to C_OPB_DWIDTH-1);
---- begin
-- -------------------------------------------------------------------
-- -- Always include the first of two possilble mux channels thru LUT.
-- -------------------------------------------------------------------
-- ip2bus_data_rmmx0 <=
-- ----------------------------------------------
-- -- RESET_MIR
-- ----------------------------------------------
-- reset2bus_data(i)
-- when INCLUDE_RESET_MIR and
-- (2*j = RESET_MIR_CE_IDX)
-- else
-- ----------------------------------------------
-- -- INTR -- ToDo, this is inefficient because
-- -- interrupt_control already multiplexes
-- -- the data. Optimize later.
-- ----------------------------------------------
-- intr2bus_data(i)
-- when INCLUDE_INTR and
-- (2*j >= INTR_CE_LO) and
-- (2*j <= INTR_CE_HI)
-- else
-- ----------------------------------------------
-- -- Read FIFO
-- ----------------------------------------------
-- rdfifo2bus_data(i)
-- when INCLUDE_RDFIFO and (
-- ((2*j >= RFIFO_REG_CE_LO) and (2*j <= RFIFO_REG_CE_HI))
-- or
-- (2*j = RFIFO_DATA_CE) )
-- else
-- ----------------------------------------------
-- -- Write FIFO
-- ----------------------------------------------
-- wrfifo2bus_data(i)
-- when INCLUDE_WRFIFO and (
-- ((2*j >= WFIFO_REG_CE_LO) and (2*j <= WFIFO_REG_CE_HI))
-- or
-- (2*j = WFIFO_DATA_CE) )
-- else
-- ----------------------------------------------
-- -- IP Core
-- ----------------------------------------------
-- --IP2Bus_Data((2*j )*C_OPB_DWIDTH + i);
-- IP2Bus_Data(i);
-- -------------------------------------------------------------------
-- -- Don't include second channel when odd number and on last LUT.
-- -------------------------------------------------------------------
-- WOPAD : if nopad generate
-- begin
-- ip2bus_data_rmmx1 <=
-- ----------------------------------------------
-- -- RESET_MIR
-- ----------------------------------------------
-- reset2bus_data(i)
-- when INCLUDE_RESET_MIR and
-- (2*j+1 = RESET_MIR_CE_IDX)
-- else
-- ----------------------------------------------
-- -- INTR
-- ----------------------------------------------
-- intr2bus_data(i)
-- when INCLUDE_INTR and
-- (2*j+1 >= INTR_CE_LO) and
-- (2*j+1 <= INTR_CE_HI)
-- else
-- ----------------------------------------------
-- -- Read FIFO
-- ----------------------------------------------
-- rdfifo2bus_data(i)
-- when INCLUDE_RDFIFO and (
-- ((2*j+1 >= RFIFO_REG_CE_LO) and (2*j+1 <= RFIFO_REG_CE_HI))
-- or
-- (2*j+1 = RFIFO_DATA_CE) )
-- else
-- ----------------------------------------------
-- -- Write FIFO
-- ----------------------------------------------
-- wrfifo2bus_data(i)
-- when INCLUDE_WRFIFO and (
-- ((2*j+1 >= WFIFO_REG_CE_LO) and (2*j+1 <= WFIFO_REG_CE_HI))
-- or
-- (2*j+1 = WFIFO_DATA_CE) )
-- else
-- ----------------------------------------------
-- -- IP Core
-- ----------------------------------------------
-- --IP2Bus_Data((2*j+1)*C_OPB_DWIDTH + i);
-- IP2Bus_Data(i);
-- --lut_out <= not (
-- -- (ip2bus_data_rmmx0(i) and bus2ip_rdce_s1(2*j )) or
-- -- (ip2bus_data_rmmx1(i) and bus2ip_rdce_s1(2*j+1)));
-- lut_out <= not (
-- (ip2bus_data_rmmx0 and bus2ip_rdce_s1(2*j )) or
-- (ip2bus_data_rmmx1 and bus2ip_rdce_s1(2*j+1)));
-- end generate;
-- WIPAD : if not nopad generate
-- lut_out <= not (
-- (ip2bus_data_rmmx0 and bus2ip_rdce_s1(2*j )));
-- end generate;
-- -----------------------------------------------------------------------
-- -- MUXCY
-- -----------------------------------------------------------------------
-- I_MUXCY : MUXCY
-- port map (
-- O => cry(j+1),
-- CI => cry(j),
-- DI => '1',
-- S => lut_out
-- );
-- end generate;
-- ip2bus_data_mx(i) <= cry((Bus2IP_RdCE'length + 1)/2);
-- end generate;
-- end generate;
--
--
-- READMUX_SINGLE_CE_GEN : if SINGLE_CE and INCLUDE_OPBOUT_PSTAGE generate
-- begin
-- ip2bus_data_mx <= ip2bus_data;
-- end generate;
-------------------------------------------------------------------------------
-- Reset/MIR
-------------------------------------------------------------------------------
INCLUDE_RESET_MIR_GEN : if INCLUDE_RESET_MIR generate
begin
RESET_MIR_I0 : entity opb_v20_v1_10_d.reset_mir
Generic map (
C_DWIDTH => C_OPB_DWIDTH,
C_INCLUDE_SW_RST => 1,
C_INCLUDE_MIR => C_DEV_MIR_ENABLE,
C_MIR_MAJOR_VERSION => MIR_MAJOR_VERSION,
C_MIR_MINOR_VERSION => MIR_MINOR_VERSION,
C_MIR_REVISION => MIR_REVISION,
C_MIR_BLK_ID => C_DEV_BLK_ID,
C_MIR_TYPE => MIR_TYPE
)
port map (
Reset => Reset,
Bus2IP_Clk => bus2ip_clk_i,
SW_Reset_WrCE => bus2ip_wrce_s1(RESET_MIR_CE_IDX),
SW_Reset_RdCE => bus2ip_rdce_s1(RESET_MIR_CE_IDX),
Bus2IP_Data => bus2ip_data_s1,
Bus2IP_Reset => bus2ip_reset_i,
Reset2Bus_Data => reset2bus_data,
Reset2Bus_Ack => reset2bus_ack,
Reset2Bus_Error => reset2bus_error,
Reset2Bus_Retry => reset2bus_retry,
Reset2Bus_ToutSup => reset2bus_toutsup
);
end generate;
EXCLUDE_RESET_MIR_GEN : if not INCLUDE_RESET_MIR generate
begin
bus2ip_reset_i <= Reset;
reset2bus_data <= (others => '0');
reset2bus_ack <= '0';
reset2bus_error <= '0';
reset2bus_retry <= '0';
reset2bus_toutsup <= '0';
end generate;
Bus2IP_Reset <= bus2ip_reset_i;
-------------------------------------------------------------------------------
-- Interrupts
-- ALS - added interrupts from Read and Write FIFOs
-- ALS - added code to allow C_INCLUDE_DEV_ISC and C_INCLUDE_DEV_PENCODER to
-- come from dependent props array
-------------------------------------------------------------------------------
INTR_CTRLR_GEN : if INCLUDE_INTR generate
constant NUM_IPIF_IRPT_SRC : natural := 4;
constant INTR_INDEX : integer :=
get_id_index(C_ARD_ID_ARRAY, IPIF_INTR);
signal errack_reserved: std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector( 0 to NUM_IPIF_IRPT_SRC-1);
begin
errack_reserved <= Sln_errack_s2 & '0';
ipif_lvl_interrupts(0) <= '0'; -- assign to DMA2Intr_Intr(0) when DMA is added
ipif_lvl_interrupts(1) <= '0'; -- assign to DMA2Intr_Intr(1) when DMA is added
ipif_lvl_interrupts(2) <= rdfifo2intr_deadlock; -- = '0' if FIFOs not included
ipif_lvl_interrupts(3) <= wrfifo2intr_deadlock; -- = '0' if FIFOs not included
INTERRUPT_CONTROL_I : entity opb_v20_v1_10_d.interrupt_control
generic map (
C_INTERRUPT_REG_NUM => number_CEs_for(IPIF_INTR),
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => C_ARD_DEPENDENT_PROPS_ARRAY
(INTR_INDEX)(INCLUDE_DEV_PENCODER)=1,
C_INCLUDE_DEV_ISC => C_ARD_DEPENDENT_PROPS_ARRAY
(INTR_INDEX)(EXCLUDE_DEV_ISC)=0,
C_IRPT_DBUS_WIDTH => C_OPB_DWIDTH
)
port map (
Bus2IP_Clk_i => bus2ip_clk_i,
Bus2IP_Data_sa => bus2ip_data_s1,
Bus2IP_RdReq_sa => '0',
Bus2IP_Reset_i => bus2ip_reset_i,
Bus2IP_WrReq_sa => '0',
Interrupt_RdCE => bus2ip_rdce_s1(INTR_CE_LO to INTR_CE_HI),
Interrupt_WrCE => bus2ip_wrce_s1(INTR_CE_LO to INTR_CE_HI),
IPIF_Reg_Interrupts => errack_reserved,
-- ALS - modified to connect read and write FIFO interrupts
--IPIF_Lvl_Interrupts => ZERO_SLV(0 to NUM_IPIF_IRPT_SRC-1),
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
IP2Bus_IntrEvent => IP2Bus_IntrEvent,
Intr2Bus_DevIntr => IP2INTC_Irpt,
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error, -- These are tied low in block
Intr2Bus_Retry => intr2bus_retry, --
Intr2Bus_ToutSup => intr2bus_toutsup --
);
end generate;
REMOVE_INTERRUPT : if (not INCLUDE_INTR) generate
intr2bus_data <= (others => '0');
IP2INTC_Irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_retry <= '0';
intr2bus_toutsup <= '0';
intr2bus_wrack <= '0';
end generate REMOVE_INTERRUPT;
intr2bus_ack <= intr2bus_rdack or intr2bus_wrack;
-------------------------------------------------------------------------------
-- RDREQ_WRREQ Generation if FIFOs are included
-------------------------------------------------------------------------------
NO_RDREQ_WRREQ_GEN: if not(INCLUDE_RDFIFO) and not(INCLUDE_WRFIFO) generate
bus2ip_rdreq_s0 <= '0';
bus2ip_wrreq_s0 <= '0';
end generate NO_RDREQ_WRREQ_GEN;
GEN_RDREQ_WREQ: if ((INCLUDE_RDFIFO) or (INCLUDE_WRFIFO)) generate
-- only 4 possible CS for FIFOs, size vector accordingly
signal fifo_cs : std_logic_vector(0 to 3);
signal any_fifo_cs : std_logic;
begin
-----------------------------------------------------------------------------
-- ALS - added process to generate read and write request
-- Generation of Bus2IP_RdReq and Bus2IP_WrReq stage 0 signals
-- These stage 0 signals will follow the pipeline models and generate statements
-- so that the appropriate stage 1 signal is created.
--
-- MODIFIED: 01/24/04 to be for any CS, not just FIFO CS - also
-- these signals will be qualified with ADDR
-- These signals assert for any FIFO CS. They are 1-clock pulse wide for single
-- transfers and stay asserted for burst transfers.
-----------------------------------------------------------------------------
GEN_PFIFOS_NO_WRBUF : if C_INCLUDE_WR_BUF = 0 generate
BOTHFIFOS_GEN: if INCLUDE_RDFIFO and INCLUDE_WRFIFO generate
fifo_cs <= bus2ip_cs_s0(RDFIFO_REG_CS_IDX) & bus2ip_cs_s0(RDFIFO_DATA_CS_IDX)
& bus2ip_cs_s0(WRFIFO_REG_CS_IDX) & bus2ip_cs_s0(WRFIFO_DATA_CS_IDX);
end generate BOTHFIFOS_GEN;
ONLY_RDFIFO_GEN: if INCLUDE_RDFIFO and not(INCLUDE_WRFIFO) generate
fifo_cs <= bus2ip_cs_s0(RDFIFO_REG_CS_IDX) & bus2ip_cs_s0(RDFIFO_DATA_CS_IDX)
& "00";
end generate ONLY_RDFIFO_GEN;
ONLY_WRFIFO_GEN: if INCLUDE_WRFIFO and not(INCLUDE_RDFIFO) generate
fifo_cs <= bus2ip_cs_s0(WRFIFO_REG_CS_IDX) & bus2ip_cs_s0(WRFIFO_DATA_CS_IDX)
& "00";
end generate ONLY_WRFIFO_GEN;
end generate;
GEN_PFIFOS_WITH_WRBUF : if C_INCLUDE_WR_BUF = 1 generate
BOTHFIFOS_GEN: if INCLUDE_RDFIFO and INCLUDE_WRFIFO generate
fifo_cs <= bus2ip_cs_s1(RDFIFO_REG_CS_IDX) & bus2ip_cs_s1(RDFIFO_DATA_CS_IDX)
& bus2ip_cs_s1(WRFIFO_REG_CS_IDX) & bus2ip_cs_s1(WRFIFO_DATA_CS_IDX);
end generate BOTHFIFOS_GEN;
ONLY_RDFIFO_GEN: if INCLUDE_RDFIFO and not(INCLUDE_WRFIFO) generate
fifo_cs <= bus2ip_cs_s1(RDFIFO_REG_CS_IDX) & bus2ip_cs_s1(RDFIFO_DATA_CS_IDX)
& "00";
end generate ONLY_RDFIFO_GEN;
ONLY_WRFIFO_GEN: if INCLUDE_WRFIFO and not(INCLUDE_RDFIFO) generate
fifo_cs <= bus2ip_cs_s1(WRFIFO_REG_CS_IDX) & bus2ip_cs_s1(WRFIFO_DATA_CS_IDX)
& "00";
end generate ONLY_WRFIFO_GEN;
end generate;
-- ToDo: see if LUT OR would be better here since max of 4 bits
ANYCS_OR_I: entity opb_v20_v1_10_d.or_muxcy
generic map (
C_NUM_BITS => 4
)
port map (
In_bus => fifo_cs,
Or_out => any_fifo_cs
);
-------------------------------------------------------------------------------
-- RDREQ_WRREQ Generation
-------------------------------------------------------------------------------
-- read request
rdreq <= '1'
when any_fifo_cs = '1' and opb_rnw_s0 = '1' and rdreq_hold = '0'
else '0';
-- hold the value of rdreq by setting a flop when rdreq asserts
-- this is used to gate off rdreq to keep it a one-clock pulse
rdreq_hold_rst <= (not(sln_xferack_s1) and (sln_xferack_s1_d1))
or sln_retry_s1
or not(opb_select_s0);
RDREQ_HOLD_FF: FDRE
port map (
Q => rdreq_hold, --[out]
C => bus2ip_clk_i, --[in]
CE=> rdreq, --[in]
D => '1', --[in]
R => rdreq_hold_rst --[in]
);
RDREQ_PIPE0_GEN: if C_PIPELINE_MODEL=0 generate
begin
-- need to extend read req 1 clock after sequential address
bus2ip_rdreq_s0 <= rdreq or (opb_seqaddr_s0_d1 and opb_rnw_s0);
end generate RDREQ_PIPE0_GEN;
RDREQ_PIPE_NOT0_GEN: if C_PIPELINE_MODEL /= 0 generate
-- generate bus2ip_rdreq by OR'ing the single pulse request with the burst
-- signal
bus2ip_rdreq_s0 <= rdreq or (opb_seqaddr_s0 and opb_rnw_s0);
end generate RDREQ_PIPE_NOT0_GEN;
WRREQ_GEN_FOR_PIPE_0_1 : if C_PIPELINE_MODEL = 0
or C_PIPELINE_MODEL = 1 generate
wrreq <= '1'
when any_fifo_cs = '1' and opb_rnw_s0 = '0'
else '0';
end generate WRREQ_GEN_FOR_PIPE_0_1;
WRREQ_GEN_FOR_REST : if C_PIPELINE_MODEL /= 0
and C_PIPELINE_MODEL /= 1 generate
-- write request
wrreq <= '1'
when any_fifo_cs = '1' and opb_rnw_s0 = '0' and wrreq_hold='0'
else '0';
-- hold the value of wrreq by setting a flop when wrreq asserts
-- this is used to gate off wrreq to keep it a one-clock pulse
wrreq_hold_rst <= (not(sln_xferack_s1) and (sln_xferack_s1_d1))
or sln_retry_s1
or not(opb_select_s0);
WRREQ_HOLD_FF: FDRE
port map (
Q => wrreq_hold, --[out]
C => bus2ip_clk_i, --[in]
CE=> wrreq, --[in]
D => '1', --[in]
R => wrreq_hold_rst --[in]
);
end generate WRREQ_GEN_FOR_REST;
-- generate bus2ip_wrreq by OR'ing the single pulse request with the burst
-- signal extended by 1 clock so that the write request is valid during entire burst
-- for all pipeline models except 5
WRREQ_PIPE_NOT5_GEN: if C_PIPELINE_MODEL = 0 or
C_PIPELINE_MODEL = 1 or
C_PIPELINE_MODEL = 2 or
C_PIPELINE_MODEL = 3 or
C_PIPELINE_MODEL = 7 generate
bus2ip_wrreq_s0 <= wrreq or (not(opb_rnw_s0) and bus2ip_burst_s1);
end generate WRREQ_PIPE_NOT5_GEN;
-- for pipeline model 5, generate bus2ip_wrreq by OR'ing the single pulse request
-- with delayed version of the burst_s1 signal
WRREQ_PIPE5_GEN: if C_PIPELINE_MODEL=4 or
C_PIPELINE_MODEL=5 or
C_PIPELINE_MODEL=6 generate
begin
bus2ip_wrreq_s0 <= wrreq or (not(bus2ip_rnw_s1) and bus2ip_burst_s1_d1);
end generate WRREQ_PIPE5_GEN;
end generate GEN_RDREQ_WREQ;
-------------------------------------------------------------------------------
-- Bus2IP_RdAddrValid and Bus2IP_WrAddrValid Generation
-- These signals are a single pulse during single transactions and are extended
-- during burst transactions
--bus2ip_rdaddrvalid_s0 <= bus2ip_rdreq_s0 and wrbuf_addrvalid;
--bus2ip_wraddrvalid_s0 <= bus2ip_wrreq_s0 and wrbuf_addrvalid;
------------------------------------------------------------------------------
-- Read FIFO
------------------------------------------------------------------------------
INCLUDE_RDFIFO_GEN : if (INCLUDE_RDFIFO) generate
constant DATA_INDEX : integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_RDFIFO_DATA);
constant DATA_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
DATA_INDEX);
constant REG_INDEX : integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_RDFIFO_REG);
constant REG_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
REG_INDEX);
signal bus2ip_rdreq_rfifo: std_logic;
signal bus2ip_rdce3_rfifo: std_logic;
begin
--synopsys translate_off
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(RD_WIDTH_BITS)
report "This implementation of the OPB IPIF requires the read " &
" width to be equal to the write width for the RDFIFO."
severity FAILURE;
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DWIDTH_ARRAY(DATA_INDEX)
report "This implementation of the OPB IPIF requires the write " &
" width to be equal to the data width specified in " &
" C_ARD_DWIDTH_ARRAY for RDFIFO."
severity FAILURE;
--synopsys translate_on
----------------------------------------------------------------------------
-- For RDFIFO, trim Bus2IP_RdReq as needed per pipeline model. The RDFIFO
-- moves burst data on every cycle and requires that
-- OPB_seqAddr is low on the next-to-last cycle.
----------------------------------------------------------------------------
RDREQ_RDCE_PIPE0_GEN: if C_PIPELINE_MODEL = 0 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1;
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE) and
not (not opb_seqaddr_d1 and bus2ip_burst_s1);
end generate RDREQ_RDCE_PIPE0_GEN;
RDREQ_RDCE_PIPE124_GEN: if C_PIPELINE_MODEL=1 or
C_PIPELINE_MODEL=2 or
C_PIPELINE_MODEL=4 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1;
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE);
end generate RDREQ_RDCE_PIPE124_GEN;
RDREQ_RDCE_PIPE3_GEN: if C_PIPELINE_MODEL=3 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1 and
not (not opb_seqaddr_d1 and bus2ip_burst_s1);
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE) and
not (not opb_seqaddr_d1 and bus2ip_burst_s1);
end generate RDREQ_RDCE_PIPE3_GEN;
RDREQ_RDCE_PIPE56_GEN: if C_PIPELINE_MODEL = 5 or
C_PIPELINE_MODEL = 6 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1 and
not (not OPB_seqAddr_eff and opb_seqaddr_d1);
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE) and
not (not OPB_seqAddr_eff and opb_seqaddr_d1);
end generate RDREQ_RDCE_PIPE56_GEN;
RDREQ_RDCE_PIPE7_GEN: if C_PIPELINE_MODEL = 7 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1 and
not (not OPB_seqAddr_eff and (opb_seqaddr_d1 or bus2ip_burst_s1));
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE) and
not (not OPB_seqAddr_eff and (opb_seqaddr_d1 or bus2ip_burst_s1));
end generate RDREQ_RDCE_PIPE7_GEN;
I_RDFIFO: entity opb_v20_v1_10_d.rdpfifo_top
Generic map(
C_MIR_ENABLE => (C_DEV_MIR_ENABLE /= 0),
C_BLOCK_ID => C_DEV_BLK_ID,
C_FIFO_DEPTH_LOG2X => log2(
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(FIFO_CAPACITY_BITS) /
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS)
),
C_FIFO_WIDTH => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS),
C_INCLUDE_PACKET_MODE => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_PACKET_MODE)=0,
C_INCLUDE_VACANCY => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_VACANCY)=0,
C_SUPPORT_BURST => true,
C_IPIF_DBUS_WIDTH => C_OPB_DWIDTH,
C_VIRTEX_II => VIRTEX_II
)
port map(
-- Inputs From the IPIF Bus
Bus_rst => bus2ip_reset_i,
Bus_Clk => bus2ip_clk_i,
Bus_RdReq => bus2ip_rdreq_rfifo,
Bus_WrReq => bus2ip_wrreq_s1,
Bus2FIFO_RdCE1 => bus2ip_rdce_s1(RFIFO_REG_CE_LO),
Bus2FIFO_RdCE2 => bus2ip_rdce_s1(RFIFO_REG_CE_LO+1),
Bus2FIFO_RdCE3 => bus2ip_rdce3_rfifo,
Bus2FIFO_WrCE1 => bus2ip_wrce_s1(RFIFO_REG_CE_LO),
Bus2FIFO_WrCE2 => bus2ip_wrce_s1(RFIFO_REG_CE_LO+1),
Bus2FIFO_WrCE3 => bus2ip_wrce_s1(RFIFO_DATA_CE),
Bus_DBus => bus2ip_data_s1,
-- Inputs from the IP
IP2RFIFO_WrReq => IP2RFIFO_WrReq,
IP2RFIFO_WrMark => IP2RFIFO_WrMark,
IP2RFIFO_WrRestore => IP2RFIFO_WrRestore,
IP2RFIFO_WrRelease => IP2RFIFO_WrRelease,
IP2RFIFO_Data => IP2RFIFO_Data,
-- Outputs to the IP
RFIFO2IP_WrAck => RFIFO2IP_WrAck,
RFIFO2IP_AlmostFull => RFIFO2IP_AlmostFull,
RFIFO2IP_Full => RFIFO2IP_Full,
RFIFO2IP_Vacancy => RFIFO2IP_Vacancy,
-- Outputs to the IPIF DMA/SG function
RFIFO2DMA_AlmostEmpty => open,
RFIFO2DMA_Empty => open,
RFIFO2DMA_Occupancy => open,
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock => rdfifo2intr_deadlock,
-- Outputs to the IPIF Bus
FIFO2Bus_DBus => rdfifo2bus_data,
FIFO2Bus_WrAck => rfifo_wrack,
FIFO2Bus_RdAck => rfifo_rdack,
FIFO2Bus_Error => rfifo_error,
FIFO2Bus_Retry => rfifo_retry,
FIFO2Bus_ToutSup => rfifo_toutsup
);
end generate INCLUDE_RDFIFO_GEN;
REMOVE_RDFIFO_GEN : if (not INCLUDE_RDFIFO) generate
rdfifo2bus_data <= (others => '0');
rdfifo2intr_deadlock <= '0';
RFIFO2IP_AlmostFull <= '0';
RFIFO2IP_Full <= '0';
RFIFO2IP_Vacancy <= (others => '0');
RFIFO2IP_WrAck <= '0';
rfifo_error <= '0';
rfifo_rdack <= '0';
rfifo_retry <= '0';
rfifo_toutsup <= '0';
rfifo_wrack <= '0';
end generate REMOVE_RDFIFO_GEN;
rdfifo_ack <= rfifo_wrack or rfifo_rdack;
--------------------------------------------------------------------------------
-- Write FIFO
--------------------------------------------------------------------------------
INCLUDE_WRFIFO_GEN : if (INCLUDE_WRFIFO) generate
constant DATA_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_WRFIFO_DATA);
constant DATA_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
DATA_INDEX);
constant REG_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_WRFIFO_REG);
constant REG_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
REG_INDEX);
begin
--synopsys translate_off
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(RD_WIDTH_BITS)
report "This implementation of the OPB IPIF requires the read " &
" width to be equal to the write width for the WRFIFO."
severity FAILURE;
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DWIDTH_ARRAY(DATA_INDEX)
report "This implementation of the OPB IPIF requires the write " &
" width to be equal to the data width specified in " &
" C_ARD_DWIDTH_ARRAY for WRFIFO."
severity FAILURE;
--synopsys translate_on
I_WRPFIFO_TOP: entity opb_v20_v1_10_d.wrpfifo_top
Generic map(
C_MIR_ENABLE => (C_DEV_MIR_ENABLE /= 0),
C_BLOCK_ID => C_DEV_BLK_ID,
C_FIFO_DEPTH_LOG2X => log2(
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(FIFO_CAPACITY_BITS) /
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS)
),
C_FIFO_WIDTH => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS),
C_INCLUDE_PACKET_MODE => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_PACKET_MODE)=0,
C_INCLUDE_VACANCY => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_VACANCY)=0,
C_SUPPORT_BURST => true,
C_IPIF_DBUS_WIDTH => C_OPB_DWIDTH,
C_VIRTEX_II => VIRTEX_II
)
port map(
-- Inputs From the IPIF Bus
Bus_rst => bus2ip_reset_i,
Bus_clk => bus2ip_clk_i,
Bus_RdReq => bus2ip_rdreq_s1,
Bus_WrReq => bus2ip_wrreq_s1,
Bus2FIFO_RdCE1 => bus2ip_rdce_s1(WFIFO_REG_CE_LO),
Bus2FIFO_RdCE2 => bus2ip_rdce_s1(WFIFO_REG_CE_LO+1),
Bus2FIFO_RdCE3 => bus2ip_rdce_s1(WFIFO_DATA_CE),
Bus2FIFO_WrCE1 => bus2ip_wrce_s1(WFIFO_REG_CE_LO),
Bus2FIFO_WrCE2 => bus2ip_wrce_s1(WFIFO_REG_CE_LO+1),
Bus2FIFO_WrCE3 => bus2ip_wrce_s1(WFIFO_DATA_CE),
Bus_DBus => bus2ip_data_s1,
-- Inputs from the IP
IP2WFIFO_RdReq => IP2WFIFO_RdReq,
IP2WFIFO_RdMark => IP2WFIFO_RdMark,
IP2WFIFO_RdRestore => IP2WFIFO_RdRestore,
IP2WFIFO_RdRelease => IP2WFIFO_RdRelease,
-- Outputs to the IP
WFIFO2IP_Data => WFIFO2IP_Data,
WFIFO2IP_RdAck => WFIFO2IP_RdAck,
WFIFO2IP_AlmostEmpty => WFIFO2IP_AlmostEmpty,
WFIFO2IP_Empty => WFIFO2IP_Empty,
WFIFO2IP_Occupancy => WFIFO2IP_Occupancy,
-- Outputs to the IP
WFIFO2DMA_AlmostFull => open,
WFIFO2DMA_Full => open,
WFIFO2DMA_Vacancy => open,
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock => wrfifo2intr_deadlock,
-- Outputs to the IPIF Bus
FIFO2Bus_DBus => wrfifo2bus_data,
FIFO2Bus_WrAck => wfifo_wrack,
FIFO2Bus_RdAck => wfifo_rdack,
FIFO2Bus_Error => wfifo_error,
FIFO2Bus_Retry => wfifo_retry,
FIFO2Bus_ToutSup => wfifo_toutsup
);
end generate INCLUDE_WRFIFO_GEN;
REMOVE_WRFIFO_GEN : if (not INCLUDE_WRFIFO) generate
WFIFO2IP_AlmostEmpty <= '0';
WFIFO2IP_Data <= (others => '0');
WFIFO2IP_Empty <= '0';
WFIFO2IP_Occupancy <= (others => '0');
WFIFO2IP_RdAck <= '0';
wfifo_error <= '0';
wfifo_rdack <= '0';
wfifo_retry <= '0';
wfifo_toutsup <= '0';
wfifo_wrack <= '0';
wrfifo2bus_data <= (others => '0');
wrfifo2intr_deadlock <= '0';
end generate REMOVE_WRFIFO_GEN;
wrfifo_ack <= wfifo_wrack or wfifo_rdack;
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: opb_bam.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_bam.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_bam.vhd
-- Version: v3.01a
-- Description: Bus Attachment Module, OPB to IPIC.
--
-- VHDL Standard: VHDL 93
-------------------------------------------------------------------------------
-- Structure: opb_bam
-- -- reset_mir
-- -- interrupt_control
-- -- rdpfifo_top
-- -- wrpfifo_top
-- -- opb_be_gen
-- -- brst_addr_cntr
-- -- brst_addr_cntr_reg
-- -- opb_flex_addr_cntr
-- -- write_buffer
-- -- srl_fifo3
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
--
-- FLO 10/22/02
-- ^^^^^^
-- Initial version.
-- ~~~~~~
-- FLO 12/09/02
-- ^^^^^^
-- Support now for posted writes and burst of posted writes under
-- OPB_seqAddr=1. (The latter not yet tested.)
-- ~~~~~~
-- FLO 03/21/03
-- ^^^^^^
-- Hooked up neglected connection of OPB_BE to opb_be_s0.
-- ~~~~~~
-- FLO 05/15/2003
-- ^^^^^^
-- Introduced signal OPB_seqAddr_eff to disable bursts when parameter
-- C_DEV_BURST_ENABLE is false.
-- ~~~~~~
--
-- FLO 05/27/2003
-- ^^^^^^
-- Use sln_xferack_s1 to enable other than '0' values to the
-- OPBOUT pipestage when this stage is present and there is
-- a single address range. This, in turn, allows the optimization
-- of passing ip2bus_data through to ip2bus_data_mx without
-- qualification by a CE Address-Range decode, saving a LUT per
-- data-bus bit for this case.
-- ~~~~~~
--
-- FLO 05/28/2003
-- ^^^^^^
-- Made a correction to the last change that was causing it to
-- drive sln_dbus during a write transaction.
-- Now the sln_dbus_s2 signals are separated from the other _s2 signals
-- for application of the reset when sln_xferack_s1 = '0' and this
-- reset is further qualified by bus2ip_rnw_s1.
-- ~~~~~~
-- FLO 09/10/2003
-- ^^^^^^
-- Fixed the mirror instantiation, which erroneously had the address tied low.
-- ~~~~~~
--
-- ALS 10/22/03
-- ^^^^^^
-- Creation of version v3_00_b to include read and write packet FIFOs.
-- Also modified code for direct entity instantiation.
-- ~~~~~~
-- ALS 11/18/03
-- ^^^^^^
-- Creation of version v3_01_a to modify generics and some ports to align
-- with the PLB IPIF. Added look-ahead address counter for read bursts and write
-- buffer for write bursts.
-- ~~~~~~~
--
-- ALS 04/09/04
-- ^^^^^^
-- Removed vectorization of IP2Bus signals
-- ^^^^^^
-- GAB 04/15/04
-- ^^^^^^
-- - Updated to use libraries proc_common_v2_00_a, wrpfifo_v1_01_b,
-- rdpfifo_v1_01_b, and interrupt_control_v1_00_a.
-- - Fixed issues with wrpfifo for pipeline model 0
-- - Fixed issues with wrpfifo and rdpfifo for cases when write buffer
-- was instantiated.
-- - Fixed issues with master aborts, delayed IP acknowledges.
-- - Fixed double clock wide wrce which caused an interrupt to be generated
-- when an interrupt was cleared.
-- - Improved utilization by allowing the tools to place the read mux
-- - Removed checks on postedwrinh when write buffer was instantiated because
-- the write buffer currently does not support this feature.
-- - Set MAX_USER_ADDR_RANGE minimum to 7 because opb_flex_addr_cntr.vhd expects
-- a minimum of 7 address bits to decode.
-- - Changed reset/mir to be posted write inhibited because of problems with
-- various pipeline models and single beat reads. CS,CE, etc. to reset_mir
-- would not occur because they where inhibited on the same clock cycle as
-- they were to be generated.
-- - Created abort detection logic for pipeline models 1,3, and 7 to allow the
-- ipif to properly recover from a master abort.
--
-- ~~~~~~~
-- GAB 07/07/04
-- ^^^^^^
-- - Fixed issues with dynamic switching of IP2Bus_PostedWrInh signal
-- - Optimized slave data read mux
-- - Fixed issue with Bus2IP_Burst signal when WriteBuffer was instantiated
-- - Fixed issue with Bus2IP_AddrValid when WriteBuffer was instantiated
-- ~~~~~~~
-- GAB 08/10/04
-- ^^^^^^
-- - Modified port range for IP2RFIFO_Data and WFIFO2IP_Data to be based on
-- the C_ARD_DWIDTH_ARRAY generic and not hard coded. Fixes CR191551
-- - Added synopsys translate_off/translate_on statements to exclude assert
-- statements from the synthesis process.
-- - Added assert statement to check for match of C_ARD_DWIDTH_ARRAY element
-- and fifo WR_WIDTH_BITS setting, though the mis-match of array sizes should
-- cause the simulation to error out on load.
-- ~~~~~~~
-- GAB 07/06/05
-- ^^^^^^
-- Removed xfer_abort signal from Sln_xferack logic to help improve timing.
-- ~~~~~~~
-- GAB 08/05/05
-- ^^^^^^
-- Fixed issue with IP2Bus_Postedwrinh_s2 getting reset with OPB_Select would
-- negate. IP2Bus_Postedwrinh_s2 should only negat based on UserIP.
-- ~~~~~~~
--
-- GAB 09/21/05
-- ^^^^^^
-- Fixed long timing path issue with Sln_Retry signal and cycle aborts. Modified
-- logic to suppress sln_xferack_s1 with cycle_abort for models where out-pipe was
-- included.
-- ~~~~~~~
-- GAB 10/12/05
-- ^^^^^^
-- Incorperated rev C mods into rev A to fix slow timing path with the address
-- decode. The modification simply shifts the input pipe stage for the address
-- to after the address decode. Therefore the functionality does not change
-- nor does the latency. This fix only improves pipeline 5 and 7 (i.e. any
-- with a model with a input pipeline stage).
-- ~~~~~~~
-- GAB 5/19/06
-- ^^^^^^
-- Removed unused last_wr_xferack, last_wr_xferack_d1,
-- and last_wr_xferack_d2.
-- Added bus2ip_rnw_s1 signal to SLN_XFERACK_PROC process's sinsitivity list.
-- This fixes CR231744.
-- ~~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-- -------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.all;
use opb_v20_v1_10_d.ipif_pkg.all;
use opb_v20_v1_10_d.ipif_steer;
use opb_v20_v1_10_d.family.all;
use opb_v20_v1_10_d.pselect;
use opb_v20_v1_10_d.or_muxcy;
use opb_v20_v1_10_d.reset_mir;
use opb_v20_v1_10_d.brst_addr_cntr;
use opb_v20_v1_10_d.brst_addr_cntr_reg;
use opb_v20_v1_10_d.opb_be_gen;
use opb_v20_v1_10_d.interrupt_control;
use opb_v20_v1_10_d.wrpfifo_top;
use opb_v20_v1_10_d.rdpfifo_top;
entity opb_bam is
generic
(
C_ARD_ID_ARRAY : INTEGER_ARRAY_TYPE
:= ( 0 => IPIF_INTR,
1 => IPIF_RST,
2 => USER_00
);
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= ( x"0000_0000_6000_0000", -- IPIF_INTR
x"0000_0000_6000_003F",
--
x"0000_0000_6000_0040", -- IPIF_RST
x"0000_0000_6000_0043",
--
x"0000_0000_6000_0100", -- USER_00
x"0000_0000_6000_01FF"
);
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE
:= ( 32, -- IPIF_INTR
32, -- IPIF_INTR
32 -- USER_00
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
:= ( 16, -- IPIF_INTR
1, -- IPIF_RST
8 -- USER_00
);
C_ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE
:= (
0 => (others => 0)
,1 => (others => 0)
,2 => (others => 0)
);
C_PIPELINE_MODEL : integer := 7;
-- The pipe stages are enumerated and numbered as:
-- -- ----------
-- n Pipe stage
-- -- ----------
-- 0 OPBIN
-- 1 IPIC
-- 2 OPBOUT
-- Each pipe stage is either present or absent (i.e. bypassed).
-- The pipe stage, n, is present if the (2^n)th
-- bit in C_PIPELINE_MODEL is 1.
--
C_DEV_BLK_ID : INTEGER := 1;
-- Unique block ID, assigned to the device when the system is built.
C_DEV_MIR_ENABLE : INTEGER := 0;
C_OPB_AWIDTH : INTEGER := 32;
-- width of Address Bus (in bits)
C_OPB_DWIDTH : INTEGER := 32;
-- Width of the Data Bus (in bits)
C_FAMILY : string := "virtexe";
--
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := ( 5, 1 );
--
-- There will be one interrupt signal for each entry in
-- C_IP_INTR_MODE_ARRAY. The leftmost entry will be the
-- mode for input port IP2Bus_Intr(0), the next entry
-- for IP2Bus_Intr(1), etc.
--
-- These modes are supported:
--
-- Mode Description
--
-- 1 Active-high interrupt condition.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port-- that is an interrupt condition
-- that is latched and cleared in the IP core and made available
-- to the system via the Interrupt Source Controller in
-- the Bus Attachment Module.
--
-- 2 Active-low interrupt condition.
-- Like 1, except that the interrupt condition is asserted low.
--
-- 3 Active-high pulse interrupt event.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port--whose single clock period of active-high
-- assertion is an interrupt event that is latched,
-- and cleared as a service of the Interrupt Source
-- Controller in the Bus Attachment Module.
--
-- 4 Active-low pulse interrupt event.
-- Like 3, except the interrupt-event pulse is active low.
--
-- 5 Positive-edge interrupt event.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port--whose low-to-high transition, synchronous
-- with the clock, is an interrupt event that is latched,
-- and cleared as a service of the Interrupt Source
-- Controller in the Bus Attachment Module.
--
-- 6 Negative-edge interrupt event.
-- Like 5, except that the interrupt event is a
-- high-to-low transition.
--
-- Other mode codes are reserved.
--
C_DEV_BURST_ENABLE : INTEGER := 0;
-- Burst Enable for IPIF Interface
C_INCLUDE_ADDR_CNTR : INTEGER := 0;
-- ALS added generic for read address counter
-- inclusion of read address look ahead counter and write address counter
C_INCLUDE_WR_BUF : INTEGER := 0
-- ALS: added generic for write buffer
);
port
(
-- OPB signals
OPB_select : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_RNW : in std_logic;
OPB_seqAddr : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
-- IPIC signals (address, data, acknowledges)
Bus2IP_CS : out std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
Bus2IP_CE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Data : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Bus2IP_Addr : out std_logic_vector(0 to C_OPB_AWIDTH-1);
Bus2IP_AddrValid : out std_logic;
Bus2IP_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
Bus2IP_RNW : out std_logic;
Bus2IP_Burst : out std_logic;
IP2Bus_Data : in std_logic_vector(0 to C_OPB_DWIDTH-1);
IP2Bus_Ack : in std_logic;
IP2Bus_AddrAck : in std_logic;
IP2Bus_Error : in std_logic;
IP2Bus_Retry : in std_logic;
IP2Bus_ToutSup : in std_logic;
IP2Bus_PostedWrInh : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
-- IPIC signals (Read Packet FIFO)
IP2RFIFO_Data : in std_logic_vector(0 to C_ARD_DWIDTH_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY,
IPIF_RDFIFO_DATA)) - 1) := (others => '0');
IP2RFIFO_WrMark : in std_logic := '0';
IP2RFIFO_WrRelease : in std_logic := '0';
IP2RFIFO_WrReq : in std_logic := '0';
IP2RFIFO_WrRestore : in std_logic := '0';
RFIFO2IP_AlmostFull : out std_logic;
RFIFO2IP_Full : out std_logic;
RFIFO2IP_Vacancy : out std_logic_vector(0 to bits_needed_for_vac(
find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe
(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA))) - 1);
RFIFO2IP_WrAck : out std_logic;
-- IPIC signals (Write Packet FIFO)
IP2WFIFO_RdMark : in std_logic := '0';
IP2WFIFO_RdRelease : in std_logic := '0';
IP2WFIFO_RdReq : in std_logic := '0';
IP2WFIFO_RdRestore : in std_logic := '0';
WFIFO2IP_AlmostEmpty: out std_logic;
WFIFO2IP_Data : out std_logic_vector(0 to C_ARD_DWIDTH_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY,
IPIF_WRFIFO_DATA)) - 1);
WFIFO2IP_Empty : out std_logic;
WFIFO2IP_Occupancy : out std_logic_vector(0 to bits_needed_for_occ(
find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe
(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA))) - 1);
WFIFO2IP_RdAck : out std_logic;
-- interrupts
IP2Bus_IntrEvent : in std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
IP2INTC_Irpt : out std_logic;
-- Software test breakpoint signal
Freeze : in std_logic;
Bus2IP_Freeze : out std_logic;
-- clocks and reset
OPB_Clk : in std_logic;
Bus2IP_Clk : out std_logic;
IP2Bus_Clk : in std_logic;
Reset : in std_logic;
Bus2IP_Reset : out std_logic
);
end entity opb_bam;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
architecture implementation of opb_bam is
-------------------------------------------------------------------------------
-- Function and Constant Declarations
-------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- MIR fields
--
-- 4 7 5 8 8 # bits
--
-- 0-----3 4----------10 11-----15 16-----------23 24------------31
-- +-------+-------------+---------+---------------+----------------+
-- |MAJOR | MINOR |REVISION | BLK_ID | TYPE | MIR
-- |VERSION| VERSION |(letter) | | |
-- +-------+-------------+---------+---------------+----------------+
-- 0 = a
-- 1 = b
-- etc.
--
-- \ | /
-- \ | /
-- \ | /
-- \ | /
-- \ | /
-- \ | /
--
-- v1_03_c (aka V1.3c)
----------------------------------------------------------------------------
-- constant MIR_MAJOR_VERSION : INTEGER range 0 to 15 := 1;
-- constant MIR_MINOR_VERSION : INTEGER range 0 to 127:= 0;
-- constant MIR_REVISION : INTEGER := 0;
-- ALS - modified MIR_MAJOR_VERSION to 3 and MIR_MINOR_VERSION to 1
constant MIR_MAJOR_VERSION : INTEGER range 0 to 15 := 3;
constant MIR_MINOR_VERSION : INTEGER range 0 to 127:= 1;
constant MIR_REVISION : INTEGER range 0 to 25 := 0;
constant MIR_TYPE : INTEGER := 1;
-- Always '1' for OPB ipif interface type
-- ToDo, stays same for bus_attach?
constant NUM_ARDS : integer := C_ARD_ID_ARRAY'length;
constant NUM_CES : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant WRBUF_DEPTH : integer := 16;
constant INCLUDE_OPBIN_PSTAGE : boolean := (C_PIPELINE_MODEL/1) mod 2 = 1;
constant INCLUDE_IPIC_PSTAGE : boolean := (C_PIPELINE_MODEL/2) mod 2 = 1;
constant INCLUDE_OPBOUT_PSTAGE : boolean := (C_PIPELINE_MODEL/4) mod 2 = 1;
constant INCLUDE_RESET_MIR : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_RST);
constant INCLUDE_INTR : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_INTR);
constant INCLUDE_ADDR_CNTR : boolean
:= (C_INCLUDE_ADDR_CNTR=1 and C_DEV_BURST_ENABLE=1)
or (C_INCLUDE_ADDR_CNTR=1 and C_INCLUDE_WR_BUF=1);
-- ALS - added boolean constants for Read and Write Packet FIFOs
constant INCLUDE_RDFIFO : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA);
constant INCLUDE_WRFIFO : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA);
-- Set SINGLE_CE if the only attached element is a user IP with only 1 CE.
constant SINGLE_CE : boolean := C_ARD_ID_ARRAY'length = 1
and C_ARD_NUM_CE_ARRAY(0) = 1
and C_ARD_ID_ARRAY(0) /= IPIF_RST;
-- constant ZERO_SLV : std_logic_vector(0 to 199) := (others => '0');
constant VIRTEX_II : boolean := derived(C_FAMILY, virtex2);
---------------------------------------------------------------------------
-- Function bo2sl
---------------------------------------------------------------------------
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl_table : bo2sl_type := ('0', '1');
function bo2sl(b: boolean) return std_logic is
begin
return bo2sl_table(b);
end bo2sl;
---------------------------------------------------------------------------
-- Function num_common_high_order_addr_bits
---------------------------------------------------------------------------
----------------------------------------------------------------------------
-- This function returns the number of high-order address bits
-- that can be commonly decoded across all address pairs passed in as
-- the argument ara. Note: only the C_OPB_AWIDTH rightmost bits of an entry
-- in ara are considered to make up the address.
----------------------------------------------------------------------------
function num_common_high_order_addr_bits(ara: SLV64_ARRAY_TYPE)
return integer is
variable n : integer := C_OPB_AWIDTH;
-- Maximum number of common high-order bits for
-- the ranges starting at an index less than i.
variable i, j: integer;
variable old_base: std_logic_vector(0 to C_OPB_AWIDTH-1)
:= ara(0)( ara(0)'length-C_OPB_AWIDTH
to ara(0)'length-1
);
variable new_base, new_high: std_logic_vector(0 to C_OPB_AWIDTH-1);
begin
i := 0;
while i < ara'length loop
new_base := ara(i )(ara(0)'length-C_OPB_AWIDTH to ara(0)'length-1);
new_high := ara(i+1)(ara(0)'length-C_OPB_AWIDTH to ara(0)'length-1);
j := 0;
while j < n -- Limited by earlier value.
and new_base(j) = old_base(j) -- High-order addr diff found
-- with a previous range.
and (new_base(j) xor new_high(j))='0' -- Addr-range boundary found
-- for current range.
loop
j := j+1;
end loop;
n := j;
i := i+2;
end loop;
return n;
end num_common_high_order_addr_bits;
constant K_DEV_ADDR_DECODE_WIDTH
: integer
:= num_common_high_order_addr_bits(C_ARD_ADDR_RANGE_ARRAY);
---------------------------------------------------------------------------
-- Function cs_index_or_maxint
---------------------------------------------------------------------------
function cs_index_or_maxint(C_ARD_ID_ARRAY:INTEGER_ARRAY_TYPE; ID:INTEGER)
return integer is
begin
if find_ard_id(C_ARD_ID_ARRAY, ID) then
return get_id_index(C_ARD_ID_ARRAY, ID);
else
return integer'high;
end if;
end cs_index_or_maxint;
constant RESET_MIR_CS_IDX : natural
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_RST);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_RESET_MIR is false.
constant INTR_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_INTR);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_INTR is false.
-- ALS - added read and write packet FIFOs indices
constant RDFIFO_DATA_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_RDPFIFO is false.
constant RDFIFO_REG_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_RDFIFO_REG);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_RDPFIFO is false.
constant WRFIFO_DATA_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_WRPFIFO is false.
constant WRFIFO_REG_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_WRFIFO_REG);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_WRPFIFO is false.
---------------------------------------------------------------------------
-- Function ce_index_or_maxint
---------------------------------------------------------------------------
function ce_index_or_maxint(C_ARD_ID_ARRAY: INTEGER_ARRAY_TYPE; IDX: integer)
return integer is
begin
if IDX < NUM_ARDS then
return calc_start_ce_index(C_ARD_NUM_CE_ARRAY, IDX);
else
return integer'high;
end if;
end ce_index_or_maxint;
constant RESET_MIR_CE_IDX : natural
:=ce_index_or_maxint(C_ARD_ID_ARRAY,
RESET_MIR_CS_IDX);
constant INTR_CE_LO : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
INTR_CS_IDX);
-- ALS - added constants for read and write FIFOS
constant RFIFO_REG_CE_LO : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
RDFIFO_REG_CS_IDX);
constant RFIFO_DATA_CE : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
RDFIFO_DATA_CS_IDX);
constant WFIFO_REG_CE_LO : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
WRFIFO_REG_CS_IDX);
constant WFIFO_DATA_CE : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
WRFIFO_DATA_CS_IDX);
---------------------------------------------------------------------------
-- Function ce_hi_avoiding_bounds_error (was intr_ce_hi_avoiding_bounds_error)
-- ALS - modified this function to be usable by the FIFO Register CEs
---------------------------------------------------------------------------
function ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY: INTEGER_ARRAY_TYPE;
CS_IDX: integer
) return integer is
begin
if CS_IDX < NUM_ARDS then
return calc_start_ce_index(C_ARD_NUM_CE_ARRAY, CS_IDX)
+ C_ARD_NUM_CE_ARRAY(CS_IDX) - 1;
else
return integer'high;
end if;
end ce_hi_avoiding_bounds_error;
constant INTR_CE_HI : natural
:= ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY,
INTR_CS_IDX
);
-- ALS - added constant for read/write FIFO register CE high
constant RFIFO_REG_CE_HI : natural
:= ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY,
RDFIFO_REG_CS_IDX
);
constant WFIFO_REG_CE_HI : natural
:= ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY,
WRFIFO_REG_CS_IDX
);
---------------------------------------------------------------------------
-- Function number_CEs_for
---------------------------------------------------------------------------
function number_CEs_for(ard_id: integer) return integer is
variable id_included: boolean;
begin
id_included := find_ard_id(C_ARD_ID_ARRAY, ard_id);
if id_included then
return C_ARD_NUM_CE_ARRAY(get_id_index(C_ARD_ID_ARRAY, ard_id));
else return 0;
end if;
end number_CEs_for;
----------------------------------------------------------------------------
-- Constant zero std_logic_vector large enough for any needed use.
----------------------------------------------------------------------------
constant ZSLV : std_logic_vector(0 to 255) := (others => '0');
---------------------------------------------------------------------------
-- Function num_decode_bits
---------------------------------------------------------------------------
----------------------------------------------------------------------------
-- This function returns the number of address bits that need to be
-- decoded to find a "hit" in the address range defined by
-- the idx'th pair of base_address/high_address in c_ard_addr_range_array.
-- Only the rightmost numbits are considered and the result is the
-- number of leftmost bits within this field that need to be decoded.
----------------------------------------------------------------------------
function num_decode_bits(ard_addr_range_array : SLV64_ARRAY_TYPE;
numbits : natural;
idx : natural)
return integer is
constant SZ : natural := ard_addr_range_array(0)'length;
constant ADDR_XOR : std_logic_vector(0 to numbits-1)
:= ard_addr_range_array(2*idx )(SZ-numbits to SZ-1) -- base
xor ard_addr_range_array(2*idx+1)(SZ-numbits to SZ-1); -- high
begin
for i in 0 to numbits-1 loop
if ADDR_XOR(i)='1' then return i;
end if;
end loop;
return(numbits);
end function num_decode_bits;
---------------------------------------------------------------------------
-- Function encoded_size_is_1
---------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Returns whether bit n of the encoded representation of the data size
-- for address range ar is a 1
--
-- DSIZE Encoded value
-- 8 001
-- 16 010
-- 32 011
-- 64 100
-- 128 101
-- Others not supported
--------------------------------------------------------------------------
function encoded_size_is_1(ar, n: natural) return boolean is
begin
case n is
-- high-order bit
when 0 => return C_ARD_DWIDTH_ARRAY(ar) = 64 or
C_ARD_DWIDTH_ARRAY(ar) =128;
-- middle bit
when 1 => return C_ARD_DWIDTH_ARRAY(ar) = 16 or
C_ARD_DWIDTH_ARRAY(ar) = 32;
-- low-order bit
when 2 => return C_ARD_DWIDTH_ARRAY(ar) = 8 or
C_ARD_DWIDTH_ARRAY(ar) = 32 or
C_ARD_DWIDTH_ARRAY(ar) =128;
-- default for unsupported values
when others => return false;
end case;
end encoded_size_is_1;
---------------------------------------------------------------------------
-- Function num_cs_for_bit
---------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Returns the number of CS signals that need to be or'ed to give
-- bit n of the encoded size.
----------------------------------------------------------------------------
function num_cs_for_bit(n: natural) return natural is
variable r: natural;
begin
r := 0;
for k in 0 to NUM_ARDS-1 loop
if encoded_size_is_1(k, n) then r := r+1; end if;
end loop;
return r;
end num_cs_for_bit;
---------------------------------------------------------------------------
-- Function eff_ip2bus_val
---------------------------------------------------------------------------
-- ALS - modified to include read and write packet fifos
function eff_ip2bus_val(i : integer;
rst : std_logic;
intr : std_logic;
wrfifo : std_logic;
rdfifo : std_logic;
user : std_logic
) return std_logic is
begin
if C_ARD_ID_ARRAY(i) = IPIF_RST then return rst;
elsif C_ARD_ID_ARRAY(i) = IPIF_INTR then return intr;
elsif C_ARD_ID_ARRAY(i) = IPIF_WRFIFO_REG or
C_ARD_ID_ARRAY(i) = IPIF_WRFIFO_DATA then return wrfifo;
elsif C_ARD_ID_ARRAY(i) = IPIF_RDFIFO_REG or
C_ARD_ID_ARRAY(i) = IPIF_RDFIFO_DATA then return rdfifo;
else return user;
end if;
end eff_ip2bus_val;
---------------------------------------------------------------------------
-- ALS: added function get_max_addr_range
-- Function get_max_addr_range
-- This function parses the ARD_ADDR_RANGE_ARRAY to determine which
-- baseaddr/highaddr pair spans the greatest address range. This is then
-- used to size the burst address counter
---------------------------------------------------------------------------
function get_max_user_addr_range(bus_awidth:integer) return integer is
variable max_range : integer := 0;
variable curr_range : integer := 0;
begin
for i in 0 to C_ARD_ADDR_RANGE_ARRAY'length/2-1 loop
if C_ARD_ID_ARRAY(i) = IPIF_RST or
C_ARD_ID_ARRAY(i) = IPIF_INTR or
C_ARD_ID_ARRAY(i) = IPIF_WRFIFO_REG or
C_ARD_ID_ARRAY(i) = IPIF_WRFIFO_DATA or
C_ARD_ID_ARRAY(i) = IPIF_RDFIFO_REG or
C_ARD_ID_ARRAY(i) = IPIF_RDFIFO_DATA then
max_range := max_range;
else
-- addr_bits function returns number of address bits that are equal
-- between baseaddr and highaddr, so the address range is the
-- bus width minus the address bits
curr_range := bus_awidth - num_decode_bits(C_ARD_ADDR_RANGE_ARRAY,
C_OPB_AWIDTH,
i);
if curr_range >= max_range then
max_range := curr_range;
else
max_range := max_range;
end if;
end if;
end loop;
return max_range;
end get_max_user_addr_range;
-- opb_flex_addr_cntr requires a minimum range of 7 (or 0 to 6)
-- constant MAX_USER_ADDR_RANGE : integer := get_max_user_addr_range(C_OPB_AWIDTH); --GB
constant MAX_USER_ADDR_RANGE : integer := max2(7,get_max_user_addr_range(C_OPB_AWIDTH)); --GB
------------------------------------------------------------------------------
-- Signal declarations
------------------------------------------------------------------------------
signal bus2ip_clk_i : std_logic;
signal bus2ip_reset_i : std_logic;
signal opb_select_s0 : std_logic;
signal opb_select_s0_d1 : std_logic;
signal opb_rnw_s0 : std_logic;
signal opb_seqaddr_s0 : std_logic;
signal opb_seqaddr_s0_d1 : std_logic;
signal bus2ip_burst_s1 : std_logic;
signal bus2ip_burst_s1_d1 : std_logic;
signal opb_seqaddr_d1 : std_logic;
signal opb_abus_s0 : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal opb_dbus_s0 : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal opb_be_s0 : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal bus2ip_rnw_s1 : std_logic;
signal bus2ip_be_s0 : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal bus2ip_be_s1 : std_logic_vector(0 to C_OPB_DWIDTH/8-1) := (others => '0');
signal bus2ip_cs_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_s0_d1 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_s1 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_hit_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_hit : std_logic_vector(0 to NUM_ARDS-1); -- GAB 10/12/05
signal bus2ip_cs_hit_s0_d1 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_enable_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_ce_s0 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_ce_s1 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_rdce_s0 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_rdce_s1 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_wrce_s0 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_wrce_s1 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_addr_s0 : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal bus2ip_addr_s1 : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal bus2ip_addrvalid_s1 : std_logic;
signal bus2ip_data_s0 : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal bus2ip_data_s1 : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal devicesel_s0 : std_logic;
signal devicesel : std_logic; -- GAB 10/12/05
-- ALS - added address counter signals
signal address_load : std_logic;
signal opb_addr_cntr_out : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal next_opb_addr_cntr_out : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal next_steer_addr_cntr_out : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal steer_addr_cntr_out : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal opb_be_cntr_out : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal opb_be_cntr_steer : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
-- ALS - added bus2ip_rdreq and bus2ip_wrreq and signals to support their
-- generation
signal rdreq : std_logic;
signal rdreq_hold : std_logic;
signal rdreq_hold_rst : std_logic;
signal bus2ip_rdreq_s0 : std_logic;
signal bus2ip_rdreq_s1 : std_logic;
signal Bus2IP_RdReq : std_logic; --REMOVE IF THIS BECOMES A PORT
signal wrreq : std_logic;
signal wrreq_hold : std_logic;
signal wrreq_hold_rst : std_logic;
signal bus2ip_wrreq_s0 : std_logic;
signal bus2ip_wrreq_s1 : std_logic;
signal Bus2IP_WrReq : std_logic; --REMOVE IF THIS BECOMES A PORT
-- ALS added write buffer signals
signal wrbuf_data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal wrbuf_be : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal wrbuf_burst : std_logic;
signal wrbuf_xferack : std_logic;
signal wrbuf_errack : std_logic;
signal wrbuf_retry : std_logic;
signal wrbuf_cs : std_logic_vector(0 to NUM_ARDS-1);
signal wrbuf_rnw : std_logic;
signal wrbuf_ce : std_logic_vector(0 to NUM_CES-1);
signal wrbuf_wrce : std_logic_vector(0 to NUM_CES-1);
signal wrbuf_rdce : std_logic_vector(0 to NUM_CES-1);
signal wrbuf_empty : std_logic;
signal wrbuf_addrcntr_en : std_logic;
signal wrbuf_addrcntr_rst : std_logic;
signal wrbuf_addrvalid : std_logic;
signal ipic_pstage_ce : std_logic;
signal wrdata_ack : std_logic;
signal wrbuf_addrack : std_logic;
-- ALS added transfer start and done signals
signal opb_xfer_done : std_logic;
signal opb_xfer_start : std_logic;
constant NUM_ENCODED_SIZE_BITS : natural := 3;
type OR_CSES_PER_BIT_TABLE_TYPE is array(0 to NUM_ENCODED_SIZE_BITS-1) of
std_logic_vector(0 to NUM_ARDS-1);
signal cs_to_or_for_dsize_bit : OR_CSES_PER_BIT_TABLE_TYPE;
signal encoded_dsize_s0 : std_logic_vector(0
to NUM_ENCODED_SIZE_BITS-1);
signal encoded_dsize_s1 : std_logic_vector(0
to NUM_ENCODED_SIZE_BITS-1);
signal ip2bus_data_mx : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal sln_dbus_s1 : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal sln_dbus_s2 : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal ipic_xferack : std_logic;
signal sln_xferack_s1 : std_logic;
signal sln_xferack_s1_d1 : std_logic;
signal sln_xferack_s1_d2 : std_logic;
signal sln_xferack_s2 : std_logic;
signal sln_retry_s1 : std_logic;
signal sln_retry_s1_d1 : std_logic;
signal sln_retry_s1_d2 : std_logic;
signal sln_retry_s2 : std_logic;
signal sln_errack_s1 : std_logic;
signal sln_errack_s2 : std_logic;
signal sln_toutsup_s1 : std_logic;
signal sln_toutsup_s2 : std_logic;
signal reset2bus_data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal reset2bus_ack : std_logic;
signal reset2bus_error : std_logic;
signal reset2bus_retry : std_logic;
signal reset2bus_toutsup : std_logic;
signal reset2bus_postedwrinh : std_logic;
-- interrupt signals
signal intr2bus_data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal intr2bus_rdack : std_logic;
signal intr2bus_wrack : std_logic;
signal intr2bus_ack : std_logic;
signal intr2bus_error : std_logic;
signal intr2bus_retry : std_logic;
signal intr2bus_toutsup : std_logic;
signal intr2bus_postedwrinh : std_logic;
-- FIFO signals
signal rfifo_error : std_logic;
signal rfifo_rdack : std_logic;
signal rfifo_retry : std_logic;
signal rfifo_toutsup : std_logic;
signal rfifo_wrack : std_logic;
signal rdfifo_ack : std_logic;
signal rdfifo2bus_data : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal rdfifo2intr_deadlock : std_logic;
signal wfifo_error : std_logic;
signal wfifo_rdack : std_logic;
signal wfifo_retry : std_logic;
signal wfifo_toutsup : std_logic;
signal wfifo_wrack : std_logic;
signal wrfifo_ack : std_logic;
signal wrfifo2bus_data : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal wrfifo2intr_deadlock : std_logic;
signal new_pw_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal new_pw_s0_d1 : std_logic_vector(0 to NUM_ARDS-1);
signal inh_cs_when_pw : std_logic_vector(0 to NUM_ARDS-1);
signal inh_cs_wnot_pw : std_logic;
signal inh_xferack_when_pw : std_logic;
signal inh_xferack_when_burst_rd: std_logic;
signal last_xferack : std_logic;
signal last_xferack_s0 : std_logic;
signal last_xferack_d1 : std_logic;
signal last_xferack_d1_s0 : std_logic;
signal last_xferack_d2 : std_logic;
signal last_pw_xferack : std_logic;
signal last_pw_xferack_d1 : std_logic;
signal last_pw_xferack_d2 : std_logic;
-- signal last_wr_xferack : std_logic;
-- signal last_wr_xferack_d1 : std_logic;
-- signal last_wr_xferack_d2 : std_logic;
signal last_burstrd_xferack : std_logic;
signal last_burstrd_xferack_d1 : std_logic;
signal last_burstrd_xferack_d2 : std_logic;
signal OPB_seqAddr_eff : std_logic;
signal postedwr_s0 : std_logic;
signal postedwrack_s2 : std_logic;
signal cycle_abort : std_logic;
signal cycle_abort_d1 : std_logic;
signal xfer_abort : std_logic;
signal cycle_active : std_logic;
signal ip2bus_postedwrinh_s1 : std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
signal ip2bus_postedwrinh_s2 : std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
signal ip2bus_postedwrinh_s2_d1 : std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
signal ip2bus_postedwrinh_s2_d2 : std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
signal ip2bus_xferack : std_logic;
-------------------------------------------------------------------------------
begin
OPB_seqAddr_eff <= OPB_seqAddr and bo2sl(C_DEV_BURST_ENABLE=1);
bus2ip_clk_i <= OPB_Clk;
Bus2IP_Clk <= OPB_Clk;
Bus2IP_Freeze <= Freeze;
reset2bus_postedwrinh <= '1'; --GB
intr2bus_postedwrinh <= '1';
---------------------------------------------------------------------------
-- Pipeline Stage 0
---------------------------------------------------------------------------
GEN_PSTAGE0: if INCLUDE_OPBIN_PSTAGE generate
begin
PROC_PSTAGE0 : process(bus2ip_clk_i)
begin
--------------------------------------------------------------------
-- Sigs that need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if Reset = '1' then
opb_select_s0 <= '0';
bus2ip_cs_hit_s0 <= (others => '0'); -- GAB 10/12/05
else
opb_select_s0 <= OPB_select;
bus2ip_cs_hit_s0 <= bus2ip_cs_hit; -- GAB 10/12/05
end if;
end if;
--------------------------------------------------------------------
-- Sigs that do not need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
opb_rnw_s0 <= OPB_RNW;
opb_seqaddr_s0 <= OPB_seqAddr_eff;
opb_abus_s0 <= OPB_ABus;
opb_dbus_s0 <= OPB_DBus;
opb_be_s0 <= OPB_BE;
last_xferack_s0 <= last_xferack;
last_xferack_d1_s0 <= last_xferack_d1;
end if;
end process;
end generate;
--
GEN_BYPASS0: if not INCLUDE_OPBIN_PSTAGE generate
begin
opb_select_s0 <= OPB_select;
opb_rnw_s0 <= OPB_RNW;
opb_seqaddr_s0 <= OPB_seqAddr_eff;
opb_abus_s0 <= OPB_ABus;
opb_dbus_s0 <= OPB_DBus;
opb_be_s0 <= OPB_BE;
last_xferack_s0 <= last_xferack;
last_xferack_d1_s0 <= last_xferack_d1;
bus2ip_cs_hit_s0 <= bus2ip_cs_hit; -- GAB 10/12/05
end generate;
---------------------------------------------------------------------------
-- Pipeline Stage 1
---------------------------------------------------------------------------
GEN_PSTAGE1: if INCLUDE_IPIC_PSTAGE generate
begin
-- RdReq and WrReq need to be registered for this stage independent
-- of write buffer inclusion
PROC_PSTAGE1_RDWR_REQ : process(bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if Reset = '1' then
-- ALS - added bus2ip_rdreq and bus2ip_wrreq
bus2ip_rdreq_s1 <= '0';
bus2ip_wrreq_s1 <= '0';
encoded_dsize_s1 <= (others => '0');
else
bus2ip_rdreq_s1 <= bus2ip_rdreq_s0;
bus2ip_wrreq_s1 <= bus2ip_wrreq_s0;
encoded_dsize_s1 <= encoded_dsize_s0;
end if;
end if;
end process PROC_PSTAGE1_RDWR_REQ;
-- Write Buffer takes place of IPIC PSTAGE for the remaining signals
-- register in this stage only if Write Buffer is not included
WRBUF_IPIC_PSTAGE_GEN: if C_INCLUDE_WR_BUF = 1 generate
bus2ip_cs_s1 <= wrbuf_cs;
bus2ip_ce_s1 <= wrbuf_ce;
bus2ip_wrce_s1 <= wrbuf_wrce;
bus2ip_rdce_s1 <= wrbuf_rdce;
bus2ip_data_s1 <= wrbuf_data;
bus2ip_rnw_s1 <= wrbuf_rnw;
bus2ip_burst_s1 <= wrbuf_burst;
bus2ip_addrvalid_s1 <= wrbuf_addrvalid;
bus2ip_be_s1 <= wrbuf_be;
bus2ip_addr_s1 <= opb_addr_cntr_out;
end generate WRBUF_IPIC_PSTAGE_GEN;
NOWRBUF_IPIC_PSTAGE_GEN: if C_INCLUDE_WR_BUF = 0 generate
begin
PROC_PSTAGE1 : process(bus2ip_clk_i)
begin
--------------------------------------------------------------------
-- Sigs that need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if Reset = '1' then
bus2ip_cs_s1 <= (others => '0');
bus2ip_ce_s1 <= (others => '0');
bus2ip_rdce_s1 <= (others => '0');
bus2ip_wrce_s1 <= (others => '0');
bus2ip_addrvalid_s1 <= '0';
else
bus2ip_cs_s1 <= wrbuf_cs;
bus2ip_ce_s1 <= wrbuf_ce;
bus2ip_wrce_s1 <= wrbuf_wrce;
bus2ip_rdce_s1 <= wrbuf_rdce;
bus2ip_addrvalid_s1 <= wrbuf_addrvalid;
end if;
end if;
--------------------------------------------------------------------
-- Sigs that do not need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
bus2ip_data_s1 <= wrbuf_data;
bus2ip_rnw_s1 <= wrbuf_rnw;
bus2ip_burst_s1 <= wrbuf_burst;
end if;
end process PROC_PSTAGE1;
-- If the address counter is included, it represents the S1 register stage
-- It is just necessary to register the BEs
-- If the address counter is not included, create the register stage for both
-- the address and the BEs
ADDRCNT_IPIC_STAGE: if INCLUDE_ADDR_CNTR generate
bus2ip_addr_s1 <= opb_addr_cntr_out;
ADDRCNT_IPIC_REG_PROC : process(bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
bus2ip_be_s1 <= wrbuf_be; -- BEs output from steering logic
end if;
end process ADDRCNT_IPIC_REG_PROC;
end generate ADDRCNT_IPIC_STAGE;
NOADDRCNT_IPIC_STAGE: if not(INCLUDE_ADDR_CNTR) generate
NOADDRCNT_IPIC_REG_PROC : process(bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
bus2ip_addr_s1 <= opb_addr_cntr_out;
bus2ip_be_s1 <= wrbuf_be; -- BEs output from steering logic
end if;
end process NOADDRCNT_IPIC_REG_PROC;
end generate NOADDRCNT_IPIC_STAGE;
end generate NOWRBUF_IPIC_PSTAGE_GEN;
end generate GEN_PSTAGE1;
--
GEN_BYPASS1: if not INCLUDE_IPIC_PSTAGE generate
begin
bus2ip_cs_s1 <= wrbuf_cs;
bus2ip_ce_s1 <= wrbuf_ce;
bus2ip_wrce_s1 <= wrbuf_wrce;
bus2ip_data_s1 <= wrbuf_data;
bus2ip_rnw_s1 <= wrbuf_rnw;
bus2ip_burst_s1 <= wrbuf_burst;
bus2ip_addrvalid_s1 <= wrbuf_addrvalid;
encoded_dsize_s1 <= encoded_dsize_s0;
bus2ip_rdce_s1 <= wrbuf_rdce;
bus2ip_addr_s1 <= opb_addr_cntr_out;
bus2ip_be_s1 <= wrbuf_be;
-- ALS - added bus2ip_rdreq and bus2ip_wrreq
bus2ip_rdreq_s1 <= bus2ip_rdreq_s0;
bus2ip_wrreq_s1 <= bus2ip_wrreq_s0;
end generate GEN_BYPASS1;
Bus2IP_CS <= bus2ip_cs_s1;
Bus2IP_CE <= bus2ip_ce_s1;
Bus2IP_RdCE <= bus2ip_rdce_s1;
Bus2IP_WrCE <= bus2ip_wrce_s1;
Bus2IP_Addr <= bus2ip_addr_s1;
Bus2IP_Data <= bus2ip_data_s1;
Bus2IP_BE <= bus2ip_be_s1;
Bus2IP_RNW <= bus2ip_rnw_s1;
Bus2IP_Burst <= bus2ip_burst_s1 and or_reduce(bus2ip_cs_s1);
Bus2IP_AddrValid <= bus2ip_addrvalid_s1;
-- ALS - added Bus2IP_RdReq and Bus2IP_WrReq
-- ToDo - determine if these should be ports
Bus2IP_RdReq <= bus2ip_rdreq_s1;
Bus2IP_WrReq <= bus2ip_wrreq_s1;
ip2bus_postedwrinh_s1 <= IP2Bus_PostedWrInh; --GB
---------------------------------------------------------------------------
-- Pipeline Stage 2
---------------------------------------------------------------------------
GEN_PSTAGE2: if INCLUDE_OPBOUT_PSTAGE generate
begin
PROC_PSTAGE2 : process(bus2ip_clk_i)
begin
--------------------------------------------------------------------
-- Sigs that need to be reset by OPB_Select
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if OPB_Select = '0' then
sln_xferack_s2 <= '0';
sln_errack_s2 <= '0';
sln_retry_s2 <= '0';
sln_toutsup_s2 <= '0';
-- ip2bus_postedwrinh_s2 <= (others => '0'); --GB
else
sln_xferack_s2 <= sln_xferack_s1 and not cycle_abort ;
sln_retry_s2 <= sln_retry_s1 ;
sln_errack_s2 <= sln_errack_s1 ;
sln_toutsup_s2 <= sln_toutsup_s1;
-- ip2bus_postedwrinh_s2 <= ip2bus_postedwrinh_s1; --GB
end if;
end if;
--------------------------------------------------------------------
-- Sigs that need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if (Reset or not (sln_xferack_s1 and bus2ip_rnw_s1)) = '1' then
sln_dbus_s2 <= (others => '0');
else
sln_dbus_s2 <= sln_dbus_s1;
end if;
end if;
--------------------------------------------------------------------
-- Sigs that do not need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
postedwrack_s2 <= postedwr_s0;
ip2bus_postedwrinh_s2 <= ip2bus_postedwrinh_s1; --GB
end if;
end process;
end generate;
--
GEN_BYPASS2: if not INCLUDE_OPBOUT_PSTAGE generate
begin
sln_dbus_s2 <= sln_dbus_s1;
sln_xferack_s2 <= sln_xferack_s1 and OPB_Select;
sln_retry_s2 <= sln_retry_s1 and OPB_Select;
sln_errack_s2 <= sln_errack_s1 and OPB_Select;
sln_toutsup_s2 <= sln_toutsup_s1 and OPB_Select;
postedwrack_s2 <= postedwr_s0;
ip2bus_postedwrinh_s2 <= ip2bus_postedwrinh_s1; --GB
end generate;
Sln_Dbus <= sln_dbus_s2;
Sln_xferAck <= sln_xferack_s2 and OPB_Select; --GB
Sln_retry <= sln_retry_s2 and OPB_Select; --GB
-- Sln_xferAck <= sln_xferack_s2 and OPB_Select and not(xfer_abort); --GB
-- Sln_retry <= (sln_retry_s2 or cycle_abort) and OPB_Select; --GB
Sln_errAck <= sln_errack_s2 and OPB_Select;
Sln_toutSup <= sln_toutsup_s2;
-----------------------------------------------------------------------------
-- Extend burst signal by 1 clock
-----------------------------------------------------------------------------
BURST_EXTEND_PROCESS: process (bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i = '1' then
opb_seqaddr_s0_d1 <= opb_seqaddr_s0;
end if;
end process;
------------------------------------------------------------------------------
-- Generation of devicesel_s0
-----------------------------------------------------------------------------
DEVICESEL_S0_I: entity opb_v20_v1_10_d.pselect
generic map (
C_AB => K_DEV_ADDR_DECODE_WIDTH,
C_AW => C_OPB_AWIDTH,
C_BAR => C_ARD_ADDR_RANGE_ARRAY(0)
( C_ARD_ADDR_RANGE_ARRAY(0)'length-C_OPB_AWIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length-1
)
)
port map (
-- A => opb_abus_s0, -- GAB 10/12/05
-- AValid => opb_select_s0, -- GAB 10/12/05
-- CS => devicesel_s0 -- GAB 10/12/05
A => OPB_abus, -- GAB 10/12/05
AValid => OPB_select, -- GAB 10/12/05
CS => devicesel -- GAB 10/12/05
);
------------------------------------------------------------------------------
-- Determination of clock periods on which IPIC transactions are blocked
-- from starting, either because
-- (1) an acknowledged IPIC transaction is finishing and being cleared
-- from the pipeline, or
-- (2) the posted-write pipeline is filling.
-----------------------------------------------------------------------------
DELAYS_FOR_BLK_PROC : process (OPB_Clk) is
begin
if OPB_Clk'event and OPB_Clk='1' then
sln_xferack_s1_d1 <= sln_xferack_s1;
sln_xferack_s1_d2 <= sln_xferack_s1_d1;
sln_retry_s1_d1 <= sln_retry_s1;
sln_retry_s1_d2 <= sln_retry_s1_d1;
opb_select_s0_d1 <= opb_select_s0;
new_pw_s0_d1 <= new_pw_s0;
opb_seqaddr_d1 <= OPB_seqAddr_eff;
-- last_wr_xferack_d1 <= last_wr_xferack;
-- last_wr_xferack_d2 <= last_wr_xferack_d1;
last_burstrd_xferack_d1 <= last_burstrd_xferack;
last_burstrd_xferack_d2 <= last_burstrd_xferack_d1;
bus2ip_cs_hit_s0_d1 <= bus2ip_cs_hit_s0;
ip2bus_postedwrinh_s2_d1 <= ip2bus_postedwrinh_s2;
ip2bus_postedwrinh_s2_d2 <= ip2bus_postedwrinh_s2_d1;
end if;
end process;
--ToDo, can bus2ip_clk_i be used on the above, as below?
DX_FFS_PROC : process (bus2ip_clk_i) is
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
last_xferack_d1 <= last_xferack;
last_xferack_d2 <= last_xferack_d1;
last_pw_xferack_d1 <= last_pw_xferack;
last_pw_xferack_d2 <= last_pw_xferack_d1;
end if;
end process;
-- Code below works with Write buffer included
-- inh_cs_wnot_pw <= bo2sl(
-- not (opb_rnw_s0='1' and OPB_seqAddr_s0='1')
-- -- Do not
-- and -- inhibit when a burst read
-- (
-- (sln_xferack_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE or INCLUDE_OPBOUT_PSTAGE))
--
--
-- or (sln_xferack_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE and INCLUDE_OPBOUT_PSTAGE))
--
--
-- or (sln_retry_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE or INCLUDE_OPBOUT_PSTAGE))
--
-- or (sln_retry_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE and INCLUDE_OPBOUT_PSTAGE))
-- )
-- );
--
-- -- ABove works when burst enable, pipeline model 2, no writebuffer, doing back to back write/reads
-- -- But causes interrupts/ pfifo tests to fail
--
--
-- original code
INH_CS_NOWRBUF_GEN : if C_INCLUDE_WR_BUF = 0 generate
inh_cs_wnot_pw <= bo2sl
(
-- Do not inhibit when a burst read
not (opb_rnw_s0='1' and opb_seqaddr_s0='1')
and
(
(sln_xferack_s1='1' and (INCLUDE_IPIC_PSTAGE))
or
(sln_xferack_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE
or INCLUDE_OPBOUT_PSTAGE))
or
(sln_xferack_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE
and INCLUDE_OPBOUT_PSTAGE))
or
(sln_retry_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE
or INCLUDE_OPBOUT_PSTAGE))
or
(sln_retry_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE
and INCLUDE_OPBOUT_PSTAGE))
)
);
end generate;
INH_CS_WRBUF_GEN : if C_INCLUDE_WR_BUF = 1 generate
inh_cs_wnot_pw <= bo2sl
(
-- Do not inhibit when a burst read
not (opb_rnw_s0='1' and opb_seqaddr_s0_d1='1')
and
(
(sln_xferack_s1='1' and (INCLUDE_IPIC_PSTAGE))
or
(sln_xferack_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE
or INCLUDE_OPBOUT_PSTAGE))
or
(sln_xferack_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE
and INCLUDE_OPBOUT_PSTAGE))
)
);
end generate;
-- GB - Removed check of postedwrinh when write buffer is instantiated. Write buffer
-- logic does not have postedwrinh implemented yet and this was causing a problem
-- with some of the configurations. When the write buffer is instantiated the
-- postedwrinh signal is ignored.
GEN_INH_CS_WPW_NO_WRBUF : if C_INCLUDE_WR_BUF = 0 generate
INH_CS_WHEN_PW_GEN: for i in 0 to NUM_ARDS-1 generate
begin
new_pw_s0(i) <= ((bus2ip_cs_hit_s0(i) and not bus2ip_cs_hit_s0_d1(i))
or (last_xferack_d1_s0 and opb_select_s0))
and not opb_rnw_s0
and not eff_ip2bus_val(
i => i,
rst => reset2bus_postedwrinh,
intr => intr2bus_postedwrinh,
wrfifo => '0',
rdfifo => '0',
user => ip2bus_postedwrinh(i));
inh_cs_when_pw(i) <= bo2sl(
(new_pw_s0(i)='1' and (INCLUDE_OPBIN_PSTAGE or
INCLUDE_OPBOUT_PSTAGE))
or
(new_pw_s0_d1(i)='1' and (INCLUDE_OPBIN_PSTAGE and
INCLUDE_OPBOUT_PSTAGE))
);
end generate;
end generate GEN_INH_CS_WPW_NO_WRBUF;
GEN_INH_CS_WPW_WRBUF : if C_INCLUDE_WR_BUF = 1 generate --GB
INH_CS_WHEN_PW_GEN: for i in 0 to NUM_ARDS-1 generate
begin
new_pw_s0(i) <= ((bus2ip_cs_hit_s0(i) and not bus2ip_cs_hit_s0_d1(i))
or (last_xferack_d1_s0 and opb_select_s0))
and not opb_rnw_s0;
inh_cs_when_pw(i) <= bo2sl(
(new_pw_s0(i)='1' and (INCLUDE_OPBIN_PSTAGE or
INCLUDE_OPBOUT_PSTAGE))
or (new_pw_s0_d1(i)='1' and (INCLUDE_OPBIN_PSTAGE and
INCLUDE_OPBOUT_PSTAGE))
);
end generate;
end generate GEN_INH_CS_WPW_WRBUF;
-- GB - Removed check of postedwrinh when write buffer is instantiated. Write buffer
-- logic does not have postedwrinh implemented yet and this was causing a problem
-- with some of the configurations. When the write buffer is instantiated the
-- postedwrinh signal is ignored.
GEN_PWI_PROC_NO_WRBUF : if C_INCLUDE_WR_BUF = 0 generate
POSTEDWRINH_PROC: process(reset2bus_postedwrinh, intr2bus_postedwrinh,
ip2bus_postedwrinh, bus2ip_cs_hit_s0,
opb_rnw_s0)
variable r : std_logic;
begin
r := '0';
for i in 0 to NUM_ARDS-1 loop
r := r or ( bus2ip_cs_hit_s0(i)
and not eff_ip2bus_val(
i => i,
rst => reset2bus_postedwrinh,
intr => intr2bus_postedwrinh,
wrfifo => '0',
rdfifo => '0',
user => ip2bus_postedwrinh(i)
)
);
end loop;
postedwr_s0 <= bo2sl(r='1' and not opb_rnw_s0='1'); --and C_DEV_BURST_ENABLE=1);--GB
end process;
end generate GEN_PWI_PROC_NO_WRBUF;
GEN_PWI_PROC_WRBUF : if C_INCLUDE_WR_BUF = 1 generate --GB
POSTEDWRINH_PROC: process(reset2bus_postedwrinh, intr2bus_postedwrinh,
bus2ip_cs_hit_s0, opb_rnw_s0)
variable r : std_logic;
begin
r := '0';
for i in 0 to NUM_ARDS-1 loop
r := r or bus2ip_cs_hit_s0(i);
end loop;
postedwr_s0 <= bo2sl(r='1' and not opb_rnw_s0='1' and C_DEV_BURST_ENABLE=1);
end process;
end generate GEN_PWI_PROC_WRBUF;
last_xferack <= sln_xferack_s2
and not OPB_seqAddr_eff
and not(last_xferack_d1);
last_burstrd_xferack <= sln_xferack_s2
and (not OPB_seqAddr_eff and opb_seqaddr_d1) -- falling edge of burst
and not(last_xferack_d1);
inh_xferack_when_burst_rd <= not(or_reduce(new_pw_s0)) and
( (last_burstrd_xferack and bo2sl(INCLUDE_OPBOUT_PSTAGE))
or (last_burstrd_xferack_d1 and bo2sl(INCLUDE_OPBIN_PSTAGE or
INCLUDE_IPIC_PSTAGE))
or (last_burstrd_xferack_d2 and bo2sl(INCLUDE_OPBIN_PSTAGE and
INCLUDE_IPIC_PSTAGE)) );
last_pw_xferack <= sln_xferack_s2 and not OPB_seqAddr_eff and postedwrack_s2;
inh_xferack_when_pw <=
bo2sl((last_pw_xferack='1' and (INCLUDE_OPBOUT_PSTAGE))
or
(last_pw_xferack_d1='1' and (INCLUDE_OPBIN_PSTAGE or
INCLUDE_IPIC_PSTAGE))
or (last_pw_xferack_d2='1' and (INCLUDE_OPBIN_PSTAGE and
INCLUDE_IPIC_PSTAGE)) );
-----------------------------------------------------------------------------
-- ALS: added register to extend burst signal 1 clock
-----------------------------------------------------------------------------
BUS2IP_BURST_EXTEND_PROCESS: process (bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i = '1' then
bus2ip_burst_s1_d1 <= bus2ip_burst_s1;
end if;
end process BUS2IP_BURST_EXTEND_PROCESS;
-----------------------------------------------------------------------------
-- Start and end of transaction detection
-----------------------------------------------------------------------------
opb_xfer_done <= (last_xferack
or sln_retry_s2
-- detected master abort (required for some pipe models)
or (xfer_abort )
-- master abort
or (not(opb_select_s0) and (opb_select_s0_d1) ) );
-- Not being used
-- XFER_DONE_REG_I: FDR
-- port map (
-- Q => opb_xfer_done_d1, --[out]
-- C => bus2ip_clk_i, --[in]
-- D => opb_xfer_done, --[in]
-- R => bus2ip_reset_i --[in]
-- );
-- New xfer starts when any CS is asserted and on the next clock
-- after xfer done if select is still asserted, or on the rising edge
-- of select
opb_xfer_start <= (or_reduce(bus2ip_cs_hit_s0) and not xfer_abort and --GB
( (opb_select_s0 and last_xferack_d1_s0)
or (opb_select_s0 and not(opb_select_s0_d1)) ) );
------------------------------------------------------------------------------
-- ALS: added address counter and BE generator
-- Generation of address counter and BE generator
-- When the IPIC pipe stage is included, a registered counter is used. The counter
-- register acts as the IPIC pipe stage register. The CE
-- generation logic needs the next address count so that the output CEs are
-- in alignment with the address
-- When the IPIC pipe stage is not included, a direct path counter is used.
-- The next address count is the same as the address count and the output CEs
-- will align with the address.
-- Steer address counter generates the addresses on each IP2Bus Ack
-- for use in generating the byte enables
------------------------------------------------------------------------------
ADDRCNT_BE_GEN: if INCLUDE_ADDR_CNTR or C_INCLUDE_WR_BUF = 1 generate
signal byte_xfer : std_logic;
signal hw_xfer : std_logic;
signal fw_xfer : std_logic;
signal addrcntr_en : std_logic;
signal steeraddr_cnt_en : std_logic;
begin
addrcntr_en <= IP2Bus_AddrAck
and wrbuf_addrcntr_en
and bus2ip_burst_s1;
steeraddr_cnt_en <= IP2Bus_Ack and bus2ip_burst_s1;
address_load <= opb_xfer_start and wrbuf_empty;
BE_GEN_I: entity opb_v20_v1_10_d.opb_be_gen
generic map (
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_INCLUDE_WR_BUF => C_INCLUDE_WR_BUF
)
port map (
Bus_clk => bus2ip_clk_i,
Address_in => next_steer_addr_cntr_out,
BE_in => opb_be_s0,
Load_BE => address_load,
Rst_BE => bus2ip_reset_i,
BE_out => opb_be_cntr_out,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer
);
DIRECTPATH_CNTR_GEN: if not(INCLUDE_IPIC_PSTAGE) and C_INCLUDE_WR_BUF=0 generate
-- since no IPIC pipe stage, use direct path cntr so that there is not
-- a clock delay for loading the address
signal addr_cntr_load : std_logic;
begin
addr_cntr_load <= not((or_reduce(bus2ip_cs_hit_s0))) or opb_xfer_done;
BUS2IPADDR_CNTR_I: entity opb_v20_v1_10_d.brst_addr_cntr
generic map (
C_CNTR_WIDTH => MAX_USER_ADDR_RANGE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH )
port map (
Address_in => opb_abus_s0,
Addr_load => addr_cntr_load,
Addr_CntEn => addrcntr_en,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer,
Address_out => opb_addr_cntr_out,
OPB_Clk => bus2ip_clk_i);
-- since directpath cntr, next count value is the same as the count value
next_opb_addr_cntr_out <= opb_addr_cntr_out;
STEERADDR_CNTR_I: entity opb_v20_v1_10_d.brst_addr_cntr
generic map (
C_CNTR_WIDTH => MAX_USER_ADDR_RANGE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH )
port map (
Address_in => opb_abus_s0,
Addr_load => addr_cntr_load,
Addr_CntEn => steeraddr_cnt_en,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer,
Address_out => steer_addr_cntr_out,
OPB_Clk => bus2ip_clk_i);
-- since directpath cntr, next count value is the same as the count value
next_steer_addr_cntr_out <= steer_addr_cntr_out;
end generate DIRECTPATH_CNTR_GEN;
REG_CNTR_GEN: if INCLUDE_IPIC_PSTAGE or C_INCLUDE_WR_BUF = 1 generate
-- since IPIC pipe stage, use registered counter. This will act as the pipe stage
-- for the address. The CEs will use the un-registered counter address so that
-- they align with the address after going through the pipe stage
BUS2IPADDR_CNTR_I: entity opb_v20_v1_10_d.brst_addr_cntr_reg
generic map (
C_CNTR_WIDTH => MAX_USER_ADDR_RANGE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH)
port map (
Bus_reset => bus2ip_reset_i,
Bus_clk => bus2ip_clk_i,
Xfer_done => opb_xfer_done,
RNW => wrbuf_rnw,
Addr_Load => address_load,
Addr_Cnt_en => addrcntr_en,
Addr_Cnt_rst => wrbuf_addrcntr_rst,
Address_In => opb_abus_s0,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer,
Next_address_out => next_opb_addr_cntr_out,
Address_Out => opb_addr_cntr_out
);
STEERADDR_CNTR_I: entity opb_v20_v1_10_d.brst_addr_cntr_reg
generic map (
C_CNTR_WIDTH => MAX_USER_ADDR_RANGE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH)
port map (
Bus_reset => bus2ip_reset_i,
Bus_clk => bus2ip_clk_i,
Xfer_done => opb_xfer_done,
RNW => wrbuf_rnw,
Addr_Load => address_load,
Addr_Cnt_en => steeraddr_cnt_en,
Addr_Cnt_rst => bus2ip_reset_i,
Address_In => opb_abus_s0,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer,
Next_address_out => next_steer_addr_cntr_out,
Address_Out => steer_addr_cntr_out
);
end generate REG_CNTR_GEN;
end generate ADDRCNT_BE_GEN;
NO_ADDRCNT_BE_GEN: if not(INCLUDE_ADDR_CNTR) and C_INCLUDE_WR_BUF = 0 generate
next_opb_addr_cntr_out <= opb_abus_s0;
opb_addr_cntr_out <= opb_abus_s0;
next_steer_addr_cntr_out<= opb_abus_s0;
steer_addr_cntr_out <= opb_abus_s0;
opb_be_cntr_out <= opb_be_s0;
address_load <= '1';
end generate NO_ADDRCNT_BE_GEN;
-----------------------------------------------------------------------------
-- Generation of Write Buffer
-----------------------------------------------------------------------------
WRITE_BUFFER_GEN: if C_INCLUDE_WR_BUF = 1 generate
begin
wrbuf_addrack <= IP2Bus_AddrAck;
wrdata_ack <= '1' when (ipic_xferack='1' and wrbuf_rnw='0')
else '0';
WRITE_BUF: entity opb_v20_v1_10_d.write_buffer
generic map ( C_INCLUDE_OPBIN_PSTAGE => INCLUDE_OPBIN_PSTAGE,
C_INCLUDE_IPIC_PSTAGE => INCLUDE_IPIC_PSTAGE,
C_INCLUDE_OPBOUT_PSTAGE => INCLUDE_OPBOUT_PSTAGE,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_WRBUF_DEPTH => WRBUF_DEPTH,
C_NUM_CES => NUM_CES,
C_NUM_ARDS => NUM_ARDS
)
port map (
Bus_reset => bus2ip_reset_i,
Bus_clk => bus2ip_clk_i,
Data_in => bus2ip_data_s0,
CE => bus2ip_ce_s0,
Wr_CE => bus2ip_wrce_s0,
Rd_CE => bus2ip_rdce_s0,
RNW => opb_rnw_s0,
CS_hit => bus2ip_cs_hit_s0,
CS => bus2ip_cs_s0,
CS_enable => bus2ip_cs_enable_s0,
Burst => opb_seqaddr_s0,
Xfer_start => opb_xfer_start,
Xfer_done => opb_xfer_done,
Addr_ack => wrbuf_addrack,
Wrdata_ack => wrdata_ack,
WrBuf_data => wrbuf_data,
WrBuf_burst => wrbuf_burst,
WrBuf_xferack => wrbuf_xferack,
WrBuf_errack => wrbuf_errack,
WrBuf_retry => wrbuf_retry,
WrBuf_CS => wrbuf_cs,
WrBuf_RNW => wrbuf_rnw,
WrBuf_CE => wrbuf_ce,
WrBuf_WrCE => wrbuf_wrce,
WrBuf_RdCE => wrbuf_rdce,
WrBuf_Empty => wrbuf_empty,
WrBuf_AddrCnt_en => wrbuf_addrcntr_en,
WrBuf_AddrCntr_rst => wrbuf_addrcntr_rst,
WrBuf_AddrValid => wrbuf_addrvalid,
IPIC_Pstage_CE => ipic_pstage_ce
);
-- inclusion of write buffer requires the BEs to be registered
BE_REG_PROC : process(bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if bus2ip_reset_i = '1' then
wrbuf_be <= (others => '0');
else
wrbuf_be <= opb_be_cntr_steer;
end if;
end if;
end process BE_REG_PROC;
end generate WRITE_BUFFER_GEN;
NO_WRITE_BUFFER_GEN: if C_INCLUDE_WR_BUF = 0 generate
begin
wrbuf_data <= bus2ip_data_s0;
wrbuf_burst <= opb_seqaddr_s0;
wrbuf_xferack <= '0';
wrbuf_errack <= '0';
wrbuf_retry <= '0';
wrbuf_cs <= bus2ip_cs_s0;
wrbuf_rnw <= opb_rnw_s0;
wrbuf_ce <= bus2ip_ce_s0;
wrbuf_wrce <= bus2ip_wrce_s0;
wrbuf_rdce <= bus2ip_rdce_s0;
wrbuf_empty <= '1';
wrbuf_addrcntr_en <= '1';
wrbuf_addrcntr_rst <= '0';
wrbuf_addrvalid <= or_reduce(bus2ip_ce_s0);
wrbuf_be <= opb_be_cntr_steer;
ipic_pstage_ce <= '1';
end generate NO_WRITE_BUFFER_GEN;
------------------------------------------------------------------------------
-- Generation of per-address-range mechanism.
------------------------------------------------------------------------------
PER_AR_GEN: for i in 0 to NUM_ARDS-1 generate
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,i);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= log2(C_ARD_NUM_CE_ARRAY(i));
constant OFFSET : integer
:= log2(C_ARD_DWIDTH_ARRAY(i)/8);
-- OFFSET gives the number of address bits corresponding to the
-- DWIDTH of the address range, e.g. zero for bytes, 1 for
-- doublets, 2 for quadlets, 3 for octlets, etc.
begin
--------------------------------------------------------------------------
-- CS decoders
--------------------------------------------------------------------------
CS_I: entity opb_v20_v1_10_d.pselect
generic map (
C_AB => - K_DEV_ADDR_DECODE_WIDTH
+ num_decode_bits(C_ARD_ADDR_RANGE_ARRAY,
C_OPB_AWIDTH,
i),
C_AW => C_OPB_AWIDTH - K_DEV_ADDR_DECODE_WIDTH,
C_BAR => C_ARD_ADDR_RANGE_ARRAY(i*2)
( C_ARD_ADDR_RANGE_ARRAY(0)'length
- C_OPB_AWIDTH
+ K_DEV_ADDR_DECODE_WIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length-1
)
)
port map (
-- A => opb_abus_s0(K_DEV_ADDR_DECODE_WIDTH to C_OPB_AWIDTH-1),
-- AValid => devicesel_s0, --NEW GB
-- CS => bus2ip_cs_hit_s0(i)
A => opb_abus(K_DEV_ADDR_DECODE_WIDTH to C_OPB_AWIDTH-1), -- GAB 10/12/05
AValid => devicesel, -- GAB 10/12/05
CS => bus2ip_cs_hit(i) -- GAB 10/12/05
);
--
-- ToDo, pselect above and AND gate below can
-- be optimized later with a special pselect that
-- has outputs for both bus2ip_cs_s0 and bus2ip_cs_hit_s0.
--
-- GB - Removed check of postedwrinh when write buffer is instantiated. Write buffer
-- logic does not have postedwrinh implemented yet and this was causing a problem
-- with some of the configurations. When the write buffer is instantiated the
-- postedwrinh signal is ignored.
-- bus2ip_cs_enable_s0(i) <= not inh_cs_wnot_pw --GB
--
-- when C_DEV_BURST_ENABLE=0 or
--
-- (opb_seqaddr_s0 = '0'and opb_seqaddr_s0_d1 = '0') or
-- opb_rnw_s0 = '1' or
-- eff_ip2bus_val(
-- i =>i,
-- rst =>reset2bus_postedwrinh,
-- intr=>intr2bus_postedwrinh,
-- wrfifo=>'0',
-- rdfifo=>'0',
-- user=> ip2bus_postedwrinh(i)
-- --user=>ip2bus_postedwrinh
-- )='1'
-- else
-- not inh_cs_when_pw(i);
GEN_CS_ENABLE_NOWRBUF : if C_INCLUDE_WR_BUF = 0 generate --GB
bus2ip_cs_enable_s0(i) <= not(inh_cs_wnot_pw)
when opb_rnw_s0 = '1'
or eff_ip2bus_val(
i => i,
rst => reset2bus_postedwrinh,
intr => intr2bus_postedwrinh,
wrfifo => '0',
rdfifo => '0',
-- user => ip2bus_postedwrinh(i)
user => (ip2bus_postedwrinh_s2_d1(i)
and bo2sl(INCLUDE_OPBIN_PSTAGE))
or (ip2bus_postedwrinh_s2(i)
and bo2sl(not INCLUDE_OPBIN_PSTAGE))
)='1'
else not(inh_cs_when_pw(i));
end generate GEN_CS_ENABLE_NOWRBUF;
GEN_CS_ENABLE_WRBUF : if C_INCLUDE_WR_BUF = 1 generate --GB
bus2ip_cs_enable_s0(i) <= not inh_cs_wnot_pw
when C_DEV_BURST_ENABLE=0
or (opb_seqaddr_s0 = '0'
and opb_seqaddr_s0_d1 = '0')
or opb_rnw_s0 = '1'
else not inh_cs_when_pw(i);
end generate GEN_CS_ENABLE_WRBUF;
bus2ip_cs_s0(i) <= bus2ip_cs_hit_s0(i) and bus2ip_cs_enable_s0(i);
-------------------------------------------------------------------------
-- Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(i) - 1 generate
begin
----------------------------------------------------------------------
-- CE decoders
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1)
:= std_logic_vector(TO_UNSIGNED(j, CE_ADDR_SIZE));
begin
CE_I : entity opb_v20_v1_10_d.pselect
generic map (
C_AB => CE_ADDR_SIZE,
C_AW => CE_ADDR_SIZE,
C_BAR => BAR
)
port map (
A => next_opb_addr_cntr_out(C_OPB_AWIDTH - OFFSET - CE_ADDR_SIZE to
C_OPB_AWIDTH - OFFSET - 1),
AValid => bus2ip_cs_s0(i),
CS => bus2ip_ce_s0(CE_INDEX_START+j)
);
end generate;
--
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
bus2ip_ce_s0(CE_INDEX_START+j) <= bus2ip_cs_s0(i);
end generate;
--
----------------------------------------------------------------------
-- RdCE decoders
----------------------------------------------------------------------
bus2ip_rdce_s0(CE_INDEX_START+j) <=
bus2ip_ce_s0(CE_INDEX_START+j) and opb_rnw_s0;
----------------------------------------------------------------------
-- WrCE decoders
----------------------------------------------------------------------
bus2ip_wrce_s0(CE_INDEX_START+j) <=
bus2ip_ce_s0(CE_INDEX_START+j) and not opb_rnw_s0;
----------------------------------------------------------------------
end generate PER_CE_GEN;
end generate PER_AR_GEN;
------------------------------------------------------------------------
-- Master Abort Detection --GB
------------------------------------------------------------------------
-- This process detects when an abort occurs from the master.
-- and is used to gate off sln_xferack and sln_retry from the bus
--
GEN_ABORTS_FOR_1_3_7 : if (INCLUDE_OPBIN_PSTAGE and not (INCLUDE_OPBOUT_PSTAGE))
or (INCLUDE_OPBIN_PSTAGE and INCLUDE_IPIC_PSTAGE) generate
ABORT_DET : process(bus2ip_clk_i)
begin
if(bus2ip_clk_i'EVENT and bus2ip_clk_i='1')then
if(Reset = '1' or last_xferack_d1 = '1'
or or_reduce(bus2ip_cs_hit_s0) = '0' or sln_retry_s2 = '1')then
cycle_active <= '0';
elsif(or_reduce(bus2ip_cs_hit_s0) = '1' and sln_retry_s2 = '0')then
cycle_active <= '1';
end if;
cycle_abort_d1 <= cycle_abort;
end if;
end process ABORT_DET;
cycle_abort <= '1' when ( cycle_active = '1'
and or_reduce(bus2ip_cs_hit_s0) = '0'
and last_xferack_d1 = '0')
else '0';
GEN_XFERABORT_FOR_1_3 : if INCLUDE_OPBIN_PSTAGE and not(INCLUDE_OPBOUT_PSTAGE) generate
xfer_abort <= cycle_abort or cycle_abort_d1;
end generate;
GEN_XFERABORT_FOR_REST : if not(INCLUDE_OPBIN_PSTAGE) or INCLUDE_OPBOUT_PSTAGE generate
xfer_abort <= cycle_abort;
end generate;
end generate GEN_ABORTS_FOR_1_3_7;
-- Abort logic is not needed for pipeline models 0,2,4,5, and 6
GEN_NOABORTS_FOR_REST : if not(INCLUDE_OPBIN_PSTAGE)
or (not(INCLUDE_IPIC_PSTAGE) and INCLUDE_OPBOUT_PSTAGE) generate
begin
xfer_abort <= '0';
cycle_abort <= '0';
end generate GEN_NOABORTS_FOR_REST;
------------------------------------------------------------------------------
-- This process selects the set of CS signals that activate a given bit of the
-- encoded size.
------------------------------------------------------------------------------
ENCODE_SIZE_BIT_SEL_PROC : process (bus2ip_cs_s0)
type NAT_ARRAY_TYPE is array(natural range <>) of natural;
variable next_bit : NAT_ARRAY_TYPE(0 to 2);
begin
next_bit := (others => 0);
for i in 0 to NUM_ARDS-1 loop
for j in 0 to NUM_ENCODED_SIZE_BITS-1 loop
if encoded_size_is_1(i,j) then
cs_to_or_for_dsize_bit(j)(next_bit(j)) <= bus2ip_cs_s0(i);
next_bit(j) := next_bit(j)+1;
end if;
end loop;
end loop;
end process;
------------------------------------------------------------------------------
-- This generates the encoded data size as a function of the address range
-- being addressed.
------------------------------------------------------------------------------
ENCODED_SIZE_CS_OR_GEN : for i in 0 to NUM_ENCODED_SIZE_BITS-1 generate
begin
----------------------------------------------------------------------------
-- If no address range requires the bit high, then fix it low.
----------------------------------------------------------------------------
ALWAYS_LOW_GEN : if num_cs_for_bit(i) = 0 generate
encoded_dsize_s0(i) <= '0';
end generate;
----------------------------------------------------------------------------
-- If all address ranges require the bit high, then fix it high.
----------------------------------------------------------------------------
ALWAYS_HIGH_GEN: if num_cs_for_bit(i) = NUM_ARDS generate
encoded_dsize_s0(i) <= '1';
end generate;
----------------------------------------------------------------------------
-- If some address ranges require the bit high, and other address ranges
-- require it low, then OR together the CS signals for the address ranges
-- that require it high.
----------------------------------------------------------------------------
SOMETIMES_HIGH_GEN: if num_cs_for_bit(i) /= 0
and num_cs_for_bit(i) /= NUM_ARDS generate
-- instance of carry-chain OR for each bit
ENCODED_SIZE_OR : entity opb_v20_v1_10_d.or_muxcy
generic map (
C_NUM_BITS => num_cs_for_bit(i)
)
port map (
In_bus => cs_to_or_for_dsize_bit(i)(0 to num_cs_for_bit(i)-1),
Or_out => encoded_dsize_s0(i)
);
end generate;
end generate;
------------------------------------------------------------------------------
-- Steer write data from appropriate data lanes if C_ARD_DWIDTH_ARRAY has
-- mixed width values.
-- this steering module is used to steer the write data and BEs before the
-- write buffer
------------------------------------------------------------------------------
I_STEER_DATA : entity opb_v20_v1_10_d.IPIF_Steer
generic map(
C_DWIDTH => C_OPB_DWIDTH,
C_SMALLEST => get_min_dwidth(C_ARD_DWIDTH_ARRAY),
C_AWIDTH => C_OPB_AWIDTH
)
port map (
Wr_Data_In => opb_dbus_s0,
Addr => opb_abus_s0,
BE_In => opb_be_s0,
Decode_size => encoded_dsize_s0,
Wr_Data_Out => bus2ip_data_s0,
BE_Out => open,
--
-- Rd mirroring tied off, see I_MIRROR
Rd_Data_In => ZSLV(0 to C_OPB_DWIDTH-1),
Rd_Data_Out => open
);
------------------------------------------------------------------------------
-- Steer byte enables from appropriate data lanes if C_ARD_DWIDTH_ARRAY has
-- mixed width values.
-- this steering module is used to steer the byte enables output from
-- the address counter/be generator during reads
------------------------------------------------------------------------------
I_STEER_BE : entity opb_v20_v1_10_d.IPIF_Steer
generic map(
C_DWIDTH => C_OPB_DWIDTH,
C_SMALLEST => get_min_dwidth(C_ARD_DWIDTH_ARRAY),
C_AWIDTH => C_OPB_AWIDTH
)
port map (
Wr_Data_In => ZSLV(0 to C_OPB_DWIDTH-1),
Addr => next_steer_addr_cntr_out,
BE_In => opb_be_cntr_out,
Decode_size => encoded_dsize_s0,
Wr_Data_Out => open,
BE_Out => opb_be_cntr_steer,
--
-- Rd mirroring tied off, see I_MIRROR
Rd_Data_In => ZSLV(0 to C_OPB_DWIDTH-1),
Rd_Data_Out => open
);
------------------------------------------------------------------------------
-- Mirror read data to appropriate data lanes if C_ARD_DWIDTH_ARRAY has
-- mixed width values.
------------------------------------------------------------------------------
I_MIRROR : entity opb_v20_v1_10_d.IPIF_Steer
generic map(
C_DWIDTH => C_OPB_DWIDTH,
C_SMALLEST => get_min_dwidth(C_ARD_DWIDTH_ARRAY),
C_AWIDTH => C_OPB_AWIDTH
)
port map (
Rd_Data_In => ip2bus_data_mx,
Decode_size => encoded_dsize_s1,
--Addr => bus2ip_addr_s1,
Addr => steer_addr_cntr_out,
Rd_Data_Out => sln_dbus_s1,
--
-- Wr steering tied off, see I_STEER
Wr_Data_In => ZSLV(0 to C_OPB_DWIDTH-1),
BE_In => ZSLV(0 to C_OPB_DWIDTH/8-1),
Wr_Data_Out => open,
BE_Out => open
);
-- Generate for pipeline model 0, 2, 4, 6
IP2BUS_XFERACK_0_2_GEN : if not(INCLUDE_OPBIN_PSTAGE) generate
------------------------------------------------------------------------------
-- For inhibiting of posted writes IP2Bus_Ack needs to be gated off for 1
-- clocks during dynamic changes in the ip2bus_postedwrinh signal. During
-- reads and when the write buffer is instantiated simply pass IP2Bus_Ack
-- without gating it off.
------------------------------------------------------------------------------
-- GB
IP2BUS_XFERACK_PROC : process(bus2ip_cs_s1,IP2Bus_Ack,opb_rnw_s0,
ip2bus_postedwrinh_s2_d1)
variable r : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
r := r or (IP2Bus_Ack and bus2ip_cs_s1(i)
and
( (ip2bus_postedwrinh_s2_d1(i) and not(opb_rnw_s0))
or (opb_rnw_s0)
or (bo2sl(C_INCLUDE_WR_BUF=1))
));
end loop;
ip2bus_xferack <= r;
end process IP2BUS_XFERACK_PROC;
end generate;
-- Generate for pipeline model 1,3,5,and 7
IP2BUS_XFERACK_REST_GEN : if INCLUDE_OPBIN_PSTAGE generate
------------------------------------------------------------------------------
-- For inhibiting of posted writes IP2Bus_Ack needs to be gated off for 2
-- clocks during dynamic changes in the ip2bus_postedwrinh signal. During
-- reads and when the write buffer is instantiated simply pass IP2Bus_Ack
-- without gating it off.
------------------------------------------------------------------------------
-- GB
IP2BUS_XFERACK_PROC : process(bus2ip_cs_s1,IP2Bus_Ack,opb_rnw_s0,
ip2bus_postedwrinh_s2_d2)
variable r : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
r := r or (IP2Bus_Ack and bus2ip_cs_s1(i)
and
( (ip2bus_postedwrinh_s2_d2(i) and not(opb_rnw_s0))
or (opb_rnw_s0)
or (bo2sl(C_INCLUDE_WR_BUF=1))
));
end loop;
ip2bus_xferack <= r;
end process IP2BUS_XFERACK_PROC;
end generate;
------------------------------------------------------------------------------
-- Generation of sln_xferack.
-- ALS - modified to include read and write FIFOs
-- ALS - modified to include write buffer
------------------------------------------------------------------------------
IPIC_XFERACK_PROC : process (bus2ip_cs_s1, bus2ip_cs_hit_s0,
opb_rnw_s0, ip2bus_xferack,
reset2bus_ack, intr2bus_ack,
reset2bus_postedwrinh, intr2bus_postedwrinh,
wrfifo_ack, rdfifo_ack,ip2bus_postedwrinh_s2_d2,
IP2Bus_PostedWrInh) is
variable r : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
if (
-- GB - Removed check of postedwrinh when write buffer is instantiated. Write buffer
-- logic does not have postedwrinh implemented yet and this was causing a problem
-- with some of the configurations. When the write buffer is instantiated the
-- postedwrinh signal is ignored.
(bo2sl(C_INCLUDE_WR_BUF=0)
and eff_ip2bus_val(i => i,
rst => reset2bus_postedwrinh,
intr => intr2bus_postedwrinh,
wrfifo => '0',
rdfifo => '0',
user => IP2Bus_PostedWrInh(i))
)
or opb_rnw_s0
or bo2sl(C_INCLUDE_WR_BUF=1)) = '1' then
-- This is the case where transactions are reads, or writes
-- that are not posted or write buffer is included
r := r or (bus2ip_cs_s1(i)
and eff_ip2bus_val(i => i,
rst => reset2bus_ack,
intr => intr2bus_ack,
wrfifo => wrfifo_ack,
rdfifo => rdfifo_ack,
user => ip2bus_xferack --GB
));
else
-- posted writes, but no write buffer is included
r := r or bus2ip_cs_hit_s0(i);
end if;
end loop;
ipic_xferack <= r ;
end process ;
SLN_XFERACK_PROC : process (ipic_xferack, wrbuf_xferack, bus2ip_rnw_s1,
inh_xferack_when_pw , inh_xferack_when_burst_rd ) is
begin
if bus2ip_rnw_s1 = '0' then
if C_INCLUDE_WR_BUF = 1 then
sln_xferack_s1 <= wrbuf_xferack and not(inh_xferack_when_pw);
else
sln_xferack_s1 <= ipic_xferack and not (inh_xferack_when_pw);
end if;
else
sln_xferack_s1 <= ipic_xferack and not (inh_xferack_when_burst_rd);
end if;
end process SLN_XFERACK_PROC;
------------------------------------------------------------------------------
-- Generation of sln_retry.
-- ALS - modified to include read and write FIFOs
-- ALS - modified to include write buffer
------------------------------------------------------------------------------
SLN_RETRY_PROC : process (bus2ip_cs_s1, IP2Bus_Retry, reset2bus_retry,
intr2bus_retry,rfifo_retry, wfifo_retry,
wrbuf_retry, bus2ip_rnw_s1) is
variable r : std_logic;
variable ip2bus_retry_help : std_logic;
begin
if C_INCLUDE_WR_BUF = 1 and bus2ip_rnw_s1 = '0' then
-- write buffer generates Retry during write transfers
sln_retry_s1 <= wrbuf_retry;
else
r := '0';
for i in bus2ip_cs_s1'range loop
if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
ip2bus_retry_help := reset2bus_retry;
elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
ip2bus_retry_help := intr2bus_retry;
elsif INCLUDE_RDFIFO and ((i = RDFIFO_DATA_CS_IDX) or (i = RDFIFO_REG_CS_IDX)) then
ip2bus_retry_help := rfifo_retry;
elsif INCLUDE_WRFIFO and ((i = WRFIFO_DATA_CS_IDX) or (i = WRFIFO_REG_CS_IDX)) then
ip2bus_retry_help := wfifo_retry;
else
ip2bus_retry_help := IP2Bus_Retry;
end if;
r := r or (bus2ip_cs_s1(i) and ip2bus_retry_help);
end loop;
sln_retry_s1 <= r;
end if;
end process;
------------------------------------------------------------------------------
-- Generation of sln_error.
-- ALS - modified to include read and write FIFOs
-- ALS - modified to include write buffer
------------------------------------------------------------------------------
SLN_ERRACK_PROC : process (bus2ip_cs_s1, IP2Bus_Error, reset2bus_error,
intr2bus_error, rfifo_error, wfifo_error,
wrbuf_errack, bus2ip_rnw_s1) is
variable r : std_logic;
variable ip2bus_error_help : std_logic;
begin
if C_INCLUDE_WR_BUF = 1 and bus2ip_rnw_s1 = '0' then
-- write buffer generates ErrAck during write transfers
sln_errack_s1 <= wrbuf_errack;
else
r := '0';
for i in bus2ip_cs_s1'range loop
if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
ip2bus_error_help := reset2bus_error;
elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
ip2bus_error_help := intr2bus_error;
elsif INCLUDE_RDFIFO and ((i = RDFIFO_DATA_CS_IDX) or (i = RDFIFO_REG_CS_IDX)) then
ip2bus_error_help := rfifo_error;
elsif INCLUDE_WRFIFO and ((i = WRFIFO_DATA_CS_IDX) or (i = WRFIFO_REG_CS_IDX)) then
ip2bus_error_help := wfifo_error;
else
ip2bus_error_help := IP2Bus_Error;
end if;
r := r or (bus2ip_cs_s1(i) and ip2bus_error_help);
end loop;
sln_errack_s1 <= r;
end if;
end process;
------------------------------------------------------------------------------
-- Generation of sln_toutsup.
-- ALS - modified to include read and write FIFOs
------------------------------------------------------------------------------
SLN_TOUTSUP_PROC : process (bus2ip_cs_s1, IP2Bus_ToutSup, reset2bus_toutsup,
intr2bus_toutsup, rfifo_toutsup, wfifo_toutsup) is
variable r : std_logic;
variable ip2bus_toutsup_help : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
ip2bus_toutsup_help := reset2bus_toutsup;
elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
ip2bus_toutsup_help := intr2bus_toutsup;
elsif INCLUDE_RDFIFO and ((i = RDFIFO_DATA_CS_IDX) or (i = RDFIFO_REG_CS_IDX)) then
ip2bus_toutsup_help := rfifo_toutsup;
elsif INCLUDE_WRFIFO and ((i = WRFIFO_DATA_CS_IDX) or (i = WRFIFO_REG_CS_IDX)) then
ip2bus_toutsup_help := wfifo_toutsup;
else
ip2bus_toutsup_help := IP2Bus_ToutSup;
end if;
r := r or (bus2ip_cs_s1(i) and ip2bus_toutsup_help);
end loop;
sln_toutsup_s1 <= r;
end process;
------------------------------------------------------------------------------
-- Generation of ip2bus_data_mx, as a function of IP2Bus_Data
-- and bus2ip_rdce, using carry chain logic.
-- Note, internal address ranges such as RESET_MIR or Interrupt Source
-- controller are multiplexed into the appropriate "slot".
------------------------------------------------------------------------------
-- READMUX_GEN : if not SINGLE_CE generate
-- begin
-- READMUX_PROCESS: process(bus2ip_rdce_s1,
-- reset2bus_data,
-- intr2bus_data,
-- rdfifo2bus_data,
-- wrfifo2bus_data,
-- ip2bus_data)
-- begin
-- ip2bus_data_mx <= (others => '0');
-- for i in bus2ip_cs_s1'range loop
-- if bus2ip_cs_s1(i) = '1' then
-- if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
-- ip2bus_data_mx <= reset2bus_data;
-- elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
-- ip2bus_data_mx <= intr2bus_data;
-- elsif INCLUDE_RDFIFO and ((i = RDFIFO_DATA_CS_IDX)
-- or (i = RDFIFO_REG_CS_IDX)) then
-- ip2bus_data_mx <= rdfifo2bus_data;
-- elsif INCLUDE_WRFIFO and ((i = WRFIFO_DATA_CS_IDX)
-- or (i = WRFIFO_REG_CS_IDX)) then
-- ip2bus_data_mx <= wrfifo2bus_data;
-- else
-- ip2bus_data_mx <= ip2bus_data;
-- end if;
-- end if;
-- end loop;
-- end process READMUX_PROCESS;
-- end generate;
READMUX_GEN : if not SINGLE_CE generate
begin
READMUX_PROCESS: process(reset2bus_data,
intr2bus_data,
rdfifo2bus_data,
wrfifo2bus_data,
ip2bus_data)
begin
for i in ip2bus_data_mx'range loop
ip2bus_data_mx(i) <= reset2bus_data(i)
or intr2bus_data(i)
or rdfifo2bus_data(i)
or wrfifo2bus_data(i)
or ip2bus_data(i);
end loop;
end process READMUX_PROCESS;
end generate;
READMUX_SINGLE_CE_GEN : if SINGLE_CE generate
begin
ip2bus_data_mx <= ip2bus_data;
end generate;
-- PER_BIT_GEN : for i in 0 to C_OPB_DWIDTH-1 generate
-- signal cry : std_logic_vector(0 to (Bus2IP_RdCE'length + 1)/2);
-- begin
-- cry(0) <= '0';
-- PER_CE_PAIR_GEN : for j in 0 to (Bus2IP_RdCE'length + 1)/2-1 generate
-- signal ip2bus_data_rmmx0 : std_logic;
-- signal ip2bus_data_rmmx1 : std_logic;
-- signal lut_out : std_logic;
-- constant nopad : boolean
-- := (j /= (Bus2IP_RdCE'length + 1)/2-1)
-- or (Bus2IP_RdCE'length mod 2 = 0);
-- begin
-- -----------------------------------------------------------------------
-- -- ToDo, the read-back mux can be optimized to exclude any data bits
-- -- that are not present in AR with DWIDTH less than C_OPB_DWIDTH...
-- -- possibly also for bits that are known to be not implemented, e.g.
-- -- a register that doesn't use all bit positions or is write-only.
-- -----------------------------------------------------------------------
-- -- LUT (last LUT may multiplex one data bit instead of two)
-- -----------------------------------------------------------------------
---- WOPAD : if nopad generate
---- signal ip2bus_data_rmmx0 : std_logic_vector(0 to C_OPB_DWIDTH-1);
---- signal ip2bus_data_rmmx1 : std_logic_vector(0 to C_OPB_DWIDTH-1);
---- begin
-- -------------------------------------------------------------------
-- -- Always include the first of two possilble mux channels thru LUT.
-- -------------------------------------------------------------------
-- ip2bus_data_rmmx0 <=
-- ----------------------------------------------
-- -- RESET_MIR
-- ----------------------------------------------
-- reset2bus_data(i)
-- when INCLUDE_RESET_MIR and
-- (2*j = RESET_MIR_CE_IDX)
-- else
-- ----------------------------------------------
-- -- INTR -- ToDo, this is inefficient because
-- -- interrupt_control already multiplexes
-- -- the data. Optimize later.
-- ----------------------------------------------
-- intr2bus_data(i)
-- when INCLUDE_INTR and
-- (2*j >= INTR_CE_LO) and
-- (2*j <= INTR_CE_HI)
-- else
-- ----------------------------------------------
-- -- Read FIFO
-- ----------------------------------------------
-- rdfifo2bus_data(i)
-- when INCLUDE_RDFIFO and (
-- ((2*j >= RFIFO_REG_CE_LO) and (2*j <= RFIFO_REG_CE_HI))
-- or
-- (2*j = RFIFO_DATA_CE) )
-- else
-- ----------------------------------------------
-- -- Write FIFO
-- ----------------------------------------------
-- wrfifo2bus_data(i)
-- when INCLUDE_WRFIFO and (
-- ((2*j >= WFIFO_REG_CE_LO) and (2*j <= WFIFO_REG_CE_HI))
-- or
-- (2*j = WFIFO_DATA_CE) )
-- else
-- ----------------------------------------------
-- -- IP Core
-- ----------------------------------------------
-- --IP2Bus_Data((2*j )*C_OPB_DWIDTH + i);
-- IP2Bus_Data(i);
-- -------------------------------------------------------------------
-- -- Don't include second channel when odd number and on last LUT.
-- -------------------------------------------------------------------
-- WOPAD : if nopad generate
-- begin
-- ip2bus_data_rmmx1 <=
-- ----------------------------------------------
-- -- RESET_MIR
-- ----------------------------------------------
-- reset2bus_data(i)
-- when INCLUDE_RESET_MIR and
-- (2*j+1 = RESET_MIR_CE_IDX)
-- else
-- ----------------------------------------------
-- -- INTR
-- ----------------------------------------------
-- intr2bus_data(i)
-- when INCLUDE_INTR and
-- (2*j+1 >= INTR_CE_LO) and
-- (2*j+1 <= INTR_CE_HI)
-- else
-- ----------------------------------------------
-- -- Read FIFO
-- ----------------------------------------------
-- rdfifo2bus_data(i)
-- when INCLUDE_RDFIFO and (
-- ((2*j+1 >= RFIFO_REG_CE_LO) and (2*j+1 <= RFIFO_REG_CE_HI))
-- or
-- (2*j+1 = RFIFO_DATA_CE) )
-- else
-- ----------------------------------------------
-- -- Write FIFO
-- ----------------------------------------------
-- wrfifo2bus_data(i)
-- when INCLUDE_WRFIFO and (
-- ((2*j+1 >= WFIFO_REG_CE_LO) and (2*j+1 <= WFIFO_REG_CE_HI))
-- or
-- (2*j+1 = WFIFO_DATA_CE) )
-- else
-- ----------------------------------------------
-- -- IP Core
-- ----------------------------------------------
-- --IP2Bus_Data((2*j+1)*C_OPB_DWIDTH + i);
-- IP2Bus_Data(i);
-- --lut_out <= not (
-- -- (ip2bus_data_rmmx0(i) and bus2ip_rdce_s1(2*j )) or
-- -- (ip2bus_data_rmmx1(i) and bus2ip_rdce_s1(2*j+1)));
-- lut_out <= not (
-- (ip2bus_data_rmmx0 and bus2ip_rdce_s1(2*j )) or
-- (ip2bus_data_rmmx1 and bus2ip_rdce_s1(2*j+1)));
-- end generate;
-- WIPAD : if not nopad generate
-- lut_out <= not (
-- (ip2bus_data_rmmx0 and bus2ip_rdce_s1(2*j )));
-- end generate;
-- -----------------------------------------------------------------------
-- -- MUXCY
-- -----------------------------------------------------------------------
-- I_MUXCY : MUXCY
-- port map (
-- O => cry(j+1),
-- CI => cry(j),
-- DI => '1',
-- S => lut_out
-- );
-- end generate;
-- ip2bus_data_mx(i) <= cry((Bus2IP_RdCE'length + 1)/2);
-- end generate;
-- end generate;
--
--
-- READMUX_SINGLE_CE_GEN : if SINGLE_CE and INCLUDE_OPBOUT_PSTAGE generate
-- begin
-- ip2bus_data_mx <= ip2bus_data;
-- end generate;
-------------------------------------------------------------------------------
-- Reset/MIR
-------------------------------------------------------------------------------
INCLUDE_RESET_MIR_GEN : if INCLUDE_RESET_MIR generate
begin
RESET_MIR_I0 : entity opb_v20_v1_10_d.reset_mir
Generic map (
C_DWIDTH => C_OPB_DWIDTH,
C_INCLUDE_SW_RST => 1,
C_INCLUDE_MIR => C_DEV_MIR_ENABLE,
C_MIR_MAJOR_VERSION => MIR_MAJOR_VERSION,
C_MIR_MINOR_VERSION => MIR_MINOR_VERSION,
C_MIR_REVISION => MIR_REVISION,
C_MIR_BLK_ID => C_DEV_BLK_ID,
C_MIR_TYPE => MIR_TYPE
)
port map (
Reset => Reset,
Bus2IP_Clk => bus2ip_clk_i,
SW_Reset_WrCE => bus2ip_wrce_s1(RESET_MIR_CE_IDX),
SW_Reset_RdCE => bus2ip_rdce_s1(RESET_MIR_CE_IDX),
Bus2IP_Data => bus2ip_data_s1,
Bus2IP_Reset => bus2ip_reset_i,
Reset2Bus_Data => reset2bus_data,
Reset2Bus_Ack => reset2bus_ack,
Reset2Bus_Error => reset2bus_error,
Reset2Bus_Retry => reset2bus_retry,
Reset2Bus_ToutSup => reset2bus_toutsup
);
end generate;
EXCLUDE_RESET_MIR_GEN : if not INCLUDE_RESET_MIR generate
begin
bus2ip_reset_i <= Reset;
reset2bus_data <= (others => '0');
reset2bus_ack <= '0';
reset2bus_error <= '0';
reset2bus_retry <= '0';
reset2bus_toutsup <= '0';
end generate;
Bus2IP_Reset <= bus2ip_reset_i;
-------------------------------------------------------------------------------
-- Interrupts
-- ALS - added interrupts from Read and Write FIFOs
-- ALS - added code to allow C_INCLUDE_DEV_ISC and C_INCLUDE_DEV_PENCODER to
-- come from dependent props array
-------------------------------------------------------------------------------
INTR_CTRLR_GEN : if INCLUDE_INTR generate
constant NUM_IPIF_IRPT_SRC : natural := 4;
constant INTR_INDEX : integer :=
get_id_index(C_ARD_ID_ARRAY, IPIF_INTR);
signal errack_reserved: std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector( 0 to NUM_IPIF_IRPT_SRC-1);
begin
errack_reserved <= Sln_errack_s2 & '0';
ipif_lvl_interrupts(0) <= '0'; -- assign to DMA2Intr_Intr(0) when DMA is added
ipif_lvl_interrupts(1) <= '0'; -- assign to DMA2Intr_Intr(1) when DMA is added
ipif_lvl_interrupts(2) <= rdfifo2intr_deadlock; -- = '0' if FIFOs not included
ipif_lvl_interrupts(3) <= wrfifo2intr_deadlock; -- = '0' if FIFOs not included
INTERRUPT_CONTROL_I : entity opb_v20_v1_10_d.interrupt_control
generic map (
C_INTERRUPT_REG_NUM => number_CEs_for(IPIF_INTR),
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => C_ARD_DEPENDENT_PROPS_ARRAY
(INTR_INDEX)(INCLUDE_DEV_PENCODER)=1,
C_INCLUDE_DEV_ISC => C_ARD_DEPENDENT_PROPS_ARRAY
(INTR_INDEX)(EXCLUDE_DEV_ISC)=0,
C_IRPT_DBUS_WIDTH => C_OPB_DWIDTH
)
port map (
Bus2IP_Clk_i => bus2ip_clk_i,
Bus2IP_Data_sa => bus2ip_data_s1,
Bus2IP_RdReq_sa => '0',
Bus2IP_Reset_i => bus2ip_reset_i,
Bus2IP_WrReq_sa => '0',
Interrupt_RdCE => bus2ip_rdce_s1(INTR_CE_LO to INTR_CE_HI),
Interrupt_WrCE => bus2ip_wrce_s1(INTR_CE_LO to INTR_CE_HI),
IPIF_Reg_Interrupts => errack_reserved,
-- ALS - modified to connect read and write FIFO interrupts
--IPIF_Lvl_Interrupts => ZERO_SLV(0 to NUM_IPIF_IRPT_SRC-1),
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
IP2Bus_IntrEvent => IP2Bus_IntrEvent,
Intr2Bus_DevIntr => IP2INTC_Irpt,
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error, -- These are tied low in block
Intr2Bus_Retry => intr2bus_retry, --
Intr2Bus_ToutSup => intr2bus_toutsup --
);
end generate;
REMOVE_INTERRUPT : if (not INCLUDE_INTR) generate
intr2bus_data <= (others => '0');
IP2INTC_Irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_retry <= '0';
intr2bus_toutsup <= '0';
intr2bus_wrack <= '0';
end generate REMOVE_INTERRUPT;
intr2bus_ack <= intr2bus_rdack or intr2bus_wrack;
-------------------------------------------------------------------------------
-- RDREQ_WRREQ Generation if FIFOs are included
-------------------------------------------------------------------------------
NO_RDREQ_WRREQ_GEN: if not(INCLUDE_RDFIFO) and not(INCLUDE_WRFIFO) generate
bus2ip_rdreq_s0 <= '0';
bus2ip_wrreq_s0 <= '0';
end generate NO_RDREQ_WRREQ_GEN;
GEN_RDREQ_WREQ: if ((INCLUDE_RDFIFO) or (INCLUDE_WRFIFO)) generate
-- only 4 possible CS for FIFOs, size vector accordingly
signal fifo_cs : std_logic_vector(0 to 3);
signal any_fifo_cs : std_logic;
begin
-----------------------------------------------------------------------------
-- ALS - added process to generate read and write request
-- Generation of Bus2IP_RdReq and Bus2IP_WrReq stage 0 signals
-- These stage 0 signals will follow the pipeline models and generate statements
-- so that the appropriate stage 1 signal is created.
--
-- MODIFIED: 01/24/04 to be for any CS, not just FIFO CS - also
-- these signals will be qualified with ADDR
-- These signals assert for any FIFO CS. They are 1-clock pulse wide for single
-- transfers and stay asserted for burst transfers.
-----------------------------------------------------------------------------
GEN_PFIFOS_NO_WRBUF : if C_INCLUDE_WR_BUF = 0 generate
BOTHFIFOS_GEN: if INCLUDE_RDFIFO and INCLUDE_WRFIFO generate
fifo_cs <= bus2ip_cs_s0(RDFIFO_REG_CS_IDX) & bus2ip_cs_s0(RDFIFO_DATA_CS_IDX)
& bus2ip_cs_s0(WRFIFO_REG_CS_IDX) & bus2ip_cs_s0(WRFIFO_DATA_CS_IDX);
end generate BOTHFIFOS_GEN;
ONLY_RDFIFO_GEN: if INCLUDE_RDFIFO and not(INCLUDE_WRFIFO) generate
fifo_cs <= bus2ip_cs_s0(RDFIFO_REG_CS_IDX) & bus2ip_cs_s0(RDFIFO_DATA_CS_IDX)
& "00";
end generate ONLY_RDFIFO_GEN;
ONLY_WRFIFO_GEN: if INCLUDE_WRFIFO and not(INCLUDE_RDFIFO) generate
fifo_cs <= bus2ip_cs_s0(WRFIFO_REG_CS_IDX) & bus2ip_cs_s0(WRFIFO_DATA_CS_IDX)
& "00";
end generate ONLY_WRFIFO_GEN;
end generate;
GEN_PFIFOS_WITH_WRBUF : if C_INCLUDE_WR_BUF = 1 generate
BOTHFIFOS_GEN: if INCLUDE_RDFIFO and INCLUDE_WRFIFO generate
fifo_cs <= bus2ip_cs_s1(RDFIFO_REG_CS_IDX) & bus2ip_cs_s1(RDFIFO_DATA_CS_IDX)
& bus2ip_cs_s1(WRFIFO_REG_CS_IDX) & bus2ip_cs_s1(WRFIFO_DATA_CS_IDX);
end generate BOTHFIFOS_GEN;
ONLY_RDFIFO_GEN: if INCLUDE_RDFIFO and not(INCLUDE_WRFIFO) generate
fifo_cs <= bus2ip_cs_s1(RDFIFO_REG_CS_IDX) & bus2ip_cs_s1(RDFIFO_DATA_CS_IDX)
& "00";
end generate ONLY_RDFIFO_GEN;
ONLY_WRFIFO_GEN: if INCLUDE_WRFIFO and not(INCLUDE_RDFIFO) generate
fifo_cs <= bus2ip_cs_s1(WRFIFO_REG_CS_IDX) & bus2ip_cs_s1(WRFIFO_DATA_CS_IDX)
& "00";
end generate ONLY_WRFIFO_GEN;
end generate;
-- ToDo: see if LUT OR would be better here since max of 4 bits
ANYCS_OR_I: entity opb_v20_v1_10_d.or_muxcy
generic map (
C_NUM_BITS => 4
)
port map (
In_bus => fifo_cs,
Or_out => any_fifo_cs
);
-------------------------------------------------------------------------------
-- RDREQ_WRREQ Generation
-------------------------------------------------------------------------------
-- read request
rdreq <= '1'
when any_fifo_cs = '1' and opb_rnw_s0 = '1' and rdreq_hold = '0'
else '0';
-- hold the value of rdreq by setting a flop when rdreq asserts
-- this is used to gate off rdreq to keep it a one-clock pulse
rdreq_hold_rst <= (not(sln_xferack_s1) and (sln_xferack_s1_d1))
or sln_retry_s1
or not(opb_select_s0);
RDREQ_HOLD_FF: FDRE
port map (
Q => rdreq_hold, --[out]
C => bus2ip_clk_i, --[in]
CE=> rdreq, --[in]
D => '1', --[in]
R => rdreq_hold_rst --[in]
);
RDREQ_PIPE0_GEN: if C_PIPELINE_MODEL=0 generate
begin
-- need to extend read req 1 clock after sequential address
bus2ip_rdreq_s0 <= rdreq or (opb_seqaddr_s0_d1 and opb_rnw_s0);
end generate RDREQ_PIPE0_GEN;
RDREQ_PIPE_NOT0_GEN: if C_PIPELINE_MODEL /= 0 generate
-- generate bus2ip_rdreq by OR'ing the single pulse request with the burst
-- signal
bus2ip_rdreq_s0 <= rdreq or (opb_seqaddr_s0 and opb_rnw_s0);
end generate RDREQ_PIPE_NOT0_GEN;
WRREQ_GEN_FOR_PIPE_0_1 : if C_PIPELINE_MODEL = 0
or C_PIPELINE_MODEL = 1 generate
wrreq <= '1'
when any_fifo_cs = '1' and opb_rnw_s0 = '0'
else '0';
end generate WRREQ_GEN_FOR_PIPE_0_1;
WRREQ_GEN_FOR_REST : if C_PIPELINE_MODEL /= 0
and C_PIPELINE_MODEL /= 1 generate
-- write request
wrreq <= '1'
when any_fifo_cs = '1' and opb_rnw_s0 = '0' and wrreq_hold='0'
else '0';
-- hold the value of wrreq by setting a flop when wrreq asserts
-- this is used to gate off wrreq to keep it a one-clock pulse
wrreq_hold_rst <= (not(sln_xferack_s1) and (sln_xferack_s1_d1))
or sln_retry_s1
or not(opb_select_s0);
WRREQ_HOLD_FF: FDRE
port map (
Q => wrreq_hold, --[out]
C => bus2ip_clk_i, --[in]
CE=> wrreq, --[in]
D => '1', --[in]
R => wrreq_hold_rst --[in]
);
end generate WRREQ_GEN_FOR_REST;
-- generate bus2ip_wrreq by OR'ing the single pulse request with the burst
-- signal extended by 1 clock so that the write request is valid during entire burst
-- for all pipeline models except 5
WRREQ_PIPE_NOT5_GEN: if C_PIPELINE_MODEL = 0 or
C_PIPELINE_MODEL = 1 or
C_PIPELINE_MODEL = 2 or
C_PIPELINE_MODEL = 3 or
C_PIPELINE_MODEL = 7 generate
bus2ip_wrreq_s0 <= wrreq or (not(opb_rnw_s0) and bus2ip_burst_s1);
end generate WRREQ_PIPE_NOT5_GEN;
-- for pipeline model 5, generate bus2ip_wrreq by OR'ing the single pulse request
-- with delayed version of the burst_s1 signal
WRREQ_PIPE5_GEN: if C_PIPELINE_MODEL=4 or
C_PIPELINE_MODEL=5 or
C_PIPELINE_MODEL=6 generate
begin
bus2ip_wrreq_s0 <= wrreq or (not(bus2ip_rnw_s1) and bus2ip_burst_s1_d1);
end generate WRREQ_PIPE5_GEN;
end generate GEN_RDREQ_WREQ;
-------------------------------------------------------------------------------
-- Bus2IP_RdAddrValid and Bus2IP_WrAddrValid Generation
-- These signals are a single pulse during single transactions and are extended
-- during burst transactions
--bus2ip_rdaddrvalid_s0 <= bus2ip_rdreq_s0 and wrbuf_addrvalid;
--bus2ip_wraddrvalid_s0 <= bus2ip_wrreq_s0 and wrbuf_addrvalid;
------------------------------------------------------------------------------
-- Read FIFO
------------------------------------------------------------------------------
INCLUDE_RDFIFO_GEN : if (INCLUDE_RDFIFO) generate
constant DATA_INDEX : integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_RDFIFO_DATA);
constant DATA_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
DATA_INDEX);
constant REG_INDEX : integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_RDFIFO_REG);
constant REG_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
REG_INDEX);
signal bus2ip_rdreq_rfifo: std_logic;
signal bus2ip_rdce3_rfifo: std_logic;
begin
--synopsys translate_off
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(RD_WIDTH_BITS)
report "This implementation of the OPB IPIF requires the read " &
" width to be equal to the write width for the RDFIFO."
severity FAILURE;
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DWIDTH_ARRAY(DATA_INDEX)
report "This implementation of the OPB IPIF requires the write " &
" width to be equal to the data width specified in " &
" C_ARD_DWIDTH_ARRAY for RDFIFO."
severity FAILURE;
--synopsys translate_on
----------------------------------------------------------------------------
-- For RDFIFO, trim Bus2IP_RdReq as needed per pipeline model. The RDFIFO
-- moves burst data on every cycle and requires that
-- OPB_seqAddr is low on the next-to-last cycle.
----------------------------------------------------------------------------
RDREQ_RDCE_PIPE0_GEN: if C_PIPELINE_MODEL = 0 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1;
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE) and
not (not opb_seqaddr_d1 and bus2ip_burst_s1);
end generate RDREQ_RDCE_PIPE0_GEN;
RDREQ_RDCE_PIPE124_GEN: if C_PIPELINE_MODEL=1 or
C_PIPELINE_MODEL=2 or
C_PIPELINE_MODEL=4 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1;
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE);
end generate RDREQ_RDCE_PIPE124_GEN;
RDREQ_RDCE_PIPE3_GEN: if C_PIPELINE_MODEL=3 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1 and
not (not opb_seqaddr_d1 and bus2ip_burst_s1);
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE) and
not (not opb_seqaddr_d1 and bus2ip_burst_s1);
end generate RDREQ_RDCE_PIPE3_GEN;
RDREQ_RDCE_PIPE56_GEN: if C_PIPELINE_MODEL = 5 or
C_PIPELINE_MODEL = 6 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1 and
not (not OPB_seqAddr_eff and opb_seqaddr_d1);
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE) and
not (not OPB_seqAddr_eff and opb_seqaddr_d1);
end generate RDREQ_RDCE_PIPE56_GEN;
RDREQ_RDCE_PIPE7_GEN: if C_PIPELINE_MODEL = 7 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1 and
not (not OPB_seqAddr_eff and (opb_seqaddr_d1 or bus2ip_burst_s1));
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE) and
not (not OPB_seqAddr_eff and (opb_seqaddr_d1 or bus2ip_burst_s1));
end generate RDREQ_RDCE_PIPE7_GEN;
I_RDFIFO: entity opb_v20_v1_10_d.rdpfifo_top
Generic map(
C_MIR_ENABLE => (C_DEV_MIR_ENABLE /= 0),
C_BLOCK_ID => C_DEV_BLK_ID,
C_FIFO_DEPTH_LOG2X => log2(
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(FIFO_CAPACITY_BITS) /
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS)
),
C_FIFO_WIDTH => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS),
C_INCLUDE_PACKET_MODE => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_PACKET_MODE)=0,
C_INCLUDE_VACANCY => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_VACANCY)=0,
C_SUPPORT_BURST => true,
C_IPIF_DBUS_WIDTH => C_OPB_DWIDTH,
C_VIRTEX_II => VIRTEX_II
)
port map(
-- Inputs From the IPIF Bus
Bus_rst => bus2ip_reset_i,
Bus_Clk => bus2ip_clk_i,
Bus_RdReq => bus2ip_rdreq_rfifo,
Bus_WrReq => bus2ip_wrreq_s1,
Bus2FIFO_RdCE1 => bus2ip_rdce_s1(RFIFO_REG_CE_LO),
Bus2FIFO_RdCE2 => bus2ip_rdce_s1(RFIFO_REG_CE_LO+1),
Bus2FIFO_RdCE3 => bus2ip_rdce3_rfifo,
Bus2FIFO_WrCE1 => bus2ip_wrce_s1(RFIFO_REG_CE_LO),
Bus2FIFO_WrCE2 => bus2ip_wrce_s1(RFIFO_REG_CE_LO+1),
Bus2FIFO_WrCE3 => bus2ip_wrce_s1(RFIFO_DATA_CE),
Bus_DBus => bus2ip_data_s1,
-- Inputs from the IP
IP2RFIFO_WrReq => IP2RFIFO_WrReq,
IP2RFIFO_WrMark => IP2RFIFO_WrMark,
IP2RFIFO_WrRestore => IP2RFIFO_WrRestore,
IP2RFIFO_WrRelease => IP2RFIFO_WrRelease,
IP2RFIFO_Data => IP2RFIFO_Data,
-- Outputs to the IP
RFIFO2IP_WrAck => RFIFO2IP_WrAck,
RFIFO2IP_AlmostFull => RFIFO2IP_AlmostFull,
RFIFO2IP_Full => RFIFO2IP_Full,
RFIFO2IP_Vacancy => RFIFO2IP_Vacancy,
-- Outputs to the IPIF DMA/SG function
RFIFO2DMA_AlmostEmpty => open,
RFIFO2DMA_Empty => open,
RFIFO2DMA_Occupancy => open,
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock => rdfifo2intr_deadlock,
-- Outputs to the IPIF Bus
FIFO2Bus_DBus => rdfifo2bus_data,
FIFO2Bus_WrAck => rfifo_wrack,
FIFO2Bus_RdAck => rfifo_rdack,
FIFO2Bus_Error => rfifo_error,
FIFO2Bus_Retry => rfifo_retry,
FIFO2Bus_ToutSup => rfifo_toutsup
);
end generate INCLUDE_RDFIFO_GEN;
REMOVE_RDFIFO_GEN : if (not INCLUDE_RDFIFO) generate
rdfifo2bus_data <= (others => '0');
rdfifo2intr_deadlock <= '0';
RFIFO2IP_AlmostFull <= '0';
RFIFO2IP_Full <= '0';
RFIFO2IP_Vacancy <= (others => '0');
RFIFO2IP_WrAck <= '0';
rfifo_error <= '0';
rfifo_rdack <= '0';
rfifo_retry <= '0';
rfifo_toutsup <= '0';
rfifo_wrack <= '0';
end generate REMOVE_RDFIFO_GEN;
rdfifo_ack <= rfifo_wrack or rfifo_rdack;
--------------------------------------------------------------------------------
-- Write FIFO
--------------------------------------------------------------------------------
INCLUDE_WRFIFO_GEN : if (INCLUDE_WRFIFO) generate
constant DATA_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_WRFIFO_DATA);
constant DATA_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
DATA_INDEX);
constant REG_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_WRFIFO_REG);
constant REG_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
REG_INDEX);
begin
--synopsys translate_off
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(RD_WIDTH_BITS)
report "This implementation of the OPB IPIF requires the read " &
" width to be equal to the write width for the WRFIFO."
severity FAILURE;
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DWIDTH_ARRAY(DATA_INDEX)
report "This implementation of the OPB IPIF requires the write " &
" width to be equal to the data width specified in " &
" C_ARD_DWIDTH_ARRAY for WRFIFO."
severity FAILURE;
--synopsys translate_on
I_WRPFIFO_TOP: entity opb_v20_v1_10_d.wrpfifo_top
Generic map(
C_MIR_ENABLE => (C_DEV_MIR_ENABLE /= 0),
C_BLOCK_ID => C_DEV_BLK_ID,
C_FIFO_DEPTH_LOG2X => log2(
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(FIFO_CAPACITY_BITS) /
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS)
),
C_FIFO_WIDTH => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS),
C_INCLUDE_PACKET_MODE => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_PACKET_MODE)=0,
C_INCLUDE_VACANCY => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_VACANCY)=0,
C_SUPPORT_BURST => true,
C_IPIF_DBUS_WIDTH => C_OPB_DWIDTH,
C_VIRTEX_II => VIRTEX_II
)
port map(
-- Inputs From the IPIF Bus
Bus_rst => bus2ip_reset_i,
Bus_clk => bus2ip_clk_i,
Bus_RdReq => bus2ip_rdreq_s1,
Bus_WrReq => bus2ip_wrreq_s1,
Bus2FIFO_RdCE1 => bus2ip_rdce_s1(WFIFO_REG_CE_LO),
Bus2FIFO_RdCE2 => bus2ip_rdce_s1(WFIFO_REG_CE_LO+1),
Bus2FIFO_RdCE3 => bus2ip_rdce_s1(WFIFO_DATA_CE),
Bus2FIFO_WrCE1 => bus2ip_wrce_s1(WFIFO_REG_CE_LO),
Bus2FIFO_WrCE2 => bus2ip_wrce_s1(WFIFO_REG_CE_LO+1),
Bus2FIFO_WrCE3 => bus2ip_wrce_s1(WFIFO_DATA_CE),
Bus_DBus => bus2ip_data_s1,
-- Inputs from the IP
IP2WFIFO_RdReq => IP2WFIFO_RdReq,
IP2WFIFO_RdMark => IP2WFIFO_RdMark,
IP2WFIFO_RdRestore => IP2WFIFO_RdRestore,
IP2WFIFO_RdRelease => IP2WFIFO_RdRelease,
-- Outputs to the IP
WFIFO2IP_Data => WFIFO2IP_Data,
WFIFO2IP_RdAck => WFIFO2IP_RdAck,
WFIFO2IP_AlmostEmpty => WFIFO2IP_AlmostEmpty,
WFIFO2IP_Empty => WFIFO2IP_Empty,
WFIFO2IP_Occupancy => WFIFO2IP_Occupancy,
-- Outputs to the IP
WFIFO2DMA_AlmostFull => open,
WFIFO2DMA_Full => open,
WFIFO2DMA_Vacancy => open,
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock => wrfifo2intr_deadlock,
-- Outputs to the IPIF Bus
FIFO2Bus_DBus => wrfifo2bus_data,
FIFO2Bus_WrAck => wfifo_wrack,
FIFO2Bus_RdAck => wfifo_rdack,
FIFO2Bus_Error => wfifo_error,
FIFO2Bus_Retry => wfifo_retry,
FIFO2Bus_ToutSup => wfifo_toutsup
);
end generate INCLUDE_WRFIFO_GEN;
REMOVE_WRFIFO_GEN : if (not INCLUDE_WRFIFO) generate
WFIFO2IP_AlmostEmpty <= '0';
WFIFO2IP_Data <= (others => '0');
WFIFO2IP_Empty <= '0';
WFIFO2IP_Occupancy <= (others => '0');
WFIFO2IP_RdAck <= '0';
wfifo_error <= '0';
wfifo_rdack <= '0';
wfifo_retry <= '0';
wfifo_toutsup <= '0';
wfifo_wrack <= '0';
wrfifo2bus_data <= (others => '0');
wrfifo2intr_deadlock <= '0';
end generate REMOVE_WRFIFO_GEN;
wrfifo_ack <= wfifo_wrack or wfifo_rdack;
end implementation;
|
architecture RTL of FIFO is
procedure average_samples;
begin
Average_samples;
PROC1 : process () is
begin
AVERAGE_SAMPLES;
AVERAGE_SaMPLES;
aVeRAGE_SaMPLES;
end process;
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc540.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b01x00p02n01i00540ent IS
END c03s03b01x00p02n01i00540ent;
ARCHITECTURE c03s03b01x00p02n01i00540arch OF c03s03b01x00p02n01i00540ent IS
type ARR -- Failure_here
type L1 is access ARR;
type ARR is array (positive range <>) of BIT;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s03b01x00p02n01i00540 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b01x00p02n01i00540arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc540.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b01x00p02n01i00540ent IS
END c03s03b01x00p02n01i00540ent;
ARCHITECTURE c03s03b01x00p02n01i00540arch OF c03s03b01x00p02n01i00540ent IS
type ARR -- Failure_here
type L1 is access ARR;
type ARR is array (positive range <>) of BIT;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s03b01x00p02n01i00540 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b01x00p02n01i00540arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc540.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b01x00p02n01i00540ent IS
END c03s03b01x00p02n01i00540ent;
ARCHITECTURE c03s03b01x00p02n01i00540arch OF c03s03b01x00p02n01i00540ent IS
type ARR -- Failure_here
type L1 is access ARR;
type ARR is array (positive range <>) of BIT;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s03b01x00p02n01i00540 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b01x00p02n01i00540arch;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: constants_mem_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : constants_mem.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 1
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 1
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY constants_mem_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END constants_mem_prod;
ARCHITECTURE xilinx OF constants_mem_prod IS
COMPONENT constants_mem_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : constants_mem_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
-- cb20_width_adapter.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 34;
IN_PKT_ADDR_L : integer := 18;
IN_PKT_DATA_H : integer := 15;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 17;
IN_PKT_BYTEEN_L : integer := 16;
IN_PKT_BYTE_CNT_H : integer := 43;
IN_PKT_BYTE_CNT_L : integer := 41;
IN_PKT_TRANS_COMPRESSED_READ : integer := 35;
IN_PKT_BURSTWRAP_H : integer := 44;
IN_PKT_BURSTWRAP_L : integer := 44;
IN_PKT_BURST_SIZE_H : integer := 47;
IN_PKT_BURST_SIZE_L : integer := 45;
IN_PKT_RESPONSE_STATUS_H : integer := 69;
IN_PKT_RESPONSE_STATUS_L : integer := 68;
IN_PKT_TRANS_EXCLUSIVE : integer := 40;
IN_PKT_BURST_TYPE_H : integer := 49;
IN_PKT_BURST_TYPE_L : integer := 48;
IN_ST_DATA_W : integer := 70;
OUT_PKT_ADDR_H : integer := 52;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 61;
OUT_PKT_BYTE_CNT_L : integer := 59;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 53;
OUT_PKT_BURST_SIZE_H : integer := 65;
OUT_PKT_BURST_SIZE_L : integer := 63;
OUT_PKT_RESPONSE_STATUS_H : integer := 87;
OUT_PKT_RESPONSE_STATUS_L : integer := 86;
OUT_PKT_TRANS_EXCLUSIVE : integer := 58;
OUT_PKT_BURST_TYPE_H : integer := 67;
OUT_PKT_BURST_TYPE_L : integer := 66;
OUT_ST_DATA_W : integer := 88;
ST_CHANNEL_W : integer := 8;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(7 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(69 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(87 downto 0); -- .data
out_channel : out std_logic_vector(7 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity cb20_width_adapter;
architecture rtl of cb20_width_adapter is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(87 downto 0); -- data
out_channel : out std_logic_vector(7 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of cb20_width_adapter
|
-------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <paulino@dte.us.es>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- You can get more info at http://www.dte.us.es/id2
--
--*------------------------------- End auto header, don't touch this line --*--
-- Nexyys4 brings a dual display where 4 bytes can be displayes
-- This module defines a 8+2 bits inputs
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.digilent_peripherals_pk.all;
entity port_display32_dig is port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
w : in std_logic;
digit_in : in std_logic_vector (7 downto 0);
dp_in : in std_logic_vector (1 downto 0);
byte_sel : in std_logic_vector (1 downto 0);
seg_out : out std_logic_vector (6 downto 0);
dp_out : out std_logic;
an_out : out std_logic_vector (7 downto 0));
end port_display32_dig;
architecture Behavioral of port_display32_dig is
signal counter : unsigned (23 downto 0);
signal counter8 : unsigned (2 downto 0);
signal digits : std_logic_vector (31 downto 0);
signal dps : std_logic_vector (7 downto 0);
signal conv_in : std_logic_vector (3 downto 0);
signal divider : std_logic;
signal dp_inter_out : std_logic;
begin
dp_out <= not dp_inter_out;
-- Writer process
write_proc : process (clk,enable,byte_sel,w)
begin
if falling_edge(clk) and enable='1' and w='1' then
case byte_sel is
when "00" =>
digits(7 downto 0) <= digit_in(7 downto 0);
dps(1 downto 0) <= dp_in;
when "01" =>
digits(15 downto 8) <= digit_in(7 downto 0);
dps(3 downto 2) <= dp_in;
when "10" =>
digits(23 downto 16)<= digit_in(7 downto 0);
dps(5 downto 4) <= dp_in;
when others =>
digits(31 downto 24)<= digit_in(7 downto 0);
dps(7 downto 6) <= dp_in;
end case;
end if;
end process;
-- Clock divider process
div_proc : process (clk,counter,reset)
begin
if falling_edge(clk) then
if counter > NEXYS4_DIVIDER or reset = '1' then
counter <= x"000000";
divider <= '1';
else
counter <= counter + 1;
divider <= '0';
end if;
end if;
end process;
div2_proc : process(clk,divider,reset)
begin
if falling_edge(clk) then
if reset = '1' then
counter8 <= "000";
elsif divider='1' then
counter8 <= counter8 +1;
end if;
end if;
end process;
mux_anod : process (counter8)
begin
case counter8 is
when "000" =>
conv_in <= digits(3 downto 0);
dp_inter_out <= dps(0);
an_out <= "11111110";
when "001" =>
conv_in <= digits(7 downto 4);
dp_inter_out <= dps(1);
an_out <= "11111101";
when "010" =>
conv_in <= digits(11 downto 8);
dp_inter_out <= dps(2);
an_out <= "11111011";
when "011" =>
conv_in <= digits(15 downto 12);
dp_inter_out <= dps(3);
an_out <= "11110111";
when "100" =>
conv_in <= digits(19 downto 16);
dp_inter_out <= dps(4);
an_out <= "11101111";
when "101" =>
conv_in <= digits(23 downto 20);
dp_inter_out <= dps(5);
an_out <= "11011111";
when "110" =>
conv_in <= digits(27 downto 24);
dp_inter_out <= dps(6);
an_out <= "10111111";
when others =>
conv_in <= digits(31 downto 28);
dp_inter_out <= dps(7);
an_out <= "01111111";
end case;
end process;
-- Binary to seven seg converter
with conv_in select
seg_out <= "1000000" when "0000", --0
"1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when others; --F
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
Port (
CLK : in std_logic; -- Pixel clock 32.5MHz
RESET : in std_logic; -- Reset (active low)
CACHE_SWAP : out std_logic; -- Active buffer
CACHE_A : out std_logic_vector(5 downto 0); -- Cache address
CACHE_D : in std_logic_vector(7 downto 0); -- Cache data
CURRENT_LINE : out std_logic_vector(7 downto 0); -- Current line to read in cache
COLORS : in std_logic_vector(6 downto 0);
R : out std_logic_vector(3 downto 0); -- Red
G : out std_logic_vector(3 downto 0); -- Green
B : out std_logic_vector(3 downto 0); -- Blue
HSYNC : out std_logic; -- Hor. sync
VSYNC : out std_logic -- Ver. sync
);
end video;
architecture BEHAVIORAL of video is
-- VGA timing constants (XGA - 1024x768@60) (512x768@60)
-- HOR
constant HSIZE : INTEGER := 512; -- Visible area
constant HFP : INTEGER := 12; -- Front porch
constant HS : INTEGER := 68; -- HSync pulse
constant HB : INTEGER := 80; -- Back porch
constant HOFFSET : INTEGER := 0; -- HSync offset
-- VER
constant VSIZE : INTEGER := 768; -- Visible area
constant VFP : INTEGER := 3; -- Front porch
constant VS : INTEGER := 6; -- VSync pulse
constant VB : INTEGER := 29; -- Back porch
constant VOFFSET : INTEGER := 0; -- VSync offset
------------------------------------------------------------
signal H_COUNTER : UNSIGNED(9 downto 0); -- Horizontal Counter
signal V_COUNTER : UNSIGNED(9 downto 0); -- Vertical Counter
signal THREE_ROW_CNT : UNSIGNED(1 downto 0); -- 3 Row Counter
signal ROW_COUNTER : UNSIGNED(7 downto 0); -- Korvet Row Counter
signal PAPER : STD_LOGIC; -- Paper zone
signal PAPER_L : STD_LOGIC; -- Paper zone latched
signal COLOR_R : STD_LOGIC;
signal COLOR_G : STD_LOGIC;
signal COLOR_B : STD_LOGIC;
signal PIX0 : STD_LOGIC_VECTOR(3 downto 0);
signal PIX1 : STD_LOGIC_VECTOR(3 downto 0);
begin
u_COLOR_MUX : entity work.clr_mux
port map(
color => PIX1(3 - to_integer(H_COUNTER(2 downto 1))) & PIX0(3 - to_integer(H_COUNTER(2 downto 1))),
portb => COLORS,
out_r => COLOR_R,
out_g => COLOR_G,
out_b => COLOR_B );
CURRENT_LINE <= std_logic_vector(ROW_COUNTER);
process (CLK) -- H/V Counters
begin
if rising_edge(CLK) then
if RESET = '0' then
H_COUNTER <= (others=>'0');
V_COUNTER <= (others=>'0');
else
H_COUNTER <= H_COUNTER + 1;
if H_COUNTER = (HSIZE + HFP + HS + HB - 1) then
H_COUNTER <= (others=>'0');
V_COUNTER <= V_COUNTER + 1;
if V_COUNTER = (VSIZE + VFP + VS + VB - 1) then
V_COUNTER <= (others=>'0');
end if;
end if;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if RESET = '0' then
THREE_ROW_CNT <= (others=>'0');
ROW_COUNTER <= (others=>'0');
CACHE_SWAP <= '0';
else
CACHE_SWAP <= '0';
if H_COUNTER = 544 then
if V_COUNTER < 768 then
THREE_ROW_CNT <= THREE_ROW_CNT + 1;
if THREE_ROW_CNT = 2 then
THREE_ROW_CNT <= (others=>'0');
ROW_COUNTER <= ROW_COUNTER + 1;
CACHE_SWAP <= '1';
end if;
else
ROW_COUNTER <= (others=>'0');
THREE_ROW_CNT <= (others=>'0');
end if;
end if;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
HSYNC <= '1';
VSYNC <= '1';
PAPER <= '0';
if H_COUNTER >= (HSIZE + HOFFSET + HFP) and H_COUNTER < (HSIZE + HOFFSET + HFP + HS) then
HSYNC <= '0';
end if;
if V_COUNTER >= (VSIZE + VOFFSET + VFP) and V_COUNTER < (VSIZE + VOFFSET + VFP + VS) then
VSYNC <= '0';
end if;
if H_COUNTER < HSIZE and V_COUNTER < VSIZE then
PAPER <= '1';
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
case H_COUNTER(2 downto 0) is
when "001" =>
CACHE_A <= std_logic_vector(H_COUNTER(8 downto 3));
when "111" =>
PIX0 <= CACHE_D(3 downto 0);
PIX1 <= CACHE_D(7 downto 4);
PAPER_L <= PAPER;
when OTHERS =>
null;
end case;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if PAPER_L = '1' then
if THREE_ROW_CNT = "01" then
R <= COLOR_R & COLOR_R & COLOR_R & COLOR_R;
G <= COLOR_G & COLOR_G & COLOR_G & COLOR_G;
B <= COLOR_B & COLOR_B & COLOR_B & COLOR_B;
else
R <= COLOR_R & "000";
G <= COLOR_G & "000";
B <= COLOR_B & "000";
end if;
else
R <= (others=>'0');
G <= (others=>'0');
B <= (others=>'0');
end if;
end if;
end process;
end BEHAVIORAL;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
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-- (including loss of data, profits, goodwill, or any type of
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-- reasonably foreseeable or Xilinx had been advised of the
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--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
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-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
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-- PART OF THIS FILE AT ALL TIMES.
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity mwfc is
Generic (
precision : integer := 13;
bcdprecision : integer := 16 );
Port (
rawfrq : out unsigned(precision - 1 downto 0); -- May need an extra bit of margin
bcdfrq : out std_logic_vector(bcdprecision - 1 downto 0);
ord : out signed(7 downto 0);
overflow : out std_logic;
clk : in std_logic;
clk2 : in std_logic;
rst : in std_logic );
end mwfc;
architecture Behavioral of mwfc is
-- The following constants are taken from the accuracy calculation
-- on the associated spreadsheet
constant hfbitmargin : integer := 2; -- FIXME should be 2
constant lfbitmargin : integer := 19;
constant inputbits : integer := precision + hfbitmargin;
constant timerbits : integer := lfbitmargin;
constant nscalestages : integer := 7; -- FIXME log2 of maxscalefactor
signal tcount, isync1 : unsigned(timerbits-1 downto 0);
signal icount, isync0 : unsigned(inputbits-1 downto 0);
signal scaling : signed(nscalestages-1 downto 0);
signal ratio : unsigned(precision-1 downto 0);
signal divbusy, divoverflow, divstrobe : std_logic;
signal bcdstrobe : std_logic;
signal final : unsigned(rawfrq'range);
signal order : signed(ord'range);
constant measureinterval : integer := 2**precision;
signal bcd : std_logic_vector(bcdfrq'range);
signal convbusy, convstrobe : std_logic;
begin
-- The current values of the corrections arrays expect this
-- given precision
assert precision = 17 report "Mismatch in precision!" severity error;
ord <= order;
bcdfrq <= bcd;
rawfrq <= final;
overflow <= divoverflow;
conv : entity work.hex2bcd
generic map (
precision => final'length,
width => bcd'length,
bits => 5,
ndigits => 5 ) -- log2 of precision
port map (
hex => final,
bcd => bcd,
strobe => bcdstrobe,
rst => rst,
clk => clk );
-- Count the number of timer and input tics in the given
-- measurement interval, taking a whole number of input tics.
stage1 : entity work.counter
generic map (
Tlen => tcount'length,
ILen => icount'length,
measureinterval => measureinterval )
port map (
timer => clk,
input => clk2,
tcount => tcount,
icount => icount,
enable => '1',
strobe => divstrobe,
rst => rst);
-- Synchronize the reciprocal counter to the 'clk' clock domain
process(clk)
begin
if rising_edge(clk) then
isync1 <= (others => '0');
isync1(isync0'range) <= isync0;
isync0 <= icount;
end if;
end process;
-- Divide M by N
stage2 : entity work.fpdiv
generic map (
size => tcount'length,
precision => ratio'length,
pscale => scaling'length )
port map (
dividend => isync1,
divisor => tcount,
quotient => ratio,
scale => scaling,
busy => divbusy,
overflow => divoverflow,
strobe => divstrobe,
clk => clk,
rst => rst );
process(clk,rst)
variable divold : std_logic;
begin
if rst = '1' then
divold := '0';
elsif rising_edge(clk) then
if divold = '0' and divbusy = '1' then
convstrobe <= '1';
else
convstrobe <= '0';
end if;
divold := divbusy;
end if;
end process;
stage3 : entity work.fpbaseconv
generic map (
precision => final'length,
exp_precision => order'length,
nscalestages => nscalestages )
port map (
mantissa => final,
exponent => order,
busy => convbusy,
scaling => scaling,
ratio => ratio,
strobe => convstrobe,
clk => clk,
rst => rst );
process(clk,rst)
variable convold : std_logic;
begin
if rst = '1' then
convold := '0';
elsif rising_edge(clk) then
if convold = '0' and convbusy = '1' then
bcdstrobe <= '1';
else
bcdstrobe <= '0';
end if;
convold := convbusy;
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_modulator/hdl_modulator_hdl_modulator_pkg.vhd
-- Created: 2018-02-27 13:25:15
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE hdl_modulator_hdl_modulator_pkg IS
TYPE vector_of_signed16 IS ARRAY (NATURAL RANGE <>) OF signed(15 DOWNTO 0);
TYPE vector_of_unsigned9 IS ARRAY (NATURAL RANGE <>) OF unsigned(8 DOWNTO 0);
END hdl_modulator_hdl_modulator_pkg;
|
-- CHECKED AND MODIFIED BY PRASANJEET
-------------------------------------------
--UPDATED ON: 7/9/09, 7/13/10
-- TASK : Complete the four TODO sections
-------------------------------------------
-------------------------------------------------------------------------------
--
-- Design : Load/Store Issue Cntrl
-- Project : Tomasulo Processor
-- Author : Rohit Goel
-- ComOppany : University of Southern California
--
-------------------------------------------------------------------------------
--
-- File : Lsqcntrl.vhd
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : The Issue control controls the Issuque
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
-- Entity declaration
entity Lsquectrl is
port (
-- Global Clk and Resetb Signals
Clk : in std_logic ;
Resetb : in std_logic ;
-- cdb interface
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0) ;
Cdb_PhyRegWrite : in std_logic;
Cdb_Valid : in std_logic ;
-- lsq interface
Opcode : in std_logic_vector(7 downto 0);
AddrReadyBit : in std_logic_vector(7 downto 0);
AddrUpdate : out std_logic_vector(7 downto 0);
AddrUpdateSel : out std_logic_vector(7 downto 0);
-- ROB Interface
Cdb_Flush : in std_logic ;
Rob_TopPtr : in std_logic_vector (4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector (4 downto 0 ) ;
-- Dispatch / issue unit interface
Dis_LdIssquenable : in std_logic ;
Iss_LdStIssued : in std_logic ;
DCE_ReadBusy : in std_logic;
Lsbuf_Done : in std_logic;
-- shift register inputs
InstructionValidBit : in std_logic_vector(7 downto 0); -- '1' indicates instruction is valid in the buffer
RsDataValidBit : in std_logic_vector(7 downto 0); -- '1' indicates rs data is valid in the buffer
Buffer0RsTag : in std_logic_vector(5 downto 0);
Buffer1RsTag : in std_logic_vector(5 downto 0);
Buffer2RsTag : in std_logic_vector(5 downto 0);
Buffer3RsTag : in std_logic_vector(5 downto 0);
Buffer4RsTag : in std_logic_vector(5 downto 0);
Buffer5RsTag : in std_logic_vector(5 downto 0);
Buffer6RsTag : in std_logic_vector(5 downto 0);
Buffer7RsTag : in std_logic_vector(5 downto 0);
Buffer0RdTag : in std_logic_vector(4 downto 0);
Buffer1RdTag : in std_logic_vector(4 downto 0);
Buffer2RdTag : in std_logic_vector(4 downto 0);
Buffer3RdTag : in std_logic_vector(4 downto 0);
Buffer4RdTag : in std_logic_vector(4 downto 0);
Buffer5RdTag : in std_logic_vector(4 downto 0);
Buffer6RdTag : in std_logic_vector(4 downto 0);
Buffer7RdTag : in std_logic_vector(4 downto 0);
IssuqueCounter0 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter1 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter2 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter3 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter4 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter5 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter6 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter7 : in std_logic_vector ( 2 downto 0 ) ;
-- output control signals - group 1
Sel0 : out std_logic; -- '1' indicates update from dispatch
Flush : out std_logic_vector(7 downto 0); -- '1' indicates invalidate instruction valid bit
Sel1Rs : out std_logic_vector(7 downto 0); -- '1' indicates update from cdb - highest priority
En : out std_logic_vector(7 downto 0); -- '1' indicates update / shift
OutSelect : out std_logic_vector(2 downto 0);
IncrementCounter : out std_logic_vector(7 downto 0 ) ;
-- issue que unit control signals
Issque_LdStQueueFull : out std_logic ;
IssuequefullTemp_Upper,IssuequefullTemp_Lower : out std_logic ;
Iss_LdStReady : out std_logic ;
-- Address Buffer Signal
AddrBuffFull : in std_logic;
AddrMatch0 : in std_logic ;
AddrMatch1 : in std_logic ;
AddrMatch2 : in std_logic ;
AddrMatch3 : in std_logic ;
AddrMatch4 : in std_logic ;
AddrMatch5 : in std_logic ;
AddrMatch6 : in std_logic ;
AddrMatch7 : in std_logic ;
AddrMatch0Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch1Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch2Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch3Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch4Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch5Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch6Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch7Num : in std_logic_vector ( 2 downto 0 ) ;
ScanAddr0 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr1 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr2 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr3 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr4 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr5 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr6 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr7 : in std_logic_vector ( 31 downto 0 )
);
end Lsquectrl ;
architecture behavctrl of Lsquectrl is
signal OutTemp : std_logic_vector ( 2 downto 0 ) ;
signal OutSelectTemp , Entemp : std_logic_vector ( 7 downto 0 ) ;
signal IssuequeReadyTemp , IssuequefullTemp,IssuequefullTemp_Upper_sig,IssuequefullTemp_Lower_sig : std_logic ;
signal Buffer0Depth, Buffer1Depth ,Buffer2Depth ,Buffer3Depth, Buffer4Depth,
Buffer5Depth ,Buffer6Depth ,Buffer7Depth : std_logic_vector(4 downto 0) ;
signal OutSelectTemp2 : std_logic_vector( 7 downto 0 ) ;
begin
----------------------Generating Issuque ready -------------------------------------
Iss_LdStReady <= IssuequeReadyTemp and ( not AddrBuffFull); --so you can't issue any lw/sw when address buffer is full!! NOTE: qualify for "sw" only
---------- ----------Done Generating issuque Ready --------------------------------
-------------------- Generating Full Condition-------------------------------------
--###############################################################################################
-- TODO 1: Generate the Full control signal
--################################################################################################
process ( InstructionValidBit ,Iss_LdStIssued )
begin
if ( Iss_LdStIssued = '1' ) then --when an instruction is issued issueque is not full
IssuequefullTemp <= '0' ;
IssuequefullTemp_Upper_sig <= ----- ; --Fill in the initial values of these two signals. //almost same as Issueque full signal
IssuequefullTemp_Lower_sig <= ----- ;
else
IssuequefullTemp_Upper_sig <=InstructionValidBit(7) and InstructionValidBit(6) and
InstructionValidBit(5) and InstructionValidBit(4);
IssuequefullTemp_Lower_sig <=InstructionValidBit(3) and InstructionValidBit(2) and
InstructionValidBit(1) and InstructionValidBit(0) ;
end if ;
end process ;
IssuequefullTemp_Upper<=IssuequefullTemp_Upper_sig;
IssuequefullTemp_Lower<=IssuequefullTemp_Lower_sig;
Issque_LdStQueueFull <= -- ------------------------------------------; --Complete the right hand side of the expression
------------------ Done Generating Full Condition -------------------------------
--################################################################################################
------------------- Generating OutSelect----------------------------------------
--these are simple output select signals based on the instruction and corresponding necessary operands being ready
OutSelectTemp (0)<= AddrReadyBit(0) and InstructionValidBit(0);
OutSelectTemp (1)<= AddrReadyBit(1) and InstructionValidBit(1) ;
OutSelectTemp (2)<= AddrReadyBit(2) and InstructionValidBit(2) ;
OutSelectTemp (3)<= AddrReadyBit(3) and InstructionValidBit(3) ;
OutSelectTemp (4)<= AddrReadyBit(4) and InstructionValidBit(4) ;
OutSelectTemp (5)<= AddrReadyBit(5) and InstructionValidBit(5) ;
OutSelectTemp (6)<= AddrReadyBit(6) and InstructionValidBit(6) ;
OutSelectTemp (7)<= AddrReadyBit(7) and InstructionValidBit(7) ;
--**********************************************************************************************************
--###############################################################################################
-- TODO 2: Complete the memory disambiguation
--################################################################################################
--*****************************************************************************************************************
-- Complete the processes to satisfy the memory disambiguation rules
-- do not issue a "lw" if number of address matches is greater than the number of "sw" skipping the "lw"
-- do not issue a "sw" if any lw with unkonwn address is lying ahead of it, you need the address of the lw to make an entry in the address buffer
-- as the sw is bypassing it.
--**************************************************************************************************************
-- These processes takes care of memory disambiguation
--=====================================================
-- 1. For an instruction being a valid "lw" it can only be issued when all the "sw"(with same address) in front of it had comitted
-- This case is substantiated by address match number being less than issuecounter signal which indicates that
-- all the "sw" that were issued earlier have comitted so one can issue the lw
-- 2. For an instruction being a valid "sw" it can be issued only if all the "lw" in front of it have their address ready, this
-- Precaution is needed because you need to store the address of any bypassing sw (for any lw) if the address matches
--**************************************************************************************************************
process ( AddrMatch0Num , AddrMatch0 , IssuqueCounter0 , Opcode ,InstructionValidBit,OutSelectTemp)
begin
OutSelectTemp2(0) <= OutSelectTemp(0) ; --initialize the signal OutSelectTemp2 = OutSelectTemp
if ( opcode(0) = '1' and InstructionValidBit(0) = '1' ) then --valid "lw"
if ( AddrMatch0 = '1' ) then
if ( AddrMatch0Num > IssuqueCounter0 ) then -- "lw" can not be issued only when no of matches is greater than no of "sw"s skipping "lw"
OutSelectTemp2(0) <= '0' ;
end if ;
end if ;
end if ;
end process ;
process ( AddrMatch1Num , AddrMatch1 , IssuqueCounter1 , OutSelectTemp ,
Opcode, AddrReadyBit, InstructionValidBit, ScanAddr0 , ScanAddr1)
begin
OutSelectTemp2(1) <= OutSelectTemp(1) ;
if ( InstructionValidBit(1) = '1' ) then
if ( opcode(1) = '1' ) then --"lw""
if ( AddrMatch1 = '1' ) then
if ( AddrMatch1Num > IssuqueCounter1 ) then
OutSelectTemp2(1) <= '0' ;
end if ;
end if ;
--**********************************************************************
-- -- Mod by PRASANJEET: 7/25/09
--**********************************************************************
if(InstructionValidBit(0)= '1' and (AddrReadyBit(0) = '0' or (AddrReadyBit(0) = '1' and ( ScanAddr0 = ScanAddr1 )))and opcode(0) = '0')then -- not ready "sw" in front
OutSelectTemp2(1)<='0';
end if;
--***********************************************************************
else -- this clause states that you can issue a "sw" in the following two cases: 1. there is a sw in fornt of it 2. it has lw with known address in fornt of it. NOTE: this portion of code emphasizes on the fact that a sw can't skip a lw with unknown address. (because you need to store the address of sw in the address buffer if it matches)
--//write code for OutSelectTemp 2, 3, 4, 5, 6, 7
--*****************************************************************************************
-- Mod by PRASANJEET: 7/26/09
--*****************************************************************************************
if( InstructionValidBit(0) = '1' and (opcode(0) = '1' and AddrReadyBit(0) = '0' )) then -- Mod by PRASANJEET: 7/26/09
OutSelectTemp2(1) <= '0';
end if;
--******************************************************************************************
end if ;
end if ;
end process ;
-- Going along the same lines complete the rest of the six processes
process ( AddrMatch2Num , AddrMatch2 , IssuqueCounter2 , Opcode ,OutSelectTemp ,
InstructionValidBit , AddrReadyBit, ScanAddr0 , ScanAddr1 , ScanAddr2)
begin
OutSelectTemp2(2) <= OutSelectTemp(2) ;
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
end process ;
process ( AddrMatch3Num, InstructionValidBit , AddrMatch3 , IssuqueCounter3 , Opcode ,OutSelectTemp,
AddrReadyBit, ScanAddr0 , ScanAddr1 , Scanaddr2, ScanAddr3 )
begin
OutSelectTemp2(3) <= OutSelectTemp(3) ;
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
end process ;
process ( AddrMatch4Num, InstructionValidBit , AddrMatch4 , IssuqueCounter4 , Opcode ,OutSelectTemp,
AddrReadyBit, ScanAddr0 , ScanAddr1 , Scanaddr2, ScanAddr3, ScanAddr4 )
begin
OutSelectTemp2(4) <= OutSelectTemp(4) ;
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
end process ;
process ( AddrMatch5Num, InstructionValidBit , AddrMatch5 , IssuqueCounter5 , Opcode ,OutSelectTemp,
AddrReadyBit, ScanAddr0 , ScanAddr1 , Scanaddr2, ScanAddr3, ScanAddr4, ScanAddr5 )
begin
OutSelectTemp2(5) <= OutSelectTemp(5) ;
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
end process ;
process ( AddrMatch6Num, InstructionValidBit , AddrMatch6 , IssuqueCounter6 , Opcode ,OutSelectTemp,
AddrReadyBit, ScanAddr0 , ScanAddr1 , Scanaddr2, ScanAddr3, ScanAddr4, ScanAddr5, ScanAddr6 )
begin
OutSelectTemp2(6) <= OutSelectTemp(6) ;
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
end process ;
process ( AddrMatch7Num, InstructionValidBit , AddrMatch7 , IssuqueCounter7 , Opcode ,OutSelectTemp,
AddrReadyBit, ScanAddr0 , ScanAddr1 , Scanaddr2, ScanAddr3, ScanAddr4, ScanAddr5, ScanAddr6, ScanAddr7 )
begin
OutSelectTemp2(7) <= OutSelectTemp(7) ;
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
end process ;
--##################################################################################################################
--***************************************************************************************
-- This process is used to assign priority so that only one instruction is issued even
-- when multiple instructions are ready to be issued
--***************************************************************************************
process ( OutSelectTemp2) --to issue only one at a time, priority is given over here
begin
Outtemp <= "000" ;
if ( OutSelectTemp2(0) = '1') then
Outtemp <= "000" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(1) = '1' ) then
Outtemp <= "001" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(2) = '1') then
Outtemp <= "010" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(3) = '1') then
Outtemp <= "011" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(4) = '1') then
Outtemp <= "100" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(5) = '1') then
Outtemp <= "101" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(6) = '1') then
Outtemp <= "110" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(7) = '1') then
Outtemp <= "111" ;
IssuequeReadyTemp <= '1' ;
else
IssuequeReadyTemp <= '0' ;
end if ;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process ;
OutSelect <= Outtemp ;
------------------------------------Done Generating OutSelect ------------------------------------------
--********************************************************************************************************
-- These processes keep track of bypassing "sw" for every entry of "lw"
-- The increment counter signal is sort of count enable that increments the corresponding counter for a "lw"
-- If the bypassing "sw" has the same address
--***********************************************************************************************************
process ( Outtemp , opcode , ScanAddr0 , ScanAddr1 , ScanAddr2 , ScanAddr3,
ScanAddr4 , ScanAddr5 , ScanAddr6 , ScanAddr7,Iss_LdStIssued ) -- generating the done signal as well as incrementing the counter to make note of sw skipping lw
begin --gives the total no. of address matches
IncrementCounter(0) <= '0' ;
if ( opcode(0) = '1' and Iss_LdStIssued = '1' ) then -- an "lw/sw" instruction is about to be issued so make a note of it
case Outtemp is
when "000" => IncrementCounter(0) <= '0' ;
when "001" => if ( ScanAddr0 = ScanAddr1 ) then
IncrementCounter(0) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(0) <= '0' ;
end if ;
when "010" => if ( ScanAddr0 = ScanAddr2 ) then
IncrementCounter(0) <= '1' ;
else
IncrementCounter(0) <= '0' ;
end if ;
when "011" => if ( ScanAddr0 = ScanAddr3 ) then
IncrementCounter(0) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(0) <= '0' ;
end if ;
when "100" => if ( ScanAddr0 = ScanAddr4 ) then
IncrementCounter(0) <= '1' ;
else
IncrementCounter(0) <= '0' ;
end if ;
when "101" => if ( ScanAddr0 = ScanAddr5 ) then
IncrementCounter(0) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(0) <= '0' ;
end if ;
when "110" => if ( ScanAddr0 = ScanAddr6 ) then
IncrementCounter(0) <= '1' ;
else
IncrementCounter(0) <= '0' ;
end if ;
when others => if ( ScanAddr0 = ScanAddr7 ) then
IncrementCounter(0) <= '1' ;
else
IncrementCounter(0) <= '0' ;
end if ;
end case ;
end if ;
end process ;
process ( Outtemp , opcode ,Iss_LdStIssued, ScanAddr1 , ScanAddr2 , ScanAddr3, ScanAddr4,
ScanAddr5, ScanAddr6, ScanAddr7)
begin
IncrementCounter(1) <= '0' ;
if ( opcode(1) = '1' and Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" => IncrementCounter(1) <= '0' ;
when "001" => IncrementCounter(1) <= '0' ;
when "010" => if ( ScanAddr1 = ScanAddr2) then
IncrementCounter(1) <= '1' ;
else
IncrementCounter(1) <= '0' ;
end if ;
when "011" => if ( ScanAddr1 = ScanAddr3 ) then
IncrementCounter(1) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(1) <= '0' ;
end if ;
when "100" => if ( ScanAddr1 = ScanAddr4 ) then
IncrementCounter(1) <= '1' ;
else
IncrementCounter(1) <= '0' ;
end if ;
when "101" => if ( ScanAddr1 = ScanAddr5 ) then
IncrementCounter(1) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(1) <= '0' ;
end if ;
when "110" => if ( ScanAddr1 = ScanAddr6 ) then
IncrementCounter(1) <= '1' ;
else
IncrementCounter(1) <= '0' ;
end if ;
when others => if ( ScanAddr1 = ScanAddr7 ) then
IncrementCounter(1) <= '1' ;
else
IncrementCounter(1) <= '0' ;
end if ;
end case ;
end if ;
end process ;
process ( Outtemp, opcode, ScanAddr2, ScanAddr3, ScanAddr4, ScanAddr5, ScanAddr6, ScanAddr7, Iss_LdStIssued )
begin
IncrementCounter(2) <= '0' ;
if ( opcode(2) = '1' and Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" => IncrementCounter(2) <= '0' ;
when "001" => IncrementCounter(2) <= '0' ;
when "010" => IncrementCounter(2) <= '0' ;
when "011" => if ( ScanAddr2 = ScanAddr3 ) then
IncrementCounter(2) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(2) <= '0' ;
end if ;
when "100" => if ( ScanAddr2 = ScanAddr4 ) then
IncrementCounter(2) <= '1' ;
else
IncrementCounter(2) <= '0' ;
end if ;
when "101" => if ( ScanAddr2 = ScanAddr5 ) then
IncrementCounter(2) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(2) <= '0' ;
end if ;
when "110" => if ( ScanAddr2 = ScanAddr6 ) then
IncrementCounter(2) <= '1' ;
else
IncrementCounter(2) <= '0' ;
end if ;
when others => if ( ScanAddr2 = ScanAddr7 ) then
IncrementCounter(2) <= '1' ;
else
IncrementCounter(2) <= '0' ;
end if ;
end case ;
end if;
end process ;
process ( Outtemp, opcode, ScanAddr3, ScanAddr4, ScanAddr5, ScanAddr6, ScanAddr7, Iss_LdStIssued )
begin
IncrementCounter(3) <= '0' ;
if ( opcode(3) = '1' and Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" => IncrementCounter(3) <= '0' ;
when "001" => IncrementCounter(3) <= '0' ;
when "010" => IncrementCounter(3) <= '0' ;
when "011" => IncrementCounter(3) <= '0' ;
when "100" => if ( ScanAddr3 = ScanAddr4 ) then
IncrementCounter(3) <= '1' ;
else
IncrementCounter(3) <= '0' ;
end if ;
when "101" => if ( ScanAddr3 = ScanAddr5 ) then
IncrementCounter(3) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(3) <= '0' ;
end if ;
when "110" => if ( ScanAddr3 = ScanAddr6 ) then
IncrementCounter(3) <= '1' ;
else
IncrementCounter(3) <= '0' ;
end if ;
when others => if ( ScanAddr3 = ScanAddr7 ) then
IncrementCounter(3) <= '1' ;
else
IncrementCounter(3) <= '0' ;
end if ;
end case ;
end if;
end process ;
process ( Outtemp, opcode, ScanAddr4, ScanAddr5, ScanAddr6, ScanAddr7, Iss_LdStIssued )
begin
IncrementCounter(4) <= '0' ;
if ( opcode(4) = '1' and Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" => IncrementCounter(4) <= '0' ;
when "001" => IncrementCounter(4) <= '0' ;
when "010" => IncrementCounter(4) <= '0' ;
when "011" => IncrementCounter(4) <= '0' ;
when "100" => IncrementCounter(4) <= '0' ;
when "101" => if ( ScanAddr4 = ScanAddr5 ) then
IncrementCounter(4) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(4) <= '0' ;
end if ;
when "110" => if ( ScanAddr4 = ScanAddr6 ) then
IncrementCounter(4) <= '1' ;
else
IncrementCounter(4) <= '0' ;
end if ;
when others => if ( ScanAddr4 = ScanAddr7 ) then
IncrementCounter(4) <= '1' ;
else
IncrementCounter(4) <= '0' ;
end if ;
end case ;
end if;
end process ;
process ( Outtemp, opcode, ScanAddr5, ScanAddr6, ScanAddr7, Iss_LdStIssued )
begin
IncrementCounter(5) <= '0' ;
if ( opcode(5) = '1' and Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" => IncrementCounter(5) <= '0' ;
when "001" => IncrementCounter(5) <= '0' ;
when "010" => IncrementCounter(5) <= '0' ;
when "011" => IncrementCounter(5) <= '0' ;
when "100" => IncrementCounter(5) <= '0' ;
when "101" => IncrementCounter(5) <= '0' ;
when "110" => if ( ScanAddr5 = ScanAddr6 ) then
IncrementCounter(5) <= '1' ;
else
IncrementCounter(5) <= '0' ;
end if ;
when others => if ( ScanAddr5 = ScanAddr7 ) then
IncrementCounter(5) <= '1' ;
else
IncrementCounter(5) <= '0' ;
end if ;
end case ;
end if;
end process ;
process ( Outtemp, opcode, ScanAddr6, ScanAddr7, Iss_LdStIssued )
begin
IncrementCounter(6) <= '0' ;
if ( opcode(6) = '1' and Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" => IncrementCounter(6) <= '0' ;
when "001" => IncrementCounter(6) <= '0' ;
when "010" => IncrementCounter(6) <= '0' ;
when "011" => IncrementCounter(6) <= '0' ;
when "100" => IncrementCounter(6) <= '0' ;
when "101" => IncrementCounter(6) <= '0' ;
when "110" => IncrementCounter(6) <= '0' ;
when others => if ( ScanAddr6 = ScanAddr7 ) then
IncrementCounter(6) <= '1' ;
else
IncrementCounter(6) <= '0' ;
end if ;
end case ;
end if;
end process ;
IncrementCounter(7) <= '0' ; --since the last so will always be '0'
----------------------------------- Generating Address Update Condition--------------------
--********************************************************************************************************************************
-- This process takes care of address updating conditions, there are two control signals
-- 1. the addrupdate which tell i need to update the "rs" field data for address calculation on this entry
-- 2. The addrupdate sel which when "0" indicates that i have the valid rs field data with me so i update myself with my own data
-- when "1" indicates that i will get the updated rs field data from the entry above me
--*********************************************************************************************************************************
process ( RsDataValidBit, Entemp, Outtemp, AddrReadyBit, Iss_LdStIssued, InstructionValidBit)
begin
AddrUpdate <= "00000000" ; -- i want to update this address
AddrUpdateSel <= "00000000" ; -- whether to update from the one above me (1)/or from me(0)
if( Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" =>
AddrUpdateSel (7 downto 0) <= '0' & RsDataValidBit (7 downto 1);
for i in 0 to 6 loop
if (RsDataValidBit (i+1) = '1') then
AddrUpdate (i) <= not AddrReadyBit(i+1); -- if address is ready no need to update!!
end if;
end loop;
AddrUpdate (7) <= '0';
when "001" =>
if( (RsDataValidBit(0) ='1') and (AddrReadyBit(0) = '0') ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
AddrUpdateSel (7 downto 1) <= '0' & RsDataValidBit (7 downto 2);
for i in 1 to 6 loop
if (RsDataValidBit (i+1) = '1') then
AddrUpdate (i) <= not AddrReadyBit (i+1);
end if;
end loop;
AddrUpdate (7) <= '0';
when "010" =>
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
if(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '0' ;
end if;
AddrUpdateSel (7 downto 2) <= '0' & RsDataValidBit (7 downto 3);
for i in 2 to 6 loop
if (RsDataValidBit (i+1) = '1') then
AddrUpdate (i) <= not AddrReadyBit (i+1);
end if;
end loop;
AddrUpdate (7) <= '0';
when "011" =>
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
if(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '0' ;
end if;
if(RsDataValidBit(2) = '1' and AddrReadyBit(2) = '0' ) then
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '0' ;
end if;
AddrUpdateSel (7 downto 3) <= '0' & RsDataValidBit (7 downto 4);
for i in 3 to 6 loop
if (RsDataValidBit (i+1) = '1') then
AddrUpdate (i) <= not AddrReadyBit (i+1);
end if;
end loop;
AddrUpdate (7) <= '0';
when "100" =>
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
if(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '0' ;
end if;
if(RsDataValidBit(2) = '1' and AddrReadyBit(2) = '0' ) then
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '0' ;
end if;
if(RsDataValidBit(3) = '1' and AddrReadyBit(3) = '0' ) then
AddrUpdate(3) <= '1';
AddrUpdateSel(3) <= '0' ;
end if;
AddrUpdateSel (7 downto 4) <= '0' & RsDataValidBit (7 downto 5);
for i in 4 to 6 loop
if (RsDataValidBit (i+1) = '1') then
AddrUpdate (i) <= not AddrReadyBit (i+1);
end if;
end loop;
AddrUpdate (7) <= '0';
when "101" =>
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
if(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '0' ;
end if;
if(RsDataValidBit(2) = '1' and AddrReadyBit(2) = '0' ) then
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '0' ;
end if;
if(RsDataValidBit(3) = '1' and AddrReadyBit(3) = '0' ) then
AddrUpdate(3) <= '1';
AddrUpdateSel(3) <= '0' ;
end if;
if(RsDataValidBit(4) = '1' and AddrReadyBit(4) = '0' ) then
AddrUpdate(4) <= '1';
AddrUpdateSel(4) <= '0' ;
end if;
AddrUpdateSel (7 downto 5) <= '0' & RsDataValidBit (7 downto 6);
for i in 5 to 6 loop
if (RsDataValidBit (i+1) = '1') then
AddrUpdate (i) <= not AddrReadyBit (i+1);
end if;
end loop;
AddrUpdate (7) <= '0';
when "110" =>
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
if(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '0' ;
end if;
if(RsDataValidBit(2) = '1' and AddrReadyBit(2) = '0' ) then
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '0' ;
end if;
if(RsDataValidBit(3) = '1' and AddrReadyBit(3) = '0' ) then
AddrUpdate(3) <= '1';
AddrUpdateSel(3) <= '0' ;
end if;
if(RsDataValidBit(4) = '1' and AddrReadyBit(4) = '0' ) then
AddrUpdate(4) <= '1';
AddrUpdateSel(4) <= '0' ;
end if;
if(RsDataValidBit(5) = '1' and AddrReadyBit(5) = '0' ) then
AddrUpdate(5) <= '1';
AddrUpdateSel(5) <= '0' ;
end if;
AddrUpdateSel (7 downto 6) <= '0' & RsDataValidBit (7);
if (RsDataValidBit (7) = '1') then
AddrUpdate (6) <= not AddrReadyBit (7);
end if;
AddrUpdate (7) <= '0';
when others =>
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
if(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '0' ;
end if;
if(RsDataValidBit(2) = '1' and AddrReadyBit(2) = '0' ) then
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '0' ;
end if;
if(RsDataValidBit(3) = '1' and AddrReadyBit(3) = '0' ) then
AddrUpdate(3) <= '1';
AddrUpdateSel(3) <= '0' ;
end if;
if(RsDataValidBit(4) = '1' and AddrReadyBit(4) = '0' ) then
AddrUpdate(4) <= '1';
AddrUpdateSel(4) <= '0' ;
end if;
if(RsDataValidBit(5) = '1' and AddrReadyBit(5) = '0' ) then
AddrUpdate(5) <= '1';
AddrUpdateSel(5) <= '0' ;
end if;
if(RsDataValidBit(6) = '1' and AddrReadyBit(6) = '0' ) then
AddrUpdate(6) <= '1';
AddrUpdateSel(6) <= '0' ;
end if;
AddrUpdate(7) <= '0';
AddrUpdateSel(7) <= '0' ;
end case ;
else
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
elsif(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
if ( Entemp(0) = '0' ) then
AddrUpdate(1) <= '1'; --not moving so update myself
AddrUpdateSel(1) <= '0' ;
else
AddrUpdate(0) <= '1'; -- update as per the below one is moving
AddrUpdateSel(0) <= '1' ;
end if ;
elsif(RsDataValidBit(2) = '1' and AddrReadyBit(2) = '0' ) then
if ( Entemp(1) = '0' ) then
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '0' ;
else
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '1' ;
end if ;
elsif(RsDataValidBit(3) = '1' and AddrReadyBit(3) = '0' ) then
if ( Entemp(2) = '0' ) then
AddrUpdate(3) <= '1';
AddrUpdateSel(3) <= '0' ;
else
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '1' ;
end if;
elsif(RsDataValidBit(4) = '1' and AddrReadyBit(4) = '0' ) then
if ( Entemp(3) = '0' ) then
AddrUpdate(4) <= '1'; --not moving so update myself
AddrUpdateSel(4) <= '0' ;
else
AddrUpdate(3) <= '1'; -- update as per the below one is moving
AddrUpdateSel(3) <= '1' ;
end if ;
elsif(RsDataValidBit(5) = '1' and AddrReadyBit(5) = '0' ) then
if ( Entemp(4) = '0' ) then
AddrUpdate(5) <= '1';
AddrUpdateSel(5) <= '0' ;
else
AddrUpdate(4) <= '1';
AddrUpdateSel(4) <= '1' ;
end if ;
elsif(RsDataValidBit(6) = '1' and AddrReadyBit(6) = '0' ) then
if ( Entemp(5) = '0' ) then
AddrUpdate(6) <= '1';
AddrUpdateSel(6) <= '0' ;
else
AddrUpdate(5) <= '1';
AddrUpdateSel(5) <= '1' ;
end if;
elsif(RsDataValidBit(7) = '1' and AddrReadyBit(7) = '0' ) then
if ( Entemp(6) = '0' ) then
AddrUpdate(7) <= '1';
AddrUpdateSel(7) <= '0' ;
else
AddrUpdate(6) <= '1';
AddrUpdateSel(6) <= '1' ;
end if;
else
AddrUpdate <= "00000000" ; -- i want to update this address
AddrUpdateSel <= "00000000" ;
end if;
end if ;
end process;
-----------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- hereonwards same as in issuequeues
----------------------------------------------------------------------
------------------------------- Generating Flush Condition for Queues -----------------
--###############################################################################################
-- TODO 3: Calculation of buffer depth to help in selective flushing
-- fill in the eight expressions
--################################################################################################
-- you arrive at the younger instruction to branch by first calcualting its depth using the tag and top pointer of rob
-- and comparing its depth with depth of branch instruction (known as Cdb_RobDepth)
Buffer0Depth <= --------------------------; //unsigned subraction
Buffer1Depth <= --------------------------;
Buffer2Depth <= --------------------------;
Buffer3Depth <= --------------------------;
Buffer4Depth <= --------------------------;
Buffer5Depth <= --------------------------;
Buffer6Depth <= --------------------------;
Buffer7Depth <= --------------------------;
--################################################################################################
--****************************************************************************************
-- This process takes care of selective flushing and also takes care of shift aspect while
-- doing the selective flushing, i.e if 1 get a shift update signal then instead of flushing
-- myself 1 will be 0 instead (as 1 gets shifted to the place of 0) but remember when flushing
-- 1 you will be checking bufferdepth 1 and entemp(0) as entemp(0) means 1 is shifting to 0 place
--******************************************************************************************
--###############################################################################################
-- TODO 4: Complete the code on selective flusing
-- fill in the missing expressions
-- NOTE: Remember the queue is from 7 downto 0
-- buffer 7th is at top so dispatch writes to it
-- buffer 0 is at the bottom
--################################################################################################
process ( Cdb_Flush , Cdb_RobDepth , Buffer0Depth , Buffer1Depth ,
Buffer2Depth , Buffer3Depth, Buffer4Depth, Buffer5Depth,
Buffer7Depth, Buffer6Depth, Entemp, InstructionValidBit)
begin
Flush <= "00000000";
if ( Cdb_Flush = '1' ) then
if ( Buffer0Depth > Cdb_RobDepth ) then --note this depth is calculated with respect to branch instruction
if ( EnTemp(0) = '0' ) then
Flush(0) <= InstructionValidBit(0) ;
end if ;
end if ;
if ( Buffer1Depth > Cdb_RobDepth ) then
if ( Entemp(0) = '1' ) then
Flush(0) <= ---------------------------------------; Hint: Take into account the shift mechanism so is it i or i+1 or i - 1? -- flush only when instructionvalidbit is 1??? only flush the valid instructions //similar to integer_queue
else
Flush(1) <= InstructionValidBit(1) ;
end if ;
else
Flush(1) <= '0' ;
end if ;
if ( Buffer2Depth > Cdb_RobDepth ) then
if ( Entemp(1) = '1' ) then
Flush(1) <= ---------------------------------------;
else
Flush(2) <= InstructionValidBit(2) ;
end if ;
else
Flush(2) <= '0' ;
end if ;
if ( Buffer3Depth > Cdb_RobDepth ) then
if ( Entemp(2) = '1' ) then
Flush(2) <= ---------------------------------------;
else
Flush(3) <= InstructionValidBit(3) ;
end if ;
else
Flush(3) <= '0' ;
end if ;
if ( Buffer4Depth > Cdb_RobDepth ) then
if ( Entemp(3) = '1' ) then
Flush(3) <= ---------------------------------------;
else
Flush(4) <= InstructionValidBit(4) ;
end if ;
else
Flush(4) <= '0' ;
end if ;
if ( Buffer5Depth > Cdb_RobDepth ) then
if ( Entemp(4) = '1' ) then
Flush(4) <= ---------------------------------------;
else
Flush(5) <= InstructionValidBit(5) ;
end if ;
else
Flush(5) <= '0' ;
end if ;
if ( Buffer6Depth > Cdb_RobDepth ) then
if ( Entemp(5) = '1' ) then
Flush(5) <= ---------------------------------------;
else
Flush(6) <= InstructionValidBit(6) ;
end if ;
else
Flush(6) <= '0' ;
end if ;
if ( Buffer7Depth > Cdb_RobDepth ) then
if ( Entemp(6) = '1' ) then
Flush(6) <= ---------------------------------------;
else
Flush(7) <= InstructionValidBit(7) ;
end if ;
else
Flush(7) <= '0' ;
end if ;
end if ;
end process ;
-------------------- Done Generating Flush Condition ----------------------
--################################################################################################
---------------------- Generating Rs and Rt Select for Queues to Update from Dispatch -----
Sel0 <= Dis_LdIssquenable ;
En <= Entemp ;
--***********************************************************************
-- this process deals with generation of enable temp signal
--***********************************************************************
process ( OutTemp, Iss_LdStIssued, InstructionValidBit, Dis_LdIssquenable )
begin
if ( Iss_LdStIssued = '1' ) then
Case (OutTemp) is
when "000" => Entemp <= "11111111" ;
when "001" => Entemp <= "11111110" ;
when "010" => Entemp <= "11111100" ;
when "011" => Entemp <= "11111000" ;
when "100" => Entemp <= "11110000" ;
when "101" => Entemp <= "11100000" ;
when "110" => Entemp <= "11000000" ;
when others => Entemp <= "10000000" ;
end case ;
else
Entemp(0) <= not (InstructionValidBit(0));
Entemp(1) <= ( not (InstructionValidBit(1))) or ( not (InstructionValidBit(0) )) ;
Entemp(2) <= (not (InstructionValidBit(2)))or (not (InstructionValidBit(1) )) or ( not (InstructionValidBit(0) ));
Entemp(3) <= (not (InstructionValidBit(3))) or (not (InstructionValidBit(2) ))or
( not (InstructionValidBit(1) )) or ( not (InstructionValidBit(0) ) ) ;
Entemp(4) <= (not (InstructionValidBit(4))) or (not (InstructionValidBit(3))) or
(not (InstructionValidBit(2) ))or( not (InstructionValidBit(1) )) or ( not (InstructionValidBit(0) ) ) ;
Entemp(5) <= (not (InstructionValidBit(5))) or (not (InstructionValidBit(4))) or (not (InstructionValidBit(3))) or
(not (InstructionValidBit(2) ))or( not (InstructionValidBit(1) )) or ( not (InstructionValidBit(0) ) ) ;
Entemp(6) <= (not (InstructionValidBit(6))) or (not (InstructionValidBit(5))) or
(not (InstructionValidBit(4))) or (not (InstructionValidBit(3))) or
(not (InstructionValidBit(2) ))or( not (InstructionValidBit(1) )) or ( not (InstructionValidBit(0) ) ) ;
Entemp(7) <= Dis_LdIssquenable or (not (InstructionValidBit(6))) or (not (InstructionValidBit(5))) or
(not (InstructionValidBit(4))) or (not (InstructionValidBit(3))) or(not (InstructionValidBit(2) )) or
( not (InstructionValidBit(1) )) or ( not (InstructionValidBit(0) ) ) ;
end if ;
end process ;
--*******************************************************************************************
-- This process does updation of rs data as done in issuequecntrl
--********************************************************************************************
process ( Buffer0RsTag ,Buffer1RsTag, Buffer2RsTag, Buffer3RsTag, InstructionValidBit,
Buffer7RsTag, Buffer4RsTag, Buffer5RsTag, Buffer6RsTag, Cdb_RdPhyAddr, Cdb_Valid, Entemp, RsDataValidBit,Cdb_PhyRegWrite)
begin
Sel1Rs <= "00000000" ;
if ( Cdb_Valid = '1' ) then --updation from CDB
if ( Buffer0RsTag = Cdb_RdPhyAddr and RsDataValidBit(0) ='0' and InstructionValidBit(0) = '1' and Cdb_PhyRegWrite ='1' ) then
Sel1Rs(0) <= '1' ;
end if ;
if ( Buffer1RsTag = Cdb_RdPhyAddr and RsDataValidBit(1) ='0'and InstructionValidBit(1) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (0) = '1' ) then
Sel1Rs(0) <= '1' ;
else
Sel1Rs(1) <= '1' ;
end if ;
end if ;
if ( Buffer2RsTag = Cdb_RdPhyAddr and RsDataValidBit(2) ='0'and InstructionValidBit(2) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (1) = '1' ) then
Sel1Rs(1) <= '1' ;
else
Sel1Rs(2) <= '1' ;
end if ;
end if ;
if ( Buffer3RsTag = Cdb_RdPhyAddr and RsDataValidBit(3) ='0'and InstructionValidBit(3) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (2) = '1' ) then
Sel1Rs(2) <= '1' ;
else
Sel1Rs(3) <= '1' ;
end if ;
end if ;
if ( Buffer4RsTag = Cdb_RdPhyAddr and RsDataValidBit(4) ='0'and InstructionValidBit(4) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (3) = '1' ) then
Sel1Rs(3) <= '1' ;
else
Sel1Rs(4) <= '1' ;
end if ;
end if ;
if ( Buffer5RsTag = Cdb_RdPhyAddr and RsDataValidBit(5) ='0'and InstructionValidBit(5) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (4) = '1' ) then
Sel1Rs(4) <= '1' ;
else
Sel1Rs(5) <= '1' ;
end if ;
end if ;
if ( Buffer6RsTag = Cdb_RdPhyAddr and RsDataValidBit(6) ='0'and InstructionValidBit(6) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (5) = '1' ) then
Sel1Rs(5) <= '1' ;
else
Sel1Rs(6) <= '1' ;
end if ;
end if ;
if ( Buffer7RsTag = Cdb_RdPhyAddr and RsDataValidBit(7) ='0' and InstructionValidBit(7) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (6) = '1' ) then
Sel1Rs(6) <= '1' ;
else
Sel1Rs(7) <= '1' ;
end if ;
end if ;
else
Sel1Rs <= "00000000" ;
end if ;
end process ;
end behavctrl ;
---------------------------------------------------------------------------------------------------- |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity receiver is
end entity receiver;
-- code from book
architecture behavioral of receiver is
-- . . . -- type declarations, etc
-- not in book
subtype packet_index_range is integer range 1 to 8;
type packet_array is array (packet_index_range) of bit;
-- end not in book
signal recovered_data : bit;
signal recovered_clock : bit;
-- . . .
procedure receive_packet ( signal rx_data : in bit;
signal rx_clock : in bit;
data_buffer : out packet_array ) is
begin
for index in packet_index_range loop
wait until rx_clock = '1';
data_buffer(index) := rx_data;
end loop;
end procedure receive_packet;
begin
packet_assembler : process is
variable packet : packet_array;
begin
-- . . .
receive_packet ( recovered_data, recovered_clock, packet );
-- . . .
end process packet_assembler;
-- . . .
-- not in book
data_generator : recovered_data <= '1' after 5 ns,
'0' after 15 ns,
'1' after 25 ns,
'0' after 35 ns,
'0' after 45 ns,
'1' after 55 ns,
'0' after 65 ns,
'1' after 75 ns;
clock_generator : process is
begin
recovered_clock <= '0' after 2 ns, '1' after 10 ns;
wait for 10 ns;
end process clock_generator;
-- end not in book
end architecture behavioral;
-- end code from book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity receiver is
end entity receiver;
-- code from book
architecture behavioral of receiver is
-- . . . -- type declarations, etc
-- not in book
subtype packet_index_range is integer range 1 to 8;
type packet_array is array (packet_index_range) of bit;
-- end not in book
signal recovered_data : bit;
signal recovered_clock : bit;
-- . . .
procedure receive_packet ( signal rx_data : in bit;
signal rx_clock : in bit;
data_buffer : out packet_array ) is
begin
for index in packet_index_range loop
wait until rx_clock = '1';
data_buffer(index) := rx_data;
end loop;
end procedure receive_packet;
begin
packet_assembler : process is
variable packet : packet_array;
begin
-- . . .
receive_packet ( recovered_data, recovered_clock, packet );
-- . . .
end process packet_assembler;
-- . . .
-- not in book
data_generator : recovered_data <= '1' after 5 ns,
'0' after 15 ns,
'1' after 25 ns,
'0' after 35 ns,
'0' after 45 ns,
'1' after 55 ns,
'0' after 65 ns,
'1' after 75 ns;
clock_generator : process is
begin
recovered_clock <= '0' after 2 ns, '1' after 10 ns;
wait for 10 ns;
end process clock_generator;
-- end not in book
end architecture behavioral;
-- end code from book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity receiver is
end entity receiver;
-- code from book
architecture behavioral of receiver is
-- . . . -- type declarations, etc
-- not in book
subtype packet_index_range is integer range 1 to 8;
type packet_array is array (packet_index_range) of bit;
-- end not in book
signal recovered_data : bit;
signal recovered_clock : bit;
-- . . .
procedure receive_packet ( signal rx_data : in bit;
signal rx_clock : in bit;
data_buffer : out packet_array ) is
begin
for index in packet_index_range loop
wait until rx_clock = '1';
data_buffer(index) := rx_data;
end loop;
end procedure receive_packet;
begin
packet_assembler : process is
variable packet : packet_array;
begin
-- . . .
receive_packet ( recovered_data, recovered_clock, packet );
-- . . .
end process packet_assembler;
-- . . .
-- not in book
data_generator : recovered_data <= '1' after 5 ns,
'0' after 15 ns,
'1' after 25 ns,
'0' after 35 ns,
'0' after 45 ns,
'1' after 55 ns,
'0' after 65 ns,
'1' after 75 ns;
clock_generator : process is
begin
recovered_clock <= '0' after 2 ns, '1' after 10 ns;
wait for 10 ns;
end process clock_generator;
-- end not in book
end architecture behavioral;
-- end code from book
|
-------------------------------------------------------------- ------------
-- filename: ro_filt_3x3.vhd
-- author: Tony Nelson
-- date: 12/21/99
--
-- detail: 3x3 Rank Order Filter. Generic order sets filter order.
-- order: integer:= 5 is a Median Filter.
--
-- auditoria
----------------------------------- ----------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ro_filt_3x3 is
generic (
vwidth: integer:=8;
order: integer:=5;
num_cols: integer:=16;
num_rows: integer:=16
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
Dout : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic;
FColPos : out integer;
FRowPos : out integer
);
end ro_filt_3x3;
architecture ro_filt_3x3 of ro_filt_3x3 is
component sort_3x3
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
w11 : in std_logic_vector((vwidth -1) downto 0);
w12 : in std_logic_vector((vwidth -1) downto 0);
w13 : in std_logic_vector((vwidth -1) downto 0);
w21 : in std_logic_vector((vwidth-1) downto 0);
w22 : in std_logic_vector((vwidth -1) downto 0);
w23 : in std_logic_vector((vwidth -1) downto 0);
w31 : in std_logic_vector((vwidth -1) downto 0);
w32 : in std_logic_vector((vwidth -1) downto 0);
w33 : in std_logic_vector((vwidth-1) downto 0);
DVw : in std_logic;
DVs : out std_logic;
s1 : out std_logic_vector(vwidth -1 downto 0);
s2 : out std_logic_vector(vwidth -1 downto 0);
s3 : out std_logic_vector(vwidth -1 downto 0);
s4 : out std_logic_vector(vwidth-1 downto 0);
s5 : out std_logic_vector(vwidth -1 downto 0);
s6 : out std_logic_vector(vwidth -1 downto 0);
s7 : out std_logic_vector(vwidth -1 downto 0);
s8 : out std_logic_vector(vwidth -1 downto 0);
s9 : out std_logic_vector(vwidth -1 downto 0)
);
end component sort_3x3;
signal w11: std_logic_vector((vwidth -1) downto 0);
signal w12: std_logic_vector((vwidth -1) downto 0);
signal w13: std_logic_vector((vwidth -1) downto 0);
signal w21: std_logic_vector((vwidth -1) downto 0);
signal w22: std_logic_vector((vwidth-1) downto 0);
signal w23: std_logic_vector((vwidth -1) downto 0);
signal w31: std_logic_vector((vwidth -1) downto 0);
signal w32: std_logic_vector((vwidth -1) downto 0);
signal w33: std_logic_vector((vwidth -1) downto 0);
signal DVw: std_logic;
signal DVs: std_logic;
signal s1: std_logic_vector(vwidth -1 downto 0);
signal s2: std_logic_vector(vwidth -1 downto 0);
signal s3: std_logic_vector(vwidth -1 downto 0);
signal s4: std_logic_vector(vwidth -1 downto 0);
signal s5: std_logic_vector(vwidth-1 downto 0);
signal s6: std_logic_vector(vwidth -1 downto 0);
signal s7: std_logic_vector(vwidth -1 downto 0);
signal s8: std_logic_vector(vwidth -1 downto 0);
signal s9: std_logic_vector(vwidth -1 downto 0);
component window_3x3
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
w11 : out std_logic_vector(vwidth -1 downto 0);
w12 : out std_logic_vector(vwidth -1 downto 0);
w13 : out std_logic_vector(vwidth-1 downto 0);
w21 : out std_logic_vector(vwidth -1 downto 0);
w22 : out std_logic_vector(vwidth -1 downto 0);
w23 : out std_logic_vector(vwidth -1 downto 0);
w31 : out std_logic_vector(vwidth -1 downto 0);
w32 : out std_logic_vector(vwidth-1 downto 0);
w33 : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic:='0'
);
end component window_3x3;
component rc_counter
generic (
num_cols: integer:=16;
num_rows: integer:=16
);
port (
Clk : in std_logic;
RSTn : in std_logic;
En : in std_logic;
ColPos : out integer;
RowPos : out integer
);
end component rc_counter;
signal ColPos: integer:=0;
signal RowPos: integer:=0;
signal ColPos_c: integer:=0; -- corrected positions
signal RowPos_c: integer:=0;
signal rt1: integer:=0;
signal rt2: integer:=0;
signal rt3: integer:=0;
signal rt4: integer:=0;
signal rt5: integer:=0;
signal rt6: integer:=0;
signal rt7: integer:=0;
signal rt8: integer:=0;
signal rt9: integer:=0;
signal rt10: integer:=0;
signal rt11: integer:=0;
signal rt12: integer:=0;
signal rt13: integer:=0;
signal rt14: integer:=0;
signal rt15: integer:=0;
signal rt16: integer:=0;
signal flag: std_logic:='0';
begin
sort_3x3x: sort_3x3
generic map (
vwidth => 8
)
port map (
Clk => Clk,
RSTn => RSTn,
w11 => w11,
w12 => w12,
w13 => w13,
w21 => w21,
w22 => w22,
w23 => w23,
w31 => w31,
w32 => w32,
w33 => w33,
DVw => DVw,
DVs => DVs,
s1 => s1,
s2 => s2,
s3 => s3,
s4 => s4,
s5 => s5,
s6 => s6,
s7 => s7,
s8 => s8,
s9 => s9
);
window_3x3x: window_3x3
generic map (
vwidth => 8
)
port map (
Clk => Clk,
RSTn => RSTn,
D => D,
w11 => w11,
w12 => w12,
w13 => w13,
w21 => w21,
w22 => w22,
w23 => w23,
w31 => w31,
w32 => w32,
w33 => w33,
DV => DVw
);
rc_counterx: rc_counter
generic map (
num_cols => 16,
num_rows => 16
)
port map (
Clk => Clk,
RSTn => RSTn,
En => RSTn,
ColPos => ColPos,
RowPos => RowPos
);
FColPos <= ColPos;
FRowPos <= RowPos;
ro_filt_proc: process(RSTn,Clk)
begin
if RSTn = '0' then
ColPos_c <= 0;
rt1 <= 0;
rt2 <= 0;
rt3 <= 0;
rt4 <= 0;
rt5 <= 0;
rt6 <= 0;
rt7 <= 0;
rt8 <= 0;
rt9 <= 0;
rt10 <= 0;
rt11 <= 0;
rt12 <= 0;
rt13 <= 0;
rt14 <= 0;
rt15 <= 0;
rt16 <= 0;
RowPos_c <= 0;
Dout <= (others=>'0');
DV <= '0';
flag <= '0';
elsif rising_edge(Clk) then
-- counter correction
ColPos_c <= ((ColPos-17) mod 16);-- ojo aquí antes era 512 --ojo con el 17);
rt1 <= ((RowPos-1) mod 16);-- ojo aquí antes era 512);
rt2 <= rt1;
rt3 <= rt2;
rt4 <= rt3;
rt5 <= rt4;
rt6 <= rt5;
rt7 <= rt6;
rt8 <= rt7;
rt9 <= rt8;
rt10 <= rt9;
rt11 <= rt10;
rt12 <= rt11;
rt13 <= rt12;
rt14 <= rt13;
rt15 <= rt14;
rt16 <= rt15;
RowPos_c <= rt16;
-- screen edge detection
if (ColPos_c = num_cols-1) or (RowPos_c = num_rows-1) or (ColPos_c
= num_cols-2) or (RowPos_c = 0) then
Dout <= (others=>'0');
else
if order = 1 then
Dout <= s1;
elsif order = 2 then
Dout <= s2;
elsif order = 3 then
Dout <= s3;
elsif order = 4 then
Dout <= s4;
elsif order = 5 then
Dout <= s5;
elsif order = 6 then
Dout <= s6;
elsif order = 7 then
Dout <= s7;
elsif order = 8 then
Dout <= s8;
elsif order = 9 then
Dout <= s9;
end if;
end if;
if ColPos >= 1 and RowPos >= 2 then -- antes eran 17 y 1(por que 1???)
DV <= '1';
flag <= '1';
elsif flag = '1' then
DV <= '1';
else
DV <= '0';
end if;
end if;
end process;
end ro_filt_3x3;
|
--------------------------------------------------------------------------------
-- Company: UMD ECE
-- Engineers: Benjamin Doiron, Daniel Noyes
--
-- Create Date: 12:35:25 03/26/2014
-- Design Name: Scan to Hex Testbench
-- Module Name: scan_to_hex_tb
-- Project Name: Risc Machine Project 1
-- Target Device: Spartan 3E Board
-- Tool versions: Xilinx 14.7
-- Description: This is the testbench for reading scancodes and changing them into hex.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY scan_to_hex_tb IS
END scan_to_hex_tb;
ARCHITECTURE behavior OF scan_to_hex_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT scan_to_hex
PORT(
Send : IN std_logic;
Resetn : IN std_logic;
scancode : IN std_logic_vector(7 downto 0);
output : OUT std_logic_vector(23 downto 0);
outCount : out STD_LOGIC_VECTOR (3 downto 0);
hexdebug : out STD_LOGIC_VECTOR (3 downto 0);
outbufdebug : out STD_LOGIC_VECTOR (63 downto 0)
);
END COMPONENT;
--Inputs
signal Send : std_logic := '0';
signal Resetn : std_logic := '0';
signal scancode : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal hexdebug : std_logic_vector(3 downto 0);
signal output : std_logic_vector(23 downto 0);
signal counter : std_logic_vector(3 downto 0);
signal outbufdebug : STD_LOGIC_VECTOR (63 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: scan_to_hex PORT MAP (
Send => Send,
Resetn => Resetn,
scancode => scancode,
output => output,
outCount => counter,
hexdebug => hexdebug,
outbufdebug => outbufdebug
);
-- Stimulus process
stim_proc: process
begin
Resetn <= '1';
wait for 20 ns;
send <= '1';
scancode <= x"16";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"26";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"16";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"26";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"16";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"16";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"5A";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"36";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"46";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"36";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"46";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"23";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"23";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"5A";
wait for 20 ns;
send <= '0';
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity adder_tester_tb is
file TEST_FILE : text open READ_MODE is "testing_files/test_sum_float_23_6.txt";
constant TOTAL_BITS : integer := 23;
constant EXP_BITS : integer := 6;
constant PIPELINE_STEPS : integer := 6;
end entity;
architecture adder_tester_tb_arq of adder_tester_tb is
signal enable_in : std_logic := '0';
signal reset_in : std_logic := '0';
signal clk_in : std_logic := '0';
signal number_1_in : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
signal number_2_in : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
signal result : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
signal expected_result_before : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
signal expected_result_after : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
component floating_point_adder is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
enable : in std_logic;
reset : in std_logic;
clk : in std_logic;
number_1_in : in std_logic_vector(TOTAL_BITS - 1 downto 0);
number_2_in : in std_logic_vector(TOTAL_BITS - 1 downto 0);
result: out std_logic_vector(TOTAL_BITS - 1 downto 0)
);
end component;
component shift_register is
generic(REGISTRY_BITS : integer := 32;
STEPS : integer := 4);
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
D: in std_logic_vector(REGISTRY_BITS - 1 downto 0);
Q: out std_logic_vector(REGISTRY_BITS - 1 downto 0)
);
end component;
for floating_point_adder_0 : floating_point_adder use entity work.floating_point_adder;
for shift_register_0 : shift_register use entity work.shift_register;
begin
shift_register_0 : shift_register
generic map(REGISTRY_BITS => TOTAL_BITS, STEPS => PIPELINE_STEPS + 1)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => expected_result_before,
Q => expected_result_after
);
floating_point_adder_0 : floating_point_adder
generic map(TOTAL_BITS => TOTAL_BITS, EXP_BITS => EXP_BITS)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
number_1_in => number_1_in,
number_2_in => number_2_in,
result => result
);
process
variable in_line : line;
variable number1_in : integer;
variable number2_in : integer;
variable precomputed_result_before : integer;
variable precomputed_result_after : integer;
variable to_integer_result : integer;
variable i : integer := 0;
begin
enable_in <= '1';
clk_in <= '0';
while not endfile(TEST_FILE) loop
readline(TEST_FILE, in_line);
read(in_line, number1_in);
read(in_line, number2_in);
read(in_line, precomputed_result_before);
--report "NUMBER 1: " & integer'image(number1_in);
--report "NUMBER 2: " & integer'image(number2_in);
number_1_in <= std_logic_vector(to_unsigned(number1_in, TOTAL_BITS));
number_2_in <= std_logic_vector(to_unsigned(number2_in, TOTAL_BITS));
expected_result_before <= std_logic_vector(to_unsigned(precomputed_result_before, TOTAL_BITS));
--One clock cycle
clk_in <= '1';
wait for 1 ns;
to_integer_result := to_integer(unsigned(result));
precomputed_result_after := to_integer(unsigned(expected_result_after));
--report "REGISTRY RESULT: " & integer'image(precomputed_result_after) & " ADDER RESULT: " & integer'image(to_integer_result);
if(i > PIPELINE_STEPS) then --dont compare in the first iterations because garbage leaves the registers
assert precomputed_result_after = to_integer_result report "EXPECTED: " & integer'image(precomputed_result_after) & " ACTUAL: " & integer'image(to_integer_result);
end if;
clk_in <= '0';
wait for 1 ns;
i := i + 1;
end loop;
--Compare remainder values
for i in 0 to PIPELINE_STEPS loop
clk_in <= '1';
wait for 100 ms;
to_integer_result := to_integer(unsigned(result));
precomputed_result_after := to_integer(unsigned(expected_result_after));
--report "REGISTRY RESULT: " & integer'image(precomputed_result_after) & " ADDER RESULT: " & integer'image(to_integer_result);
assert precomputed_result_after = to_integer_result report "EXPECTED: " & integer'image(precomputed_result_after) & " ACTUAL: " & integer'image(to_integer_result);
clk_in <= '0';
wait for 1 ns;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Reconfiguration engine for DRP enabled Xilinx primtives
--
-- Description:
-- ------------------------------------
-- Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration
-- Port (DRP) to reconfigure the primitive at runtime without reconfiguring then
-- whole FPGA.
-- This module is a DRP master that can be preconfigured at compile time with
-- different configuration sets. The configuration sets are mapped into a ROM.
-- The user can select a stored configuration with 'ConfigSelect' and sending a
-- strobe to 'Reconfig'. The Operation completes with an other strobe on
-- 'ReconfigDone'.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.xil.all;
entity xil_Reconfigurator is
generic (
DEBUG : BOOLEAN := FALSE; --
CLOCK_FREQ : FREQ := 100 MHz; --
CONFIG_ROM : in T_XIL_DRP_CONFIG_ROM := (0 downto 0 => C_XIL_DRP_CONFIG_SET_EMPTY) --
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Reconfig : in STD_LOGIC; --
ReconfigDone : out STD_LOGIC; --
ConfigSelect : in STD_LOGIC_VECTOR(log2ceilnz(CONFIG_ROM'length) - 1 downto 0); --
DRP_en : out STD_LOGIC; --
DRP_Address : out T_XIL_DRP_ADDRESS; --
DRP_we : out STD_LOGIC; --
DRP_DataIn : in T_XIL_DRP_DATA; --
DRP_DataOut : out T_XIL_DRP_DATA; --
DRP_Ack : in STD_LOGIC --
);
end;
architecture rtl of xil_Reconfigurator is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
attribute signal_ENCODING : STRING;
type T_STATE is (
ST_IDLE,
ST_READ_BEGIN, ST_READ_WAIT,
ST_WRITE_BEGIN, ST_WRITE_WAIT,
ST_DONE
);
-- DualConfiguration - Statemachine
signal State : T_STATE := ST_IDLE;
signal NextState : T_STATE;
attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", "speed1");
signal DataBuffer_en : STD_LOGIC;
signal DataBuffer_d : T_XIL_DRP_DATA := (others => '0');
signal ROM_Entry : T_XIL_DRP_CONFIG;
signal ROM_LastConfigWord : STD_LOGIC;
constant CONFIGINDEX_BITS : POSITIVE := log2ceilnz(CONFIG_ROM'length);
signal ConfigIndex_rst : STD_LOGIC;
signal ConfigIndex_en : STD_LOGIC;
signal ConfigIndex_us : UNSIGNED(CONFIGINDEX_BITS - 1 downto 0);
attribute KEEP OF ROM_LastConfigWord : signal IS DEBUG;
begin
-- configuration ROM
blkCONFIG_ROM : block
signal SetIndex : inTEGER range 0 to CONFIG_ROM'high;
signal RowIndex : T_XIL_DRP_CONFIG_INDEX;
attribute KEEP OF SetIndex : signal IS DEBUG;
attribute KEEP OF RowIndex : signal IS DEBUG;
begin
SetIndex <= to_index(ConfigSelect, CONFIG_ROM'high);
RowIndex <= to_index(ConfigIndex_us, T_XIL_DRP_CONFIG_INDEX'high);
ROM_Entry <= CONFIG_ROM(SetIndex).Configs(RowIndex);
ROM_LastConfigWord <= to_sl(RowIndex = CONFIG_ROM(SetIndex).LastIndex);
end block;
-- configuration index counter
process(Clock)
begin
if rising_edge(Clock) then
if ((Reset or ConfigIndex_rst) = '1') then
ConfigIndex_us <= (others => '0');
else
if (ConfigIndex_en = '1') then
ConfigIndex_us <= ConfigIndex_us + 1;
end if;
end if;
end if;
end process;
-- data buffer for DRP configuration words
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
DataBuffer_d <= (others => '0');
else
if (DataBuffer_en = '1') then
DataBuffer_d <= ((DRP_DataIn and not ROM_Entry.Mask) or
(ROM_Entry.Data and ROM_Entry.Mask));
end if;
end if;
end if;
end process;
-- assign DRP signals
DRP_Address <= ROM_Entry.Address;
DRP_DataOut <= DataBuffer_d;
-- DRP read-modify-write statemachine
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
State <= ST_IDLE;
else
State <= NextState;
end if;
end if;
end process;
process(State, Reconfig, ROM_LastConfigWord, DRP_Ack )
begin
NextState <= State;
ReconfigDone <= '0';
-- Dynamic Reconfiguration Port
DRP_en <= '0';
DRP_we <= '0';
-- internal modules
ConfigIndex_rst <= '0';
ConfigIndex_en <= '0';
DataBuffer_en <= '0';
case State is
when ST_IDLE =>
if (Reconfig = '1') then
ConfigIndex_rst <= '1';
NextState <= ST_READ_BEGIN;
end if;
when ST_READ_BEGIN =>
DRP_en <= '1';
DRP_we <= '0';
NextState <= ST_READ_WAIT;
when ST_READ_WAIT =>
if (DRP_Ack = '1') then
DataBuffer_en <= '1';
NextState <= ST_WRITE_BEGIN;
end if;
when ST_WRITE_BEGIN =>
DRP_en <= '1';
DRP_we <= '1';
NextState <= ST_WRITE_WAIT;
when ST_WRITE_WAIT =>
if (DRP_Ack = '1') then
if (ROM_LastConfigWord = '1') then
NextState <= ST_DONE;
ELSE
ConfigIndex_en <= '1';
NextState <= ST_READ_BEGIN;
end if;
end if;
when ST_DONE =>
ReconfigDone <= '1';
NextState <= ST_IDLE;
end case;
end process;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Reconfiguration engine for DRP enabled Xilinx primtives
--
-- Description:
-- ------------------------------------
-- Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration
-- Port (DRP) to reconfigure the primitive at runtime without reconfiguring then
-- whole FPGA.
-- This module is a DRP master that can be preconfigured at compile time with
-- different configuration sets. The configuration sets are mapped into a ROM.
-- The user can select a stored configuration with 'ConfigSelect' and sending a
-- strobe to 'Reconfig'. The Operation completes with an other strobe on
-- 'ReconfigDone'.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.xil.all;
entity xil_Reconfigurator is
generic (
DEBUG : BOOLEAN := FALSE; --
CLOCK_FREQ : FREQ := 100 MHz; --
CONFIG_ROM : in T_XIL_DRP_CONFIG_ROM := (0 downto 0 => C_XIL_DRP_CONFIG_SET_EMPTY) --
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Reconfig : in STD_LOGIC; --
ReconfigDone : out STD_LOGIC; --
ConfigSelect : in STD_LOGIC_VECTOR(log2ceilnz(CONFIG_ROM'length) - 1 downto 0); --
DRP_en : out STD_LOGIC; --
DRP_Address : out T_XIL_DRP_ADDRESS; --
DRP_we : out STD_LOGIC; --
DRP_DataIn : in T_XIL_DRP_DATA; --
DRP_DataOut : out T_XIL_DRP_DATA; --
DRP_Ack : in STD_LOGIC --
);
end;
architecture rtl of xil_Reconfigurator is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
attribute signal_ENCODING : STRING;
type T_STATE is (
ST_IDLE,
ST_READ_BEGIN, ST_READ_WAIT,
ST_WRITE_BEGIN, ST_WRITE_WAIT,
ST_DONE
);
-- DualConfiguration - Statemachine
signal State : T_STATE := ST_IDLE;
signal NextState : T_STATE;
attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", "speed1");
signal DataBuffer_en : STD_LOGIC;
signal DataBuffer_d : T_XIL_DRP_DATA := (others => '0');
signal ROM_Entry : T_XIL_DRP_CONFIG;
signal ROM_LastConfigWord : STD_LOGIC;
constant CONFIGINDEX_BITS : POSITIVE := log2ceilnz(CONFIG_ROM'length);
signal ConfigIndex_rst : STD_LOGIC;
signal ConfigIndex_en : STD_LOGIC;
signal ConfigIndex_us : UNSIGNED(CONFIGINDEX_BITS - 1 downto 0);
attribute KEEP OF ROM_LastConfigWord : signal IS DEBUG;
begin
-- configuration ROM
blkCONFIG_ROM : block
signal SetIndex : inTEGER range 0 to CONFIG_ROM'high;
signal RowIndex : T_XIL_DRP_CONFIG_INDEX;
attribute KEEP OF SetIndex : signal IS DEBUG;
attribute KEEP OF RowIndex : signal IS DEBUG;
begin
SetIndex <= to_index(ConfigSelect, CONFIG_ROM'high);
RowIndex <= to_index(ConfigIndex_us, T_XIL_DRP_CONFIG_INDEX'high);
ROM_Entry <= CONFIG_ROM(SetIndex).Configs(RowIndex);
ROM_LastConfigWord <= to_sl(RowIndex = CONFIG_ROM(SetIndex).LastIndex);
end block;
-- configuration index counter
process(Clock)
begin
if rising_edge(Clock) then
if ((Reset or ConfigIndex_rst) = '1') then
ConfigIndex_us <= (others => '0');
else
if (ConfigIndex_en = '1') then
ConfigIndex_us <= ConfigIndex_us + 1;
end if;
end if;
end if;
end process;
-- data buffer for DRP configuration words
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
DataBuffer_d <= (others => '0');
else
if (DataBuffer_en = '1') then
DataBuffer_d <= ((DRP_DataIn and not ROM_Entry.Mask) or
(ROM_Entry.Data and ROM_Entry.Mask));
end if;
end if;
end if;
end process;
-- assign DRP signals
DRP_Address <= ROM_Entry.Address;
DRP_DataOut <= DataBuffer_d;
-- DRP read-modify-write statemachine
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
State <= ST_IDLE;
else
State <= NextState;
end if;
end if;
end process;
process(State, Reconfig, ROM_LastConfigWord, DRP_Ack )
begin
NextState <= State;
ReconfigDone <= '0';
-- Dynamic Reconfiguration Port
DRP_en <= '0';
DRP_we <= '0';
-- internal modules
ConfigIndex_rst <= '0';
ConfigIndex_en <= '0';
DataBuffer_en <= '0';
case State is
when ST_IDLE =>
if (Reconfig = '1') then
ConfigIndex_rst <= '1';
NextState <= ST_READ_BEGIN;
end if;
when ST_READ_BEGIN =>
DRP_en <= '1';
DRP_we <= '0';
NextState <= ST_READ_WAIT;
when ST_READ_WAIT =>
if (DRP_Ack = '1') then
DataBuffer_en <= '1';
NextState <= ST_WRITE_BEGIN;
end if;
when ST_WRITE_BEGIN =>
DRP_en <= '1';
DRP_we <= '1';
NextState <= ST_WRITE_WAIT;
when ST_WRITE_WAIT =>
if (DRP_Ack = '1') then
if (ROM_LastConfigWord = '1') then
NextState <= ST_DONE;
ELSE
ConfigIndex_en <= '1';
NextState <= ST_READ_BEGIN;
end if;
end if;
when ST_DONE =>
ReconfigDone <= '1';
NextState <= ST_IDLE;
end case;
end process;
end;
|
-- Library & Use Statements
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- Entity Declaration
ENTITY start_bit_detect IS
PORT(
clk : IN std_logic;
baud_tick : IN std_logic;
reset_n : IN std_logic;
edge : IN std_logic;
start_bit : OUT std_logic
);
END start_bit_detect;
-- Architecture Declaration
ARCHITECTURE rtl OF start_bit_detect IS
CONSTANT count_from : unsigned(3 downto 0) := to_unsigned(8,4);
CONSTANT count_to : unsigned(3 downto 0) := to_unsigned(0,4);
SIGNAL count, next_count : unsigned(3 downto 0);
-- Begin Architecture
BEGIN
--------------------------------------------------
-- PROCESS FOR COMBINATORIAL LOGIC
--------------------------------------------------
comb_logic: PROCESS(count, edge, baud_tick)
BEGIN
IF (count = count_to AND edge = '1') THEN
next_count <= count_from;
-- decrement
ELSIF (count > count_to AND baud_tick = '1') THEN
next_count <= count - 1 ;
-- freezes
ELSE
next_count <= count;
END IF;
END PROCESS comb_logic;
comb_logic_out: PROCESS(count, edge)
BEGIN
if(count = count_to AND edge = '1') THEN
start_bit <= '1';
ELSE
start_bit <= '0';
END IF;
END PROCESS comb_logic_out;
-------------------------------------------
-- Process for registers
-------------------------------------------
flip_flops : PROCESS(clk, reset_n)
BEGIN
IF reset_n = '0' THEN
count <= count_to; -- convert integer value 0 to unsigned with 4bits
ELSIF rising_edge(clk) THEN
count <= next_count;
END IF;
END PROCESS flip_flops;
END rtl;
|
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_slv_read
-- Architectures: lipif_slv_read_rtl
-- Description:
--
-- Dependencies:
-- lipif_mst_pipeliner
--
-- Notes:
-- When Sl_rdBTerm is asserted at the end of a primary transfer,
-- M_rdBurst must be set according to the secondary transfer in
-- the following cycle.
-- M_rdBurst may not be set until after AddrAck!!!
--
-- Revision:
-- 11.4.2006 - File Created
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library lisipif_master_v1_00_c;
use lisipif_master_v1_00_c.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lipif_mst_read is
generic (
C_NUM_WIDTH : integer := 5;
C_EN_SRL16 : boolean := true;
C_EN_FAST_ABORT : boolean := false
);
port (
clk : in std_logic;
reset : in std_logic;
-- Control Signals to/from Arbiter
xfer_rdy_o : out std_logic;
xfer_init_i : in std_logic;
xfer_ack_i : in std_logic;
xfer_rearb_i : in std_logic;
xfer_retry_o : out std_logic;
xfer_abort_o : out std_logic;
-- LIS-IPIC Transfer Signals
M_rdNum_i : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
M_rdRearb_o : out std_logic;
M_rdAbort_i : in std_logic;
M_rdError_o : out std_logic;
M_rdData_o : out std_logic_vector(63 downto 0);
M_rdAck_o : out std_logic;
M_rdComp_o : out std_logic;
-- PLB Signals
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
M_rdBurst : out std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63)
);
end lipif_mst_read;
architecture lipif_mst_read_rtl of lipif_mst_read is
-- Pipebuf primary control signals
signal prim_valid : std_logic;
signal prim_last : std_logic;
signal prim_ack : std_logic;
signal prim_ack_p : std_logic;
signal prim_comp : std_logic;
-- Transfer termination requests from IP/PLB
signal mst_term : std_logic;
signal mst_term_r : std_logic; -- Track until transfer complete
signal plb_term : std_logic;
-- Burst will continue through next cycle
signal prim_burst_nxt : std_logic;
signal pipe_burst_nxt : std_logic;
begin
-- Generate PLB read burst signal (M_rdBurst)
-- TIMING(18%) M_rdBurst is a register, so no problem
-- TODO: When C_EN_FAST_ABORT, M_rdBurst must respond with M_rdAbort
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
M_rdBurst <= '0';
else
-- Burst must display pipelined value in response to PLB terminate
if(PLB_MRdBTerm='1') then
M_rdBurst <= pipe_burst_nxt;
-- Burst must go low in response to IP abort
elsif(M_rdAbort_i='1') then
M_rdBurst <= '0';
-- Update burst signal at start of transfer, or with each data ack
-- TODO: M_rdBurst may not be asserted until xfer_ack_i
elsif(xfer_init_i='1' or PLB_MRdDAck='1') then
M_rdBurst <= prim_burst_nxt;
end if;
end if;
end if;
end process;
-- process(plb_term, mst_term_r, prim_last, pipe_burst, pipe_valid) begin
-- if(plb_term='1') then
-- M_rdBurst <= pipe_burst and pipe_valid;
-- else
-- M_rdBurst <= not mst_term_r and not prim_last;
-- end if;
-- end process;
-- Assert prim_comp to complete transfer:
-- * with last d-ack of transfer
-- * with next d-ack when plb_term or mst_term are asserted
-- * with mst_term when primary transfer not acknowledged
process(PLB_MRdDAck, prim_last, plb_term, mst_term, prim_ack) begin
if(PLB_MRdDAck='1') then
prim_comp <= prim_last or plb_term or mst_term;
else
prim_comp <= mst_term and not prim_ack;
end if;
end process;
-- Latch IP termination request until completion of transfer
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
mst_term_r <= '0';
else
if(prim_comp='1') then
mst_term_r <= '0';
elsif(M_rdAbort_i='1') then
mst_term_r <= '1';
end if;
end if;
end if;
end process;
-- When not C_EN_FAST_ABORT, assert terminate signal immediately only if rearbitrating
NEN_FAST_ABORT: if(not C_EN_FAST_ABORT) generate
mst_term <= M_rdAbort_i when(xfer_rearb_i='1' and prim_ack_p='0') else mst_term_r;
end generate NEN_FAST_ABORT;
-- When C_EN_FAST_ABORT, always pass M_rdAbort_i through
EN_FAST_ABORT: if(C_EN_FAST_ABORT) generate
mst_term <= '1' when(mst_term_r='1') else M_rdAbort_i;
end generate EN_FAST_ABORT;
-- Wait until one cycle after prim_ack goes low before rearbitrating
M_rdRearb_o <= xfer_rearb_i and not prim_ack_p;
-- Control signals to arbiter (Affect arbiter only!)
xfer_retry_o <= xfer_rearb_i and not prim_ack_p;
xfer_abort_o <= mst_term and prim_valid and not prim_ack;
-- Various registers
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
M_rdData_o <= (others=>'0');
M_rdAck_o <= '0';
M_rdComp_o <= '0';
M_rdError_o <= '0';
plb_term <= '0';
else
M_rdAck_o <= PLB_MRdDAck;
if(PLB_MRdDAck='1') then
M_rdData_o <= PLB_MRdDBus;
end if;
-- Generate delayed prim_ack for rearbitration signal generation
prim_ack_p <= prim_ack;
-- IPIC's complete signal is pipeliner's complete signal delayed
M_rdComp_o <= prim_comp;
-- Error occurred if transfer completes before all data was transferred,
-- or if transfer was never acknowledged
M_rdError_o <= prim_comp and (not prim_last or not prim_ack);
-- Keep track of previous termination request by slave
-- Since PLB_MRdBTerm may already be asserted for a following transfer
-- with the last data item, give priority to asserting plb_term
if(PLB_MRdBTerm='1') then
plb_term <= '1';
elsif(prim_comp='1') then
plb_term <= '0';
end if;
end if;
end if;
end process;
-- Instantiate the request pipeliner
pipeliner_0: entity lisipif_master_v1_00_c.lipif_mst_pipeliner
generic map (
C_NUM_WIDTH => C_NUM_WIDTH
)
port map (
clk => clk,
reset => reset,
xfer_num_i => M_rdNum_i,
xfer_adv_i => PLB_MRdDAck,
xfer_nxt_i => prim_comp,
xfer_req_i => xfer_init_i,
xfer_ack_i => xfer_ack_i,
xfer_rdy_o => xfer_rdy_o,
prim_valid_o => prim_valid,
prim_last_o => prim_last,
prim_ack_o => prim_ack,
prim_nburst_o => prim_burst_nxt,
pipe_nburst_o => pipe_burst_nxt
);
end lipif_mst_read_rtl;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:14:52 11/09/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/OZ-3/EX_TB.vhd
-- Project Name: OZ-3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: EX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY EX_TB IS
END EX_TB;
ARCHITECTURE behavior OF EX_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT EX
PORT(
clock : IN std_logic;
reset : IN std_logic;
ALUA_from_ID : IN std_logic_vector(31 downto 0);
ALUB_from_ID : IN std_logic_vector(31 downto 0);
cntl_from_ID : IN std_logic_vector(11 downto 0);
p_flag_from_MEM : IN std_logic;
ALUR_to_MEM : OUT std_logic_vector(31 downto 0);
dest_reg_addr_to_ID : OUT std_logic_vector(4 downto 0);
cond_bit_to_IF : OUT std_logic
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal ALUA_from_ID : std_logic_vector(31 downto 0) := (others => '0');
signal ALUB_from_ID : std_logic_vector(31 downto 0) := (others => '0');
signal cntl_from_ID : std_logic_vector(11 downto 0) := (others => '0');
signal p_flag_from_MEM : std_logic := '0';
--Outputs
signal ALUR_to_MEM : std_logic_vector(31 downto 0);
signal dest_reg_addr_to_ID : std_logic_vector(4 downto 0);
signal cond_bit_to_IF : std_logic;
-- Clock period definitions
constant clock_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: EX PORT MAP (
clock => clock,
reset => reset,
ALUA_from_ID => ALUA_from_ID,
ALUB_from_ID => ALUB_from_ID,
cntl_from_ID => cntl_from_ID,
p_flag_from_MEM => p_flag_from_MEM,
ALUR_to_MEM => ALUR_to_MEM,
dest_reg_addr_to_ID => dest_reg_addr_to_ID,
cond_bit_to_IF => cond_bit_to_IF
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for 40 ns;
reset <= '0';
ALUA_from_ID <= x"00000001";
ALUB_from_ID <= x"00000001";
cntl_from_ID <= b"00001_000_0000";
p_flag_from_MEM <= '0';
wait for 20 ns;
reset <= '0';
ALUA_from_ID <= x"00000002";
ALUB_from_ID <= x"00000001";
cntl_from_ID <= b"00001_011_0000";
p_flag_from_MEM <= '0';
wait;
end process;
END;
|
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