content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.numeric_bit.all;
entity xnor23 is
port (
a_i : in bit_vector (22 downto 0);
b_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity xnor23;
architecture rtl of xnor23 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity xnor23 is
port (
a_i : in bit_vector (22 downto 0);
b_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity xnor23;
architecture rtl of xnor23 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity xnor23 is
port (
a_i : in bit_vector (22 downto 0);
b_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity xnor23;
architecture rtl of xnor23 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity xnor23 is
port (
a_i : in bit_vector (22 downto 0);
b_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity xnor23;
architecture rtl of xnor23 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--!
--! Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--! @file rf_blocks_pkg.vhd
--! @brief Package containing all basic elements in BoostDSP
--! @author Scott Teal (Scott@Teals.org)
--! @date 2013-11-04
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except ... |
library ieee;
use ieee.std_logic_1164.all;
entity repro is
end;
architecture behav of repro is
type t_axilite_write_address_channel is record
--DUT inputs
awaddr : std_logic_vector;
awvalid : std_logic;
awprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged acces... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:55:36 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- file_pixel_gen.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity file_pixel_gen is
generic (
WIDTH : integer;
HEIGHT : integer
);
port (
... |
library verilog;
use verilog.vl_types.all;
entity mist1032sa_uart_transmitter is
generic(
BAUDRATE_FIXED : vl_logic := Hi1;
BAUDRATE_COUNTER: vl_logic_vector(0 to 19) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1, Hi1, Hi0, Hi1, Hi1, Hi0, Hi0)
);
port(
iCL... |
entity bug is
end;
use work.pkg.all;
architecture behav of bug is
begin
p: process
variable rec : rec_t;
begin
wait;
end process;
end behav;
|
entity bug is
end;
use work.pkg.all;
architecture behav of bug is
begin
p: process
variable rec : rec_t;
begin
wait;
end process;
end behav;
|
entity bug is
end;
use work.pkg.all;
architecture behav of bug is
begin
p: process
variable rec : rec_t;
begin
wait;
end process;
end behav;
|
----------------------------------------------------------------------
-- brdLexSwx (for Trenz TEM0001 Board)
----------------------------------------------------------------------
-- (c) 2019 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Gabbe
--
-- Create Date: 09:40:15 09/17/2014
-- Design Name:
-- Module Name: comp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies: ... |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: RX core
-- # Outputs are synchronous to wb_clk_i
-- ####################################
-- # Adress Map:
-- # Adr[3:0]:
-- # 0x0 : RX Enable Mask
library IEEE;
use ieee.std_logic_1... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_214 is
port (
result : out std_logic_vector(7 downto 0);
in_a : in std_logic_vector(7 downto 0);
in_b : in std_logic_vector(7 downto 0)
);
end add_214;
architecture augh of add_214 is
signal carry_inA : std_logi... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_214 is
port (
result : out std_logic_vector(7 downto 0);
in_a : in std_logic_vector(7 downto 0);
in_b : in std_logic_vector(7 downto 0)
);
end add_214;
architecture augh of add_214 is
signal carry_inA : std_logi... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity shift2 is
end entity;
architecture test of shift2 is
begin
assert bit_vector'("11100") ror -8 = "00111"
report "ror -8 is broken" severity error;
assert bit_vector'("11100") ror -7 = "10011"
report "ror -7 is broken" severity error;
assert bit_vector'("11100"... |
entity shift2 is
end entity;
architecture test of shift2 is
begin
assert bit_vector'("11100") ror -8 = "00111"
report "ror -8 is broken" severity error;
assert bit_vector'("11100") ror -7 = "10011"
report "ror -7 is broken" severity error;
assert bit_vector'("11100"... |
entity shift2 is
end entity;
architecture test of shift2 is
begin
assert bit_vector'("11100") ror -8 = "00111"
report "ror -8 is broken" severity error;
assert bit_vector'("11100") ror -7 = "10011"
report "ror -7 is broken" severity error;
assert bit_vector'("11100"... |
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
---------------------------... |
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
---------------------------... |
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
---------------------------... |
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
---------------------------... |
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
---------------------------... |
library ieee;
use ieee.std_logic_1164.all;
library virtual_button_lib;
use virtual_button_lib.ws2812_data.all;
package ws2812_constant_colours is
constant ws2812_clear : ws2812_t := lighten_ws2812(ws2812_t'(000, 000, 000), 0.05);
constant ws2812_green : ws2812_t := lighten_ws2812(ws2812_t'(000, 128, 000), 0.05)... |
architecture RTL of FIFO is
constant c_width : integer := 16;
constant C_DEPTH : integer := 512;
constant C_word : integer := 1024;
begin
end architecture RTL;
|
-----------------------------------------------------------------------------
-- LEON3 Xilinx KC705 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) ... |
Library ieee;
Use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
ENTITY Execution IS
port(
Clk,Rst,enable : in std_logic;
OpCode : in std_logic_vector(4 downto 0);
R1_Reg1,R2_Reg1,ROut_Alu1,ROut_Mem1: in std_logic_vector(2 downto 0);
R1_dec: in std_logic_vector(15 downto 0);
R2_dec: in std_log... |
set vhdlList {
|
set vhdlList {
|
------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;
use work.picpkg.all;
entity memory_instruction is
Generic (
CONTENTS : string := "scripts/instructions.mif"
);
Port ( clk : in STD_LOGIC;
a1 : in STD_LOGIC_VECTOR (12 downto 0);
d1 :... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
entity delay2 is
end entity;
architecture test of delay2 is
signal clk : bit;
begin
clock_p: process is
begin
if now < 1 us then
clk <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
else
wait;
end if;
end process;
check_p: process is
... |
entity delay2 is
end entity;
architecture test of delay2 is
signal clk : bit;
begin
clock_p: process is
begin
if now < 1 us then
clk <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
else
wait;
end if;
end process;
check_p: process is
... |
entity delay2 is
end entity;
architecture test of delay2 is
signal clk : bit;
begin
clock_p: process is
begin
if now < 1 us then
clk <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
else
wait;
end if;
end process;
check_p: process is
... |
entity delay2 is
end entity;
architecture test of delay2 is
signal clk : bit;
begin
clock_p: process is
begin
if now < 1 us then
clk <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
else
wait;
end if;
end process;
check_p: process is
... |
entity delay2 is
end entity;
architecture test of delay2 is
signal clk : bit;
begin
clock_p: process is
begin
if now < 1 us then
clk <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
else
wait;
end if;
end process;
check_p: process is
... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FSM_STFILT is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
SF_reg_move_target: in vl_logic;
SF_reg_apbwr : in vl_lo... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FSM_STFILT is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
SF_reg_move_target: in vl_logic;
SF_reg_apbwr : in vl_lo... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FSM_STFILT is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
SF_reg_move_target: in vl_logic;
SF_reg_apbwr : in vl_lo... |
-------------------------------------------------------------------------------
-- Title : Vivadi DDS sin lut for SIRIUS 130M
-- Project :
-------------------------------------------------------------------------------
-- File : dds_sin_lut.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- C... |
-------------------------------------------------------------------------------
-- $Id: opb_bam.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_bam.vhd
-------------------------------------------------------------------------------
--... |
-------------------------------------------------------------------------------
-- $Id: opb_bam.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_bam.vhd
-------------------------------------------------------------------------------
--... |
architecture RTL of FIFO is
procedure average_samples;
begin
Average_samples;
PROC1 : process () is
begin
AVERAGE_SAMPLES;
AVERAGE_SaMPLES;
aVeRAGE_SaMPLES;
end process;
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file ... |
-- cb20_width_adapter.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 34;
IN_PKT_ADDR_L : integer := 18;
IN_PKT_DATA_H ... |
-------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <paulino@dte.us.es>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
Port (
CLK : in std_logic; -- Pixel clock 32.5MHz
RESET : in std_logic; -- Reset (active low)
CACHE_SWAP : out std_logic; --... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity mwfc is
Generic (
precision : integer := 13;
bcdprecision : integer := 16 );
Port (
rawfrq : out unsigned(precision - 1 downto 0); -- May need an extra b... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_modulator/hdl_modulator_hdl_modulator_pkg.vhd
-- Created: 2018-02-27 13:25:15
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
LIBRARY... |
-- CHECKED AND MODIFIED BY PRASANJEET
-------------------------------------------
--UPDATED ON: 7/9/09, 7/13/10
-- TASK : Complete the four TODO sections
-------------------------------------------
-------------------------------------------------------------------------------
--
-- Design : Load/Store Issue C... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------- ------------
-- filename: ro_filt_3x3.vhd
-- author: Tony Nelson
-- date: 12/21/99
--
-- detail: 3x3 Rank Order Filter. Generic order sets filter order.
-- order: integer:= 5 is a Median Filter.
--
-- auditoria
----------------------------------- ----------... |
--------------------------------------------------------------------------------
-- Company: UMD ECE
-- Engineers: Benjamin Doiron, Daniel Noyes
--
-- Create Date: 12:35:25 03/26/2014
-- Design Name: Scan to Hex Testbench
-- Module Name: scan_to_hex_tb
-- Project Name: Risc Machine Project 1
-- Target Devic... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity adder_tester_tb is
file TEST_FILE : text open READ_MODE is "testing_files/test_sum_float_23_6.txt";
constant TOTAL_BITS : integer := 23;
constant EXP_BITS : integer := 6;
constant PIPELINE_STEPS : integer := 6;
end ent... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Reconfiguration engine ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Reconfiguration engine ... |
-- Library & Use Statements
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- Entity Declaration
ENTITY start_bit_detect IS
PORT(
clk : IN std_logic;
baud_tick : IN std_logic;
reset_n : IN std_logic;
edge : IN std_logic;
start_bit : OUT std_logic
);
END start_bit_detect;... |
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_slv_read
-- Architectures: lipif_slv_read_rtl
-- Description:
--
-- Dependencies:
-- lipif_mst_pi... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:14:52 11/09/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/OZ-3/EX_TB.vhd
-- Project Name: OZ-3
-- Target Device:
-- Tool versions:
-- De... |
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