content stringlengths 1 1.04M ⌀ |
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-- vga_control.vhd
-- given pixel clock, calculate sync signals and location index
-- input: pixel clock
-- output: sync signals, pixel locations(row, col)
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.all;
use IEEE.std_logic_UNSIGNED.all;
entity vga_control is
generic (
-- constants
h_pixels: integer := 640;
h_fp : integer := 16;
h_pulse : integer := 96;
h_bp : integer := 48;
v_pixels: integer := 480;
v_fp : integer := 11;
v_pulse : integer := 2;
v_bp : integer := 33
);
port (
pixel_clock: in std_logic;
h_sync, v_sync: out std_logic;
n_blank, n_sync: out std_logic;
row, col: out integer
);
end vga_control;
architecture arch of vga_control is
constant h_period: integer := h_pulse + h_bp + h_pixels + h_fp;
constant v_period: integer := v_pulse + v_bp + v_pixels + v_fp;
signal power_on: std_logic := '0';
begin
n_blank <= '1';
n_sync <= '0';
process(pixel_clock)
variable h_count: integer range 0 to h_period - 1 := 0;
variable v_count: integer range 0 to v_period - 1 := 0;
begin
if(power_on = '0') then
h_count := 0;
v_count := 0;
h_sync <= '1';
v_sync <= '1';
col <= 0;
row <= 0;
power_on <= '1';
elsif(pixel_clock'event and pixel_clock = '1') then
-- counters
if(h_count < h_period - 1) then
h_count := h_count + 1;
else
h_count := 0;
if(v_count < v_period - 1) then
v_count := v_count + 1;
else
v_count := 0;
end if;
end if;
-- horizontal sync signal
if(h_count < h_pixels + h_fp or h_count > h_pixels + h_fp + h_pulse) then
h_sync <= '1';
else
h_sync <= '0';
end if;
-- vertical sync signal
if(v_count < v_pixels + v_fp or v_count > v_pixels + v_fp + v_pulse) then
v_sync <= '1';
else
v_sync <= '0';
end if;
-- set pixel coordinates
if(h_count < h_pixels) then
col <= h_count;
end if;
if(v_count < v_pixels) then
row <= v_count;
end if;
end if;
end process;
end arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity bcd_1_adder is
port (
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
C_IN: in STD_LOGIC;
SUM: out STD_LOGIC_VECTOR (3 downto 0);
C_OUT: out STD_LOGIC
);
end bcd_1_adder;
--algorithm
-- If A + B <= 9 then -- assume both A and B are valid BCD numbers
-- RESULT = A + B ;
-- CARRY = 0 ;
-- else
-- RESULT = A + B + 6 ;
-- CARRY = 1;
-- end if ;
architecture bcd_1_adder_arch of bcd_1_adder is
begin
--BCD adder logic
process (A,B,C_IN)
variable temp : std_logic_vector(3 downto 0);
variable overflow : boolean;
begin
temp := A + B + C_IN;
overflow := A(0) and B(0) and A(1) and B(1) and A(2) and B(2) and A(3) and B(3) and C_IN;
if (temp <= 9) then
SUM <= temp + overflow*6;
C_OUT <= overflow;
else
SUM <= (temp + 6);
C_OUT <= '1';
end if;
-- if (A >0 and B >0 and A + B < 9) then
-- SUM <= temp+6;
-- C_OUT <= '1';
-- else
-- if ( temp <= 9 ) then
-- SUM <= temp;
-- C_OUT <= '0';
-- else
-- SUM <= (temp + 6);
-- C_OUT <= '1';
-- end if;
-- end if;
-- if ( ('0'&A) + ('0'&B) + C_IN <= 9 ) then
-- SUM <= (A + B + C_IN);
-- C_OUT <= '0';
-- else
-- SUM <= (A + B + C_IN + 6);
-- C_OUT <= '1';
-- end if;
end process;
end bcd_1_adder_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
entity toplevel is
port(
clk : in std_logic;
rst : in std_logic;
ps2Data : in std_logic;
ps2Clk : in std_logic;
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_db : out std_logic_vector(7 downto 0)
);
end entity toplevel;
architecture RTL of toplevel is
signal rxData : std_logic_vector(7 downto 0);
signal asciiData : std_logic_vector(7 downto 0);
signal asciiDataBig : std_logic_vector(7 downto 0);
signal dataReady : std_logic;
signal dataReadydly : std_logic;
signal dataFetched : std_logic;
signal released : std_logic;
signal line_buffer : std_logic_vector(255 downto 0);
signal pos : natural;
signal shifta : std_logic;
signal shiftb : std_logic;
begin
inst_ps2Recv : entity work.ps2Receiver
port map(
clk => clk,
rst => rst,
rxData => rxData,
dataReady => dataReady,
dataFetched => dataFetched,
ps2Data => ps2Data,
ps2Clk => ps2Clk);
dataFetched <= '1';
inst_lcd : entity work.lcd16x2_ctrl
port map(
clk => clk,
rst => rst,
lcd_e => lcd_e,
lcd_rs => lcd_rs,
lcd_rw => lcd_rw,
lcd_db => lcd_db(7 downto 4),
line1_buffer => line_buffer(255 downto 128),
line2_buffer => line_buffer(127 downto 0));
lcd_db(3 downto 0) <= (others => '1');
pos_counter: process(clk, rst)
begin
if rst = '1' then
pos <= 31;
released <= '0';
line_buffer <= X"2020202020202020202020202020202020202020202020202020202020202020";
shifta <= '0';
shiftb <= '0';
elsif rising_edge(clk) then
dataReadydly <= dataReady;
if dataReady = '1' and dataReadydly = '0' then
if rxData = X"F0" then
released <= '1';
elsif released = '1' then
if rxData = X"12" then
shifta <= '0';
elsif rxData = X"59" then
shiftb <= '0';
end if;
released <= '0';
else
if rxData = X"12" then
shifta <= '1';
elsif rxData = X"59" then
shiftb <= '1';
else
line_buffer((pos*8)+7 downto pos*8) <= asciiDataBig;
if pos = 0 then
pos <= 32;
else
pos <= pos - 1;
end if;
end if;
end if;
end if;
end if;
end process pos_counter;
asciiData <=
X"61" when rxData = X"1C" else --a
X"62" when rxData = X"32" else
X"63" when rxData = X"21" else
X"64" when rxData = X"23" else
X"65" when rxData = X"24" else
X"66" when rxData = X"2B" else
X"67" when rxData = X"34" else
X"68" when rxData = X"33" else
X"69" when rxData = X"43" else
X"6A" when rxData = X"3B" else
X"6B" when rxData = X"42" else
X"6C" when rxData = X"4B" else
X"6D" when rxData = X"3A" else
X"6E" when rxData = X"31" else
X"6F" when rxData = X"44" else
X"70" when rxData = X"4D" else
X"71" when rxData = X"15" else
X"72" when rxData = X"2D" else
X"73" when rxData = X"1B" else
X"74" when rxData = X"2C" else
X"75" when rxData = X"3C" else
X"76" when rxData = X"2A" else
X"77" when rxData = X"1D" else
X"78" when rxData = X"22" else
X"79" when rxData = X"35" else
X"7A" when rxData = X"1A" else
X"30" when rxData = X"45" else --0
X"31" when rxData = X"16" else
X"32" when rxData = X"1E" else
X"33" when rxData = X"26" else
X"34" when rxData = X"25" else
X"35" when rxData = X"2E" else
X"36" when rxData = X"36" else
X"37" when rxData = X"3D" else
X"38" when rxData = X"3E" else
X"39" when rxData = X"46" else
X"20" when rxData = X"29" else
X"FF";
asciiDataBig <= asciiData - X"20" when shifta = '1' or shiftb = '1' else
asciiData;
end architecture RTL;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00210
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00210(ARCH00210)
-- ENT00210_Test_Bench(ARCH00210_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00210 is
generic (G : integer) ;
port (
s_st_rec3 : inout st_rec3
) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00210 ;
--
--
architecture ARCH00210 of ENT00210 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_rec3 : inout st_rec3
; variable counter : inout integer
; variable correct : inout boolean
; variable savtime : inout time
; signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=>
s_st_rec3.f1 <= transport
c_st_rec3_2.f1 ;
s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns ;
wait until s_st_rec3.f2 =
c_st_rec3_2.f2 ;
Test_Report (
"ENT00210",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3.f2 =
c_st_rec3_2.f2 )) ;
--
when 1
=>
s_st_rec3.f1 <= transport
c_st_rec3_1.f1 ;
s_st_rec3.f3 <= transport
c_st_rec3_2.f3 after 10 ns ;
wait until s_st_rec3.f3 =
c_st_rec3_2.f3 ;
Test_Report (
"ENT00210",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3.f3 =
c_st_rec3_2.f3 )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
Proc1 (
s_st_rec3
, counter
, correct
, savtime
, chk_st_rec3
) ;
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_rec3 = 1 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00210 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00210_Test_Bench is
end ENT00210_Test_Bench ;
--
--
architecture ARCH00210_Test_Bench of ENT00210_Test_Bench is
begin
L1:
block
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
component UUT
generic (G : integer) ;
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00210 ( ARCH00210 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00210_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2566.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s04b02x00p15n01i02566ent_a IS
GENERIC ( gen_prm : INTEGER );
END c07s04b02x00p15n01i02566ent_a;
ARCHITECTURE c07s04b02x00p15n01i02566arch_a OF c07s04b02x00p15n01i02566ent_a IS
SIGNAL s : BIT;
ATTRIBUTE attr1 : INTEGER;
ATTRIBUTE attr1 OF s : SIGNAL IS gen_prm;
--
-- Usage of user-defined attribute as a globally-static expression
--
CONSTANT c0 : INTEGER := s'attr1;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c0 = gen_prm )
report "***PASSED TEST: c07s04b02x00p15n01i02566"
severity NOTE;
assert ( c0 = gen_prm )
report "***FAILED TEST: c07s04b02x00p15n01i02566 - Constant initialization to user-attribute value failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s04b02x00p15n01i02566arch_a;
ENTITY c07s04b02x00p15n01i02566ent IS
END c07s04b02x00p15n01i02566ent;
ARCHITECTURE c07s04b02x00p15n01i02566arch OF c07s04b02x00p15n01i02566ent IS
COMPONENT c07s04b02x00p15n01i02566ent_a
GENERIC ( gen_prm : INTEGER );
END COMPONENT;
for cmp : c07s04b02x00p15n01i02566ent_a use entity work.c07s04b02x00p15n01i02566ent_a(c07s04b02x00p15n01i02566arch_a);
BEGIN
cmp : c07s04b02x00p15n01i02566ent_a generic map (123);
END c07s04b02x00p15n01i02566arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2566.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s04b02x00p15n01i02566ent_a IS
GENERIC ( gen_prm : INTEGER );
END c07s04b02x00p15n01i02566ent_a;
ARCHITECTURE c07s04b02x00p15n01i02566arch_a OF c07s04b02x00p15n01i02566ent_a IS
SIGNAL s : BIT;
ATTRIBUTE attr1 : INTEGER;
ATTRIBUTE attr1 OF s : SIGNAL IS gen_prm;
--
-- Usage of user-defined attribute as a globally-static expression
--
CONSTANT c0 : INTEGER := s'attr1;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c0 = gen_prm )
report "***PASSED TEST: c07s04b02x00p15n01i02566"
severity NOTE;
assert ( c0 = gen_prm )
report "***FAILED TEST: c07s04b02x00p15n01i02566 - Constant initialization to user-attribute value failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s04b02x00p15n01i02566arch_a;
ENTITY c07s04b02x00p15n01i02566ent IS
END c07s04b02x00p15n01i02566ent;
ARCHITECTURE c07s04b02x00p15n01i02566arch OF c07s04b02x00p15n01i02566ent IS
COMPONENT c07s04b02x00p15n01i02566ent_a
GENERIC ( gen_prm : INTEGER );
END COMPONENT;
for cmp : c07s04b02x00p15n01i02566ent_a use entity work.c07s04b02x00p15n01i02566ent_a(c07s04b02x00p15n01i02566arch_a);
BEGIN
cmp : c07s04b02x00p15n01i02566ent_a generic map (123);
END c07s04b02x00p15n01i02566arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2566.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s04b02x00p15n01i02566ent_a IS
GENERIC ( gen_prm : INTEGER );
END c07s04b02x00p15n01i02566ent_a;
ARCHITECTURE c07s04b02x00p15n01i02566arch_a OF c07s04b02x00p15n01i02566ent_a IS
SIGNAL s : BIT;
ATTRIBUTE attr1 : INTEGER;
ATTRIBUTE attr1 OF s : SIGNAL IS gen_prm;
--
-- Usage of user-defined attribute as a globally-static expression
--
CONSTANT c0 : INTEGER := s'attr1;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c0 = gen_prm )
report "***PASSED TEST: c07s04b02x00p15n01i02566"
severity NOTE;
assert ( c0 = gen_prm )
report "***FAILED TEST: c07s04b02x00p15n01i02566 - Constant initialization to user-attribute value failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s04b02x00p15n01i02566arch_a;
ENTITY c07s04b02x00p15n01i02566ent IS
END c07s04b02x00p15n01i02566ent;
ARCHITECTURE c07s04b02x00p15n01i02566arch OF c07s04b02x00p15n01i02566ent IS
COMPONENT c07s04b02x00p15n01i02566ent_a
GENERIC ( gen_prm : INTEGER );
END COMPONENT;
for cmp : c07s04b02x00p15n01i02566ent_a use entity work.c07s04b02x00p15n01i02566ent_a(c07s04b02x00p15n01i02566arch_a);
BEGIN
cmp : c07s04b02x00p15n01i02566ent_a generic map (123);
END c07s04b02x00p15n01i02566arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pos01 is
generic (g_en : boolean := True);
port (clk : std_logic;
rst : std_logic;
en : std_logic;
st : out std_logic_vector(1 downto 0));
end pos01;
architecture behav of pos01 is
type t_state is (IDLE, WAIT1, WAIT2, DONE);
signal s : t_state;
constant c1 : integer := t_state'pos(WAIT2);
constant c2 : integer := boolean'pos(g_en);
begin
process (clk) is
begin
if rising_edge(clk) then
if rst = '1' then
s <= IDLE;
else
case s is
when IDLE =>
if en = '1' then
s <= WAIT1;
end if;
when WAIT1 =>
if en = '1' then
s <= WAIT2;
end if;
when WAIT2 =>
if en = '1' then
s <= DONE;
end if;
when DONE =>
null;
end case;
end if;
end if;
end process;
st <= std_logic_vector(to_unsigned(t_state'pos(s), 2));
end behav;
|
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5744)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5744)
`protect data_block
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`protect end_protected
|
-- NEED RESULT: ARCH00686: Allocators with generic composite subtype indication passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00686
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.6 (2)
-- 7.3.6 (8)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00686)
-- ENT00686_Test_Bench(ARCH00686_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00686 of GENERIC_STANDARD_TYPES is
begin
process
variable correct : boolean := true ;
type a_bit_vector is access bit_vector ;
variable va_bit_vector_1, va_bit_vector_2 : a_bit_vector
:= new st_bit_vector ;
type a_string is access string ;
variable va_string_1, va_string_2 : a_string
:= new st_string ;
type a_t_rec1 is access t_rec1 ;
variable va_t_rec1_1, va_t_rec1_2 : a_t_rec1
:= new st_rec1 ;
type a_st_rec1 is access st_rec1 ;
variable va_st_rec1_1, va_st_rec1_2 : a_st_rec1
:= new st_rec1 ;
type a_t_rec2 is access t_rec2 ;
variable va_t_rec2_1, va_t_rec2_2 : a_t_rec2
:= new st_rec2 ;
type a_st_rec2 is access st_rec2 ;
variable va_st_rec2_1, va_st_rec2_2 : a_st_rec2
:= new st_rec2 ;
type a_t_rec3 is access t_rec3 ;
variable va_t_rec3_1, va_t_rec3_2 : a_t_rec3
:= new st_rec3 ;
type a_st_rec3 is access st_rec3 ;
variable va_st_rec3_1, va_st_rec3_2 : a_st_rec3
:= new st_rec3 ;
type a_t_arr1 is access t_arr1 ;
variable va_t_arr1_1, va_t_arr1_2 : a_t_arr1
:= new st_arr1 ;
type a_st_arr1 is access st_arr1 ;
variable va_st_arr1_1, va_st_arr1_2 : a_st_arr1
:= new st_arr1 ;
type a_t_arr2 is access t_arr2 ;
variable va_t_arr2_1, va_t_arr2_2 : a_t_arr2
:= new st_arr2 ;
type a_st_arr2 is access st_arr2 ;
variable va_st_arr2_1, va_st_arr2_2 : a_st_arr2
:= new st_arr2 ;
type a_t_arr3 is access t_arr3 ;
variable va_t_arr3_1, va_t_arr3_2 : a_t_arr3
:= new st_arr3 ;
type a_st_arr3 is access st_arr3 ;
variable va_st_arr3_1, va_st_arr3_2 : a_st_arr3
:= new st_arr3 ;
begin
correct := correct and
va_bit_vector_1.all = d_st_bit_vector ;
correct := correct and
va_string_1.all = d_st_string ;
correct := correct and
va_t_rec1_1.all = d_st_rec1 ;
correct := correct and
va_st_rec1_1.all = d_st_rec1 ;
correct := correct and
va_t_rec2_1.all = d_st_rec2 ;
correct := correct and
va_st_rec2_1.all = d_st_rec2 ;
correct := correct and
va_t_rec3_1.all = d_st_rec3 ;
correct := correct and
va_st_rec3_1.all = d_st_rec3 ;
correct := correct and
va_t_arr1_1.all = d_st_arr1 ;
correct := correct and
va_st_arr1_1.all = d_st_arr1 ;
correct := correct and
va_t_arr2_1.all = d_st_arr2 ;
correct := correct and
va_st_arr2_1.all = d_st_arr2 ;
correct := correct and
va_t_arr3_1.all = d_st_arr3 ;
correct := correct and
va_st_arr3_1.all = d_st_arr3 ;
test_report ( "ARCH00686" ,
"Allocators with generic composite subtype indication" ,
correct) ;
wait ;
end process ;
end ARCH00686 ;
--
entity ENT00686_Test_Bench is
end ENT00686_Test_Bench ;
--
architecture ARCH00686_Test_Bench of ENT00686_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00686 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00686_Test_Bench ;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity processor is
end entity processor;
-- code from book
architecture rtl of processor is
component latch is
generic ( width : positive );
port ( d : in std_ulogic_vector(0 to width - 1);
q : out std_ulogic_vector(0 to width - 1);
-- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component latch;
component ROM is
port ( d_out : out std_ulogic_vector; -- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component ROM;
subtype std_logic_word is std_logic_vector(0 to 31);
signal source1, source2, destination : std_logic_word;
-- . . .
begin
temp_register : component latch
generic map ( width => 32 )
port map ( d => std_ulogic_vector(destination),
std_logic_vector(q) => source1, -- . . . );
-- not in book
other_port => open );
-- end not in book
constant_ROM : component ROM
port map ( std_logic_word(d_out) => source2, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture rtl;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity processor is
end entity processor;
-- code from book
architecture rtl of processor is
component latch is
generic ( width : positive );
port ( d : in std_ulogic_vector(0 to width - 1);
q : out std_ulogic_vector(0 to width - 1);
-- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component latch;
component ROM is
port ( d_out : out std_ulogic_vector; -- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component ROM;
subtype std_logic_word is std_logic_vector(0 to 31);
signal source1, source2, destination : std_logic_word;
-- . . .
begin
temp_register : component latch
generic map ( width => 32 )
port map ( d => std_ulogic_vector(destination),
std_logic_vector(q) => source1, -- . . . );
-- not in book
other_port => open );
-- end not in book
constant_ROM : component ROM
port map ( std_logic_word(d_out) => source2, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture rtl;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity processor is
end entity processor;
-- code from book
architecture rtl of processor is
component latch is
generic ( width : positive );
port ( d : in std_ulogic_vector(0 to width - 1);
q : out std_ulogic_vector(0 to width - 1);
-- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component latch;
component ROM is
port ( d_out : out std_ulogic_vector; -- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component ROM;
subtype std_logic_word is std_logic_vector(0 to 31);
signal source1, source2, destination : std_logic_word;
-- . . .
begin
temp_register : component latch
generic map ( width => 32 )
port map ( d => std_ulogic_vector(destination),
std_logic_vector(q) => source1, -- . . . );
-- not in book
other_port => open );
-- end not in book
constant_ROM : component ROM
port map ( std_logic_word(d_out) => source2, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture rtl;
-- end code from book
|
-- file: spi_sram_ctrl.vhd
-- description: Microchip SPI SRAM and EEPROM chip controller
-- date: 03/2018
-- author: Sergio Johann Filho <sergio.filho@pucrs.br>
--
-- A memory controller compatible with the 23lc1024 and similar SRAM chips.
-- For the 23lc512 chip, only two address bytes should be transmitted, and
-- this controller needs some small changes. The controller assumes that
-- the chip is configured to burst (sequential) data mode by default (which
-- is not true for the 23x256 family of chips.
-- In short address mode (sddr_i = '1'), this controller is also compatible with
-- EEPRROMs, which operate in burst mode by default but use the 16 bit address
-- format. Warning: this controller doesn't use page writes, so EEPROMs may
-- wear out faster than normal. To avoid this, hook the write protection pin.
-- Traffic to / from SRAM / EEPROM is performed in 32 bit words (4 SPI 8 bit words)
-- or multiple (burst) of 32 bit words. For single word access, a half word or
-- byte can be individually accessed. In this case burst mode must be deselected.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity spi_sram_ctrl is
generic (
BURST_SIZE: integer := 4
);
port ( -- core interface
clk_i: in std_logic;
rst_i: in std_logic;
addr_i: in std_logic_vector(23 downto 0);
data_i: in std_logic_vector(31 downto 0);
data_o: out std_logic_vector(31 downto 0);
burst_i: in std_logic; -- data in burst mode
bmode_i: in std_logic; -- byte access
hmode_i: in std_logic; -- half word access
wr_i: in std_logic;
rd_i: in std_logic;
saddr_i: in std_logic; -- 16 bit short address select
wren_i: in std_logic; -- EEPROM write enable latch
data_ack_o: out std_logic; -- signals the last byte of a word
cpu_stall_o: out std_logic;
-- SPI interface
spi_cs_n_o: out std_logic;
spi_clk_o: out std_logic; -- spi bus sck
spi_mosi_o: out std_logic; -- spi bus mosi output
spi_miso_i: in std_logic -- spi bus miso input
);
end spi_sram_ctrl;
architecture spi_sram_ctrl_arch of spi_sram_ctrl is
type states is (start, cmd_wren, cmd_write, cmd_read, addr_phase, data_phase, ready);
signal state: states;
signal data_o_reg: std_logic_vector(31 downto 0);
signal cmd_counter: std_logic;
signal addr_counter: std_logic_vector(1 downto 0);
signal data_counter: std_logic_vector(2**BURST_SIZE downto 0);
signal data_in, data_out: std_logic_vector(7 downto 0);
signal wren, data_valid, bmode, hmode, cpu_stall: std_logic;
begin
spi_core: entity work.spi_master
generic map(
BYTE_SIZE => 8
)
port map( clk_i => clk_i,
rst_i => rst_i,
data_i => data_in,
data_o => data_out,
wren_i => wren,
data_valid_o => data_valid,
spi_clk_o => spi_clk_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i
);
data_o <= data_o_reg;
cpu_stall_o <= cpu_stall or wr_i or rd_i;
process(clk_i, rst_i, data_valid)
begin
if rst_i = '1' then
data_o_reg <= (others => '0');
cmd_counter <= '0';
addr_counter <= (others => '0');
data_counter <= (others => '0');
data_in <= (others => '0');
wren <= '0';
spi_cs_n_o <= '1';
data_ack_o <= '0';
cpu_stall <= '0';
bmode <= '0';
hmode <= '0';
elsif clk_i'event and clk_i = '1' then
case state is
when start =>
cmd_counter <= '0';
if (saddr_i = '0') then
addr_counter <= "00";
else
addr_counter <= "01";
end if;
data_o_reg <= (others => '0');
if (hmode_i = '1' and bmode_i = '0' and burst_i = '0') then
data_counter(1 downto 0) <= "10";
data_counter(2**BURST_SIZE downto 2) <= (others => '0');
bmode <= '0';
hmode <= '1';
elsif (hmode_i = '0' and bmode_i = '1' and burst_i = '0') then
data_counter(1 downto 0) <= "11";
data_counter(2**BURST_SIZE downto 2) <= (others => '0');
bmode <= '1';
hmode <= '0';
else
data_counter <= (others => '0');
bmode <= '0';
hmode <= '0';
end if;
wren <= '0';
spi_cs_n_o <= '0';
data_ack_o <= '0';
cpu_stall <= '1';
when cmd_wren =>
if (data_valid = '0') then
data_in <= x"06";
wren <= '1';
else
cmd_counter <= '1';
wren <= '0';
end if;
when cmd_write =>
if (data_valid = '0') then
data_in <= x"02";
wren <= '1';
else
cmd_counter <= '1';
wren <= '0';
end if;
when cmd_read =>
if (data_valid = '0') then
data_in <= x"03";
wren <= '1';
else
cmd_counter <= '1';
wren <= '0';
end if;
when addr_phase =>
if (data_valid = '0') then
case addr_counter is
when "00" => data_in <= addr_i(23 downto 16);
when "01" => data_in <= addr_i(15 downto 8);
when "10" => data_in <= addr_i(7 downto 0);
when others => null;
end case;
wren <= '1';
else
if (wren = '1') then
addr_counter <= addr_counter + 1;
end if;
wren <= '0';
end if;
when data_phase =>
if (data_valid = '0') then
case data_counter(1 downto 0) is
when "00" => data_in <= data_i(31 downto 24);
data_o_reg(31 downto 24) <= data_out;
data_ack_o <= '0';
when "01" => data_in <= data_i(23 downto 16);
data_o_reg(23 downto 16) <= data_out;
when "10" => data_in <= data_i(15 downto 8);
data_o_reg(15 downto 8) <= data_out;
when "11" => data_in <= data_i(7 downto 0);
if bmode = '1' then
data_o_reg <= data_out & data_out & data_out & data_out;
elsif hmode = '1' then
data_o_reg <= data_o_reg(15 downto 8) & data_out & data_o_reg(15 downto 8) & data_out;
else
data_o_reg(7 downto 0) <= data_out;
end if;
data_ack_o <= '1';
when others => null;
end case;
wren <= '1';
else
if (wren = '1') then
data_counter <= data_counter + 1;
end if;
wren <= '0';
end if;
when ready =>
spi_cs_n_o <= '1';
cpu_stall <= '0';
when others => null;
end case;
end if;
end process;
process(clk_i, rst_i, state, cmd_counter, addr_counter, data_counter, wr_i, rd_i)
begin
if rst_i = '1' then
state <= ready;
elsif clk_i'event and clk_i = '1' then
case state is
when start =>
if (wr_i = '1') then
if (wren_i = '1') then
state <= cmd_wren;
else
state <= cmd_write;
end if;
elsif (rd_i = '1') then
state <= cmd_read;
else
state <= start;
end if;
when cmd_wren =>
if (cmd_counter = '1') then
state <= ready;
else
state <= cmd_wren;
end if;
when cmd_write =>
if (cmd_counter = '1') then
state <= addr_phase;
else
state <= cmd_write;
end if;
when cmd_read =>
if (cmd_counter = '1') then
state <= addr_phase;
else
state <= cmd_read;
end if;
when addr_phase =>
if (addr_counter < 3) then
state <= addr_phase;
else
state <= data_phase;
end if;
when data_phase =>
if (burst_i = '1') then
if (data_counter < (4 * BURST_SIZE)) then
state <= data_phase;
else
state <= ready;
end if;
else
if (data_counter < 4) then
state <= data_phase;
else
state <= ready;
end if;
end if;
when ready =>
if (wr_i = '1' or rd_i = '1') then
state <= start;
else
state <= ready;
end if;
when others => null;
end case;
end if;
end process;
end spi_sram_ctrl_arch;
|
-- $Id: sys_conf_sim.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1812.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01812ent IS
END c07s01b00x00p08n01i01812ent;
ARCHITECTURE c07s01b00x00p08n01i01812arch OF c07s01b00x00p08n01i01812ent IS
type small_int is range 0 to 7;
signal s_int : small_int := 0;
BEGIN
TESTING: PROCESS
BEGIN
if (small_int > s_int) then
null;
end if;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01812 - Type name are not permitted as primaries."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01812arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1812.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01812ent IS
END c07s01b00x00p08n01i01812ent;
ARCHITECTURE c07s01b00x00p08n01i01812arch OF c07s01b00x00p08n01i01812ent IS
type small_int is range 0 to 7;
signal s_int : small_int := 0;
BEGIN
TESTING: PROCESS
BEGIN
if (small_int > s_int) then
null;
end if;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01812 - Type name are not permitted as primaries."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01812arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1812.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01812ent IS
END c07s01b00x00p08n01i01812ent;
ARCHITECTURE c07s01b00x00p08n01i01812arch OF c07s01b00x00p08n01i01812ent IS
type small_int is range 0 to 7;
signal s_int : small_int := 0;
BEGIN
TESTING: PROCESS
BEGIN
if (small_int > s_int) then
null;
end if;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01812 - Type name are not permitted as primaries."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01812arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc150.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p14n01i00150ent IS
END c04s03b02x02p14n01i00150ent;
ARCHITECTURE c04s03b02x02p14n01i00150arch OF c04s03b02x02p14n01i00150ent IS
FUNCTION FLOAT ( ival : in integer) return real is
VARIABLE v1 : real := 543.0;
begin
RETURN v1;
end FLOAT;
FUNCTION ROUND ( rval : in real) return integer is
VARIABLE v1 : integer := 543;
begin
RETURN v1;
end ROUND;
PROCEDURE test_bed
( in1 : in integer;
out1 : out real )
is
begin
out1 := FLOAT (in1);
end test_bed;
BEGIN
TESTING: PROCESS
VARIABLE var1 : real;
VARIABLE var2 : real := 543.2;
BEGIN
test_bed ( ROUND (var2), var1 );
assert NOT( var1 = 543.0 )
report "***PASSED TEST:c04s03b02x02p14n01i00150"
severity NOTE;
assert ( var1 = 543.0 )
report "***FAILED TEST:c04s03b02x02p14n01i00150 - The actual part of a named element association may be in the form of a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p14n01i00150arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc150.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p14n01i00150ent IS
END c04s03b02x02p14n01i00150ent;
ARCHITECTURE c04s03b02x02p14n01i00150arch OF c04s03b02x02p14n01i00150ent IS
FUNCTION FLOAT ( ival : in integer) return real is
VARIABLE v1 : real := 543.0;
begin
RETURN v1;
end FLOAT;
FUNCTION ROUND ( rval : in real) return integer is
VARIABLE v1 : integer := 543;
begin
RETURN v1;
end ROUND;
PROCEDURE test_bed
( in1 : in integer;
out1 : out real )
is
begin
out1 := FLOAT (in1);
end test_bed;
BEGIN
TESTING: PROCESS
VARIABLE var1 : real;
VARIABLE var2 : real := 543.2;
BEGIN
test_bed ( ROUND (var2), var1 );
assert NOT( var1 = 543.0 )
report "***PASSED TEST:c04s03b02x02p14n01i00150"
severity NOTE;
assert ( var1 = 543.0 )
report "***FAILED TEST:c04s03b02x02p14n01i00150 - The actual part of a named element association may be in the form of a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p14n01i00150arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc150.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p14n01i00150ent IS
END c04s03b02x02p14n01i00150ent;
ARCHITECTURE c04s03b02x02p14n01i00150arch OF c04s03b02x02p14n01i00150ent IS
FUNCTION FLOAT ( ival : in integer) return real is
VARIABLE v1 : real := 543.0;
begin
RETURN v1;
end FLOAT;
FUNCTION ROUND ( rval : in real) return integer is
VARIABLE v1 : integer := 543;
begin
RETURN v1;
end ROUND;
PROCEDURE test_bed
( in1 : in integer;
out1 : out real )
is
begin
out1 := FLOAT (in1);
end test_bed;
BEGIN
TESTING: PROCESS
VARIABLE var1 : real;
VARIABLE var2 : real := 543.2;
BEGIN
test_bed ( ROUND (var2), var1 );
assert NOT( var1 = 543.0 )
report "***PASSED TEST:c04s03b02x02p14n01i00150"
severity NOTE;
assert ( var1 = 543.0 )
report "***FAILED TEST:c04s03b02x02p14n01i00150 - The actual part of a named element association may be in the form of a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p14n01i00150arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2770.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s08b00x00p01n01i02770ent IS
END c13s08b00x00p01n01i02770ent;
ARCHITECTURE c13s08b00x00p01n01i02770arch OF c13s08b00x00p01n01i02770ent IS
--This is an
error.
--ERROR: COMMENTS MUST BE ON ONE LINE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s08b00x00p01n01i02770 - Comments must be on one line."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s08b00x00p01n01i02770arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2770.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s08b00x00p01n01i02770ent IS
END c13s08b00x00p01n01i02770ent;
ARCHITECTURE c13s08b00x00p01n01i02770arch OF c13s08b00x00p01n01i02770ent IS
--This is an
error.
--ERROR: COMMENTS MUST BE ON ONE LINE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s08b00x00p01n01i02770 - Comments must be on one line."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s08b00x00p01n01i02770arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2770.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s08b00x00p01n01i02770ent IS
END c13s08b00x00p01n01i02770ent;
ARCHITECTURE c13s08b00x00p01n01i02770arch OF c13s08b00x00p01n01i02770ent IS
--This is an
error.
--ERROR: COMMENTS MUST BE ON ONE LINE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s08b00x00p01n01i02770 - Comments must be on one line."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s08b00x00p01n01i02770arch;
|
--
-- Test bench for signed multiplier.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb is
end entity;
architecture arch of tb is
procedure test_mul(constant xbits: in integer;
constant ybits: in integer;
constant npipe: in integer;
signal clk: out std_ulogic;
signal xin: out std_logic_vector;
signal yin: out std_logic_vector;
signal zout: in std_logic_vector) is
variable all_x: boolean;
variable all_y: boolean;
variable num_x: integer;
variable num_y: integer;
variable x: integer;
variable y: integer;
variable i: integer;
type pipe_type is array (0 to npipe) of integer;
variable px, py: pipe_type;
begin
-- Test all X inputs if xbits <= 11; otherwise test a subset.
all_x := (xbits <= 11);
if all_x then
num_x := 2**xbits;
else
num_x := (xbits-8) * 2 * 256;
end if;
-- Test all Y inputs if ybits <= 11; otherwise test a subset.
all_y := (ybits <= 11);
if all_y then
num_y := 2**ybits;
else
num_y := (ybits-8) * 2 * 256;
end if;
i := 0;
for kx in 0 to num_x-1 loop
if all_x then
x := kx - 2**(xbits-1);
else
x := (kx mod 512 - 256) * 2**(kx/512);
end if;
for ky in 0 to num_y-1 loop
if all_y then
y := ky - 2**(ybits-1);
else
y := (ky mod 512 - 256) * (2**(ky/512));
end if;
clk <= '0';
xin <= std_logic_vector(to_signed(x, xbits));
yin <= std_logic_vector(to_signed(y, ybits));
wait for 5 ns;
px(1 to npipe) := px(0 to npipe-1);
py(1 to npipe) := py(0 to npipe-1);
px(0) := x;
py(0) := y;
if i >= npipe then
assert zout =
std_logic_vector(to_signed(px(npipe), xbits) *
to_signed(py(npipe), ybits));
end if;
clk <= '1';
wait for 5 ns;
i := i + 1;
end loop;
end loop;
xin(xin'high downto xin'low) <= (others => 'U');
yin(yin'high downto yin'low) <= (others => 'U');
for i in 1 to npipe loop
px(1 to npipe) := px(0 to npipe-1);
py(1 to npipe) := py(0 to npipe-1);
assert zout = std_logic_vector(to_signed(px(npipe), xbits) *
to_signed(py(npipe), ybits));
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end loop;
clk <= '0';
end procedure;
signal s1_clk: std_ulogic;
signal s1_xin: std_logic_vector(3 downto 0);
signal s1_yin: std_logic_vector(3 downto 0);
signal s1_zout: std_logic_vector(7 downto 0);
signal s2_clk: std_ulogic;
signal s2_xin: std_logic_vector(6 downto 0);
signal s2_yin: std_logic_vector(7 downto 0);
signal s2_zout: std_logic_vector(14 downto 0);
signal s3_clk: std_ulogic;
signal s3_xin: std_logic_vector(7 downto 0);
signal s3_yin: std_logic_vector(7 downto 0);
signal s3_zout: std_logic_vector(15 downto 0);
signal s4_clk: std_ulogic;
signal s4_xin: std_logic_vector(9 downto 0);
signal s4_yin: std_logic_vector(10 downto 0);
signal s4_zout: std_logic_vector(20 downto 0);
signal s5_clk: std_ulogic;
signal s5_xin: std_logic_vector(3 downto 0);
signal s5_yin: std_logic_vector(11 downto 0);
signal s5_zout: std_logic_vector(15 downto 0);
signal s6_clk: std_ulogic;
signal s6_xin: std_logic_vector(17 downto 0);
signal s6_yin: std_logic_vector(17 downto 0);
signal s6_zout: std_logic_vector(35 downto 0);
signal s7_clk: std_ulogic;
signal s7_xin: std_logic_vector(18 downto 0);
signal s7_yin: std_logic_vector(23 downto 0);
signal s7_zout: std_logic_vector(42 downto 0);
begin
-- Signed 4x4 multiplier, latency 0 clocks.
u1: entity work.smul_4_4
port map ( clk => s1_clk,
clken => '1',
xin => s1_xin,
yin => s1_yin,
zout => s1_zout );
-- Signed 7x8 multiplier, latency 0 clocks.
u2: entity work.smul_7_8
port map ( clk => s2_clk,
clken => '1',
xin => s2_xin,
yin => s2_yin,
zout => s2_zout );
-- Signex 8x8 multiplier, latency 0 clocks.
u3: entity work.smul_8_8
port map ( clk => s3_clk,
clken => '1',
xin => s3_xin,
yin => s3_yin,
zout => s3_zout );
-- Signex 10x11 multiplier, latency 0 clocks.
u4: entity work.smul_10_11
port map ( clk => s4_clk,
clken => '1',
xin => s4_xin,
yin => s4_yin,
zout => s4_zout );
-- Signex 4x12 multiplier, latency 1 clock.
u5: entity work.smul_4_12
port map ( clk => s5_clk,
clken => '1',
xin => s5_xin,
yin => s5_yin,
zout => s5_zout );
-- Signex 18x18 multiplier, latency 2 clocks.
u6: entity work.smul_18_18
port map ( clk => s6_clk,
clken => '1',
xin => s6_xin,
yin => s6_yin,
zout => s6_zout );
-- Signex 19x24 multiplier, latency 1 clock.
u7: entity work.smul_19_24
port map ( clk => s7_clk,
clken => '1',
xin => s7_xin,
yin => s7_yin,
zout => s7_zout );
process is
begin
report "Start test bench";
report "Testing 4x4 multiplier, latency 0";
test_mul(4, 4, 0, s1_clk, s1_xin, s1_yin, s1_zout);
report "Testing 7x8 multiplier, latency 0";
test_mul(7, 8, 0, s2_clk, s2_xin, s2_yin, s2_zout);
report "Testing 8x8 multiplier, latency 0";
test_mul(8, 8, 0, s3_clk, s3_xin, s3_yin, s3_zout);
report "Testing 10x11 multiplier, latency 0";
test_mul(10, 11, 0, s4_clk, s4_xin, s4_yin, s4_zout);
report "Testing 4x12 multiplier, latency 1 (subset of inputs)";
test_mul(4, 12, 1, s5_clk, s5_xin, s5_yin, s5_zout);
report "Testing 18x18 multiplier, latency 2 (subset of inputs)";
test_mul(18, 18, 2, s6_clk, s6_xin, s6_yin, s6_zout);
report "Testing 19x24 multiplier, latency 1 (subset of inputs)";
test_mul(19, 24, 1, s7_clk, s7_xin, s7_yin, s7_zout);
report "End test bench";
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_eclipse.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Quicklogic Eclipse rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- translate_off
library eclipsee;
use eclipsee.all;
-- translate_on
entity eclipse_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of eclipse_syncram_2p is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end component;
component RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end component;
component RAM512X4_25um
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end component;
component RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end component;
constant dlen : integer := dbits + 18;
signal di1, q2, gnd : std_logic_vector(dlen downto 0);
signal a1, a2 : std_logic_vector(12 downto 0);
begin
gnd <= (others => '0');
di1(dbits-1 downto 0) <= din; di1(dlen downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= waddr; a1(12 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= raddr; a2(12 downto abits) <= (others => '0');
dout <= q2(dbits-1 downto 0); q2(dlen downto dbits) <= (others => '0');
a7 : if (abits <= 7) generate
x : for i in 0 to (dbits-1)/18 generate
u0 : RAM128X18_25um port map (
a1(6 downto 0), a2(6 downto 0), di1(i*18+17 downto i*18),
write, rena, wclk, rclk, gnd(0), q2(i*18+17 downto i*18));
end generate;
end generate;
a8 : if (abits = 8) generate
x : for i in 0 to (dbits-1)/9 generate
u0 : RAM256X9_25um port map (
a1(7 downto 0), a2(7 downto 0), di1(i*9+8 downto i*9),
write, rena, wclk, rclk, gnd(0), q2(i*9+8 downto i*9));
end generate;
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to (dbits-1)/4 generate
u0 : RAM512X4_25um port map (
a1(8 downto 0), a2(8 downto 0), di1(i*4+3 downto i*4),
write, rena, wclk, rclk, gnd(0), q2(i*4+3 downto i*4));
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to (dbits-1)/2 generate
u0 : RAM1024X2_25um port map (
a1(9 downto 0), a2(9 downto 0), di1(i*2+1 downto i*2),
write, rena, wclk, rclk, gnd(0), q2(i*2+1 downto i*2));
end generate;
end generate;
-- pragma translate_off
unsup : if abits > 10 generate
x : process
begin
assert false
report "Address depth larger than 10 is not supported for Eclipse rams"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2778.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ARCHITECTURE is
end ARCHITECTURE;
ENTITY c13s09b00x00p99n01i02778ent IS
END c13s09b00x00p99n01i02778ent;
ARCHITECTURE c13s09b00x00p99n01i02778arch OF c13s09b00x00p99n01i02778ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02778 - Reserved word ARCHITECTURE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02778arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2778.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ARCHITECTURE is
end ARCHITECTURE;
ENTITY c13s09b00x00p99n01i02778ent IS
END c13s09b00x00p99n01i02778ent;
ARCHITECTURE c13s09b00x00p99n01i02778arch OF c13s09b00x00p99n01i02778ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02778 - Reserved word ARCHITECTURE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02778arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2778.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ARCHITECTURE is
end ARCHITECTURE;
ENTITY c13s09b00x00p99n01i02778ent IS
END c13s09b00x00p99n01i02778ent;
ARCHITECTURE c13s09b00x00p99n01i02778arch OF c13s09b00x00p99n01i02778ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02778 - Reserved word ARCHITECTURE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02778arch;
|
--------------------------------------------------------------------------------
--
-- FileName: debounce.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 3/26/2012 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY debounce IS
GENERIC(
counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)
PORT(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC); --debounced signal
END debounce;
ARCHITECTURE logic OF debounce IS
SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set : STD_LOGIC; --sync reset to zero
SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output
BEGIN
counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
PROCESS(clk)
BEGIN
IF(clk'EVENT and clk = '1') THEN
flipflops(0) <= button;
flipflops(1) <= flipflops(0);
If(counter_set = '1') THEN --reset counter because input is changing
counter_out <= (OTHERS => '0');
ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
counter_out <= counter_out + 1;
ELSE --stable input time is met
result <= flipflops(1);
END IF;
END IF;
END PROCESS;
END logic;
|
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: mpu_fifo.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY mpu_fifo IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
wrfull : OUT STD_LOGIC
);
END mpu_fifo;
ARCHITECTURE SYN OF mpu_fifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
wrfull <= sub_wire0;
q <= sub_wire1(7 DOWNTO 0);
rdempty <= sub_wire2;
rdusedw <= sub_wire3(5 DOWNTO 0);
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => 64,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 8,
lpm_widthu => 6,
overflow_checking => "ON",
rdsync_delaypipe => 4,
read_aclr_synch => "ON",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 4
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2,
rdusedw => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "64"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: rdusedw 0 0 6 0 OUTPUT NODEFVAL "rdusedw[5..0]"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: rdusedw 0 0 6 0 @rdusedw 0 0 6 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu_wave*.jpg FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mpu_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mpu_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mpu_fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mpu_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mpu_fifo_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FFDCLR is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end FFDCLR;
architecture Behavioral of FFDCLR is
signal aux : std_logic := '0';
begin
with CLR select
Q <= '0' when '1',
aux when Others;
process (CLK)
begin
if CLK'event and CLK='1' then
if CLR = '1' then
aux <= '0';
else
aux <= D;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc263.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00263ent IS
END c03s01b02x00p08n01i00263ent;
ARCHITECTURE c03s01b02x00p08n01i00263arch OF c03s01b02x00p08n01i00263ent IS
BEGIN
TESTING: PROCESS
variable V : INTEGER := INTEGER'HIGH / 2 + 1;
BEGIN
V := V + V; -- operation should overflow
assert FALSE
report "***FAILED TEST: c03s01b02x00p08n01i00263 - Number is out of integer bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00263arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc263.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00263ent IS
END c03s01b02x00p08n01i00263ent;
ARCHITECTURE c03s01b02x00p08n01i00263arch OF c03s01b02x00p08n01i00263ent IS
BEGIN
TESTING: PROCESS
variable V : INTEGER := INTEGER'HIGH / 2 + 1;
BEGIN
V := V + V; -- operation should overflow
assert FALSE
report "***FAILED TEST: c03s01b02x00p08n01i00263 - Number is out of integer bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00263arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc263.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00263ent IS
END c03s01b02x00p08n01i00263ent;
ARCHITECTURE c03s01b02x00p08n01i00263arch OF c03s01b02x00p08n01i00263ent IS
BEGIN
TESTING: PROCESS
variable V : INTEGER := INTEGER'HIGH / 2 + 1;
BEGIN
V := V + V; -- operation should overflow
assert FALSE
report "***FAILED TEST: c03s01b02x00p08n01i00263 - Number is out of integer bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00263arch;
|
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_tb.all;
entity tb is
end tb;
architecture behavior of tb is
signal clock : std_logic := '0';
signal clock_next : std_logic := '0';
signal reset : std_logic := '0';
--TOP signals
signal n_error : std_logic;
signal stopped : std_logic;
begin
test : entity work.cp3_test(rtl)
port map(
clock => clock,
reset => reset,
n_error => n_error,
stopped => stopped
);
--clock generator
clock <= clock_next after 10 ns;
clock_next <= not clock when stopped = '0' else '0';
reset_proc : process
begin
reset <= '1';
for i in 1 to 5 loop
wait until rising_edge(clock);
end loop;
reset <= '0';
wait;
end process reset_proc;
end behavior;
|
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_tb.all;
entity tb is
end tb;
architecture behavior of tb is
signal clock : std_logic := '0';
signal clock_next : std_logic := '0';
signal reset : std_logic := '0';
--TOP signals
signal n_error : std_logic;
signal stopped : std_logic;
begin
test : entity work.cp3_test(rtl)
port map(
clock => clock,
reset => reset,
n_error => n_error,
stopped => stopped
);
--clock generator
clock <= clock_next after 10 ns;
clock_next <= not clock when stopped = '0' else '0';
reset_proc : process
begin
reset <= '1';
for i in 1 to 5 loop
wait until rising_edge(clock);
end loop;
reset <= '0';
wait;
end process reset_proc;
end behavior;
|
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_tb.all;
entity tb is
end tb;
architecture behavior of tb is
signal clock : std_logic := '0';
signal clock_next : std_logic := '0';
signal reset : std_logic := '0';
--TOP signals
signal n_error : std_logic;
signal stopped : std_logic;
begin
test : entity work.cp3_test(rtl)
port map(
clock => clock,
reset => reset,
n_error => n_error,
stopped => stopped
);
--clock generator
clock <= clock_next after 10 ns;
clock_next <= not clock when stopped = '0' else '0';
reset_proc : process
begin
reset <= '1';
for i in 1 to 5 loop
wait until rising_edge(clock);
end loop;
reset <= '0';
wait;
end process reset_proc;
end behavior;
|
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_tb.all;
entity tb is
end tb;
architecture behavior of tb is
signal clock : std_logic := '0';
signal clock_next : std_logic := '0';
signal reset : std_logic := '0';
--TOP signals
signal n_error : std_logic;
signal stopped : std_logic;
begin
test : entity work.cp3_test(rtl)
port map(
clock => clock,
reset => reset,
n_error => n_error,
stopped => stopped
);
--clock generator
clock <= clock_next after 10 ns;
clock_next <= not clock when stopped = '0' else '0';
reset_proc : process
begin
reset <= '1';
for i in 1 to 5 loop
wait until rising_edge(clock);
end loop;
reset <= '0';
wait;
end process reset_proc;
end behavior;
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 17, 2017
--! @brief Contains the entity and architecture of the
--! CPU's Master AXI4-Full Write Memory Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.plasoc_cpu_pack.all;
--! The Write Memory Controller implements a Master AXI4-Full Write
--! interface in order to allow the CPU to perform writes to
--! main memory and other devices external to the CPU. Much optimization
--! of the Write and Read Memory Controllers is needed for future revisions,
--! considering the current revision is implemented in a sequential, blocking
--! manner. Specifically, for the sake simplicity, the AXI4-Full Write Address,
--! Write Data, and Write Response channels are implemented as a state machine,
--! rather than as separate processes that can permit concurrent execution.
--!
--! Information specific to the AXI4-Full
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_cpu_axi4_write_cntrl is
generic(
-- CPU parameters.
cpu_address_width : integer := 16; --! Defines the address width of the CPU. This should normally be equal to the CPU's width.
cpu_data_width : integer := 32; --! Defines the data width of the CPU. This should normally be equal to the CPU's width.
-- Cache parameters.
cache_offset_width : integer := 5; --! Indicates whether the requested address of the CPU is cacheable or noncacheable.
-- AXI4-Full Write parameters.
axi_awuser_width : integer := 0; --! Width of user-define AXI4-Full Address Write signal.
axi_wuser_width : integer := 0; --! Width of user-define AXI4-Full Write Data signal.
axi_buser_width : integer := 0 --! Width of user-define AXI4-Full Write Response signal.
);
port(
-- Global interfaces.
clock : in std_logic; --! Clock. Tested with 50 MHz.
nreset : in std_logic; --! Reset on low.
-- Memory interface.
mem_write_address : in std_logic_vector(cpu_address_width-1 downto 0); --! The requested address sent to the write memory controller.
mem_write_data : in std_logic_vector(cpu_data_width-1 downto 0) := (others=>'0'); --! The word written to the write memory controller.
mem_write_strobe : in std_logic_vector(cpu_data_width/8-1 downto 0); --! Each bit that is high enables writing for the corresponding byte in mem_write_data.
mem_write_enable : in std_logic; --! Enables the operation of the write memory controller.
mem_write_valid : in std_logic; --! Indicates the cache has a valid word on mem_write_data.
mem_write_ready : out std_logic; --! Indicates the read memory controller is ready to sample a word from mem_write_data.
-- Cache interface.
cache_cacheable : in std_logic; --! Indicates whether the requested address of the CPU is cacheable or noncacheable.
-- Master AXI4-Full Write interface.
axi_awid : out std_logic_vector(-1 downto 0); --! AXI4-Full Address Write signal.
axi_awaddr : out std_logic_vector(cpu_address_width-1 downto 0) := (others=>'0'); --! AXI4-Full Address Write signal.
axi_awlen : out std_logic_vector(7 downto 0); --! AXI4-Full Address Write signal.
axi_awsize : out std_logic_vector(2 downto 0); --! AXI4-Full Address Write signal.
axi_awburst : out std_logic_vector(1 downto 0); --! AXI4-Full Address Write signal.
axi_awlock : out std_logic; --! AXI4-Full Address Write signal.
axi_awcache : out std_logic_vector(3 downto 0); --! AXI4-Full Address Write signal.
axi_awprot : out std_logic_vector(2 downto 0); --! AXI4-Full Address Write signal.
axi_awqos : out std_logic_vector(3 downto 0); --! AXI4-Full Address Write signal.
axi_awregion : out std_logic_vector(3 downto 0); --! AXI4-Full Address Write signal.
axi_awuser : out std_logic_vector(axi_awuser_width-1 downto 0); --! AXI4-Full Address Write signal.
axi_awvalid : out std_logic; --! AXI4-Full Address Write signal.
axi_awready : in std_logic; --! AXI4-Full Address Write signal.
axi_wdata : out std_logic_vector(cpu_data_width-1 downto 0) := (others=>'0'); --! AXI4-Full Write Data signal.
axi_wstrb : out std_logic_vector(cpu_data_width/8-1 downto 0) := (others=>'0'); --! AXI4-Full Write Data signal.
axi_wlast : out std_logic := '0'; --! AXI4-Full Write Data signal.
axi_wuser : out std_logic_vector(axi_wuser_width-1 downto 0); --! AXI4-Full Write Data signal.
axi_wvalid : out std_logic; --! AXI4-Full Write Data signal.
axi_wready : in std_logic; --! AXI4-Full Write Data signal.
axi_bid : in std_logic_vector(-1 downto 0); --! AXI4-Full Write Response signal.
axi_bresp : in std_logic_vector(1 downto 0); --! AXI4-Full Write Response signal.
axi_buser : in std_logic_vector(axi_buser_width-1 downto 0); --! AXI4-Full Write Response signal.
axi_bvalid : in std_logic; --! AXI4-Full Write Response signal.
axi_bready : out std_logic; --! AXI4-Full Write Response signal.
-- Error interface.
error_data : out std_logic_vector(2 downto 0) := (others=>'0') --! Returns value signifying error in the transaction.
);
end plasoc_cpu_axi4_write_cntrl;
architecture Behavioral of plasoc_cpu_axi4_write_cntrl is
subtype error_data_type is std_logic_vector(error_data'high downto error_data'low);
constant cpu_bytes_per_word : integer := cpu_data_width/8;
constant cache_words_per_line : integer := 2**cache_offset_width/cpu_bytes_per_word;
constant axi_burst_len_noncacheable : integer := 0;
constant axi_burst_len_cacheable : integer := cache_words_per_line-1;
type state_type is (state_wait,state_write,state_response,state_error);
signal state : state_type := state_wait;
signal counter : integer range 0 to cache_words_per_line;
signal axi_awlen_buff : std_logic_vector(7 downto 0) := (others=>'0');
signal axi_awvalid_buff : std_logic := '0';
signal axi_wvalid_buff : std_logic := '0';
signal axi_wlast_buff : std_logic := '0';
signal mem_write_ready_buff : std_logic := '0';
signal axi_bready_buff : std_logic := '0';
signal finished : boolean;
constant fifo_index_width : integer := cache_offset_width-clogb2(cpu_data_width/8);
type fifo_type is array(0 to 2**fifo_index_width-1) of std_logic_vector(cpu_data_width-1 downto 0);
type cntrl_fifo_type is array(0 to 2**fifo_index_width-1) of std_logic_vector((cpu_data_width/8+1)-1 downto 0);
signal fifo : fifo_type := (others=>(others=>'0'));
signal cntrl_fifo : cntrl_fifo_type := (others=>(others=>'0'));
signal m_ptr : integer range 0 to 2**fifo_index_width-1 := 0;
signal s_ptr : integer range 0 to 2**fifo_index_width-1 := 0;
begin
axi_awid <= (others=>'0');
axi_awlen <= axi_awlen_buff;
axi_awsize <= std_logic_vector(to_unsigned(clogb2(cpu_bytes_per_word),axi_awsize'length));
axi_awburst <= axi_burst_incr;
axi_awlock <= axi_lock_normal_access;
axi_awcache <= axi_cache_device_nonbufferable;
axi_awprot <= axi_prot_instr & not axi_prot_sec & not axi_prot_priv;
axi_awqos <= (others=>'0');
axi_awregion <= (others=>'0');
axi_awuser <= (others=>'0');
axi_awvalid <= axi_awvalid_buff;
axi_wvalid <= axi_wvalid_buff;
axi_wlast <= axi_wlast_buff;
mem_write_ready <= mem_write_ready_buff;
axi_bready <= axi_bready_buff;
axi_wuser <= (others=>'0');
axi_wdata <= fifo(m_ptr);
axi_wstrb <= cntrl_fifo(m_ptr)(cpu_data_width/8-1 downto 0);
axi_wlast_buff <= cntrl_fifo(m_ptr)(cpu_data_width/8);
process (clock)
variable burst_len : integer range 0 to 2**axi_awlen'length-1;
variable error_data_buff : error_data_type := (others=>'0');
begin
if rising_edge(clock) then
if nreset='0' then
error_data <= (others=>'0');
state <= state_wait;
else
case state is
-- WAIT mode.
when state_wait=>
-- Wait until the memory write interface issues a write memory access.
if mem_write_enable='1' then
-- Set control information.
axi_awaddr <= mem_write_address;
-- The burst length will change according to whether the memory access is cacheable or not.
if cache_cacheable='1' then
burst_len := axi_burst_len_cacheable;
else
burst_len := axi_burst_len_noncacheable;
end if;
axi_awlen_buff <= std_logic_vector(to_unsigned(burst_len,axi_awlen'length));
-- Set counter to keep track the number of words written to the axi write interface.
counter <= 0;
m_ptr <= 0;
s_ptr <= 0;
cntrl_fifo <= (others=>(others=>'0'));
finished <= False;
-- Wait until handshake before writing data.
if axi_awvalid_buff='1' and axi_awready='1' then
axi_awvalid_buff <= '0';
mem_write_ready_buff <= '1';
state <= state_write;
else
axi_awvalid_buff <= '1';
end if;
end if;
-- WRITE mode.
when state_write=>
if mem_write_valid='1' and mem_write_ready_buff='1' then
fifo(s_ptr) <= mem_write_data;
cntrl_fifo(s_ptr)(cpu_data_width/8-1 downto 0) <= mem_write_strobe;
if counter=axi_awlen_buff then
cntrl_fifo(s_ptr)(cpu_data_width/8) <= '1';
else
cntrl_fifo(s_ptr)(cpu_data_width/8) <= '0';
end if;
end if;
if s_ptr/=m_ptr and axi_wvalid_buff='1' and axi_wready='1' then
if m_ptr=2**fifo_index_width-1 then
m_ptr <= 0;
else
m_ptr <= m_ptr+1;
end if;
end if;
if mem_write_valid='1' and mem_write_ready_buff='1' and ((s_ptr+1)mod 2**fifo_index_width)/=m_ptr then
if s_ptr=2**fifo_index_width-1 then
s_ptr <= 0;
else
s_ptr <= s_ptr+1;
end if;
end if;
if mem_write_valid='1' and mem_write_ready_buff='1' and counter/=axi_awlen_buff then
counter <= counter+1;
end if;
if mem_write_valid='1' and mem_write_ready_buff='1' and counter=axi_awlen_buff then
finished <= True;
end if;
if (mem_write_valid='1' and mem_write_ready_buff='1' and counter=axi_awlen_buff) or finished then
mem_write_ready_buff <= '0';
elsif ((s_ptr+1)mod 2**fifo_index_width)/=m_ptr then
mem_write_ready_buff <= '1';
else
mem_write_ready_buff <= '0';
end if;
if axi_wvalid_buff='1' and axi_wready='1' and axi_wlast_buff='1' then
axi_wvalid_buff <= '0';
elsif s_ptr/=m_ptr then
axi_wvalid_buff <= '1';
else
axi_wvalid_buff <= '0';
end if;
if axi_wvalid_buff='1' and axi_wready='1' and axi_wlast_buff='1' then
axi_bready_buff <= '1';
state <= state_response;
end if;
when state_response=>
if axi_bvalid='1' and axi_bready_buff='1' then
axi_bready_buff <= '0';
if axi_bresp/=axi_resp_okay then
state <= state_error;
if axi_bresp=axi_resp_exokay then
error_data(error_axi_read_exokay) <= '1';
elsif axi_bresp=axi_resp_slverr then
error_data(error_axi_read_slverr) <= '1';
elsif axi_bresp=axi_resp_decerr then
error_data(error_axi_read_decerr) <= '1';
end if;
else
state <= state_wait;
end if;
end if;
-- ERROR mode.
when state_error=>
end case;
end if;
end if;
end process;
end Behavioral;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY random IS
PORT ( clk,clr : IN STD_LOGIC;
POSITION1, POSITION2 : OUT INTEGER RANGE 0 TO 48);
END random;
ARCHITECTURE behave OF random IS
SIGNAL ranvar_1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ranvar_2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(clk,clr)
BEGIN
if clr = '0' then
ranvar_1 <= "00100101";
-- ranvar_2 <= "00100101";
elsIF clk'event and clk = '1' THEN
ranvar_1 <= ranvar_1(7 DOWNTO 0);-- &PN_1
END IF;
IF conv_integer(ranvar_1)< 32 THEN
POSITION1<=16;
POSITION2<= 16;
elsif (conv_integer(ranvar_1) < 40) and (conv_integer(ranvar_1) >31) then
POSITION1<=17;
POSITION2<= 17;
elsif (conv_integer(ranvar_1) < 48) and (conv_integer(ranvar_1) >39) then
POSITION1<=18;
POSITION2<= 18;
elsif (conv_integer(ranvar_1) < 56) and (conv_integer(ranvar_1) >47) then
POSITION1<=19;
POSITION2<= 19;
ELSIF (conv_integer(ranvar_1) < 64) AND (conv_integer(ranvar_1) > 55) THEN
POSITION1<=20;
POSITION2 <=20;
elsif (conv_integer(ranvar_1) < 72) and (conv_integer(ranvar_1) >63) then
POSITION1<=21;
POSITION2<= 21;
elsif (conv_integer(ranvar_1) < 80) and (conv_integer(ranvar_1) >71) then
POSITION1<=22;
POSITION2<= 22;
elsif (conv_integer(ranvar_1) < 88) and (conv_integer(ranvar_1) >79) then
POSITION1<=23;
POSITION2<= 23;
ELSIF (conv_integer(ranvar_1) < 96) AND (conv_integer(ranvar_1) > 87) THEN
POSITION1<=24;
POSITION2 <=24;
elsif (conv_integer(ranvar_1) < 104) and (conv_integer(ranvar_1) >95) then
POSITION1<=25;
POSITION2<= 25;
elsif (conv_integer(ranvar_1) < 112) and (conv_integer(ranvar_1) >103) then
POSITION1<=26;
POSITION2<= 26;
elsif (conv_integer(ranvar_1) < 120) and (conv_integer(ranvar_1) >111) then
POSITION1<=27;
POSITION2<= 27;
ELSIF (conv_integer(ranvar_1) < 128) AND (conv_integer(ranvar_1) > 119) THEN
POSITION1<=28;
POSITION2 <=28;
elsif (conv_integer(ranvar_1) < 136) and (conv_integer(ranvar_1) >127) then
POSITION1<=29;
POSITION2<= 29;
elsif (conv_integer(ranvar_1) < 144) and (conv_integer(ranvar_1) >135) then
POSITION1<=30;
POSITION2<= 30;
elsif (conv_integer(ranvar_1) < 152) and (conv_integer(ranvar_1) >143) then
POSITION1<=31;
POSITION2<= 31;
ELSIF (conv_integer(ranvar_1) < 160) AND (conv_integer(ranvar_1) > 151) THEN
POSITION1<=32;
POSITION2 <=32;
elsif (conv_integer(ranvar_1) < 168) and (conv_integer(ranvar_1) >159) then
POSITION1<=33;
POSITION2<= 33;
elsif (conv_integer(ranvar_1) < 176) and (conv_integer(ranvar_1) >167) then
POSITION1<=34;
POSITION2<= 34;
elsif (conv_integer(ranvar_1) < 184) and (conv_integer(ranvar_1) >175) then
POSITION1<=35;
POSITION2<= 35;
ELSIF (conv_integer(ranvar_1) < 192) AND (conv_integer(ranvar_1) > 183) THEN
POSITION1<=36;
POSITION2 <=36;
elsif (conv_integer(ranvar_1) < 200) and (conv_integer(ranvar_1) >191) then
POSITION1<=37;
POSITION2<= 37;
elsif (conv_integer(ranvar_1) < 208) and (conv_integer(ranvar_1) >199) then
POSITION1<=38;
POSITION2<= 38;
elsif (conv_integer(ranvar_1) < 216) and (conv_integer(ranvar_1) >207) then
POSITION1<=39;
POSITION2<= 39;
ELSIF (conv_integer(ranvar_1) < 224) AND (conv_integer(ranvar_1) > 215) THEN
POSITION1<=40;
POSITION2 <=40;
elsif (conv_integer(ranvar_1) < 232) and (conv_integer(ranvar_1) >223) then
POSITION1<=41;
POSITION2<= 41;
elsif (conv_integer(ranvar_1) < 240) and (conv_integer(ranvar_1) >231) then
POSITION1<=42;
POSITION2<= 42;
elsif (conv_integer(ranvar_1) < 248) and (conv_integer(ranvar_1) >239) then
POSITION1<=43;
POSITION2<= 43;
ELSIF (conv_integer(ranvar_1) > 247) THEN
POSITION1<=44;
POSITION2 <=44;
END IF;
END PROCESS;
END behave; |
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`protect end_protected
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:47:46 05/10/2017
-- Design Name:
-- Module Name: /home/robert/Github/Spartan-HW/wankel_test.vhd
-- Project Name: SpartanHardware
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: rotary_machine
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY wankel_test IS
END wankel_test;
ARCHITECTURE behavior OF wankel_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rotary_machine
PORT(
EN : IN std_logic;
INS : IN std_logic_vector(1 downto 0);
DIR : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal EN : std_logic := '0';
signal INS : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal DIR : std_logic_vector(1 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rotary_machine PORT MAP (
EN => EN,
INS => INS,
DIR => DIR
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
EN <= '1';
wait for CLK_period*10;
-- insert stimulus here
INS <= "01";
wait for CLK_period;
INS <= "11";
wait for CLK_period;
INS <= "00";
wait for CLK_period;
INS <= "01";
wait for CLK_period;
INS <= "11";
wait for CLK_period;
INS <= "10";
wait for CLK_period;
INS <= "00";
wait for CLK_period;
INS <= "10";
wait for CLK_period;
INS <= "11";
wait for CLK_period;
INS <= "00";
wait;
end process;
END;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux2 is port(
a,b,s: in std_logic;
z: out std_logic
);
end mux2;
--
architecture mux2 of mux2 is
signal nb : std_logic;
signal v : std_logic;
signal w : std_logic;
component AND2 is port(
a,b: in std_logic;
z: out std_logic);
end component;
component OR2 is port(
a,b: in std_logic;
z: out std_logic);
end component;
component NOT1 is port(
a: in std_logic;
z: out std_logic);
end component;
begin
M1: NOT1 port map (b, nb);
M2: AND2 port map (a, nb, v);
M3: AND2 port map (s, b, w);
M4: OR2 port map (v, w, z);
end mux2; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:53:43 11/10/2013
-- Design Name:
-- Module Name: RS232_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RS232_TX is
port (
Clk : in std_logic;
Reset : in std_logic;
Start : in std_logic;
Data : in std_logic_vector(7 downto 0);
EOT : out std_logic;
TX : out std_logic);
end RS232_TX;
architecture Behavioral of RS232_TX is
type state is (idle, startbit, senddata, stopbit);
SIGNAL current_st, next_st: state;
SIGNAL copy_data: std_logic_vector (7 downto 0);
SIGNAL enable_copy, pw_sreset, dc_sreset, dc_enable: std_logic;
SIGNAL pulse_width: std_logic_vector (8 downto 0);
CONSTANT PEOC: std_logic_vector (8 downto 0) := "010101101";
SIGNAL data_count: std_logic_vector (2 downto 0);
BEGIN
PROCESS (clk, reset)
BEGIN
IF reset = '0' THEN
current_st <= idle;
ELSIF clk'event AND clk='1' THEN
current_st <= next_st;
END IF;
END PROCESS;
PROCESS (current_st, start, pulse_width, data_count)
BEGIN
enable_copy <= '0';
pw_sreset <= '0';
dc_sreset <= '0';
dc_enable <= '0';
EOT <= '0';
TX <= '1';
CASE current_st IS
WHEN idle =>
enable_copy <= '1';
EOT <= '1';
IF (start = '1') THEN
pw_sreset <= '1';
next_st <= startbit;
ELSE
next_st <= idle;
END IF;
WHEN startbit =>
TX <= '0';
IF (pulse_width = PEOC) THEN
pw_sreset <= '1';
dc_sreset <= '1';
next_st <= senddata;
ELSE
next_st <= startbit;
END IF;
WHEN senddata =>
TX <= copy_data(conv_integer(data_count));
IF (pulse_width = PEOC) THEN
dc_enable <= '1';
pw_sreset <= '1';
END IF;
IF (data_count = "111") AND (pulse_width = PEOC) THEN
pw_sreset <= '1';
next_st <= stopbit;
ELSE
next_st <= senddata;
END IF;
WHEN stopbit =>
TX <= '1';
IF (pulse_width = PEOC) THEN
next_st <= idle;
ELSE
next_st <= stopbit;
END IF;
END CASE;
END PROCESS;
PROCESS (clk, reset)
BEGIN
IF reset = '0' THEN
copy_data <= (others=>'0');
ELSIF clk'event AND clk = '1' THEN
IF enable_copy = '1' THEN
copy_data <= data;
END IF;
END IF;
END PROCESS;
PROCESS (clk, reset, pw_sreset)
BEGIN
IF reset = '0' THEN
pulse_width <= (others => '0');
ELSIF clk'event AND clk = '1' THEN
IF pw_sreset = '1' THEN
pulse_width <= (others => '0');
ELSE
pulse_width <= pulse_width + '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk, reset, dc_sreset)
BEGIN
IF reset = '0' THEN
data_count <= (others => '0');
ELSIF clk'event AND clk = '1' THEN
IF dc_sreset = '1' THEN
data_count <= (others => '0');
ELSIF dc_enable = '1' THEN
data_count <= data_count + '1';
END IF;
END IF;
END PROCESS;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity ic4021_tb is
end ic4021_tb;
architecture behavior of ic4021_tb is
component ic4021
port (d : in std_logic_vector(7 downto 0);
pl : in std_logic;
ds : in std_logic;
cp : in std_logic;
q5 : out std_logic;
q6 : out std_logic;
q7 : out std_logic);
end component;
signal clock: std_logic := '0';
signal serial: std_logic := '0';
signal load: std_logic := '0';
signal d: std_logic_vector(0 to 7) := "00000000";
signal q5, q6, q7: std_logic;
for ic: ic4021 use entity work.ic4021;
begin
ic: ic4021 port map (d => d,
pl => load,
ds => serial,
cp => clock,
q5 => q5,
q6 => q6,
q7 => q7);
process
constant byte: std_logic_vector(7 downto 0) := "01001101";
begin
wait for 10 ns;
report "should load parallel data when PL is high";
d <= byte;
load <= '1'; wait for 10 ns; load <= '0'; wait for 10 ns;
assert q5 = '0';
assert q6 = '1';
assert q7 = '0';
report "should load parallel data ignoring CP";
d <= byte;
load <= '1';
clock <= '1'; wait for 10 ns; clock <= '0'; wait for 10 ns;
assert q5 = '0';
assert q6 = '1';
assert q7 = '0';
report "should shift data";
d <= byte;
load <= '1'; wait for 10 ns; load <= '0';
serial <= '1';
for i in byte'range loop
assert q7 = byte(i);
clock <= '1'; wait for 10 ns; clock <= '0'; wait for 10 ns;
end loop;
assert q7 = serial;
report "end of test";
wait;
end process;
end behavior;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc975.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00975ent IS
END c06s03b00x00p05n01i00975ent;
ARCHITECTURE c06s03b00x00p05n01i00975arch OF c06s03b00x00p05n01i00975ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
type R2 is record
RE2: BOOLEAN;
end record;
type ONE is range 1 to 1;
type A1 is array (ONE) of BOOLEAN;
variable V1: R1 ;
variable V2: R2 ;
variable V5: A1 ;
variable V10: BOOLEAN;
BEGIN
V10 := V5.ONE;
-- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00975 - Illegal record element name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00975arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc975.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00975ent IS
END c06s03b00x00p05n01i00975ent;
ARCHITECTURE c06s03b00x00p05n01i00975arch OF c06s03b00x00p05n01i00975ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
type R2 is record
RE2: BOOLEAN;
end record;
type ONE is range 1 to 1;
type A1 is array (ONE) of BOOLEAN;
variable V1: R1 ;
variable V2: R2 ;
variable V5: A1 ;
variable V10: BOOLEAN;
BEGIN
V10 := V5.ONE;
-- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00975 - Illegal record element name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00975arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc975.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00975ent IS
END c06s03b00x00p05n01i00975ent;
ARCHITECTURE c06s03b00x00p05n01i00975arch OF c06s03b00x00p05n01i00975ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
type R2 is record
RE2: BOOLEAN;
end record;
type ONE is range 1 to 1;
type A1 is array (ONE) of BOOLEAN;
variable V1: R1 ;
variable V2: R2 ;
variable V5: A1 ;
variable V10: BOOLEAN;
BEGIN
V10 := V5.ONE;
-- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00975 - Illegal record element name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00975arch;
|
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect end_protected
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Class: ECE 368 Digital Design
-- Engineer: [Engineer 1]
-- [Engineer 2]
--
-- Create Date: [Date]
-- Module Name: [Module Name]
-- Project Name: [Project Name]
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- [Insert Description]
--
-- Notes:
-- [Insert Notes]
--
-- Revision:
-- [Insert Revision]
--
---------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity [Name]_tb is
end [Name]_tb;
architecture Behavioral of [Name] is
component [ComponentName] is
generic(
[VariableName]:integer:=8
);
port (
CLK : in STD_LOGIC;
[IN_Port0] : in STD_LOGIC;
[IN_Port1] : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
[OUT_Port0] : out STD_LOGIC;
[OUT_Port1] : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal CLK : STD_LOGIC := '0';
signal RESET : STD_LOGIC := '0';
begin
-- Instantiate the Unit Under Testing (UUT)
uut: [ComponentName] port map(
CLK => CLK : in STD_LOGIC;
[IN_Port0] => [IN_Port0] : in STD_LOGIC;
[IN_Port1] => [IN_Port1] : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
[OUT_Port0] => [OUT_Port0] : out STD_LOGIC;
[OUT_Port1] => [OUT_Port1] : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
m50MHZ_CLK: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process m50MHZ_CLK;
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 100 ns;
report "Starting [name] Test Bench" severity NOTE;
----- Unit Test -----
--Reset
RESET <= '1'; wait for period;
RESET <= '0'; wait for period;
assert ([OUT_Port0] = 00) report "Failed READ. [OUT_Port0]=" & integer'image(to_integer(unsigned([OUT_Port0]))) severity ERROR;
-- Test each input via loop
for i in 0 to 256 loop
[IN_Port0] <= x"F0";
[OUT_Port0] <= '0'; wait for period;
[OUT_Port0] <= '1'; wait for period;
[IN_Port0] <= std_logic_vector(to_signed(i,IN_Port0'length)); wait for 2*period;
[OUT_Port0] <= '0'; wait for period;
[OUT_Port0] <= '1'; wait for period;
end loop;
end process;
end Behavioral;
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rc_gen_stage_2 is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- 0 (enc), 1 (dec)
rc_out : out std_logic_vector(7 downto 0));
end rc_gen_stage_2;
architecture Behavioral of rc_gen_stage_2 is
signal rc_s : std_logic_vector(7 downto 0);
begin
pr_gen: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
if enc = '0' then
rc_s <= X"1b"; --80
else
rc_s <= X"D4";
end if;
else
if enc = '0' then
if ((rc_s and X"80") = X"00") then
rc_s <= rc_s(6 downto 0) & '0';
else
rc_s <= (rc_s(6 downto 0) & '0') xor X"1B";
end if;
else
if ((rc_s and X"01") = X"00") then
rc_s <= '0' & rc_s(7 downto 1);
else
rc_s <= ('0' & rc_s(7 downto 1)) xor X"8D";
end if;
end if;
end if;
end if;
end process;
rc_out <= rc_s;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "igmp_wrapper"
-- Project :
-------------------------------------------------------------------------------
-- File : igmp_wrapper_tb.vhd
-- Author : Colin Shea <colinshea@Colin-Sheas-MacBook-Pro.local>
-- Company :
-- Created : 2010-06-27
-- Last update: 2010-08-13
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-06-27 1.0 colinshea Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity igmp_wrapper_tb is
end igmp_wrapper_tb;
-------------------------------------------------------------------------------
architecture testbench of igmp_wrapper_tb is
-- component generics
constant gen_dataWidth : integer := 8;
signal srcMAC : std_logic_vector(47 downto 0):=X"010040506660";
signal destMAC : std_logic_vector(47 downto 0):=X"01005E1C1901";
signal vlanEn : std_logic := '0';
signal vlanId : std_logic_vector(11 downto 0):=X"06A";
signal srcIP : std_logic_vector(31 downto 0):=X"C0A80164";
signal destIP : std_logic_vector(31 downto 0):=X"EF9C1901";
signal tx_ready_n : std_logic;
signal tx_sof : std_logic;
signal tx_eof : std_logic;
signal tx_vld : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal igmp_sof : std_logic;
signal igmp_eof : std_logic;
signal igmp_vld : std_logic;
signal igmp_data : std_logic_vector(7 downto 0);
-- component ports
signal dataClk : std_logic;
signal reset : std_logic;
signal join : std_logic;
signal leave : std_logic;
signal respond : std_logic;
signal rspTime : std_logic_vector(7 downto 0);
-- signal destIP : std_logic_vector(31 downto 0);
-- signal destMAC : std_logic_vector(47 downto 0);
-- signal messageSent : std_logic;
-- signal out_join : std_logic;
-- signal out_leave : std_logic;
-- signal out_destMAC_o : std_logic_vector(47 downto 0);
-- signal out_destIP_o : std_logic_vector(31 downto 0);
signal out_enProc : std_logic;
signal out_enCommand : std_logic;
begin -- testbench
igmp_wrapper_1: entity work.igmp_wrapper
port map (
dataClk => dataClk,
reset => reset,
join => join,
leave => leave,
srcMAC => srcMAC,
srcIP => srcIP,
destMAC => destMAC,
destIP => destIP,
vlanEn => vlanEn,
vlanId => vlanId,
tx_ready_n => tx_ready_n,
tx_data => tx_data,
tx_vld => tx_vld,
tx_sof => tx_sof,
tx_eof => tx_eof,
igmp_data => igmp_data,
igmp_vld => igmp_vld,
igmp_sof => igmp_sof,
igmp_eof => igmp_eof,
out_enProc => out_enProc,
out_enCommand => out_enCommand
);
process
begin
dataClk <= '1';
wait for 4 ns;
dataClk <= '0';
wait for 4 ns;
end process;
process
begin
reset <= '1';
rspTime <= (others => '0');
leave <= '0';
join <= '0';
respond <= '0';
tx_ready_n <= '1';
wait for 24 ns;
reset <= '0';
join <= '1';
tx_ready_n <= '0';
wait for 8 ns;
join <= '0';
wait for 1 ms;
-- respond <= '1';
-- rspTime <= X"0A";
-- wait for 8 ns;
-- respond <= '0';
-- wait for 1 sec;
wait for 750 ns;
leave <= '1';
wait for 8 ns;
leave <= '0';
wait;
end process;
end testbench;
|
-- procSim.vhd
--
-- entity procSim -testbench for pipeline processor
-- architecture tb_noIO -
------------------------------------------------------------------------------
library ieee; -- packages:
use ieee.std_logic_1164.all; -- std_logic
use ieee.numeric_std.all; -- (un)signed
use work.sramPkg.all; -- sram
use work.procPkg.all; -- pipeProc
-- entity --------------------------------------------------------------
------------------------------------------------------------------------------
entity procSim is
generic(clkPeriod : time := 20 ns; -- clock period
clkCycles : positive := 200); -- clock cycles
end entity procSim;
-- architecture --------------------------------------------------------------
------------------------------------------------------------------------------
architecture tb_noIO of procSim is
signal clk, nRst : std_logic;
signal const0, const1 : std_logic;
signal dnWE, dnOE : std_logic;
signal iAddr, dAddr : std_logic_vector(31 downto 0);
signal iData, dData : std_logic_vector(31 downto 0);
signal iCtrl, dCtrl : fileIOty;
begin
const0 <= '0';
const1 <= '1';
-- memories ------------------------------------------------------
instMemI: sram generic map ( addrWd => 16,
dataWd => 32,
fileID => "instMem.dat")
port map ( nCS => const0,
nWE => const1,
nOE => const0,
addr => iAddr(7 downto 0),
data => iData,
fileIO => iCtrl);
dataMemI: sram generic map ( addrWd => 16,
dataWd => 32,
fileID => "dataMem.dat")
port map ( nCS => const0,
nWE => dnWE,
nOE => dnOE,
addr => dAddr(7 downto 0),
data => dData,
fileIO => dCtrl);
-- pipe processor ------------------------------------------------------
procIdeaI: procIdea port map ( clk => clk,
nRst => nRst,
iAddr => iAddr,
iData => iData,
dnWE => dnWE,
dnOE => dnOE,
dAddr => dAddr,
dData => dData);
-- stimuli ------------------------------------------------------
stiP: process is
begin
clk <= '0';
nRst <= '0', '1' after 5 ns;
iCtrl <= load, none after 5 ns;
dCtrl <= load, none after 5 ns;
wait for clkPeriod/2;
for n in 1 to clkCycles loop
clk <= '0', '1' after clkPeriod/2;
wait for clkPeriod;
end loop;
wait;
end process stiP;
end architecture tb_noIO;
------------------------------------------------------------------------------
-- procSim.vhd - end
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2855.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s10b00x00p03n01i02855ent IS
END c13s10b00x00p03n01i02855ent;
ARCHITECTURE c13s10b00x00p03n01i02855arch OF c13s10b00x00p03n01i02855ent IS
BEGIN
TESTING: PROCESS
variable based_int : integer := 3#12:;
BEGIN
assert FALSE
report "***FAILED TEST: c13s10b00x00p03n01i02855 - The sharp character (#) of a based literal can be replaced by colons (:), the replacement is done for both occurences.(Here left hand side # sign did not be replaced)"
severity ERROR;
wait;
END PROCESS TESTING;
END c13s10b00x00p03n01i02855arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2855.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s10b00x00p03n01i02855ent IS
END c13s10b00x00p03n01i02855ent;
ARCHITECTURE c13s10b00x00p03n01i02855arch OF c13s10b00x00p03n01i02855ent IS
BEGIN
TESTING: PROCESS
variable based_int : integer := 3#12:;
BEGIN
assert FALSE
report "***FAILED TEST: c13s10b00x00p03n01i02855 - The sharp character (#) of a based literal can be replaced by colons (:), the replacement is done for both occurences.(Here left hand side # sign did not be replaced)"
severity ERROR;
wait;
END PROCESS TESTING;
END c13s10b00x00p03n01i02855arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2855.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s10b00x00p03n01i02855ent IS
END c13s10b00x00p03n01i02855ent;
ARCHITECTURE c13s10b00x00p03n01i02855arch OF c13s10b00x00p03n01i02855ent IS
BEGIN
TESTING: PROCESS
variable based_int : integer := 3#12:;
BEGIN
assert FALSE
report "***FAILED TEST: c13s10b00x00p03n01i02855 - The sharp character (#) of a based literal can be replaced by colons (:), the replacement is done for both occurences.(Here left hand side # sign did not be replaced)"
severity ERROR;
wait;
END PROCESS TESTING;
END c13s10b00x00p03n01i02855arch;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_aa_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa_e-e_1.vhd,v 1.1 2007/03/03 17:24:06 wig Exp $
-- $Date: 2007/03/03 17:24:06 $
-- $Log: inst_aa_e-e_1.vhd,v $
-- Revision 1.1 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_aa_e
--
entity inst_aa_e is
-- Generics:
-- No Generated Generics for Entity inst_aa_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_aa_e
case_aa_p : out _E_CONNTYPE
-- End of Generated Port for Entity inst_aa_e
);
end inst_aa_e;
--
-- End of Generated Entity inst_aa_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- ----------------------------------------------------------------------------
-- Entity for value decoding (N->1)
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity VALUE_DECODER is
generic(
DATA_WIDTH : integer := 8;
VALUE : integer := 0
);
port(
-- input data interface
INPUT : in std_logic_vector(DATA_WIDTH - 1 downto 0);
-- output data interface
OUTPUT : out std_logic
);
end entity VALUE_DECODER;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of VALUE_DECODER is
begin
dec: process(INPUT)
begin
if (INPUT = conv_std_logic_vector(VALUE, DATA_WIDTH)) then
OUTPUT <= '1';
else
OUTPUT <= '0';
end if;
end process dec;
end architecture full; |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity DoubleMul is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_illegal_op : out std_logic;
o_overflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end;
architecture arch_DoubleMul of DoubleMul is
component imul53 is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_a : in std_logic_vector(52 downto 0);
i_b : in std_logic_vector(52 downto 0);
o_result : out std_logic_vector(105 downto 0);
o_shift : out std_logic_vector(6 downto 0);
o_rdy : out std_logic;
o_overflow : out std_logic
);
end component;
type RegistersType is record
busy : std_logic;
ena : std_logic_vector(4 downto 0);
a : std_logic_vector(63 downto 0);
b : std_logic_vector(63 downto 0);
result : std_logic_vector(63 downto 0);
zeroA : std_logic;
zeroB : std_logic;
mantA : std_logic_vector(52 downto 0);
mantB : std_logic_vector(52 downto 0);
expAB : std_logic_vector(12 downto 0);
expAlign : std_logic_vector(11 downto 0);
mantAlign : std_logic_vector(104 downto 0);
postShift : std_logic_vector(11 downto 0);
mantPostScale : std_logic_vector(104 downto 0);
nanA : std_logic;
nanB : std_logic;
overflow : std_logic;
illegal_op : std_logic;
end record;
constant R_RESET : RegistersType := (
'0', (others => '0'), -- busy, ena
(others => '0'), (others => '0'), (others => '0'), -- a, b, result
'0', '0', (others => '0'), (others => '0'), -- zeroA, zeroB, mantA, mantB
(others => '0'), (others => '0'), (others => '0'), -- expAB, expAlign, mantAlign
(others => '0'), (others => '0'), -- postShift, mantPostScale
'0', '0', '0', '0' -- nanA, nanB, overflow, illegal_op
);
constant zero11 : std_logic_vector(10 downto 0) := (others => '0');
constant zero63 : std_logic_vector(62 downto 0) := (others => '0');
constant zero105 : std_logic_vector(104 downto 0) := (others => '0');
signal r, rin : RegistersType;
signal w_imul_ena : std_logic;
signal wb_imul_result : std_logic_vector(105 downto 0);
signal wb_imul_shift : std_logic_vector(6 downto 0);
signal w_imul_rdy : std_logic;
signal w_imul_overflow : std_logic;
begin
u_imul53 : imul53 generic map (
async_reset => async_reset
) port map (
i_nrst => i_nrst,
i_clk => i_clk,
i_ena => w_imul_ena,
i_a => r.mantA,
i_b => r.mantB,
o_result => wb_imul_result,
o_shift => wb_imul_shift,
o_rdy => w_imul_rdy,
o_overflow => w_imul_overflow
);
-- registers:
comb : process(i_nrst, i_ena, i_a, i_b, r,
wb_imul_result, wb_imul_shift, w_imul_rdy, w_imul_overflow)
variable v : RegistersType;
variable signA : std_logic;
variable signB : std_logic;
variable mantA : std_logic_vector(52 downto 0);
variable mantB : std_logic_vector(52 downto 0);
variable zeroA : std_logic;
variable zeroB : std_logic;
variable expAB_t : std_logic_vector(11 downto 0);
variable expAB : std_logic_vector(12 downto 0);
variable mantAlign : std_logic_vector(104 downto 0);
variable expAlign_t : std_logic_vector(12 downto 0);
variable expAlign : std_logic_vector(12 downto 0);
variable postShift : std_logic_vector(11 downto 0);
variable mantPostScale : std_logic_vector(104 downto 0);
variable mantShort : std_logic_vector(52 downto 0);
variable tmpMant05 : std_logic_vector(51 downto 0);
variable mantOnes : std_logic;
variable mantEven : std_logic;
variable mant05 : std_logic;
variable rndBit : std_logic;
variable nanA : std_logic;
variable nanB : std_logic;
variable mantZeroA : std_logic;
variable mantZeroB : std_logic;
variable res : std_logic_vector(63 downto 0);
begin
v := r;
v.ena(0) := i_ena and not r.busy;
v.ena(1) := r.ena(0);
v.ena(4 downto 2) := r.ena(3 downto 2) & w_imul_rdy;
if i_ena = '1' then
v.busy := '1';
v.overflow := '0';
v.a := i_a;
v.b := i_b;
end if;
signA := r.a(63);
signB := r.b(63);
zeroA := '0';
if r.a(62 downto 0) = zero63 then
zeroA := '1';
end if;
zeroB := '0';
if r.b(62 downto 0) = zero63 then
zeroB := '1';
end if;
mantA(51 downto 0) := r.a(51 downto 0);
mantA(52) := '0';
if r.a(62 downto 52) /= zero11 then
mantA(52) := '1';
end if;
mantB(51 downto 0) := r.b(51 downto 0);
mantB(52) := '0';
if r.b(62 downto 52) /= zero11 then
mantB(52) := '1';
end if;
-- expA - expB + 1023
expAB_t := ('0' & r.a(62 downto 52)) + ('0' & r.b(62 downto 52));
expAB := ('0' & expAB_t) - 1023;
if r.ena(0) = '1' then
v.expAB := expAB;
v.zeroA := zeroA;
v.zeroB := zeroB;
v.mantA := mantA;
v.mantB := mantB;
end if;
w_imul_ena <= r.ena(1);
-- imul53 module:
mantAlign := (others => '0');
if wb_imul_result(105) = '1' then
mantAlign := wb_imul_result(105 downto 1);
elsif wb_imul_result(104) = '1' then
mantAlign := wb_imul_result(104 downto 0);
else
for i in 1 to 104 loop
if i = conv_integer(wb_imul_shift) then
mantAlign := wb_imul_result(104-i downto 0) & zero105(i-1 downto 0);
end if;
end loop;
end if;
expAlign_t := r.expAB + 1;
if wb_imul_result(105) = '1' then
expAlign := expAlign_t;
elsif r.a(62 downto 52) = zero11 or r.b(62 downto 52) = zero11 then
expAlign := expAlign_t - ("000000" & wb_imul_shift);
else
expAlign := r.expAB - ("000000" & wb_imul_shift);
end if;
-- IMPORTANT exception! new ZERO value
if expAlign(12) = '1' or expAlign = zero63(12 downto 0) then
if wb_imul_shift = "0000000" or wb_imul_result(105) = '1'
or r.a(62 downto 52) = zero11 or r.b(62 downto 52) = zero11 then
postShift := not expAlign(11 downto 0) + 2;
else
postShift := not expAlign(11 downto 0) + 1;
end if;
else
postShift := (others => '0');
end if;
if w_imul_rdy = '1' then
v.expAlign := expAlign(11 downto 0);
v.mantAlign := mantAlign;
v.postShift := postShift;
-- Exceptions:
v.nanA := '0';
if r.a(62 downto 52) = "11111111111" then
v.nanA := '1';
end if;
v.nanB := '0';
if r.b(62 downto 52) = "11111111111" then
v.nanB := '1';
end if;
v.overflow := '0';
if expAlign(12) = '0' and expAlign >= "0011111111111" then
v.overflow := '1';
end if;
end if;
-- Prepare to mantissa post-scale
mantPostScale := (others => '0');
if r.postShift = X"000" then
mantPostScale := r.mantAlign;
elsif r.postShift < conv_std_logic_vector(105, 12) then
for i in 1 to 104 loop
if conv_std_logic_vector(i, 7) = r.postShift(6 downto 0) then
mantPostScale := zero105(i-1 downto 0) & r.mantAlign(104 downto i);
end if;
end loop;
end if;
if r.ena(2) = '1' then
v.mantPostScale := mantPostScale;
end if;
-- Rounding bit
mantShort := r.mantPostScale(104 downto 52);
tmpMant05 := r.mantPostScale(51 downto 0);
mantOnes := '0';
if mantShort(52) = '1' and mantShort(51 downto 0) = X"fffffffffffff" then
mantOnes := '1';
end if;
mantEven := r.mantPostScale(52);
mant05 := '0';
if tmpMant05 = X"8000000000000" then
mant05 := '1';
end if;
rndBit := r.mantPostScale(51) and not(mant05 and not mantEven);
-- Check Borders
nanA := '0';
if r.a(62 downto 52) = "11111111111" then
nanA := '1';
end if;
nanB := '0';
if r.b(62 downto 52) = "11111111111" then
nanB := '1';
end if;
mantZeroA := '0';
if r.a(51 downto 0) = zero63(51 downto 0) then
mantZeroA := '1';
end if;
mantZeroB := '0';
if r.b(51 downto 0) = zero63(51 downto 0) then
mantZeroB := '1';
end if;
-- Result multiplexers:
if (nanA and mantZeroA and r.zeroB) = '1' or (nanB and mantZeroB and r.zeroA) = '1' then
res(63) := '1';
elsif (nanA and not mantZeroA) = '1' then
-- when both values are NaN, value B has higher priority if sign=1
res(63) := signA or (nanA and signB);
elsif (nanB and not mantZeroB) = '1' then
res(63) := signB;
else
res(63) := r.a(63) xor r.b(63);
end if;
if nanA = '1' then
res(62 downto 52) := r.a(62 downto 52);
elsif nanB = '1' then
res(62 downto 52) := r.b(62 downto 52);
elsif (r.expAlign(11) or r.zeroA or r.zeroB) = '1' then
res(62 downto 52) := (others => '0');
elsif r.overflow = '1' then
res(62 downto 52) := (others => '1');
else
res(62 downto 52) := r.expAlign(10 downto 0)
+ (mantOnes and rndBit and not r.overflow);
end if;
if (nanA and mantZeroA and not mantZeroB) = '1'
or (nanB and mantZeroB and not mantZeroA) = '1'
or (not nanA and not nanB and r.overflow) = '1' then
res(51 downto 0) := (others => '0');
elsif (nanA and not (nanB and signB)) = '1' then
-- when both values are NaN, value B has higher priority if sign=1
res(51) := '1';
res(50 downto 0) := r.a(50 downto 0);
elsif nanB = '1' then
res(51) := '1';
res(50 downto 0) := r.b(50 downto 0);
else
res(51 downto 0) := mantShort(51 downto 0) + rndBit;
end if;
if r.ena(3) = '1' then
v.result := res;
v.illegal_op := nanA or nanB;
v.busy := '0';
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
o_res <= r.result;
o_illegal_op <= r.illegal_op;
o_overflow <= r.overflow;
o_valid <= r.ena(4);
o_busy <= r.busy;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_project.template.vhdl.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_project is
-- Change these lines to setup configuration.
constant MY_PROJECT_DIR : string := "D:/git/PoC-Examples/"; -- e.g. "d:/vhdl/myproject/", "/home/me/projects/myproject/"
constant MY_OPERATING_SYSTEM : string := "WINDOWS"; -- e.g. "WINDOWS", "LINUX"
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_project.template.vhdl.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_project is
-- Change these lines to setup configuration.
constant MY_PROJECT_DIR : string := "D:/git/PoC-Examples/"; -- e.g. "d:/vhdl/myproject/", "/home/me/projects/myproject/"
constant MY_OPERATING_SYSTEM : string := "WINDOWS"; -- e.g. "WINDOWS", "LINUX"
end;
|
--This software is provided 'as-is', without any express or implied warranty.
--In no event will the authors be held liable for any damages arising from the use of this software.
--
--Permission is granted to anyone to use this software for any purpose,
--excluding commercial applications, and to alter it and redistribute
--it freely except for commercial applications.
--File: trivium.vhd
--Original Author: Richard Stern (rstern01@utopia.poly.edu)
--Author : Kyle D. Williams (kdw281@nyu.edu)
--Organization: Polytechnic University
--------------------------------------------------------
--Description: Trivium encryption algorithm
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity trivium is
port(
clk, rst : in std_logic;
hld : in std_logic; --active low if this is true then output is delayed until high again
key : in std_logic_vector(79 downto 0); --Secret 80-bit key input port
IV : in std_logic_vector(79 downto 0); --80-bit Initialization vector input port
o_vld : out std_logic; --Cipher Ready
z : out std_logic_vector(15 downto 0) --Cipher stream output
);
end trivium;
--key = 0x00000000000000000000
--IV = 0x00000000000000000000
--stream = 0xFBE0BF265859051B517A...
architecture rtl of trivium is
signal z_reg : std_logic_vector(15 downto 0);
signal z_reg_Buf : std_logic_vector(15 downto 0);
type state_type is (setup, run,hold);
signal state : state_type; --Current State
signal s, s_reg : std_logic_vector(288 downto 1);--Cipher's LFSR
signal count : integer; --Main Counter
signal count2 : integer; --buffer Counter
signal dat_rdy_buf : std_logic;
--Cipher requires bigendian so flip bits
signal key_flip :std_logic_vector(79 downto 0); --Secret 80-bit key input port
signal IV_flip :std_logic_vector(79 downto 0); --80-bit Initialization vector input port
function little_endian (b: std_logic_vector) return std_logic_vector is -- 80-bit Big Endian to Little Endian Convert (bit reverses each byte)
variable result : std_logic_vector(79 downto 0); --ex 0x0123456789 -> 0x084C2A6E19
begin
for i in 0 to 9 loop
result(((i*8)+7) downto (i*8)) :=
b(i*8) &
b((i*8) + 1) &
b((i*8) + 2) &
b((i*8) + 3) &
b((i*8) + 4) &
b((i*8) + 5) &
b((i*8) + 6) &
b((i*8) + 7);
end loop;
return result;
end;
begin
z<=z_reg;
--z <= s_reg(66) xor s_reg(93) xor s_reg(162) xor s_reg(177) xor s_reg(243) xor s_reg(288);
s(93 downto 1) <= s_reg(92 downto 1) & (s_reg(243) xor s_reg(288) xor (s_reg(286) and s_reg(287)) xor s_reg(69));
s(177 downto 94) <= s_reg(176 downto 94) & (s_reg(66) xor s_reg(93) xor (s_reg(91) and s_reg(92)) xor s_reg(171));
s(288 downto 178) <= s_reg(287 downto 178) & (s_reg(162) xor s_reg(177) xor (s_reg(175) and s_reg(176)) xor s_reg(264));
z_reg_process:
process(rst, clk) begin
if(rst = '1') then
z_reg <= (others => '0');
z_reg_Buf <= (others => '0');
count2 <= 0;
dat_rdy_buf <= '0';
elsif(rising_edge(clk)) then
if(state = run)then
if(count2 = 15)then--shift in 16 at a time
count2 <= 0;
dat_rdy_buf <= '1';
--in little endian form switch to little endian
z_reg(7 downto 0) <= ((s_reg(66) xor s_reg(93) xor s_reg(162) xor s_reg(177) xor s_reg(243) xor s_reg(288)) & z_reg_Buf(15 downto 9));
z_reg(15 downto 8)<= z_reg_Buf(8 downto 1);
else
count2 <= count2 + 1;
dat_rdy_buf <= '0';
end if;
--Bits are in little endian reverse nibbles
z_reg_Buf <= (s_reg(66) xor s_reg(93) xor s_reg(162) xor s_reg(177) xor s_reg(243) xor s_reg(288)) & z_reg_Buf(15 downto 1);
end if;
end if;
end process;
s_reg_process:
process(rst, clk) begin
if(rst = '1') then
s_reg(80 downto 1) <= key_flip(79 downto 0);
s_reg(93 downto 81) <= (others => '0');
s_reg(173 downto 94) <= IV_flip(79 downto 0);
s_reg(285 downto 174) <= (others => '0');
s_reg(288 downto 286) <= (others => '1');
elsif(rising_edge(clk)) then
if(state /= hold)then
s_reg <= s;
end if;
end if;
end process;
state_machine_process:
process(rst, clk) begin
if (rst = '1') then
state <= setup;
count <= 1;
o_vld <= '0';
elsif(rising_edge(clk)) then
case state is
when setup =>
if(count >= 1152) then --4 Cycles on 288 bits i.e. 4*288= 1152 passes
state <= run;
o_vld <= '1';
else
count <= count + 1;
state <= setup;
o_vld <= '0';
end if;
when run =>
if(count2 = 15)then
state <= hold;
else
state <= run;
end if;
when hold =>--this stops the data for the board to cycle
if(hld = '0')then --button press
state <= run;
else
state <= hold;
end if;
end case;
end if;
end process;
--Change input values to "little endian" so output matches offical test vectors
key_flip <= little_endian(key);
IV_flip <= little_endian(iv);
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1433.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01433ent IS
END c08s07b00x00p02n01i01433ent;
ARCHITECTURE c08s07b00x00p02n01i01433arch OF c08s07b00x00p02n01i01433ent IS
begin
TEST_PROCESS: process
variable I : INTEGER := 47;
begin
-- Misspelled 'elsif'.
if (I /= 47) then
NULL;
elseif (I = 47) then
NULL;
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01433 - reserved word 'elsif' is misspelled"
severity ERROR;
wait;
end process TEST_PROCESS;
END c08s07b00x00p02n01i01433arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1433.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01433ent IS
END c08s07b00x00p02n01i01433ent;
ARCHITECTURE c08s07b00x00p02n01i01433arch OF c08s07b00x00p02n01i01433ent IS
begin
TEST_PROCESS: process
variable I : INTEGER := 47;
begin
-- Misspelled 'elsif'.
if (I /= 47) then
NULL;
elseif (I = 47) then
NULL;
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01433 - reserved word 'elsif' is misspelled"
severity ERROR;
wait;
end process TEST_PROCESS;
END c08s07b00x00p02n01i01433arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1433.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01433ent IS
END c08s07b00x00p02n01i01433ent;
ARCHITECTURE c08s07b00x00p02n01i01433arch OF c08s07b00x00p02n01i01433ent IS
begin
TEST_PROCESS: process
variable I : INTEGER := 47;
begin
-- Misspelled 'elsif'.
if (I /= 47) then
NULL;
elseif (I = 47) then
NULL;
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01433 - reserved word 'elsif' is misspelled"
severity ERROR;
wait;
end process TEST_PROCESS;
END c08s07b00x00p02n01i01433arch;
|
-- A2601 Main Bench
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
--
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity bench is
port (verbose: in std_logic);
end bench;
architecture bench of bench is
component A2601 is
port(vid_clk: in std_logic;
rst: in std_logic;
d: inout std_logic_vector(7 downto 0);
a: out std_logic_vector(12 downto 0);
r: out std_logic;
pa: inout std_logic_vector(7 downto 0);
pb: inout std_logic_vector(7 downto 0);
inpt4: in std_logic;
inpt5: in std_logic;
colu: out std_logic_vector(6 downto 0);
csyn: out std_logic;
vsyn: out std_logic;
hsyn: out std_logic;
au0: out std_logic;
au1: out std_logic;
av0: out std_logic_vector(3 downto 0);
av1: out std_logic_vector(3 downto 0);
ph0_out: out std_logic;
ph1_out: out std_logic);
end component;
component ram128x8 is
port(clk: in std_logic;
r: in std_logic;
d_in: in std_logic_vector(7 downto 0);
d_out: out std_logic_vector(7 downto 0);
a: in std_logic_vector(6 downto 0));
end component;
signal vid_clk: std_logic;
signal rst: std_logic;
signal d: std_logic_vector(7 downto 0);
signal a: std_logic_vector(15 downto 0);
signal pa: std_logic_vector(7 downto 0);
signal pb: std_logic_vector(7 downto 0);
signal inpt4: std_logic;
signal inpt5: std_logic;
signal colu: std_logic_vector(6 downto 0);
signal csyn: std_logic;
signal vsyn: std_logic;
signal hsyn: std_logic;
signal au0: std_logic;
signal au1: std_logic;
signal av0: std_logic_vector(3 downto 0);
signal av1: std_logic_vector(3 downto 0);
signal ph0: std_logic;
signal ph1: std_logic;
signal sc_clk: std_logic;
signal sc_r: std_logic;
signal sc_d_in: std_logic_vector(7 downto 0);
signal sc_d_out: std_logic_vector(7 downto 0);
signal sc_a: std_logic_vector(6 downto 0);
subtype bss_type is std_logic_vector(2 downto 0);
constant BANK00: bss_type := "000";
constant BANKF8: bss_type := "001";
constant BANKF6: bss_type := "010";
constant BANKFE: bss_type := "011";
constant BANKE0: bss_type := "100";
constant BANK3F: bss_type := "101";
signal bank: std_logic_vector(3 downto 0) := "0000";
signal tf_bank: std_logic_vector(1 downto 0);
signal e0_bank: std_logic_vector(2 downto 0);
signal e0_bank0: std_logic_vector(2 downto 0) := "000";
signal e0_bank1: std_logic_vector(2 downto 0) := "000";
signal e0_bank2: std_logic_vector(2 downto 0) := "000";
signal bss: bss_type;
signal sc: std_logic;
signal cpu_d: std_logic_vector(7 downto 0);
signal cpu_a: std_logic_vector(12 downto 0);
signal r: std_logic;
constant vid_clk_period: time := 17.5 ns;
--constant vid_clk_period: time := 17.4375 ns;
--constant vid_clk_period: time := 69.75 ns;
--constant clk_period: time := 279.365 ns;
--constant clk_period: time := 279 ns;
constant clk_period: time := 280 ns;
constant aud_period: time := 22.676 us;
procedure print_msg(
constant msg: in string;
constant val: in std_logic_vector(7 downto 0)) is
variable l: line;
begin
write(l, now);
write(l, string'(": "));
write(l, msg);
write(l, string'(": "));
hwrite(l, val);
writeline(output, l);
end print_msg;
procedure print_msg(
constant msg: in string;
constant val: in integer) is
variable l: line;
begin
write(l, now);
write(l, string'(": "));
write(l, msg);
write(l, string'(": "));
write(l, val);
writeline(output, l);
end print_msg;
procedure print_a_d(
constant a: in std_logic_vector(15 downto 0);
constant d: in std_logic_vector(7 downto 0)
) is
variable l: line;
begin
write(l, now);
write(l, string'(" A: "));
hwrite(l, a);
write(l, string'(" D: "));
hwrite(l, d);
writeline(output, l);
end print_a_d;
procedure status_report(
constant msg: in string) is
variable l: line;
begin
write(l, msg);
writeline(output, l);
end status_report;
type rom_array is array(0 to 65535) of std_logic_vector(7 downto 0);
shared variable rom: rom_array;
procedure load_rom(
constant fln: in string) is
file rf: text;
variable status: file_open_status;
variable l: line;
variable i: integer;
variable d: integer;
begin
file_open(status, rf, fln, read_mode);
assert (status = open_ok) report "Cannot open file.";
i := 0;
while not (endfile(rf)) loop
readline(rf, l);
read(l, d);
rom(i) := std_logic_vector(to_unsigned(d, 8));
i := i + 1 ;
end loop;
end procedure load_rom;
procedure write_byte(
file f: text;
constant val: in std_logic_vector(7 downto 0)) is
variable l: line;
begin
write(l, to_integer(unsigned(val)));
writeline(f, l);
end procedure write_byte;
procedure write_vsync(
file f: text) is
variable l: line;
begin
write(l, string'("VSYNC"));
writeline(f, l);
end procedure write_vsync;
begin
test_A2601: A2601
port map(vid_clk, rst, cpu_d, cpu_a, r, pa, pb, inpt4, inpt5, colu, csyn, vsyn, hsyn, au0, au1, av0, av1, ph0, ph1);
sc_ram128x8: ram128x8
port map(sc_clk, sc_r, sc_d_in, sc_d_out, sc_a);
-- This clock is phase shifted so that we can use Xilinx synchronous block RAM.
sc_clk <= not ph1;
sc_r <= '0' when cpu_a(12 downto 7) = "100000" else '1';
sc_d_in <= cpu_d;
sc_a <= cpu_a(6 downto 0);
-- ROM and SC output
process(cpu_a, d, sc_d_out, sc)
begin
if (cpu_a(12 downto 7) = "100001" and sc = '1') then
cpu_d <= sc_d_out;
elsif (cpu_a(12 downto 7) = "100000" and sc = '1') then
cpu_d <= "ZZZZZZZZ";
elsif (cpu_a(12) = '1') then
cpu_d <= d;
else
cpu_d <= "ZZZZZZZZ";
end if;
end process;
with cpu_a(11 downto 10) select e0_bank <=
e0_bank0 when "00",
e0_bank1 when "01",
e0_bank2 when "10",
"111" when "11",
"---" when others;
tf_bank <= bank(1 downto 0) when (cpu_a(11) = '0') else "11";
with bss select a <=
"0000" & cpu_a(11 downto 0) when BANK00,
"000" & bank(0) & cpu_a(11 downto 0) when BANKF8,
"00" & bank(1 downto 0) & cpu_a(11 downto 0) when BANKF6,
"000" & bank(0) & cpu_a(11 downto 0) when BANKFE,
"000" & e0_bank & cpu_a(9 downto 0) when BANKE0,
"000" & tf_bank & cpu_a(10 downto 0) when BANK3F,
"----------------" when others;
bankswch: process(ph0)
begin
if (ph0'event and ph0 = '1') then
if (rst = '1') then
bank <= "0000";
e0_bank0 <= "000";
e0_bank1 <= "000";
e0_bank2 <= "000";
else
case bss is
when BANKF8 =>
if (cpu_a = "1" & X"FF8") then
bank <= "0000";
elsif (cpu_a = "1" & X"FF9") then
bank <= "0001";
end if;
when BANKF6 =>
if (cpu_a = "1" & X"FF6") then
bank <= "0000";
elsif (cpu_a = "1" & X"FF7") then
bank <= "0001";
elsif (cpu_a = "1" & X"FF8") then
bank <= "0010";
elsif (cpu_a = "1" & X"FF9") then
bank <= "0011";
end if;
when BANKFE =>
if (cpu_a = "0" & X"1FE") then
bank <= "0000";
elsif (cpu_a = "1" & X"1FE") then
bank <= "0001";
end if;
when BANKE0 =>
if (cpu_a(12 downto 4) = "1" & X"FE" and cpu_a(3) = '0') then
e0_bank0 <= cpu_a(2 downto 0);
elsif (cpu_a(12 downto 4) = "1" & X"FE" and cpu_a(3) = '1') then
e0_bank1 <= cpu_a(2 downto 0);
elsif (cpu_a(12 downto 4) = "1" & X"FF" and cpu_a(3) = '0') then
e0_bank2 <= cpu_a(2 downto 0);
end if;
when BANK3F =>
--if (cpu_a(12 downto 6) = "0000000") then
if (cpu_a = "0" & X"03F") then
bank(1 downto 0) <= cpu_d(1 downto 0);
end if;
when others =>
null;
end case;
end if;
end if;
end process;
bss <= BANK00;
sc <= '0';
pa <= "11111111";
pb(7 downto 1) <= "1111111";
inpt4 <= '1';
inpt5 <= '1';
rst_sig: process
begin
rst <= '1';
wait for 3 * clk_period / 2;
rst <= '0';
wait;
end process;
vid_clk_sig: process
begin
vid_clk <= '1';
wait for vid_clk_period / 2;
vid_clk <= '0';
wait for vid_clk_period / 2;
end process;
d <= rom(to_integer(unsigned(a)));
video: process
variable i: integer;
variable hcnt: integer;
variable vcnt: integer;
file ff: text;
begin
i := 0;
file_open(ff, "..\video\video.txt", write_mode);
wait for clk_period / 2;
while (true) loop
while (vsyn /= '1') loop
wait for clk_period;
end loop;
while (vsyn /= '0') loop
wait for clk_period;
end loop;
vcnt := 0;
while (vsyn /= '1') loop
if (hsyn = '1') then
if (hcnt /= 0) then
vcnt := vcnt + 1;
end if;
hcnt := 0;
write_byte(ff, X"FF");
else
write_byte(ff, colu & "0");
hcnt := hcnt + 1;
end if;
wait for clk_period;
end loop;
print_msg("Frame", i);
write_vsync(ff);
i := i + 1;
end loop;
file_close(ff);
end process;
audio: process
variable val: unsigned(4 downto 0);
file fa: text;
variable auv0: unsigned(3 downto 0);
variable auv1: unsigned(3 downto 0);
begin
file_open(fa, "..\audio\audio.txt", write_mode);
while (true) loop
val := "00000";
if (au0 = '1') then
val := "0" & unsigned(av0);
end if;
if (au1 = '1') then
val := val + ("0" & unsigned(av1));
end if;
write_byte(fa, std_logic_vector("000" & val));
wait for aud_period;
end loop;
end process;
process
begin
load_rom("..\rom\astrblst.txt");
wait;
end process;
end bench;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity array_io is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
d_o_0_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_0_full_n : IN STD_LOGIC;
d_o_0_write : OUT STD_LOGIC;
d_o_1_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_1_full_n : IN STD_LOGIC;
d_o_1_write : OUT STD_LOGIC;
d_o_2_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_2_full_n : IN STD_LOGIC;
d_o_2_write : OUT STD_LOGIC;
d_o_3_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_3_full_n : IN STD_LOGIC;
d_o_3_write : OUT STD_LOGIC;
d_i_0_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
d_i_0_ce0 : OUT STD_LOGIC;
d_i_0_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_0_address1 : OUT STD_LOGIC_VECTOR (3 downto 0);
d_i_0_ce1 : OUT STD_LOGIC;
d_i_0_q1 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_1_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
d_i_1_ce0 : OUT STD_LOGIC;
d_i_1_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_1_address1 : OUT STD_LOGIC_VECTOR (3 downto 0);
d_i_1_ce1 : OUT STD_LOGIC;
d_i_1_q1 : IN STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of array_io is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"array_io,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.359333,HLS_SYN_LAT=11,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=3532,HLS_SYN_LUT=2008}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (11 downto 0) := "000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (11 downto 0) := "000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (11 downto 0) := "000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (11 downto 0) := "000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (11 downto 0) := "000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (11 downto 0) := "000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (11 downto 0) := "000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (11 downto 0) := "000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (11 downto 0) := "001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (11 downto 0) := "010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (11 downto 0) := "100000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal acc_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal d_o_0_blk_n : STD_LOGIC;
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal d_o_1_blk_n : STD_LOGIC;
signal d_o_2_blk_n : STD_LOGIC;
signal d_o_3_blk_n : STD_LOGIC;
signal reg_410 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal ap_block_state6 : BOOLEAN;
signal ap_block_state8 : BOOLEAN;
signal ap_block_state10 : BOOLEAN;
signal reg_414 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_418 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_state5 : BOOLEAN;
signal ap_block_state7 : BOOLEAN;
signal ap_block_state9 : BOOLEAN;
signal reg_423 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal reg_427 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_431 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_436 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_440 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_fu_452_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_reg_1148 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp3_fu_466_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp3_reg_1169 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_1_fu_484_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_1_reg_1184 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_8_fu_494_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_8_reg_1195 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_15_fu_499_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_15_reg_1205 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp6_fu_543_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp6_reg_1216 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_2_fu_561_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_2_reg_1231 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_9_fu_571_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_9_reg_1242 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_16_fu_576_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_16_reg_1252 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp9_fu_626_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp9_reg_1263 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_3_fu_644_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_3_reg_1278 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_s_fu_654_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_s_reg_1289 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_17_fu_659_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_17_reg_1299 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp12_fu_709_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp12_reg_1310 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_4_fu_727_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_4_reg_1325 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_10_fu_737_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_10_reg_1336 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_18_fu_742_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_18_reg_1346 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp15_fu_792_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp15_reg_1357 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_5_fu_810_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_5_reg_1372 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_11_fu_820_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_11_reg_1383 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_19_fu_825_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_19_reg_1393 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp18_fu_875_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp18_reg_1404 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_6_fu_893_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_6_reg_1419 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_12_fu_903_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_12_reg_1425 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_20_fu_908_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_20_reg_1435 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp21_fu_958_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp21_reg_1441 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_7_fu_976_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_7_reg_1451 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_13_fu_986_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_13_reg_1457 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_21_fu_991_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_21_reg_1462 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp24_fu_1041_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp24_reg_1468 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_14_fu_1055_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_14_reg_1473 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_state11 : BOOLEAN;
signal tmp_1_22_fu_1060_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_22_reg_1478 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_state12 : BOOLEAN;
signal tmp_1_23_fu_586_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_24_fu_669_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_25_fu_752_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_26_fu_835_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_27_fu_918_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_28_fu_1001_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_29_fu_1066_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_30_fu_1102_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal temp_s_fu_527_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_1_fu_610_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_fu_693_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_3_fu_776_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_4_fu_859_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_5_fu_942_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_6_fu_1025_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_7_fu_1090_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_448_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_16_cast_fu_458_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_24_cast_fu_462_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_9_fu_480_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_fu_472_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp3_cast_fu_514_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_8_cast_fu_490_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp2_fu_517_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp2_cast_fu_523_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp1_fu_509_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_cast_fu_505_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_25_cast_fu_539_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_10_fu_557_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_s_fu_549_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp6_cast_fu_597_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_9_cast_fu_567_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp5_fu_600_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp5_cast_fu_606_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp4_fu_592_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_cast_fu_582_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_26_cast_fu_622_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_11_fu_640_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_fu_632_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp9_cast_fu_680_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_10_cast_fu_650_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp8_fu_683_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp8_cast_fu_689_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp7_fu_675_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_cast_fu_665_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_27_cast_fu_705_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_12_fu_723_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_fu_715_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp12_cast_fu_763_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_11_cast_fu_733_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp11_fu_766_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp11_cast_fu_772_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp10_fu_758_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_cast_fu_748_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_28_cast_fu_788_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_13_fu_806_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_fu_798_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp15_cast_fu_846_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_12_cast_fu_816_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp14_fu_849_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp14_cast_fu_855_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp13_fu_841_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_cast_fu_831_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_29_cast_fu_871_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_14_fu_889_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_5_fu_881_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp18_cast_fu_929_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_13_cast_fu_899_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp17_fu_932_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp17_cast_fu_938_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp16_fu_924_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_cast_fu_914_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_30_cast_fu_954_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_15_fu_972_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_6_fu_964_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp21_cast_fu_1012_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_14_cast_fu_982_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp20_fu_1015_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp20_cast_fu_1021_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp19_fu_1007_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_cast_fu_997_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_31_cast_fu_1037_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_7_fu_1047_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp24_cast_fu_1077_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_15_cast_fu_1051_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp23_fu_1080_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp23_cast_fu_1086_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp22_fu_1072_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (11 downto 0);
signal ap_condition_145 : BOOLEAN;
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
reg_418_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
reg_418 <= d_i_1_q0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
reg_418 <= d_i_1_q1;
end if;
end if;
end process;
reg_431_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
reg_431 <= d_i_1_q1;
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
reg_431 <= d_i_1_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
acc_0 <= temp_s_fu_527_p2;
tmp6_reg_1216 <= tmp6_fu_543_p2;
tmp_1_15_reg_1205 <= tmp_1_15_fu_499_p2;
tmp_1_1_reg_1184 <= tmp_1_1_fu_484_p2;
tmp_1_8_reg_1195 <= tmp_1_8_fu_494_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_1 <= temp_1_fu_610_p2;
tmp9_reg_1263 <= tmp9_fu_626_p2;
tmp_1_16_reg_1252 <= tmp_1_16_fu_576_p2;
tmp_1_2_reg_1231 <= tmp_1_2_fu_561_p2;
tmp_1_9_reg_1242 <= tmp_1_9_fu_571_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_2 <= temp_2_fu_693_p2;
tmp12_reg_1310 <= tmp12_fu_709_p2;
tmp_1_17_reg_1299 <= tmp_1_17_fu_659_p2;
tmp_1_3_reg_1278 <= tmp_1_3_fu_644_p2;
tmp_1_s_reg_1289 <= tmp_1_s_fu_654_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_3 <= temp_3_fu_776_p2;
tmp15_reg_1357 <= tmp15_fu_792_p2;
tmp_1_10_reg_1336 <= tmp_1_10_fu_737_p2;
tmp_1_18_reg_1346 <= tmp_1_18_fu_742_p2;
tmp_1_4_reg_1325 <= tmp_1_4_fu_727_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_4 <= temp_4_fu_859_p2;
tmp18_reg_1404 <= tmp18_fu_875_p2;
tmp_1_11_reg_1383 <= tmp_1_11_fu_820_p2;
tmp_1_19_reg_1393 <= tmp_1_19_fu_825_p2;
tmp_1_5_reg_1372 <= tmp_1_5_fu_810_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_5 <= temp_5_fu_942_p2;
tmp21_reg_1441 <= tmp21_fu_958_p2;
tmp_1_12_reg_1425 <= tmp_1_12_fu_903_p2;
tmp_1_20_reg_1435 <= tmp_1_20_fu_908_p2;
tmp_1_6_reg_1419 <= tmp_1_6_fu_893_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_6 <= temp_6_fu_1025_p2;
tmp24_reg_1468 <= tmp24_fu_1041_p2;
tmp_1_13_reg_1457 <= tmp_1_13_fu_986_p2;
tmp_1_21_reg_1462 <= tmp_1_21_fu_991_p2;
tmp_1_7_reg_1451 <= tmp_1_7_fu_976_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
acc_7 <= temp_7_fu_1090_p2;
tmp_1_14_reg_1473 <= tmp_1_14_fu_1055_p2;
tmp_1_22_reg_1478 <= tmp_1_22_fu_1060_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
reg_410 <= d_i_0_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
reg_414 <= d_i_1_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3))) then
reg_423 <= d_i_0_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3))) then
reg_427 <= d_i_0_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3))) then
reg_436 <= d_i_1_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
reg_440 <= d_i_1_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
tmp3_reg_1169 <= tmp3_fu_466_p2;
tmp_8_reg_1148 <= tmp_8_fu_452_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
if (((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state5;
end if;
when ap_ST_fsm_state6 =>
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state7 =>
if (((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state8;
else
ap_NS_fsm <= ap_ST_fsm_state7;
end if;
when ap_ST_fsm_state8 =>
if (((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state9;
else
ap_NS_fsm <= ap_ST_fsm_state8;
end if;
when ap_ST_fsm_state9 =>
if (((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_state9;
end if;
when ap_ST_fsm_state10 =>
if (((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state11;
else
ap_NS_fsm <= ap_ST_fsm_state10;
end if;
when ap_ST_fsm_state11 =>
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state12;
else
ap_NS_fsm <= ap_ST_fsm_state11;
end if;
when ap_ST_fsm_state12 =>
if (((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state12;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(9);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_block_state10_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state10 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state11_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state11 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state12_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state12 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state5_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state5 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state6_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state6 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state7_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state7 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state8_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state8 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_block_state9_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_block_state9 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n));
end process;
ap_condition_145_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n)
begin
ap_condition_145 <= not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)));
end process;
ap_done_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state12)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state12)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
d_i_0_address0_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_i_0_address0 <= ap_const_lv32_F(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_i_0_address0 <= ap_const_lv32_7(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_i_0_address0 <= ap_const_lv32_6(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_i_0_address0 <= ap_const_lv32_5(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_i_0_address0 <= ap_const_lv32_4(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_i_0_address0 <= ap_const_lv32_3(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_i_0_address0 <= ap_const_lv32_2(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
d_i_0_address0 <= ap_const_lv32_1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
d_i_0_address0 <= ap_const_lv32_0(4 - 1 downto 0);
else
d_i_0_address0 <= "XXXX";
end if;
end process;
d_i_0_address1_assign_proc : process(ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_i_0_address1 <= ap_const_lv32_E(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_i_0_address1 <= ap_const_lv32_D(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_i_0_address1 <= ap_const_lv32_C(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_i_0_address1 <= ap_const_lv32_B(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_i_0_address1 <= ap_const_lv32_A(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_i_0_address1 <= ap_const_lv32_9(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
d_i_0_address1 <= ap_const_lv32_8(4 - 1 downto 0);
else
d_i_0_address1 <= "XXXX";
end if;
end process;
d_i_0_ce0_assign_proc : process(ap_start, ap_CS_fsm_state1, d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)))) then
d_i_0_ce0 <= ap_const_logic_1;
else
d_i_0_ce0 <= ap_const_logic_0;
end if;
end process;
d_i_0_ce1_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3))) then
d_i_0_ce1 <= ap_const_logic_1;
else
d_i_0_ce1 <= ap_const_logic_0;
end if;
end process;
d_i_1_address0_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_i_1_address0 <= ap_const_lv32_7(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_i_1_address0 <= ap_const_lv32_6(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_i_1_address0 <= ap_const_lv32_5(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_i_1_address0 <= ap_const_lv32_4(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_i_1_address0 <= ap_const_lv32_3(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_i_1_address0 <= ap_const_lv32_2(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
d_i_1_address0 <= ap_const_lv32_1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
d_i_1_address0 <= ap_const_lv32_0(4 - 1 downto 0);
else
d_i_1_address0 <= "XXXX";
end if;
end process;
d_i_1_address1_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_i_1_address1 <= ap_const_lv32_F(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_i_1_address1 <= ap_const_lv32_E(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_i_1_address1 <= ap_const_lv32_D(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_i_1_address1 <= ap_const_lv32_C(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_i_1_address1 <= ap_const_lv32_B(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_i_1_address1 <= ap_const_lv32_A(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
d_i_1_address1 <= ap_const_lv32_9(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
d_i_1_address1 <= ap_const_lv32_8(4 - 1 downto 0);
else
d_i_1_address1 <= "XXXX";
end if;
end process;
d_i_1_ce0_assign_proc : process(ap_start, ap_CS_fsm_state1, d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)))) then
d_i_1_ce0 <= ap_const_logic_1;
else
d_i_1_ce0 <= ap_const_logic_0;
end if;
end process;
d_i_1_ce1_assign_proc : process(ap_start, ap_CS_fsm_state1, d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state4) or ((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)))) then
d_i_1_ce1 <= ap_const_logic_1;
else
d_i_1_ce1 <= ap_const_logic_0;
end if;
end process;
d_o_0_blk_n_assign_proc : process(d_o_0_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12))) then
d_o_0_blk_n <= d_o_0_full_n;
else
d_o_0_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_0_din_assign_proc : process(ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, tmp_8_reg_1148, tmp_1_1_reg_1184, tmp_1_2_reg_1231, tmp_1_3_reg_1278, tmp_1_4_reg_1325, tmp_1_5_reg_1372, tmp_1_6_reg_1419, tmp_1_7_reg_1451, ap_condition_145)
begin
if ((ap_condition_145 = ap_const_boolean_1)) then
if ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_o_0_din <= tmp_1_7_reg_1451;
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_o_0_din <= tmp_1_6_reg_1419;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_o_0_din <= tmp_1_5_reg_1372;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_o_0_din <= tmp_1_4_reg_1325;
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_o_0_din <= tmp_1_3_reg_1278;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_o_0_din <= tmp_1_2_reg_1231;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_o_0_din <= tmp_1_1_reg_1184;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_o_0_din <= tmp_8_reg_1148;
else
d_o_0_din <= "XXXXXXXXXXXXXXXX";
end if;
else
d_o_0_din <= "XXXXXXXXXXXXXXXX";
end if;
end process;
d_o_0_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
d_o_0_write <= ap_const_logic_1;
else
d_o_0_write <= ap_const_logic_0;
end if;
end process;
d_o_1_blk_n_assign_proc : process(d_o_1_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12))) then
d_o_1_blk_n <= d_o_1_full_n;
else
d_o_1_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_1_din_assign_proc : process(ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, tmp_1_8_reg_1195, tmp_1_9_reg_1242, tmp_1_s_reg_1289, tmp_1_10_reg_1336, tmp_1_11_reg_1383, tmp_1_12_reg_1425, tmp_1_13_reg_1457, tmp_1_14_reg_1473, ap_condition_145)
begin
if ((ap_condition_145 = ap_const_boolean_1)) then
if ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_o_1_din <= tmp_1_14_reg_1473;
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_o_1_din <= tmp_1_13_reg_1457;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_o_1_din <= tmp_1_12_reg_1425;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_o_1_din <= tmp_1_11_reg_1383;
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_o_1_din <= tmp_1_10_reg_1336;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_o_1_din <= tmp_1_s_reg_1289;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_o_1_din <= tmp_1_9_reg_1242;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_o_1_din <= tmp_1_8_reg_1195;
else
d_o_1_din <= "XXXXXXXXXXXXXXXX";
end if;
else
d_o_1_din <= "XXXXXXXXXXXXXXXX";
end if;
end process;
d_o_1_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
d_o_1_write <= ap_const_logic_1;
else
d_o_1_write <= ap_const_logic_0;
end if;
end process;
d_o_2_blk_n_assign_proc : process(d_o_2_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12))) then
d_o_2_blk_n <= d_o_2_full_n;
else
d_o_2_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_2_din_assign_proc : process(ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, tmp_1_15_reg_1205, tmp_1_16_reg_1252, tmp_1_17_reg_1299, tmp_1_18_reg_1346, tmp_1_19_reg_1393, tmp_1_20_reg_1435, tmp_1_21_reg_1462, tmp_1_22_reg_1478, ap_condition_145)
begin
if ((ap_condition_145 = ap_const_boolean_1)) then
if ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_o_2_din <= tmp_1_22_reg_1478;
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_o_2_din <= tmp_1_21_reg_1462;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_o_2_din <= tmp_1_20_reg_1435;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_o_2_din <= tmp_1_19_reg_1393;
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_o_2_din <= tmp_1_18_reg_1346;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_o_2_din <= tmp_1_17_reg_1299;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_o_2_din <= tmp_1_16_reg_1252;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_o_2_din <= tmp_1_15_reg_1205;
else
d_o_2_din <= "XXXXXXXXXXXXXXXX";
end if;
else
d_o_2_din <= "XXXXXXXXXXXXXXXX";
end if;
end process;
d_o_2_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
d_o_2_write <= ap_const_logic_1;
else
d_o_2_write <= ap_const_logic_0;
end if;
end process;
d_o_3_blk_n_assign_proc : process(d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12))) then
d_o_3_blk_n <= d_o_3_full_n;
else
d_o_3_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_3_din_assign_proc : process(ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, tmp_1_23_fu_586_p2, tmp_1_24_fu_669_p2, tmp_1_25_fu_752_p2, tmp_1_26_fu_835_p2, tmp_1_27_fu_918_p2, tmp_1_28_fu_1001_p2, tmp_1_29_fu_1066_p2, tmp_1_30_fu_1102_p2, ap_condition_145)
begin
if ((ap_condition_145 = ap_const_boolean_1)) then
if ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_o_3_din <= tmp_1_30_fu_1102_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_o_3_din <= tmp_1_29_fu_1066_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_o_3_din <= tmp_1_28_fu_1001_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_o_3_din <= tmp_1_27_fu_918_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_o_3_din <= tmp_1_26_fu_835_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_o_3_din <= tmp_1_25_fu_752_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_o_3_din <= tmp_1_24_fu_669_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_o_3_din <= tmp_1_23_fu_586_p2;
else
d_o_3_din <= "XXXXXXXXXXXXXXXX";
end if;
else
d_o_3_din <= "XXXXXXXXXXXXXXXX";
end if;
end process;
d_o_3_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state10) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state7) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state9) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))) or ((ap_const_logic_1 = ap_CS_fsm_state12) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n)))))) then
d_o_3_write <= ap_const_logic_1;
else
d_o_3_write <= ap_const_logic_0;
end if;
end process;
temp_1_fu_610_p2 <= std_logic_vector(signed(tmp5_cast_fu_606_p1) + signed(tmp4_fu_592_p2));
temp_2_fu_693_p2 <= std_logic_vector(signed(tmp8_cast_fu_689_p1) + signed(tmp7_fu_675_p2));
temp_3_fu_776_p2 <= std_logic_vector(signed(tmp11_cast_fu_772_p1) + signed(tmp10_fu_758_p2));
temp_4_fu_859_p2 <= std_logic_vector(signed(tmp14_cast_fu_855_p1) + signed(tmp13_fu_841_p2));
temp_5_fu_942_p2 <= std_logic_vector(signed(tmp17_cast_fu_938_p1) + signed(tmp16_fu_924_p2));
temp_6_fu_1025_p2 <= std_logic_vector(signed(tmp20_cast_fu_1021_p1) + signed(tmp19_fu_1007_p2));
temp_7_fu_1090_p2 <= std_logic_vector(signed(tmp23_cast_fu_1086_p1) + signed(tmp22_fu_1072_p2));
temp_s_fu_527_p2 <= std_logic_vector(signed(tmp2_cast_fu_523_p1) + signed(tmp1_fu_509_p2));
tmp10_fu_758_p2 <= std_logic_vector(unsigned(acc_3) + unsigned(tmp_3_fu_715_p1));
tmp11_cast_fu_772_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp11_fu_766_p2),32));
tmp11_fu_766_p2 <= std_logic_vector(signed(tmp12_cast_fu_763_p1) + signed(tmp_11_cast_fu_733_p1));
tmp12_cast_fu_763_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp12_reg_1310),18));
tmp12_fu_709_p2 <= std_logic_vector(signed(tmp_19_cast_fu_665_p1) + signed(tmp_27_cast_fu_705_p1));
tmp13_fu_841_p2 <= std_logic_vector(unsigned(acc_4) + unsigned(tmp_4_fu_798_p1));
tmp14_cast_fu_855_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp14_fu_849_p2),32));
tmp14_fu_849_p2 <= std_logic_vector(signed(tmp15_cast_fu_846_p1) + signed(tmp_12_cast_fu_816_p1));
tmp15_cast_fu_846_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp15_reg_1357),18));
tmp15_fu_792_p2 <= std_logic_vector(signed(tmp_20_cast_fu_748_p1) + signed(tmp_28_cast_fu_788_p1));
tmp16_fu_924_p2 <= std_logic_vector(unsigned(acc_5) + unsigned(tmp_5_fu_881_p1));
tmp17_cast_fu_938_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp17_fu_932_p2),32));
tmp17_fu_932_p2 <= std_logic_vector(signed(tmp18_cast_fu_929_p1) + signed(tmp_13_cast_fu_899_p1));
tmp18_cast_fu_929_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp18_reg_1404),18));
tmp18_fu_875_p2 <= std_logic_vector(signed(tmp_21_cast_fu_831_p1) + signed(tmp_29_cast_fu_871_p1));
tmp19_fu_1007_p2 <= std_logic_vector(unsigned(acc_6) + unsigned(tmp_6_fu_964_p1));
tmp1_fu_509_p2 <= std_logic_vector(unsigned(acc_0) + unsigned(tmp_fu_472_p1));
tmp20_cast_fu_1021_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp20_fu_1015_p2),32));
tmp20_fu_1015_p2 <= std_logic_vector(signed(tmp21_cast_fu_1012_p1) + signed(tmp_14_cast_fu_982_p1));
tmp21_cast_fu_1012_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp21_reg_1441),18));
tmp21_fu_958_p2 <= std_logic_vector(signed(tmp_22_cast_fu_914_p1) + signed(tmp_30_cast_fu_954_p1));
tmp22_fu_1072_p2 <= std_logic_vector(unsigned(acc_7) + unsigned(tmp_7_fu_1047_p1));
tmp23_cast_fu_1086_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp23_fu_1080_p2),32));
tmp23_fu_1080_p2 <= std_logic_vector(signed(tmp24_cast_fu_1077_p1) + signed(tmp_15_cast_fu_1051_p1));
tmp24_cast_fu_1077_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp24_reg_1468),18));
tmp24_fu_1041_p2 <= std_logic_vector(signed(tmp_23_cast_fu_997_p1) + signed(tmp_31_cast_fu_1037_p1));
tmp2_cast_fu_523_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp2_fu_517_p2),32));
tmp2_fu_517_p2 <= std_logic_vector(signed(tmp3_cast_fu_514_p1) + signed(tmp_8_cast_fu_490_p1));
tmp3_cast_fu_514_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp3_reg_1169),18));
tmp3_fu_466_p2 <= std_logic_vector(signed(tmp_16_cast_fu_458_p1) + signed(tmp_24_cast_fu_462_p1));
tmp4_fu_592_p2 <= std_logic_vector(unsigned(acc_1) + unsigned(tmp_s_fu_549_p1));
tmp5_cast_fu_606_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp5_fu_600_p2),32));
tmp5_fu_600_p2 <= std_logic_vector(signed(tmp6_cast_fu_597_p1) + signed(tmp_9_cast_fu_567_p1));
tmp6_cast_fu_597_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp6_reg_1216),18));
tmp6_fu_543_p2 <= std_logic_vector(signed(tmp_17_cast_fu_505_p1) + signed(tmp_25_cast_fu_539_p1));
tmp7_fu_675_p2 <= std_logic_vector(unsigned(acc_2) + unsigned(tmp_2_fu_632_p1));
tmp8_cast_fu_689_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp8_fu_683_p2),32));
tmp8_fu_683_p2 <= std_logic_vector(signed(tmp9_cast_fu_680_p1) + signed(tmp_10_cast_fu_650_p1));
tmp9_cast_fu_680_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp9_reg_1263),18));
tmp9_fu_626_p2 <= std_logic_vector(signed(tmp_18_cast_fu_582_p1) + signed(tmp_26_cast_fu_622_p1));
tmp_10_cast_fu_650_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_10_fu_557_p1 <= acc_2(16 - 1 downto 0);
tmp_11_cast_fu_733_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_11_fu_640_p1 <= acc_3(16 - 1 downto 0);
tmp_12_cast_fu_816_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_12_fu_723_p1 <= acc_4(16 - 1 downto 0);
tmp_13_cast_fu_899_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_13_fu_806_p1 <= acc_5(16 - 1 downto 0);
tmp_14_cast_fu_982_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_14_fu_889_p1 <= acc_6(16 - 1 downto 0);
tmp_15_cast_fu_1051_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),18));
tmp_15_fu_972_p1 <= acc_7(16 - 1 downto 0);
tmp_16_cast_fu_458_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_414),17));
tmp_17_cast_fu_505_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_431),17));
tmp_18_cast_fu_582_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_414),17));
tmp_19_cast_fu_665_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_418),17));
tmp_1_10_fu_737_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_1_3_reg_1278));
tmp_1_11_fu_820_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_1_4_reg_1325));
tmp_1_12_fu_903_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_1_5_reg_1372));
tmp_1_13_fu_986_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_1_6_reg_1419));
tmp_1_14_fu_1055_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_1_7_reg_1451));
tmp_1_15_fu_499_p2 <= std_logic_vector(unsigned(reg_414) + unsigned(tmp_1_8_fu_494_p2));
tmp_1_16_fu_576_p2 <= std_logic_vector(unsigned(reg_431) + unsigned(tmp_1_9_fu_571_p2));
tmp_1_17_fu_659_p2 <= std_logic_vector(unsigned(reg_414) + unsigned(tmp_1_s_fu_654_p2));
tmp_1_18_fu_742_p2 <= std_logic_vector(unsigned(reg_418) + unsigned(tmp_1_10_fu_737_p2));
tmp_1_19_fu_825_p2 <= std_logic_vector(unsigned(reg_414) + unsigned(tmp_1_11_fu_820_p2));
tmp_1_1_fu_484_p2 <= std_logic_vector(unsigned(reg_423) + unsigned(tmp_9_fu_480_p1));
tmp_1_20_fu_908_p2 <= std_logic_vector(unsigned(reg_418) + unsigned(tmp_1_12_fu_903_p2));
tmp_1_21_fu_991_p2 <= std_logic_vector(unsigned(reg_414) + unsigned(tmp_1_13_fu_986_p2));
tmp_1_22_fu_1060_p2 <= std_logic_vector(unsigned(reg_418) + unsigned(tmp_1_14_fu_1055_p2));
tmp_1_23_fu_586_p2 <= std_logic_vector(unsigned(reg_418) + unsigned(tmp_1_15_reg_1205));
tmp_1_24_fu_669_p2 <= std_logic_vector(unsigned(reg_436) + unsigned(tmp_1_16_reg_1252));
tmp_1_25_fu_752_p2 <= std_logic_vector(unsigned(reg_440) + unsigned(tmp_1_17_reg_1299));
tmp_1_26_fu_835_p2 <= std_logic_vector(unsigned(reg_431) + unsigned(tmp_1_18_reg_1346));
tmp_1_27_fu_918_p2 <= std_logic_vector(unsigned(reg_436) + unsigned(tmp_1_19_reg_1393));
tmp_1_28_fu_1001_p2 <= std_logic_vector(unsigned(reg_440) + unsigned(tmp_1_20_reg_1435));
tmp_1_29_fu_1066_p2 <= std_logic_vector(unsigned(reg_431) + unsigned(tmp_1_21_reg_1462));
tmp_1_2_fu_561_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_10_fu_557_p1));
tmp_1_30_fu_1102_p2 <= std_logic_vector(unsigned(reg_436) + unsigned(tmp_1_22_reg_1478));
tmp_1_3_fu_644_p2 <= std_logic_vector(unsigned(reg_423) + unsigned(tmp_11_fu_640_p1));
tmp_1_4_fu_727_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_12_fu_723_p1));
tmp_1_5_fu_810_p2 <= std_logic_vector(unsigned(reg_423) + unsigned(tmp_13_fu_806_p1));
tmp_1_6_fu_893_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_14_fu_889_p1));
tmp_1_7_fu_976_p2 <= std_logic_vector(unsigned(reg_423) + unsigned(tmp_15_fu_972_p1));
tmp_1_8_fu_494_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_8_reg_1148));
tmp_1_9_fu_571_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_1_1_reg_1184));
tmp_1_fu_448_p1 <= acc_0(16 - 1 downto 0);
tmp_1_s_fu_654_p2 <= std_logic_vector(unsigned(reg_427) + unsigned(tmp_1_2_reg_1231));
tmp_20_cast_fu_748_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_414),17));
tmp_21_cast_fu_831_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_418),17));
tmp_22_cast_fu_914_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_414),17));
tmp_23_cast_fu_997_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_418),17));
tmp_24_cast_fu_462_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_418),17));
tmp_25_cast_fu_539_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_436),17));
tmp_26_cast_fu_622_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_440),17));
tmp_27_cast_fu_705_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_431),17));
tmp_28_cast_fu_788_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_436),17));
tmp_29_cast_fu_871_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_440),17));
tmp_2_fu_632_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),32));
tmp_30_cast_fu_954_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_431),17));
tmp_31_cast_fu_1037_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_436),17));
tmp_3_fu_715_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_423),32));
tmp_4_fu_798_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),32));
tmp_5_fu_881_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_423),32));
tmp_6_fu_964_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),32));
tmp_7_fu_1047_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_423),32));
tmp_8_cast_fu_490_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_8_fu_452_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_1_fu_448_p1));
tmp_9_cast_fu_567_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_427),18));
tmp_9_fu_480_p1 <= acc_1(16 - 1 downto 0);
tmp_fu_472_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),32));
tmp_s_fu_549_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_423),32));
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
package rec09_pkg is
type myrec is record
b : std_logic;
end record;
end rec09_pkg;
|
entity vhdl2019 is
end entity;
architecture test of vhdl2019 is
impure function func1 (variable x : inout integer) return integer is
begin
x := x + 1;
return x;
end function;
begin
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:35 11/20/2016
-- Design Name:
-- Module Name: EXE_MEM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity EXE_MEM is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
EXE_ALUOUT : in STD_LOGIC_VECTOR (15 downto 0);
EXE_Rd : in STD_LOGIC_VECTOR (3 downto 0);
EXE_AccMEM : in STD_LOGIC;
EXE_memWE : in STD_LOGIC;
EXE_regWE : in STD_LOGIC;
EXE_DataIN : in STD_LOGIC_VECTOR (15 downto 0);
MEM_ALUOUT : out STD_LOGIC_VECTOR (15 downto 0);
MEM_Rd : out STD_LOGIC_VECTOR (3 downto 0);
MEM_AccMEM : out STD_LOGIC;
MEM_memWE : out STD_LOGIC;
MEM_regWE : out STD_LOGIC;
MEM_DataIN : out STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2: in STD_LOGIC
);
end EXE_MEM;
architecture Behavioral of EXE_MEM is
begin
process(clk, rst)
begin
if (rst = '0') then
MEM_AccMEM <= '0';
MEM_memWE <= '0';
MEM_regWE <= '0';
else
if (clk'event and clk = '1') then
if (enable = '1')and(MEM_RAM2 = '0') then
MEM_ALUOUT <= EXE_ALUOUT;
MEM_Rd <= EXE_Rd;
MEM_AccMEM <= EXE_AccMEM;
MEM_memWE <= EXE_memWE;
MEM_regWE <= EXE_regWE;
MEM_DataIN <= EXE_DataIN;
else
if (MEM_RAM2 = '1') then
MEM_AccMEM <= '0';
MEM_memWE <= '0';
MEM_regWE <= '0';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- bfm_system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bfm_system is
port (
sys_reset : in std_logic;
sys_clk : in std_logic
);
end bfm_system;
architecture STRUCTURE of bfm_system is
component bfm_processor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_MAddrAck : in std_logic;
PLB_MSsize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_msize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
component bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 0);
Sl_MRdErr : out std_logic_vector(0 to 0);
Sl_MWrErr : out std_logic_vector(0 to 0);
Sl_MIRQ : out std_logic_vector(0 to 0)
);
end component;
component bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 0);
M_priority : in std_logic_vector(0 to 1);
M_buslock : in std_logic_vector(0 to 0);
M_RNW : in std_logic_vector(0 to 0);
M_BE : in std_logic_vector(0 to 15);
M_msize : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 3);
M_type : in std_logic_vector(0 to 2);
M_TAttribute : in std_logic_vector(0 to 15);
M_lockErr : in std_logic_vector(0 to 0);
M_abort : in std_logic_vector(0 to 0);
M_UABus : in std_logic_vector(0 to 31);
M_ABus : in std_logic_vector(0 to 31);
M_wrDBus : in std_logic_vector(0 to 127);
M_wrBurst : in std_logic_vector(0 to 0);
M_rdBurst : in std_logic_vector(0 to 0);
PLB_MAddrAck : in std_logic_vector(0 to 0);
PLB_MRearbitrate : in std_logic_vector(0 to 0);
PLB_MTimeout : in std_logic_vector(0 to 0);
PLB_MBusy : in std_logic_vector(0 to 0);
PLB_MRdErr : in std_logic_vector(0 to 0);
PLB_MWrErr : in std_logic_vector(0 to 0);
PLB_MIRQ : in std_logic_vector(0 to 0);
PLB_MWrDAck : in std_logic_vector(0 to 0);
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic_vector(0 to 0);
PLB_MRdBTerm : in std_logic_vector(0 to 0);
PLB_MWrBTerm : in std_logic_vector(0 to 0);
PLB_Mssize : in std_logic_vector(0 to 1);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to 1);
PLB_wrPrim : in std_logic_vector(0 to 1);
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 1);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 1);
Sl_ssize : in std_logic_vector(0 to 3);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 127);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 0);
PLB_SMRdErr : in std_logic_vector(0 to 0);
PLB_SMWrErr : in std_logic_vector(0 to 0);
PLB_SMIRQ : in std_logic_vector(0 to 0);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
component synch_bus_wrapper is
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to 127);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end component;
component plb_bus_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 1);
MPLB_Rst : out std_logic_vector(0 to 0);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_UABus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 15);
M_RNW : in std_logic_vector(0 to 0);
M_abort : in std_logic_vector(0 to 0);
M_busLock : in std_logic_vector(0 to 0);
M_TAttribute : in std_logic_vector(0 to 15);
M_lockErr : in std_logic_vector(0 to 0);
M_MSize : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 0);
M_request : in std_logic_vector(0 to 0);
M_size : in std_logic_vector(0 to 3);
M_type : in std_logic_vector(0 to 2);
M_wrBurst : in std_logic_vector(0 to 0);
M_wrDBus : in std_logic_vector(0 to 127);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_SSize : in std_logic_vector(0 to 3);
Sl_wait : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 1);
PLB_MIRQ : out std_logic_vector(0 to 0);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 15);
PLB_MAddrAck : out std_logic_vector(0 to 0);
PLB_MTimeout : out std_logic_vector(0 to 0);
PLB_MBusy : out std_logic_vector(0 to 0);
PLB_MRdErr : out std_logic_vector(0 to 0);
PLB_MWrErr : out std_logic_vector(0 to 0);
PLB_MRdBTerm : out std_logic_vector(0 to 0);
PLB_MRdDAck : out std_logic_vector(0 to 0);
PLB_MRdDBus : out std_logic_vector(0 to 127);
PLB_MRdWdAddr : out std_logic_vector(0 to 3);
PLB_MRearbitrate : out std_logic_vector(0 to 0);
PLB_MWrBTerm : out std_logic_vector(0 to 0);
PLB_MWrDAck : out std_logic_vector(0 to 0);
PLB_MSSize : out std_logic_vector(0 to 1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 127);
PLB_wrPrim : out std_logic_vector(0 to 1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 0);
PLB_SMWrErr : out std_logic_vector(0 to 0);
PLB_SMBusy : out std_logic_vector(0 to 0);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 127);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 1);
Bus_Error_Det : out std_logic
);
end component;
component my_core_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 0);
Sl_MWrErr : out std_logic_vector(0 to 0);
Sl_MRdErr : out std_logic_vector(0 to 0);
Sl_MIRQ : out std_logic_vector(0 to 0);
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(0 to 1);
signal net_gnd10 : std_logic_vector(0 to 9);
signal net_gnd32 : std_logic_vector(0 to 31);
signal pgassign1 : std_logic_vector(0 to 127);
signal plb_bus_M_ABus : std_logic_vector(0 to 31);
signal plb_bus_M_BE : std_logic_vector(0 to 15);
signal plb_bus_M_MSize : std_logic_vector(0 to 1);
signal plb_bus_M_RNW : std_logic_vector(0 to 0);
signal plb_bus_M_TAttribute : std_logic_vector(0 to 15);
signal plb_bus_M_UABus : std_logic_vector(0 to 31);
signal plb_bus_M_abort : std_logic_vector(0 to 0);
signal plb_bus_M_busLock : std_logic_vector(0 to 0);
signal plb_bus_M_lockErr : std_logic_vector(0 to 0);
signal plb_bus_M_priority : std_logic_vector(0 to 1);
signal plb_bus_M_rdBurst : std_logic_vector(0 to 0);
signal plb_bus_M_request : std_logic_vector(0 to 0);
signal plb_bus_M_size : std_logic_vector(0 to 3);
signal plb_bus_M_type : std_logic_vector(0 to 2);
signal plb_bus_M_wrBurst : std_logic_vector(0 to 0);
signal plb_bus_M_wrDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_ABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_BE : std_logic_vector(0 to 15);
signal plb_bus_PLB_MAddrAck : std_logic_vector(0 to 0);
signal plb_bus_PLB_MBusy : std_logic_vector(0 to 0);
signal plb_bus_PLB_MIRQ : std_logic_vector(0 to 0);
signal plb_bus_PLB_MRdBTerm : std_logic_vector(0 to 0);
signal plb_bus_PLB_MRdDAck : std_logic_vector(0 to 0);
signal plb_bus_PLB_MRdDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_MRdErr : std_logic_vector(0 to 0);
signal plb_bus_PLB_MRdWdAddr : std_logic_vector(0 to 3);
signal plb_bus_PLB_MRearbitrate : std_logic_vector(0 to 0);
signal plb_bus_PLB_MSSize : std_logic_vector(0 to 1);
signal plb_bus_PLB_MSize : std_logic_vector(0 to 1);
signal plb_bus_PLB_MTimeout : std_logic_vector(0 to 0);
signal plb_bus_PLB_MWrBTerm : std_logic_vector(0 to 0);
signal plb_bus_PLB_MWrDAck : std_logic_vector(0 to 0);
signal plb_bus_PLB_MWrErr : std_logic_vector(0 to 0);
signal plb_bus_PLB_PAValid : std_logic;
signal plb_bus_PLB_RNW : std_logic;
signal plb_bus_PLB_Rst : std_logic;
signal plb_bus_PLB_SAValid : std_logic;
signal plb_bus_PLB_SMBusy : std_logic_vector(0 to 0);
signal plb_bus_PLB_SMRdErr : std_logic_vector(0 to 0);
signal plb_bus_PLB_SMWrErr : std_logic_vector(0 to 0);
signal plb_bus_PLB_SaddrAck : std_logic;
signal plb_bus_PLB_SrdBTerm : std_logic;
signal plb_bus_PLB_SrdComp : std_logic;
signal plb_bus_PLB_SrdDAck : std_logic;
signal plb_bus_PLB_SrdDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_SrdWdAddr : std_logic_vector(0 to 3);
signal plb_bus_PLB_Srearbitrate : std_logic;
signal plb_bus_PLB_Sssize : std_logic_vector(0 to 1);
signal plb_bus_PLB_Swait : std_logic;
signal plb_bus_PLB_SwrBTerm : std_logic;
signal plb_bus_PLB_SwrComp : std_logic;
signal plb_bus_PLB_SwrDAck : std_logic;
signal plb_bus_PLB_TAttribute : std_logic_vector(0 to 15);
signal plb_bus_PLB_UABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_abort : std_logic;
signal plb_bus_PLB_busLock : std_logic;
signal plb_bus_PLB_lockErr : std_logic;
signal plb_bus_PLB_masterID : std_logic_vector(0 to 0);
signal plb_bus_PLB_rdBurst : std_logic;
signal plb_bus_PLB_rdPrim : std_logic_vector(0 to 1);
signal plb_bus_PLB_rdpendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_rdpendReq : std_logic;
signal plb_bus_PLB_reqPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_size : std_logic_vector(0 to 3);
signal plb_bus_PLB_type : std_logic_vector(0 to 2);
signal plb_bus_PLB_wrBurst : std_logic;
signal plb_bus_PLB_wrDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_wrPrim : std_logic_vector(0 to 1);
signal plb_bus_PLB_wrpendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_wrpendReq : std_logic;
signal plb_bus_SPLB_Rst : std_logic_vector(0 to 1);
signal plb_bus_Sl_MBusy : std_logic_vector(0 to 1);
signal plb_bus_Sl_MIRQ : std_logic_vector(0 to 1);
signal plb_bus_Sl_MRdErr : std_logic_vector(0 to 1);
signal plb_bus_Sl_MWrErr : std_logic_vector(0 to 1);
signal plb_bus_Sl_SSize : std_logic_vector(0 to 3);
signal plb_bus_Sl_addrAck : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdBTerm : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdComp : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdDAck : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdDBus : std_logic_vector(0 to 255);
signal plb_bus_Sl_rdWdAddr : std_logic_vector(0 to 7);
signal plb_bus_Sl_rearbitrate : std_logic_vector(0 to 1);
signal plb_bus_Sl_wait : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrBTerm : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrComp : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrDAck : std_logic_vector(0 to 1);
signal synch : std_logic_vector(0 to 31);
signal synch0 : std_logic_vector(0 to 31);
signal synch1 : std_logic_vector(0 to 31);
signal synch2 : std_logic_vector(0 to 31);
signal synch3 : std_logic_vector(0 to 31);
begin
-- Internal assignments
pgassign1(0 to 31) <= synch0(0 to 31);
pgassign1(32 to 63) <= synch1(0 to 31);
pgassign1(64 to 95) <= synch2(0 to 31);
pgassign1(96 to 127) <= synch3(0 to 31);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd10(0 to 9) <= B"0000000000";
net_gnd2(0 to 1) <= B"00";
net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
bfm_processor : bfm_processor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch0,
SYNCH_IN => synch,
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0),
PLB_MSsize => plb_bus_PLB_MSSize,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0),
PLB_MTimeout => plb_bus_PLB_MTimeout(0),
PLB_MBusy => plb_bus_PLB_MBusy(0),
PLB_MRdErr => plb_bus_PLB_MRdErr(0),
PLB_MWrErr => plb_bus_PLB_MWrErr(0),
PLB_MIRQ => plb_bus_PLB_MIRQ(0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0),
M_request => plb_bus_M_request(0),
M_priority => plb_bus_M_priority,
M_buslock => plb_bus_M_busLock(0),
M_RNW => plb_bus_M_RNW(0),
M_BE => plb_bus_M_BE,
M_msize => plb_bus_M_MSize,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr(0),
M_abort => plb_bus_M_abort(0),
M_UABus => plb_bus_M_UABus,
M_ABus => plb_bus_M_ABus,
M_wrDBus => plb_bus_M_wrDBus,
M_wrBurst => plb_bus_M_wrBurst(0),
M_rdBurst => plb_bus_M_rdBurst(0)
);
bfm_memory : bfm_memory_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch1,
SYNCH_IN => synch,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim(0),
PLB_wrPrim => plb_bus_PLB_wrPrim(0),
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_UABus => plb_bus_PLB_UABus,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdpendReq => plb_bus_PLB_rdpendReq,
PLB_wrpendReq => plb_bus_PLB_wrpendReq,
PLB_rdpendPri => plb_bus_PLB_rdpendPri,
PLB_wrpendPri => plb_bus_PLB_wrpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck(0),
Sl_ssize => plb_bus_Sl_SSize(0 to 1),
Sl_wait => plb_bus_Sl_wait(0),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(0),
Sl_wrDAck => plb_bus_Sl_wrDAck(0),
Sl_wrComp => plb_bus_Sl_wrComp(0),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(0),
Sl_rdDBus => plb_bus_Sl_rdDBus(0 to 127),
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr(0 to 3),
Sl_rdDAck => plb_bus_Sl_rdDAck(0),
Sl_rdComp => plb_bus_Sl_rdComp(0),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(0),
Sl_MBusy => plb_bus_Sl_MBusy(0 to 0),
Sl_MRdErr => plb_bus_Sl_MRdErr(0 to 0),
Sl_MWrErr => plb_bus_Sl_MWrErr(0 to 0),
Sl_MIRQ => plb_bus_Sl_MIRQ(0 to 0)
);
bfm_monitor : bfm_monitor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch2,
SYNCH_IN => synch,
M_request => plb_bus_M_request(0 to 0),
M_priority => plb_bus_M_priority,
M_buslock => plb_bus_M_busLock(0 to 0),
M_RNW => plb_bus_M_RNW(0 to 0),
M_BE => plb_bus_M_BE,
M_msize => plb_bus_M_MSize,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr(0 to 0),
M_abort => plb_bus_M_abort(0 to 0),
M_UABus => plb_bus_M_UABus,
M_ABus => plb_bus_M_ABus,
M_wrDBus => plb_bus_M_wrDBus,
M_wrBurst => plb_bus_M_wrBurst(0 to 0),
M_rdBurst => plb_bus_M_rdBurst(0 to 0),
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0 to 0),
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0 to 0),
PLB_MTimeout => plb_bus_PLB_MTimeout(0 to 0),
PLB_MBusy => plb_bus_PLB_MBusy(0 to 0),
PLB_MRdErr => plb_bus_PLB_MRdErr(0 to 0),
PLB_MWrErr => plb_bus_PLB_MWrErr(0 to 0),
PLB_MIRQ => plb_bus_PLB_MIRQ(0 to 0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0 to 0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0 to 0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0 to 0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0 to 0),
PLB_Mssize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_MasterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_UABus => plb_bus_PLB_UABus,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdpendReq => plb_bus_PLB_rdpendReq,
PLB_wrpendReq => plb_bus_PLB_wrpendReq,
PLB_rdpendPri => plb_bus_PLB_rdpendPri,
PLB_wrpendPri => plb_bus_PLB_wrpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck,
Sl_wait => plb_bus_Sl_wait,
Sl_rearbitrate => plb_bus_Sl_rearbitrate,
Sl_wrDAck => plb_bus_Sl_wrDAck,
Sl_wrComp => plb_bus_Sl_wrComp,
Sl_wrBTerm => plb_bus_Sl_wrBTerm,
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rdDAck => plb_bus_Sl_rdDAck,
Sl_rdComp => plb_bus_Sl_rdComp,
Sl_rdBTerm => plb_bus_Sl_rdBTerm,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MIRQ => plb_bus_Sl_MIRQ,
Sl_ssize => plb_bus_Sl_SSize,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_Swait => plb_bus_PLB_Swait,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SMBusy => plb_bus_PLB_SMBusy(0 to 0),
PLB_SMRdErr => plb_bus_PLB_SMRdErr(0 to 0),
PLB_SMWrErr => plb_bus_PLB_SMWrErr(0 to 0),
PLB_SMIRQ => net_gnd1(0 to 0),
PLB_Sssize => plb_bus_PLB_Sssize
);
synch_bus : synch_bus_wrapper
port map (
FROM_SYNCH_OUT => pgassign1,
TO_SYNCH_IN => synch
);
plb_bus : plb_bus_wrapper
port map (
PLB_Clk => sys_clk,
SYS_Rst => sys_reset,
PLB_Rst => plb_bus_PLB_Rst,
SPLB_Rst => plb_bus_SPLB_Rst,
MPLB_Rst => open,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => plb_bus_M_ABus,
M_UABus => plb_bus_M_UABus,
M_BE => plb_bus_M_BE,
M_RNW => plb_bus_M_RNW(0 to 0),
M_abort => plb_bus_M_abort(0 to 0),
M_busLock => plb_bus_M_busLock(0 to 0),
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr(0 to 0),
M_MSize => plb_bus_M_MSize,
M_priority => plb_bus_M_priority,
M_rdBurst => plb_bus_M_rdBurst(0 to 0),
M_request => plb_bus_M_request(0 to 0),
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_wrBurst => plb_bus_M_wrBurst(0 to 0),
M_wrDBus => plb_bus_M_wrDBus,
Sl_addrAck => plb_bus_Sl_addrAck,
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_rdBTerm => plb_bus_Sl_rdBTerm,
Sl_rdComp => plb_bus_Sl_rdComp,
Sl_rdDAck => plb_bus_Sl_rdDAck,
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rearbitrate => plb_bus_Sl_rearbitrate,
Sl_SSize => plb_bus_Sl_SSize,
Sl_wait => plb_bus_Sl_wait,
Sl_wrBTerm => plb_bus_Sl_wrBTerm,
Sl_wrComp => plb_bus_Sl_wrComp,
Sl_wrDAck => plb_bus_Sl_wrDAck,
Sl_MIRQ => plb_bus_Sl_MIRQ,
PLB_MIRQ => plb_bus_PLB_MIRQ(0 to 0),
PLB_ABus => plb_bus_PLB_ABus,
PLB_UABus => plb_bus_PLB_UABus,
PLB_BE => plb_bus_PLB_BE,
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0 to 0),
PLB_MTimeout => plb_bus_PLB_MTimeout(0 to 0),
PLB_MBusy => plb_bus_PLB_MBusy(0 to 0),
PLB_MRdErr => plb_bus_PLB_MRdErr(0 to 0),
PLB_MWrErr => plb_bus_PLB_MWrErr(0 to 0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0 to 0),
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0 to 0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0 to 0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0 to 0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0 to 0),
PLB_MSSize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_RNW => plb_bus_PLB_RNW,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_MSize => plb_bus_PLB_MSize,
PLB_rdPendPri => plb_bus_PLB_rdpendPri,
PLB_wrPendPri => plb_bus_PLB_wrpendPri,
PLB_rdPendReq => plb_bus_PLB_rdpendReq,
PLB_wrPendReq => plb_bus_PLB_wrpendReq,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_SMRdErr => plb_bus_PLB_SMRdErr(0 to 0),
PLB_SMWrErr => plb_bus_PLB_SMWrErr(0 to 0),
PLB_SMBusy => plb_bus_PLB_SMBusy(0 to 0),
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_Sssize => plb_bus_PLB_Sssize,
PLB_Swait => plb_bus_PLB_Swait,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB2OPB_rearb => net_gnd2,
Bus_Error_Det => open
);
my_core : my_core_wrapper
port map (
SPLB_Clk => sys_clk,
SPLB_Rst => plb_bus_SPLB_Rst(1),
PLB_ABus => plb_bus_PLB_ABus,
PLB_UABus => plb_bus_PLB_UABus,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim(1),
PLB_wrPrim => plb_bus_PLB_wrPrim(1),
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_MSize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_wrPendReq => plb_bus_PLB_wrpendReq,
PLB_rdPendReq => plb_bus_PLB_rdpendReq,
PLB_wrPendPri => plb_bus_PLB_wrpendPri,
PLB_rdPendPri => plb_bus_PLB_rdpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_TAttribute => plb_bus_PLB_TAttribute,
Sl_addrAck => plb_bus_Sl_addrAck(1),
Sl_SSize => plb_bus_Sl_SSize(2 to 3),
Sl_wait => plb_bus_Sl_wait(1),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(1),
Sl_wrDAck => plb_bus_Sl_wrDAck(1),
Sl_wrComp => plb_bus_Sl_wrComp(1),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(1),
Sl_rdDBus => plb_bus_Sl_rdDBus(128 to 255),
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr(4 to 7),
Sl_rdDAck => plb_bus_Sl_rdDAck(1),
Sl_rdComp => plb_bus_Sl_rdComp(1),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(1),
Sl_MBusy => plb_bus_Sl_MBusy(1 to 1),
Sl_MWrErr => plb_bus_Sl_MWrErr(1 to 1),
Sl_MRdErr => plb_bus_Sl_MRdErr(1 to 1),
Sl_MIRQ => plb_bus_Sl_MIRQ(1 to 1),
SYNCH_IN => synch,
SYNCH_OUT => synch3
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- bfm_system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bfm_system is
port (
sys_reset : in std_logic;
sys_clk : in std_logic
);
end bfm_system;
architecture STRUCTURE of bfm_system is
component bfm_processor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_MAddrAck : in std_logic;
PLB_MSsize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_msize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
component bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 0);
Sl_MRdErr : out std_logic_vector(0 to 0);
Sl_MWrErr : out std_logic_vector(0 to 0);
Sl_MIRQ : out std_logic_vector(0 to 0)
);
end component;
component bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 0);
M_priority : in std_logic_vector(0 to 1);
M_buslock : in std_logic_vector(0 to 0);
M_RNW : in std_logic_vector(0 to 0);
M_BE : in std_logic_vector(0 to 15);
M_msize : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 3);
M_type : in std_logic_vector(0 to 2);
M_TAttribute : in std_logic_vector(0 to 15);
M_lockErr : in std_logic_vector(0 to 0);
M_abort : in std_logic_vector(0 to 0);
M_UABus : in std_logic_vector(0 to 31);
M_ABus : in std_logic_vector(0 to 31);
M_wrDBus : in std_logic_vector(0 to 127);
M_wrBurst : in std_logic_vector(0 to 0);
M_rdBurst : in std_logic_vector(0 to 0);
PLB_MAddrAck : in std_logic_vector(0 to 0);
PLB_MRearbitrate : in std_logic_vector(0 to 0);
PLB_MTimeout : in std_logic_vector(0 to 0);
PLB_MBusy : in std_logic_vector(0 to 0);
PLB_MRdErr : in std_logic_vector(0 to 0);
PLB_MWrErr : in std_logic_vector(0 to 0);
PLB_MIRQ : in std_logic_vector(0 to 0);
PLB_MWrDAck : in std_logic_vector(0 to 0);
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic_vector(0 to 0);
PLB_MRdBTerm : in std_logic_vector(0 to 0);
PLB_MWrBTerm : in std_logic_vector(0 to 0);
PLB_Mssize : in std_logic_vector(0 to 1);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to 1);
PLB_wrPrim : in std_logic_vector(0 to 1);
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 1);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 1);
Sl_ssize : in std_logic_vector(0 to 3);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 127);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 0);
PLB_SMRdErr : in std_logic_vector(0 to 0);
PLB_SMWrErr : in std_logic_vector(0 to 0);
PLB_SMIRQ : in std_logic_vector(0 to 0);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
component synch_bus_wrapper is
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to 127);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end component;
component plb_bus_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 1);
MPLB_Rst : out std_logic_vector(0 to 0);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_UABus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 15);
M_RNW : in std_logic_vector(0 to 0);
M_abort : in std_logic_vector(0 to 0);
M_busLock : in std_logic_vector(0 to 0);
M_TAttribute : in std_logic_vector(0 to 15);
M_lockErr : in std_logic_vector(0 to 0);
M_MSize : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 0);
M_request : in std_logic_vector(0 to 0);
M_size : in std_logic_vector(0 to 3);
M_type : in std_logic_vector(0 to 2);
M_wrBurst : in std_logic_vector(0 to 0);
M_wrDBus : in std_logic_vector(0 to 127);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_SSize : in std_logic_vector(0 to 3);
Sl_wait : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 1);
PLB_MIRQ : out std_logic_vector(0 to 0);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 15);
PLB_MAddrAck : out std_logic_vector(0 to 0);
PLB_MTimeout : out std_logic_vector(0 to 0);
PLB_MBusy : out std_logic_vector(0 to 0);
PLB_MRdErr : out std_logic_vector(0 to 0);
PLB_MWrErr : out std_logic_vector(0 to 0);
PLB_MRdBTerm : out std_logic_vector(0 to 0);
PLB_MRdDAck : out std_logic_vector(0 to 0);
PLB_MRdDBus : out std_logic_vector(0 to 127);
PLB_MRdWdAddr : out std_logic_vector(0 to 3);
PLB_MRearbitrate : out std_logic_vector(0 to 0);
PLB_MWrBTerm : out std_logic_vector(0 to 0);
PLB_MWrDAck : out std_logic_vector(0 to 0);
PLB_MSSize : out std_logic_vector(0 to 1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 127);
PLB_wrPrim : out std_logic_vector(0 to 1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 0);
PLB_SMWrErr : out std_logic_vector(0 to 0);
PLB_SMBusy : out std_logic_vector(0 to 0);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 127);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 1);
Bus_Error_Det : out std_logic
);
end component;
component my_core_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 0);
Sl_MWrErr : out std_logic_vector(0 to 0);
Sl_MRdErr : out std_logic_vector(0 to 0);
Sl_MIRQ : out std_logic_vector(0 to 0);
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(0 to 1);
signal net_gnd10 : std_logic_vector(0 to 9);
signal net_gnd32 : std_logic_vector(0 to 31);
signal pgassign1 : std_logic_vector(0 to 127);
signal plb_bus_M_ABus : std_logic_vector(0 to 31);
signal plb_bus_M_BE : std_logic_vector(0 to 15);
signal plb_bus_M_MSize : std_logic_vector(0 to 1);
signal plb_bus_M_RNW : std_logic_vector(0 to 0);
signal plb_bus_M_TAttribute : std_logic_vector(0 to 15);
signal plb_bus_M_UABus : std_logic_vector(0 to 31);
signal plb_bus_M_abort : std_logic_vector(0 to 0);
signal plb_bus_M_busLock : std_logic_vector(0 to 0);
signal plb_bus_M_lockErr : std_logic_vector(0 to 0);
signal plb_bus_M_priority : std_logic_vector(0 to 1);
signal plb_bus_M_rdBurst : std_logic_vector(0 to 0);
signal plb_bus_M_request : std_logic_vector(0 to 0);
signal plb_bus_M_size : std_logic_vector(0 to 3);
signal plb_bus_M_type : std_logic_vector(0 to 2);
signal plb_bus_M_wrBurst : std_logic_vector(0 to 0);
signal plb_bus_M_wrDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_ABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_BE : std_logic_vector(0 to 15);
signal plb_bus_PLB_MAddrAck : std_logic_vector(0 to 0);
signal plb_bus_PLB_MBusy : std_logic_vector(0 to 0);
signal plb_bus_PLB_MIRQ : std_logic_vector(0 to 0);
signal plb_bus_PLB_MRdBTerm : std_logic_vector(0 to 0);
signal plb_bus_PLB_MRdDAck : std_logic_vector(0 to 0);
signal plb_bus_PLB_MRdDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_MRdErr : std_logic_vector(0 to 0);
signal plb_bus_PLB_MRdWdAddr : std_logic_vector(0 to 3);
signal plb_bus_PLB_MRearbitrate : std_logic_vector(0 to 0);
signal plb_bus_PLB_MSSize : std_logic_vector(0 to 1);
signal plb_bus_PLB_MSize : std_logic_vector(0 to 1);
signal plb_bus_PLB_MTimeout : std_logic_vector(0 to 0);
signal plb_bus_PLB_MWrBTerm : std_logic_vector(0 to 0);
signal plb_bus_PLB_MWrDAck : std_logic_vector(0 to 0);
signal plb_bus_PLB_MWrErr : std_logic_vector(0 to 0);
signal plb_bus_PLB_PAValid : std_logic;
signal plb_bus_PLB_RNW : std_logic;
signal plb_bus_PLB_Rst : std_logic;
signal plb_bus_PLB_SAValid : std_logic;
signal plb_bus_PLB_SMBusy : std_logic_vector(0 to 0);
signal plb_bus_PLB_SMRdErr : std_logic_vector(0 to 0);
signal plb_bus_PLB_SMWrErr : std_logic_vector(0 to 0);
signal plb_bus_PLB_SaddrAck : std_logic;
signal plb_bus_PLB_SrdBTerm : std_logic;
signal plb_bus_PLB_SrdComp : std_logic;
signal plb_bus_PLB_SrdDAck : std_logic;
signal plb_bus_PLB_SrdDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_SrdWdAddr : std_logic_vector(0 to 3);
signal plb_bus_PLB_Srearbitrate : std_logic;
signal plb_bus_PLB_Sssize : std_logic_vector(0 to 1);
signal plb_bus_PLB_Swait : std_logic;
signal plb_bus_PLB_SwrBTerm : std_logic;
signal plb_bus_PLB_SwrComp : std_logic;
signal plb_bus_PLB_SwrDAck : std_logic;
signal plb_bus_PLB_TAttribute : std_logic_vector(0 to 15);
signal plb_bus_PLB_UABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_abort : std_logic;
signal plb_bus_PLB_busLock : std_logic;
signal plb_bus_PLB_lockErr : std_logic;
signal plb_bus_PLB_masterID : std_logic_vector(0 to 0);
signal plb_bus_PLB_rdBurst : std_logic;
signal plb_bus_PLB_rdPrim : std_logic_vector(0 to 1);
signal plb_bus_PLB_rdpendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_rdpendReq : std_logic;
signal plb_bus_PLB_reqPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_size : std_logic_vector(0 to 3);
signal plb_bus_PLB_type : std_logic_vector(0 to 2);
signal plb_bus_PLB_wrBurst : std_logic;
signal plb_bus_PLB_wrDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_wrPrim : std_logic_vector(0 to 1);
signal plb_bus_PLB_wrpendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_wrpendReq : std_logic;
signal plb_bus_SPLB_Rst : std_logic_vector(0 to 1);
signal plb_bus_Sl_MBusy : std_logic_vector(0 to 1);
signal plb_bus_Sl_MIRQ : std_logic_vector(0 to 1);
signal plb_bus_Sl_MRdErr : std_logic_vector(0 to 1);
signal plb_bus_Sl_MWrErr : std_logic_vector(0 to 1);
signal plb_bus_Sl_SSize : std_logic_vector(0 to 3);
signal plb_bus_Sl_addrAck : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdBTerm : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdComp : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdDAck : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdDBus : std_logic_vector(0 to 255);
signal plb_bus_Sl_rdWdAddr : std_logic_vector(0 to 7);
signal plb_bus_Sl_rearbitrate : std_logic_vector(0 to 1);
signal plb_bus_Sl_wait : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrBTerm : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrComp : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrDAck : std_logic_vector(0 to 1);
signal synch : std_logic_vector(0 to 31);
signal synch0 : std_logic_vector(0 to 31);
signal synch1 : std_logic_vector(0 to 31);
signal synch2 : std_logic_vector(0 to 31);
signal synch3 : std_logic_vector(0 to 31);
begin
-- Internal assignments
pgassign1(0 to 31) <= synch0(0 to 31);
pgassign1(32 to 63) <= synch1(0 to 31);
pgassign1(64 to 95) <= synch2(0 to 31);
pgassign1(96 to 127) <= synch3(0 to 31);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd10(0 to 9) <= B"0000000000";
net_gnd2(0 to 1) <= B"00";
net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
bfm_processor : bfm_processor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch0,
SYNCH_IN => synch,
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0),
PLB_MSsize => plb_bus_PLB_MSSize,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0),
PLB_MTimeout => plb_bus_PLB_MTimeout(0),
PLB_MBusy => plb_bus_PLB_MBusy(0),
PLB_MRdErr => plb_bus_PLB_MRdErr(0),
PLB_MWrErr => plb_bus_PLB_MWrErr(0),
PLB_MIRQ => plb_bus_PLB_MIRQ(0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0),
M_request => plb_bus_M_request(0),
M_priority => plb_bus_M_priority,
M_buslock => plb_bus_M_busLock(0),
M_RNW => plb_bus_M_RNW(0),
M_BE => plb_bus_M_BE,
M_msize => plb_bus_M_MSize,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr(0),
M_abort => plb_bus_M_abort(0),
M_UABus => plb_bus_M_UABus,
M_ABus => plb_bus_M_ABus,
M_wrDBus => plb_bus_M_wrDBus,
M_wrBurst => plb_bus_M_wrBurst(0),
M_rdBurst => plb_bus_M_rdBurst(0)
);
bfm_memory : bfm_memory_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch1,
SYNCH_IN => synch,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim(0),
PLB_wrPrim => plb_bus_PLB_wrPrim(0),
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_UABus => plb_bus_PLB_UABus,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdpendReq => plb_bus_PLB_rdpendReq,
PLB_wrpendReq => plb_bus_PLB_wrpendReq,
PLB_rdpendPri => plb_bus_PLB_rdpendPri,
PLB_wrpendPri => plb_bus_PLB_wrpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck(0),
Sl_ssize => plb_bus_Sl_SSize(0 to 1),
Sl_wait => plb_bus_Sl_wait(0),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(0),
Sl_wrDAck => plb_bus_Sl_wrDAck(0),
Sl_wrComp => plb_bus_Sl_wrComp(0),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(0),
Sl_rdDBus => plb_bus_Sl_rdDBus(0 to 127),
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr(0 to 3),
Sl_rdDAck => plb_bus_Sl_rdDAck(0),
Sl_rdComp => plb_bus_Sl_rdComp(0),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(0),
Sl_MBusy => plb_bus_Sl_MBusy(0 to 0),
Sl_MRdErr => plb_bus_Sl_MRdErr(0 to 0),
Sl_MWrErr => plb_bus_Sl_MWrErr(0 to 0),
Sl_MIRQ => plb_bus_Sl_MIRQ(0 to 0)
);
bfm_monitor : bfm_monitor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch2,
SYNCH_IN => synch,
M_request => plb_bus_M_request(0 to 0),
M_priority => plb_bus_M_priority,
M_buslock => plb_bus_M_busLock(0 to 0),
M_RNW => plb_bus_M_RNW(0 to 0),
M_BE => plb_bus_M_BE,
M_msize => plb_bus_M_MSize,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr(0 to 0),
M_abort => plb_bus_M_abort(0 to 0),
M_UABus => plb_bus_M_UABus,
M_ABus => plb_bus_M_ABus,
M_wrDBus => plb_bus_M_wrDBus,
M_wrBurst => plb_bus_M_wrBurst(0 to 0),
M_rdBurst => plb_bus_M_rdBurst(0 to 0),
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0 to 0),
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0 to 0),
PLB_MTimeout => plb_bus_PLB_MTimeout(0 to 0),
PLB_MBusy => plb_bus_PLB_MBusy(0 to 0),
PLB_MRdErr => plb_bus_PLB_MRdErr(0 to 0),
PLB_MWrErr => plb_bus_PLB_MWrErr(0 to 0),
PLB_MIRQ => plb_bus_PLB_MIRQ(0 to 0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0 to 0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0 to 0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0 to 0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0 to 0),
PLB_Mssize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_MasterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_UABus => plb_bus_PLB_UABus,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdpendReq => plb_bus_PLB_rdpendReq,
PLB_wrpendReq => plb_bus_PLB_wrpendReq,
PLB_rdpendPri => plb_bus_PLB_rdpendPri,
PLB_wrpendPri => plb_bus_PLB_wrpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck,
Sl_wait => plb_bus_Sl_wait,
Sl_rearbitrate => plb_bus_Sl_rearbitrate,
Sl_wrDAck => plb_bus_Sl_wrDAck,
Sl_wrComp => plb_bus_Sl_wrComp,
Sl_wrBTerm => plb_bus_Sl_wrBTerm,
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rdDAck => plb_bus_Sl_rdDAck,
Sl_rdComp => plb_bus_Sl_rdComp,
Sl_rdBTerm => plb_bus_Sl_rdBTerm,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MIRQ => plb_bus_Sl_MIRQ,
Sl_ssize => plb_bus_Sl_SSize,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_Swait => plb_bus_PLB_Swait,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SMBusy => plb_bus_PLB_SMBusy(0 to 0),
PLB_SMRdErr => plb_bus_PLB_SMRdErr(0 to 0),
PLB_SMWrErr => plb_bus_PLB_SMWrErr(0 to 0),
PLB_SMIRQ => net_gnd1(0 to 0),
PLB_Sssize => plb_bus_PLB_Sssize
);
synch_bus : synch_bus_wrapper
port map (
FROM_SYNCH_OUT => pgassign1,
TO_SYNCH_IN => synch
);
plb_bus : plb_bus_wrapper
port map (
PLB_Clk => sys_clk,
SYS_Rst => sys_reset,
PLB_Rst => plb_bus_PLB_Rst,
SPLB_Rst => plb_bus_SPLB_Rst,
MPLB_Rst => open,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => plb_bus_M_ABus,
M_UABus => plb_bus_M_UABus,
M_BE => plb_bus_M_BE,
M_RNW => plb_bus_M_RNW(0 to 0),
M_abort => plb_bus_M_abort(0 to 0),
M_busLock => plb_bus_M_busLock(0 to 0),
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr(0 to 0),
M_MSize => plb_bus_M_MSize,
M_priority => plb_bus_M_priority,
M_rdBurst => plb_bus_M_rdBurst(0 to 0),
M_request => plb_bus_M_request(0 to 0),
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_wrBurst => plb_bus_M_wrBurst(0 to 0),
M_wrDBus => plb_bus_M_wrDBus,
Sl_addrAck => plb_bus_Sl_addrAck,
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_rdBTerm => plb_bus_Sl_rdBTerm,
Sl_rdComp => plb_bus_Sl_rdComp,
Sl_rdDAck => plb_bus_Sl_rdDAck,
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rearbitrate => plb_bus_Sl_rearbitrate,
Sl_SSize => plb_bus_Sl_SSize,
Sl_wait => plb_bus_Sl_wait,
Sl_wrBTerm => plb_bus_Sl_wrBTerm,
Sl_wrComp => plb_bus_Sl_wrComp,
Sl_wrDAck => plb_bus_Sl_wrDAck,
Sl_MIRQ => plb_bus_Sl_MIRQ,
PLB_MIRQ => plb_bus_PLB_MIRQ(0 to 0),
PLB_ABus => plb_bus_PLB_ABus,
PLB_UABus => plb_bus_PLB_UABus,
PLB_BE => plb_bus_PLB_BE,
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0 to 0),
PLB_MTimeout => plb_bus_PLB_MTimeout(0 to 0),
PLB_MBusy => plb_bus_PLB_MBusy(0 to 0),
PLB_MRdErr => plb_bus_PLB_MRdErr(0 to 0),
PLB_MWrErr => plb_bus_PLB_MWrErr(0 to 0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0 to 0),
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0 to 0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0 to 0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0 to 0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0 to 0),
PLB_MSSize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_RNW => plb_bus_PLB_RNW,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_MSize => plb_bus_PLB_MSize,
PLB_rdPendPri => plb_bus_PLB_rdpendPri,
PLB_wrPendPri => plb_bus_PLB_wrpendPri,
PLB_rdPendReq => plb_bus_PLB_rdpendReq,
PLB_wrPendReq => plb_bus_PLB_wrpendReq,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_SMRdErr => plb_bus_PLB_SMRdErr(0 to 0),
PLB_SMWrErr => plb_bus_PLB_SMWrErr(0 to 0),
PLB_SMBusy => plb_bus_PLB_SMBusy(0 to 0),
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_Sssize => plb_bus_PLB_Sssize,
PLB_Swait => plb_bus_PLB_Swait,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB2OPB_rearb => net_gnd2,
Bus_Error_Det => open
);
my_core : my_core_wrapper
port map (
SPLB_Clk => sys_clk,
SPLB_Rst => plb_bus_SPLB_Rst(1),
PLB_ABus => plb_bus_PLB_ABus,
PLB_UABus => plb_bus_PLB_UABus,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim(1),
PLB_wrPrim => plb_bus_PLB_wrPrim(1),
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_MSize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_wrPendReq => plb_bus_PLB_wrpendReq,
PLB_rdPendReq => plb_bus_PLB_rdpendReq,
PLB_wrPendPri => plb_bus_PLB_wrpendPri,
PLB_rdPendPri => plb_bus_PLB_rdpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_TAttribute => plb_bus_PLB_TAttribute,
Sl_addrAck => plb_bus_Sl_addrAck(1),
Sl_SSize => plb_bus_Sl_SSize(2 to 3),
Sl_wait => plb_bus_Sl_wait(1),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(1),
Sl_wrDAck => plb_bus_Sl_wrDAck(1),
Sl_wrComp => plb_bus_Sl_wrComp(1),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(1),
Sl_rdDBus => plb_bus_Sl_rdDBus(128 to 255),
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr(4 to 7),
Sl_rdDAck => plb_bus_Sl_rdDAck(1),
Sl_rdComp => plb_bus_Sl_rdComp(1),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(1),
Sl_MBusy => plb_bus_Sl_MBusy(1 to 1),
Sl_MWrErr => plb_bus_Sl_MWrErr(1 to 1),
Sl_MRdErr => plb_bus_Sl_MRdErr(1 to 1),
Sl_MIRQ => plb_bus_Sl_MIRQ(1 to 1),
SYNCH_IN => synch,
SYNCH_OUT => synch3
);
end architecture STRUCTURE;
|
architecture rtl of fifo is
begin
GEN_LABEL : case expression generate
end generate;
GEN_LABEL : case expression GENERATE
end GENERATE;
end architecture;
|
entity gensub1 is
end entity;
architecture test of gensub1 is
function adder generic (n : integer) (x : integer) return integer is
begin
return x + n;
end function;
function add1 is new adder generic map (1);
signal s : integer;
begin
p1: process is
begin
assert add1(1) = 2;
s <= 5;
wait for 1 ns;
assert add1(s) = 6;
wait;
end process;
end architecture;
|
-- The MIT License (MIT)
-- Copyright (c) 2014 Shuo Li
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--------------------------
-- address generation unit
-- for N-point FFT
--------------------------
library ieee;
use ieee.std_logic_1164.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
entity agu is
generic ( address_width : integer := 8 );
port (
count_in : in std_logic_vector(address_width - 2 downto 0);
current_stage : in integer range 0 to address_width - 1;
address_out_0 : out std_logic_vector(address_width - 1 downto 0);
address_out_1 : out std_logic_vector(address_width - 1 downto 0)
);
end agu;
-- Function Implementation 0
architecture FIMP_0 of agu is
begin
process(count_in, current_stage)
begin
if current_stage = 0 then
address_out_0 <= count_in & '0';
address_out_1 <= count_in & '1';
elsif current_stage = address_width - 1 then
address_out_0 <= '0' & count_in;
address_out_1 <= '1' & count_in;
else
for i in 1 to address_width - 2 loop
if current_stage = i then
address_out_0 <= count_in(address_width-2 downto i) & '0' & count_in(i - 1 downto 0);
address_out_1 <= count_in(address_width-2 downto i) & '0' & count_in(i - 1 downto 0);
end if;
end loop;
end if;
end process;
end FIMP_0; |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests a simple counter.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity Counter_Tester is
end entity;
architecture stdarch of Counter_Tester is
--------------------
-- Constants
--------------------
constant clk_period: time := 5ns;
constant test_width: integer := 32;
constant test_delay: time := 1ns;
--------------------
-- Inputs
--------------------
signal clk: std_logic := '0';
signal reset: std_logic := '0';
signal clear: std_logic := '0';
signal counter_enable: std_logic := '0';
--------------------
-- Outputs
--------------------
signal value: unsigned(test_width-1 downto 0);
--------------------
-- Internals
--------------------
signal run_test: boolean := true;
begin
--------------------------------------------------------------------------------
-- Instantiate the UUT(s).
--------------------------------------------------------------------------------
counter: entity work.Counter
generic map
(
width => test_width
)
port map
(
clk => clk,
clear => clear,
ce => counter_enable,
value => value
);
--------------------------------------------------------------------------------
-- Generate the counter clock.
--------------------------------------------------------------------------------
clk <= not clk after clk_period/2 when run_test;
--------------------------------------------------------------------------------
-- Stimulate the UUT.
--------------------------------------------------------------------------------
stimulus: process is
variable iteration: integer := 0;
begin
-- Count for a few cycles while enabling and disabling the counter and check
-- whether the counter works properly.
wait until falling_edge(clk);
counter_enable <= '1';
wait for 5 * clk_period;
assert (value = to_unsigned(5, test_width)) report "Counter failed when enabled." severity error;
counter_enable <= '0';
wait for 5 * clk_period;
assert (value = to_unsigned(5, test_width)) report "Counter failed when disabled." severity error;
counter_enable <= '1';
wait for 5 * clk_period;
assert (value = to_unsigned(10, test_width)) report "Counter failed when re-enabled." severity error;
-- Clear synchronously and check whether we get a zero value after the next counter
-- clock cycle (but not before).
wait until falling_edge(clk);
clear <= '1';
wait for test_delay;
assert (value /= to_unsigned(0, test_width)) report "Counter cleared too early." severity error;
wait until falling_edge(clk);
assert (value = to_unsigned(0, test_width)) report "Counter not cleared." severity error;
clear <= '0';
-- Repeat the test once to verify proper continuous operation, then
-- terminate the test.
if (iteration = 0) then
counter_enable <= '0';
iteration := iteration + 1;
else
run_test <= false;
wait;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fr is
port(
clk : in std_logic;
latch : in std_logic;
inZF : in std_logic;
inSF : in std_logic;
inOF : in std_logic;
outZF : out std_logic;
outSF : out std_logic;
outOF : out std_logic
);
end fr;
architecture BEHAVIOR of fr is
-- Definitions --
signal ZFG : std_logic;
signal SFG : std_logic;
signal OFG : std_logic;
-- Main --
begin
process(clk) begin
if(clk'event and (clk = '1') and (latch = '1')) then
ZFG <= inZF;
SFG <= inSF;
OFG <= inOF;
else
null;
end if;
end process;
outZF <= ZFG;
outSF <= SFG;
outOF <= OFG;
end BEHAVIOR;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fr is
port(
clk : in std_logic;
latch : in std_logic;
inZF : in std_logic;
inSF : in std_logic;
inOF : in std_logic;
outZF : out std_logic;
outSF : out std_logic;
outOF : out std_logic
);
end fr;
architecture BEHAVIOR of fr is
-- Definitions --
signal ZFG : std_logic;
signal SFG : std_logic;
signal OFG : std_logic;
-- Main --
begin
process(clk) begin
if(clk'event and (clk = '1') and (latch = '1')) then
ZFG <= inZF;
SFG <= inSF;
OFG <= inOF;
else
null;
end if;
end process;
outZF <= ZFG;
outSF <= SFG;
outOF <= OFG;
end BEHAVIOR;
|
library ieee;
use ieee.std_logic_1164.all;
entity generic_enabler_tb is
end;
architecture generic_enabler_tb_func of generic_enabler_tb is
signal rst_in: std_logic:='1';
signal enable_out: std_logic:='0';
signal clk_in: std_logic:='0';
component generic_enabler is
generic(
PERIOD:natural := 1000000 --1MHz
);
port(
clk: in std_logic;
rst: in std_logic;
enabler_out: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 1 ns;
rst_in <= '0' after 10 ns;
generic_enablerMap: generic_enabler
generic map(6)
port map(
clk => clk_in,
rst => rst_in,
enabler_out => enable_out
);
end architecture;
|
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Receive synchronous serial data over 3 wires.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity serial_3wire_rx is
generic (
-- Data bit width
data_width_g : positive := 32);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Reception lines
rx_frame_i : in std_ulogic;
rx_bit_en_i : in std_ulogic;
rx_i : in std_ulogic;
-- Interface
data_o : out std_ulogic_vector(data_width_g - 1 downto 0);
data_en_o : out std_ulogic;
error_o : out std_ulogic);
end entity serial_3wire_rx;
architecture rtl of serial_3wire_rx is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- Using odd parity detects empty frames as errors
constant parity_init_c : std_ulogic := '1';
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal data : std_ulogic_vector(data_width_g downto 0) := (others => '0');
signal data_en : std_ulogic := '0';
signal parity : std_ulogic := parity_init_c;
signal parity_error : std_ulogic := '0';
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal frame_fedge : std_ulogic;
signal bit_en_redge : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
data_o <= data(data_width_g - 1 downto 0);
data_en_o <= data_en;
error_o <= parity_error;
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
-- Detect falling edge on rx_frame_i
frame_edge_inst : entity work.edge_detector
generic map (
init_value_g => '0',
edge_type_g => 1,
hold_flag_g => false)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => '1',
ack_i => '0',
sig_i => rx_frame_i,
edge_o => frame_fedge);
-- Detect rising edge on rx_bit_en_i
bit_en_edge_inst : entity work.edge_detector
generic map (
init_value_g => '0',
edge_type_g => 0,
hold_flag_g => false)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => '1',
ack_i => '0',
sig_i => rx_bit_en_i,
edge_o => bit_en_redge);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
data <= (others => '0');
data_en <= '0';
parity <= parity_init_c;
parity_error <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
-- Shift-in data and calculate parity on rising edges within a valid frame
if rx_frame_i = '1' and bit_en_redge = '1' then
data <= rx_i & data(data'high downto data'low + 1);
parity <= parity xor rx_i;
end if;
-- Data is valid at the end of the frame if the parity is correct
data_en <= frame_fedge and (not parity);
-- If the parity is not correct at the end of the frame, an error is reported
parity_error <= frame_fedge and parity;
-- Reset parity at the end of every frame
if frame_fedge = '1' then
parity <= parity_init_c;
end if;
end if;
end if;
end process regs;
end architecture rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity a1sComplement is
Generic
(
BITS : INTEGER := 4
);
Port
(
A : in STD_LOGIC_VECTOR (BITS-1 downto 0);
Z : out STD_LOGIC_VECTOR (BITS-1 downto 0)
);
end a1sComplement;
-------------------------------------------------------------------------
architecture Behavioral of a1sComplement is
begin
Z <= not(A);
end Behavioral;
|
-- Demonstration of a functional FSMD coding style.
entity function_fsmd is
port(
clk_i,
reset_i : in bit;
a_i, b_i : in bit;
x_o, y_o : out bit);
end;
architecture rtl of function_fsmd is
type seq_t is (idle, start, run);
type state_t is record
seq : seq_t;
x : bit;
end record;
constant reset_state_c : state_t := (
seq => idle,
x => '0');
signal r : state_t;
impure function delta(r : state_t) return state_t is
variable n : state_t := r;
begin
case r.seq is
when idle =>
if a_i = '1' then
n.seq := start;
end if;
when start =>
n.seq := run;
n.x := '1';
when run =>
if b_i = '1' then
n.seq := idle;
n.x := '0';
end if;
end case;
return n;
end;
begin
sync : process(clk_i, reset_i)
begin
if reset_i = '1' then
r <= reset_state_c;
elsif rising_edge(clk_i) then
r <= delta(r);
end if;
end process;
lambda : process(r, b_i)
begin
x_o <= r.x;
if r.seq = idle then
y_o <= b_i;
else
y_o <= '0';
end if;
end process;
end;
|
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: fwi $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2010-07-02 09:41:24 +0200 (vr, 02 jul 2010) $
-- Revision : $Revision: 531 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
--common:
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--user:
-----------
library work;
use work.all;
-----------------------
-- ENTITY DEFINITION --
-----------------------
entity syncchanneldecoder is
generic (
NROF_CONN : integer;
DATAWIDTH : integer;
NROF_WINDOWS : integer
);
port (
-- Control signals
CLOCK : in std_logic;
RESET : in std_logic;
-- Internal signaling
en_decoder : in std_logic;
--busy_decoder : out std_logic;
PAR_DATA_RDEN : out std_logic;
PAR_DATA_EMPTY : in std_logic;
PAR_DATAIN : in std_logic_vector((NROF_CONN*DATAWIDTH)-1 downto 0);
PAR_SYNCOUT : out std_logic_vector((DATAWIDTH)-1 downto 0);
PAR_DATAOUT : out std_logic_vector(((NROF_CONN-1)*DATAWIDTH)-1 downto 0);
PAR_DATA_IMGVALID : out std_logic;
PAR_DATA_BLACKVALID : out std_logic;
PAR_DATA_LINE : out std_logic;
PAR_DATA_FRAME : out std_logic;
KERNEL_ODD_EVEN : out std_logic;
START_KERNEL : out std_logic;
StartOddEven : in std_logic_vector(31 downto 0);
LS_value : in std_logic_vector(9 downto 0);
LE_value : in std_logic_vector(9 downto 0);
FS_value : in std_logic_vector(9 downto 0);
FE_value : in std_logic_vector(9 downto 0);
BL_value : in std_logic_vector(9 downto 0);
IMG_value : in std_logic_vector(9 downto 0);
TR_value : in std_logic_vector(9 downto 0);
CRC_value : in std_logic_vector(9 downto 0);
-- synchro signals
framestart : out std_logic;
windowstart : out std_logic;
windowend : out std_logic;
linestart : out std_logic;
lineend : out std_logic;
blacklinestart : out std_logic;
blacklineend : out std_logic;
imagelinestart : out std_logic;
imagelineend : out std_logic;
validcrc : out std_logic;
-- counters
FramesCnt : out std_logic_vector(31 downto 0);
-- lines/frame counter
BlackLinesCnt : out std_logic_vector(31 downto 0);
ImgLinesCnt : out std_logic_vector(31 downto 0);
-- pixels/frame counter
BlackPixelCnt : out std_logic_vector(31 downto 0);
ImgPixelCnt : out std_logic_vector(31 downto 0);
-- windows/frame counter
WindowsCnt : out std_logic_vector(31 downto 0);
-- clocks/frame counter -> fps
ClocksCnt : out std_logic_vector(31 downto 0);
StartLineCnt : out std_logic_vector(31 downto 0);
EndLineCnt : out std_logic_vector(31 downto 0);
-- monitors
MONITOR : in std_logic_vector(1 downto 0);
Monitor0HighCnt : out std_logic_vector(31 downto 0);
Monitor0LowCnt : out std_logic_vector(31 downto 0);
Monitor1HighCnt : out std_logic_vector(31 downto 0);
Monitor1LowCnt : out std_logic_vector(31 downto 0)
);
end syncchanneldecoder;
---------------------------
-- BEHAVIOUR DESCRIPTION --
---------------------------
architecture rtl of syncchanneldecoder is
alias SyncChannel : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAIN((DATAWIDTH-1) downto 0);
alias DataChannels : std_logic_vector(((NROF_CONN-1)*DATAWIDTH-1) downto 0) is PAR_DATAIN((NROF_CONN*DATAWIDTH-1) downto DATAWIDTH);
--debug only
--inp
alias DataChannel0 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAIN((DATAWIDTH-1)+1*DATAWIDTH downto 1*DATAWIDTH);
alias DataChannel1 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAIN((DATAWIDTH-1)+2*DATAWIDTH downto 2*DATAWIDTH);
alias DataChannel2 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAIN((DATAWIDTH-1)+3*DATAWIDTH downto 3*DATAWIDTH);
alias DataChannel3 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAIN((DATAWIDTH-1)+4*DATAWIDTH downto 4*DATAWIDTH);
--outp
alias ParOutChannel0 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAOUT((DATAWIDTH-1)+0*DATAWIDTH downto 0*DATAWIDTH);
alias ParOutChannel1 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAOUT((DATAWIDTH-1)+1*DATAWIDTH downto 1*DATAWIDTH);
alias ParOutChannel2 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAOUT((DATAWIDTH-1)+2*DATAWIDTH downto 2*DATAWIDTH);
alias ParOutChannel3 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAOUT((DATAWIDTH-1)+3*DATAWIDTH downto 3*DATAWIDTH);
type SyncDelayPipetp is array (0 to 5) of std_logic_vector((DATAWIDTH-1) downto 0);
signal SyncDelayPipe : SyncDelayPipetp;
type DataDelayPipetp is array (0 to SyncDelayPipe'high) of std_logic_vector(((NROF_CONN-1)*DATAWIDTH-1) downto 0);
signal DataDelayPipe : DataDelayPipetp;
signal DataValidPipe : std_logic_vector(0 to 5);
constant zeros : std_logic_vector((DATAWIDTH-1) downto 0) := (others => '0');
--signal extstartframe : std_logic;
--signal intstartframe : std_logic;
signal startframe : std_logic;
signal startwindow : std_logic;
signal endwindow : std_logic;
signal startwindowid : std_logic_vector(1023 downto 0);
signal endwindowid : std_logic_vector(1023 downto 0);
signal windowid : std_logic_vector((DATAWIDTH-1) downto 0);
signal startline : std_logic;
signal endline : std_logic;
signal startblackline : std_logic;
signal endblackline : std_logic;
signal startimageline : std_logic;
signal endimageline : std_logic;
signal blackdatavalid : std_logic;
signal imgdatavalid : std_logic;
signal datavalid : std_logic;
signal crcvalid : std_logic;
signal en_valid : std_logic;
--signal firststartframe : std_logic;
--signal nextstartframe : std_logic;
signal StartLineCntr : std_logic_vector(31 downto 0);
signal EndLineCntr : std_logic_vector(31 downto 0);
signal rst_cntrs : std_logic;
signal decode : std_logic;
--signal dec : std_logic;
signal enpipe : std_logic_vector(15 downto 0);
signal syncvalid : std_logic;
signal syncvalid_r : std_logic;
-- framescounter
signal FramesCntr : std_logic_vector(31 downto 0);
-- lines/frame counter
signal BlackLinesCntr : std_logic_vector(31 downto 0);
signal ImgLinesCntr : std_logic_vector(31 downto 0);
-- pixels/frame counter
signal BlackPixelCntr : std_logic_vector(31 downto 0);
signal ImgPixelCntr : std_logic_vector(31 downto 0);
-- windows/frame counter
signal WindowsCntr : std_logic_vector(31 downto 0);
-- clocks/frame counter -> fps
signal ClocksCntr : std_logic_vector(31 downto 0);
--signal ClocksCnt : std_logic_vector(31 downto 0);
type DataStatetp is (
Idle,
Valid
);
signal BlackDataState : DataStatetp;
signal ImgDataState : DataStatetp;
type DecoderEnablerStatetp is (
Idle,
DetectEnableStart,
--DetectFirstFrameStart,
Enabled
);
signal DecoderEnablerState : DecoderEnablerStatetp;
type blacklinecntstatetp is (
WaitFirstBlackLine,
CountBlackLines
);
signal blacklinecntstate : blacklinecntstatetp;
signal Monitor0HighCntr : std_logic_vector(31 downto 0);
signal Monitor0LowCntr : std_logic_vector(31 downto 0);
signal Monitor1HighCntr : std_logic_vector(31 downto 0);
signal Monitor1LowCntr : std_logic_vector(31 downto 0);
signal monitor_rising : std_logic_vector(1 downto 0);
signal monitor_falling : std_logic_vector(1 downto 0);
type Monitor_synctp is array (2 downto 0) of std_logic_vector(1 downto 0);
signal Monitor_sync : Monitor_synctp;
begin
PAR_DATA_RDEN <= enpipe(4);
en_valid <= enpipe(15) and en_decoder;
syncvalid <= not PAR_DATA_EMPTY;
syncvalid_r <= DataValidPipe(0);
EnPipePr: process(RESET, CLOCK)
begin
if (RESET = '1') then
enpipe <= (others => '0');
elsif (CLOCK'event and CLOCK = '1') then
enpipe(0) <= en_decoder;
for i in 0 to enpipe'high-1 loop
enpipe(i+1) <= enpipe(i);
end loop;
end if;
end process;
DataPipe: process(RESET, CLOCK)
begin
if (RESET = '1') then
SyncDelayPipe <= (others => (others => '0'));
PAR_SYNCOUT <= (others => '0');
-- DataDelayPipe doesnt need reset state
DataValidPipe <= (others => '0');
PAR_DATA_LINE <= '0';
PAR_DATA_FRAME <= '0';
elsif (CLOCK'event and CLOCK = '1') then
PAR_DATA_LINE <= (startimageline or startblackline) and syncvalid_r; --needs one cycle delay
PAR_DATA_FRAME <= startframe and syncvalid_r;
if (PAR_DATA_EMPTY = '0') then
SyncDelayPipe(0) <= SyncChannel;
DataDelayPipe(0) <= DataChannels;
for i in 0 to (SyncDelayPipe'high-1) loop
SyncDelayPipe(i+1) <= SyncDelayPipe(i);
DataDelayPipe(i+1) <= DataDelayPipe(i);
end loop;
end if;
PAR_DATAOUT <= DataDelayPipe(3);
PAR_SYNCOUT <= SyncDelayPipe(3);
for i in 0 to (DataValidPipe'high-1) loop
DataValidPipe(i+1) <= DataValidPipe(i);
end loop;
DataValidPipe(0) <= not PAR_DATA_EMPTY;
end if;
end process;
PAR_DATA_IMGVALID <= imgdatavalid and DataValidPipe(1);
PAR_DATA_BLACKVALID <= blackdatavalid and DataValidPipe(1);
framestart <= startframe;
windowstart <= startwindow;
windowend <= endwindow;
linestart <= startline;
lineend <= endline;
blacklinestart <= startblackline;
blacklineend <= endblackline;
imagelinestart <= startimageline;
imagelineend <= endimageline;
validcrc <= crcvalid and DataValidPipe(1);
-- counters
FramesCnt <= FramesCntr;
-- lines/frame count
BlackLinesCnt <= BlackLinesCntr;
ImgLinesCnt <= ImgLinesCntr;
-- pixels/frame count
BlackPixelCnt <= BlackPixelCntr;
ImgPixelCnt <= ImgPixelCntr;
-- windows/frame count
WindowsCnt <= WindowsCntr;
--
StartLineCnt <= StartLineCntr;
EndLineCnt <= EndLineCntr;
--extstartframe <= nextstartframe or firststartframe;
Decoder: process(RESET, CLOCK)
begin
if (RESET = '1') then
startframe <= '0';
startwindow <= '0';
endwindow <= '0';
startline <= '0';
startblackline <= '0';
startimageline <= '0';
endline <= '0';
endblackline <= '0';
endimageline <= '0';
datavalid <= '0';
blackdatavalid <= '0';
imgdatavalid <= '0';
crcvalid <= '0';
-- StartFrameState <= Idle;
BlackDataState <= Idle;
windowid <= (others => '0');
startwindowid <= (others => '0');
endwindowid <= (others => '0');
-- firststartframe <= '0';
-- nextstartframe <= '0';
decode <= '0';
elsif (CLOCK'event and CLOCK = '1') then
-- detect framestart by:
-- 1. first looking for a linestart from a blackline
-- 2. then look for the first framestart available
--framedetection for decoder enabler
-- startframe is detected 2 clks before internal startframe, should be enough
--firststartframe <= '0';
if (en_valid = '1') then
--if (syncvalid = '1') then
case DecoderEnablerState is
when Idle =>
decode <= '0';
if (SyncDelayPipe(2) = LS_value(9 downto (10-DATAWIDTH)) and SyncDelayPipe(0) = BL_value(9 downto (10-DATAWIDTH))) then
DecoderEnablerState <= DetectEnableStart;
end if;
when DetectEnableStart =>
if (SyncDelayPipe(0) = FS_value(9 downto (10-DATAWIDTH))) then
decode <= '1';
--firststartframe <= '1';
DecoderEnablerState <= Enabled;
end if;
when Enabled =>
decode <= '1';
when others =>
DecoderEnablerState <= Idle;
end case;
--end if;
else
decode <= '0';
DecoderEnablerState <= Idle;
end if;
if (decode = '1') then
startframe <= '0';
if (SyncDelayPipe(2) = FS_value(9 downto (10-DATAWIDTH)) and SyncDelayPipe(1) = zeros(9 downto (10-DATAWIDTH) )) then
startframe <= '1';
end if;
else
startframe <= '0';
end if;
-- frameend detect, not feasible without software...
--start window detection
if (decode = '1') then
startwindow <= '0';
startwindowid <= (others => '0');
if (SyncDelayPipe(2) = FS_value(9 downto (10-DATAWIDTH))) then
startwindow <= '1';
startwindowid( TO_INTEGER(UNSIGNED(SyncDelayPipe(1))) ) <= '1';
windowid <= SyncDelayPipe(1);
end if;
else
startwindow <= '0';
startwindowid <= (others => '0');
end if;
--end window detection
if (decode = '1') then
endwindow <= '0';
endwindowid <= (others => '0');
if (SyncDelayPipe(4) = FE_value(9 downto (10-DATAWIDTH))) then
endwindow <= '1';
endwindowid(TO_INTEGER(UNSIGNED(SyncDelayPipe(3))) ) <= '1';
end if;
else
endwindowid <= (others => '0');
endwindow <= '0';
end if;
-- start line pulse generation
--startline is detected every startline code passes
if (decode = '1') then
startline <= '0';
if (SyncDelayPipe(2) = LS_value(9 downto (10-DATAWIDTH))) then
startline <= '1';
end if;
else
startline <= '0';
end if;
--startblackline is detected after every combination of LS + dontcare + BL
if (decode = '1') then
startblackline <= '0';
if (SyncDelayPipe(2) = LS_value(9 downto (10-DATAWIDTH)) and SyncDelayPipe(0) = BL_value(9 downto (10-DATAWIDTH))) then
startblackline <= '1';
end if;
else
startblackline <= '0';
end if;
--startimageline is detected after either:
-- 1. LS + dontcare + IMG (a normal line without a funny windowing exception)
-- 2. LS + LS + dontcare (2 linestarts right after eachother -> 2 startimagelines will be detected)
-- 3. LS + dontcare + LS (2 linestarts almost right after eachother -> 2 startimagelines will be detected
-- 4. in theory 3 linestarts could follow eachother, this is not supported for now.
-- 5. the same with FS in place of LS (ignore MSB)
-- note: case 2 and case 4 are probably not possible
if (decode = '1') then
startimageline <= '0';
if ((SyncDelayPipe(2)(DATAWIDTH-2 downto 0) = LS_value(8 downto (10-DATAWIDTH)) and SyncDelayPipe(0) = IMG_value(9 downto (10-DATAWIDTH))) or
(SyncDelayPipe(2)(DATAWIDTH-2 downto 0) = LS_value(8 downto (10-DATAWIDTH)) and SyncDelayPipe(1)(DATAWIDTH-2 downto 0) = LS_value(8 downto (10-DATAWIDTH))) or
(SyncDelayPipe(2)(DATAWIDTH-2 downto 0) = LS_value(8 downto (10-DATAWIDTH)) and SyncDelayPipe(0)(DATAWIDTH-2 downto 0) = LS_value(8 downto (10-DATAWIDTH)))
) then
startimageline <= '1';
end if;
else
startimageline <= '0';
end if;
-- end line pulse generation
-- endline is detected every endline code passes
if (decode = '1') then
endline <= '0';
if (SyncDelayPipe(4) = LE_value(9 downto (10-DATAWIDTH))) then
endline <= '1';
end if;
else
endline <= '0';
end if;
-- endblackline is detected after BL + LE
if (decode = '1') then
endblackline <= '0';
if (SyncDelayPipe(5) = BL_value(9 downto (10-DATAWIDTH)) and SyncDelayPipe(4) = LE_value(9 downto (10-DATAWIDTH))) then
endblackline <= '1';
end if;
else
endblackline <= '0';
end if;
-- endimageline is detected after either
-- 1. IMG + LE
-- 2. LE + LE
-- 3 the same with frameend
if (decode = '1') then
endimageline <= '0';
if (SyncDelayPipe(5) = IMG_value(9 downto (10-DATAWIDTH)) and SyncDelayPipe(4)(DATAWIDTH-2 downto 0) = LE_value(8 downto (10-DATAWIDTH))) or
(SyncDelayPipe(5)(DATAWIDTH-2 downto 0) = LE_value(8 downto (10-DATAWIDTH)) and SyncDelayPipe(4)(DATAWIDTH-2 downto 0) = LE_value(8 downto (10-DATAWIDTH)))
then
endimageline <= '1';
end if;
else
endimageline <= '0';
end if;
-- data valid generation
-- simple valid data, independant of black or img
-- always valid except when TR and CRC are present
datavalid <= '0';
if (decode = '1') then
if (SyncDelayPipe(3) = TR_value(9 downto (10-DATAWIDTH)) or
SyncDelayPipe(3) = CRC_value(9 downto (10-DATAWIDTH))
) then
datavalid <= '0';
else
datavalid <= '1';
end if;
end if;
--black data valid
-- black lines are non overlapping with other windows -> all blackline start/ blackline end pulses should be present
if (decode = '1') then
case BlackDataState is
when Idle =>
if (startblackline = '1' and syncvalid_r = '1') then
blackdatavalid <= '1';
BlackDataState <= Valid;
else
blackdatavalid <= '0';
end if;
when Valid =>
if (endblackline = '1' and syncvalid_r = '1') then
blackdatavalid <= '0';
BlackDataState <= Idle;
else
blackdatavalid <= '1';
end if;
end case;
else
blackdatavalid <= '0';
BlackDataState <= Idle;
end if;
-- image data valid -> valid data and not black data = img data
--img data valid
--imgdatavalid <= datavalid and not blackdatavalid;
if (decode = '1') then
case ImgDataState is
when Idle =>
if (startimageline = '1' and syncvalid_r = '1') then
imgdatavalid <= '1';
ImgDataState <= Valid;
else
imgdatavalid <= '0';
end if;
when Valid =>
if (endimageline = '1' and startimageline = '0' and syncvalid_r = '1') then
imgdatavalid <= '0';
ImgDataState <= Idle;
else
imgdatavalid <= '1';
end if;
end case;
else
imgdatavalid <= '0';
ImgDataState <= Idle;
end if;
-- CRC
if (decode = '1') then
crcvalid <= '0';
if (SyncDelayPipe(3) = CRC_value(9 downto (10-DATAWIDTH))) then
crcvalid <= '1';
end if;
else
crcvalid <= '0';
end if;
end if;
end process;
Counters: process(RESET, CLOCK)
begin
if (RESET = '1') then
StartLineCntr <= (others => '0');
EndLineCntr <= (others => '0');
rst_cntrs <= '0';
FramesCntr <= (others => '0');
BlackLinesCntr <= (others => '0');
ImgLinesCntr <= (others => '0');
BlackPixelCntr <= (others => '0');
ImgPixelCntr <= (others => '0');
WindowsCntr <= (others => '0');
ClocksCntr <= (others => '0');
ClocksCnt <= (others => '0');
elsif (CLOCK'event and CLOCK = '1') then
-- counter rst logic
if (enpipe(0) = '1' and enpipe(1) = '0') then --rising edge
rst_cntrs <= '1';
else
rst_cntrs <= '0';
end if;
-- startlinecounter (/readout) (including black lines)
if (rst_cntrs = '1' ) then
StartLineCntr <= (others => '0');
EndLineCntr <= (others => '0');
else
if (syncvalid_r = '1') then
if (startline = '1' and decode = '1') then
StartLineCntr <= StartLineCntr + '1';
end if;
if (endline = '1' and decode = '1') then
EndLineCntr <= EndLineCntr + '1';
end if;
end if;
end if;
-- framescounter
if (rst_cntrs = '1') then
FramesCntr <= (others => '0');
else
if (syncvalid_r = '1') then
if (startframe = '1' and decode = '1') then
FramesCntr <= FramesCntr + '1';
end if;
end if;
end if;
-- lines/frame counter
-- counts total amount of blacklines
if (rst_cntrs = '1') then
BlackLinesCntr <= (others => '0');
blacklinecntstate <= WaitFirstBlackLine;
else
if (syncvalid_r = '1') then
case blacklinecntstate is
when WaitFirstBlackLine =>
if (startblackline = '1') then
BlackLinesCntr <= X"00000001";
blacklinecntstate <= CountBlackLines;
end if;
when CountBlackLines =>
if (startblackline = '1') then
BlackLinesCntr <= BlackLinesCntr + '1';
elsif (startimageline = '1') then
blacklinecntstate <= WaitFirstBlackLine;
end if;
when others =>
blacklinecntstate <= WaitFirstBlackLine;
end case;
end if;
end if;
if (rst_cntrs = '1' or (startframe = '1' and decode = '1')) then
ImgLinesCntr <= (others => '0');
else
if (syncvalid_r = '1' and decode = '1') then
if (startimageline = '1') then
ImgLinesCntr <= ImgLinesCntr + '1';
end if;
end if;
end if;
-- pixels/frame counter
if (rst_cntrs = '1' or startblackline = '1') then
BlackPixelCntr <= (others => '0');
else
if (syncvalid_r = '1') then
if (blackdatavalid = '1') then
BlackPixelCntr <= BlackPixelCntr + '1';
end if;
end if;
end if;
if (rst_cntrs = '1' or (startimageline = '1' and decode = '1')) then
ImgPixelCntr <= (others => '0');
else
if (syncvalid_r = '1' and decode = '1') then
if (imgdatavalid = '1') then
ImgPixelCntr <= ImgPixelCntr + '1';
end if;
end if;
end if;
-- windows/frame counter
if (rst_cntrs = '1') then
WindowsCntr <= (others => '0');
elsif (startframe = '1' and decode = '1') then --equal to the first window start
WindowsCntr <= X"00000001";
else
if (syncvalid_r = '1' and decode = '1') then
if (startwindow = '1') then
WindowsCntr <= WindowsCntr + '1';
end if;
end if;
end if;
-- clocks/frame counter -> fps
if (startframe = '1' and syncvalid_r = '1') then
ClocksCntr <= (others => '0');
ClocksCnt <= ClocksCntr;
else
ClocksCntr <= ClocksCntr + '1';
end if;
end if;
end process;
-- should run sync to data
Odd_Even_indication: process(RESET, CLOCK)
begin
if (RESET = '1') then
KERNEL_ODD_EVEN <= '0';
START_KERNEL <= '0';
elsif(CLOCK = '1' and CLOCK'event) then
START_KERNEL <= '0';
if (startwindow = '1') then
KERNEL_ODD_EVEN <= StartOddEven(to_integer(unsigned(windowid(4 downto 0))));
START_KERNEL <= '1';
end if;
end if;
end process;
-- monitor parser
-- also used for lightsource triggering
monitor_parser: process(RESET, CLOCK)
begin
if (RESET = '1') then
Monitor0HighCntr <= (others => '0');
Monitor0LowCntr <= (others => '0');
Monitor1HighCntr <= (others => '0');
Monitor1LowCntr <= (others => '0');
Monitor0HighCnt <= (others => '0');
Monitor0LowCnt <= (others => '0');
Monitor1HighCnt <= (others => '0');
Monitor1LowCnt <= (others => '0');
for i in 0 to 1 loop
monitor_rising(i) <= '0';
monitor_falling(i) <= '0';
end loop;
Monitor_sync <= (others => (others => '0'));
elsif(CLOCK = '1' and CLOCK'event) then
--defaults
Monitor_sync(0)(0) <= MONITOR(0);
Monitor_sync(0)(1) <= MONITOR(1);
for i in 0 to (Monitor_sync'high - 1) loop
Monitor_sync(i+1) <= Monitor_sync(i);
end loop;
-- monitor counters
for i in 0 to 1 loop
--defaults
monitor_rising(i) <= '0';
monitor_falling(i) <= '0';
if (decode = '1') then
if (Monitor_sync(2)(i) = '0' and Monitor_sync(1)(i) = '1') then --rising edge
monitor_rising(i) <= '1';
elsif (Monitor_sync(2)(0) = '1' and Monitor_sync(1)(i) = '0') then --falling edge
monitor_falling(i) <= '1';
end if;
end if;
end loop;
if (decode = '1') then
if (monitor_rising(0) = '1') then
Monitor0HighCnt <= Monitor0HighCntr;
Monitor0HighCntr <= (others => '0');
elsif (Monitor_sync(2)(0) = '1') then
Monitor0HighCntr <= Monitor0HighCntr + '1';
end if;
if (monitor_falling(0) = '1') then
Monitor0LowCnt <= Monitor0LowCntr;
Monitor0LowCntr <= (others => '0');
elsif (Monitor_sync(2)(0) = '0') then
Monitor0LowCntr <= Monitor0LowCntr + '1';
end if;
if (monitor_rising(1) = '1') then
Monitor1HighCnt <= Monitor1HighCntr;
Monitor1HighCntr <= (others => '0');
elsif (Monitor_sync(2)(1) = '1') then
Monitor1HighCntr <= Monitor1HighCntr + '1';
end if;
if (monitor_falling(1) = '1') then
Monitor1LowCnt <= Monitor1LowCntr;
Monitor1LowCntr <= (others => '0');
elsif (Monitor_sync(2)(1) = '0') then
Monitor1LowCntr <= Monitor1LowCntr + '1';
end if;
end if;
end if;
end process;
end rtl;
|
globalcnt_inst : globalcnt PORT MAP (
clock => clock_sig,
cout => cout_sig,
q => q_sig
);
|
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- barrel_bit_shifter.vhd: Barrel shifter with generic data width
-- Copyright (C) 2010 CESNET
-- Author(s): Viktor Pus <pus@liberouter.org>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: barrel_bit_shifter.vhd 13189 2010-03-10 15:07:35Z pus $
--
-- TODO:
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- ENTITY DECLARATION -- Barrel shifter --
-- ----------------------------------------------------------------------------
entity BARREL_BIT_SHIFTER is
generic (
DATA_WIDTH : integer := 8;
-- set true to shift left, false to shift right
SHIFT_LEFT : boolean := true
);
port (
-- Input interface ------------------------------------------------------
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
SEL : in std_logic_vector(log2(DATA_WIDTH)-1 downto 0)
);
end BARREL_BIT_SHIFTER;
-- ----------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION --
-- ----------------------------------------------------------------------------
architecture barrel_bit_shifter_arch of BARREL_BIT_SHIFTER is
begin
multiplexors: for i in 0 to DATA_WIDTH-1 generate
process (DATA_IN, SEL)
variable sel_aux: integer;
begin
if (SHIFT_LEFT) then
sel_aux := conv_integer('0'&SEL);
else
sel_aux := conv_integer('0'&(0-SEL));
end if;
DATA_OUT(i) <= DATA_IN((DATA_WIDTH-sel_aux+i) mod (DATA_WIDTH));
end process;
end generate;
end barrel_bit_shifter_arch;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Module: Debounce module for BITS many bouncing input pins.
--
-- Description:
-- ------------------------------------
-- This module debounces several input pins preventing input changes
-- following a previous one within the configured BOUNCE_TIME to pass.
-- Internally, the forwarded state is locked for, at least, this BOUNCE_TIME.
-- As the backing timer is restarted on every input fluctuation, the next
-- passing input update must have seen a stabilized input.
--
-- The parameter COMMON_LOCK uses a single internal timer for all processed
-- inputs. Thus, all inputs must stabilize before any one may pass changed.
-- This option is usually fully acceptable for user inputs such as push buttons.
--
-- The parameter ADD_INPUT_SYNCHRONIZERS triggers the optional instantiation
-- of a two-FF input synchronizer on each input bit.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
entity io_Debounce is
generic (
CLOCK_FREQ : freq;
BOUNCE_TIME : time;
BITS : positive := 1;
ADD_INPUT_SYNCHRONIZERS : boolean := true;
COMMON_LOCK : boolean := false
);
port (
Clock : in std_logic;
Reset : in std_logic := '0';
Input : in std_logic_vector(BITS-1 downto 0);
Output : out std_logic_vector(BITS-1 downto 0)
);
end;
architecture rtl of io_Debounce is
-- Number of required locking cycles
constant LOCK_COUNT_X : integer := TimingToCycles(BOUNCE_TIME, CLOCK_FREQ) - 1;
-- Input Refinements
signal sync : std_logic_vector(Input'range); -- Synchronized
signal prev : std_logic_vector(Input'range) := (others => '0'); -- Delayed
signal active : std_logic_vector(Input'range); -- Allow Output Updates
begin
-----------------------------------------------------------------------------
-- Input Synchronization
genNoSync: if not ADD_INPUT_SYNCHRONIZERS generate
sync <= Input;
end generate;
genSync: if ADD_INPUT_SYNCHRONIZERS generate
sync_i : entity PoC.sync_Bits
generic map (
BITS => BITS
)
port map (
Clock => Clock, -- Clock to be synchronized to
Input => Input, -- Data to be synchronized
Output => sync -- synchronised data
);
end generate;
-----------------------------------------------------------------------------
-- Bounce Filter
process(Clock)
begin
if rising_edge(Clock) then
prev <= sync;
if (Reset = '1') then
Output <= sync;
else
for i in Output'range loop
if active(i) = '1' then
Output(i) <= sync(i);
end if;
end loop;
end if;
end if;
end process;
genNoLock: if LOCK_COUNT_X <= 0 generate
active <= (others => '1');
end generate genNoLock;
genLock: if LOCK_COUNT_X > 0 generate
constant LOCKS : positive := ite(COMMON_LOCK, 1, BITS);
signal toggle : std_logic_vector(LOCKS-1 downto 0);
signal locked : std_logic_vector(LOCKS-1 downto 0);
begin
genOneLock: if COMMON_LOCK generate
toggle(0) <= '1' when prev /= sync else '0';
active <= (others => not locked(0));
end generate genOneLock;
genManyLocks: if not COMMON_LOCK generate
toggle <= prev xor sync;
active <= not locked;
end generate genManyLocks;
genLocks: for i in 0 to LOCKS-1 generate
signal Lock : signed(log2ceil(LOCK_COUNT_X+1) downto 0) := (others => '0');
begin
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Lock <= (others => '0');
else
if toggle(i) = '1' then
Lock <= to_signed(-LOCK_COUNT_X, Lock'length);
elsif locked(i) = '1' then
Lock <= Lock + 1;
end if;
end if;
end if;
end process;
locked(i) <= Lock(Lock'left);
end generate genLocks;
end generate genLock;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Module: Debounce module for BITS many bouncing input pins.
--
-- Description:
-- ------------------------------------
-- This module debounces several input pins preventing input changes
-- following a previous one within the configured BOUNCE_TIME to pass.
-- Internally, the forwarded state is locked for, at least, this BOUNCE_TIME.
-- As the backing timer is restarted on every input fluctuation, the next
-- passing input update must have seen a stabilized input.
--
-- The parameter COMMON_LOCK uses a single internal timer for all processed
-- inputs. Thus, all inputs must stabilize before any one may pass changed.
-- This option is usually fully acceptable for user inputs such as push buttons.
--
-- The parameter ADD_INPUT_SYNCHRONIZERS triggers the optional instantiation
-- of a two-FF input synchronizer on each input bit.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
entity io_Debounce is
generic (
CLOCK_FREQ : freq;
BOUNCE_TIME : time;
BITS : positive := 1;
ADD_INPUT_SYNCHRONIZERS : boolean := true;
COMMON_LOCK : boolean := false
);
port (
Clock : in std_logic;
Reset : in std_logic := '0';
Input : in std_logic_vector(BITS-1 downto 0);
Output : out std_logic_vector(BITS-1 downto 0)
);
end;
architecture rtl of io_Debounce is
-- Number of required locking cycles
constant LOCK_COUNT_X : integer := TimingToCycles(BOUNCE_TIME, CLOCK_FREQ) - 1;
-- Input Refinements
signal sync : std_logic_vector(Input'range); -- Synchronized
signal prev : std_logic_vector(Input'range) := (others => '0'); -- Delayed
signal active : std_logic_vector(Input'range); -- Allow Output Updates
begin
-----------------------------------------------------------------------------
-- Input Synchronization
genNoSync: if not ADD_INPUT_SYNCHRONIZERS generate
sync <= Input;
end generate;
genSync: if ADD_INPUT_SYNCHRONIZERS generate
sync_i : entity PoC.sync_Bits
generic map (
BITS => BITS
)
port map (
Clock => Clock, -- Clock to be synchronized to
Input => Input, -- Data to be synchronized
Output => sync -- synchronised data
);
end generate;
-----------------------------------------------------------------------------
-- Bounce Filter
process(Clock)
begin
if rising_edge(Clock) then
prev <= sync;
if (Reset = '1') then
Output <= sync;
else
for i in Output'range loop
if active(i) = '1' then
Output(i) <= sync(i);
end if;
end loop;
end if;
end if;
end process;
genNoLock: if LOCK_COUNT_X <= 0 generate
active <= (others => '1');
end generate genNoLock;
genLock: if LOCK_COUNT_X > 0 generate
constant LOCKS : positive := ite(COMMON_LOCK, 1, BITS);
signal toggle : std_logic_vector(LOCKS-1 downto 0);
signal locked : std_logic_vector(LOCKS-1 downto 0);
begin
genOneLock: if COMMON_LOCK generate
toggle(0) <= '1' when prev /= sync else '0';
active <= (others => not locked(0));
end generate genOneLock;
genManyLocks: if not COMMON_LOCK generate
toggle <= prev xor sync;
active <= not locked;
end generate genManyLocks;
genLocks: for i in 0 to LOCKS-1 generate
signal Lock : signed(log2ceil(LOCK_COUNT_X+1) downto 0) := (others => '0');
begin
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Lock <= (others => '0');
else
if toggle(i) = '1' then
Lock <= to_signed(-LOCK_COUNT_X, Lock'length);
elsif locked(i) = '1' then
Lock <= Lock + 1;
end if;
end if;
end if;
end process;
locked(i) <= Lock(Lock'left);
end generate genLocks;
end generate genLock;
end;
|
library verilog;
use verilog.vl_types.all;
entity EX is
port(
PC_ID_EX_out : in vl_logic_vector(31 downto 0);
PC_IF_ID : in vl_logic_vector(31 downto 0);
ExResultSrc : in vl_logic_vector(1 downto 0);
ALUSrcA : in vl_logic;
ALUSrcB : in vl_logic;
ALUOp : in vl_logic_vector(3 downto 0);
RegDst : in vl_logic_vector(1 downto 0);
ShiftAmountSrc : in vl_logic;
ShiftOp : in vl_logic_vector(1 downto 0);
A_in : in vl_logic_vector(31 downto 0);
B_in : in vl_logic_vector(31 downto 0);
Rs : in vl_logic_vector(4 downto 0);
Rt : in vl_logic_vector(4 downto 0);
Rd : in vl_logic_vector(4 downto 0);
Imm32 : in vl_logic_vector(31 downto 0);
Shamt : in vl_logic_vector(4 downto 0);
A_in_sel : in vl_logic_vector(7 downto 0);
B_in_sel : in vl_logic_vector(7 downto 0);
WBData_Mem : in vl_logic_vector(31 downto 0);
Data : in vl_logic_vector(31 downto 0);
Branch_Addr : out vl_logic_vector(31 downto 0);
WBData_EX : out vl_logic_vector(31 downto 0);
MemData : out vl_logic_vector(31 downto 0);
A : out vl_logic_vector(31 downto 0);
Less : out vl_logic;
Zero : out vl_logic;
Overflow : out vl_logic;
Rd_Dst : out vl_logic_vector(4 downto 0);
ALU_A : out vl_logic_vector(31 downto 0);
ALU_B : out vl_logic_vector(31 downto 0)
);
end EX;
|
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: onchip_memory.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY onchip_memory IS
PORT
(
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END onchip_memory;
ARCHITECTURE SYN OF onchip_memory IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 16384,
numwords_b => 16384,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => 14,
widthad_b => 14,
width_a => 16,
width_b => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
address_b => rdaddress,
clock0 => clock,
data_a => data,
wren_a => wren,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "262144"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 14 0 INPUT NODEFVAL "rdaddress[13..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 14 0 INPUT NODEFVAL "wraddress[13..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 14 0 wraddress 0 0 14 0
-- Retrieval info: CONNECT: @address_b 0 0 14 0 rdaddress 0 0 14 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL onchip_memory.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL onchip_memory.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL onchip_memory.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL onchip_memory.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL onchip_memory_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- ************************************
-- Automatically Generated FSM
-- mergesort
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity bubblesort is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32
);
port
(
array0_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
array0_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
array0_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
array0_rENA0 : out std_logic;
array0_wENA0 : out std_logic;
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity bubblesort;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of bubblesort is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
idle,
decode,
dispatch,
begin_sort,
halt,
extra1,
for_loop,
extra2,
cond_check,
cond_body
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal swapped, swapped_next : std_logic;
signal n, n_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal n_new, n_new_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal i, i_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal data1, data1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal data2, data2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal arg1, arg1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal arg2, arg2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
-- ************************
-- BRAM implementations
-- ************************
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
swapped_next,
n_next,
n_new_next,
i_next,
data1_next,
data2_next,
arg1_next,
arg2_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
swapped <= '0';
n <= (others => '0');
n_new <= (others => '0');
i <= (others => '0');
data1 <= (others => '0');
data2 <= (others => '0');
arg1 <= (others => '0');
arg2 <= (others => '0');
current_state <= reset;
else
-- Transition to next state
swapped <= swapped_next;
n <= n_next;
n_new <= n_new_next;
i <= i_next;
data1 <= data1_next;
data2 <= data2_next;
arg1 <= arg1_next;
arg2 <= arg2_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
array0_dOUT0,
chan1_channelDataOut, chan1_full, chan1_exists,
swapped,
n,
n_new,
i,
data1,
data2,
arg1,
arg2,
current_state) is
begin
-- Default signal assignments
swapped_next <= swapped;
n_next <= n;
n_new_next <= n_new;
i_next <= i;
data1_next <= data1;
data2_next <= data2;
arg1_next <= arg1;
arg2_next <= arg2;
array0_addr0 <= (others => '0');
array0_dIN0 <= (others => '0');
array0_rENA0 <= '0';
array0_wENA0 <= '0';
chan1_channelDataIn <= (others => '0');
chan1_channelRead <= '0';
chan1_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when begin_sort =>
if ( swapped = '0' ) then
next_state <= halt;
elsif ( swapped = '1' ) then
array0_addr0 <= arg1;
array0_rENA0 <= '1';
next_state <= extra1;
end if;
when cond_body =>
i_next <= i + 1;
swapped_next <= '1';
n_new_next <= i;
array0_addr0 <= i + 1;
array0_dIN0 <= data1;
array0_wENA0 <= '1';
array0_rENA0 <= '1';
next_state <= for_loop;
when cond_check =>
if ( data1 <= data2 ) then
i_next <= i + 1;
data1_next <= data2;
next_state <= for_loop;
elsif ( data1 > data2 ) then
array0_addr0 <= i;
array0_dIN0 <= data2;
array0_wENA0 <= '1';
array0_rENA0 <= '1';
next_state <= cond_body;
end if;
when decode =>
arg2_next <= "00000000000000000" & n(2 to 16);
arg1_next <= "00000000000000000" & n(17 to 31);
next_state <= dispatch;
when dispatch =>
swapped_next <= '1';
n_next <= arg2;
n_new_next <= arg2;
next_state <= begin_sort;
when extra1 =>
data1_next <= array0_dOUT0;
i_next <= arg1;
swapped_next <= '0';
next_state <= for_loop;
when extra2 =>
data2_next <= array0_dOUT0;
next_state <= cond_check;
when for_loop =>
if ( i >= n ) then
n_next <= n_new;
next_state <= begin_sort;
elsif ( i < n ) then
array0_addr0 <= i + 1;
array0_rENA0 <= '1';
next_state <= extra2;
end if;
when halt =>
if chan1_full /= '0' then
next_state <= halt;
elsif chan1_full = '0' then
chan1_channelDataIn <= (others => '0');
chan1_channelWrite <= '1';
next_state <= idle;
end if;
when idle =>
if chan1_exists = '0' then
next_state <= idle;
elsif chan1_exists /= '0' then
n_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
next_state <= decode;
end if;
when reset =>
next_state <= idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate2_cached is
generic (
g_version : unsigned(7 downto 0) := X"A8" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate2_cached;
architecture structural of ultimate2_cached is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal mem_req_cached : t_mem_burst_req;
signal mem_resp_cached : t_mem_burst_resp;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
IEC_ATN => IEC_ATN,
IEC_DATA => IEC_DATA,
IEC_CLOCK => IEC_CLOCK,
IEC_RESET => IEC_RESET,
IEC_SRQ_IN => IEC_SRQ_IN,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Buttons
BUTTON => button_i );
i_cache: entity work.dm_cache
port map (
clock => sys_clock,
reset => sys_reset,
client_req => mem_req,
client_resp => mem_resp,
mem_req => mem_req_cached,
mem_resp => mem_resp_cached );
i_memctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req_cached,
resp => mem_resp_cached,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate2_cached is
generic (
g_version : unsigned(7 downto 0) := X"A8" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate2_cached;
architecture structural of ultimate2_cached is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal mem_req_cached : t_mem_burst_req;
signal mem_resp_cached : t_mem_burst_resp;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
IEC_ATN => IEC_ATN,
IEC_DATA => IEC_DATA,
IEC_CLOCK => IEC_CLOCK,
IEC_RESET => IEC_RESET,
IEC_SRQ_IN => IEC_SRQ_IN,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Buttons
BUTTON => button_i );
i_cache: entity work.dm_cache
port map (
clock => sys_clock,
reset => sys_reset,
client_req => mem_req,
client_resp => mem_resp,
mem_req => mem_req_cached,
mem_resp => mem_resp_cached );
i_memctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req_cached,
resp => mem_resp_cached,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate2_cached is
generic (
g_version : unsigned(7 downto 0) := X"A8" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate2_cached;
architecture structural of ultimate2_cached is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal mem_req_cached : t_mem_burst_req;
signal mem_resp_cached : t_mem_burst_resp;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
IEC_ATN => IEC_ATN,
IEC_DATA => IEC_DATA,
IEC_CLOCK => IEC_CLOCK,
IEC_RESET => IEC_RESET,
IEC_SRQ_IN => IEC_SRQ_IN,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Buttons
BUTTON => button_i );
i_cache: entity work.dm_cache
port map (
clock => sys_clock,
reset => sys_reset,
client_req => mem_req,
client_resp => mem_resp,
mem_req => mem_req_cached,
mem_resp => mem_resp_cached );
i_memctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req_cached,
resp => mem_resp_cached,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate2_cached is
generic (
g_version : unsigned(7 downto 0) := X"A8" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate2_cached;
architecture structural of ultimate2_cached is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal mem_req_cached : t_mem_burst_req;
signal mem_resp_cached : t_mem_burst_resp;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
IEC_ATN => IEC_ATN,
IEC_DATA => IEC_DATA,
IEC_CLOCK => IEC_CLOCK,
IEC_RESET => IEC_RESET,
IEC_SRQ_IN => IEC_SRQ_IN,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Buttons
BUTTON => button_i );
i_cache: entity work.dm_cache
port map (
clock => sys_clock,
reset => sys_reset,
client_req => mem_req,
client_resp => mem_resp,
mem_req => mem_req_cached,
mem_resp => mem_resp_cached );
i_memctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req_cached,
resp => mem_resp_cached,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MAC4S_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(6 - 1 downto 0);
p: out std_logic_vector(14 - 1 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MAC4S_1 is
signal tmp_product : std_logic_vector(14 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(6 - 1 downto 0);
signal p_tmp : std_logic_vector(14 - 1 downto 0);
signal a_reg : std_logic_vector(8 - 1 downto 0);
signal b_reg : std_logic_vector(6 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(14 - 1 downto 0);
signal buff1 : std_logic_vector(14 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff1;
tmp_product <= std_logic_vector(resize(unsigned(a_reg) * unsigned(b_reg), 14));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg <= a_i;
b_reg <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 is
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MAC4S_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MAC4S_1_U : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MAC4S_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
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