content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
entity func02 is
port (a : std_logic_vector (7 downto 0);
b : out std_logic_vector (7 downto 0));
end func02;
architecture behav of func02 is
function gen_mask (len : natural) return std_logic_vector is
variable res : std_logic_vector (len - 1 downto 0);
be... |
-------------------------------------------------------------------------------
--
-- File: TMDS_Encoder.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI output on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright D... |
entity gensub2 is
end entity;
architecture test of gensub2 is
function adder generic (type t;
function "+"(l, r : t) return t is <>;
n : t) (x : t) return t is
begin
return x + n;
end function;
function add1 is new adder generic map (t =>... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 12;
constant AMPL_WIDTH : integer := 14;
type lut_type is arr... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 12;
constant AMPL_WIDTH : integer := 14;
type lut_type is arr... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- shifts data into the LSB
entity shift_in is
generic (
width : positive
);
port (
reset : in std_logic;
clk : in std_logic;
ce : in std_logic;
ser_in : in std_logic;
par_out : out std_logic_vector(width - 1 downto 0)
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- shifts data into the LSB
entity shift_in is
generic (
width : positive
);
port (
reset : in std_logic;
clk : in std_logic;
ce : in std_logic;
ser_in : in std_logic;
par_out : out std_logic_vector(width - 1 downto 0)
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- NEED RESULT: ARCH00638.P1: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00638.P2: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00638.P3: Multi transport transactions occurred on signal asg with slice n... |
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2015 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Testbench for Fibonacci Linear Feedback Shift Register (LFSR) package.
------------------------------------------------------------------------------... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_k1_k2_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 17:41:51 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-------------------------------------------------------------------------------
-- Title : Direct digital synhtesis module
-------------------------------------------------------------------------------
-- Author : cjt@users.sourceforge.net
---------------------------------------------------------------------... |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... |
-- $Id: iob_reg_o.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_i - syn
-- Description: Registered IOB, ... |
-------------------------------------------------------------------------------
-- (C) P. Crosthwaite, University of Queensland (2011)
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; eit... |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: sniff_fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ==========================================... |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: sniff_fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ==========================================... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_127 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_127;
architecture augh of cmp_127 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_127 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_127;
architecture augh of cmp_127 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library verilog;
use verilog.vl_types.all;
entity sysreg_spr_register is
generic(
N : integer := 32
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREGIST_REQ : in vl_logic;
iREGIST_DATA : in vl_logic_vector... |
-------------------------------------------------------------------------------
-- $Id: addr_load_and_incr.vhd,v 1.1 2003/03/15 01:05:24 ostlerf Exp $
-------------------------------------------------------------------------------
-- addr_load_and_incr - entity and architecture
-----------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: addr_load_and_incr.vhd,v 1.1 2003/03/15 01:05:24 ostlerf Exp $
-------------------------------------------------------------------------------
-- addr_load_and_incr - entity and architecture
-----------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/27/2016 07:08:32 PM
-- Design Name:
-- Module Name: sim5 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:29 09/22/2014
-- Design Name:
-- Module Name: brutus_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:29 09/22/2014
-- Design Name:
-- Module Name: brutus_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
--------------------------------------------------------------------------------
-- Company: UMASS DARTMOUTH
-- Engineer: Christopher Parks
--
-- Create Date: 13:20:29 03/25/2016
-- Design Name:
-- Module Name: Z:/Xilinx/RegisterBank2/RegisterBank_tb.vhd
-- Project Name: RegisterBank
-- Target Device: ... |
-- Automatically generated: write_netlist -wraprm_lec -vhdl -module max6682-wrapreconfmodule-lec.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MAX6682 is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
M... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Tue Apr 4 05:28:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../hier.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
--... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
-------------------------------------------------------------------------------
-- Title : Components package (generated by Emacs VHDL Mode 3.33.6)
-- Project :
-------------------------------------------------------------------------------
-- File : components.vhd
-- Author : Calle <calle@Alukiste>... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:48:46 10/15/2014
-- Design Name:
-- Module Name: C:/Users/ael10jso/Xilinx/embedded_bruteforce/brutus_system/ISE/controller_sg_pp_md_comp/tb_brutus_dual.vhd
-- Project Name: controller... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- NEED RESULT: ARCH00195.P2: Transaction occurred on signal asg with no time expression -- 0 ns assumed passed
-- NEED RESULT: ARCH00195.P1: Transaction occurred on signal asg with no time expression -- 0 ns assumed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Tr... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.i2c_arb_wbgen2_pkg.all;
package i2c_arb_pkg is
constant c_I2C_ARB_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:22:40 10/12/2015
-- Design Name:
-- Module Name: memory_32x36_r128x9 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Depe... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_PROCESS is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
O : out STD_LOGIC_VECTOR (7 downto 0));
end AND_PROCESS;
architecture Behavioral of AND_PROCESS is
begin
O <= A and B;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
use work.reconos_thread_pkg.all;
entity rt_matrixmul is
port (
-- OSIF FIFO ports
OSIF_Sw2Hw_Data : in std_logic_vec... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use work.utility.all;
entity bcd_1_counter_tb is
end;
architecture bcd_1_counter_tb_func of bcd_1_counter_tb is
signal rst_in: std_logic:='1';
signal clk_in: std_logic:='0';
signal ena_in: std_logic:='0';
signal counter_out: bcd_vector (2 downto 0);
compon... |
--
-- Implements gaussian filter
-- 1 2 1
-- 2 4 2 * 1/16
-- 1 2 1
--
-- Copyright Erik Zachrisson - erik@zachrisson.info
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
use work.OV76X0Pack.all;
entity GaussianFilter is
generic (
Data... |
entity Game is
port(Rb, Reset, Clk: in bit;
Win, Lose: out bit);
end Game;
architecture Play1 of Game is
component Counter
port(Clk, Roll: in bit;
Sum: out integer range 2 to 12);
end component;
component DiceGame
port(Rb, Reset, CLK: in bit;
Sum: in integer range 2 to 12;
Roll, Win... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
context IEEE_BIT_CONTEXT is
library IEEE;
use IEEE.NUMERIC_BIT.all;
end context IEEE_BIT_CONTEXT;
|
context IEEE_BIT_CONTEXT is
library IEEE;
use IEEE.NUMERIC_BIT.all;
end context IEEE_BIT_CONTEXT;
|
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