content stringlengths 1 1.04M ⌀ |
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context IEEE_BIT_CONTEXT is
library IEEE;
use IEEE.NUMERIC_BIT.all;
end context IEEE_BIT_CONTEXT;
|
context IEEE_BIT_CONTEXT is
library IEEE;
use IEEE.NUMERIC_BIT.all;
end context IEEE_BIT_CONTEXT;
|
context IEEE_BIT_CONTEXT is
library IEEE;
use IEEE.NUMERIC_BIT.all;
end context IEEE_BIT_CONTEXT;
|
--
-- File Name: TranscriptPkg.vhd
-- Design Unit Name: TranscriptPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
--
-- Description:
-- Define file identifier TranscriptFile
-- provide subprograms to open, close, and print to it.
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.03 Create YAML with files opened during test
-- 12/2020 2020.12 Updated TranscriptOpen parameter Status to InOut to work around simulator bug.
-- 01/2020 2020.01 Updated Licenses to Apache
-- 11/2016 2016.l1 Added procedure BlankLine
-- 01/2016 2016.01 TranscriptOpen function now calls procedure of same name
-- 01/2015 2015.01 Initial revision
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
package TranscriptPkg is
-- File Identifier to facilitate usage of one transcript file
file TranscriptFile : text ;
-- Cause compile errors if READ_MODE is passed to TranscriptOpen
subtype WRITE_APPEND_OPEN_KIND is FILE_OPEN_KIND range WRITE_MODE to APPEND_MODE ;
-- Open and close TranscriptFile. Function allows declarative opens
procedure TranscriptOpen (Status: InOut FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS ;
procedure TranscriptClose ;
impure function IsTranscriptOpen return boolean ;
alias IsTranscriptEnabled is IsTranscriptOpen [return boolean] ;
-- Mirroring. When using TranscriptPkw WriteLine and Print, uses both TranscriptFile and OUTPUT
procedure SetTranscriptMirror (A : boolean := TRUE) ;
impure function IsTranscriptMirrored return boolean ;
alias GetTranscriptMirror is IsTranscriptMirrored [return boolean] ;
-- Write to TranscriptFile when open. Write to OUTPUT when not open or IsTranscriptMirrored
procedure WriteLine(buf : inout line) ;
procedure Print(s : string) ;
-- Create "count" number of blank lines
procedure BlankLine (count : integer := 1) ;
end TranscriptPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TranscriptPkg is
------------------------------------------------------------
type LocalBooleanPType is protected
procedure Set (A : boolean) ;
impure function get return boolean ;
end protected LocalBooleanPType ;
type LocalBooleanPType is protected body
variable GlobalVar : boolean := FALSE ;
procedure Set (A : boolean) is
begin
GlobalVar := A ;
end procedure Set ;
impure function get return boolean is
begin
return GlobalVar ;
end function get ;
end protected body LocalBooleanPType ;
file TranscriptYamlFile : text ;
------------------------------------------------------------
shared variable TranscriptEnable : LocalBooleanPType ;
shared variable TranscriptMirror : LocalBooleanPType ;
shared variable TranscriptOpened : LocalBooleanPType ;
------------------------------------------------------------
procedure CreateTranscriptYamlLog (Name : STRING) is
------------------------------------------------------------
variable buf : line ;
begin
-- Create Yaml file with list of files.
if not TranscriptOpened.Get then
file_open(TranscriptYamlFile, "OSVVM_transcript.yml", WRITE_MODE) ;
-- swrite(buf, "Transcripts: ") ;
-- WriteLine(TranscriptYamlFile, buf) ;
TranscriptOpened.Set(TRUE) ;
else
file_open(TranscriptYamlFile, "OSVVM_transcript.yml", APPEND_MODE) ;
end if ;
swrite(buf, " - " & Name) ;
WriteLine(TranscriptYamlFile, buf) ;
file_close(TranscriptYamlFile) ;
end procedure CreateTranscriptYamlLog ;
------------------------------------------------------------
procedure TranscriptOpen (Status: InOut FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
begin
file_open(Status, TranscriptFile, ExternalName, OpenKind) ;
if Status = OPEN_OK then
CreateTranscriptYamlLog(ExternalName) ;
TranscriptEnable.Set(TRUE) ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
if Status /= OPEN_OK then
report "TranscriptPkg.TranscriptOpen file: " &
ExternalName & " status is: " & to_string(status) & " and is not OPEN_OK" severity FAILURE ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
return Status ;
end function TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptClose is
------------------------------------------------------------
begin
if TranscriptEnable.Get then
file_close(TranscriptFile) ;
end if ;
TranscriptEnable.Set(FALSE) ;
end procedure TranscriptClose ;
------------------------------------------------------------
impure function IsTranscriptOpen return boolean is
------------------------------------------------------------
begin
return TranscriptEnable.Get ;
end function IsTranscriptOpen ;
------------------------------------------------------------
procedure SetTranscriptMirror (A : boolean := TRUE) is
------------------------------------------------------------
begin
TranscriptMirror.Set(A) ;
end procedure SetTranscriptMirror ;
------------------------------------------------------------
impure function IsTranscriptMirrored return boolean is
------------------------------------------------------------
begin
return TranscriptMirror.Get ;
end function IsTranscriptMirrored ;
------------------------------------------------------------
procedure WriteLine(buf : inout line) is
------------------------------------------------------------
begin
if not TranscriptEnable.Get then
WriteLine(OUTPUT, buf) ;
elsif TranscriptMirror.Get then
TEE(TranscriptFile, buf) ;
else
WriteLine(TranscriptFile, buf) ;
end if ;
end procedure WriteLine ;
------------------------------------------------------------
procedure Print(s : string) is
------------------------------------------------------------
variable buf : line ;
begin
write(buf, s) ;
WriteLine(buf) ;
end procedure Print ;
------------------------------------------------------------
procedure BlankLine (count : integer := 1) is
------------------------------------------------------------
begin
for i in 1 to count loop
print("") ;
end loop ;
end procedure Blankline ;
end package body TranscriptPkg ; |
-----------------------------------------------------------------------------------------------------------
--
-- MILK COPROCESSOR BASIC DEFINITIONS
--
-- This file contains basic parameters definitions.
--
-- Created by Claudio Brunelli, 2004
--
-----------------------------------------------------------------------------------------------------------
--Copyright (c) 2004, Tampere University of Technology.
--All rights reserved.
--Redistribution and use in source and binary forms, with or without modification,
--are permitted provided that the following conditions are met:
--* Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--* Neither the name of Tampere University of Technology nor the names of its
-- contributors may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--THIS HARDWARE DESCRIPTION OR SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
--CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND NONINFRINGEMENT AND
--FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
--OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
--EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
--PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
--BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--ARISING IN ANY WAY OUT OF THE USE OF THIS HARDWARE DESCRIPTION OR SOFTWARE, EVEN
--IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package cop_definitions is
-----------------------------------------------------------------------------------------------------------
--
-- bus width configuration
--
-----------------------------------------------------------------------------------------------------------
constant word_width : positive := 32; -- data bus width
constant sreg_width : positive := 14; -- status register width
constant buffer_width : positive := 32; -- RF output tristate buffers width
constant RF_width : positive := 8; -- number of general purpose registers
constant instr_word_width : positive := 24; -- amount of significative bits loaded in control register
constant exceptions_amount : positive := 22; -- overall number of "internal" exceptions
constant RF_exceptions_amount : positive := 1; -- number of "internal" exceptions related to the register file
constant flags_amount : positive := 7; -- number of status flag bits
constant cop_opcode_width : positive := 6; -- amount of bits of the "opcode" field of the instruction word
-----------------------------------------------------------------------------------------------------------
--
-- ctrl_logic configuration
--
-----------------------------------------------------------------------------------------------------------
constant wrbck_sgls_width : positive := 8; -- wrbck signals set in ctrl_logic
constant m : positive := 12; -- amount of sub-buses in the register delay chain (ctrl_logic)
constant n : positive := 3; -- width of sub-buses in the register delay chain (ctrl_logic)
constant conv_clk_cycles : positive := 2; -- latency (in clk cycles) required by conv
constant trunc_clk_cycles : positive := 2; -- latency (in clk cycles) required by trunc
constant mul_clk_cycles : positive := 3; -- latency (in clk cycles) required by mul
constant div_clk_cycles : positive := 12; -- latency (in clk cycles) required by div
constant add_clk_cycles : positive := 5; -- latency (in clk cycles) required by add
constant sqrt_clk_cycles : positive := 8; -- latency (in clk cycles) required by sqrt
-----------------------------------------------------------------------------------------------------------
--
-- main constants
--
-----------------------------------------------------------------------------------------------------------
constant reset_active : Std_logic := '1'; -- '1' -> positive logic
constant we_active : Std_logic := '1';
constant oe_active : Std_logic := '1';
constant ovfw_active : Std_logic := '1';
constant underfw_active : Std_logic := '1';
-----------------------------------------------------------------------------------------------------------
--
-- FUs insertion generics' boolean values
--
-----------------------------------------------------------------------------------------------------------
constant conv_flag_value : integer := 1;
constant trunc_flag_value : integer := 1;
constant mul_flag_value : integer := 1;
constant div_flag_value : integer := 1;
constant add_flag_value : integer := 1;
constant sqrt_flag_value : integer := 1;
constant compare_flag_value : integer := 1;
-----------------------------------------------------------------------------------------------------------
--
-- "integer_sqrt" block configuration constants
--
-----------------------------------------------------------------------------------------------------------
constant radicand_width : positive := 52; -- operand width
constant sqrt_width : positive := 26; -- result width
constant rem_width : positive := 28; -- remainder width
constant k_max : positive := 26; -- number of "iterations" in the algorithm
-----------------------------------------------------------------------------------------------------------
--
-- "integer_divider" block configuration constants
--
-----------------------------------------------------------------------------------------------------------
constant dividend_width : positive := 24; -- operand width
constant divisor_width : positive := 24; -- operand width
constant quotient_width : positive := 25; -- result width
constant division_rem_width : positive := 25; -- remainder width
constant div_k_max : positive := 25; -- number of "iterations" in the algorithm
type bus_8Xd is array (8 downto 0) of std_logic_vector(divisor_width+1 downto 0);
-----------------------------------------------------------------------------------------------------------
--
-- user defined types
--
-----------------------------------------------------------------------------------------------------------
type bus8X32 is array (RF_width-1 downto 0) of std_logic_vector(word_width-1 downto 0);
type bus_mXn is array (m downto 0) of std_logic_vector(n-1 downto 0);
subtype rf_addr is std_logic_vector(2 downto 0); -- RF registers' address bits
subtype wb_code is std_logic_vector(3 downto 0); -- result writeback logic's "indexing" bits
subtype cop_opcode is std_logic_vector(cop_opcode_width-1 downto 0); -- opcode specification bits
-----------------------------------------------------------------------------------------------------------
--
-- instruction set mnemonics
--
-----------------------------------------------------------------------------------------------------------
-- opcodes are the same as those in the MIPS' coprocessor instruction set
constant cop_add_s : cop_opcode := "000000"; -- adds two FP single precision numbers : ADD.S
constant cop_sub_s : cop_opcode := "000001"; -- subtracts two FP single precision numbers : SUB.S
constant cop_mul_s : cop_opcode := "000010"; -- multiplies two FP single precision numbers : MUL.S
constant cop_div_s : cop_opcode := "000011"; -- divides two FP single precision numbers : DIV.S
constant cop_sqrt_s : cop_opcode := "000100"; -- extracts the square root of a FP single precision number : SQRT.S
constant cop_abs_s : cop_opcode := "000101"; -- extracts the absolute value of a FP single precision number : ABS.S
constant cop_mov_s : cop_opcode := "000110"; -- moves a value from a register to another : MOV.S
constant cop_neg_s : cop_opcode := "000111"; -- inverts the sign of a single precision FP number : NEG.S
constant nop : cop_opcode := "001000"; -- no operation executed : NOP.S
constant cop_trunc_w : cop_opcode := "001101";
constant cop_cvt_s : cop_opcode := "100000"; -- converts an integer into a single precision FP : CVT.S
constant cop_cvt_w : cop_opcode := "100100"; -- converts a single precision FP into an integer : CVT.W
-- Note: the comparison is obtained through a set of 16 sub-instructions whose opcodes are charaterized by the two
-- most-significant bits set
------------------------------------------------------------------------------------------------------------
--
-- result writeback selection signals
--
------------------------------------------------------------------------------------------------------------
constant wb_cvt_s : wb_code := "0000";
constant wb_trunc_w : wb_code := "0001";
constant wb_mul_s : wb_code := "0010";
constant wb_div_s : wb_code := "0011";
constant wb_addsub_s : wb_code := "0100";
constant wb_sqrt_s : wb_code := "0101";
constant wb_abs_s : wb_code := "0110";
constant wb_mov_s : wb_code := "0111";
constant wb_neg_s : wb_code := "1000";
constant wb_compare_s : wb_code := "1001";
end cop_definitions ;
package body cop_definitions is
end cop_definitions;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity dft_out_fsm is
port (
reset : in std_logic;
clk : in std_logic;
dft_ce : out std_logic;
dft_dout : in std_logic_vector(31 downto 0);
dft_fd_out : in std_logic;
fifo_data : out std_logic_vector(31 downto 0);
fifo_wr_en : out std_logic;
fifo_wr_count : in std_logic_vector(9 downto 0);
fifo_watchdog_reset : out std_logic
);
end dft_out_fsm;
architecture rtl of dft_out_fsm is
constant data_size : integer := 960;
constant fifo_size : integer := 1024;
type fsm is (rst, idle, fifo_wait, dft_out);
signal state : fsm := rst;
signal data_cnt : std_logic_vector(15 downto 0);
signal fifo_cnt_prev : std_logic_vector(9 downto 0);
begin
fifo_data <= dft_dout;
process(clk)
begin
if (clk'event and clk = '1') then
case state is
when rst =>
dft_ce <= '1';
fifo_wr_en <= '0';
data_cnt <= std_logic_vector(to_unsigned(data_size - 1, data_cnt'length));
state <= idle;
when idle =>
dft_ce <= '1';
fifo_wr_en <= '0';
data_cnt <= std_logic_vector(to_unsigned(data_size - 1, data_cnt'length));
if (dft_fd_out = '1') then
if (fifo_wr_count /= (fifo_wr_count'range => '0')) then
dft_ce <= '0';
state <= fifo_wait;
else
dft_ce <= '0';
fifo_wr_en <= '1';
state <= dft_out;
end if;
else
state <= idle;
end if;
when fifo_wait =>
dft_ce <= '0';
fifo_wr_en <= '0';
data_cnt <= std_logic_vector(to_unsigned(data_size - 1, data_cnt'length));
if (to_integer(unsigned(fifo_wr_count)) > (fifo_size - data_size)) then
state <= fifo_wait;
else
fifo_wr_en <= '1';
dft_ce <= '1';
state <= dft_out;
end if;
when dft_out =>
dft_ce <= '1';
fifo_wr_en <= '1';
data_cnt <= data_cnt;
if (data_cnt /= (data_cnt'range => '0')) then
data_cnt <= data_cnt - '1';
state <= dft_out;
else
fifo_wr_en <= '0';
state <= idle;
end if;
when others =>
null;
end case;
if (reset = '1') then
state <= rst;
end if;
-- Watchdog control signal
if (fifo_wr_count /= fifo_cnt_prev) then
fifo_watchdog_reset <= '1';
fifo_cnt_prev <= fifo_wr_count;
else
fifo_watchdog_reset <= '0';
fifo_cnt_prev <= fifo_cnt_prev;
end if;
end if;
end process;
end rtl; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lifo is
port (
x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0) :="0000";
clk : in std_logic;
wr : in std_logic; -- wr =1 to write wr = 0 to read
empty, full : out std_logic :='0'
);
end entity;
architecture lifo of lifo is
type ram_type is array(5 downto 0) of std_logic_vector(3 downto 0);
signal lifo : ram_type :=("0000","0000","0000","0000","0000","0000");
signal last : integer range -1 to 5 := -1;
begin
process(clk)
begin
if rising_edge(clk) then
if wr = '1' then
if last < 5 then
lifo(last+1)<=x;
last <= last +1;
if last = 5 then
full <= '1';
end if;
end if;
elsif wr = '0' then
if last > -1 then
y<=lifo(last);
last <= last -1;
if last = -1 then
empty <= '1';
end if;
end if;
end if;
end if;
end process;
end architecture;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_04a is
end entity inline_04a;
architecture test of inline_04a is
component opamp is
port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
end component opamp;
terminal plus_in, minus_in, output, vdd, vss, gnd : electrical;
begin
voltage_amp : component opamp
port map ( plus_in => plus_in, minus_in => minus_in, output => output,
vdd => vdd, vss => vss, gnd => gnd );
end architecture test;
configuration inline_04a_test of inline_04a is
for test
-- code from book (in text)
for voltage_amp : opamp
use configuration work.opamp_mosfets;
end for;
-- end code from book
end for;
end configuration inline_04a_test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_04a is
end entity inline_04a;
architecture test of inline_04a is
component opamp is
port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
end component opamp;
terminal plus_in, minus_in, output, vdd, vss, gnd : electrical;
begin
voltage_amp : component opamp
port map ( plus_in => plus_in, minus_in => minus_in, output => output,
vdd => vdd, vss => vss, gnd => gnd );
end architecture test;
configuration inline_04a_test of inline_04a is
for test
-- code from book (in text)
for voltage_amp : opamp
use configuration work.opamp_mosfets;
end for;
-- end code from book
end for;
end configuration inline_04a_test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_04a is
end entity inline_04a;
architecture test of inline_04a is
component opamp is
port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
end component opamp;
terminal plus_in, minus_in, output, vdd, vss, gnd : electrical;
begin
voltage_amp : component opamp
port map ( plus_in => plus_in, minus_in => minus_in, output => output,
vdd => vdd, vss => vss, gnd => gnd );
end architecture test;
configuration inline_04a_test of inline_04a is
for test
-- code from book (in text)
for voltage_amp : opamp
use configuration work.opamp_mosfets;
end for;
-- end code from book
end for;
end configuration inline_04a_test;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: cachemem
-- File: cachemem.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Contains ram cells for both instruction and data caches
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.macro.all;
use work.tech_map.all;
entity cachemem is
port (
clk : in clk_type;
crami : in cram_in_type;
cramo : out cram_out_type
);
end;
architecture rtl of cachemem is
constant ITDEPTH : natural := 2**IOFFSET_BITS;
constant DTDEPTH : natural := 2**DOFFSET_BITS;
constant ITWIDTH : natural := ITAG_BITS;
constant DTWIDTH : natural := DTAG_BITS;
signal itaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
signal idaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
signal itdatain : std_logic_vector(ITAG_BITS -1 downto 0);
signal itdataout : std_logic_vector(ITAG_BITS -1 downto 0);
signal iddatain : std_logic_vector(32 -1 downto 0);
signal iddataout : std_logic_vector(32 -1 downto 0);
signal itenable : std_logic;
signal idenable : std_logic;
signal itwrite : std_logic;
signal idwrite : std_logic;
signal dtaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr2 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal ddaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
signal dtdatain : std_logic_vector(DTAG_BITS -1 downto 0);
signal dtdatain2 : std_logic_vector(DTAG_BITS -1 downto 0);
signal dtdataout : std_logic_vector(DTAG_BITS -1 downto 0);
signal dtdataout2: std_logic_vector(DTAG_BITS -1 downto 0);
signal dddatain : std_logic_vector(32 -1 downto 0);
signal dddataout : std_logic_vector(32 -1 downto 0);
signal dtenable : std_logic;
signal dtenable2 : std_logic;
signal ddenable : std_logic;
signal dtwrite : std_logic;
signal dtwrite2 : std_logic;
signal ddwrite : std_logic;
signal vcc, gnd : std_logic;
begin
vcc <= '1'; gnd <= '0'; dtdatain2 <= (others => '0');
itaddr <= crami.icramin.idramin.address(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
idaddr <= crami.icramin.idramin.address;
itinsel : process(crami)
begin
itdatain(ITAG_BITS - 1 downto 0) <= crami.icramin.itramin.tag &
crami.icramin.itramin.valid;
iddatain(31 downto 0) <= crami.icramin.idramin.data;
dtdatain(DTAG_BITS - 1 downto 0) <= crami.dcramin.dtramin.tag &
crami.dcramin.dtramin.valid;
dddatain(32 - 1 downto 0) <= crami.dcramin.ddramin.data;
end process;
itwrite <= crami.icramin.itramin.write;
idwrite <= crami.icramin.idramin.write;
itenable <= crami.icramin.itramin.enable;
idenable <= crami.icramin.idramin.enable;
dtaddr <= crami.dcramin.ddramin.address(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
dtaddr2 <= crami.dcramin.dtraminsn.address;
ddaddr <= crami.dcramin.ddramin.address;
dtwrite <= crami.dcramin.dtramin.write;
dtwrite2 <= crami.dcramin.dtraminsn.write;
ddwrite <= crami.dcramin.ddramin.write;
dtenable <= crami.dcramin.dtramin.enable;
dtenable2 <= crami.dcramin.dtraminsn.enable;
ddenable <= crami.dcramin.ddramin.enable;
itags0 : syncram
generic map ( dbits => ITAG_BITS, abits => IOFFSET_BITS)
port map ( itaddr, clk, itdatain, itdataout, itenable, itwrite);
dtags0 : if not DSNOOP generate
dtags0 : syncram
generic map ( dbits => DTAG_BITS, abits => DOFFSET_BITS)
port map ( dtaddr, clk, dtdatain, dtdataout, dtenable, dtwrite);
end generate;
dtags1 : if DSNOOP generate
dtags0 : dpsyncram
generic map ( dbits => DTAG_BITS, abits => DOFFSET_BITS)
port map ( dtaddr, clk, dtdatain, dtdataout, dtenable, dtwrite,
dtaddr2, dtdatain2, dtdataout2, dtenable2, dtwrite2);
end generate;
idata0 : syncram
generic map ( dbits => 32, abits => IOFFSET_BITS+ILINE_BITS)
port map ( idaddr, clk, iddatain, iddataout, idenable, idwrite);
ddata0 : syncram
generic map ( dbits => 32, abits => DOFFSET_BITS+DLINE_BITS)
port map ( ddaddr, clk, dddatain, dddataout, ddenable, ddwrite);
cramo.icramout.itramout.valid <= itdataout(ILINE_SIZE -1 downto 0);
cramo.icramout.itramout.tag <= itdataout(ITAG_BITS-1 downto ILINE_SIZE);
cramo.icramout.idramout.data <= iddataout(31 downto 0);
cramo.dcramout.dtramout.valid <= dtdataout(DLINE_SIZE -1 downto 0);
cramo.dcramout.dtramout.tag <= dtdataout(DTAG_BITS-1 downto DLINE_SIZE);
cramo.dcramout.dtramoutsn.tag <= dtdataout2(DTAG_BITS-1 downto DLINE_SIZE);
cramo.dcramout.ddramout.data <= dddataout(31 downto 0);
end ;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ArithmeticalLogicalLeftShifter_x16 is
Port (
input : STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end ArithmeticalLogicalLeftShifter_x16;
architecture skeleton of ArithmeticalLogicalLeftShifter_x16 is
begin
process(input) is
begin
for i in 15 downto 1 loop
output(i) <= input(i - 1);
end loop;
output(0) <= '0';
end process;
end skeleton; |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Loop_lojbC_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Loop_lojbC_shiftReg;
architecture rtl of start_for_Loop_lojbC_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_Loop_lojbC is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Loop_lojbC is
component start_for_Loop_lojbC_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Loop_lojbC_shiftReg : start_for_Loop_lojbC_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ap_a_01 is
end entity ap_a_01;
library ieee; use ieee.std_logic_1164.all;
architecture test of ap_a_01 is
signal clk : std_ulogic;
begin
process (clk) is
-- code from book
-- end code from book
begin
if
-- code from book
clk'event and (To_X01(clk) = '1') and (To_X01(clk'last_value) = '0')
-- end code from book
then
report "rising edge on clk";
end if;
end process;
clk <= '0', '1' after 10 ns, '0' after 20 ns,
'1' after 30 ns, '0' after 40 ns;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ap_a_01 is
end entity ap_a_01;
library ieee; use ieee.std_logic_1164.all;
architecture test of ap_a_01 is
signal clk : std_ulogic;
begin
process (clk) is
-- code from book
-- end code from book
begin
if
-- code from book
clk'event and (To_X01(clk) = '1') and (To_X01(clk'last_value) = '0')
-- end code from book
then
report "rising edge on clk";
end if;
end process;
clk <= '0', '1' after 10 ns, '0' after 20 ns,
'1' after 30 ns, '0' after 40 ns;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ap_a_01 is
end entity ap_a_01;
library ieee; use ieee.std_logic_1164.all;
architecture test of ap_a_01 is
signal clk : std_ulogic;
begin
process (clk) is
-- code from book
-- end code from book
begin
if
-- code from book
clk'event and (To_X01(clk) = '1') and (To_X01(clk'last_value) = '0')
-- end code from book
then
report "rising edge on clk";
end if;
end process;
clk <= '0', '1' after 10 ns, '0' after 20 ns,
'1' after 30 ns, '0' after 40 ns;
end architecture test;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 - 2012 Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
cpu_rst_n : in std_ulogic;
clk_fpga_50m : in std_ulogic;
-- DDR SDRAM
ram_a : out std_logic_vector (13 downto 0); -- ddr address
ram_ck_p : out std_logic;
ram_ck_n : out std_logic;
ram_cke : out std_logic;
ram_cs_n : out std_logic;
ram_ws_n : out std_ulogic; -- ddr write enable
ram_ras_n : out std_ulogic; -- ddr ras
ram_cas_n : out std_ulogic; -- ddr cas
ram_dm : out std_logic_vector(1 downto 0); -- ram_udm & ram_ldm
ram_dqs : inout std_logic_vector (1 downto 0); -- ram_udqs & ram_lqds
ram_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ram_d : inout std_logic_vector (15 downto 0); -- ddr data
-- Ethernet PHY
txd : out std_logic_vector(3 downto 0);
rxd : in std_logic_vector(3 downto 0);
tx_clk : in std_logic;
rx_clk : in std_logic;
tx_en : out std_logic;
rx_dv : in std_logic;
eth_crs : in std_logic;
rx_er : in std_logic;
eth_col : in std_logic;
mdio : inout std_logic;
mdc : out std_logic;
eth_reset_n : out std_logic;
-- Temperature sensor
temp_sc : inout std_logic;
temp_cs_n : out std_logic;
temp_sio : inout std_logic;
-- LEDs
f_led : inout std_logic_vector(7 downto 0);
-- User push-button
pbsw_n : in std_logic;
-- Reconfig SW1 and SW2
reconfig_sw : in std_logic_vector(2 downto 1);
-- SD card interface
sd_dat0 : inout std_logic;
sd_dat1 : inout std_logic;
sd_dat2 : inout std_logic;
sd_dat3 : inout std_logic;
sd_cmd : inout std_logic;
sd_clk : inout std_logic;
-- EPCS
epcs_data : in std_ulogic;
epcs_dclk : out std_ulogic;
epcs_csn : out std_ulogic;
epcs_asdi : out std_ulogic
-- Expansion connector on card edge (set as reserved in design's QSF)
--reset_exp_n : out std_logic;
--exp_present : in std_logic;
--p : inout std_logic_vector(64 downto 1)
);
end;
architecture rtl of leon3mp is
constant maxahbm : integer := NCPU+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbs : integer := 6
--pragma translate_off
+1 -- one more in simulation (AHBREP)
--pragma translate_on
;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal clkm, clkml : std_ulogic;
signal lclk, resetn : std_ulogic;
signal clklock, lock : std_ulogic;
signal rstn, rawrstn : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal tck : std_ulogic;
signal tckn : std_ulogic;
signal tms : std_ulogic;
signal tdi : std_ulogic;
signal tdo : std_ulogic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u0i : uart_in_type;
signal u0o : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spii2 : spi_in_type;
signal spio2 : spi_out_type;
signal slvsel2 : std_logic_vector(0 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal dsu_breakn : std_ulogic;
attribute syn_keep : boolean;
attribute syn_keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
begin
vcc <= (others => '1'); gnd <= (others => '0');
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
cgi.pllctrl <= "00"; cgi.pllrst <= not rawrstn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clk_pad : clkpad generic map (tech => padtech)
port map (clk_fpga_50m, lclk);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (
tech => CFG_CLKTECH,
clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV,
sdramen => 0,
freq => freq)
port map (
clkin => lclk,
pciclkin => gnd(0),
clk => clkm,
clkn => open,
clk2x => open,
sdclk => open,
pciclk => open,
cgi => cgi,
cgo => cgo);
reset_pad : inpad generic map (tech => padtech) port map (cpu_rst_n, resetn);
rst0 : rstgen -- reset generator
port map (
rstin => resetn,
clk => clkm,
clklock => clklock,
rstout => rstn,
rstoutraw => rawrstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (
defmast => CFG_DEFMST,
split => CFG_SPLIT,
rrobin => CFG_RROBIN,
ioaddr => CFG_AHBIO,
ioen => IOAEN,
nahbm => maxahbm,
nahbs => maxahbs)
port map (
rst => rstn,
clk => clkm,
msti => ahbmi,
msto => ahbmo,
slvi => ahbsi,
slvo => ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (
hindex => i,
fabtech => fabtech,
memtech => memtech,
nwindows => CFG_NWIN,
dsu => CFG_DSU,
fpu => CFG_FPU,
v8 => CFG_V8,
cp => 0,
mac => CFG_MAC,
pclow => pclow,
notag => CFG_NOTAG,
nwp => CFG_NWP,
icen => CFG_ICEN,
irepl => CFG_IREPL,
isets => CFG_ISETS,
ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ,
isetlock => CFG_ILOCK,
dcen => CFG_DCEN,
drepl => CFG_DREPL,
dsets => CFG_DSETS,
dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ,
dsetlock => CFG_DLOCK,
dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN,
ilramsize => CFG_ILRAMSZ,
ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN,
dlramsize => CFG_DLRAMSZ,
dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN,
itlbnum => CFG_ITLBNUM,
dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE,
tlb_rep => CFG_TLB_REP,
lddel => CFG_LDDEL,
disas => disas,
tbuf => CFG_ITBSZ,
pwd => CFG_PWD,
svt => CFG_SVT,
rstaddr => CFG_RSTADDR,
smp => NCPU-1,
cached => CFG_DFIXED,
scantest => CFG_SCAN,
mmupgsz => CFG_MMU_PAGE,
bp => CFG_BP,
npasi => CFG_NP_ASI,
pwrpsr => CFG_WRPSR)
port map (
clk => clkm,
rstn => rstn,
ahbi => ahbmi,
ahbo => ahbmo(i),
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi(i),
irqo => irqo(i),
dbgi => dbgi(i),
dbgo => dbgo(i));
end generate;
errorn_pad : toutpad generic map (tech => padtech) port map (f_led(6), gnd(0), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (
hindex => 2,
haddr => 16#900#,
hmask => 16#F00#,
ncpu => NCPU,
tbits => 30,
tech => memtech,
irq => 0,
kbytes => CFG_ATBSZ)
port map (
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(2),
dbgi => dbgo,
dbgo => dbgi,
dsui => dsui,
dsuo => dsuo);
dsui.enable <= '1';
dsui.break <= not dsu_breakn; -- Switch polarity
dsubre_pad : inpad generic map (tech => padtech) port map (pbsw_n, dsu_breakn);
dsuact_pad : toutpad generic map (tech => padtech) port map (f_led(7), gnd(0), dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(
rst => rstn,
clk => clkm,
tck => tck,
tms => tms,
tdi => tdi,
tdo => tdo,
ahbi => ahbmi,
ahbo => ahbmo(NCPU+CFG_AHB_UART),
tapo_tck => open,
tapo_tdi => open,
tapo_inst => open,
tapo_rst => open,
tapo_capt => open,
tapo_shft => open,
tapo_upd => open,
tapi_tdo => gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR memory controller
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa
generic map (
fabtech => fabtech,
memtech => memtech,
hindex => 0,
haddr => 16#400#,
hmask => 16#F00#,
ioaddr => 1,
pwron => CFG_DDRSP_INIT,
MHz => BOARD_FREQ/1000,
rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/5,
clkdiv => 10,
ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE,
ddrbits => 16,
regoutput => 1,
mobile => 0)
port map (
rst_ddr => rawrstn,
rst_ahb => rstn,
clk_ddr => lclk,
clk_ahb => clkm,
lock => lock,
clkddro => clkml,
clkddri => clkml,
ahbsi => ahbsi,
ahbso => ahbso(0),
ddr_clk => ddr_clkv,
ddr_clkb => ddr_clkbv,
ddr_clk_fb_out => open,
ddr_clk_fb => gnd(0),
ddr_cke => ddr_ckev,
ddr_csb => ddr_csbv,
ddr_web => ram_ws_n,
ddr_rasb => ram_ras_n,
ddr_casb => ram_cas_n,
ddr_dm => ram_dm,
ddr_dqs => ram_dqs,
ddr_ad => ram_a,
ddr_ba => ram_ba,
ddr_dq => ram_d);
end generate;
ram_ck_p <= ddr_clkv(0);
ram_ck_n <= ddr_clkbv(0);
ram_cke <= ddr_ckev(0);
ram_cs_n <= ddr_csbv(0);
ddrsp1 : if (CFG_DDRSP = 0) generate
ahbso(0) <= ahbs_none;
lock <= '1';
ddr_clkv <= (others => '0');
ddr_clkbv <= (others => '0');
ddr_ckev <= (others => '1');
ddr_csbv <= (others => '1');
end generate;
-- SPI Memory Controller
spimc: if CFG_SPIMCTRL /= 0 and CFG_AHBROMEN = 0 generate
spimctrl0 : spimctrl
generic map (
hindex => 4,
hirq => 9,
faddr => 16#000#,
fmask => 16#f00#,
ioaddr => 16#002#,
iomask => 16#fff#,
spliten => CFG_SPLIT,
oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT,
offset => CFG_SPIMCTRL_OFFSET)
port map (
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(4),
spii => spmi,
spio => spmo);
end generate;
epcs_miso_pad : inpad generic map (tech => padtech)
port map (epcs_data, spmi.miso);
epcs_mosi_pad : outpad generic map (tech => padtech)
port map (epcs_asdi, spmo.mosi);
epcs_sck_pad : outpad generic map (tech => padtech)
port map (epcs_dclk, spmo.sck);
epcs_slvsel0_pad : outpad generic map (tech => padtech)
port map (epcs_csn, spmo.csn);
nospimc : if CFG_SPIMCTRL /= 1 or CFG_AHBROMEN /= 0 generate
spmo <= spimctrl_out_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- AHB/APB bridge
apb0 : apbctrl
generic map (
hindex => 1,
haddr => CFG_APBADDR,
nslaves => 7)
port map (
rst => rstn,
clk => clkm,
ahbi => ahbsi,
ahbo => ahbso(1),
apbi => apbi,
apbo => apbo);
-- 8-bit UART, not connected off-chip, use in loopback with GRMON
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (
pindex => 1,
paddr => 1,
pirq => 2,
console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(1),
uarti => u0i,
uarto => u0o);
end generate;
u0i.rxd <= '0'; u0i.ctsn <= '0'; u0i.extclk <= '0';
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (
pindex => 2,
paddr => 2,
ncpu => NCPU)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(2),
irqi => irqo,
irqo => irqi);
end generate;
noirqctrl : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (
pindex => 3,
paddr => 3,
pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ,
sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(3),
gpti => gpti,
gpto => open);
end generate;
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
gpti.wdogen <= '0';
notim : if CFG_GPT_ENABLE = 0 generate
apbo(3) <= apb_none;
end generate;
-- GPIO unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(
pindex => 0,
paddr => 0,
imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map(
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(0),
gpioi => gpioi,
gpioo => gpioo);
end generate;
gpio_pads : iopadvv generic map (tech => padtech, width => 6)
port map (f_led(5 downto 0), gpioo.dout(5 downto 0),
gpioo.oen(5 downto 0), gpioi.din(5 downto 0));
gpioi.din(31 downto 6) <= (others => '0');
nogpio : if CFG_GRGPIO_ENABLE = 0 generate
apbo(0) <= apb_none;
end generate;
-- SPI controller connected to temperature sensor
spic: if CFG_SPICTRL_ENABLE /= 0 generate
spi1 : spictrl
generic map (
pindex => 4,
paddr => 4,
pmask => 16#fff#,
pirq => 9,
fdepth => CFG_SPICTRL_FIFO,
slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => 1,
maxwlen => CFG_SPICTRL_MAXWLEN,
netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM,
ft => CFG_SPICTRL_FT)
port map (
rstn => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(4),
spii => spii,
spio => spio,
slvsel => slvsel);
end generate spic;
-- MISO signal not used
spii.miso <= '0';
mosi_pad : iopad generic map (tech => padtech)
port map (temp_sio, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (temp_sc, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (temp_cs_n, slvsel(0));
spii.spisel <= '1'; -- Master only
nospic : if CFG_SPICTRL_ENABLE = 0 generate
apbo(4) <= apb_none;
spio.misooen <= '1';
spio.mosioen <= '1';
spio.sckoen <= '1';
slvsel <= (others => '1');
end generate;
-- SPI controller connected to SD card slot
spic2: if CFG_SPICTRL_ENABLE /= 0 and CFG_SPICTRL_NUM > 1 generate
spi1 : spictrl
generic map (
pindex => 5,
paddr => 5,
pmask => 16#fff#,
pirq => 11,
fdepth => CFG_SPICTRL_FIFO,
slvselen => 1,
slvselsz => 1,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => 0,
maxwlen => CFG_SPICTRL_MAXWLEN,
netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM,
ft => CFG_SPICTRL_FT)
port map (
rstn => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(5),
spii => spii2,
spio => spio2,
slvsel => slvsel2);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat0, spio2.miso, spio2.misooen, spii2.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio2.mosi, spio2.mosioen, spii2.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_clk, spio2.sck, spio2.sckoen, spii2.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel2(0));
spii2.spisel <= '1'; -- Master only
end generate;
nospic2 : if CFG_SPICTRL_ENABLE = 0 or CFG_SPICTRL_NUM < 2 generate
apbo(5) <= apb_none;
spio2.misooen <= '1';
spio2.mosioen <= '1';
spio2.sckoen <= '1';
slvsel2(0) <= '0';
end generate;
-- sd_dat1 and sd_dat2 are unused
unuseddat1_pad : iopad generic map (tech => padtech)
port map (sd_dat1, gnd(0), vcc(1), open);
unuseddat2_pad : iopad generic map (tech => padtech)
port map (sd_dat2, gnd(0), vcc(1), open);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH /= 0 generate -- Gaisler Ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_JTAG,
pindex => 6,
paddr => 6,
pirq => 10,
memtech => memtech,
mdcscaler => CPU_FREQ/(4*1000)-1,
enable_mdio => 1,
fifosize => CFG_ETH_FIFO,
nsync => 1,
edcl => CFG_DSU_ETH,
edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM,
macaddrl => CFG_ETH_ENL,
phyrstadr => 1,
ipaddrh => CFG_ETH_IPM,
ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_JTAG),
apbi => apbi,
apbo => apbo(6),
ethi => ethi,
etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (eth_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (eth_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (tx_en, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (eth_reset_n, rawrstn);
end generate;
noeth : if CFG_GRETH = 0 generate
apbo(6) <= apb_none;
ethi <= eth_in_none;
etho <= eth_out_none;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (
hindex => 3,
haddr => CFG_AHBRODDR,
pipe => CFG_AHBROPIP)
port map (
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(3));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(3) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (
hindex => 5,
haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(5));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(5) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- AHB Report Module for simulation ----------------------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
driveahbm : for i in maxahbm to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
driveahbs : for i in maxahbs to NAHBSLV-1 generate
ahbso(i) <= ahbs_none;
end generate;
driveapb : for i in 7 to NAPBSLV-1 generate
apbo(i) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 BeMicro SDK Design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2avl_async
-- File: ahb2avl_async.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Asynchronous AHB to Avalon-MM interface based on ddr2spa
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ahb2avl_async is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
avldbits : integer := 32;
avlabits : integer := 20
);
port (
rst_ahb : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
rst_avl : in std_ulogic;
clk_avl : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type
);
end;
architecture struct of ahb2avl_async is
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(avldbits);
constant l2ahbw: integer := log2(ahbbits);
-- Write buffer dimensions
constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw;
constant wbuf_rabits_r: integer := wbuf_rabits_s;
constant wbuf_rdbits: integer := avldbits;
constant wbuf_wabits: integer := 1+l2blen-5;
constant wbuf_wdbits: integer := ahbbits;
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw;
constant rbuf_rdbits: integer := wbuf_wdbits;
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := avldbits;
signal request : ddr_request_type;
signal start_tog : std_ulogic;
signal response : ddr_response_type;
signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0);
signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0);
signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0);
signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0);
signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0);
signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0);
signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0);
signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0);
signal wbwrite,wbwritebig,rbwrite: std_ulogic;
signal gnd: std_logic_vector(3 downto 0);
signal vcc: std_ulogic;
begin
gnd <= (others => '0');
vcc <= '1';
fe0: ddr2spax_ahb
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
ioaddr => 0,
iomask => 0,
burstlen => burstlen,
nosync => nosync,
ahbbits => ahbbits,
devid => GAISLER_AHB2AVLA,
ddrbits => avldbits/2
)
port map (
rst => rst_ahb,
clk_ahb => clk_ahb,
ahbsi => ahbsi,
ahbso => ahbso,
request => request,
start_tog => start_tog,
response => response,
wbwaddr => wbwaddr,
wbwdata => wbwdata,
wbwrite => wbwrite,
wbwritebig => wbwritebig,
rbraddr => rbraddr,
rbrdata => rbrdata,
hwidth => gnd(0),
beid => gnd(3 downto 0)
);
be0: ahb2avl_async_be
generic map (
avldbits => avldbits,
avlabits => avlabits,
ahbbits => ahbbits,
burstlen => burstlen,
nosync => nosync
)
port map (
rst => rst_avl,
clk => clk_avl,
avlsi => avlsi,
avlso => avlso,
request => request,
start_tog => start_tog,
response => response,
wbraddr => wbraddr,
wbrdata => wbrdata,
rbwaddr => rbwaddr,
rbwdata => rbwdata,
rbwrite => rbwrite
);
wbuf: ddr2buf
generic map (tech => 0, wabits => wbuf_wabits, wdbits => wbuf_wdbits,
rabits => wbuf_rabits_r, rdbits => wbuf_rdbits,
sepclk => 1, wrfst => 0, testen => 0)
port map ( rclk => clk_avl, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0),
dataout => wbrdata, wclk => clk_ahb, write => wbwrite,
writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata,
testin => ahbsi.testin);
rbuf: ddr2buf
generic map (tech => 0, wabits => rbuf_wabits, wdbits => rbuf_wdbits,
rabits => rbuf_rabits, rdbits => rbuf_rdbits,
sepclk => 1, wrfst => 0, testen => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr,
dataout => rbrdata,
wclk => clk_avl, write => rbwrite,
writebig => '0', waddress => rbwaddr, datain => rbwdata,
testin => ahbsi.testin);
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_985 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_985;
architecture augh of cmp_985 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_985 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_985;
architecture augh of cmp_985 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3180.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p78n01i03180ent IS
END c14s01b00x00p78n01i03180ent;
ARCHITECTURE c14s01b00x00p78n01i03180arch OF c14s01b00x00p78n01i03180ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'leftof(15) = 14 and
roufbit'leftof(0) = 1 )
report "***PASSED TEST: c14s01b00x00p78n01i03180"
severity NOTE;
assert ( fourbit'leftof(15) = 14 and
roufbit'leftof(0) = 1 )
report "***FAILED TEST: c14s01b00x00p78n01i03180 - Predefined attribute LEFTOF for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p78n01i03180arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3180.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p78n01i03180ent IS
END c14s01b00x00p78n01i03180ent;
ARCHITECTURE c14s01b00x00p78n01i03180arch OF c14s01b00x00p78n01i03180ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'leftof(15) = 14 and
roufbit'leftof(0) = 1 )
report "***PASSED TEST: c14s01b00x00p78n01i03180"
severity NOTE;
assert ( fourbit'leftof(15) = 14 and
roufbit'leftof(0) = 1 )
report "***FAILED TEST: c14s01b00x00p78n01i03180 - Predefined attribute LEFTOF for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p78n01i03180arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3180.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p78n01i03180ent IS
END c14s01b00x00p78n01i03180ent;
ARCHITECTURE c14s01b00x00p78n01i03180arch OF c14s01b00x00p78n01i03180ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'leftof(15) = 14 and
roufbit'leftof(0) = 1 )
report "***PASSED TEST: c14s01b00x00p78n01i03180"
severity NOTE;
assert ( fourbit'leftof(15) = 14 and
roufbit'leftof(0) = 1 )
report "***FAILED TEST: c14s01b00x00p78n01i03180 - Predefined attribute LEFTOF for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p78n01i03180arch;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief This file implements RF-controller entity axi_rfctrl.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! @brief RF-front controller based on MAX2769 ICs.
--! @details This unit implements SPI interface with MAX2769 ICs
--! and interacts with the antenna control signals.
entity axi_rfctrl is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port (
nrst : in std_logic;
clk : in std_logic;
o_cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
--! @name Synthezator's SPI interface signals:
--! @brief Connects to MAX2769 IC.
--! @{
outSCLK : out std_logic;
outSDATA : out std_logic;
outCSn : out std_logic_vector(1 downto 0);
--! @}
--! @name Antenna control signals:
--! @brief RF front-end IO analog signals.
--! @{
inExtAntStat : in std_logic;
inExtAntDetect : in std_logic;
outExtAntEna : out std_logic;
outIntAntContr : out std_logic
--! @}
);
end;
architecture rtl of axi_rfctrl is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_RF_CONTROL,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of integer;
type registers is record
bank_axi : nasti_slave_bank_type;
conf1 : std_logic_vector(27 downto 0);
conf2 : std_logic_vector(27 downto 0);
conf3 : std_logic_vector(27 downto 0);
pllconf : std_logic_vector(27 downto 0);
div : std_logic_vector(27 downto 0);
fdiv : std_logic_vector(27 downto 0);
strm : std_logic_vector(27 downto 0);
clkdiv : std_logic_vector(27 downto 0);
test1 : std_logic_vector(27 downto 0);
test2 : std_logic_vector(27 downto 0);
scale : std_logic_vector(31 downto 0);
load_run : std_ulogic;
select_spi : std_logic_vector(1 downto 0);
loading : std_ulogic;
ScaleCnt : std_logic_vector(31 downto 0);
SClkPosedge : std_ulogic;
SClkNegedge : std_ulogic;
SCLK : std_ulogic;
BitCnt : integer range 0 to 33;
CS : std_ulogic; --!! not inversed!!
WordSelector : std_logic_vector(8 downto 0);
SendWord : std_logic_vector(31 downto 0);
ExtAntEna : std_ulogic;
IntAntContr : std_ulogic;
end record;
signal r, rin : registers;
begin
comblogic : process(nrst, r, i_axi, i_glo_ld, i_gps_ld, inExtAntStat, inExtAntDetect)
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_ALIGN_BYTES-1 downto 0);
variable v : registers;
variable readdata : std_logic_vector(31 downto 0);
variable wNewWord : std_ulogic;
begin
v := r;
v.load_run := '0';
procedureAxi4(i_axi, xconfig, r.bank_axi, v.bank_axi);
-- read registers:
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
tmp := (others => '0');
case raddr_reg(n) is
when 0 => tmp := "0000" & r.conf1;
when 1 => tmp := "0000" & r.conf2;
when 2 => tmp := "0000" & r.conf3;
when 3 => tmp := "0000" & r.pllconf;
when 4 => tmp := "0000" & r.div;
when 5 => tmp := "0000" & r.fdiv;
when 6 => tmp := "0000" & r.strm;
when 7 => tmp := "0000" & r.clkdiv;
when 8 => tmp := "0000" & r.test1;
when 9 => tmp := "0000" & r.test2;
when 10 => tmp := r.scale;
when 11 =>
tmp(9 downto 0):= conv_std_logic_vector(r.BitCnt,6) & '0' & r.loading & i_glo_ld & i_gps_ld;
when 15 =>
tmp(5 downto 0) := inExtAntStat & inExtAntDetect & "00"& r.IntAntContr & r.ExtAntEna;
when others =>
end case;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
-- write registers
if i_axi.w_valid = '1' and
r.bank_axi.wstate = wtrans and
r.bank_axi.wresp = NASTI_RESP_OKAY then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
tmp := i_axi.w_data(32*(n+1)-1 downto 32*n);
wstrb := i_axi.w_strb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n);
if conv_integer(wstrb) /= 0 then
case waddr_reg(n) is
when 0 => v.conf1 := tmp(27 downto 0);
when 1 => v.conf2 := tmp(27 downto 0);
when 2 => v.conf3 := tmp(27 downto 0);
when 3 => v.pllconf := tmp(27 downto 0);
when 4 => v.div := tmp(27 downto 0);
when 5 => v.fdiv := tmp(27 downto 0);
when 6 => v.strm := tmp(27 downto 0);
when 7 => v.clkdiv := tmp(27 downto 0);
when 8 => v.test1 := tmp(27 downto 0);
when 9 => v.test2 := tmp(27 downto 0);
when 10 =>
if tmp(31 downto 1) = zero32(31 downto 1) then
v.scale := conv_std_logic_vector(2,32);
else
v.scale := tmp;
end if;
when 11 =>
v.load_run := '1';
v.ScaleCnt := (others => '0');
v.BitCnt := 0;
if tmp = zero32 then
v.select_spi := "01";
elsif tmp = conv_std_logic_vector(1,32) then
v.select_spi := "10";
else
v.select_spi := "00";
end if;
when 15 =>
v.ExtAntEna := tmp(0);
v.IntAntContr := tmp(1);
when others =>
end case;
end if;
end loop;
end if;
-- loading procedure:
if((r.SClkNegedge='1') and (r.BitCnt=33)) then wNewWord := '1';
else wNewWord := '0'; end if;
if(r.load_run='1') then v.loading := '1';
elsif((wNewWord='1')and(r.WordSelector="000000000")) then v.loading := '0'; end if;
if((r.loading and r.SClkNegedge)='1') then v.ScaleCnt := (others => '0');
elsif(r.loading='1') then v.ScaleCnt := r.ScaleCnt+1; end if;
-- scaler pulse:
if((r.scale/=zero32)and(r.ScaleCnt=r.scale)) then v.SClkNegedge := '1';
else v.SClkNegedge := '0'; end if;
if((r.scale/=zero32)and(r.ScaleCnt=('0'& r.scale(31 downto 1)))) then v.SClkPosedge := '1';
else v.SClkPosedge := '0'; end if;
-- SCLK former:
if(r.SClkPosedge='1') then v.SCLK := '1';
elsif(r.SClkNegedge='1') then v.SCLK := '0'; end if;
-- Not inversed CS signal:
if((r.SClkNegedge='1')and(r.BitCnt=33)) then v.BitCnt := 0;
elsif(r.SClkNegedge='1') then v.BitCnt := r.BitCnt + 1; end if;
if((r.BitCnt=0)or((r.BitCnt=33))) then v.CS := '0';
else v.CS := '1'; end if;
-- Word multiplexer:
if(r.load_run='1') then v.WordSelector := "000000001";
elsif(wNewWord='1') then v.WordSelector := r.WordSelector(7 downto 0) & '0'; end if;
if(r.load_run='1') then v.SendWord := r.conf1 & "0000";
elsif((wNewWord='1')and(r.WordSelector(0)='1')) then v.SendWord := r.conf2 & "0001";
elsif((wNewWord='1')and(r.WordSelector(1)='1')) then v.SendWord := r.conf3 & "0010";
elsif((wNewWord='1')and(r.WordSelector(2)='1')) then v.SendWord := r.pllconf & "0011";
elsif((wNewWord='1')and(r.WordSelector(3)='1')) then v.SendWord := r.div & "0100";
elsif((wNewWord='1')and(r.WordSelector(4)='1')) then v.SendWord := r.fdiv & "0101";
elsif((wNewWord='1')and(r.WordSelector(5)='1')) then v.SendWord := r.strm & "0110";
elsif((wNewWord='1')and(r.WordSelector(6)='1')) then v.SendWord := r.clkdiv & "0111";
elsif((wNewWord='1')and(r.WordSelector(7)='1')) then v.SendWord := r.test1 & "1000";
elsif((wNewWord='1')and(r.WordSelector(8)='1')) then v.SendWord := r.test2 & "1001";
elsif((r.SClkNegedge='1')and(r.BitCnt/=0)and(r.BitCnt/=33)) then v.SendWord := r.SendWord(30 downto 0)&'0'; end if;
-- reset operation
if nrst = '0' then
v.bank_axi := NASTI_SLAVE_BANK_RESET;
v.load_run := '0';
v.conf1 := (others => '0');
v.conf2 := (others => '0');
v.conf3 := (others => '0');
v.pllconf := (others => '0');
v.div := (others => '0');
v.fdiv := (others => '0');
v.strm := (others => '0');
v.clkdiv := (others => '0');
v.test1 := (others => '0');
v.test2 := (others => '0');
v.scale := (others => '0');
v.SCLK := '0';
v.BitCnt := 0;
v.CS := '0';
v.select_spi := (others => '0');
v.ExtAntEna := '0';
v.SendWord := (others=>'0');
v.loading := '0';
v.ScaleCnt := (others => '0');
v.WordSelector := (others => '0');
v.IntAntContr := '0';
end if;
rin <= v;
o_axi <= functionAxi4Output(r.bank_axi, rdata);
end process;
o_cfg <= xconfig;
outSCLK <= r.SCLK;
outCSn(0) <= not(r.CS and r.select_spi(0));
outCSn(1) <= not(r.CS and r.select_spi(1));
outSDATA <= r.SendWord(31);
outExtAntEna <= r.ExtAntEna;
outIntAntContr <= r.IntAntContr;
-- registers:
regs : process(clk, nrst) begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief This file implements RF-controller entity axi_rfctrl.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! @brief RF-front controller based on MAX2769 ICs.
--! @details This unit implements SPI interface with MAX2769 ICs
--! and interacts with the antenna control signals.
entity axi_rfctrl is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port (
nrst : in std_logic;
clk : in std_logic;
o_cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
--! @name Synthezator's SPI interface signals:
--! @brief Connects to MAX2769 IC.
--! @{
outSCLK : out std_logic;
outSDATA : out std_logic;
outCSn : out std_logic_vector(1 downto 0);
--! @}
--! @name Antenna control signals:
--! @brief RF front-end IO analog signals.
--! @{
inExtAntStat : in std_logic;
inExtAntDetect : in std_logic;
outExtAntEna : out std_logic;
outIntAntContr : out std_logic
--! @}
);
end;
architecture rtl of axi_rfctrl is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_RF_CONTROL,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of integer;
type registers is record
bank_axi : nasti_slave_bank_type;
conf1 : std_logic_vector(27 downto 0);
conf2 : std_logic_vector(27 downto 0);
conf3 : std_logic_vector(27 downto 0);
pllconf : std_logic_vector(27 downto 0);
div : std_logic_vector(27 downto 0);
fdiv : std_logic_vector(27 downto 0);
strm : std_logic_vector(27 downto 0);
clkdiv : std_logic_vector(27 downto 0);
test1 : std_logic_vector(27 downto 0);
test2 : std_logic_vector(27 downto 0);
scale : std_logic_vector(31 downto 0);
load_run : std_ulogic;
select_spi : std_logic_vector(1 downto 0);
loading : std_ulogic;
ScaleCnt : std_logic_vector(31 downto 0);
SClkPosedge : std_ulogic;
SClkNegedge : std_ulogic;
SCLK : std_ulogic;
BitCnt : integer range 0 to 33;
CS : std_ulogic; --!! not inversed!!
WordSelector : std_logic_vector(8 downto 0);
SendWord : std_logic_vector(31 downto 0);
ExtAntEna : std_ulogic;
IntAntContr : std_ulogic;
end record;
signal r, rin : registers;
begin
comblogic : process(nrst, r, i_axi, i_glo_ld, i_gps_ld, inExtAntStat, inExtAntDetect)
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_ALIGN_BYTES-1 downto 0);
variable v : registers;
variable readdata : std_logic_vector(31 downto 0);
variable wNewWord : std_ulogic;
begin
v := r;
v.load_run := '0';
procedureAxi4(i_axi, xconfig, r.bank_axi, v.bank_axi);
-- read registers:
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
tmp := (others => '0');
case raddr_reg(n) is
when 0 => tmp := "0000" & r.conf1;
when 1 => tmp := "0000" & r.conf2;
when 2 => tmp := "0000" & r.conf3;
when 3 => tmp := "0000" & r.pllconf;
when 4 => tmp := "0000" & r.div;
when 5 => tmp := "0000" & r.fdiv;
when 6 => tmp := "0000" & r.strm;
when 7 => tmp := "0000" & r.clkdiv;
when 8 => tmp := "0000" & r.test1;
when 9 => tmp := "0000" & r.test2;
when 10 => tmp := r.scale;
when 11 =>
tmp(9 downto 0):= conv_std_logic_vector(r.BitCnt,6) & '0' & r.loading & i_glo_ld & i_gps_ld;
when 15 =>
tmp(5 downto 0) := inExtAntStat & inExtAntDetect & "00"& r.IntAntContr & r.ExtAntEna;
when others =>
end case;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
-- write registers
if i_axi.w_valid = '1' and
r.bank_axi.wstate = wtrans and
r.bank_axi.wresp = NASTI_RESP_OKAY then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
tmp := i_axi.w_data(32*(n+1)-1 downto 32*n);
wstrb := i_axi.w_strb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n);
if conv_integer(wstrb) /= 0 then
case waddr_reg(n) is
when 0 => v.conf1 := tmp(27 downto 0);
when 1 => v.conf2 := tmp(27 downto 0);
when 2 => v.conf3 := tmp(27 downto 0);
when 3 => v.pllconf := tmp(27 downto 0);
when 4 => v.div := tmp(27 downto 0);
when 5 => v.fdiv := tmp(27 downto 0);
when 6 => v.strm := tmp(27 downto 0);
when 7 => v.clkdiv := tmp(27 downto 0);
when 8 => v.test1 := tmp(27 downto 0);
when 9 => v.test2 := tmp(27 downto 0);
when 10 =>
if tmp(31 downto 1) = zero32(31 downto 1) then
v.scale := conv_std_logic_vector(2,32);
else
v.scale := tmp;
end if;
when 11 =>
v.load_run := '1';
v.ScaleCnt := (others => '0');
v.BitCnt := 0;
if tmp = zero32 then
v.select_spi := "01";
elsif tmp = conv_std_logic_vector(1,32) then
v.select_spi := "10";
else
v.select_spi := "00";
end if;
when 15 =>
v.ExtAntEna := tmp(0);
v.IntAntContr := tmp(1);
when others =>
end case;
end if;
end loop;
end if;
-- loading procedure:
if((r.SClkNegedge='1') and (r.BitCnt=33)) then wNewWord := '1';
else wNewWord := '0'; end if;
if(r.load_run='1') then v.loading := '1';
elsif((wNewWord='1')and(r.WordSelector="000000000")) then v.loading := '0'; end if;
if((r.loading and r.SClkNegedge)='1') then v.ScaleCnt := (others => '0');
elsif(r.loading='1') then v.ScaleCnt := r.ScaleCnt+1; end if;
-- scaler pulse:
if((r.scale/=zero32)and(r.ScaleCnt=r.scale)) then v.SClkNegedge := '1';
else v.SClkNegedge := '0'; end if;
if((r.scale/=zero32)and(r.ScaleCnt=('0'& r.scale(31 downto 1)))) then v.SClkPosedge := '1';
else v.SClkPosedge := '0'; end if;
-- SCLK former:
if(r.SClkPosedge='1') then v.SCLK := '1';
elsif(r.SClkNegedge='1') then v.SCLK := '0'; end if;
-- Not inversed CS signal:
if((r.SClkNegedge='1')and(r.BitCnt=33)) then v.BitCnt := 0;
elsif(r.SClkNegedge='1') then v.BitCnt := r.BitCnt + 1; end if;
if((r.BitCnt=0)or((r.BitCnt=33))) then v.CS := '0';
else v.CS := '1'; end if;
-- Word multiplexer:
if(r.load_run='1') then v.WordSelector := "000000001";
elsif(wNewWord='1') then v.WordSelector := r.WordSelector(7 downto 0) & '0'; end if;
if(r.load_run='1') then v.SendWord := r.conf1 & "0000";
elsif((wNewWord='1')and(r.WordSelector(0)='1')) then v.SendWord := r.conf2 & "0001";
elsif((wNewWord='1')and(r.WordSelector(1)='1')) then v.SendWord := r.conf3 & "0010";
elsif((wNewWord='1')and(r.WordSelector(2)='1')) then v.SendWord := r.pllconf & "0011";
elsif((wNewWord='1')and(r.WordSelector(3)='1')) then v.SendWord := r.div & "0100";
elsif((wNewWord='1')and(r.WordSelector(4)='1')) then v.SendWord := r.fdiv & "0101";
elsif((wNewWord='1')and(r.WordSelector(5)='1')) then v.SendWord := r.strm & "0110";
elsif((wNewWord='1')and(r.WordSelector(6)='1')) then v.SendWord := r.clkdiv & "0111";
elsif((wNewWord='1')and(r.WordSelector(7)='1')) then v.SendWord := r.test1 & "1000";
elsif((wNewWord='1')and(r.WordSelector(8)='1')) then v.SendWord := r.test2 & "1001";
elsif((r.SClkNegedge='1')and(r.BitCnt/=0)and(r.BitCnt/=33)) then v.SendWord := r.SendWord(30 downto 0)&'0'; end if;
-- reset operation
if nrst = '0' then
v.bank_axi := NASTI_SLAVE_BANK_RESET;
v.load_run := '0';
v.conf1 := (others => '0');
v.conf2 := (others => '0');
v.conf3 := (others => '0');
v.pllconf := (others => '0');
v.div := (others => '0');
v.fdiv := (others => '0');
v.strm := (others => '0');
v.clkdiv := (others => '0');
v.test1 := (others => '0');
v.test2 := (others => '0');
v.scale := (others => '0');
v.SCLK := '0';
v.BitCnt := 0;
v.CS := '0';
v.select_spi := (others => '0');
v.ExtAntEna := '0';
v.SendWord := (others=>'0');
v.loading := '0';
v.ScaleCnt := (others => '0');
v.WordSelector := (others => '0');
v.IntAntContr := '0';
end if;
rin <= v;
o_axi <= functionAxi4Output(r.bank_axi, rdata);
end process;
o_cfg <= xconfig;
outSCLK <= r.SCLK;
outCSn(0) <= not(r.CS and r.select_spi(0));
outCSn(1) <= not(r.CS and r.select_spi(1));
outSDATA <= r.SendWord(31);
outExtAntEna <= r.ExtAntEna;
outIntAntContr <= r.IntAntContr;
-- registers:
regs : process(clk, nrst) begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:45:06 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_2/blk_mem_gen_2_funcsim.vhdl
-- Design : blk_mem_gen_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_prim_wrapper is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end blk_mem_gen_2blk_mem_gen_prim_wrapper;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_prim_width is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end blk_mem_gen_2blk_mem_gen_prim_width;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.blk_mem_gen_2blk_mem_gen_prim_wrapper
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end blk_mem_gen_2blk_mem_gen_generic_cstr;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.blk_mem_gen_2blk_mem_gen_prim_width
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 6) => dina(25 downto 24),
dina(5 downto 4) => dina(17 downto 16),
dina(3 downto 2) => dina(9 downto 8),
dina(1 downto 0) => dina(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 6) => dina(27 downto 26),
dina(5 downto 4) => dina(19 downto 18),
dina(3 downto 2) => dina(11 downto 10),
dina(1 downto 0) => dina(3 downto 2),
doutb(1 downto 0) => doutb(3 downto 2),
enb => enb,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 6) => dina(29 downto 28),
dina(5 downto 4) => dina(21 downto 20),
dina(3 downto 2) => dina(13 downto 12),
dina(1 downto 0) => dina(5 downto 4),
doutb(1 downto 0) => doutb(5 downto 4),
enb => enb,
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 6) => dina(31 downto 30),
dina(5 downto 4) => dina(23 downto 22),
dina(3 downto 2) => dina(15 downto 14),
dina(1 downto 0) => dina(7 downto 6),
doutb(1 downto 0) => doutb(7 downto 6),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_top : entity is "blk_mem_gen_top";
end blk_mem_gen_2blk_mem_gen_top;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_top is
begin
\valid.cstr\: entity work.blk_mem_gen_2blk_mem_gen_generic_cstr
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_v8_2_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end blk_mem_gen_2blk_mem_gen_v8_2_synth;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.blk_mem_gen_2blk_mem_gen_top
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
attribute C_FAMILY : string;
attribute C_FAMILY of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "./";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 4;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "no_coe_file_loaded";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_2.mem";
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "READ_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 32;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 32;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 4096;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 4096;
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 12;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "READ_FIRST";
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 16384;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 14;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "4";
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 10.9418 mW";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "yes";
end \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(31) <= \<const0>\;
douta(30) <= \<const0>\;
douta(29) <= \<const0>\;
douta(28) <= \<const0>\;
douta(27) <= \<const0>\;
douta(26) <= \<const0>\;
douta(25) <= \<const0>\;
douta(24) <= \<const0>\;
douta(23) <= \<const0>\;
douta(22) <= \<const0>\;
douta(21) <= \<const0>\;
douta(20) <= \<const0>\;
douta(19) <= \<const0>\;
douta(18) <= \<const0>\;
douta(17) <= \<const0>\;
douta(16) <= \<const0>\;
douta(15) <= \<const0>\;
douta(14) <= \<const0>\;
douta(13) <= \<const0>\;
douta(12) <= \<const0>\;
douta(11) <= \<const0>\;
douta(10) <= \<const0>\;
douta(9) <= \<const0>\;
douta(8) <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.blk_mem_gen_2blk_mem_gen_v8_2_synth
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2 is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of blk_mem_gen_2 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of blk_mem_gen_2 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of blk_mem_gen_2 : entity is "blk_mem_gen_v8_2,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of blk_mem_gen_2 : entity is "blk_mem_gen_2,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of blk_mem_gen_2 : entity is "blk_mem_gen_2,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 10.9418 mW}";
end blk_mem_gen_2;
architecture STRUCTURE of blk_mem_gen_2 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 1;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 10.9418 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "blk_mem_gen_2.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 4096;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 4096;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "READ_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
dina(31 downto 0) => dina(31 downto 0),
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(31 downto 0) => NLW_U0_douta_UNCONNECTED(31 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
eccpipece => '0',
ena => '0',
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_IO_STBX : in std_logic;
MCU_LCD_WR : in std_logic;
MCU_ADDR : in std_logic;
MCU_LCD_TE : out std_logic;
MCU_P2_8 : in std_logic;
MCU_LCD_RD : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(15 downto 0);
LCD_TE : in std_logic;
LCD_BACKLIGHT : out std_logic
);
end top;
architecture rtl of top is
signal switches : std_logic_vector(7 downto 0);
type data_direction_t is (from_mcu, to_mcu);
signal data_dir : data_direction_t;
signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
signal mcu_data_out_io : std_logic_vector(7 downto 0);
signal mcu_data_out : std_logic_vector(7 downto 0);
signal mcu_data_in : std_logic_vector(7 downto 0);
signal lcd_data_in : std_logic_vector(15 downto 0);
signal lcd_data_in_mux : std_logic_vector(7 downto 0);
signal lcd_data_out : std_logic_vector(15 downto 0);
signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_reset_q : std_logic := '1';
signal lcd_backlight_q : std_logic := '0';
signal dir_read : boolean;
signal dir_write : boolean;
signal lcd_read_strobe : boolean;
signal lcd_write_strobe : boolean;
signal lcd_write : boolean;
signal io_strobe : boolean;
signal io_read_strobe : boolean;
signal io_write_strobe : boolean;
begin
-- I/O data
switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
LCD_BACKLIGHT <= lcd_backlight_q;
MCU_LCD_TE <= LCD_TE;
-- State management
data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
dir_read <= (data_dir = to_mcu);
dir_write <= (data_dir = from_mcu);
io_strobe <= (MCU_IO_STBX = '0');
io_read_strobe <= io_strobe and dir_read;
lcd_read_strobe <= (MCU_LCD_RD = '1');
lcd_write <= not lcd_read_strobe;
-- LCD interface
LCD_RS <= MCU_ADDR;
LCD_RDX <= not MCU_LCD_RD;
LCD_WRX <= not MCU_LCD_WR;
lcd_data_out <= lcd_data_out_q & mcu_data_in;
lcd_data_in <= LCD_DB;
LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
LCD_RESETX <= not lcd_reset_q;
-- MCU interface
mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
mcu_data_out_io <= switches;
mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
mcu_data_in <= MCU_D;
MCU_D <= mcu_data_out when dir_read else (others => 'Z');
-- Synchronous behaviors:
-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
process(MCU_LCD_WR, mcu_data_in)
begin
if rising_edge(MCU_LCD_WR) then
lcd_data_out_q <= mcu_data_in;
end if;
end process;
-- LCD read: Capture LCD low byte on LCD_RD falling edge.
process(MCU_LCD_RD, lcd_data_in)
begin
if falling_edge(MCU_LCD_RD) then
lcd_data_in_q <= lcd_data_in(7 downto 0);
end if;
end process;
-- I/O write (to resistive touch panel): Capture data from
-- MCU and hold on TP pins until further notice.
process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
begin
if rising_edge(MCU_IO_STBX) and dir_write then
if MCU_ADDR = '0' then
tp_q <= mcu_data_in;
else
lcd_reset_q <= mcu_data_in(0);
lcd_backlight_q <= mcu_data_in(7);
end if;
end if;
end process;
end rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
------------------------------------------------------------------------------------------------------------------------
-- Simple Port I/O
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-16 V0.01 zelenkaj First version
-- 2010-10-04 V0.02 zelenkaj Bugfix: PORTDIR was mapped incorrectly (according to doc) to Avalon bus
-- 2010-11-23 V0.03 zelenkaj Added Operational Flag to portio
-- Added counter for valid assertion duration
-- 2011-04-20 V0.10 zelenkaj Added synchronizer at inputs
-- 2011-12-02 V0.11 zelenkaj Added I, O and T instead of IO ports
-- 2012-03-16 V0.12 zelenkaj Traveled back to the past to change the version history
-- Removed readdata register (saves resources)
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity portio is
generic (
pioValLen_g : integer := 50; --clock ticks of pcp_clk
pioGenIoBuf_g : boolean := true
);
port (
s0_address : in std_logic;
s0_read : in std_logic;
s0_readdata : out std_logic_vector(31 downto 0);
s0_write : in std_logic;
s0_writedata : in std_logic_vector(31 downto 0);
s0_byteenable : in std_logic_vector(3 downto 0);
s0_waitrequest : out std_logic;
clk : in std_logic;
reset : in std_logic;
x_pconfig : in std_logic_vector(3 downto 0);
x_portInLatch : in std_logic_vector(3 downto 0);
x_portOutValid : out std_logic_vector(3 downto 0);
x_portio : inout std_logic_vector(31 downto 0);
x_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
x_portio_O : out std_logic_vector(31 downto 0);
x_portio_T : out std_logic_vector(31 downto 0);
x_operational : out std_logic
);
end entity portio;
architecture rtl of portio is
signal sPortConfig : std_logic_vector(x_pconfig'range);
signal sPortOut : std_logic_vector(x_portio'range);
signal sPortIn, sPortIn_s, sPortInL : std_logic_vector(x_portio'range);
signal x_portInLatch_s : std_logic_vector(x_portInLatch'range);
signal x_operational_s : std_logic;
signal x_portOutValid_s : std_logic_vector(x_portOutValid'range);
begin
sPortConfig <= x_pconfig;
x_operational <= x_operational_s;
portGen : for i in 3 downto 0 generate
genIoBuf : if pioGenIoBuf_g generate
begin
--if port configuration bit is set to '0', the appropriate port-byte is an output
x_portio((i+1)*8-1 downto (i+1)*8-8) <= sPortOut((i+1)*8-1 downto (i+1)*8-8) when sPortConfig(i) = '0' else (others => 'Z');
--if port configuration bit is set to '1', the appropriate port-byte is forwarded to the portio registers for the PCP
sPortIn((i+1)*8-1 downto (i+1)*8-8) <= x_portio((i+1)*8-1 downto (i+1)*8-8) when sPortConfig(i) = '1' else (others => '0');
end generate;
dontGenIoBuf : if not pioGenIoBuf_g generate
begin
x_portio_O((i+1)*8-1 downto (i+1)*8-8) <= sPortOut((i+1)*8-1 downto (i+1)*8-8);
sPortIn((i+1)*8-1 downto (i+1)*8-8) <= x_portio_I((i+1)*8-1 downto (i+1)*8-8);
--if port configuration bit is set to '0', the appropriate port-byte is an output ('0')
--if port configuration bit is set to '1', the appropriate port-byte is an input ('1')
x_portio_T((i+1)*8-1 downto (i+1)*8-8) <= (others => '0') when sPortConfig(i) = '0' else (others => '1');
end generate;
end generate;
--Avalon interface
avalonPro : process(clk, reset)
begin
if reset = '1' then
x_portOutValid_s <= (others => '0');
sPortOut <= (others => '0');
x_operational_s <= '0';
elsif clk = '1' and clk'event then
x_portOutValid_s <= (others => '0');
if s0_write = '1' then
case s0_address is
when '0' => --write port
for i in 3 downto 0 loop
if s0_byteenable(i) = '1' then
sPortOut((i+1)*8-1 downto (i+1)*8-8) <= s0_writedata((i+1)*8-1 downto (i+1)*8-8);
x_portOutValid_s(i) <= '1';
end if;
end loop;
when '1' => --write to config register operational flag
if s0_byteenable(3) = '1' then
x_operational_s <= s0_writedata(s0_writedata'left);
end if;
when others =>
end case;
end if;
end if;
end process;
s0_readdata <= sPortInL when s0_read = '1' and s0_address = '0' else
x_operational_s & "000" & x"00000" & x"0" & sPortConfig;
thePortioCnters : for i in 0 to 3 generate
thePortioCnt : entity work.portio_cnt
generic map (
maxVal => pioValLen_g
)
port map (
clk => clk,
rst => reset,
pulse => x_portOutValid_s(i),
valid => x_portOutValid(i)
);
end generate;
--latch input signals
latchInPro : process(clk, reset)
begin
if reset = '1' then
sPortInL <= (others => '0');
elsif clk = '1' and clk'event then
for i in 3 downto 0 loop
if x_portInLatch_s(i) = '1' then
sPortInL((i+1)*8-1 downto (i+1)*8-8) <= sPortIn_s((i+1)*8-1 downto (i+1)*8-8);
end if;
end loop;
end if;
end process;
-- waitrequest signals
theWaitrequestGenerators : block
signal s0_rd_ack, s0_wr_ack : std_logic;
begin
-- PCP
thePcpWrWaitReqAckGen : entity work.req_ack
generic map (
zero_delay_g => true
)
port map (
clk => clk,
rst => reset,
enable => s0_write,
ack => s0_wr_ack
);
thePcpRdWaitReqAckGen : entity work.req_ack
generic map (
zero_delay_g => true
)
port map (
clk => clk,
rst => reset,
enable => s0_read,
ack => s0_rd_ack
);
s0_waitrequest <= not(s0_rd_ack or s0_wr_ack);
end block;
--synchronize input signals
genSyncInputs : for i in sPortIn'range generate
syncInputs : entity work.sync
port map (
din => sPortIn(i),
dout => sPortIn_s(i),
clk => clk,
rst => reset
);
end generate;
--synchronize latch signals
genSyncLatch : for i in x_portInLatch'range generate
syncInputs : entity work.sync
port map (
din => x_portInLatch(i),
dout => x_portInLatch_s(i),
clk => clk,
rst => reset
);
end generate;
end architecture rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- Simple Port I/O
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-16 V0.01 zelenkaj First version
-- 2010-10-04 V0.02 zelenkaj Bugfix: PORTDIR was mapped incorrectly (according to doc) to Avalon bus
-- 2010-11-23 V0.03 zelenkaj Added Operational Flag to portio
-- Added counter for valid assertion duration
-- 2011-04-20 V0.10 zelenkaj Added synchronizer at inputs
-- 2011-12-02 V0.11 zelenkaj Added I, O and T instead of IO ports
-- 2012-03-16 V0.12 zelenkaj Traveled back to the past to change the version history
-- Removed readdata register (saves resources)
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity portio is
generic (
pioValLen_g : integer := 50; --clock ticks of pcp_clk
pioGenIoBuf_g : boolean := true
);
port (
s0_address : in std_logic;
s0_read : in std_logic;
s0_readdata : out std_logic_vector(31 downto 0);
s0_write : in std_logic;
s0_writedata : in std_logic_vector(31 downto 0);
s0_byteenable : in std_logic_vector(3 downto 0);
s0_waitrequest : out std_logic;
clk : in std_logic;
reset : in std_logic;
x_pconfig : in std_logic_vector(3 downto 0);
x_portInLatch : in std_logic_vector(3 downto 0);
x_portOutValid : out std_logic_vector(3 downto 0);
x_portio : inout std_logic_vector(31 downto 0);
x_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
x_portio_O : out std_logic_vector(31 downto 0);
x_portio_T : out std_logic_vector(31 downto 0);
x_operational : out std_logic
);
end entity portio;
architecture rtl of portio is
signal sPortConfig : std_logic_vector(x_pconfig'range);
signal sPortOut : std_logic_vector(x_portio'range);
signal sPortIn, sPortIn_s, sPortInL : std_logic_vector(x_portio'range);
signal x_portInLatch_s : std_logic_vector(x_portInLatch'range);
signal x_operational_s : std_logic;
signal x_portOutValid_s : std_logic_vector(x_portOutValid'range);
begin
sPortConfig <= x_pconfig;
x_operational <= x_operational_s;
portGen : for i in 3 downto 0 generate
genIoBuf : if pioGenIoBuf_g generate
begin
--if port configuration bit is set to '0', the appropriate port-byte is an output
x_portio((i+1)*8-1 downto (i+1)*8-8) <= sPortOut((i+1)*8-1 downto (i+1)*8-8) when sPortConfig(i) = '0' else (others => 'Z');
--if port configuration bit is set to '1', the appropriate port-byte is forwarded to the portio registers for the PCP
sPortIn((i+1)*8-1 downto (i+1)*8-8) <= x_portio((i+1)*8-1 downto (i+1)*8-8) when sPortConfig(i) = '1' else (others => '0');
end generate;
dontGenIoBuf : if not pioGenIoBuf_g generate
begin
x_portio_O((i+1)*8-1 downto (i+1)*8-8) <= sPortOut((i+1)*8-1 downto (i+1)*8-8);
sPortIn((i+1)*8-1 downto (i+1)*8-8) <= x_portio_I((i+1)*8-1 downto (i+1)*8-8);
--if port configuration bit is set to '0', the appropriate port-byte is an output ('0')
--if port configuration bit is set to '1', the appropriate port-byte is an input ('1')
x_portio_T((i+1)*8-1 downto (i+1)*8-8) <= (others => '0') when sPortConfig(i) = '0' else (others => '1');
end generate;
end generate;
--Avalon interface
avalonPro : process(clk, reset)
begin
if reset = '1' then
x_portOutValid_s <= (others => '0');
sPortOut <= (others => '0');
x_operational_s <= '0';
elsif clk = '1' and clk'event then
x_portOutValid_s <= (others => '0');
if s0_write = '1' then
case s0_address is
when '0' => --write port
for i in 3 downto 0 loop
if s0_byteenable(i) = '1' then
sPortOut((i+1)*8-1 downto (i+1)*8-8) <= s0_writedata((i+1)*8-1 downto (i+1)*8-8);
x_portOutValid_s(i) <= '1';
end if;
end loop;
when '1' => --write to config register operational flag
if s0_byteenable(3) = '1' then
x_operational_s <= s0_writedata(s0_writedata'left);
end if;
when others =>
end case;
end if;
end if;
end process;
s0_readdata <= sPortInL when s0_read = '1' and s0_address = '0' else
x_operational_s & "000" & x"00000" & x"0" & sPortConfig;
thePortioCnters : for i in 0 to 3 generate
thePortioCnt : entity work.portio_cnt
generic map (
maxVal => pioValLen_g
)
port map (
clk => clk,
rst => reset,
pulse => x_portOutValid_s(i),
valid => x_portOutValid(i)
);
end generate;
--latch input signals
latchInPro : process(clk, reset)
begin
if reset = '1' then
sPortInL <= (others => '0');
elsif clk = '1' and clk'event then
for i in 3 downto 0 loop
if x_portInLatch_s(i) = '1' then
sPortInL((i+1)*8-1 downto (i+1)*8-8) <= sPortIn_s((i+1)*8-1 downto (i+1)*8-8);
end if;
end loop;
end if;
end process;
-- waitrequest signals
theWaitrequestGenerators : block
signal s0_rd_ack, s0_wr_ack : std_logic;
begin
-- PCP
thePcpWrWaitReqAckGen : entity work.req_ack
generic map (
zero_delay_g => true
)
port map (
clk => clk,
rst => reset,
enable => s0_write,
ack => s0_wr_ack
);
thePcpRdWaitReqAckGen : entity work.req_ack
generic map (
zero_delay_g => true
)
port map (
clk => clk,
rst => reset,
enable => s0_read,
ack => s0_rd_ack
);
s0_waitrequest <= not(s0_rd_ack or s0_wr_ack);
end block;
--synchronize input signals
genSyncInputs : for i in sPortIn'range generate
syncInputs : entity work.sync
port map (
din => sPortIn(i),
dout => sPortIn_s(i),
clk => clk,
rst => reset
);
end generate;
--synchronize latch signals
genSyncLatch : for i in x_portInLatch'range generate
syncInputs : entity work.sync
port map (
din => x_portInLatch(i),
dout => x_portInLatch_s(i),
clk => clk,
rst => reset
);
end generate;
end architecture rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- Simple Port I/O
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-16 V0.01 zelenkaj First version
-- 2010-10-04 V0.02 zelenkaj Bugfix: PORTDIR was mapped incorrectly (according to doc) to Avalon bus
-- 2010-11-23 V0.03 zelenkaj Added Operational Flag to portio
-- Added counter for valid assertion duration
-- 2011-04-20 V0.10 zelenkaj Added synchronizer at inputs
-- 2011-12-02 V0.11 zelenkaj Added I, O and T instead of IO ports
-- 2012-03-16 V0.12 zelenkaj Traveled back to the past to change the version history
-- Removed readdata register (saves resources)
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity portio is
generic (
pioValLen_g : integer := 50; --clock ticks of pcp_clk
pioGenIoBuf_g : boolean := true
);
port (
s0_address : in std_logic;
s0_read : in std_logic;
s0_readdata : out std_logic_vector(31 downto 0);
s0_write : in std_logic;
s0_writedata : in std_logic_vector(31 downto 0);
s0_byteenable : in std_logic_vector(3 downto 0);
s0_waitrequest : out std_logic;
clk : in std_logic;
reset : in std_logic;
x_pconfig : in std_logic_vector(3 downto 0);
x_portInLatch : in std_logic_vector(3 downto 0);
x_portOutValid : out std_logic_vector(3 downto 0);
x_portio : inout std_logic_vector(31 downto 0);
x_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
x_portio_O : out std_logic_vector(31 downto 0);
x_portio_T : out std_logic_vector(31 downto 0);
x_operational : out std_logic
);
end entity portio;
architecture rtl of portio is
signal sPortConfig : std_logic_vector(x_pconfig'range);
signal sPortOut : std_logic_vector(x_portio'range);
signal sPortIn, sPortIn_s, sPortInL : std_logic_vector(x_portio'range);
signal x_portInLatch_s : std_logic_vector(x_portInLatch'range);
signal x_operational_s : std_logic;
signal x_portOutValid_s : std_logic_vector(x_portOutValid'range);
begin
sPortConfig <= x_pconfig;
x_operational <= x_operational_s;
portGen : for i in 3 downto 0 generate
genIoBuf : if pioGenIoBuf_g generate
begin
--if port configuration bit is set to '0', the appropriate port-byte is an output
x_portio((i+1)*8-1 downto (i+1)*8-8) <= sPortOut((i+1)*8-1 downto (i+1)*8-8) when sPortConfig(i) = '0' else (others => 'Z');
--if port configuration bit is set to '1', the appropriate port-byte is forwarded to the portio registers for the PCP
sPortIn((i+1)*8-1 downto (i+1)*8-8) <= x_portio((i+1)*8-1 downto (i+1)*8-8) when sPortConfig(i) = '1' else (others => '0');
end generate;
dontGenIoBuf : if not pioGenIoBuf_g generate
begin
x_portio_O((i+1)*8-1 downto (i+1)*8-8) <= sPortOut((i+1)*8-1 downto (i+1)*8-8);
sPortIn((i+1)*8-1 downto (i+1)*8-8) <= x_portio_I((i+1)*8-1 downto (i+1)*8-8);
--if port configuration bit is set to '0', the appropriate port-byte is an output ('0')
--if port configuration bit is set to '1', the appropriate port-byte is an input ('1')
x_portio_T((i+1)*8-1 downto (i+1)*8-8) <= (others => '0') when sPortConfig(i) = '0' else (others => '1');
end generate;
end generate;
--Avalon interface
avalonPro : process(clk, reset)
begin
if reset = '1' then
x_portOutValid_s <= (others => '0');
sPortOut <= (others => '0');
x_operational_s <= '0';
elsif clk = '1' and clk'event then
x_portOutValid_s <= (others => '0');
if s0_write = '1' then
case s0_address is
when '0' => --write port
for i in 3 downto 0 loop
if s0_byteenable(i) = '1' then
sPortOut((i+1)*8-1 downto (i+1)*8-8) <= s0_writedata((i+1)*8-1 downto (i+1)*8-8);
x_portOutValid_s(i) <= '1';
end if;
end loop;
when '1' => --write to config register operational flag
if s0_byteenable(3) = '1' then
x_operational_s <= s0_writedata(s0_writedata'left);
end if;
when others =>
end case;
end if;
end if;
end process;
s0_readdata <= sPortInL when s0_read = '1' and s0_address = '0' else
x_operational_s & "000" & x"00000" & x"0" & sPortConfig;
thePortioCnters : for i in 0 to 3 generate
thePortioCnt : entity work.portio_cnt
generic map (
maxVal => pioValLen_g
)
port map (
clk => clk,
rst => reset,
pulse => x_portOutValid_s(i),
valid => x_portOutValid(i)
);
end generate;
--latch input signals
latchInPro : process(clk, reset)
begin
if reset = '1' then
sPortInL <= (others => '0');
elsif clk = '1' and clk'event then
for i in 3 downto 0 loop
if x_portInLatch_s(i) = '1' then
sPortInL((i+1)*8-1 downto (i+1)*8-8) <= sPortIn_s((i+1)*8-1 downto (i+1)*8-8);
end if;
end loop;
end if;
end process;
-- waitrequest signals
theWaitrequestGenerators : block
signal s0_rd_ack, s0_wr_ack : std_logic;
begin
-- PCP
thePcpWrWaitReqAckGen : entity work.req_ack
generic map (
zero_delay_g => true
)
port map (
clk => clk,
rst => reset,
enable => s0_write,
ack => s0_wr_ack
);
thePcpRdWaitReqAckGen : entity work.req_ack
generic map (
zero_delay_g => true
)
port map (
clk => clk,
rst => reset,
enable => s0_read,
ack => s0_rd_ack
);
s0_waitrequest <= not(s0_rd_ack or s0_wr_ack);
end block;
--synchronize input signals
genSyncInputs : for i in sPortIn'range generate
syncInputs : entity work.sync
port map (
din => sPortIn(i),
dout => sPortIn_s(i),
clk => clk,
rst => reset
);
end generate;
--synchronize latch signals
genSyncLatch : for i in x_portInLatch'range generate
syncInputs : entity work.sync
port map (
din => x_portInLatch(i),
dout => x_portInLatch_s(i),
clk => clk,
rst => reset
);
end generate;
end architecture rtl;
|
-------------------------------------------------------------------------------
-- Entity: mcu_pkg
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- VHDL package for definition of design parameters and types used throughout
-- the MCU.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mcu_pkg is
-----------------------------------------------------------------------------
-- tool chain selection (because no suppoprt of 'val attritube in ISE XST)
-----------------------------------------------------------------------------
constant ISE_TOOL : boolean := true; -- true = ISE XST
-- false = other synthesizer (e.g. Vivado)
-- system clock frequency in Hz
constant CF : natural := 50_000_000; -- 50 MHz
-----------------------------------------------------------------------------
-- Helper functions (prototypes)
-----------------------------------------------------------------------------
-- std_logic_vector(to_signed(i,w))
function i2slv(i : integer; w : positive) return std_logic_vector;
-- std_logic_vector(to_unsigned(n,w))
function n2slv(n : natural; w : positive) return std_logic_vector;
-- form instruction word for NOP instruction
function iw_nop return std_logic_vector;
-----------------------------------------------------------------------------
-- design parameters: Memory Map & Peripherals
-----------------------------------------------------------------------------
-- bus architecture parameters
constant DW : natural range 4 to 64 := 16; -- data word width
constant AW : natural range 2 to 64 := 10; -- total address width
constant AWH : natural range 1 to 64 := 4; -- high address width
constant AWL : natural range 1 to 64 := AW-AWH; -- low address width
-- memory map
type t_bus_slave is (ROM, RAM, GPIO, FMC, TIM, UART); -- list of bus slaves
type t_ba is array (t_bus_slave) of std_logic_vector(AW-1 downto 0);
constant BA : t_ba := ( -- full base addresses
ROM => "0-" & "----" & "----",
RAM => "10" & "----" & "----",
GPIO => "11" & "00--" & "----",
FMC => "11" & "01--" & "----",
TIM => "11" & "10--" & "----",
UART => "11" & "11--" & "----"
);
type t_hba is array (t_bus_slave) of std_logic_vector(AWH-1 downto 0);
constant HBA : t_hba := ( -- high base address for decoding
ROM => BA(ROM) (AW-1 downto AW-AWH),
RAM => BA(RAM) (AW-1 downto AW-AWH),
GPIO => BA(GPIO)(AW-1 downto AW-AWH),
FMC => BA(FMC) (AW-1 downto AW-AWH),
TIM => BA(TIM) (AW-1 downto AW-AWH),
UART => BA(UART)(AW-1 downto AW-AWH)
);
-- Relative Register Addresses of Peripherals
-- GPIO
constant c_addr_gpio_data_in : std_logic_vector(AWL-1 downto 0) := n2slv( 0, AWL);
constant c_addr_gpio_data_out : std_logic_vector(AWL-1 downto 0) := n2slv( 1, AWL);
constant c_addr_gpio_out_enb : std_logic_vector(AWL-1 downto 0) := n2slv( 2, AWL);
type t_gpio_addr_sel is (none, gpio_data_in, gpio_data_out, gpio_enb);
-- FMC
constant FMC_NUM_CHN : natural range 1 to 8 := 8; -- # of FMC channels
constant FMC_ROM_AW : natural range 1 to 10 := 10; -- FMC ROM addr width
constant FMC_ROM_DW : natural range 1 to 20 := 20; -- FMC ROM data width
constant FMC_TON_WW : natural range 1 to 16 := 6; -- FMC duration word width
constant FMC_DUR_WW : natural range 1 to 16 := 14; -- FMC tone word width
constant FMC_LAST_TONE : unsigned(FMC_DUR_WW-1 downto 0) := (others => '1'); -- last-tone indicator
constant c_addr_fmc_chn_enb : std_logic_vector(AWL-1 downto 0) := n2slv( 0, AWL);
constant c_addr_fmc_tmp_ctrl : std_logic_vector(AWL-1 downto 0) := n2slv( 1, AWL);
type t_fmc_addr_sel is (none, fmc_chn_enb, fmc_tmp_ctrl);
-- TIM
-- UART
-----------------------------------------------------------------------------
-- design parameters: CPU Instructions
-----------------------------------------------------------------------------
-- CPU instruction set
-- Note: Defining the OPcode in the way shown below, allows assembler-style
-- programming with mnemonics rather than machine coding (see rom.vhd).
constant OPCW : natural range 1 to DW := 5; -- Opcode word width
constant OPAW : natural range 1 to DW := 4; -- ALU operation word width
constant IOWW : natural range 1 to DW := 8; -- immediate operand word width
type t_instr is (add, sub, andi, ori, xori, slai, srai, mov,
ld, st,
addil, addih, setil, setih,
jmp, bne, bge, blt, bca, bov,
nop);
-- Instructions targeted at the ALU are defined by means of a sub-type.
-- This allows changing the opcode of instructions without having to
-- modify the source code of the ALU.
subtype t_alu_instr is t_instr range add to mov;
type t_opcode is array (t_instr) of std_logic_vector(OPCW-1 downto 0);
constant OPC : t_opcode := ( -- OPcode
-- ALU operations -------------------------------
add => "00000", -- 0: addition
sub => "00001", -- 1: subtraction
andi => "00010", -- 2: bit-wise AND
ori => "00011", -- 3: bit-wise OR
xori => "00100", -- 4: bit-wise XOR
slai => "00101", -- 5: shift-left arithmetically
srai => "00110", -- 6: shift-right arithmetically
mov => "00111", -- 7: move between register
-- Immediate Operands ---------------------------
addil => "01100", -- 12: add imm. constant low
addih => "01101", -- 13: add imm. constant high
setil => "01110", -- 14: set imm. constant low
setih => "01111", -- 15: set imm. constant high
-- Memory load/store ----------------------------
ld => "10000", -- 16: load from memory
st => "10001", -- 17: store to memory
-- Jump/Branch ----------------------------------
jmp => "11000", -- 24: absolute jump
bne => "11001", -- 25: branch if not equal (not Z)
bge => "11010", -- 26: branch if greater/equal (not N or Z)
blt => "11011", -- 27: branch if less than (N)
bca => "11100", -- 28: branch if carry set (C)
bov => "11101", -- 29: branch if overflow set (O)
-- Others ---------------------------------------
nop => "11111" -- 31: no operation
);
type t_flags is (Z, N, C, O); -- ALU flags (zero, negative, carry, overflow)
type t_flag_arr is array (t_flags) of std_logic;
-- register block
constant RIDW : natural range 1 to DW := 3; -- register ID word width
type t_regid is array(0 to 7) of std_logic_vector(RIDW-1 downto 0);
constant reg : t_regid := ("000","001","010","011","100","101","110","111");
type t_regblk is array(0 to 7) of std_logic_vector(DW-1 downto 0);
-- CPU address generation
type t_pc_mode is (linear, abs_jump, rel_offset); -- addr calcultion modi
type t_addr_exc is (no_err, lin_err, rel_err); -- address exceptions
-----------------------------------------------------------------------------
-- global types
-----------------------------------------------------------------------------
-- Master bus interface -----------------------------------------------------
type t_bus2cpu is record
data : std_logic_vector(DW-1 downto 0);
end record;
type t_cpu2bus is record
data : std_logic_vector(DW-1 downto 0);
addr : std_logic_vector(AW-1 downto 0);
rd_enb : std_logic;
wr_enb : std_logic;
end record;
-- Read-only slave bus interface -------------------------------------------
type t_bus2ros is record
addr : std_logic_vector(AWL-1 downto 0);
rd_enb : std_logic;
end record;
type t_ros2bus is record
data : std_logic_vector(DW-1 downto 0);
end record;
-- read/write slave bus interface -------------------------------------------
type t_bus2rws is record
addr : std_logic_vector(AWL-1 downto 0);
data : std_logic_vector(DW-1 downto 0);
rd_enb : std_logic; -- use of this signal is optional, depending on slave
wr_enb : std_logic;
end record;
type t_rws2bus is record
data : std_logic_vector(DW-1 downto 0);
end record;
-----------------------------------------------------------------------------
-- CPU internal types
-----------------------------------------------------------------------------
-- Control Unit / Register Block interface ----------------------------------
type t_ctr2reg is record
src1 : std_logic_vector(RIDW-1 downto 0);
src2 : std_logic_vector(RIDW-1 downto 0);
dest : std_logic_vector(RIDW-1 downto 0);
enb_res : std_logic;
data : std_logic_vector(DW-1 downto 0);
enb_data : std_logic;
end record;
type t_reg2ctr is record
data : std_logic_vector(DW-1 downto 0);
addr : std_logic_vector(AW-1 downto 0);
end record;
-- Control Unit / Program Counter interface --------------------------------
type t_ctr2prc is record
enb : std_logic;
mode : t_pc_mode;
addr : std_logic_vector(AW-1 downto 0);
end record;
type t_prc2ctr is record
pc : std_logic_vector(AW-1 downto 0);
exc : t_addr_exc;
end record;
-- Control Unit / ALU interface ---------------------------------------------
type t_ctr2alu is record
op : std_logic_vector(OPAW-1 downto 0); -- operation
imm : std_logic_vector(IOWW-1 downto 0); -- immediate operand
enb : std_logic; -- enable flag update
end record;
type t_alu2ctr is record
flag : t_flag_arr;
end record;
end package mcu_pkg;
package body mcu_pkg is
-----------------------------------------------------------------------------
-- Function Implementations
-----------------------------------------------------------------------------
function i2slv(i : integer;w : positive) return std_logic_vector is
begin
return std_logic_vector(to_signed(i,w));
end function i2slv;
function n2slv(n : natural;w : positive) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(n,w));
end function n2slv;
function iw_nop return std_logic_vector is
variable v : std_logic_vector(DW-1 downto 0);
begin
for k in DW-1 downto DW-OPCW loop
v(k) := OPC(nop)(k-DW+OPCW);
end loop;
for k in DW-OPCW-1 downto 0 loop
v(k) := '0';
end loop;
return v;
end function iw_nop;
end package body mcu_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
entity mux_2to1_11bit is
port ( data0: in std_logic_vector (10 downto 0);
data1: in std_logic_vector (10 downto 0);
sel: in std_logic;
data_out: out std_logic_vector(10 downto 0));
end mux_2to1_11bit;
architecture Behaviour of mux_2to1_11bit is
begin
process(data0,data1,sel)
begin
if(sel='0') then
data_out <= data0;
elsif(sel='1') then
data_out <= data1;
end if;
end process;
end Behaviour; |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- Configuration file for a Digilent ArtyA7-100 board.
--
--
-- License:
-- =============================================================================
-- Copyright 2017-2020 Patrick Lehmann - Boetzingen, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
--
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ArtyA7-100"; -- Digilent ArtyA7-100 - Xilinx Artix-7: XC7A100T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
|
entity block1 is
end entity;
architecture test of block1 is
signal u, v, w: integer;
begin
process is
begin
u <= 1;
wait for 1 ns;
u <= 2;
wait;
end process;
a: block is
signal x : integer;
begin
x <= u + 2;
v <= x;
end block;
b: block is
signal x : integer;
begin
x <= v + 6;
w <= x;
end block;
process is
begin
wait for 1 ns;
assert w = 9;
wait for 1 ns;
assert w = 10;
wait;
end process;
end architecture;
|
entity block1 is
end entity;
architecture test of block1 is
signal u, v, w: integer;
begin
process is
begin
u <= 1;
wait for 1 ns;
u <= 2;
wait;
end process;
a: block is
signal x : integer;
begin
x <= u + 2;
v <= x;
end block;
b: block is
signal x : integer;
begin
x <= v + 6;
w <= x;
end block;
process is
begin
wait for 1 ns;
assert w = 9;
wait for 1 ns;
assert w = 10;
wait;
end process;
end architecture;
|
entity block1 is
end entity;
architecture test of block1 is
signal u, v, w: integer;
begin
process is
begin
u <= 1;
wait for 1 ns;
u <= 2;
wait;
end process;
a: block is
signal x : integer;
begin
x <= u + 2;
v <= x;
end block;
b: block is
signal x : integer;
begin
x <= v + 6;
w <= x;
end block;
process is
begin
wait for 1 ns;
assert w = 9;
wait for 1 ns;
assert w = 10;
wait;
end process;
end architecture;
|
entity block1 is
end entity;
architecture test of block1 is
signal u, v, w: integer;
begin
process is
begin
u <= 1;
wait for 1 ns;
u <= 2;
wait;
end process;
a: block is
signal x : integer;
begin
x <= u + 2;
v <= x;
end block;
b: block is
signal x : integer;
begin
x <= v + 6;
w <= x;
end block;
process is
begin
wait for 1 ns;
assert w = 9;
wait for 1 ns;
assert w = 10;
wait;
end process;
end architecture;
|
entity block1 is
end entity;
architecture test of block1 is
signal u, v, w: integer;
begin
process is
begin
u <= 1;
wait for 1 ns;
u <= 2;
wait;
end process;
a: block is
signal x : integer;
begin
x <= u + 2;
v <= x;
end block;
b: block is
signal x : integer;
begin
x <= v + 6;
w <= x;
end block;
process is
begin
wait for 1 ns;
assert w = 9;
wait for 1 ns;
assert w = 10;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : UART Testbench support procedures
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package uart_tb_pkg is
procedure uart_transmit (
-- The signal that is to be driven by this model...
signal tx_line : out std_logic;
-- Inputs to control how to send one character:
data : in std_logic_vector; -- usually 8 bits
baud_rate : in integer -- e.g. 9600
);
end package uart_tb_pkg;
package body uart_tb_pkg is
procedure uart_transmit (
-- The signal that is to be driven by this model...
signal tx_line : out std_logic;
-- Inputs to control how to send one character:
data : in std_logic_vector; -- usually 8 bits
baud_rate : in integer -- e.g. 9600
) is
constant bit_time : time := 1 sec / baud_rate;
begin
-- Send the start bit
tx_line <= '0';
wait for bit_time;
-- Send the data bits, least significant first
for i in data'reverse_range loop
tx_line <= data(i);
wait for bit_time;
end loop;
-- Send the stop bit
tx_line <= '1';
wait for bit_time;
end uart_transmit;
end uart_tb_pkg;
|
-------------------------------------------------------------------------------
-- Title : UART Testbench support procedures
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package uart_tb_pkg is
procedure uart_transmit (
-- The signal that is to be driven by this model...
signal tx_line : out std_logic;
-- Inputs to control how to send one character:
data : in std_logic_vector; -- usually 8 bits
baud_rate : in integer -- e.g. 9600
);
end package uart_tb_pkg;
package body uart_tb_pkg is
procedure uart_transmit (
-- The signal that is to be driven by this model...
signal tx_line : out std_logic;
-- Inputs to control how to send one character:
data : in std_logic_vector; -- usually 8 bits
baud_rate : in integer -- e.g. 9600
) is
constant bit_time : time := 1 sec / baud_rate;
begin
-- Send the start bit
tx_line <= '0';
wait for bit_time;
-- Send the data bits, least significant first
for i in data'reverse_range loop
tx_line <= data(i);
wait for bit_time;
end loop;
-- Send the stop bit
tx_line <= '1';
wait for bit_time;
end uart_transmit;
end uart_tb_pkg;
|
-------------------------------------------------------------------------------
-- axi_cdma_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_sf.vhd
--
-- Description:
-- This file implements the AXI CDMA store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control interfaces. The design is such that predictive address
-- pipelining can be supported on the AXI Read Bus without over-commiting
-- the internal Data FIFO and potentially throttling the Read Data Channel
-- if the Data FIFO goes full. On the AXI Write side, the Write Master is
-- only allowed to post AXI WRite Requests if the associated write data needed
-- to complete the Write Data transfer is present in the Data FIFO. In
-- addition, the Write side logic is such that Write transfer requests can
-- be pipelined to the AXI bus based on the Data FIFO contents but ahead of
-- the actual Write Data transfers.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
use lib_pkg_v1_0.lib_pkg.clog2;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
library axi_cdma_v4_1;
use axi_cdma_v4_1.axi_cdma_sfifo_autord;
-------------------------------------------------------------------------------
entity axi_cdma_sf is
generic (
C_WR_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter indicates the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4
-- Write Address Channel will be the value assigned plus 2.
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max burst length being used by the external
-- AXI4 Master for each AXI4 transfer request.
C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- Indicates if the external Master is utilizing a DRE on
-- the stream input to this module.
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock input
aclk : in std_logic;
-- Primary synchronization clock for the Master side
-- interface and internal logic. It is also used
-- for the User interface synchronization when
-- C_STSCMD_IS_ASYNC = 0.
-- Reset input
reset : in std_logic;
-- Reset used for the internal syncronization logic
-- DataMover Read Side Address Pipelining Control Interface ---------------
ok_to_post_rd_addr : Out Std_logic;
-- Indicates that the transfer token pool has at least
-- one token available to borrow
rd_addr_posted : In std_logic;
-- Indication that a read address has been posted to AXI4
rd_xfer_cmplt : In std_logic;
-- Indicates that the Datamover has completed a Read Data
-- transfer on the AXI4
-- Read Side Stream In from DataMover MM2S -----------------------------------
sf2sin_tready : Out Std_logic;
-- DRE Stream READY input
sin2sf_tvalid : In std_logic;
-- DRE Stream VALID Output
sin2sf_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0);
-- DRE Stream DATA input
sin2sf_tkeep : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- DRE Stream STRB input
sin2sf_tlast : In std_logic;
-- DRE Xfer LAST input
-- DataMover Write Side Address Pipelining Control Interface --------------
ok_to_post_wr_addr : Out Std_logic;
-- Indicates that the internal FIFO has enough data
-- physically present to supply one more max length
-- burst transfer or a completion burst
-- (tlast asserted)
wr_addr_posted : In std_logic;
-- Indication that a write address has been posted to AXI4
wr_xfer_cmplt : In Std_logic;
-- Indicates that the Datamover has completed a Write Data
-- transfer on the AXI4
wr_ld_nxt_len : in std_logic;
-- Active high pulse indicating a new transfer LEN qualifier
-- has been queued to the DataMover Write Data Controller
wr_len : in std_logic_vector(7 downto 0);
-- The actual LEN qualifier value that has been queued to the
-- DataMover Write Data Controller
-- Write Side Stream Out to DataMover S2MM -------------------------------
sout2sf_tready : In std_logic;
-- Write READY input from the Stream Master
sf2sout_tvalid : Out std_logic;
-- Write VALID output to the Stream Master
sf2sout_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0);
-- Write DATA output to the Stream Master
sf2sout_tkeep : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- Write DATA output to the Stream Master
sf2sout_tlast : Out std_logic
-- Write LAST output to the Stream Master
);
end entity axi_cdma_sf;
architecture implementation of axi_cdma_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbcntr_width
--
-- Function Description:
-- simple function to set the width of the burst counter
-- based on the parameterized max burst length.
--
-------------------------------------------------------------------
function funct_get_dbcntr_width (max_burst_length : integer)
return integer is
Variable temp_width : integer := 0;
begin
case max_burst_length is
when 2 =>
temp_width := 1;
when 4 =>
temp_width := 2;
when 8 =>
temp_width := 3;
when 16 =>
temp_width := 4;
when 32 =>
temp_width := 5;
when 64 =>
temp_width := 6;
when 128 =>
temp_width := 7;
when others => -- 256 beats
temp_width := 8;
end case;
Return (temp_width);
end function funct_get_dbcntr_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_pwr2_depth
--
-- Function Description:
-- Rounds up to the next power of 2 depth value in an input
-- range of 1 to 8192
--
-------------------------------------------------------------------
function funct_get_pwr2_depth (min_depth : integer) return integer is
Variable var_temp_depth : Integer := 16;
begin
if (min_depth = 1) then
var_temp_depth := 1;
elsif (min_depth = 2) then
var_temp_depth := 2;
elsif (min_depth <= 4) then
var_temp_depth := 4;
elsif (min_depth <= 8) then
var_temp_depth := 8;
elsif (min_depth <= 16) then
var_temp_depth := 16;
elsif (min_depth <= 32) then
var_temp_depth := 32;
elsif (min_depth <= 64) then
var_temp_depth := 64;
elsif (min_depth <= 128) then
var_temp_depth := 128;
elsif (min_depth <= 256) then
var_temp_depth := 256;
elsif (min_depth <= 512) then
var_temp_depth := 512;
elsif (min_depth <= 1024) then
var_temp_depth := 1024;
elsif (min_depth <= 2048) then
var_temp_depth := 2048;
elsif (min_depth <= 4096) then
var_temp_depth := 4096;
else -- assume 8192 depth
var_temp_depth := 8192;
end if;
Return (var_temp_depth);
end function funct_get_pwr2_depth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_wrcnt_lsrip
--
-- Function Description:
-- Calculates the ls index of the upper slice of the data fifo
-- write count needed to repesent one max burst worth of data
-- present in the fifo.
--
-------------------------------------------------------------------
function funct_get_wrcnt_lsrip (max_burst_dbeats : integer) return integer is
Variable temp_ls_index : Integer := 0;
begin
if (max_burst_dbeats <= 2) then
temp_ls_index := 1;
elsif (max_burst_dbeats <= 4) then
temp_ls_index := 2;
elsif (max_burst_dbeats <= 8) then
temp_ls_index := 3;
elsif (max_burst_dbeats <= 16) then
temp_ls_index := 4;
elsif (max_burst_dbeats <= 32) then
temp_ls_index := 5;
elsif (max_burst_dbeats <= 64) then
temp_ls_index := 6;
elsif (max_burst_dbeats <= 128) then
temp_ls_index := 7;
else
temp_ls_index := 8;
end if;
Return (temp_ls_index);
end function funct_get_wrcnt_lsrip;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stall_thresh
--
-- Function Description:
-- Calculates the Stall threshold for the input side of the Data
-- FIFO. If DRE is being used by the DataMover, then the threshold
-- must be reduced to account for the potential of an extra write
-- databeat per request (DRE alignment dependent).
--
-------------------------------------------------------------------
function funct_get_stall_thresh (dre_is_used : integer;
max_xfer_length : integer;
data_fifo_depth : integer;
pipeline_delay_clks : integer;
fifo_settling_clks : integer) return integer is
Constant DRE_PIPE_DELAY : integer := 2; -- clks
Variable var_num_max_xfers_allowed : Integer := 0;
Variable var_dre_dbeat_overhead : Integer := 0;
Variable var_delay_fudge_factor : Integer := 0;
Variable var_thresh_headroom : Integer := 0;
Variable var_stall_thresh : Integer := 0;
begin
var_num_max_xfers_allowed := data_fifo_depth/max_xfer_length;
var_dre_dbeat_overhead := var_num_max_xfers_allowed * dre_is_used;
var_delay_fudge_factor := (dre_is_used * DRE_PIPE_DELAY) +
pipeline_delay_clks +
fifo_settling_clks;
var_thresh_headroom := max_xfer_length +
var_dre_dbeat_overhead +
var_delay_fudge_factor;
-- Scale the result to be in max transfer length increments
var_stall_thresh := (data_fifo_depth - var_thresh_headroom)/max_xfer_length;
Return (var_stall_thresh);
end function funct_get_stall_thresh;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant WSTB_WIDTH : integer := C_STREAM_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_STREAM_DWIDTH+
WSTB_WIDTH +
TLAST_WIDTH;
Constant DATA_OUT_MSB_INDEX : integer := C_STREAM_DWIDTH-1;
Constant DATA_OUT_LSB_INDEX : integer := 0;
Constant TSTRB_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant TSTRB_OUT_MSB_INDEX : integer := (TSTRB_OUT_LSB_INDEX+WSTB_WIDTH)-1;
Constant TLAST_OUT_INDEX : integer := TSTRB_OUT_MSB_INDEX+1;
Constant DBEAT_CNTR_WIDTH : integer := funct_get_dbcntr_width(C_MAX_BURST_LEN);
Constant MAX_BURST_DBEATS : Unsigned(DBEAT_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, DBEAT_CNTR_WIDTH);
Constant DBC_ONE : Unsigned(DBEAT_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DBEAT_CNTR_WIDTH);
Constant TOKEN_POOL_SIZE : integer := C_SF_FIFO_DEPTH / C_MAX_BURST_LEN;
Constant TOKEN_CNTR_WIDTH : integer := clog2(TOKEN_POOL_SIZE)+1;
Constant TOKEN_CNT_ZERO : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_ONE : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_MAX : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(TOKEN_POOL_SIZE, TOKEN_CNTR_WIDTH);
Constant THRESH_COMPARE_WIDTH : integer := TOKEN_CNTR_WIDTH+2;
Constant RD_PATH_PIPE_DEPTH : integer := 2; -- clocks excluding DRE
Constant WRCNT_SETTLING_TIME : integer := 2; -- data fifo push or pop settling clocks
Constant RD_ADDR_POST_STALL_THRESH : integer :=
funct_get_stall_thresh(C_DRE_IS_USED ,
C_MAX_BURST_LEN ,
C_SF_FIFO_DEPTH ,
RD_PATH_PIPE_DEPTH ,
WRCNT_SETTLING_TIME);
Constant RD_ADDR_POST_STALL_THRESH_US : Unsigned(THRESH_COMPARE_WIDTH-1 downto 0) :=
TO_UNSIGNED(RD_ADDR_POST_STALL_THRESH ,
THRESH_COMPARE_WIDTH);
Constant WR_LEN_FIFO_DWIDTH : integer := 8;
Constant WR_LEN_FIFO_DEPTH : integer := funct_get_pwr2_depth(C_WR_ADDR_PIPE_DEPTH + 2);
Constant LEN_CNTR_WIDTH : integer := 8;
Constant LEN_CNT_ZERO : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, LEN_CNTR_WIDTH);
Constant LEN_CNT_ONE : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, LEN_CNTR_WIDTH);
Constant WR_XFER_CNTR_WIDTH : integer := 8;
Constant WR_XFER_CNT_ZERO : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, WR_XFER_CNTR_WIDTH);
Constant WR_XFER_CNT_ONE : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, WR_XFER_CNTR_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector(WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cnt_unsgnd : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_wrcnt_mblen_slice : unsigned(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX) := (others => '0');
signal sig_ok_to_post_rd_addr : std_logic := '0';
signal sig_rd_addr_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_taking_last_token : std_logic := '0';
signal sig_stall_rd_addr_posts : std_logic := '0';
signal sig_incr_token_cntr : std_logic := '0';
signal sig_decr_token_cntr : std_logic := '0';
signal sig_token_eq_max : std_logic := '0';
signal sig_token_eq_zero : std_logic := '0';
signal sig_token_eq_one : std_logic := '0';
signal sig_token_cntr : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_tokens_commited : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_commit_plus_actual : unsigned(THRESH_COMPARE_WIDTH-1 downto 0) := (others => '0');
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_wr_addr_posted : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_wr_ld_nxt_len : std_logic := '0';
signal sig_push_len_fifo : std_logic := '0';
signal sig_pop_len_fifo : std_logic := '0';
signal sig_len_fifo_full : std_logic := '0';
signal sig_len_fifo_empty : std_logic := '0';
signal sig_len_fifo_data_in : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_data_out : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_len_out_un : unsigned(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_uncom_wrcnt : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_sub_len_uncom_wrcnt : std_logic := '0';
signal sig_incr_uncom_wrcnt : std_logic := '0';
signal sig_resized_fifo_len : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_num_wr_dbeats_needed : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_enough_dbeats_rcvd : std_logic := '0';
begin --(architecture implementation)
-- Read Side (MM2S) Control Flags port connections
ok_to_post_rd_addr <= sig_ok_to_post_rd_addr ;
sig_rd_addr_posted <= rd_addr_posted ;
sig_rd_xfer_cmplt <= rd_xfer_cmplt ;
-- Write Side (S2MM) Control Flags port connections
ok_to_post_wr_addr <= sig_ok_to_post_wr_addr ;
sig_wr_addr_posted <= wr_addr_posted ;
sig_wr_xfer_cmplt <= wr_xfer_cmplt ;
sig_wr_ld_nxt_len <= wr_ld_nxt_len ;
sig_len_fifo_data_in <= wr_len ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_strm_sin_ready <= not(sig_data_fifo_full); -- Throttle if Read Side Data fifo goes full.
-- This should never happen if read address
-- posting control is working properly.
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
----------------------------------------------------------------
-- Token Counter Logic
-- Predicting fifo space availability at some point in the
-- future is based on managing a virtual pool of transfer tokens.
-- A token represents 1 max length burst worth of space in the
-- Data FIFO.
----------------------------------------------------------------
-- calculate how many tokens are commited to pending transfers
sig_tokens_commited <= TOKEN_CNT_MAX - sig_token_cntr;
-- Decrement the token counter when a token is
-- borrowed
sig_decr_token_cntr <= '1'
when (sig_rd_addr_posted = '1' and
sig_token_eq_zero = '0')
else '0';
-- Increment the token counter when a
-- token is returned.
sig_incr_token_cntr <= '1'
when (sig_rd_xfer_cmplt = '1' and
sig_token_eq_max = '0')
else '0';
-- Detect when the xfer token count is at max value
sig_token_eq_max <= '1'
when (sig_token_cntr = TOKEN_CNT_MAX)
Else '0';
-- Detect when the xfer token count is at one
sig_token_eq_one <= '1'
when (sig_token_cntr = TOKEN_CNT_ONE)
Else '0';
-- Detect when the xfer token count is at zero
sig_token_eq_zero <= '1'
when (sig_token_cntr = TOKEN_CNT_ZERO)
Else '0';
-- Look ahead to see if the xfer token pool is going empty
sig_taking_last_token <= '1'
When (sig_token_eq_one = '1' and
sig_rd_addr_posted = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_CMTR
--
-- Process Description:
-- Implements the Token counter
--
-------------------------------------------------------------
IMP_TOKEN_CMTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' ) then
sig_token_cntr <= TOKEN_CNT_MAX;
elsif (sig_incr_token_cntr = '1' and
sig_decr_token_cntr = '0') then
sig_token_cntr <= sig_token_cntr + TOKEN_CNT_ONE;
elsif (sig_incr_token_cntr = '0' and
sig_decr_token_cntr = '1') then
sig_token_cntr <= sig_token_cntr - TOKEN_CNT_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_TOKEN_CMTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_AVAIL_FLAG
--
-- Process Description:
-- Implements the flag indicating that the AXI Read Master
-- can post a read address request on the AXI4 bus.
--
-- Read address posting can occur if:
--
-- - The write side LEN fifo is not empty.
-- - The commited plus actual Data FIFO space is less than
-- the stall threshold (a max length read burst can fit
-- in the data FIFO without overflow).
-- - The max allowed commited read count has not been reached.
--
-- The flag is cleared after each address has been posted to
-- ensure a second unauthotized post occurs.
-------------------------------------------------------------
IMP_TOKEN_AVAIL_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_rd_addr_posted = '1') then
sig_ok_to_post_rd_addr <= '0';
else
sig_ok_to_post_rd_addr <= not(sig_stall_rd_addr_posts) and -- the commited Data FIFO space is approaching full
not(sig_token_eq_zero) and -- max allowed pending reads has not been reached
not(sig_taking_last_token); -- the max allowed pending reads is about to be reached
end if;
end if;
end process IMP_TOKEN_AVAIL_FLAG;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
-- FIFO Output to output stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid ;
sig_sf2sout_tdata <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_sf2sout_tkeep <= sig_data_fifo_data_out(TSTRB_OUT_MSB_INDEX downto
TSTRB_OUT_LSB_INDEX);
sig_sf2sout_tlast <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
-- Stall Threshold calculations
sig_fifo_wr_cnt_unsgnd <= UNSIGNED(sig_data_fifo_wr_cnt);
sig_wrcnt_mblen_slice <= sig_fifo_wr_cnt_unsgnd(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX);
sig_commit_plus_actual <= RESIZE(sig_tokens_commited, THRESH_COMPARE_WIDTH) +
RESIZE(sig_wrcnt_mblen_slice, THRESH_COMPARE_WIDTH);
-- Compare the commited read space plus the actual used space against the
-- stall threshold. Assert the read address posting stall flag if the
-- threshold is met or exceeded.
sig_stall_rd_addr_posts <= '1'
when (sig_commit_plus_actual > RD_ADDR_POST_STALL_THRESH_US)
Else '0';
-- FIFO Rd/WR Controls
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
sig_pop_data_fifo <= sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= sin2sf_tlast &
sin2sf_tkeep &
sin2sf_tdata;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_cdma_v4_1.axi_cdma_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
--------------------------------------------------------------------
-- Write Side Control Logic
--------------------------------------------------------------------
-- Convert the LEN fifo data output to unsigned
sig_len_fifo_len_out_un <= unsigned(sig_len_fifo_data_out);
-- Resize the unsigned LEN output to the Data FIFO writecount width
sig_resized_fifo_len <= RESIZE(sig_len_fifo_len_out_un , DATA_FIFO_CNT_WIDTH);
-- The actual number of databeats needed for the queued write transfer
-- is the current LEN fifo output plus 1.
sig_num_wr_dbeats_needed <= sig_resized_fifo_len + UNCOM_WRCNT_1;
-- Compare the uncommited receved data beat count to that needed
-- for the next queued write request.
sig_enough_dbeats_rcvd <= '1'
When (sig_num_wr_dbeats_needed <= sig_uncom_wrcnt)
else '0';
-- Increment the uncommited databeat counter on a good input
-- stream databeat (Read Side of SF)
sig_incr_uncom_wrcnt <= sig_good_sin_strm_dbeat;
-- Subtract the current number of databeats needed from the
-- uncommited databeat counter when the associated transfer
-- address/qualifiers have been posted to the AXI Write
-- Address Channel
sig_sub_len_uncom_wrcnt <= sig_wr_addr_posted;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_UNCOM_DBEAT_CNTR
--
-- Process Description:
-- Implements the counter that keeps track of the received read
-- data beat count that has not been commited to a transfer on
-- the write side with a Write Address posting.
--
-------------------------------------------------------------
IMP_UNCOM_DBEAT_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_uncom_wrcnt <= UNCOM_WRCNT_0;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_resized_fifo_len;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '0') then
sig_uncom_wrcnt <= sig_uncom_wrcnt + UNCOM_WRCNT_1;
elsif (sig_incr_uncom_wrcnt = '0' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_num_wr_dbeats_needed;
else
null; -- hold current value
end if;
end if;
end process IMP_UNCOM_DBEAT_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_ADDR_POST_FLAG
--
-- Process Description:
-- Implements the flag indicating that the pending write
-- transfer's data beat count has been received on the input
-- side of the Data FIFO. This means the Write side can post
-- the associated write address to the AXI4 bus and the
-- associated write data transfer can complete without CDMA
-- throttling the Write Data Channel.
--
-- The flag is cleared immediately after an address is posted
-- to prohibit a second unauthorized posting while the control
-- logic stabilizes to the next LEN FIFO value
--.
-------------------------------------------------------------
IMP_WR_ADDR_POST_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_wr_addr_posted = '1') then
sig_ok_to_post_wr_addr <= '0';
else
sig_ok_to_post_wr_addr <= not(sig_len_fifo_empty) and
sig_enough_dbeats_rcvd;
end if;
end if;
end process IMP_WR_ADDR_POST_FLAG;
-------------------------------------------------------------
-- LEN FIFO logic
sig_push_len_fifo <= sig_wr_ld_nxt_len and
not(sig_len_fifo_full);
sig_pop_len_fifo <= wr_addr_posted and
not(sig_len_fifo_empty);
------------------------------------------------------------
-- Instance: I_WR_LEN_FIFO
--
-- Description:
-- Implement the LEN FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_WR_LEN_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map (
C_DWIDTH => WR_LEN_FIFO_DWIDTH ,
C_DEPTH => WR_LEN_FIFO_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => aclk ,
Reset => reset ,
FIFO_Write => sig_push_len_fifo ,
Data_In => sig_len_fifo_data_in ,
FIFO_Read => sig_pop_len_fifo ,
Data_Out => sig_len_fifo_data_out ,
FIFO_Empty => sig_len_fifo_empty ,
FIFO_Full => sig_len_fifo_full ,
Addr => open
);
end implementation;
|
-- -------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 15.1
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from xlr8_float_add1_0002
-- VHDL created on Tue Mar 29 13:46:59 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity xlr8_float_add1_0002 is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
en : in std_logic_vector(0 downto 0); -- ufix1
q : out std_logic_vector(31 downto 0); -- float32_m23
clk : in std_logic;
areset : in std_logic
);
end xlr8_float_add1_0002;
architecture normal of xlr8_float_add1_0002 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal cstAllOWE_uid18_fpAddTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstZeroWF_uid19_fpAddTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal cstAllZWE_uid20_fpAddTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal fracXIsZero_uid25_fpAddTest_a : STD_LOGIC_VECTOR (22 downto 0);
signal fracXIsZero_uid25_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal fracXIsZero_uid25_fpAddTest_q_i : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid25_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_bSig_uid41_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excI_bSig_uid41_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excI_bSig_uid41_fpAddTest_q_i : STD_LOGIC_VECTOR (0 downto 0);
signal excI_bSig_uid41_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_bSig_uid42_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excN_bSig_uid42_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excN_bSig_uid42_fpAddTest_q_i : STD_LOGIC_VECTOR (0 downto 0);
signal excN_bSig_uid42_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_bSig_uid45_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excR_bSig_uid45_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excR_bSig_uid45_fpAddTest_q_i : STD_LOGIC_VECTOR (0 downto 0);
signal excR_bSig_uid45_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal cWFP2_uid61_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal padConst_uid64_fpAddTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal zocst_uid76_fpAddTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal cAmA_uid86_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal oneCST_uid90_fpAddTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cRBit_uid99_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal wEP2AllOwE_uid105_fpAddTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal wEP2AllZ_uid112_fpAddTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal oneFracRPostExc2_uid141_fpAddTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal zs_uid151_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (15 downto 0);
signal mO_uid154_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal zs_uid165_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal zs_uid171_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal wIntCst_uid184_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (5 downto 0);
signal rightShiftStage0Idx3Pad24_uid193_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal rightShiftStage0Idx4Pad32_uid196_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal rightShiftStage0Idx5Pad40_uid199_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (39 downto 0);
signal rightShiftStage0Idx6Pad48_uid202_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (47 downto 0);
signal rightShiftStage0Idx7_uid204_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx3Pad3_uid214_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal rightShiftStage1Idx5Pad5_uid220_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal rightShiftStage1Idx6Pad6_uid223_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (5 downto 0);
signal rightShiftStage1Idx7Pad7_uid226_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (6 downto 0);
signal leftShiftStage0Idx3Pad12_uid241_fracPostNormExt_uid88_fpAddTest_q : STD_LOGIC_VECTOR (11 downto 0);
signal leftShiftStage0Idx5Pad20_uid247_fracPostNormExt_uid88_fpAddTest_q : STD_LOGIC_VECTOR (19 downto 0);
signal leftShiftStage0Idx7_uid253_fracPostNormExt_uid88_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal redist0_q : STD_LOGIC_VECTOR (7 downto 0);
signal redist1_q : STD_LOGIC_VECTOR (7 downto 0);
signal redist2_q : STD_LOGIC_VECTOR (11 downto 0);
signal redist3_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist4_q : STD_LOGIC_VECTOR (27 downto 0);
signal redist5_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist6_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist7_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist9_q : STD_LOGIC_VECTOR (7 downto 0);
signal expFracX_uid6_fpAddTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal expFracX_uid6_fpAddTest_b : STD_LOGIC_VECTOR (30 downto 0);
signal expFracY_uid7_fpAddTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal expFracY_uid7_fpAddTest_b : STD_LOGIC_VECTOR (30 downto 0);
signal fracY_uid9_fpAddTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal fracY_uid9_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal expY_uid10_fpAddTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal expY_uid10_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal sigY_uid11_fpAddTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal sigY_uid11_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal xGTEy_uid8_fpAddTest_a : STD_LOGIC_VECTOR (33 downto 0);
signal xGTEy_uid8_fpAddTest_b : STD_LOGIC_VECTOR (33 downto 0);
signal xGTEy_uid8_fpAddTest_o : STD_LOGIC_VECTOR (33 downto 0);
signal xGTEy_uid8_fpAddTest_cin : STD_LOGIC_VECTOR (0 downto 0);
signal xGTEy_uid8_fpAddTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_aSig_uid16_uid23_fpAddTest_a : STD_LOGIC_VECTOR (7 downto 0);
signal excZ_aSig_uid16_uid23_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal excZ_aSig_uid16_uid23_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid24_fpAddTest_a : STD_LOGIC_VECTOR (7 downto 0);
signal expXIsMax_uid24_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expXIsMax_uid24_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid26_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid26_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_aSig_uid27_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excI_aSig_uid27_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excI_aSig_uid27_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_aSig_uid28_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excN_aSig_uid28_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excN_aSig_uid28_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid29_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid29_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid30_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid30_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_aSig_uid31_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excR_aSig_uid31_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excR_aSig_uid31_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expInc_uid91_fpAddTest_a : STD_LOGIC_VECTOR (8 downto 0);
signal expInc_uid91_fpAddTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal expInc_uid91_fpAddTest_o : STD_LOGIC_VECTOR (8 downto 0);
signal expInc_uid91_fpAddTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal regInputs_uid119_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal regInputs_uid119_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal regInputs_uid119_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN2_uid125_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN2_uid125_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN2_uid125_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excAIBISub_uid126_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excAIBISub_uid126_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excAIBISub_uid126_fpAddTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal excAIBISub_uid126_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN_uid127_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN_uid127_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN_uid127_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sigBBInf_uid132_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal sigBBInf_uid132_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal sigBBInf_uid132_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sigAAInf_uid133_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal sigAAInf_uid133_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal sigAAInf_uid133_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signRInf_uid134_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal signRInf_uid134_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signRInf_uid134_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excAZBZSigASigB_uid135_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excAZBZSigASigB_uid135_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excAZBZSigASigB_uid135_fpAddTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal excAZBZSigASigB_uid135_fpAddTest_d : STD_LOGIC_VECTOR (0 downto 0);
signal excAZBZSigASigB_uid135_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excBZARSigA_uid136_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excBZARSigA_uid136_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excBZARSigA_uid136_fpAddTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal excBZARSigA_uid136_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signRZero_uid137_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal signRZero_uid137_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signRZero_uid137_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExcRNaN_uid139_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal invExcRNaN_uid139_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vCount_uid161_lzCountVal_uid85_fpAddTest_a : STD_LOGIC_VECTOR (7 downto 0);
signal vCount_uid161_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal vCount_uid161_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid164_lzCountVal_uid85_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid164_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal leftShiftStage0Idx4_uid246_fracPostNormExt_uid88_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal leftShiftStage0Idx1Rng4_uid236_fracPostNormExt_uid88_fpAddTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal leftShiftStage0Idx1Rng4_uid236_fracPostNormExt_uid88_fpAddTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal leftShiftStage0Idx2Rng8_uid239_fracPostNormExt_uid88_fpAddTest_in : STD_LOGIC_VECTOR (19 downto 0);
signal leftShiftStage0Idx2Rng8_uid239_fracPostNormExt_uid88_fpAddTest_b : STD_LOGIC_VECTOR (19 downto 0);
signal leftShiftStage0Idx3Rng12_uid242_fracPostNormExt_uid88_fpAddTest_in : STD_LOGIC_VECTOR (15 downto 0);
signal leftShiftStage0Idx3Rng12_uid242_fracPostNormExt_uid88_fpAddTest_b : STD_LOGIC_VECTOR (15 downto 0);
signal leftShiftStage0Idx5Rng20_uid248_fracPostNormExt_uid88_fpAddTest_in : STD_LOGIC_VECTOR (7 downto 0);
signal leftShiftStage0Idx5Rng20_uid248_fracPostNormExt_uid88_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal leftShiftStage0Idx6Rng24_uid251_fracPostNormExt_uid88_fpAddTest_in : STD_LOGIC_VECTOR (3 downto 0);
signal leftShiftStage0Idx6Rng24_uid251_fracPostNormExt_uid88_fpAddTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal ypn_uid12_fpAddTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal aSig_uid16_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal aSig_uid16_fpAddTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal bSig_uid17_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal bSig_uid17_fpAddTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal rVStage_uid166_lzCountVal_uid85_fpAddTest_in : STD_LOGIC_VECTOR (7 downto 0);
signal rVStage_uid166_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal vStage_uid168_lzCountVal_uid85_fpAddTest_in : STD_LOGIC_VECTOR (3 downto 0);
signal vStage_uid168_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal leftShiftStage0Idx1_uid237_fracPostNormExt_uid88_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal leftShiftStage0Idx2_uid240_fracPostNormExt_uid88_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal leftShiftStage0Idx3_uid243_fracPostNormExt_uid88_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal leftShiftStage0Idx5_uid249_fracPostNormExt_uid88_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal leftShiftStage0Idx6_uid252_fracPostNormExt_uid88_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal exp_aSig_uid21_fpAddTest_in : STD_LOGIC_VECTOR (30 downto 0);
signal exp_aSig_uid21_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_aSig_uid22_fpAddTest_in : STD_LOGIC_VECTOR (22 downto 0);
signal frac_aSig_uid22_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal sigA_uid50_fpAddTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal sigA_uid50_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal exp_bSig_uid35_fpAddTest_in : STD_LOGIC_VECTOR (30 downto 0);
signal exp_bSig_uid35_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_bSig_uid36_fpAddTest_in : STD_LOGIC_VECTOR (22 downto 0);
signal frac_bSig_uid36_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal sigB_uid51_fpAddTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal sigB_uid51_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal vCount_uid167_lzCountVal_uid85_fpAddTest_a : STD_LOGIC_VECTOR (3 downto 0);
signal vCount_uid167_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal vCount_uid167_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid170_lzCountVal_uid85_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid170_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal expAmExpB_uid60_fpAddTest_a : STD_LOGIC_VECTOR (8 downto 0);
signal expAmExpB_uid60_fpAddTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal expAmExpB_uid60_fpAddTest_o : STD_LOGIC_VECTOR (8 downto 0);
signal expAmExpB_uid60_fpAddTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal effSub_uid52_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal effSub_uid52_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal effSub_uid52_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_bSig_uid17_uid37_fpAddTest_a : STD_LOGIC_VECTOR (7 downto 0);
signal excZ_bSig_uid17_uid37_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal excZ_bSig_uid17_uid37_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid38_fpAddTest_a : STD_LOGIC_VECTOR (7 downto 0);
signal expXIsMax_uid38_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expXIsMax_uid38_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid39_fpAddTest_a : STD_LOGIC_VECTOR (22 downto 0);
signal fracXIsZero_uid39_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal fracXIsZero_uid39_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracBz_uid56_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal fracBz_uid56_fpAddTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal rVStage_uid172_lzCountVal_uid85_fpAddTest_in : STD_LOGIC_VECTOR (3 downto 0);
signal rVStage_uid172_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal vStage_uid174_lzCountVal_uid85_fpAddTest_in : STD_LOGIC_VECTOR (1 downto 0);
signal vStage_uid174_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal shiftedOut_uid63_fpAddTest_a : STD_LOGIC_VECTOR (11 downto 0);
signal shiftedOut_uid63_fpAddTest_b : STD_LOGIC_VECTOR (11 downto 0);
signal shiftedOut_uid63_fpAddTest_o : STD_LOGIC_VECTOR (11 downto 0);
signal shiftedOut_uid63_fpAddTest_cin : STD_LOGIC_VECTOR (0 downto 0);
signal shiftedOut_uid63_fpAddTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_a : STD_LOGIC_VECTOR (11 downto 0);
signal shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (11 downto 0);
signal shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_o : STD_LOGIC_VECTOR (11 downto 0);
signal shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_cin : STD_LOGIC_VECTOR (0 downto 0);
signal shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal rightShiftStageSel5Dto3_uid205_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal rightShiftStageSel5Dto3_uid205_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal rightShiftStageSel2Dto0_uid228_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (2 downto 0);
signal rightShiftStageSel2Dto0_uid228_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal InvExpXIsZero_uid44_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid44_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid43_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid43_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid40_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid40_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oFracB_uid59_fpAddTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal vCount_uid173_lzCountVal_uid85_fpAddTest_a : STD_LOGIC_VECTOR (1 downto 0);
signal vCount_uid173_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal vCount_uid173_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid176_lzCountVal_uid85_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid176_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal iShiftedOut_uid67_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal iShiftedOut_uid67_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selLSBs_in : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selLSBs_b : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selMSBs_in : STD_LOGIC_VECTOR (2 downto 0);
signal rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selMSBs_b : STD_LOGIC_VECTOR (0 downto 0);
signal rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selLSBs_in : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selLSBs_b : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selMSBs_in : STD_LOGIC_VECTOR (2 downto 0);
signal rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selMSBs_b : STD_LOGIC_VECTOR (0 downto 0);
signal rightPaddedIn_uid65_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal rVStage_uid178_lzCountVal_uid85_fpAddTest_in : STD_LOGIC_VECTOR (1 downto 0);
signal rVStage_uid178_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal rightShiftStage0Idx1Rng8_uid186_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage0Idx1Rng8_uid186_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (40 downto 0);
signal rightShiftStage0Idx2Rng16_uid189_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage0Idx2Rng16_uid189_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (32 downto 0);
signal rightShiftStage0Idx3Rng24_uid192_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage0Idx3Rng24_uid192_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0Idx4Rng32_uid195_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage0Idx4Rng32_uid195_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (16 downto 0);
signal rightShiftStage0Idx5Rng40_uid198_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage0Idx5Rng40_uid198_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal rightShiftStage0Idx6Rng48_uid201_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage0Idx6Rng48_uid201_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal vCount_uid179_lzCountVal_uid85_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal vCount_uid179_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal vCount_uid179_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rightShiftStage0Idx1_uid188_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage0Idx2_uid191_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage0Idx3_uid194_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage0Idx4_uid197_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage0Idx5_uid200_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage0Idx6_uid203_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal r_uid180_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0_s : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1_s : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1_q : STD_LOGIC_VECTOR (48 downto 0);
signal aMinusA_uid87_fpAddTest_a : STD_LOGIC_VECTOR (4 downto 0);
signal aMinusA_uid87_fpAddTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal aMinusA_uid87_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expPostNorm_uid92_fpAddTest_a : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNorm_uid92_fpAddTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNorm_uid92_fpAddTest_o : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNorm_uid92_fpAddTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal leftShiftStageSel4Dto2_uid254_fracPostNormExt_uid88_fpAddTest_in : STD_LOGIC_VECTOR (4 downto 0);
signal leftShiftStageSel4Dto2_uid254_fracPostNormExt_uid88_fpAddTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal leftShiftStageSel1Dto0_uid265_fracPostNormExt_uid88_fpAddTest_in : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStageSel1Dto0_uid265_fracPostNormExt_uid88_fpAddTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_s : STD_LOGIC_VECTOR (0 downto 0);
signal rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_q : STD_LOGIC_VECTOR (48 downto 0);
signal invAMinusA_uid130_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal invAMinusA_uid130_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selLSBs_in : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selLSBs_b : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selMSBs_in : STD_LOGIC_VECTOR (2 downto 0);
signal leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selMSBs_b : STD_LOGIC_VECTOR (0 downto 0);
signal rightShiftStage1Idx1Rng1_uid207_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx1Rng1_uid207_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (47 downto 0);
signal rightShiftStage1Idx2Rng2_uid210_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx2Rng2_uid210_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (46 downto 0);
signal rightShiftStage1Idx3Rng3_uid213_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx3Rng3_uid213_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (45 downto 0);
signal rightShiftStage1Idx4Rng4_uid216_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx4Rng4_uid216_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (44 downto 0);
signal rightShiftStage1Idx5Rng5_uid219_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx5Rng5_uid219_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (43 downto 0);
signal rightShiftStage1Idx6Rng6_uid222_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx6Rng6_uid222_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (42 downto 0);
signal rightShiftStage1Idx7Rng7_uid225_alignmentShifter_uid64_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx7Rng7_uid225_alignmentShifter_uid64_fpAddTest_b : STD_LOGIC_VECTOR (41 downto 0);
signal signRReg_uid131_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal signRReg_uid131_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signRReg_uid131_fpAddTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal signRReg_uid131_fpAddTest_d : STD_LOGIC_VECTOR (0 downto 0);
signal signRReg_uid131_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0_q : STD_LOGIC_VECTOR (27 downto 0);
signal leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1_q : STD_LOGIC_VECTOR (27 downto 0);
signal leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal_s : STD_LOGIC_VECTOR (0 downto 0);
signal leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal_q : STD_LOGIC_VECTOR (27 downto 0);
signal rightShiftStage1Idx1_uid209_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx2_uid212_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx3_uid215_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx4_uid218_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx5_uid221_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx6_uid224_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1Idx7_uid227_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal signRInfRZRReg_uid138_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal signRInfRZRReg_uid138_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signRInfRZRReg_uid138_fpAddTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal signRInfRZRReg_uid138_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal leftShiftStage1Idx1Rng1_uid257_fracPostNormExt_uid88_fpAddTest_in : STD_LOGIC_VECTOR (26 downto 0);
signal leftShiftStage1Idx1Rng1_uid257_fracPostNormExt_uid88_fpAddTest_b : STD_LOGIC_VECTOR (26 downto 0);
signal leftShiftStage1Idx2Rng2_uid260_fracPostNormExt_uid88_fpAddTest_in : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx2Rng2_uid260_fracPostNormExt_uid88_fpAddTest_b : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx3Rng3_uid263_fracPostNormExt_uid88_fpAddTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal leftShiftStage1Idx3Rng3_uid263_fracPostNormExt_uid88_fpAddTest_b : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0_s : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0_q : STD_LOGIC_VECTOR (48 downto 0);
signal rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1_s : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1_q : STD_LOGIC_VECTOR (48 downto 0);
signal signRPostExc_uid140_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExc_uid140_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExc_uid140_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal leftShiftStage1Idx1_uid258_fracPostNormExt_uid88_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal leftShiftStage1Idx2_uid261_fracPostNormExt_uid88_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal leftShiftStage1Idx3_uid264_fracPostNormExt_uid88_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_mfinal_s : STD_LOGIC_VECTOR (0 downto 0);
signal rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_mfinal_q : STD_LOGIC_VECTOR (48 downto 0);
signal leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal r_uid231_alignmentShifter_uid64_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal r_uid231_alignmentShifter_uid64_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal fracPostNorm_uid89_fpAddTest_in : STD_LOGIC_VECTOR (27 downto 0);
signal fracPostNorm_uid89_fpAddTest_b : STD_LOGIC_VECTOR (26 downto 0);
signal Sticky0_uid93_fpAddTest_in : STD_LOGIC_VECTOR (0 downto 0);
signal Sticky0_uid93_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal Sticky1_uid94_fpAddTest_in : STD_LOGIC_VECTOR (1 downto 0);
signal Sticky1_uid94_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal Round_uid95_fpAddTest_in : STD_LOGIC_VECTOR (2 downto 0);
signal Round_uid95_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal Guard_uid96_fpAddTest_in : STD_LOGIC_VECTOR (3 downto 0);
signal Guard_uid96_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal LSB_uid97_fpAddTest_in : STD_LOGIC_VECTOR (4 downto 0);
signal LSB_uid97_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal alignFracBPostShiftOut_uid68_fpAddTest_a : STD_LOGIC_VECTOR (48 downto 0);
signal alignFracBPostShiftOut_uid68_fpAddTest_b : STD_LOGIC_VECTOR (48 downto 0);
signal alignFracBPostShiftOut_uid68_fpAddTest_q : STD_LOGIC_VECTOR (48 downto 0);
signal fracPostNormRndRange_uid102_fpAddTest_in : STD_LOGIC_VECTOR (25 downto 0);
signal fracPostNormRndRange_uid102_fpAddTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal rndBitCond_uid98_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal stickyBits_uid69_fpAddTest_in : STD_LOGIC_VECTOR (22 downto 0);
signal stickyBits_uid69_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal alignFracBOpRange_uid78_fpAddTest_in : STD_LOGIC_VECTOR (48 downto 0);
signal alignFracBOpRange_uid78_fpAddTest_b : STD_LOGIC_VECTOR (25 downto 0);
signal expFracR_uid103_fpAddTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal rBi_uid100_fpAddTest_a : STD_LOGIC_VECTOR (4 downto 0);
signal rBi_uid100_fpAddTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal rBi_uid100_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal cmpEQ_stickyBits_cZwF_uid71_fpAddTest_a : STD_LOGIC_VECTOR (22 downto 0);
signal cmpEQ_stickyBits_cZwF_uid71_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal cmpEQ_stickyBits_cZwF_uid71_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracBAddOp_uid80_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0);
signal roundBit_uid101_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal roundBit_uid101_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invCmpEQ_stickyBits_cZwF_uid72_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal invCmpEQ_stickyBits_cZwF_uid72_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracBAddOpPostXor_uid81_fpAddTest_a : STD_LOGIC_VECTOR (26 downto 0);
signal fracBAddOpPostXor_uid81_fpAddTest_b : STD_LOGIC_VECTOR (26 downto 0);
signal fracBAddOpPostXor_uid81_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0);
signal rndExpFrac_uid104_fpAddTest_a : STD_LOGIC_VECTOR (34 downto 0);
signal rndExpFrac_uid104_fpAddTest_b : STD_LOGIC_VECTOR (34 downto 0);
signal rndExpFrac_uid104_fpAddTest_o : STD_LOGIC_VECTOR (34 downto 0);
signal rndExpFrac_uid104_fpAddTest_q : STD_LOGIC_VECTOR (34 downto 0);
signal invSticky_uid73_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal invSticky_uid73_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rndExp_uid106_fpAddTest_in : STD_LOGIC_VECTOR (33 downto 0);
signal rndExp_uid106_fpAddTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal rndExpFracOvfBits_uid109_fpAddTest_in : STD_LOGIC_VECTOR (33 downto 0);
signal rndExpFracOvfBits_uid109_fpAddTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal rUdfExtraBit_uid115_fpAddTest_in : STD_LOGIC_VECTOR (33 downto 0);
signal rUdfExtraBit_uid115_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPreExc_uid117_fpAddTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPreExc_uid117_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal expRPreExc_uid118_fpAddTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal expRPreExc_uid118_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal effSubInvSticky_uid74_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal effSubInvSticky_uid74_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal effSubInvSticky_uid74_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rOvfEQMax_uid107_fpAddTest_a : STD_LOGIC_VECTOR (9 downto 0);
signal rOvfEQMax_uid107_fpAddTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal rOvfEQMax_uid107_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rUdfEQMin_uid114_fpAddTest_a : STD_LOGIC_VECTOR (9 downto 0);
signal rUdfEQMin_uid114_fpAddTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal rUdfEQMin_uid114_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rOvfExtraBits_uid110_fpAddTest_a : STD_LOGIC_VECTOR (4 downto 0);
signal rOvfExtraBits_uid110_fpAddTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal rOvfExtraBits_uid110_fpAddTest_o : STD_LOGIC_VECTOR (4 downto 0);
signal rOvfExtraBits_uid110_fpAddTest_cin : STD_LOGIC_VECTOR (0 downto 0);
signal rOvfExtraBits_uid110_fpAddTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal rUdf_uid116_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal rUdf_uid116_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal rUdf_uid116_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracAAddOp_uid77_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0);
signal rOvf_uid111_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal rOvf_uid111_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal rOvf_uid111_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRZeroVInC_uid120_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal fracAddResult_uid82_fpAddTest_a : STD_LOGIC_VECTOR (27 downto 0);
signal fracAddResult_uid82_fpAddTest_b : STD_LOGIC_VECTOR (27 downto 0);
signal fracAddResult_uid82_fpAddTest_o : STD_LOGIC_VECTOR (27 downto 0);
signal fracAddResult_uid82_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal rInfOvf_uid122_fpAddTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal rInfOvf_uid122_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal rInfOvf_uid122_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRZero_uid121_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rangeFracAddResultMwfp3Dto0_uid83_fpAddTest_in : STD_LOGIC_VECTOR (26 downto 0);
signal rangeFracAddResultMwfp3Dto0_uid83_fpAddTest_b : STD_LOGIC_VECTOR (26 downto 0);
signal excRInfVInC_uid123_fpAddTest_q : STD_LOGIC_VECTOR (5 downto 0);
signal fracGRS_uid84_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal excRInf_uid124_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rVStage_uid152_lzCountVal_uid85_fpAddTest_in : STD_LOGIC_VECTOR (27 downto 0);
signal rVStage_uid152_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (15 downto 0);
signal vStage_uid155_lzCountVal_uid85_fpAddTest_in : STD_LOGIC_VECTOR (11 downto 0);
signal vStage_uid155_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (11 downto 0);
signal concExc_uid128_fpAddTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal vCount_uid153_lzCountVal_uid85_fpAddTest_a : STD_LOGIC_VECTOR (15 downto 0);
signal vCount_uid153_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (15 downto 0);
signal vCount_uid153_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal cStage_uid156_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (15 downto 0);
signal excREnc_uid129_fpAddTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal vStagei_uid158_lzCountVal_uid85_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid158_lzCountVal_uid85_fpAddTest_q : STD_LOGIC_VECTOR (15 downto 0);
signal fracRPostExc_uid144_fpAddTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostExc_uid144_fpAddTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPostExc_uid148_fpAddTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal expRPostExc_uid148_fpAddTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal rVStage_uid160_lzCountVal_uid85_fpAddTest_in : STD_LOGIC_VECTOR (15 downto 0);
signal rVStage_uid160_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal vStage_uid162_lzCountVal_uid85_fpAddTest_in : STD_LOGIC_VECTOR (7 downto 0);
signal vStage_uid162_lzCountVal_uid85_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal R_uid149_fpAddTest_q : STD_LOGIC_VECTOR (31 downto 0);
begin
-- VCC(CONSTANT,1)
-- cAmA_uid86_fpAddTest(CONSTANT,85)
cAmA_uid86_fpAddTest_q <= "11100";
-- zs_uid151_lzCountVal_uid85_fpAddTest(CONSTANT,150)
zs_uid151_lzCountVal_uid85_fpAddTest_q <= "0000000000000000";
-- sigY_uid11_fpAddTest(BITSELECT,10)@0
sigY_uid11_fpAddTest_in <= STD_LOGIC_VECTOR(b);
sigY_uid11_fpAddTest_b <= sigY_uid11_fpAddTest_in(31 downto 31);
-- expY_uid10_fpAddTest(BITSELECT,9)@0
expY_uid10_fpAddTest_in <= b;
expY_uid10_fpAddTest_b <= expY_uid10_fpAddTest_in(30 downto 23);
-- fracY_uid9_fpAddTest(BITSELECT,8)@0
fracY_uid9_fpAddTest_in <= b;
fracY_uid9_fpAddTest_b <= fracY_uid9_fpAddTest_in(22 downto 0);
-- ypn_uid12_fpAddTest(BITJOIN,11)@0
ypn_uid12_fpAddTest_q <= sigY_uid11_fpAddTest_b & expY_uid10_fpAddTest_b & fracY_uid9_fpAddTest_b;
-- GND(CONSTANT,0)
GND_q <= "0";
-- expFracY_uid7_fpAddTest(BITSELECT,6)@0
expFracY_uid7_fpAddTest_in <= b;
expFracY_uid7_fpAddTest_b <= expFracY_uid7_fpAddTest_in(30 downto 0);
-- expFracX_uid6_fpAddTest(BITSELECT,5)@0
expFracX_uid6_fpAddTest_in <= a;
expFracX_uid6_fpAddTest_b <= expFracX_uid6_fpAddTest_in(30 downto 0);
-- xGTEy_uid8_fpAddTest(COMPARE,7)@0
xGTEy_uid8_fpAddTest_cin <= GND_q;
xGTEy_uid8_fpAddTest_a <= STD_LOGIC_VECTOR("00" & expFracX_uid6_fpAddTest_b) & '0';
xGTEy_uid8_fpAddTest_b <= STD_LOGIC_VECTOR("00" & expFracY_uid7_fpAddTest_b) & xGTEy_uid8_fpAddTest_cin(0);
xGTEy_uid8_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xGTEy_uid8_fpAddTest_a) - UNSIGNED(xGTEy_uid8_fpAddTest_b));
xGTEy_uid8_fpAddTest_n(0) <= not (xGTEy_uid8_fpAddTest_o(33));
-- bSig_uid17_fpAddTest(MUX,16)@0
bSig_uid17_fpAddTest_s <= xGTEy_uid8_fpAddTest_n;
bSig_uid17_fpAddTest: PROCESS (bSig_uid17_fpAddTest_s, en, a, ypn_uid12_fpAddTest_q)
BEGIN
CASE (bSig_uid17_fpAddTest_s) IS
WHEN "0" => bSig_uid17_fpAddTest_q <= a;
WHEN "1" => bSig_uid17_fpAddTest_q <= ypn_uid12_fpAddTest_q;
WHEN OTHERS => bSig_uid17_fpAddTest_q <= (others => '0');
END CASE;
END PROCESS;
-- sigB_uid51_fpAddTest(BITSELECT,50)@0
sigB_uid51_fpAddTest_in <= STD_LOGIC_VECTOR(bSig_uid17_fpAddTest_q);
sigB_uid51_fpAddTest_b <= sigB_uid51_fpAddTest_in(31 downto 31);
-- aSig_uid16_fpAddTest(MUX,15)@0
aSig_uid16_fpAddTest_s <= xGTEy_uid8_fpAddTest_n;
aSig_uid16_fpAddTest: PROCESS (aSig_uid16_fpAddTest_s, en, ypn_uid12_fpAddTest_q, a)
BEGIN
CASE (aSig_uid16_fpAddTest_s) IS
WHEN "0" => aSig_uid16_fpAddTest_q <= ypn_uid12_fpAddTest_q;
WHEN "1" => aSig_uid16_fpAddTest_q <= a;
WHEN OTHERS => aSig_uid16_fpAddTest_q <= (others => '0');
END CASE;
END PROCESS;
-- sigA_uid50_fpAddTest(BITSELECT,49)@0
sigA_uid50_fpAddTest_in <= STD_LOGIC_VECTOR(aSig_uid16_fpAddTest_q);
sigA_uid50_fpAddTest_b <= sigA_uid50_fpAddTest_in(31 downto 31);
-- effSub_uid52_fpAddTest(LOGICAL,51)@0
effSub_uid52_fpAddTest_a <= sigA_uid50_fpAddTest_b;
effSub_uid52_fpAddTest_b <= sigB_uid51_fpAddTest_b;
effSub_uid52_fpAddTest_q <= effSub_uid52_fpAddTest_a xor effSub_uid52_fpAddTest_b;
-- exp_bSig_uid35_fpAddTest(BITSELECT,34)@0
exp_bSig_uid35_fpAddTest_in <= bSig_uid17_fpAddTest_q(30 downto 0);
exp_bSig_uid35_fpAddTest_b <= exp_bSig_uid35_fpAddTest_in(30 downto 23);
-- exp_aSig_uid21_fpAddTest(BITSELECT,20)@0
exp_aSig_uid21_fpAddTest_in <= aSig_uid16_fpAddTest_q(30 downto 0);
exp_aSig_uid21_fpAddTest_b <= exp_aSig_uid21_fpAddTest_in(30 downto 23);
-- expAmExpB_uid60_fpAddTest(SUB,59)@0
expAmExpB_uid60_fpAddTest_a <= STD_LOGIC_VECTOR("0" & exp_aSig_uid21_fpAddTest_b);
expAmExpB_uid60_fpAddTest_b <= STD_LOGIC_VECTOR("0" & exp_bSig_uid35_fpAddTest_b);
expAmExpB_uid60_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expAmExpB_uid60_fpAddTest_a) - UNSIGNED(expAmExpB_uid60_fpAddTest_b));
expAmExpB_uid60_fpAddTest_q <= expAmExpB_uid60_fpAddTest_o(8 downto 0);
-- cWFP2_uid61_fpAddTest(CONSTANT,60)
cWFP2_uid61_fpAddTest_q <= "11001";
-- shiftedOut_uid63_fpAddTest(COMPARE,62)@0
shiftedOut_uid63_fpAddTest_cin <= GND_q;
shiftedOut_uid63_fpAddTest_a <= STD_LOGIC_VECTOR("000000" & cWFP2_uid61_fpAddTest_q) & '0';
shiftedOut_uid63_fpAddTest_b <= STD_LOGIC_VECTOR("00" & expAmExpB_uid60_fpAddTest_q) & shiftedOut_uid63_fpAddTest_cin(0);
shiftedOut_uid63_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftedOut_uid63_fpAddTest_a) - UNSIGNED(shiftedOut_uid63_fpAddTest_b));
shiftedOut_uid63_fpAddTest_c(0) <= shiftedOut_uid63_fpAddTest_o(11);
-- iShiftedOut_uid67_fpAddTest(LOGICAL,66)@0
iShiftedOut_uid67_fpAddTest_a <= shiftedOut_uid63_fpAddTest_c;
iShiftedOut_uid67_fpAddTest_q <= not (iShiftedOut_uid67_fpAddTest_a);
-- rightShiftStage0Idx7_uid204_alignmentShifter_uid64_fpAddTest(CONSTANT,203)
rightShiftStage0Idx7_uid204_alignmentShifter_uid64_fpAddTest_q <= "0000000000000000000000000000000000000000000000000";
-- rightShiftStage1Idx7Pad7_uid226_alignmentShifter_uid64_fpAddTest(CONSTANT,225)
rightShiftStage1Idx7Pad7_uid226_alignmentShifter_uid64_fpAddTest_q <= "0000000";
-- rightShiftStage0Idx6Pad48_uid202_alignmentShifter_uid64_fpAddTest(CONSTANT,201)
rightShiftStage0Idx6Pad48_uid202_alignmentShifter_uid64_fpAddTest_q <= "000000000000000000000000000000000000000000000000";
-- cstAllZWE_uid20_fpAddTest(CONSTANT,19)
cstAllZWE_uid20_fpAddTest_q <= "00000000";
-- excZ_bSig_uid17_uid37_fpAddTest(LOGICAL,36)@0
excZ_bSig_uid17_uid37_fpAddTest_a <= exp_bSig_uid35_fpAddTest_b;
excZ_bSig_uid17_uid37_fpAddTest_b <= cstAllZWE_uid20_fpAddTest_q;
excZ_bSig_uid17_uid37_fpAddTest_q <= "1" WHEN excZ_bSig_uid17_uid37_fpAddTest_a = excZ_bSig_uid17_uid37_fpAddTest_b ELSE "0";
-- InvExpXIsZero_uid44_fpAddTest(LOGICAL,43)@0
InvExpXIsZero_uid44_fpAddTest_a <= excZ_bSig_uid17_uid37_fpAddTest_q;
InvExpXIsZero_uid44_fpAddTest_q <= not (InvExpXIsZero_uid44_fpAddTest_a);
-- cstZeroWF_uid19_fpAddTest(CONSTANT,18)
cstZeroWF_uid19_fpAddTest_q <= "00000000000000000000000";
-- frac_bSig_uid36_fpAddTest(BITSELECT,35)@0
frac_bSig_uid36_fpAddTest_in <= bSig_uid17_fpAddTest_q(22 downto 0);
frac_bSig_uid36_fpAddTest_b <= frac_bSig_uid36_fpAddTest_in(22 downto 0);
-- fracBz_uid56_fpAddTest(MUX,55)@0
fracBz_uid56_fpAddTest_s <= excZ_bSig_uid17_uid37_fpAddTest_q;
fracBz_uid56_fpAddTest: PROCESS (fracBz_uid56_fpAddTest_s, en, frac_bSig_uid36_fpAddTest_b, cstZeroWF_uid19_fpAddTest_q)
BEGIN
CASE (fracBz_uid56_fpAddTest_s) IS
WHEN "0" => fracBz_uid56_fpAddTest_q <= frac_bSig_uid36_fpAddTest_b;
WHEN "1" => fracBz_uid56_fpAddTest_q <= cstZeroWF_uid19_fpAddTest_q;
WHEN OTHERS => fracBz_uid56_fpAddTest_q <= (others => '0');
END CASE;
END PROCESS;
-- oFracB_uid59_fpAddTest(BITJOIN,58)@0
oFracB_uid59_fpAddTest_q <= InvExpXIsZero_uid44_fpAddTest_q & fracBz_uid56_fpAddTest_q;
-- padConst_uid64_fpAddTest(CONSTANT,63)
padConst_uid64_fpAddTest_q <= "0000000000000000000000000";
-- rightPaddedIn_uid65_fpAddTest(BITJOIN,64)@0
rightPaddedIn_uid65_fpAddTest_q <= oFracB_uid59_fpAddTest_q & padConst_uid64_fpAddTest_q;
-- rightShiftStage0Idx6Rng48_uid201_alignmentShifter_uid64_fpAddTest(BITSELECT,200)@0
rightShiftStage0Idx6Rng48_uid201_alignmentShifter_uid64_fpAddTest_in <= rightPaddedIn_uid65_fpAddTest_q;
rightShiftStage0Idx6Rng48_uid201_alignmentShifter_uid64_fpAddTest_b <= rightShiftStage0Idx6Rng48_uid201_alignmentShifter_uid64_fpAddTest_in(48 downto 48);
-- rightShiftStage0Idx6_uid203_alignmentShifter_uid64_fpAddTest(BITJOIN,202)@0
rightShiftStage0Idx6_uid203_alignmentShifter_uid64_fpAddTest_q <= rightShiftStage0Idx6Pad48_uid202_alignmentShifter_uid64_fpAddTest_q & rightShiftStage0Idx6Rng48_uid201_alignmentShifter_uid64_fpAddTest_b;
-- rightShiftStage0Idx5Pad40_uid199_alignmentShifter_uid64_fpAddTest(CONSTANT,198)
rightShiftStage0Idx5Pad40_uid199_alignmentShifter_uid64_fpAddTest_q <= "0000000000000000000000000000000000000000";
-- rightShiftStage0Idx5Rng40_uid198_alignmentShifter_uid64_fpAddTest(BITSELECT,197)@0
rightShiftStage0Idx5Rng40_uid198_alignmentShifter_uid64_fpAddTest_in <= rightPaddedIn_uid65_fpAddTest_q;
rightShiftStage0Idx5Rng40_uid198_alignmentShifter_uid64_fpAddTest_b <= rightShiftStage0Idx5Rng40_uid198_alignmentShifter_uid64_fpAddTest_in(48 downto 40);
-- rightShiftStage0Idx5_uid200_alignmentShifter_uid64_fpAddTest(BITJOIN,199)@0
rightShiftStage0Idx5_uid200_alignmentShifter_uid64_fpAddTest_q <= rightShiftStage0Idx5Pad40_uid199_alignmentShifter_uid64_fpAddTest_q & rightShiftStage0Idx5Rng40_uid198_alignmentShifter_uid64_fpAddTest_b;
-- rightShiftStage0Idx4Pad32_uid196_alignmentShifter_uid64_fpAddTest(CONSTANT,195)
rightShiftStage0Idx4Pad32_uid196_alignmentShifter_uid64_fpAddTest_q <= "00000000000000000000000000000000";
-- rightShiftStage0Idx4Rng32_uid195_alignmentShifter_uid64_fpAddTest(BITSELECT,194)@0
rightShiftStage0Idx4Rng32_uid195_alignmentShifter_uid64_fpAddTest_in <= rightPaddedIn_uid65_fpAddTest_q;
rightShiftStage0Idx4Rng32_uid195_alignmentShifter_uid64_fpAddTest_b <= rightShiftStage0Idx4Rng32_uid195_alignmentShifter_uid64_fpAddTest_in(48 downto 32);
-- rightShiftStage0Idx4_uid197_alignmentShifter_uid64_fpAddTest(BITJOIN,196)@0
rightShiftStage0Idx4_uid197_alignmentShifter_uid64_fpAddTest_q <= rightShiftStage0Idx4Pad32_uid196_alignmentShifter_uid64_fpAddTest_q & rightShiftStage0Idx4Rng32_uid195_alignmentShifter_uid64_fpAddTest_b;
-- rightShiftStageSel5Dto3_uid205_alignmentShifter_uid64_fpAddTest(BITSELECT,204)@0
rightShiftStageSel5Dto3_uid205_alignmentShifter_uid64_fpAddTest_in <= expAmExpB_uid60_fpAddTest_q(5 downto 0);
rightShiftStageSel5Dto3_uid205_alignmentShifter_uid64_fpAddTest_b <= rightShiftStageSel5Dto3_uid205_alignmentShifter_uid64_fpAddTest_in(5 downto 3);
-- rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selLSBs(BITSELECT,267)@0
rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selLSBs_in <= rightShiftStageSel5Dto3_uid205_alignmentShifter_uid64_fpAddTest_b(1 downto 0);
rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selLSBs_b <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selLSBs_in(1 downto 0);
-- rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1(MUX,270)@0
rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1_s <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selLSBs_b;
rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1: PROCESS (rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1_s, en, rightShiftStage0Idx4_uid197_alignmentShifter_uid64_fpAddTest_q, rightShiftStage0Idx5_uid200_alignmentShifter_uid64_fpAddTest_q, rightShiftStage0Idx6_uid203_alignmentShifter_uid64_fpAddTest_q, rightShiftStage0Idx7_uid204_alignmentShifter_uid64_fpAddTest_q)
BEGIN
CASE (rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1_s) IS
WHEN "00" => rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1_q <= rightShiftStage0Idx4_uid197_alignmentShifter_uid64_fpAddTest_q;
WHEN "01" => rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1_q <= rightShiftStage0Idx5_uid200_alignmentShifter_uid64_fpAddTest_q;
WHEN "10" => rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1_q <= rightShiftStage0Idx6_uid203_alignmentShifter_uid64_fpAddTest_q;
WHEN "11" => rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1_q <= rightShiftStage0Idx7_uid204_alignmentShifter_uid64_fpAddTest_q;
WHEN OTHERS => rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1_q <= (others => '0');
END CASE;
END PROCESS;
-- rightShiftStage0Idx3Pad24_uid193_alignmentShifter_uid64_fpAddTest(CONSTANT,192)
rightShiftStage0Idx3Pad24_uid193_alignmentShifter_uid64_fpAddTest_q <= "000000000000000000000000";
-- rightShiftStage0Idx3Rng24_uid192_alignmentShifter_uid64_fpAddTest(BITSELECT,191)@0
rightShiftStage0Idx3Rng24_uid192_alignmentShifter_uid64_fpAddTest_in <= rightPaddedIn_uid65_fpAddTest_q;
rightShiftStage0Idx3Rng24_uid192_alignmentShifter_uid64_fpAddTest_b <= rightShiftStage0Idx3Rng24_uid192_alignmentShifter_uid64_fpAddTest_in(48 downto 24);
-- rightShiftStage0Idx3_uid194_alignmentShifter_uid64_fpAddTest(BITJOIN,193)@0
rightShiftStage0Idx3_uid194_alignmentShifter_uid64_fpAddTest_q <= rightShiftStage0Idx3Pad24_uid193_alignmentShifter_uid64_fpAddTest_q & rightShiftStage0Idx3Rng24_uid192_alignmentShifter_uid64_fpAddTest_b;
-- rightShiftStage0Idx2Rng16_uid189_alignmentShifter_uid64_fpAddTest(BITSELECT,188)@0
rightShiftStage0Idx2Rng16_uid189_alignmentShifter_uid64_fpAddTest_in <= rightPaddedIn_uid65_fpAddTest_q;
rightShiftStage0Idx2Rng16_uid189_alignmentShifter_uid64_fpAddTest_b <= rightShiftStage0Idx2Rng16_uid189_alignmentShifter_uid64_fpAddTest_in(48 downto 16);
-- rightShiftStage0Idx2_uid191_alignmentShifter_uid64_fpAddTest(BITJOIN,190)@0
rightShiftStage0Idx2_uid191_alignmentShifter_uid64_fpAddTest_q <= zs_uid151_lzCountVal_uid85_fpAddTest_q & rightShiftStage0Idx2Rng16_uid189_alignmentShifter_uid64_fpAddTest_b;
-- rightShiftStage0Idx1Rng8_uid186_alignmentShifter_uid64_fpAddTest(BITSELECT,185)@0
rightShiftStage0Idx1Rng8_uid186_alignmentShifter_uid64_fpAddTest_in <= rightPaddedIn_uid65_fpAddTest_q;
rightShiftStage0Idx1Rng8_uid186_alignmentShifter_uid64_fpAddTest_b <= rightShiftStage0Idx1Rng8_uid186_alignmentShifter_uid64_fpAddTest_in(48 downto 8);
-- rightShiftStage0Idx1_uid188_alignmentShifter_uid64_fpAddTest(BITJOIN,187)@0
rightShiftStage0Idx1_uid188_alignmentShifter_uid64_fpAddTest_q <= cstAllZWE_uid20_fpAddTest_q & rightShiftStage0Idx1Rng8_uid186_alignmentShifter_uid64_fpAddTest_b;
-- rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0(MUX,269)@0
rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0_s <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selLSBs_b;
rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0: PROCESS (rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0_s, en, rightPaddedIn_uid65_fpAddTest_q, rightShiftStage0Idx1_uid188_alignmentShifter_uid64_fpAddTest_q, rightShiftStage0Idx2_uid191_alignmentShifter_uid64_fpAddTest_q, rightShiftStage0Idx3_uid194_alignmentShifter_uid64_fpAddTest_q)
BEGIN
CASE (rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0_s) IS
WHEN "00" => rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0_q <= rightPaddedIn_uid65_fpAddTest_q;
WHEN "01" => rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0_q <= rightShiftStage0Idx1_uid188_alignmentShifter_uid64_fpAddTest_q;
WHEN "10" => rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0_q <= rightShiftStage0Idx2_uid191_alignmentShifter_uid64_fpAddTest_q;
WHEN "11" => rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0_q <= rightShiftStage0Idx3_uid194_alignmentShifter_uid64_fpAddTest_q;
WHEN OTHERS => rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0_q <= (others => '0');
END CASE;
END PROCESS;
-- rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selMSBs(BITSELECT,268)@0
rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selMSBs_in <= rightShiftStageSel5Dto3_uid205_alignmentShifter_uid64_fpAddTest_b;
rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selMSBs_b <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selMSBs_in(2 downto 2);
-- rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal(MUX,271)@0
rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_s <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_selMSBs_b;
rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal: PROCESS (rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_s, en, rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0_q, rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1_q)
BEGIN
CASE (rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_s) IS
WHEN "0" => rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_q <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_0_q;
WHEN "1" => rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_q <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_msplit_1_q;
WHEN OTHERS => rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_q <= (others => '0');
END CASE;
END PROCESS;
-- rightShiftStage1Idx7Rng7_uid225_alignmentShifter_uid64_fpAddTest(BITSELECT,224)@0
rightShiftStage1Idx7Rng7_uid225_alignmentShifter_uid64_fpAddTest_in <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_q;
rightShiftStage1Idx7Rng7_uid225_alignmentShifter_uid64_fpAddTest_b <= rightShiftStage1Idx7Rng7_uid225_alignmentShifter_uid64_fpAddTest_in(48 downto 7);
-- rightShiftStage1Idx7_uid227_alignmentShifter_uid64_fpAddTest(BITJOIN,226)@0
rightShiftStage1Idx7_uid227_alignmentShifter_uid64_fpAddTest_q <= rightShiftStage1Idx7Pad7_uid226_alignmentShifter_uid64_fpAddTest_q & rightShiftStage1Idx7Rng7_uid225_alignmentShifter_uid64_fpAddTest_b;
-- rightShiftStage1Idx6Pad6_uid223_alignmentShifter_uid64_fpAddTest(CONSTANT,222)
rightShiftStage1Idx6Pad6_uid223_alignmentShifter_uid64_fpAddTest_q <= "000000";
-- rightShiftStage1Idx6Rng6_uid222_alignmentShifter_uid64_fpAddTest(BITSELECT,221)@0
rightShiftStage1Idx6Rng6_uid222_alignmentShifter_uid64_fpAddTest_in <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_q;
rightShiftStage1Idx6Rng6_uid222_alignmentShifter_uid64_fpAddTest_b <= rightShiftStage1Idx6Rng6_uid222_alignmentShifter_uid64_fpAddTest_in(48 downto 6);
-- rightShiftStage1Idx6_uid224_alignmentShifter_uid64_fpAddTest(BITJOIN,223)@0
rightShiftStage1Idx6_uid224_alignmentShifter_uid64_fpAddTest_q <= rightShiftStage1Idx6Pad6_uid223_alignmentShifter_uid64_fpAddTest_q & rightShiftStage1Idx6Rng6_uid222_alignmentShifter_uid64_fpAddTest_b;
-- rightShiftStage1Idx5Pad5_uid220_alignmentShifter_uid64_fpAddTest(CONSTANT,219)
rightShiftStage1Idx5Pad5_uid220_alignmentShifter_uid64_fpAddTest_q <= "00000";
-- rightShiftStage1Idx5Rng5_uid219_alignmentShifter_uid64_fpAddTest(BITSELECT,218)@0
rightShiftStage1Idx5Rng5_uid219_alignmentShifter_uid64_fpAddTest_in <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_q;
rightShiftStage1Idx5Rng5_uid219_alignmentShifter_uid64_fpAddTest_b <= rightShiftStage1Idx5Rng5_uid219_alignmentShifter_uid64_fpAddTest_in(48 downto 5);
-- rightShiftStage1Idx5_uid221_alignmentShifter_uid64_fpAddTest(BITJOIN,220)@0
rightShiftStage1Idx5_uid221_alignmentShifter_uid64_fpAddTest_q <= rightShiftStage1Idx5Pad5_uid220_alignmentShifter_uid64_fpAddTest_q & rightShiftStage1Idx5Rng5_uid219_alignmentShifter_uid64_fpAddTest_b;
-- zs_uid165_lzCountVal_uid85_fpAddTest(CONSTANT,164)
zs_uid165_lzCountVal_uid85_fpAddTest_q <= "0000";
-- rightShiftStage1Idx4Rng4_uid216_alignmentShifter_uid64_fpAddTest(BITSELECT,215)@0
rightShiftStage1Idx4Rng4_uid216_alignmentShifter_uid64_fpAddTest_in <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_q;
rightShiftStage1Idx4Rng4_uid216_alignmentShifter_uid64_fpAddTest_b <= rightShiftStage1Idx4Rng4_uid216_alignmentShifter_uid64_fpAddTest_in(48 downto 4);
-- rightShiftStage1Idx4_uid218_alignmentShifter_uid64_fpAddTest(BITJOIN,217)@0
rightShiftStage1Idx4_uid218_alignmentShifter_uid64_fpAddTest_q <= zs_uid165_lzCountVal_uid85_fpAddTest_q & rightShiftStage1Idx4Rng4_uid216_alignmentShifter_uid64_fpAddTest_b;
-- rightShiftStageSel2Dto0_uid228_alignmentShifter_uid64_fpAddTest(BITSELECT,227)@0
rightShiftStageSel2Dto0_uid228_alignmentShifter_uid64_fpAddTest_in <= expAmExpB_uid60_fpAddTest_q(2 downto 0);
rightShiftStageSel2Dto0_uid228_alignmentShifter_uid64_fpAddTest_b <= rightShiftStageSel2Dto0_uid228_alignmentShifter_uid64_fpAddTest_in(2 downto 0);
-- rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selLSBs(BITSELECT,272)@0
rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selLSBs_in <= rightShiftStageSel2Dto0_uid228_alignmentShifter_uid64_fpAddTest_b(1 downto 0);
rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selLSBs_b <= rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selLSBs_in(1 downto 0);
-- rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1(MUX,275)@0
rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1_s <= rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selLSBs_b;
rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1: PROCESS (rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1_s, en, rightShiftStage1Idx4_uid218_alignmentShifter_uid64_fpAddTest_q, rightShiftStage1Idx5_uid221_alignmentShifter_uid64_fpAddTest_q, rightShiftStage1Idx6_uid224_alignmentShifter_uid64_fpAddTest_q, rightShiftStage1Idx7_uid227_alignmentShifter_uid64_fpAddTest_q)
BEGIN
CASE (rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1_s) IS
WHEN "00" => rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1_q <= rightShiftStage1Idx4_uid218_alignmentShifter_uid64_fpAddTest_q;
WHEN "01" => rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1_q <= rightShiftStage1Idx5_uid221_alignmentShifter_uid64_fpAddTest_q;
WHEN "10" => rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1_q <= rightShiftStage1Idx6_uid224_alignmentShifter_uid64_fpAddTest_q;
WHEN "11" => rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1_q <= rightShiftStage1Idx7_uid227_alignmentShifter_uid64_fpAddTest_q;
WHEN OTHERS => rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1_q <= (others => '0');
END CASE;
END PROCESS;
-- rightShiftStage1Idx3Pad3_uid214_alignmentShifter_uid64_fpAddTest(CONSTANT,213)
rightShiftStage1Idx3Pad3_uid214_alignmentShifter_uid64_fpAddTest_q <= "000";
-- rightShiftStage1Idx3Rng3_uid213_alignmentShifter_uid64_fpAddTest(BITSELECT,212)@0
rightShiftStage1Idx3Rng3_uid213_alignmentShifter_uid64_fpAddTest_in <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_q;
rightShiftStage1Idx3Rng3_uid213_alignmentShifter_uid64_fpAddTest_b <= rightShiftStage1Idx3Rng3_uid213_alignmentShifter_uid64_fpAddTest_in(48 downto 3);
-- rightShiftStage1Idx3_uid215_alignmentShifter_uid64_fpAddTest(BITJOIN,214)@0
rightShiftStage1Idx3_uid215_alignmentShifter_uid64_fpAddTest_q <= rightShiftStage1Idx3Pad3_uid214_alignmentShifter_uid64_fpAddTest_q & rightShiftStage1Idx3Rng3_uid213_alignmentShifter_uid64_fpAddTest_b;
-- zs_uid171_lzCountVal_uid85_fpAddTest(CONSTANT,170)
zs_uid171_lzCountVal_uid85_fpAddTest_q <= "00";
-- rightShiftStage1Idx2Rng2_uid210_alignmentShifter_uid64_fpAddTest(BITSELECT,209)@0
rightShiftStage1Idx2Rng2_uid210_alignmentShifter_uid64_fpAddTest_in <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_q;
rightShiftStage1Idx2Rng2_uid210_alignmentShifter_uid64_fpAddTest_b <= rightShiftStage1Idx2Rng2_uid210_alignmentShifter_uid64_fpAddTest_in(48 downto 2);
-- rightShiftStage1Idx2_uid212_alignmentShifter_uid64_fpAddTest(BITJOIN,211)@0
rightShiftStage1Idx2_uid212_alignmentShifter_uid64_fpAddTest_q <= zs_uid171_lzCountVal_uid85_fpAddTest_q & rightShiftStage1Idx2Rng2_uid210_alignmentShifter_uid64_fpAddTest_b;
-- rightShiftStage1Idx1Rng1_uid207_alignmentShifter_uid64_fpAddTest(BITSELECT,206)@0
rightShiftStage1Idx1Rng1_uid207_alignmentShifter_uid64_fpAddTest_in <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_q;
rightShiftStage1Idx1Rng1_uid207_alignmentShifter_uid64_fpAddTest_b <= rightShiftStage1Idx1Rng1_uid207_alignmentShifter_uid64_fpAddTest_in(48 downto 1);
-- rightShiftStage1Idx1_uid209_alignmentShifter_uid64_fpAddTest(BITJOIN,208)@0
rightShiftStage1Idx1_uid209_alignmentShifter_uid64_fpAddTest_q <= GND_q & rightShiftStage1Idx1Rng1_uid207_alignmentShifter_uid64_fpAddTest_b;
-- rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0(MUX,274)@0
rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0_s <= rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selLSBs_b;
rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0: PROCESS (rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0_s, en, rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_q, rightShiftStage1Idx1_uid209_alignmentShifter_uid64_fpAddTest_q, rightShiftStage1Idx2_uid212_alignmentShifter_uid64_fpAddTest_q, rightShiftStage1Idx3_uid215_alignmentShifter_uid64_fpAddTest_q)
BEGIN
CASE (rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0_s) IS
WHEN "00" => rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0_q <= rightShiftStage0_uid206_alignmentShifter_uid64_fpAddTest_mfinal_q;
WHEN "01" => rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0_q <= rightShiftStage1Idx1_uid209_alignmentShifter_uid64_fpAddTest_q;
WHEN "10" => rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0_q <= rightShiftStage1Idx2_uid212_alignmentShifter_uid64_fpAddTest_q;
WHEN "11" => rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0_q <= rightShiftStage1Idx3_uid215_alignmentShifter_uid64_fpAddTest_q;
WHEN OTHERS => rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0_q <= (others => '0');
END CASE;
END PROCESS;
-- rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selMSBs(BITSELECT,273)@0
rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selMSBs_in <= rightShiftStageSel2Dto0_uid228_alignmentShifter_uid64_fpAddTest_b;
rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selMSBs_b <= rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selMSBs_in(2 downto 2);
-- rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_mfinal(MUX,276)@0
rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_mfinal_s <= rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_selMSBs_b;
rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_mfinal: PROCESS (rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_mfinal_s, en, rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0_q, rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1_q)
BEGIN
CASE (rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_mfinal_s) IS
WHEN "0" => rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_mfinal_q <= rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_0_q;
WHEN "1" => rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_mfinal_q <= rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_msplit_1_q;
WHEN OTHERS => rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_mfinal_q <= (others => '0');
END CASE;
END PROCESS;
-- wIntCst_uid184_alignmentShifter_uid64_fpAddTest(CONSTANT,183)
wIntCst_uid184_alignmentShifter_uid64_fpAddTest_q <= "110001";
-- shiftedOut_uid185_alignmentShifter_uid64_fpAddTest(COMPARE,184)@0
shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_cin <= GND_q;
shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_a <= STD_LOGIC_VECTOR("00" & expAmExpB_uid60_fpAddTest_q) & '0';
shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_b <= STD_LOGIC_VECTOR("00000" & wIntCst_uid184_alignmentShifter_uid64_fpAddTest_q) & shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_cin(0);
shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_a) - UNSIGNED(shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_b));
shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_n(0) <= not (shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_o(11));
-- r_uid231_alignmentShifter_uid64_fpAddTest(MUX,230)@0
r_uid231_alignmentShifter_uid64_fpAddTest_s <= shiftedOut_uid185_alignmentShifter_uid64_fpAddTest_n;
r_uid231_alignmentShifter_uid64_fpAddTest: PROCESS (r_uid231_alignmentShifter_uid64_fpAddTest_s, en, rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_mfinal_q, rightShiftStage0Idx7_uid204_alignmentShifter_uid64_fpAddTest_q)
BEGIN
CASE (r_uid231_alignmentShifter_uid64_fpAddTest_s) IS
WHEN "0" => r_uid231_alignmentShifter_uid64_fpAddTest_q <= rightShiftStage1_uid229_alignmentShifter_uid64_fpAddTest_mfinal_q;
WHEN "1" => r_uid231_alignmentShifter_uid64_fpAddTest_q <= rightShiftStage0Idx7_uid204_alignmentShifter_uid64_fpAddTest_q;
WHEN OTHERS => r_uid231_alignmentShifter_uid64_fpAddTest_q <= (others => '0');
END CASE;
END PROCESS;
-- alignFracBPostShiftOut_uid68_fpAddTest(LOGICAL,67)@0
alignFracBPostShiftOut_uid68_fpAddTest_a <= r_uid231_alignmentShifter_uid64_fpAddTest_q;
alignFracBPostShiftOut_uid68_fpAddTest_b <= STD_LOGIC_VECTOR((48 downto 1 => iShiftedOut_uid67_fpAddTest_q(0)) & iShiftedOut_uid67_fpAddTest_q);
alignFracBPostShiftOut_uid68_fpAddTest_q <= alignFracBPostShiftOut_uid68_fpAddTest_a and alignFracBPostShiftOut_uid68_fpAddTest_b;
-- alignFracBOpRange_uid78_fpAddTest(BITSELECT,77)@0
alignFracBOpRange_uid78_fpAddTest_in <= alignFracBPostShiftOut_uid68_fpAddTest_q;
alignFracBOpRange_uid78_fpAddTest_b <= alignFracBOpRange_uid78_fpAddTest_in(48 downto 23);
-- fracBAddOp_uid80_fpAddTest(BITJOIN,79)@0
fracBAddOp_uid80_fpAddTest_q <= GND_q & alignFracBOpRange_uid78_fpAddTest_b;
-- fracBAddOpPostXor_uid81_fpAddTest(LOGICAL,80)@0
fracBAddOpPostXor_uid81_fpAddTest_a <= fracBAddOp_uid80_fpAddTest_q;
fracBAddOpPostXor_uid81_fpAddTest_b <= STD_LOGIC_VECTOR((26 downto 1 => effSub_uid52_fpAddTest_q(0)) & effSub_uid52_fpAddTest_q);
fracBAddOpPostXor_uid81_fpAddTest_q <= fracBAddOpPostXor_uid81_fpAddTest_a xor fracBAddOpPostXor_uid81_fpAddTest_b;
-- zocst_uid76_fpAddTest(CONSTANT,75)
zocst_uid76_fpAddTest_q <= "01";
-- frac_aSig_uid22_fpAddTest(BITSELECT,21)@0
frac_aSig_uid22_fpAddTest_in <= aSig_uid16_fpAddTest_q(22 downto 0);
frac_aSig_uid22_fpAddTest_b <= frac_aSig_uid22_fpAddTest_in(22 downto 0);
-- invSticky_uid73_fpAddTest(LOGICAL,72)@0
invSticky_uid73_fpAddTest_a <= invCmpEQ_stickyBits_cZwF_uid72_fpAddTest_q;
invSticky_uid73_fpAddTest_q <= not (invSticky_uid73_fpAddTest_a);
-- effSubInvSticky_uid74_fpAddTest(LOGICAL,73)@0
effSubInvSticky_uid74_fpAddTest_a <= effSub_uid52_fpAddTest_q;
effSubInvSticky_uid74_fpAddTest_b <= invSticky_uid73_fpAddTest_q;
effSubInvSticky_uid74_fpAddTest_q <= effSubInvSticky_uid74_fpAddTest_a and effSubInvSticky_uid74_fpAddTest_b;
-- fracAAddOp_uid77_fpAddTest(BITJOIN,76)@0
fracAAddOp_uid77_fpAddTest_q <= zocst_uid76_fpAddTest_q & frac_aSig_uid22_fpAddTest_b & GND_q & effSubInvSticky_uid74_fpAddTest_q;
-- fracAddResult_uid82_fpAddTest(ADD,81)@0
fracAddResult_uid82_fpAddTest_a <= STD_LOGIC_VECTOR("0" & fracAAddOp_uid77_fpAddTest_q);
fracAddResult_uid82_fpAddTest_b <= STD_LOGIC_VECTOR("0" & fracBAddOpPostXor_uid81_fpAddTest_q);
fracAddResult_uid82_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(fracAddResult_uid82_fpAddTest_a) + UNSIGNED(fracAddResult_uid82_fpAddTest_b));
fracAddResult_uid82_fpAddTest_q <= fracAddResult_uid82_fpAddTest_o(27 downto 0);
-- rangeFracAddResultMwfp3Dto0_uid83_fpAddTest(BITSELECT,82)@0
rangeFracAddResultMwfp3Dto0_uid83_fpAddTest_in <= fracAddResult_uid82_fpAddTest_q(26 downto 0);
rangeFracAddResultMwfp3Dto0_uid83_fpAddTest_b <= rangeFracAddResultMwfp3Dto0_uid83_fpAddTest_in(26 downto 0);
-- stickyBits_uid69_fpAddTest(BITSELECT,68)@0
stickyBits_uid69_fpAddTest_in <= alignFracBPostShiftOut_uid68_fpAddTest_q(22 downto 0);
stickyBits_uid69_fpAddTest_b <= stickyBits_uid69_fpAddTest_in(22 downto 0);
-- cmpEQ_stickyBits_cZwF_uid71_fpAddTest(LOGICAL,70)@0
cmpEQ_stickyBits_cZwF_uid71_fpAddTest_a <= stickyBits_uid69_fpAddTest_b;
cmpEQ_stickyBits_cZwF_uid71_fpAddTest_b <= cstZeroWF_uid19_fpAddTest_q;
cmpEQ_stickyBits_cZwF_uid71_fpAddTest_q <= "1" WHEN cmpEQ_stickyBits_cZwF_uid71_fpAddTest_a = cmpEQ_stickyBits_cZwF_uid71_fpAddTest_b ELSE "0";
-- invCmpEQ_stickyBits_cZwF_uid72_fpAddTest(LOGICAL,71)@0
invCmpEQ_stickyBits_cZwF_uid72_fpAddTest_a <= cmpEQ_stickyBits_cZwF_uid71_fpAddTest_q;
invCmpEQ_stickyBits_cZwF_uid72_fpAddTest_q <= not (invCmpEQ_stickyBits_cZwF_uid72_fpAddTest_a);
-- fracGRS_uid84_fpAddTest(BITJOIN,83)@0
fracGRS_uid84_fpAddTest_q <= rangeFracAddResultMwfp3Dto0_uid83_fpAddTest_b & invCmpEQ_stickyBits_cZwF_uid72_fpAddTest_q;
-- rVStage_uid152_lzCountVal_uid85_fpAddTest(BITSELECT,151)@0
rVStage_uid152_lzCountVal_uid85_fpAddTest_in <= fracGRS_uid84_fpAddTest_q;
rVStage_uid152_lzCountVal_uid85_fpAddTest_b <= rVStage_uid152_lzCountVal_uid85_fpAddTest_in(27 downto 12);
-- vCount_uid153_lzCountVal_uid85_fpAddTest(LOGICAL,152)@0
vCount_uid153_lzCountVal_uid85_fpAddTest_a <= rVStage_uid152_lzCountVal_uid85_fpAddTest_b;
vCount_uid153_lzCountVal_uid85_fpAddTest_b <= zs_uid151_lzCountVal_uid85_fpAddTest_q;
vCount_uid153_lzCountVal_uid85_fpAddTest_q <= "1" WHEN vCount_uid153_lzCountVal_uid85_fpAddTest_a = vCount_uid153_lzCountVal_uid85_fpAddTest_b ELSE "0";
-- redist3(DELAY,285)
redist3 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => vCount_uid153_lzCountVal_uid85_fpAddTest_q, xout => redist3_q, ena => en(0), clk => clk, aclr => areset );
-- vStage_uid155_lzCountVal_uid85_fpAddTest(BITSELECT,154)@0
vStage_uid155_lzCountVal_uid85_fpAddTest_in <= fracGRS_uid84_fpAddTest_q(11 downto 0);
vStage_uid155_lzCountVal_uid85_fpAddTest_b <= vStage_uid155_lzCountVal_uid85_fpAddTest_in(11 downto 0);
-- mO_uid154_lzCountVal_uid85_fpAddTest(CONSTANT,153)
mO_uid154_lzCountVal_uid85_fpAddTest_q <= "1111";
-- cStage_uid156_lzCountVal_uid85_fpAddTest(BITJOIN,155)@0
cStage_uid156_lzCountVal_uid85_fpAddTest_q <= vStage_uid155_lzCountVal_uid85_fpAddTest_b & mO_uid154_lzCountVal_uid85_fpAddTest_q;
-- vStagei_uid158_lzCountVal_uid85_fpAddTest(MUX,157)@0
vStagei_uid158_lzCountVal_uid85_fpAddTest_s <= vCount_uid153_lzCountVal_uid85_fpAddTest_q;
vStagei_uid158_lzCountVal_uid85_fpAddTest: PROCESS (vStagei_uid158_lzCountVal_uid85_fpAddTest_s, en, rVStage_uid152_lzCountVal_uid85_fpAddTest_b, cStage_uid156_lzCountVal_uid85_fpAddTest_q)
BEGIN
CASE (vStagei_uid158_lzCountVal_uid85_fpAddTest_s) IS
WHEN "0" => vStagei_uid158_lzCountVal_uid85_fpAddTest_q <= rVStage_uid152_lzCountVal_uid85_fpAddTest_b;
WHEN "1" => vStagei_uid158_lzCountVal_uid85_fpAddTest_q <= cStage_uid156_lzCountVal_uid85_fpAddTest_q;
WHEN OTHERS => vStagei_uid158_lzCountVal_uid85_fpAddTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid160_lzCountVal_uid85_fpAddTest(BITSELECT,159)@0
rVStage_uid160_lzCountVal_uid85_fpAddTest_in <= vStagei_uid158_lzCountVal_uid85_fpAddTest_q;
rVStage_uid160_lzCountVal_uid85_fpAddTest_b <= rVStage_uid160_lzCountVal_uid85_fpAddTest_in(15 downto 8);
-- redist1(DELAY,283)
redist1 : dspba_delay
GENERIC MAP ( width => 8, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => rVStage_uid160_lzCountVal_uid85_fpAddTest_b, xout => redist1_q, ena => en(0), clk => clk, aclr => areset );
-- vCount_uid161_lzCountVal_uid85_fpAddTest(LOGICAL,160)@1
vCount_uid161_lzCountVal_uid85_fpAddTest_a <= redist1_q;
vCount_uid161_lzCountVal_uid85_fpAddTest_b <= cstAllZWE_uid20_fpAddTest_q;
vCount_uid161_lzCountVal_uid85_fpAddTest_q <= "1" WHEN vCount_uid161_lzCountVal_uid85_fpAddTest_a = vCount_uid161_lzCountVal_uid85_fpAddTest_b ELSE "0";
-- vStage_uid162_lzCountVal_uid85_fpAddTest(BITSELECT,161)@0
vStage_uid162_lzCountVal_uid85_fpAddTest_in <= vStagei_uid158_lzCountVal_uid85_fpAddTest_q(7 downto 0);
vStage_uid162_lzCountVal_uid85_fpAddTest_b <= vStage_uid162_lzCountVal_uid85_fpAddTest_in(7 downto 0);
-- redist0(DELAY,282)
redist0 : dspba_delay
GENERIC MAP ( width => 8, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => vStage_uid162_lzCountVal_uid85_fpAddTest_b, xout => redist0_q, ena => en(0), clk => clk, aclr => areset );
-- vStagei_uid164_lzCountVal_uid85_fpAddTest(MUX,163)@1
vStagei_uid164_lzCountVal_uid85_fpAddTest_s <= vCount_uid161_lzCountVal_uid85_fpAddTest_q;
vStagei_uid164_lzCountVal_uid85_fpAddTest: PROCESS (vStagei_uid164_lzCountVal_uid85_fpAddTest_s, en, redist1_q, redist0_q)
BEGIN
CASE (vStagei_uid164_lzCountVal_uid85_fpAddTest_s) IS
WHEN "0" => vStagei_uid164_lzCountVal_uid85_fpAddTest_q <= redist1_q;
WHEN "1" => vStagei_uid164_lzCountVal_uid85_fpAddTest_q <= redist0_q;
WHEN OTHERS => vStagei_uid164_lzCountVal_uid85_fpAddTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid166_lzCountVal_uid85_fpAddTest(BITSELECT,165)@1
rVStage_uid166_lzCountVal_uid85_fpAddTest_in <= vStagei_uid164_lzCountVal_uid85_fpAddTest_q;
rVStage_uid166_lzCountVal_uid85_fpAddTest_b <= rVStage_uid166_lzCountVal_uid85_fpAddTest_in(7 downto 4);
-- vCount_uid167_lzCountVal_uid85_fpAddTest(LOGICAL,166)@1
vCount_uid167_lzCountVal_uid85_fpAddTest_a <= rVStage_uid166_lzCountVal_uid85_fpAddTest_b;
vCount_uid167_lzCountVal_uid85_fpAddTest_b <= zs_uid165_lzCountVal_uid85_fpAddTest_q;
vCount_uid167_lzCountVal_uid85_fpAddTest_q <= "1" WHEN vCount_uid167_lzCountVal_uid85_fpAddTest_a = vCount_uid167_lzCountVal_uid85_fpAddTest_b ELSE "0";
-- vStage_uid168_lzCountVal_uid85_fpAddTest(BITSELECT,167)@1
vStage_uid168_lzCountVal_uid85_fpAddTest_in <= vStagei_uid164_lzCountVal_uid85_fpAddTest_q(3 downto 0);
vStage_uid168_lzCountVal_uid85_fpAddTest_b <= vStage_uid168_lzCountVal_uid85_fpAddTest_in(3 downto 0);
-- vStagei_uid170_lzCountVal_uid85_fpAddTest(MUX,169)@1
vStagei_uid170_lzCountVal_uid85_fpAddTest_s <= vCount_uid167_lzCountVal_uid85_fpAddTest_q;
vStagei_uid170_lzCountVal_uid85_fpAddTest: PROCESS (vStagei_uid170_lzCountVal_uid85_fpAddTest_s, en, rVStage_uid166_lzCountVal_uid85_fpAddTest_b, vStage_uid168_lzCountVal_uid85_fpAddTest_b)
BEGIN
CASE (vStagei_uid170_lzCountVal_uid85_fpAddTest_s) IS
WHEN "0" => vStagei_uid170_lzCountVal_uid85_fpAddTest_q <= rVStage_uid166_lzCountVal_uid85_fpAddTest_b;
WHEN "1" => vStagei_uid170_lzCountVal_uid85_fpAddTest_q <= vStage_uid168_lzCountVal_uid85_fpAddTest_b;
WHEN OTHERS => vStagei_uid170_lzCountVal_uid85_fpAddTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid172_lzCountVal_uid85_fpAddTest(BITSELECT,171)@1
rVStage_uid172_lzCountVal_uid85_fpAddTest_in <= vStagei_uid170_lzCountVal_uid85_fpAddTest_q;
rVStage_uid172_lzCountVal_uid85_fpAddTest_b <= rVStage_uid172_lzCountVal_uid85_fpAddTest_in(3 downto 2);
-- vCount_uid173_lzCountVal_uid85_fpAddTest(LOGICAL,172)@1
vCount_uid173_lzCountVal_uid85_fpAddTest_a <= rVStage_uid172_lzCountVal_uid85_fpAddTest_b;
vCount_uid173_lzCountVal_uid85_fpAddTest_b <= zs_uid171_lzCountVal_uid85_fpAddTest_q;
vCount_uid173_lzCountVal_uid85_fpAddTest_q <= "1" WHEN vCount_uid173_lzCountVal_uid85_fpAddTest_a = vCount_uid173_lzCountVal_uid85_fpAddTest_b ELSE "0";
-- vStage_uid174_lzCountVal_uid85_fpAddTest(BITSELECT,173)@1
vStage_uid174_lzCountVal_uid85_fpAddTest_in <= vStagei_uid170_lzCountVal_uid85_fpAddTest_q(1 downto 0);
vStage_uid174_lzCountVal_uid85_fpAddTest_b <= vStage_uid174_lzCountVal_uid85_fpAddTest_in(1 downto 0);
-- vStagei_uid176_lzCountVal_uid85_fpAddTest(MUX,175)@1
vStagei_uid176_lzCountVal_uid85_fpAddTest_s <= vCount_uid173_lzCountVal_uid85_fpAddTest_q;
vStagei_uid176_lzCountVal_uid85_fpAddTest: PROCESS (vStagei_uid176_lzCountVal_uid85_fpAddTest_s, en, rVStage_uid172_lzCountVal_uid85_fpAddTest_b, vStage_uid174_lzCountVal_uid85_fpAddTest_b)
BEGIN
CASE (vStagei_uid176_lzCountVal_uid85_fpAddTest_s) IS
WHEN "0" => vStagei_uid176_lzCountVal_uid85_fpAddTest_q <= rVStage_uid172_lzCountVal_uid85_fpAddTest_b;
WHEN "1" => vStagei_uid176_lzCountVal_uid85_fpAddTest_q <= vStage_uid174_lzCountVal_uid85_fpAddTest_b;
WHEN OTHERS => vStagei_uid176_lzCountVal_uid85_fpAddTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid178_lzCountVal_uid85_fpAddTest(BITSELECT,177)@1
rVStage_uid178_lzCountVal_uid85_fpAddTest_in <= vStagei_uid176_lzCountVal_uid85_fpAddTest_q;
rVStage_uid178_lzCountVal_uid85_fpAddTest_b <= rVStage_uid178_lzCountVal_uid85_fpAddTest_in(1 downto 1);
-- vCount_uid179_lzCountVal_uid85_fpAddTest(LOGICAL,178)@1
vCount_uid179_lzCountVal_uid85_fpAddTest_a <= rVStage_uid178_lzCountVal_uid85_fpAddTest_b;
vCount_uid179_lzCountVal_uid85_fpAddTest_b <= GND_q;
vCount_uid179_lzCountVal_uid85_fpAddTest_q <= "1" WHEN vCount_uid179_lzCountVal_uid85_fpAddTest_a = vCount_uid179_lzCountVal_uid85_fpAddTest_b ELSE "0";
-- r_uid180_lzCountVal_uid85_fpAddTest(BITJOIN,179)@1
r_uid180_lzCountVal_uid85_fpAddTest_q <= redist3_q & vCount_uid161_lzCountVal_uid85_fpAddTest_q & vCount_uid167_lzCountVal_uid85_fpAddTest_q & vCount_uid173_lzCountVal_uid85_fpAddTest_q & vCount_uid179_lzCountVal_uid85_fpAddTest_q;
-- aMinusA_uid87_fpAddTest(LOGICAL,86)@1
aMinusA_uid87_fpAddTest_a <= r_uid180_lzCountVal_uid85_fpAddTest_q;
aMinusA_uid87_fpAddTest_b <= cAmA_uid86_fpAddTest_q;
aMinusA_uid87_fpAddTest_q <= "1" WHEN aMinusA_uid87_fpAddTest_a = aMinusA_uid87_fpAddTest_b ELSE "0";
-- invAMinusA_uid130_fpAddTest(LOGICAL,129)@1
invAMinusA_uid130_fpAddTest_a <= aMinusA_uid87_fpAddTest_q;
invAMinusA_uid130_fpAddTest_q <= not (invAMinusA_uid130_fpAddTest_a);
-- redist7(DELAY,289)
redist7 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => sigA_uid50_fpAddTest_b, xout => redist7_q, ena => en(0), clk => clk, aclr => areset );
-- cstAllOWE_uid18_fpAddTest(CONSTANT,17)
cstAllOWE_uid18_fpAddTest_q <= "11111111";
-- expXIsMax_uid38_fpAddTest(LOGICAL,37)@0
expXIsMax_uid38_fpAddTest_a <= exp_bSig_uid35_fpAddTest_b;
expXIsMax_uid38_fpAddTest_b <= cstAllOWE_uid18_fpAddTest_q;
expXIsMax_uid38_fpAddTest_q <= "1" WHEN expXIsMax_uid38_fpAddTest_a = expXIsMax_uid38_fpAddTest_b ELSE "0";
-- invExpXIsMax_uid43_fpAddTest(LOGICAL,42)@0
invExpXIsMax_uid43_fpAddTest_a <= expXIsMax_uid38_fpAddTest_q;
invExpXIsMax_uid43_fpAddTest_q <= not (invExpXIsMax_uid43_fpAddTest_a);
-- excR_bSig_uid45_fpAddTest(LOGICAL,44)@0
excR_bSig_uid45_fpAddTest_a <= InvExpXIsZero_uid44_fpAddTest_q;
excR_bSig_uid45_fpAddTest_b <= invExpXIsMax_uid43_fpAddTest_q;
excR_bSig_uid45_fpAddTest_q_i <= excR_bSig_uid45_fpAddTest_a and excR_bSig_uid45_fpAddTest_b;
excR_bSig_uid45_fpAddTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excR_bSig_uid45_fpAddTest_q_i, xout => excR_bSig_uid45_fpAddTest_q, ena => en(0), clk => clk, aclr => areset );
-- redist9(DELAY,291)
redist9 : dspba_delay
GENERIC MAP ( width => 8, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => exp_aSig_uid21_fpAddTest_b, xout => redist9_q, ena => en(0), clk => clk, aclr => areset );
-- expXIsMax_uid24_fpAddTest(LOGICAL,23)@1
expXIsMax_uid24_fpAddTest_a <= redist9_q;
expXIsMax_uid24_fpAddTest_b <= cstAllOWE_uid18_fpAddTest_q;
expXIsMax_uid24_fpAddTest_q <= "1" WHEN expXIsMax_uid24_fpAddTest_a = expXIsMax_uid24_fpAddTest_b ELSE "0";
-- invExpXIsMax_uid29_fpAddTest(LOGICAL,28)@1
invExpXIsMax_uid29_fpAddTest_a <= expXIsMax_uid24_fpAddTest_q;
invExpXIsMax_uid29_fpAddTest_q <= not (invExpXIsMax_uid29_fpAddTest_a);
-- excZ_aSig_uid16_uid23_fpAddTest(LOGICAL,22)@1
excZ_aSig_uid16_uid23_fpAddTest_a <= redist9_q;
excZ_aSig_uid16_uid23_fpAddTest_b <= cstAllZWE_uid20_fpAddTest_q;
excZ_aSig_uid16_uid23_fpAddTest_q <= "1" WHEN excZ_aSig_uid16_uid23_fpAddTest_a = excZ_aSig_uid16_uid23_fpAddTest_b ELSE "0";
-- InvExpXIsZero_uid30_fpAddTest(LOGICAL,29)@1
InvExpXIsZero_uid30_fpAddTest_a <= excZ_aSig_uid16_uid23_fpAddTest_q;
InvExpXIsZero_uid30_fpAddTest_q <= not (InvExpXIsZero_uid30_fpAddTest_a);
-- excR_aSig_uid31_fpAddTest(LOGICAL,30)@1
excR_aSig_uid31_fpAddTest_a <= InvExpXIsZero_uid30_fpAddTest_q;
excR_aSig_uid31_fpAddTest_b <= invExpXIsMax_uid29_fpAddTest_q;
excR_aSig_uid31_fpAddTest_q <= excR_aSig_uid31_fpAddTest_a and excR_aSig_uid31_fpAddTest_b;
-- signRReg_uid131_fpAddTest(LOGICAL,130)@1
signRReg_uid131_fpAddTest_a <= excR_aSig_uid31_fpAddTest_q;
signRReg_uid131_fpAddTest_b <= excR_bSig_uid45_fpAddTest_q;
signRReg_uid131_fpAddTest_c <= redist7_q;
signRReg_uid131_fpAddTest_d <= invAMinusA_uid130_fpAddTest_q;
signRReg_uid131_fpAddTest_q <= signRReg_uid131_fpAddTest_a and signRReg_uid131_fpAddTest_b and signRReg_uid131_fpAddTest_c and signRReg_uid131_fpAddTest_d;
-- redist6(DELAY,288)
redist6 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => sigB_uid51_fpAddTest_b, xout => redist6_q, ena => en(0), clk => clk, aclr => areset );
-- redist8(DELAY,290)
redist8 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_bSig_uid17_uid37_fpAddTest_q, xout => redist8_q, ena => en(0), clk => clk, aclr => areset );
-- excAZBZSigASigB_uid135_fpAddTest(LOGICAL,134)@1
excAZBZSigASigB_uid135_fpAddTest_a <= excZ_aSig_uid16_uid23_fpAddTest_q;
excAZBZSigASigB_uid135_fpAddTest_b <= redist8_q;
excAZBZSigASigB_uid135_fpAddTest_c <= redist7_q;
excAZBZSigASigB_uid135_fpAddTest_d <= redist6_q;
excAZBZSigASigB_uid135_fpAddTest_q <= excAZBZSigASigB_uid135_fpAddTest_a and excAZBZSigASigB_uid135_fpAddTest_b and excAZBZSigASigB_uid135_fpAddTest_c and excAZBZSigASigB_uid135_fpAddTest_d;
-- excBZARSigA_uid136_fpAddTest(LOGICAL,135)@1
excBZARSigA_uid136_fpAddTest_a <= redist8_q;
excBZARSigA_uid136_fpAddTest_b <= excR_aSig_uid31_fpAddTest_q;
excBZARSigA_uid136_fpAddTest_c <= redist7_q;
excBZARSigA_uid136_fpAddTest_q <= excBZARSigA_uid136_fpAddTest_a and excBZARSigA_uid136_fpAddTest_b and excBZARSigA_uid136_fpAddTest_c;
-- signRZero_uid137_fpAddTest(LOGICAL,136)@1
signRZero_uid137_fpAddTest_a <= excBZARSigA_uid136_fpAddTest_q;
signRZero_uid137_fpAddTest_b <= excAZBZSigASigB_uid135_fpAddTest_q;
signRZero_uid137_fpAddTest_q <= signRZero_uid137_fpAddTest_a or signRZero_uid137_fpAddTest_b;
-- fracXIsZero_uid39_fpAddTest(LOGICAL,38)@0
fracXIsZero_uid39_fpAddTest_a <= cstZeroWF_uid19_fpAddTest_q;
fracXIsZero_uid39_fpAddTest_b <= frac_bSig_uid36_fpAddTest_b;
fracXIsZero_uid39_fpAddTest_q <= "1" WHEN fracXIsZero_uid39_fpAddTest_a = fracXIsZero_uid39_fpAddTest_b ELSE "0";
-- excI_bSig_uid41_fpAddTest(LOGICAL,40)@0
excI_bSig_uid41_fpAddTest_a <= expXIsMax_uid38_fpAddTest_q;
excI_bSig_uid41_fpAddTest_b <= fracXIsZero_uid39_fpAddTest_q;
excI_bSig_uid41_fpAddTest_q_i <= excI_bSig_uid41_fpAddTest_a and excI_bSig_uid41_fpAddTest_b;
excI_bSig_uid41_fpAddTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excI_bSig_uid41_fpAddTest_q_i, xout => excI_bSig_uid41_fpAddTest_q, ena => en(0), clk => clk, aclr => areset );
-- sigBBInf_uid132_fpAddTest(LOGICAL,131)@1
sigBBInf_uid132_fpAddTest_a <= redist6_q;
sigBBInf_uid132_fpAddTest_b <= excI_bSig_uid41_fpAddTest_q;
sigBBInf_uid132_fpAddTest_q <= sigBBInf_uid132_fpAddTest_a and sigBBInf_uid132_fpAddTest_b;
-- fracXIsZero_uid25_fpAddTest(LOGICAL,24)@0
fracXIsZero_uid25_fpAddTest_a <= cstZeroWF_uid19_fpAddTest_q;
fracXIsZero_uid25_fpAddTest_b <= frac_aSig_uid22_fpAddTest_b;
fracXIsZero_uid25_fpAddTest_q_i <= "1" WHEN fracXIsZero_uid25_fpAddTest_a = fracXIsZero_uid25_fpAddTest_b ELSE "0";
fracXIsZero_uid25_fpAddTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid25_fpAddTest_q_i, xout => fracXIsZero_uid25_fpAddTest_q, ena => en(0), clk => clk, aclr => areset );
-- excI_aSig_uid27_fpAddTest(LOGICAL,26)@1
excI_aSig_uid27_fpAddTest_a <= expXIsMax_uid24_fpAddTest_q;
excI_aSig_uid27_fpAddTest_b <= fracXIsZero_uid25_fpAddTest_q;
excI_aSig_uid27_fpAddTest_q <= excI_aSig_uid27_fpAddTest_a and excI_aSig_uid27_fpAddTest_b;
-- sigAAInf_uid133_fpAddTest(LOGICAL,132)@1
sigAAInf_uid133_fpAddTest_a <= redist7_q;
sigAAInf_uid133_fpAddTest_b <= excI_aSig_uid27_fpAddTest_q;
sigAAInf_uid133_fpAddTest_q <= sigAAInf_uid133_fpAddTest_a and sigAAInf_uid133_fpAddTest_b;
-- signRInf_uid134_fpAddTest(LOGICAL,133)@1
signRInf_uid134_fpAddTest_a <= sigAAInf_uid133_fpAddTest_q;
signRInf_uid134_fpAddTest_b <= sigBBInf_uid132_fpAddTest_q;
signRInf_uid134_fpAddTest_q <= signRInf_uid134_fpAddTest_a or signRInf_uid134_fpAddTest_b;
-- signRInfRZRReg_uid138_fpAddTest(LOGICAL,137)@1
signRInfRZRReg_uid138_fpAddTest_a <= signRInf_uid134_fpAddTest_q;
signRInfRZRReg_uid138_fpAddTest_b <= signRZero_uid137_fpAddTest_q;
signRInfRZRReg_uid138_fpAddTest_c <= signRReg_uid131_fpAddTest_q;
signRInfRZRReg_uid138_fpAddTest_q <= signRInfRZRReg_uid138_fpAddTest_a or signRInfRZRReg_uid138_fpAddTest_b or signRInfRZRReg_uid138_fpAddTest_c;
-- fracXIsNotZero_uid40_fpAddTest(LOGICAL,39)@0
fracXIsNotZero_uid40_fpAddTest_a <= fracXIsZero_uid39_fpAddTest_q;
fracXIsNotZero_uid40_fpAddTest_q <= not (fracXIsNotZero_uid40_fpAddTest_a);
-- excN_bSig_uid42_fpAddTest(LOGICAL,41)@0
excN_bSig_uid42_fpAddTest_a <= expXIsMax_uid38_fpAddTest_q;
excN_bSig_uid42_fpAddTest_b <= fracXIsNotZero_uid40_fpAddTest_q;
excN_bSig_uid42_fpAddTest_q_i <= excN_bSig_uid42_fpAddTest_a and excN_bSig_uid42_fpAddTest_b;
excN_bSig_uid42_fpAddTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excN_bSig_uid42_fpAddTest_q_i, xout => excN_bSig_uid42_fpAddTest_q, ena => en(0), clk => clk, aclr => areset );
-- fracXIsNotZero_uid26_fpAddTest(LOGICAL,25)@1
fracXIsNotZero_uid26_fpAddTest_a <= fracXIsZero_uid25_fpAddTest_q;
fracXIsNotZero_uid26_fpAddTest_q <= not (fracXIsNotZero_uid26_fpAddTest_a);
-- excN_aSig_uid28_fpAddTest(LOGICAL,27)@1
excN_aSig_uid28_fpAddTest_a <= expXIsMax_uid24_fpAddTest_q;
excN_aSig_uid28_fpAddTest_b <= fracXIsNotZero_uid26_fpAddTest_q;
excN_aSig_uid28_fpAddTest_q <= excN_aSig_uid28_fpAddTest_a and excN_aSig_uid28_fpAddTest_b;
-- excRNaN2_uid125_fpAddTest(LOGICAL,124)@1
excRNaN2_uid125_fpAddTest_a <= excN_aSig_uid28_fpAddTest_q;
excRNaN2_uid125_fpAddTest_b <= excN_bSig_uid42_fpAddTest_q;
excRNaN2_uid125_fpAddTest_q <= excRNaN2_uid125_fpAddTest_a or excRNaN2_uid125_fpAddTest_b;
-- redist5(DELAY,287)
redist5 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => effSub_uid52_fpAddTest_q, xout => redist5_q, ena => en(0), clk => clk, aclr => areset );
-- excAIBISub_uid126_fpAddTest(LOGICAL,125)@1
excAIBISub_uid126_fpAddTest_a <= excI_aSig_uid27_fpAddTest_q;
excAIBISub_uid126_fpAddTest_b <= excI_bSig_uid41_fpAddTest_q;
excAIBISub_uid126_fpAddTest_c <= redist5_q;
excAIBISub_uid126_fpAddTest_q <= excAIBISub_uid126_fpAddTest_a and excAIBISub_uid126_fpAddTest_b and excAIBISub_uid126_fpAddTest_c;
-- excRNaN_uid127_fpAddTest(LOGICAL,126)@1
excRNaN_uid127_fpAddTest_a <= excAIBISub_uid126_fpAddTest_q;
excRNaN_uid127_fpAddTest_b <= excRNaN2_uid125_fpAddTest_q;
excRNaN_uid127_fpAddTest_q <= excRNaN_uid127_fpAddTest_a or excRNaN_uid127_fpAddTest_b;
-- invExcRNaN_uid139_fpAddTest(LOGICAL,138)@1
invExcRNaN_uid139_fpAddTest_a <= excRNaN_uid127_fpAddTest_q;
invExcRNaN_uid139_fpAddTest_q <= not (invExcRNaN_uid139_fpAddTest_a);
-- xIn(GPIN,3)@0
-- signRPostExc_uid140_fpAddTest(LOGICAL,139)@1
signRPostExc_uid140_fpAddTest_a <= invExcRNaN_uid139_fpAddTest_q;
signRPostExc_uid140_fpAddTest_b <= signRInfRZRReg_uid138_fpAddTest_q;
signRPostExc_uid140_fpAddTest_q <= signRPostExc_uid140_fpAddTest_a and signRPostExc_uid140_fpAddTest_b;
-- cRBit_uid99_fpAddTest(CONSTANT,98)
cRBit_uid99_fpAddTest_q <= "01000";
-- leftShiftStage1Idx3Rng3_uid263_fracPostNormExt_uid88_fpAddTest(BITSELECT,262)@1
leftShiftStage1Idx3Rng3_uid263_fracPostNormExt_uid88_fpAddTest_in <= leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal_q(24 downto 0);
leftShiftStage1Idx3Rng3_uid263_fracPostNormExt_uid88_fpAddTest_b <= leftShiftStage1Idx3Rng3_uid263_fracPostNormExt_uid88_fpAddTest_in(24 downto 0);
-- leftShiftStage1Idx3_uid264_fracPostNormExt_uid88_fpAddTest(BITJOIN,263)@1
leftShiftStage1Idx3_uid264_fracPostNormExt_uid88_fpAddTest_q <= leftShiftStage1Idx3Rng3_uid263_fracPostNormExt_uid88_fpAddTest_b & rightShiftStage1Idx3Pad3_uid214_alignmentShifter_uid64_fpAddTest_q;
-- leftShiftStage1Idx2Rng2_uid260_fracPostNormExt_uid88_fpAddTest(BITSELECT,259)@1
leftShiftStage1Idx2Rng2_uid260_fracPostNormExt_uid88_fpAddTest_in <= leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal_q(25 downto 0);
leftShiftStage1Idx2Rng2_uid260_fracPostNormExt_uid88_fpAddTest_b <= leftShiftStage1Idx2Rng2_uid260_fracPostNormExt_uid88_fpAddTest_in(25 downto 0);
-- leftShiftStage1Idx2_uid261_fracPostNormExt_uid88_fpAddTest(BITJOIN,260)@1
leftShiftStage1Idx2_uid261_fracPostNormExt_uid88_fpAddTest_q <= leftShiftStage1Idx2Rng2_uid260_fracPostNormExt_uid88_fpAddTest_b & zs_uid171_lzCountVal_uid85_fpAddTest_q;
-- leftShiftStage1Idx1Rng1_uid257_fracPostNormExt_uid88_fpAddTest(BITSELECT,256)@1
leftShiftStage1Idx1Rng1_uid257_fracPostNormExt_uid88_fpAddTest_in <= leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal_q(26 downto 0);
leftShiftStage1Idx1Rng1_uid257_fracPostNormExt_uid88_fpAddTest_b <= leftShiftStage1Idx1Rng1_uid257_fracPostNormExt_uid88_fpAddTest_in(26 downto 0);
-- leftShiftStage1Idx1_uid258_fracPostNormExt_uid88_fpAddTest(BITJOIN,257)@1
leftShiftStage1Idx1_uid258_fracPostNormExt_uid88_fpAddTest_q <= leftShiftStage1Idx1Rng1_uid257_fracPostNormExt_uid88_fpAddTest_b & GND_q;
-- leftShiftStage0Idx7_uid253_fracPostNormExt_uid88_fpAddTest(CONSTANT,252)
leftShiftStage0Idx7_uid253_fracPostNormExt_uid88_fpAddTest_q <= "0000000000000000000000000000";
-- redist4(DELAY,286)
redist4 : dspba_delay
GENERIC MAP ( width => 28, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracGRS_uid84_fpAddTest_q, xout => redist4_q, ena => en(0), clk => clk, aclr => areset );
-- leftShiftStage0Idx6Rng24_uid251_fracPostNormExt_uid88_fpAddTest(BITSELECT,250)@1
leftShiftStage0Idx6Rng24_uid251_fracPostNormExt_uid88_fpAddTest_in <= redist4_q(3 downto 0);
leftShiftStage0Idx6Rng24_uid251_fracPostNormExt_uid88_fpAddTest_b <= leftShiftStage0Idx6Rng24_uid251_fracPostNormExt_uid88_fpAddTest_in(3 downto 0);
-- leftShiftStage0Idx6_uid252_fracPostNormExt_uid88_fpAddTest(BITJOIN,251)@1
leftShiftStage0Idx6_uid252_fracPostNormExt_uid88_fpAddTest_q <= leftShiftStage0Idx6Rng24_uid251_fracPostNormExt_uid88_fpAddTest_b & rightShiftStage0Idx3Pad24_uid193_alignmentShifter_uid64_fpAddTest_q;
-- leftShiftStage0Idx5Rng20_uid248_fracPostNormExt_uid88_fpAddTest(BITSELECT,247)@1
leftShiftStage0Idx5Rng20_uid248_fracPostNormExt_uid88_fpAddTest_in <= redist4_q(7 downto 0);
leftShiftStage0Idx5Rng20_uid248_fracPostNormExt_uid88_fpAddTest_b <= leftShiftStage0Idx5Rng20_uid248_fracPostNormExt_uid88_fpAddTest_in(7 downto 0);
-- leftShiftStage0Idx5Pad20_uid247_fracPostNormExt_uid88_fpAddTest(CONSTANT,246)
leftShiftStage0Idx5Pad20_uid247_fracPostNormExt_uid88_fpAddTest_q <= "00000000000000000000";
-- leftShiftStage0Idx5_uid249_fracPostNormExt_uid88_fpAddTest(BITJOIN,248)@1
leftShiftStage0Idx5_uid249_fracPostNormExt_uid88_fpAddTest_q <= leftShiftStage0Idx5Rng20_uid248_fracPostNormExt_uid88_fpAddTest_b & leftShiftStage0Idx5Pad20_uid247_fracPostNormExt_uid88_fpAddTest_q;
-- redist2(DELAY,284)
redist2 : dspba_delay
GENERIC MAP ( width => 12, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => vStage_uid155_lzCountVal_uid85_fpAddTest_b, xout => redist2_q, ena => en(0), clk => clk, aclr => areset );
-- leftShiftStage0Idx4_uid246_fracPostNormExt_uid88_fpAddTest(BITJOIN,245)@1
leftShiftStage0Idx4_uid246_fracPostNormExt_uid88_fpAddTest_q <= redist2_q & zs_uid151_lzCountVal_uid85_fpAddTest_q;
-- leftShiftStageSel4Dto2_uid254_fracPostNormExt_uid88_fpAddTest(BITSELECT,253)@1
leftShiftStageSel4Dto2_uid254_fracPostNormExt_uid88_fpAddTest_in <= r_uid180_lzCountVal_uid85_fpAddTest_q;
leftShiftStageSel4Dto2_uid254_fracPostNormExt_uid88_fpAddTest_b <= leftShiftStageSel4Dto2_uid254_fracPostNormExt_uid88_fpAddTest_in(4 downto 2);
-- leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selLSBs(BITSELECT,277)@1
leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selLSBs_in <= leftShiftStageSel4Dto2_uid254_fracPostNormExt_uid88_fpAddTest_b(1 downto 0);
leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selLSBs_b <= leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selLSBs_in(1 downto 0);
-- leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1(MUX,280)@1
leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1_s <= leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selLSBs_b;
leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1: PROCESS (leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1_s, en, leftShiftStage0Idx4_uid246_fracPostNormExt_uid88_fpAddTest_q, leftShiftStage0Idx5_uid249_fracPostNormExt_uid88_fpAddTest_q, leftShiftStage0Idx6_uid252_fracPostNormExt_uid88_fpAddTest_q, leftShiftStage0Idx7_uid253_fracPostNormExt_uid88_fpAddTest_q)
BEGIN
CASE (leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1_s) IS
WHEN "00" => leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1_q <= leftShiftStage0Idx4_uid246_fracPostNormExt_uid88_fpAddTest_q;
WHEN "01" => leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1_q <= leftShiftStage0Idx5_uid249_fracPostNormExt_uid88_fpAddTest_q;
WHEN "10" => leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1_q <= leftShiftStage0Idx6_uid252_fracPostNormExt_uid88_fpAddTest_q;
WHEN "11" => leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1_q <= leftShiftStage0Idx7_uid253_fracPostNormExt_uid88_fpAddTest_q;
WHEN OTHERS => leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStage0Idx3Rng12_uid242_fracPostNormExt_uid88_fpAddTest(BITSELECT,241)@1
leftShiftStage0Idx3Rng12_uid242_fracPostNormExt_uid88_fpAddTest_in <= redist4_q(15 downto 0);
leftShiftStage0Idx3Rng12_uid242_fracPostNormExt_uid88_fpAddTest_b <= leftShiftStage0Idx3Rng12_uid242_fracPostNormExt_uid88_fpAddTest_in(15 downto 0);
-- leftShiftStage0Idx3Pad12_uid241_fracPostNormExt_uid88_fpAddTest(CONSTANT,240)
leftShiftStage0Idx3Pad12_uid241_fracPostNormExt_uid88_fpAddTest_q <= "000000000000";
-- leftShiftStage0Idx3_uid243_fracPostNormExt_uid88_fpAddTest(BITJOIN,242)@1
leftShiftStage0Idx3_uid243_fracPostNormExt_uid88_fpAddTest_q <= leftShiftStage0Idx3Rng12_uid242_fracPostNormExt_uid88_fpAddTest_b & leftShiftStage0Idx3Pad12_uid241_fracPostNormExt_uid88_fpAddTest_q;
-- leftShiftStage0Idx2Rng8_uid239_fracPostNormExt_uid88_fpAddTest(BITSELECT,238)@1
leftShiftStage0Idx2Rng8_uid239_fracPostNormExt_uid88_fpAddTest_in <= redist4_q(19 downto 0);
leftShiftStage0Idx2Rng8_uid239_fracPostNormExt_uid88_fpAddTest_b <= leftShiftStage0Idx2Rng8_uid239_fracPostNormExt_uid88_fpAddTest_in(19 downto 0);
-- leftShiftStage0Idx2_uid240_fracPostNormExt_uid88_fpAddTest(BITJOIN,239)@1
leftShiftStage0Idx2_uid240_fracPostNormExt_uid88_fpAddTest_q <= leftShiftStage0Idx2Rng8_uid239_fracPostNormExt_uid88_fpAddTest_b & cstAllZWE_uid20_fpAddTest_q;
-- leftShiftStage0Idx1Rng4_uid236_fracPostNormExt_uid88_fpAddTest(BITSELECT,235)@1
leftShiftStage0Idx1Rng4_uid236_fracPostNormExt_uid88_fpAddTest_in <= redist4_q(23 downto 0);
leftShiftStage0Idx1Rng4_uid236_fracPostNormExt_uid88_fpAddTest_b <= leftShiftStage0Idx1Rng4_uid236_fracPostNormExt_uid88_fpAddTest_in(23 downto 0);
-- leftShiftStage0Idx1_uid237_fracPostNormExt_uid88_fpAddTest(BITJOIN,236)@1
leftShiftStage0Idx1_uid237_fracPostNormExt_uid88_fpAddTest_q <= leftShiftStage0Idx1Rng4_uid236_fracPostNormExt_uid88_fpAddTest_b & zs_uid165_lzCountVal_uid85_fpAddTest_q;
-- leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0(MUX,279)@1
leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0_s <= leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selLSBs_b;
leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0: PROCESS (leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0_s, en, redist4_q, leftShiftStage0Idx1_uid237_fracPostNormExt_uid88_fpAddTest_q, leftShiftStage0Idx2_uid240_fracPostNormExt_uid88_fpAddTest_q, leftShiftStage0Idx3_uid243_fracPostNormExt_uid88_fpAddTest_q)
BEGIN
CASE (leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0_s) IS
WHEN "00" => leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0_q <= redist4_q;
WHEN "01" => leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0_q <= leftShiftStage0Idx1_uid237_fracPostNormExt_uid88_fpAddTest_q;
WHEN "10" => leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0_q <= leftShiftStage0Idx2_uid240_fracPostNormExt_uid88_fpAddTest_q;
WHEN "11" => leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0_q <= leftShiftStage0Idx3_uid243_fracPostNormExt_uid88_fpAddTest_q;
WHEN OTHERS => leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selMSBs(BITSELECT,278)@1
leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selMSBs_in <= leftShiftStageSel4Dto2_uid254_fracPostNormExt_uid88_fpAddTest_b;
leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selMSBs_b <= leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selMSBs_in(2 downto 2);
-- leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal(MUX,281)@1
leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal_s <= leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_selMSBs_b;
leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal: PROCESS (leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal_s, en, leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0_q, leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1_q)
BEGIN
CASE (leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal_s) IS
WHEN "0" => leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal_q <= leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_0_q;
WHEN "1" => leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal_q <= leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_msplit_1_q;
WHEN OTHERS => leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStageSel1Dto0_uid265_fracPostNormExt_uid88_fpAddTest(BITSELECT,264)@1
leftShiftStageSel1Dto0_uid265_fracPostNormExt_uid88_fpAddTest_in <= r_uid180_lzCountVal_uid85_fpAddTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid265_fracPostNormExt_uid88_fpAddTest_b <= leftShiftStageSel1Dto0_uid265_fracPostNormExt_uid88_fpAddTest_in(1 downto 0);
-- leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest(MUX,265)@1
leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_s <= leftShiftStageSel1Dto0_uid265_fracPostNormExt_uid88_fpAddTest_b;
leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest: PROCESS (leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_s, en, leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal_q, leftShiftStage1Idx1_uid258_fracPostNormExt_uid88_fpAddTest_q, leftShiftStage1Idx2_uid261_fracPostNormExt_uid88_fpAddTest_q, leftShiftStage1Idx3_uid264_fracPostNormExt_uid88_fpAddTest_q)
BEGIN
CASE (leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_s) IS
WHEN "00" => leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_q <= leftShiftStage0_uid255_fracPostNormExt_uid88_fpAddTest_mfinal_q;
WHEN "01" => leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_q <= leftShiftStage1Idx1_uid258_fracPostNormExt_uid88_fpAddTest_q;
WHEN "10" => leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_q <= leftShiftStage1Idx2_uid261_fracPostNormExt_uid88_fpAddTest_q;
WHEN "11" => leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_q <= leftShiftStage1Idx3_uid264_fracPostNormExt_uid88_fpAddTest_q;
WHEN OTHERS => leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_q <= (others => '0');
END CASE;
END PROCESS;
-- LSB_uid97_fpAddTest(BITSELECT,96)@1
LSB_uid97_fpAddTest_in <= STD_LOGIC_VECTOR(leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_q(4 downto 0));
LSB_uid97_fpAddTest_b <= LSB_uid97_fpAddTest_in(4 downto 4);
-- Guard_uid96_fpAddTest(BITSELECT,95)@1
Guard_uid96_fpAddTest_in <= STD_LOGIC_VECTOR(leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_q(3 downto 0));
Guard_uid96_fpAddTest_b <= Guard_uid96_fpAddTest_in(3 downto 3);
-- Round_uid95_fpAddTest(BITSELECT,94)@1
Round_uid95_fpAddTest_in <= STD_LOGIC_VECTOR(leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_q(2 downto 0));
Round_uid95_fpAddTest_b <= Round_uid95_fpAddTest_in(2 downto 2);
-- Sticky1_uid94_fpAddTest(BITSELECT,93)@1
Sticky1_uid94_fpAddTest_in <= STD_LOGIC_VECTOR(leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_q(1 downto 0));
Sticky1_uid94_fpAddTest_b <= Sticky1_uid94_fpAddTest_in(1 downto 1);
-- Sticky0_uid93_fpAddTest(BITSELECT,92)@1
Sticky0_uid93_fpAddTest_in <= STD_LOGIC_VECTOR(leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_q(0 downto 0));
Sticky0_uid93_fpAddTest_b <= Sticky0_uid93_fpAddTest_in(0 downto 0);
-- rndBitCond_uid98_fpAddTest(BITJOIN,97)@1
rndBitCond_uid98_fpAddTest_q <= LSB_uid97_fpAddTest_b & Guard_uid96_fpAddTest_b & Round_uid95_fpAddTest_b & Sticky1_uid94_fpAddTest_b & Sticky0_uid93_fpAddTest_b;
-- rBi_uid100_fpAddTest(LOGICAL,99)@1
rBi_uid100_fpAddTest_a <= rndBitCond_uid98_fpAddTest_q;
rBi_uid100_fpAddTest_b <= cRBit_uid99_fpAddTest_q;
rBi_uid100_fpAddTest_q <= "1" WHEN rBi_uid100_fpAddTest_a = rBi_uid100_fpAddTest_b ELSE "0";
-- roundBit_uid101_fpAddTest(LOGICAL,100)@1
roundBit_uid101_fpAddTest_a <= rBi_uid100_fpAddTest_q;
roundBit_uid101_fpAddTest_q <= not (roundBit_uid101_fpAddTest_a);
-- oneCST_uid90_fpAddTest(CONSTANT,89)
oneCST_uid90_fpAddTest_q <= "00000001";
-- expInc_uid91_fpAddTest(ADD,90)@1
expInc_uid91_fpAddTest_a <= STD_LOGIC_VECTOR("0" & redist9_q);
expInc_uid91_fpAddTest_b <= STD_LOGIC_VECTOR("0" & oneCST_uid90_fpAddTest_q);
expInc_uid91_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expInc_uid91_fpAddTest_a) + UNSIGNED(expInc_uid91_fpAddTest_b));
expInc_uid91_fpAddTest_q <= expInc_uid91_fpAddTest_o(8 downto 0);
-- expPostNorm_uid92_fpAddTest(SUB,91)@1
expPostNorm_uid92_fpAddTest_a <= STD_LOGIC_VECTOR("0" & expInc_uid91_fpAddTest_q);
expPostNorm_uid92_fpAddTest_b <= STD_LOGIC_VECTOR("00000" & r_uid180_lzCountVal_uid85_fpAddTest_q);
expPostNorm_uid92_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expPostNorm_uid92_fpAddTest_a) - UNSIGNED(expPostNorm_uid92_fpAddTest_b));
expPostNorm_uid92_fpAddTest_q <= expPostNorm_uid92_fpAddTest_o(9 downto 0);
-- fracPostNorm_uid89_fpAddTest(BITSELECT,88)@1
fracPostNorm_uid89_fpAddTest_in <= leftShiftStage1_uid266_fracPostNormExt_uid88_fpAddTest_q;
fracPostNorm_uid89_fpAddTest_b <= fracPostNorm_uid89_fpAddTest_in(27 downto 1);
-- fracPostNormRndRange_uid102_fpAddTest(BITSELECT,101)@1
fracPostNormRndRange_uid102_fpAddTest_in <= fracPostNorm_uid89_fpAddTest_b(25 downto 0);
fracPostNormRndRange_uid102_fpAddTest_b <= fracPostNormRndRange_uid102_fpAddTest_in(25 downto 2);
-- expFracR_uid103_fpAddTest(BITJOIN,102)@1
expFracR_uid103_fpAddTest_q <= expPostNorm_uid92_fpAddTest_q & fracPostNormRndRange_uid102_fpAddTest_b;
-- rndExpFrac_uid104_fpAddTest(ADD,103)@1
rndExpFrac_uid104_fpAddTest_a <= STD_LOGIC_VECTOR("0" & expFracR_uid103_fpAddTest_q);
rndExpFrac_uid104_fpAddTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000" & roundBit_uid101_fpAddTest_q);
rndExpFrac_uid104_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(rndExpFrac_uid104_fpAddTest_a) + UNSIGNED(rndExpFrac_uid104_fpAddTest_b));
rndExpFrac_uid104_fpAddTest_q <= rndExpFrac_uid104_fpAddTest_o(34 downto 0);
-- expRPreExc_uid118_fpAddTest(BITSELECT,117)@1
expRPreExc_uid118_fpAddTest_in <= rndExpFrac_uid104_fpAddTest_q(31 downto 0);
expRPreExc_uid118_fpAddTest_b <= expRPreExc_uid118_fpAddTest_in(31 downto 24);
-- rndExpFracOvfBits_uid109_fpAddTest(BITSELECT,108)@1
rndExpFracOvfBits_uid109_fpAddTest_in <= rndExpFrac_uid104_fpAddTest_q(33 downto 0);
rndExpFracOvfBits_uid109_fpAddTest_b <= rndExpFracOvfBits_uid109_fpAddTest_in(33 downto 32);
-- rOvfExtraBits_uid110_fpAddTest(COMPARE,109)@1
rOvfExtraBits_uid110_fpAddTest_cin <= GND_q;
rOvfExtraBits_uid110_fpAddTest_a <= STD_LOGIC_VECTOR("00" & rndExpFracOvfBits_uid109_fpAddTest_b) & '0';
rOvfExtraBits_uid110_fpAddTest_b <= STD_LOGIC_VECTOR("00" & zocst_uid76_fpAddTest_q) & rOvfExtraBits_uid110_fpAddTest_cin(0);
rOvfExtraBits_uid110_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(rOvfExtraBits_uid110_fpAddTest_a) - UNSIGNED(rOvfExtraBits_uid110_fpAddTest_b));
rOvfExtraBits_uid110_fpAddTest_n(0) <= not (rOvfExtraBits_uid110_fpAddTest_o(4));
-- wEP2AllOwE_uid105_fpAddTest(CONSTANT,104)
wEP2AllOwE_uid105_fpAddTest_q <= "0011111111";
-- rndExp_uid106_fpAddTest(BITSELECT,105)@1
rndExp_uid106_fpAddTest_in <= rndExpFrac_uid104_fpAddTest_q(33 downto 0);
rndExp_uid106_fpAddTest_b <= rndExp_uid106_fpAddTest_in(33 downto 24);
-- rOvfEQMax_uid107_fpAddTest(LOGICAL,106)@1
rOvfEQMax_uid107_fpAddTest_a <= rndExp_uid106_fpAddTest_b;
rOvfEQMax_uid107_fpAddTest_b <= wEP2AllOwE_uid105_fpAddTest_q;
rOvfEQMax_uid107_fpAddTest_q <= "1" WHEN rOvfEQMax_uid107_fpAddTest_a = rOvfEQMax_uid107_fpAddTest_b ELSE "0";
-- rOvf_uid111_fpAddTest(LOGICAL,110)@1
rOvf_uid111_fpAddTest_a <= rOvfEQMax_uid107_fpAddTest_q;
rOvf_uid111_fpAddTest_b <= rOvfExtraBits_uid110_fpAddTest_n;
rOvf_uid111_fpAddTest_q <= rOvf_uid111_fpAddTest_a or rOvf_uid111_fpAddTest_b;
-- regInputs_uid119_fpAddTest(LOGICAL,118)@1
regInputs_uid119_fpAddTest_a <= excR_aSig_uid31_fpAddTest_q;
regInputs_uid119_fpAddTest_b <= excR_bSig_uid45_fpAddTest_q;
regInputs_uid119_fpAddTest_q <= regInputs_uid119_fpAddTest_a and regInputs_uid119_fpAddTest_b;
-- rInfOvf_uid122_fpAddTest(LOGICAL,121)@1
rInfOvf_uid122_fpAddTest_a <= regInputs_uid119_fpAddTest_q;
rInfOvf_uid122_fpAddTest_b <= rOvf_uid111_fpAddTest_q;
rInfOvf_uid122_fpAddTest_q <= rInfOvf_uid122_fpAddTest_a and rInfOvf_uid122_fpAddTest_b;
-- excRInfVInC_uid123_fpAddTest(BITJOIN,122)@1
excRInfVInC_uid123_fpAddTest_q <= rInfOvf_uid122_fpAddTest_q & excN_bSig_uid42_fpAddTest_q & excN_aSig_uid28_fpAddTest_q & excI_bSig_uid41_fpAddTest_q & excI_aSig_uid27_fpAddTest_q & redist5_q;
-- excRInf_uid124_fpAddTest(LOOKUP,123)@1
excRInf_uid124_fpAddTest: PROCESS (excRInfVInC_uid123_fpAddTest_q)
BEGIN
-- Begin reserved scope level
CASE (excRInfVInC_uid123_fpAddTest_q) IS
WHEN "000000" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "000001" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "000010" => excRInf_uid124_fpAddTest_q <= "1";
WHEN "000011" => excRInf_uid124_fpAddTest_q <= "1";
WHEN "000100" => excRInf_uid124_fpAddTest_q <= "1";
WHEN "000101" => excRInf_uid124_fpAddTest_q <= "1";
WHEN "000110" => excRInf_uid124_fpAddTest_q <= "1";
WHEN "000111" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "001000" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "001001" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "001010" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "001011" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "001100" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "001101" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "001110" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "001111" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "010000" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "010001" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "010010" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "010011" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "010100" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "010101" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "010110" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "010111" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "011000" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "011001" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "011010" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "011011" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "011100" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "011101" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "011110" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "011111" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "100000" => excRInf_uid124_fpAddTest_q <= "1";
WHEN "100001" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "100010" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "100011" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "100100" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "100101" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "100110" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "100111" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "101000" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "101001" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "101010" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "101011" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "101100" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "101101" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "101110" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "101111" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "110000" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "110001" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "110010" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "110011" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "110100" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "110101" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "110110" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "110111" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "111000" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "111001" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "111010" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "111011" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "111100" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "111101" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "111110" => excRInf_uid124_fpAddTest_q <= "0";
WHEN "111111" => excRInf_uid124_fpAddTest_q <= "0";
WHEN OTHERS => -- unreachable
excRInf_uid124_fpAddTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- rUdfExtraBit_uid115_fpAddTest(BITSELECT,114)@1
rUdfExtraBit_uid115_fpAddTest_in <= STD_LOGIC_VECTOR(rndExpFrac_uid104_fpAddTest_q(33 downto 0));
rUdfExtraBit_uid115_fpAddTest_b <= rUdfExtraBit_uid115_fpAddTest_in(33 downto 33);
-- wEP2AllZ_uid112_fpAddTest(CONSTANT,111)
wEP2AllZ_uid112_fpAddTest_q <= "0000000000";
-- rUdfEQMin_uid114_fpAddTest(LOGICAL,113)@1
rUdfEQMin_uid114_fpAddTest_a <= rndExp_uid106_fpAddTest_b;
rUdfEQMin_uid114_fpAddTest_b <= wEP2AllZ_uid112_fpAddTest_q;
rUdfEQMin_uid114_fpAddTest_q <= "1" WHEN rUdfEQMin_uid114_fpAddTest_a = rUdfEQMin_uid114_fpAddTest_b ELSE "0";
-- rUdf_uid116_fpAddTest(LOGICAL,115)@1
rUdf_uid116_fpAddTest_a <= rUdfEQMin_uid114_fpAddTest_q;
rUdf_uid116_fpAddTest_b <= rUdfExtraBit_uid115_fpAddTest_b;
rUdf_uid116_fpAddTest_q <= rUdf_uid116_fpAddTest_a or rUdf_uid116_fpAddTest_b;
-- excRZeroVInC_uid120_fpAddTest(BITJOIN,119)@1
excRZeroVInC_uid120_fpAddTest_q <= aMinusA_uid87_fpAddTest_q & rUdf_uid116_fpAddTest_q & regInputs_uid119_fpAddTest_q & redist8_q & excZ_aSig_uid16_uid23_fpAddTest_q;
-- excRZero_uid121_fpAddTest(LOOKUP,120)@1
excRZero_uid121_fpAddTest: PROCESS (excRZeroVInC_uid120_fpAddTest_q)
BEGIN
-- Begin reserved scope level
CASE (excRZeroVInC_uid120_fpAddTest_q) IS
WHEN "00000" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "00001" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "00010" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "00011" => excRZero_uid121_fpAddTest_q <= "1";
WHEN "00100" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "00101" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "00110" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "00111" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "01000" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "01001" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "01010" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "01011" => excRZero_uid121_fpAddTest_q <= "1";
WHEN "01100" => excRZero_uid121_fpAddTest_q <= "1";
WHEN "01101" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "01110" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "01111" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "10000" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "10001" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "10010" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "10011" => excRZero_uid121_fpAddTest_q <= "1";
WHEN "10100" => excRZero_uid121_fpAddTest_q <= "1";
WHEN "10101" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "10110" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "10111" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "11000" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "11001" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "11010" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "11011" => excRZero_uid121_fpAddTest_q <= "1";
WHEN "11100" => excRZero_uid121_fpAddTest_q <= "1";
WHEN "11101" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "11110" => excRZero_uid121_fpAddTest_q <= "0";
WHEN "11111" => excRZero_uid121_fpAddTest_q <= "0";
WHEN OTHERS => -- unreachable
excRZero_uid121_fpAddTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- concExc_uid128_fpAddTest(BITJOIN,127)@1
concExc_uid128_fpAddTest_q <= excRNaN_uid127_fpAddTest_q & excRInf_uid124_fpAddTest_q & excRZero_uid121_fpAddTest_q;
-- excREnc_uid129_fpAddTest(LOOKUP,128)@1
excREnc_uid129_fpAddTest: PROCESS (concExc_uid128_fpAddTest_q)
BEGIN
-- Begin reserved scope level
CASE (concExc_uid128_fpAddTest_q) IS
WHEN "000" => excREnc_uid129_fpAddTest_q <= "01";
WHEN "001" => excREnc_uid129_fpAddTest_q <= "00";
WHEN "010" => excREnc_uid129_fpAddTest_q <= "10";
WHEN "011" => excREnc_uid129_fpAddTest_q <= "10";
WHEN "100" => excREnc_uid129_fpAddTest_q <= "11";
WHEN "101" => excREnc_uid129_fpAddTest_q <= "11";
WHEN "110" => excREnc_uid129_fpAddTest_q <= "11";
WHEN "111" => excREnc_uid129_fpAddTest_q <= "11";
WHEN OTHERS => -- unreachable
excREnc_uid129_fpAddTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- expRPostExc_uid148_fpAddTest(MUX,147)@1
expRPostExc_uid148_fpAddTest_s <= excREnc_uid129_fpAddTest_q;
expRPostExc_uid148_fpAddTest: PROCESS (expRPostExc_uid148_fpAddTest_s, en, cstAllZWE_uid20_fpAddTest_q, expRPreExc_uid118_fpAddTest_b, cstAllOWE_uid18_fpAddTest_q)
BEGIN
CASE (expRPostExc_uid148_fpAddTest_s) IS
WHEN "00" => expRPostExc_uid148_fpAddTest_q <= cstAllZWE_uid20_fpAddTest_q;
WHEN "01" => expRPostExc_uid148_fpAddTest_q <= expRPreExc_uid118_fpAddTest_b;
WHEN "10" => expRPostExc_uid148_fpAddTest_q <= cstAllOWE_uid18_fpAddTest_q;
WHEN "11" => expRPostExc_uid148_fpAddTest_q <= cstAllOWE_uid18_fpAddTest_q;
WHEN OTHERS => expRPostExc_uid148_fpAddTest_q <= (others => '0');
END CASE;
END PROCESS;
-- oneFracRPostExc2_uid141_fpAddTest(CONSTANT,140)
oneFracRPostExc2_uid141_fpAddTest_q <= "00000000000000000000001";
-- fracRPreExc_uid117_fpAddTest(BITSELECT,116)@1
fracRPreExc_uid117_fpAddTest_in <= rndExpFrac_uid104_fpAddTest_q(23 downto 0);
fracRPreExc_uid117_fpAddTest_b <= fracRPreExc_uid117_fpAddTest_in(23 downto 1);
-- fracRPostExc_uid144_fpAddTest(MUX,143)@1
fracRPostExc_uid144_fpAddTest_s <= excREnc_uid129_fpAddTest_q;
fracRPostExc_uid144_fpAddTest: PROCESS (fracRPostExc_uid144_fpAddTest_s, en, cstZeroWF_uid19_fpAddTest_q, fracRPreExc_uid117_fpAddTest_b, oneFracRPostExc2_uid141_fpAddTest_q)
BEGIN
CASE (fracRPostExc_uid144_fpAddTest_s) IS
WHEN "00" => fracRPostExc_uid144_fpAddTest_q <= cstZeroWF_uid19_fpAddTest_q;
WHEN "01" => fracRPostExc_uid144_fpAddTest_q <= fracRPreExc_uid117_fpAddTest_b;
WHEN "10" => fracRPostExc_uid144_fpAddTest_q <= cstZeroWF_uid19_fpAddTest_q;
WHEN "11" => fracRPostExc_uid144_fpAddTest_q <= oneFracRPostExc2_uid141_fpAddTest_q;
WHEN OTHERS => fracRPostExc_uid144_fpAddTest_q <= (others => '0');
END CASE;
END PROCESS;
-- R_uid149_fpAddTest(BITJOIN,148)@1
R_uid149_fpAddTest_q <= signRPostExc_uid140_fpAddTest_q & expRPostExc_uid148_fpAddTest_q & fracRPostExc_uid144_fpAddTest_q;
-- xOut(GPOUT,4)@1
q <= R_uid149_fpAddTest_q;
END normal;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
package wishbone_pkg is
constant c_wishbone_address_width : integer := 32;
constant c_wishbone_data_width : integer := 32;
subtype t_wishbone_address is
std_logic_vector(c_wishbone_address_width-1 downto 0);
subtype t_wishbone_data is
std_logic_vector(c_wishbone_data_width-1 downto 0);
subtype t_wishbone_byte_select is
std_logic_vector((c_wishbone_address_width/8)-1 downto 0);
subtype t_wishbone_cycle_type is
std_logic_vector(2 downto 0);
subtype t_wishbone_burst_type is
std_logic_vector(1 downto 0);
type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
type t_wishbone_address_granularity is (BYTE, WORD);
type t_wishbone_master_out is record
cyc : std_logic;
stb : std_logic;
adr : t_wishbone_address;
sel : t_wishbone_byte_select;
we : std_logic;
dat : t_wishbone_data;
end record t_wishbone_master_out;
subtype t_wishbone_slave_in is t_wishbone_master_out;
type t_wishbone_slave_out is record
ack : std_logic;
err : std_logic;
rty : std_logic;
stall : std_logic;
int : std_logic;
dat : t_wishbone_data;
end record t_wishbone_slave_out;
subtype t_wishbone_master_in is t_wishbone_slave_out;
subtype t_wishbone_device_descriptor is std_logic_vector(255 downto 0);
type t_wishbone_byte_select_array is array(natural range <>) of t_wishbone_byte_select;
type t_wishbone_data_array is array(natural range <>) of t_wishbone_data;
type t_wishbone_address_array is array(natural range <>) of t_wishbone_address;
type t_wishbone_master_out_array is array (natural range <>) of t_wishbone_master_out;
--type t_wishbone_slave_in_array is array (natural range <>) of t_wishbone_slave_in;
subtype t_wishbone_slave_in_array is t_wishbone_master_out_array;
type t_wishbone_slave_out_array is array (natural range <>) of t_wishbone_slave_out;
--type t_wishbone_master_in_array is array (natural range <>) of t_wishbone_master_in;
subtype t_wishbone_master_in_array is t_wishbone_slave_out_array;
constant cc_dummy_address : std_logic_vector(c_wishbone_address_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_data : std_logic_vector(c_wishbone_address_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_sel : std_logic_vector(c_wishbone_data_width/8-1 downto 0) :=
(others => 'X');
constant cc_dummy_slave_in : t_wishbone_slave_in :=
('0', '0', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
constant cc_dummy_master_out : t_wishbone_master_out := cc_dummy_slave_in;
-- Dangerous! Will stall a bus.
constant cc_dummy_slave_out : t_wishbone_slave_out :=
('X', 'X', 'X', 'X', 'X', cc_dummy_data);
constant cc_dummy_master_in : t_wishbone_master_in := cc_dummy_slave_out;
constant cc_dummy_address_array : t_wishbone_address_array(0 downto 0) := (0 => cc_dummy_address);
-- A generally useful function.
function f_ceil_log2(x : natural) return natural;
function f_bits2string(s : std_logic_vector) return string;
function f_string2bits(s : string) return std_logic_vector;
function f_string2svl (s : string) return std_logic_vector;
function f_slv2string (slv : std_logic_vector) return string;
function f_string_fix_len( s : string; ret_len : natural := 10; fill_char : character := '0' ) return string;
function f_hot_to_bin(x : std_logic_vector) return natural;
-- *** Wishbone slave interface functions ***
-- f_wb_wr:
-- processes an incoming write reqest to a register while honoring the select lines
-- valid modes are overwrite "owr", set "set" (bits are or'ed) and clear "clr" (bits are nand'ed)
function f_wb_wr(pval : std_logic_vector; ival : std_logic_vector; sel : std_logic_vector; mode : string := "owr") return std_logic_vector;
------------------------------------------------------------------------------
-- SDB declaration
------------------------------------------------------------------------------
constant c_sdb_device_length : natural := 512; -- bits
subtype t_sdb_record is std_logic_vector(c_sdb_device_length-1 downto 0);
type t_sdb_record_array is array(natural range <>) of t_sdb_record;
type t_sdb_product is record
vendor_id : std_logic_vector(63 downto 0);
device_id : std_logic_vector(31 downto 0);
version : std_logic_vector(31 downto 0);
date : std_logic_vector(31 downto 0);
name : string(1 to 19);
end record t_sdb_product;
type t_sdb_component is record
addr_first : std_logic_vector(63 downto 0);
addr_last : std_logic_vector(63 downto 0);
product : t_sdb_product;
end record t_sdb_component;
constant c_sdb_endian_big : std_logic := '0';
constant c_sdb_endian_little : std_logic := '1';
type t_sdb_device is record
abi_class : std_logic_vector(15 downto 0);
abi_ver_major : std_logic_vector(7 downto 0);
abi_ver_minor : std_logic_vector(7 downto 0);
wbd_endian : std_logic; -- 0 = big, 1 = little
wbd_width : std_logic_vector(3 downto 0); -- 3=64-bit, 2=32-bit, 1=16-bit, 0=8-bit
sdb_component : t_sdb_component;
end record t_sdb_device;
type t_sdb_bridge is record
sdb_child : std_logic_vector(63 downto 0);
sdb_component : t_sdb_component;
end record t_sdb_bridge;
type t_sdb_integration is record
product : t_sdb_product;
end record t_sdb_integration;
type t_sdb_repo_url is record
repo_url : string(1 to 63);
end record t_sdb_repo_url;
type t_sdb_synthesis is record
syn_module_name : string(1 to 16);
syn_commit_id : string(1 to 32);
syn_tool_name : string(1 to 8);
syn_tool_version : std_logic_vector(31 downto 0);
syn_date : std_logic_vector(31 downto 0);
syn_username : string(1 to 15);
end record t_sdb_synthesis;
-- general crossbar building functions
function f_sdb_create_array(g_enum_dev_id : boolean := false;
g_dev_id_offs : natural := 0;
g_enum_dev_name : boolean := false;
g_dev_name_offs : natural := 0;
device : t_sdb_device;
instances : natural := 1) return t_sdb_record_array;
function f_sdb_join_arrays(a : t_sdb_record_array; b : t_sdb_record_array) return t_sdb_record_array;
function f_sdb_extract_base_addr(sdb_record : t_sdb_record) return std_logic_vector;
function f_sdb_extract_end_addr(sdb_record : t_sdb_record) return std_logic_vector;
function f_sdb_automap_array(sdb_array : t_sdb_record_array; start_offset : t_wishbone_address := (others => '0')) return t_sdb_record_array;
function f_align_addr_offset(offs : unsigned; this_rng : unsigned; prev_rng : unsigned) return unsigned;
function f_sdb_create_rom_addr(sdb_array : t_sdb_record_array) return t_wishbone_address;
-- Used to configure a device at a certain address
function f_sdb_embed_device(device : t_sdb_device; address : t_wishbone_address) return t_sdb_record;
function f_sdb_embed_bridge(bridge : t_sdb_bridge; address : t_wishbone_address) return t_sdb_record;
function f_sdb_embed_integration(integr : t_sdb_integration) return t_sdb_record;
function f_sdb_embed_repo_url(url : t_sdb_repo_url) return t_sdb_record;
function f_sdb_embed_synthesis(syn : t_sdb_synthesis) return t_sdb_record;
function f_sdb_extract_device(sdb_record : t_sdb_record) return t_sdb_device;
function f_sdb_extract_bridge(sdb_record : t_sdb_record) return t_sdb_bridge;
function f_sdb_extract_integration(sdb_record : t_sdb_record) return t_sdb_integration;
function f_sdb_extract_repo_url(sdb_record : t_sdb_record) return t_sdb_repo_url;
function f_sdb_extract_synthesis(sdb_record : t_sdb_record) return t_sdb_synthesis;
-- Automatic crossbar mapping functions
function f_sdb_auto_device(device : t_sdb_device; enable : boolean := true) return t_sdb_record;
function f_sdb_auto_bridge(bridge : t_sdb_bridge; enable : boolean := true) return t_sdb_record;
function f_sdb_auto_layout(records : t_sdb_record_array) return t_sdb_record_array;
function f_sdb_auto_sdb (records : t_sdb_record_array) return t_wishbone_address;
-- For internal use by the crossbar
function f_sdb_embed_product(product : t_sdb_product) return std_logic_vector; -- (319 downto 8)
function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address) return std_logic_vector; -- (447 downto 8)
function f_sdb_extract_product(sdb_record : std_logic_vector(319 downto 8)) return t_sdb_product;
function f_sdb_extract_component(sdb_record : std_logic_vector(447 downto 8)) return t_sdb_component;
------------------------------------------------------------------------------
-- Components declaration
-------------------------------------------------------------------------------
component wb_slave_adapter
generic (
g_master_use_struct : boolean;
g_master_mode : t_wishbone_interface_mode;
g_master_granularity : t_wishbone_address_granularity;
g_slave_use_struct : boolean;
g_slave_mode : t_wishbone_interface_mode;
g_slave_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
sl_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := cc_dummy_address;
sl_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
sl_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := cc_dummy_sel;
sl_cyc_i : in std_logic := '0';
sl_stb_i : in std_logic := '0';
sl_we_i : in std_logic := '0';
sl_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
sl_err_o : out std_logic;
sl_rty_o : out std_logic;
sl_ack_o : out std_logic;
sl_stall_o : out std_logic;
sl_int_o : out std_logic;
slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
slave_o : out t_wishbone_slave_out;
ma_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
ma_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
ma_sel_o : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
ma_cyc_o : out std_logic;
ma_stb_o : out std_logic;
ma_we_o : out std_logic;
ma_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
ma_err_i : in std_logic := '0';
ma_rty_i : in std_logic := '0';
ma_ack_i : in std_logic := '0';
ma_stall_i : in std_logic := '0';
ma_int_i : in std_logic := '0';
master_i : in t_wishbone_master_in := cc_dummy_slave_out;
master_o : out t_wishbone_master_out);
end component;
component wb_async_bridge
generic (
g_simulation : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cpu_address_width : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
cpu_cs_n_i : in std_logic;
cpu_wr_n_i : in std_logic;
cpu_rd_n_i : in std_logic;
cpu_bs_n_i : in std_logic_vector(3 downto 0);
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
cpu_data_b : inout std_logic_vector(31 downto 0);
cpu_nwait_o : out std_logic;
wb_adr_o : out std_logic_vector(c_wishbone_address_width - 1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_sel_o : out std_logic_vector(3 downto 0);
wb_cyc_o : out std_logic;
wb_dat_i : in std_logic_vector (c_wishbone_data_width-1 downto 0);
wb_ack_i : in std_logic;
wb_stall_i : in std_logic := '0');
end component;
component xwb_async_bridge
generic (
g_simulation : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cpu_address_width : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
cpu_cs_n_i : in std_logic;
cpu_wr_n_i : in std_logic;
cpu_rd_n_i : in std_logic;
cpu_bs_n_i : in std_logic_vector(3 downto 0);
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
cpu_data_b : inout std_logic_vector(31 downto 0);
cpu_nwait_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in);
end component;
component xwb_bus_fanout
generic (
g_num_outputs : natural;
g_bits_per_slave : integer;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_slave_interface_mode : t_wishbone_interface_mode := CLASSIC);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
master_i : in t_wishbone_master_in_array(0 to g_num_outputs-1);
master_o : out t_wishbone_master_out_array(0 to g_num_outputs-1));
end component;
component xwb_crossbar
generic (
g_num_masters : integer;
g_num_slaves : integer;
g_registered : boolean;
g_address : t_wishbone_address_array;
g_mask : t_wishbone_address_array);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
end component;
-- Use the f_xwb_bridge_*_sdb to bridge a crossbar to another
function f_xwb_bridge_manual_sdb( -- take a manual bus size
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge;
function f_xwb_bridge_layout_sdb( -- determine bus size from layout
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge;
component xwb_sdb_crossbar
generic (
g_num_masters : integer;
g_num_slaves : integer;
g_registered : boolean := false;
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
end component;
component xwb_register_link -- puts a register of delay between crossbars
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out);
end component;
component sdb_rom is
generic(
g_layout : t_sdb_record_array;
g_bus_end : unsigned(63 downto 0));
port(
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out);
end component;
constant c_xwb_dma_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001f",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"cababa56",
version => x"00000001",
date => x"20120518",
name => "WB4-Streaming-DMA_0")));
component xwb_dma is
generic(
-- Value 0 cannot stream
-- Value 1 only slaves with async ACK can stream
-- Value 2 only slaves with combined latency <= 2 can stream
-- Value 3 only slaves with combined latency <= 6 can stream
-- Value 4 only slaves with combined latency <= 14 can stream
-- ....
logRingLen : integer := 4
);
port(
-- Common wishbone signals
clk_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- Master reader port
r_master_i : in t_wishbone_master_in;
r_master_o : out t_wishbone_master_out;
-- Master writer port
w_master_i : in t_wishbone_master_in;
w_master_o : out t_wishbone_master_out;
-- Pulsed high completion signal
interrupt_o : out std_logic
);
end component;
-- If you reset one clock domain, you must reset BOTH!
-- Release of the reset lines may be arbitrarily out-of-phase
component xwb_clock_crossing is
generic(
g_size : natural := 16);
port(
-- Slave control port
slave_clk_i : in std_logic;
slave_rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- Master reader port
master_clk_i : in std_logic;
master_rst_n_i : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out);
end component;
-- g_size is in words
function f_xwb_dpram(g_size : natural) return t_sdb_device;
component xwb_dpram
generic (
g_size : natural;
g_init_file : string := "";
g_must_have_init_file : boolean := true;
g_slave1_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_slave2_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_slave1_granularity : t_wishbone_address_granularity := WORD;
g_slave2_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out;
slave2_i : in t_wishbone_slave_in;
slave2_o : out t_wishbone_slave_out);
end component;
-- Just like the DMA controller, but constantly at address 0
component xwb_streamer is
generic(
-- Value 0 cannot stream
-- Value 1 only slaves with async ACK can stream
-- Value 2 only slaves with combined latency = 2 can stream
-- Value 3 only slaves with combined latency = 6 can stream
-- Value 4 only slaves with combined latency = 14 can stream
-- ....
logRingLen : integer := 4
);
port(
-- Common wishbone signals
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Master reader port
r_master_i : in t_wishbone_master_in;
r_master_o : out t_wishbone_master_out;
-- Master writer port
w_master_i : in t_wishbone_master_in;
w_master_o : out t_wishbone_master_out);
end component;
constant c_xwb_gpio_port_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"441c5143",
version => x"00000001",
date => x"20121129",
name => "WB-GPIO-Port ")));
component wb_gpio_port
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
g_with_builtin_tristates : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
component xwb_gpio_port
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
g_with_builtin_tristates : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
constant c_xwb_i2c_master_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"123c5443",
version => x"00000001",
date => x"20121129",
name => "WB-I2C-Master ")));
component wb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_interfaces : integer := 1);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
scl_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0));
end component;
component xwb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_interfaces : integer := 1);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
scl_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0));
end component;
component xwb_lm32
generic (
g_profile : string;
g_reset_vector : std_logic_vector(31 downto 0) := x"00000000");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
irq_i : in std_logic_vector(31 downto 0);
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
iwb_o : out t_wishbone_master_out;
iwb_i : in t_wishbone_master_in);
end component;
constant c_xwb_onewire_master_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"779c5443",
version => x"00000001",
date => x"20121129",
name => "WB-OneWire-Master ")));
component wb_onewire_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string := "1.0";
g_ow_btp_overdrive : string := "5.0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
end component;
component xwb_onewire_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string := "5.0";
g_ow_btp_overdrive : string := "1.0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
end component;
constant c_xwb_spi_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"e503947e", -- echo "WB-SPI.Control " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-SPI.Control ")));
component wb_spi
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_divider_len : integer := 16;
g_max_char_len : integer := 128;
g_num_slaves : integer := 8);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
pad_cs_o : out std_logic_vector(g_num_slaves-1 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic);
end component;
component xwb_spi
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_divider_len : integer := 16;
g_max_char_len : integer := 128;
g_num_slaves : integer := 8);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
pad_cs_o : out std_logic_vector(g_num_slaves-1 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic);
end component;
component wb_simple_uart
generic (
g_with_virtual_uart : boolean := false;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_vuart_fifo_size : integer := 1024);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic);
end component;
component xwb_simple_uart
generic (
g_with_virtual_uart : boolean := false;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_vuart_fifo_size : integer := 1024);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic);
end component;
component wb_simple_pwm
generic (
g_num_channels : integer range 1 to 8;
g_regs_size : integer range 1 to 16 := 16;
g_default_period : integer range 0 to 255 := 0;
g_default_presc : integer range 0 to 255 := 0;
g_default_val : integer range 0 to 255 := 0;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
pwm_o : out std_logic_vector(g_num_channels-1 downto 0));
end component;
component xwb_simple_pwm
generic (
g_num_channels : integer range 1 to 8;
g_regs_size : integer range 1 to 16 := 16;
g_default_period : integer range 0 to 255 := 0;
g_default_presc : integer range 0 to 255 := 0;
g_default_val : integer range 0 to 255 := 0;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pwm_o : out std_logic_vector(g_num_channels-1 downto 0));
end component;
component wb_tics
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_period : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic);
end component;
component xwb_tics
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_period : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor);
end component;
component wb_vic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_interrupts : natural;
g_init_vectors : t_wishbone_address_array := cc_dummy_address_array
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_master_o : out std_logic);
end component;
constant c_xwb_vic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000013",
version => x"00000002",
date => x"20120113",
name => "WB-VIC-Int.Control ")));
component xwb_vic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_interrupts : natural;
g_init_vectors : t_wishbone_address_array := cc_dummy_address_array);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_master_o : out std_logic);
end component;
constant c_wb_serial_lcd_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"b77a5045",
version => x"00000001",
date => x"20130222",
name => "SERIAL-LCD-DISPLAY ")));
component wb_serial_lcd
generic(
g_cols : natural := 40;
g_rows : natural := 24;
g_hold : natural := 15; -- How many times to repeat a line (for sharpness)
g_wait : natural := 1); -- How many cycles per state change (for 20MHz timing)
port(
slave_clk_i : in std_logic;
slave_rstn_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
di_clk_i : in std_logic;
di_scp_o : out std_logic;
di_lp_o : out std_logic;
di_flm_o : out std_logic;
di_dat_o : out std_logic);
end component;
function f_wb_spi_flash_sdb(g_bits : natural) return t_sdb_device;
component wb_spi_flash is
generic(
g_port_width : natural := 1; -- 1 for EPCS, 4 for EPCQ
g_addr_width : natural := 24; -- log of memory (24=16MB)
g_idle_time : natural := 3;
g_dummy_time : natural := 8;
-- leave these at defaults if you have:
-- a) slow clock, b) valid constraints, or c) registered in/outputs
g_input_latch_edge : std_logic := '1'; -- rising
g_output_latch_edge : std_logic := '0'; -- falling
g_input_to_output_cycles : natural := 1); -- between 1 and 8
port(
clk_i : in std_logic;
rstn_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- For properly constrained designs, set clk_out_i = clk_in_i.
clk_out_i : in std_logic;
clk_in_i : in std_logic;
ncs_o : out std_logic;
oe_o : out std_logic_vector(g_port_width-1 downto 0);
asdi_o : out std_logic_vector(g_port_width-1 downto 0);
data_i : in std_logic_vector(g_port_width-1 downto 0);
external_request_i : in std_logic := '0'; -- JTAG wants to use SPI?
external_granted_o : out std_logic);
end component;
-----------------------------------------------------------------------------
-- I2C to Wishbone bridge, following protocol defined with ELMA
-----------------------------------------------------------------------------
component wb_i2c_bridge is
generic
(
-- FSM watchdog timeout, see Appendix A in the component documentation for
-- an example of setting this generic
g_fsm_wdt : positive
);
port
(
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- I2C address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- Status outputs
-- TIP : Transfer In Progress
-- '1' when the I2C slave detects a matching I2C address, thus a
-- transfer is in progress
-- '0' when idle
-- ERR : Error
-- '1' when the SysMon attempts to access an invalid WB slave
-- '0' when idle
-- WDTO : Watchdog timeout (single clock cycle pulse)
-- '1' -- timeout of watchdog occured
-- '0' -- when idle
tip_o : out std_logic;
err_p_o : out std_logic;
wdto_p_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
wbm_cyc_o : out std_logic;
wbm_sel_o : out std_logic_vector(3 downto 0);
wbm_we_o : out std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_adr_o : out std_logic_vector(31 downto 0);
wbm_ack_i : in std_logic;
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end component wb_i2c_bridge;
------------------------------------------------------------------------------
-- MultiBoot component
------------------------------------------------------------------------------
component xwb_xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component xwb_xil_multiboot;
constant c_xwb_xil_multiboot_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001f",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"11da333d", -- echo "WB-Xilinx-MultiBoot" | md5sum | cut -c1-8
version => x"00000001",
date => x"20140313",
name => "WB-Xilinx-MultiBoot")));
end wishbone_pkg;
package body wishbone_pkg is
-- f_wb_wr: processes a write reqest to a slave register with select lines. valid modes are "owr", "set" and "clr"
function f_wb_wr(pval : std_logic_vector; ival : std_logic_vector; sel : std_logic_vector; mode : string := "owr") return std_logic_vector is
variable n_sel : std_logic_vector(pval'range);
variable n_val : std_logic_vector(pval'range);
variable result : std_logic_vector(pval'range);
begin
for i in pval'range loop
n_sel(i) := sel(i / 8);
n_val(i) := ival(i);
end loop;
if(mode = "set") then
result := pval or (n_val and n_sel);
elsif (mode = "clr") then
result := pval and not (n_val and n_sel);
else
result := (pval and not n_sel) or (n_val and n_sel);
end if;
return result;
end f_wb_wr;
function f_ceil_log2(x : natural) return natural is
begin
if x <= 1
then return 0;
else return f_ceil_log2((x+1)/2) +1;
end if;
end f_ceil_log2;
function f_sdb_embed_product(product : t_sdb_product)
return std_logic_vector -- (319 downto 8)
is
variable result : std_logic_vector(319 downto 8);
begin
result(319 downto 256) := product.vendor_id;
result(255 downto 224) := product.device_id;
result(223 downto 192) := product.version;
result(191 downto 160) := product.date;
for i in 0 to 18 loop -- string to ascii
result(159-i*8 downto 152-i*8) :=
std_logic_vector(to_unsigned(character'pos(product.name(i+1)), 8));
end loop;
return result;
end;
function f_sdb_extract_product(sdb_record : std_logic_vector(319 downto 8))
return t_sdb_product
is
variable result : t_sdb_product;
begin
result.vendor_id := sdb_record(319 downto 256);
result.device_id := sdb_record(255 downto 224);
result.version := sdb_record(223 downto 192);
result.date := sdb_record(191 downto 160);
for i in 0 to 18 loop -- ascii to string
result.name(i+1) := character'val(to_integer(unsigned(sdb_record(159-i*8 downto 152-i*8))));
end loop;
return result;
end;
function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address)
return std_logic_vector -- (447 downto 8)
is
variable result : std_logic_vector(447 downto 8);
constant first : unsigned(63 downto 0) := unsigned(sdb_component.addr_first);
constant last : unsigned(63 downto 0) := unsigned(sdb_component.addr_last);
variable base : unsigned(63 downto 0) := (others => '0');
begin
base(address'length-1 downto 0) := unsigned(address);
result(447 downto 384) := std_logic_vector(base);
result(383 downto 320) := std_logic_vector(base + last - first);
result(319 downto 8) := f_sdb_embed_product(sdb_component.product);
return result;
end;
function f_sdb_extract_component(sdb_record : std_logic_vector(447 downto 8))
return t_sdb_component
is
variable result : t_sdb_component;
begin
result.addr_first := sdb_record(447 downto 384);
result.addr_last := sdb_record(383 downto 320);
result.product := f_sdb_extract_product(sdb_record(319 downto 8));
return result;
end;
function f_sdb_embed_device(device : t_sdb_device; address : t_wishbone_address)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 496) := device.abi_class;
result(495 downto 488) := device.abi_ver_major;
result(487 downto 480) := device.abi_ver_minor;
result(479 downto 456) := (others => '0');
result(455) := device.wbd_endian;
result(454 downto 452) := (others => '0');
result(451 downto 448) := device.wbd_width;
result(447 downto 8) := f_sdb_embed_component(device.sdb_component, address);
result(7 downto 0) := x"01"; -- device
return result;
end;
function f_sdb_extract_device(sdb_record : t_sdb_record)
return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := sdb_record(511 downto 496);
result.abi_ver_major := sdb_record(495 downto 488);
result.abi_ver_minor := sdb_record(487 downto 480);
result.wbd_endian := sdb_record(452);
result.wbd_width := sdb_record(451 downto 448);
result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
assert sdb_record(7 downto 0) = x"01"
report "Cannot extract t_sdb_device from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity failure;
return result;
end;
function f_sdb_embed_integration(integr : t_sdb_integration)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 320) := (others => '0');
result(319 downto 8) := f_sdb_embed_product(integr.product);
result(7 downto 0) := x"80"; -- integration record
return result;
end f_sdb_embed_integration;
function f_sdb_extract_integration(sdb_record : t_sdb_record)
return t_sdb_integration
is
variable result : t_sdb_integration;
begin
result.product := f_sdb_extract_product(sdb_record(319 downto 8));
assert sdb_record(7 downto 0) = x"80"
report "Cannot extract t_sdb_integration from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity Failure;
return result;
end f_sdb_extract_integration;
function f_sdb_embed_repo_url(url : t_sdb_repo_url)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 8) := f_string2svl(url.repo_url);
result( 7 downto 0) := x"81"; -- repo_url record
return result;
end;
function f_sdb_extract_repo_url(sdb_record : t_sdb_record)
return t_sdb_repo_url
is
variable result : t_sdb_repo_url;
begin
result.repo_url := f_slv2string(sdb_record(511 downto 8));
assert sdb_record(7 downto 0) = x"81"
report "Cannot extract t_sdb_repo_url from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity Failure;
return result;
end;
function f_sdb_embed_synthesis(syn : t_sdb_synthesis)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 384) := f_string2svl(syn.syn_module_name);
result(383 downto 256) := f_string2bits(syn.syn_commit_id);
result(255 downto 192) := f_string2svl(syn.syn_tool_name);
result(191 downto 160) := syn.syn_tool_version;
result(159 downto 128) := syn.syn_date;
result(127 downto 8) := f_string2svl(syn.syn_username);
result( 7 downto 0) := x"82"; -- synthesis record
return result;
end;
function f_sdb_extract_synthesis(sdb_record : t_sdb_record)
return t_sdb_synthesis
is
variable result : t_sdb_synthesis;
begin
result.syn_module_name := f_slv2string(sdb_record(511 downto 384));
result.syn_commit_id := f_bits2string(sdb_record(383 downto 256));
result.syn_tool_name := f_slv2string(sdb_record(255 downto 192));
result.syn_tool_version := sdb_record(191 downto 160);
result.syn_date := sdb_record(159 downto 128);
result.syn_username := f_slv2string(sdb_record(127 downto 8));
assert sdb_record(7 downto 0) = x"82"
report "Cannot extract t_sdb_repo_url from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity Failure;
return result;
end;
function f_sdb_embed_bridge(bridge : t_sdb_bridge; address : t_wishbone_address)
return t_sdb_record
is
variable result : t_sdb_record;
constant first : unsigned(63 downto 0) := unsigned(bridge.sdb_component.addr_first);
constant child : unsigned(63 downto 0) := unsigned(bridge.sdb_child);
variable base : unsigned(63 downto 0) := (others => '0');
begin
base(address'length-1 downto 0) := unsigned(address);
result(511 downto 448) := std_logic_vector(base + child - first);
result(447 downto 8) := f_sdb_embed_component(bridge.sdb_component, address);
result(7 downto 0) := x"02"; -- bridge
return result;
end;
function f_sdb_extract_bridge(sdb_record : t_sdb_record)
return t_sdb_bridge
is
variable result : t_sdb_bridge;
begin
result.sdb_child := sdb_record(511 downto 448);
result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
assert sdb_record(7 downto 0) = x"02"
report "Cannot extract t_sdb_bridge from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity failure;
return result;
end;
function f_sdb_auto_device(device : t_sdb_device; enable : boolean := true)
return t_sdb_record
is
constant c_zero : t_wishbone_address := (others => '0');
variable v_empty : t_sdb_record := (others => '0');
begin
v_empty(7 downto 0) := (others => '1');
if enable then
return f_sdb_embed_device(device, c_zero);
else
return v_empty;
end if;
end f_sdb_auto_device;
function f_sdb_auto_bridge(bridge : t_sdb_bridge; enable : boolean := true)
return t_sdb_record
is
constant c_zero : t_wishbone_address := (others => '0');
variable v_empty : t_sdb_record := (others => '0');
begin
v_empty(7 downto 0) := (others => '1');
if enable then
return f_sdb_embed_bridge(bridge, c_zero);
else
return v_empty;
end if;
end f_sdb_auto_bridge;
subtype t_usdb_address is unsigned(63 downto 0);
type t_usdb_address_array is array(natural range <>) of t_usdb_address;
-- We map devices by placing the smallest ones first.
-- This is guaranteed to pack the maximum number of devices in the smallest space.
-- If a device has an address != 0, we leave it alone and let the crossbar confirm
-- that the address does not cause a conflict.
function f_sdb_auto_layout_helper(records : t_sdb_record_array)
return t_usdb_address_array
is
alias c_records : t_sdb_record_array(records'length-1 downto 0) is records;
constant c_zero : t_usdb_address := (others => '0');
constant c_used_entries : natural := c_records'length + 1;
constant c_rom_entries : natural := 2**f_ceil_log2(c_used_entries);
constant c_rom_bytes : natural := c_rom_entries * c_sdb_device_length / 8;
variable v_component : t_sdb_component;
variable v_sizes : t_usdb_address_array(c_records'length downto 0);
variable v_address : t_usdb_address_array(c_records'length downto 0);
variable v_map : std_logic_vector(c_records'length downto 0) := (others => '0');
variable v_cursor : unsigned(63 downto 0) := (others => '0');
variable v_increment : unsigned(63 downto 0) := (others => '0');
begin
-- First, extract the length of the devices, ignoring those not to be mapped
for i in c_records'range loop
v_component := f_sdb_extract_component(c_records(i)(447 downto 8));
v_sizes(i) := unsigned(v_component.addr_last);
v_address(i) := unsigned(v_component.addr_first);
-- Silently round up to a power of two; the crossbar will give a warning for us
for j in 62 downto 0 loop
v_sizes(i)(j) := v_sizes(i)(j+1) or v_sizes(i)(j);
end loop;
-- Only map devices/bridges at address zero
if v_address(i) = c_zero then
case c_records(i)(7 downto 0) is
when x"01" => v_map(i) := '1';
when x"02" => v_map(i) := '1';
when others => null;
end case;
end if;
end loop;
-- Assign the SDB record a spot as well
v_address(c_records'length) := (others => '0');
v_sizes(c_records'length) := to_unsigned(c_rom_bytes-1, 64);
v_map(c_records'length) := '1';
-- Start assigning addresses
for j in 0 to 63 loop
v_increment := (others => '0');
v_increment(j) := '1';
for i in 0 to c_records'length loop
if v_map(i) = '1' and v_sizes(i)(j) = '0' then
v_map(i) := '0';
v_address(i) := v_cursor;
v_cursor := v_cursor + v_increment;
end if;
end loop;
-- Round up to the next required alignment
if v_cursor(j) = '1' then
v_cursor := v_cursor + v_increment;
end if;
end loop;
return v_address;
end f_sdb_auto_layout_helper;
function f_sdb_auto_layout(records : t_sdb_record_array)
return t_sdb_record_array
is
alias c_records : t_sdb_record_array(records'length-1 downto 0) is records;
variable v_result : t_sdb_record_array(c_records'range) := c_records;
constant c_address : t_usdb_address_array := f_sdb_auto_layout_helper(c_records);
variable v_address : t_wishbone_address;
begin
-- Put the addresses into the mapping
for i in v_result'range loop
v_address := std_logic_vector(c_address(i)(t_wishbone_address'range));
if c_records(i)(7 downto 0) = x"01" then
v_result(i) := f_sdb_embed_device(f_sdb_extract_device(v_result(i)), v_address);
end if;
if c_records(i)(7 downto 0) = x"02" then
v_result(i) := f_sdb_embed_bridge(f_sdb_extract_bridge(v_result(i)), v_address);
end if;
end loop;
return v_result;
end f_sdb_auto_layout;
function f_sdb_auto_sdb(records : t_sdb_record_array)
return t_wishbone_address
is
alias c_records : t_sdb_record_array(records'length-1 downto 0) is records;
constant c_address : t_usdb_address_array(c_records'length downto 0) := f_sdb_auto_layout_helper(c_records);
begin
return std_logic_vector(c_address(c_records'length)(t_wishbone_address'range));
end f_sdb_auto_sdb;
--**************************************************************************************************************************--
-- START MAT's NEW FUNCTIONS FROM 18th Oct 2013
------------------------------------------------------------------------------------------------------------------------------
function f_sdb_create_array(g_enum_dev_id : boolean := false;
g_dev_id_offs : natural := 0;
g_enum_dev_name : boolean := false;
g_dev_name_offs : natural := 0;
device : t_sdb_device;
instances : natural := 1)
return t_sdb_record_array is
variable result : t_sdb_record_array(instances-1 downto 0);
variable i,j, pos : natural;
variable dev, newdev : t_sdb_device;
variable serial_no : string(1 to 3);
variable text_possible : boolean := false;
begin
dev := device;
report "### Creating " & integer'image(instances) & " x " & dev.sdb_component.product.name
severity note;
for i in 0 to instances-1 loop
newdev := dev;
if(g_enum_dev_id) then
dev.sdb_component.product.device_id :=
std_logic_vector( unsigned(dev.sdb_component.product.device_id)
+ to_unsigned(i+g_dev_id_offs, dev.sdb_component.product.device_id'length));
end if;
if(g_enum_dev_name) then
-- find end of name
for j in dev.sdb_component.product.name'length downto 1 loop
if(dev.sdb_component.product.name(j) /= ' ') then
pos := j;
exit;
end if;
end loop;
-- convert i+g_dev_name_offs to string
serial_no := f_string_fix_len(integer'image(i+g_dev_name_offs), serial_no'length);
report "### Now: " & serial_no & " of " & dev.sdb_component.product.name severity note;
-- check if space is sufficient
assert (serial_no'length+1 <= dev.sdb_component.product.name'length - pos)
report "Not enough space in namestring of sdb_device " & dev.sdb_component.product.name
& " to add serial number " & serial_no & ". Space available " &
integer'image(dev.sdb_component.product.name'length-pos-1) & ", required "
& integer'image(serial_no'length+1)
severity Failure;
end if;
if(g_enum_dev_name) then
newdev.sdb_component.product.name(pos+1) := '_';
for j in 1 to serial_no'length loop
newdev.sdb_component.product.name(pos+1+j) := serial_no(j);
end loop;
end if;
-- insert
report "### to: " & newdev.sdb_component.product.name severity note;
result(i) := f_sdb_embed_device(newdev, (others=>'0'));
end loop;
return result;
end f_sdb_create_array;
function f_sdb_join_arrays(a : t_sdb_record_array; b : t_sdb_record_array) return t_sdb_record_array is
variable result : t_sdb_record_array(a'length+b'length-1 downto 0);
variable i : natural;
begin
for i in 0 to a'left loop
result(i) := a(i);
end loop;
for i in 0 to b'left loop
result(i+a'length) := b(i);
end loop;
return result;
end f_sdb_join_arrays;
function f_sdb_extract_base_addr(sdb_record : t_sdb_record) return std_logic_vector is
begin
return sdb_record(447 downto 384);
end f_sdb_extract_base_addr;
function f_sdb_extract_end_addr(sdb_record : t_sdb_record) return std_logic_vector is
begin
return sdb_record(383 downto 320);
end f_sdb_extract_end_addr;
function f_align_addr_offset(offs : unsigned; this_rng : unsigned; prev_rng : unsigned)
return unsigned is
variable this_pow, prev_pow : natural;
variable start, env, result : unsigned(63 downto 0) := (others => '0');
begin
start(offs'left downto 0) := offs;
--calculate address envelopes (next power of 2) for previous and this component and choose the larger one
this_pow := f_hot_to_bin(std_logic_vector(this_rng));
prev_pow := f_hot_to_bin(std_logic_vector(prev_rng));
-- no max(). thank you very much, std_numeric :-/
if(this_pow >= prev_pow) then
env(this_pow) := '1';
else
env(prev_pow) := '1';
end if;
--round up to the next multiple of the envelope...
if(prev_rng /= 0) then
result := start + env - (start mod env);
else
result := start; --...except for first element, result is start.
end if;
return result;
end f_align_addr_offset;
-- generates aligned address map for an sdb_record_array, accepts optional start offset
function f_sdb_automap_array(sdb_array : t_sdb_record_array; start_offset : t_wishbone_address := (others => '0'))
return t_sdb_record_array is
variable this_rng : unsigned(63 downto 0) := (others => '0');
variable prev_rng : unsigned(63 downto 0) := (others => '0');
variable prev_offs : unsigned(63 downto 0) := (others => '0');
variable this_offs : unsigned(63 downto 0) := (others => '0');
variable device : t_sdb_device;
variable bridge : t_sdb_bridge;
variable sdb_type : std_logic_vector(7 downto 0);
variable i : natural;
variable result : t_sdb_record_array(sdb_array'length-1 downto 0); -- last
begin
prev_offs(start_offset'left downto 0) := unsigned(start_offset);
--traverse the array
for i in 0 to sdb_array'length-1 loop
-- find the fitting extraction function by evaling the type byte.
-- could also use the component, but it's safer to use Wes' embed and extract functions.
sdb_type := sdb_array(i)(7 downto 0);
case sdb_type is
--device
when x"01" => device := f_sdb_extract_device(sdb_array(i));
this_rng := unsigned(device.sdb_component.addr_last) - unsigned(device.sdb_component.addr_first);
this_offs := f_align_addr_offset(prev_offs, this_rng, prev_rng);
result(i) := f_sdb_embed_device(device, std_logic_vector(this_offs(31 downto 0)));
--bridge
when x"02" => bridge := f_sdb_extract_bridge(sdb_array(i));
this_rng := unsigned(bridge.sdb_component.addr_last) - unsigned(bridge.sdb_component.addr_first);
this_offs := f_align_addr_offset(prev_offs, this_rng, prev_rng);
result(i) := f_sdb_embed_bridge(bridge, std_logic_vector(this_offs(31 downto 0)) );
--other
when others => result(i) := sdb_array(i);
end case;
-- doesnt hurt because this_* doesnt change if its not a device or bridge
prev_rng := this_rng;
prev_offs := this_offs;
end loop;
report "##* " & integer'image(sdb_array'length) & " Elements, last address: " & f_bits2string(std_logic_vector(this_offs+this_rng)) severity Note;
return result;
end f_sdb_automap_array;
-- find place for sdb rom on crossbar and return address. try to put it in an address gap.
function f_sdb_create_rom_addr(sdb_array : t_sdb_record_array) return t_wishbone_address is
constant rom_bytes : natural := (2**f_ceil_log2(sdb_array'length + 1)) * (c_sdb_device_length / 8);
variable result : t_wishbone_address := (others => '0');
variable this_base, this_end : unsigned(63 downto 0) := (others => '0');
variable prev_base, prev_end : unsigned(63 downto 0) := (others => '0');
variable rom_base : unsigned(63 downto 0) := (others => '0');
variable sdb_type : std_logic_vector(7 downto 0);
begin
--traverse the array
for i in 0 to sdb_array'length-1 loop
sdb_type := sdb_array(i)(7 downto 0);
if(sdb_type = x"01" or sdb_type = x"02") then
-- get
this_base := unsigned(f_sdb_extract_base_addr(sdb_array(i)));
this_end := unsigned(f_sdb_extract_end_addr(sdb_array(i)));
if(unsigned(result) = 0) then
rom_base := f_align_addr_offset(prev_base, to_unsigned(rom_bytes-1, 64), (prev_end-prev_base));
if(rom_base + to_unsigned(rom_bytes, 64) <= this_base) then
result := std_logic_vector(rom_base(t_wishbone_address'left downto 0));
end if;
end if;
prev_base := this_base;
prev_end := this_end;
end if;
end loop;
-- if there was no gap to fit the sdb rom, place it at the end
if(unsigned(result) = 0) then
result := std_logic_vector(f_align_addr_offset(this_base, to_unsigned(rom_bytes-1, 64),
this_end-this_base)(t_wishbone_address'left downto 0));
end if;
return result;
end f_sdb_create_rom_addr;
------------------------------------------------------------------------------------------------------------------------------
-- END MAT's NEW FUNCTIONS FROM 18th Oct 2013
------------------------------------------------------------------------------------------------------------------------------
function f_xwb_bridge_manual_sdb(
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge
is
variable result : t_sdb_bridge;
begin
result.sdb_child := (others => '0');
result.sdb_child(c_wishbone_address_width-1 downto 0) := g_sdb_addr;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := (others => '0');
result.sdb_component.addr_last(c_wishbone_address_width-1 downto 0) := g_size;
result.sdb_component.product.vendor_id := x"0000000000000651"; -- GSI
result.sdb_component.product.device_id := x"eef0b198";
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120511";
result.sdb_component.product.name := "WB4-Bridge-GSI ";
return result;
end f_xwb_bridge_manual_sdb;
function f_xwb_bridge_layout_sdb(
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge
is
alias c_layout : t_sdb_record_array(g_layout'length-1 downto 0) is g_layout;
-- How much space does the ROM need?
constant c_used_entries : natural := c_layout'length + 1;
constant c_rom_entries : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
constant c_sdb_bytes : natural := c_sdb_device_length / 8;
constant c_rom_bytes : natural := c_rom_entries * c_sdb_bytes;
variable result : unsigned(63 downto 0);
variable sdb_component : t_sdb_component;
begin
if not g_wraparound then
result := (others => '0');
for i in 0 to c_wishbone_address_width-1 loop
result(i) := '1';
end loop;
else
-- The ROM will be an addressed slave as well
result := (others => '0');
result(c_wishbone_address_width-1 downto 0) := unsigned(g_sdb_addr);
result := result + to_unsigned(c_rom_bytes, 64) - 1;
for i in c_layout'range loop
sdb_component := f_sdb_extract_component(c_layout(i)(447 downto 8));
if unsigned(sdb_component.addr_last) > result then
result := unsigned(sdb_component.addr_last);
end if;
end loop;
-- round result up to a power of two -1
for i in 62 downto 0 loop
result(i) := result(i) or result(i+1);
end loop;
end if;
return f_xwb_bridge_manual_sdb(std_logic_vector(result(c_wishbone_address_width-1 downto 0)), g_sdb_addr);
end f_xwb_bridge_layout_sdb;
function f_xwb_dpram(g_size : natural) return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := x"0001"; -- RAM device
result.abi_ver_major := x"01";
result.abi_ver_minor := x"00";
result.wbd_width := x"7"; -- 32/16/8-bit supported
result.wbd_endian := c_sdb_endian_big;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := std_logic_vector(to_unsigned(g_size*4-1, 64));
result.sdb_component.product.vendor_id := x"000000000000CE42"; -- CERN
result.sdb_component.product.device_id := x"66cfeb52";
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120305";
result.sdb_component.product.name := "WB4-BlockRAM ";
return result;
end f_xwb_dpram;
function f_bits2string(s : std_logic_vector) return string is
--- extend length to full hex nibble
variable result : string((s'length+7)/4 downto 1);
variable s_norm : std_logic_vector(result'length*4-1 downto 0) := (others=>'0');
variable cut : natural;
variable nibble: std_logic_vector(3 downto 0);
begin
s_norm(s'length-1 downto 0) := s;
for i in result'length-1 downto 0 loop
nibble := s_norm(i*4+3 downto i*4);
case nibble is
when "0000" => result(i+1) := '0';
when "0001" => result(i+1) := '1';
when "0010" => result(i+1) := '2';
when "0011" => result(i+1) := '3';
when "0100" => result(i+1) := '4';
when "0101" => result(i+1) := '5';
when "0110" => result(i+1) := '6';
when "0111" => result(i+1) := '7';
when "1000" => result(i+1) := '8';
when "1001" => result(i+1) := '9';
when "1010" => result(i+1) := 'a';
when "1011" => result(i+1) := 'b';
when "1100" => result(i+1) := 'c';
when "1101" => result(i+1) := 'd';
when "1110" => result(i+1) := 'e';
when "1111" => result(i+1) := 'f';
when others => result(i+1) := 'X';
end case;
end loop;
-- trim leading 0s
strip : for i in result'length downto 1 loop
cut := i;
exit strip when result(i) /= '0';
end loop;
return "0x" & result(cut downto 1);
end f_bits2string;
-- Converts string (hex number, without leading 0x) to std_logic_vector
function f_string2bits(s : string) return std_logic_vector is
variable slv : std_logic_vector(s'length*4-1 downto 0);
variable nibble : std_logic_vector(3 downto 0);
begin
for i in 0 to s'length-1 loop
case s(i+1) is
when '0' => nibble := X"0";
when '1' => nibble := X"1";
when '2' => nibble := X"2";
when '3' => nibble := X"3";
when '4' => nibble := X"4";
when '5' => nibble := X"5";
when '6' => nibble := X"6";
when '7' => nibble := X"7";
when '8' => nibble := X"8";
when '9' => nibble := X"9";
when 'a' => nibble := X"A";
when 'A' => nibble := X"A";
when 'b' => nibble := X"B";
when 'B' => nibble := X"B";
when 'c' => nibble := X"C";
when 'C' => nibble := X"C";
when 'd' => nibble := X"D";
when 'D' => nibble := X"D";
when 'e' => nibble := X"E";
when 'E' => nibble := X"E";
when 'f' => nibble := X"F";
when 'F' => nibble := X"F";
when others => nibble := "XXXX";
end case;
slv(((i+1)*4)-1 downto i*4) := nibble;
end loop;
return slv;
end f_string2bits;
-- Converts string to ascii (std_logic_vector)
function f_string2svl (s : string) return std_logic_vector is
variable slv : std_logic_vector((s'length * 8) - 1 downto 0);
begin
for i in 0 to s'length-1 loop
slv(slv'high-i*8 downto (slv'high-7)-i*8) :=
std_logic_vector(to_unsigned(character'pos(s(i+1)), 8));
end loop;
return slv;
end f_string2svl;
-- Converts ascii (std_logic_vector) to string
function f_slv2string (slv : std_logic_vector) return string is
variable s : string(1 to slv'length/8);
begin
for i in 0 to (slv'length/8)-1 loop
s(i+1) := character'val(to_integer(unsigned(slv(slv'high-i*8 downto (slv'high-7)-i*8))));
end loop;
return s;
end f_slv2string;
-- pads a string of unknown length to a given length (useful for integer'image)
function f_string_fix_len ( s : string; ret_len : natural := 10; fill_char : character := '0' ) return string is
variable ret_v : string (1 to ret_len);
constant pad_len : integer := ret_len - s'length ;
variable pad_v : string (1 to abs(pad_len));
begin
if pad_len < 1 then
ret_v := s(ret_v'range);
else
pad_v := (others => fill_char);
ret_v := pad_v & s;
end if;
return ret_v;
end f_string_fix_len;
function f_hot_to_bin(x : std_logic_vector) return natural is
variable rv : natural;
begin
rv := 0;
-- if there are few ones set in _x_ then the most significant will be
-- translated to bin
for i in 0 to x'left loop
if x(i) = '1' then
rv := i+1;
end if;
end loop;
return rv;
end function;
function f_wb_spi_flash_sdb(g_bits : natural) return t_sdb_device is
variable result : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"02",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000ffffff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"5cf12a1c",
version => x"00000002",
date => x"20140417",
name => "SPI-FLASH-16M-MMAP ")));
begin
result.sdb_component.addr_last := std_logic_vector(to_unsigned(2**g_bits-1, 64));
return result;
end f_wb_spi_flash_sdb;
end wishbone_pkg;
|
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture RTL;
-- This should not fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture RTL;
|
----------------------------------------------------------------------
-- brdLexSwx (for Fusion Embeded Dev Kit )
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end brdLexSwx;
----------------------------------------------------------------------
architecture rtl of brdLexSwx is
begin
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
o_lex <= '1';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
o_pbx <= '0';
end rtl; |
architecture RTL of ErrorBit is
signal ErrorBitSet : STD_LOGIC;
begin
ErrorInd: process (Clk_i, Reset_i_n, ErrorReset_i)
begin
if (Reset_i_n ='0') then
ErrorBitSet <= '0';
elsif(rising_edge(Clk_i)) then
if (ErrorReset_i = '1') then
ErrorBitSet <= '0';
else
-- hold status
if(ErrorBitSet ='1') then
ErrorBitSet <= ErrorBitSet;
-- only set error if getting error from input
elsif ((ErrorBitSet ='0')) then
if (ErrorBit_i ='1') then
ErrorBitSet <= '1';
else
ErrorBitSet <= '0';
end if;
end if;
end if;
end if;
end process ErrorInd;
ErrorIndicatorBit_o <= ErrorBitSet;
end RTL;
|
entity toplevel2 is
generic (
I : integer;
S : string );
end entity;
architecture test of toplevel2 is
begin
process is
begin
assert I = integer'value(S);
wait;
end process;
end architecture;
|
entity toplevel2 is
generic (
I : integer;
S : string );
end entity;
architecture test of toplevel2 is
begin
process is
begin
assert I = integer'value(S);
wait;
end process;
end architecture;
|
entity toplevel2 is
generic (
I : integer;
S : string );
end entity;
architecture test of toplevel2 is
begin
process is
begin
assert I = integer'value(S);
wait;
end process;
end architecture;
|
entity toplevel2 is
generic (
I : integer;
S : string );
end entity;
architecture test of toplevel2 is
begin
process is
begin
assert I = integer'value(S);
wait;
end process;
end architecture;
|
entity toplevel2 is
generic (
I : integer;
S : string );
end entity;
architecture test of toplevel2 is
begin
process is
begin
assert I = integer'value(S);
wait;
end process;
end architecture;
|
-- $Id: pdp11_mmu.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_mmu - syn
-- Description: pdp11: mmu - memory management unit
--
-- Dependencies: pdp11_mmu_sadr
-- pdp11_mmu_ssr12
-- ibus/ib_sres_or_3
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.4.2 now numeric_std clean
-- 2010-10-23 335 1.4.1 use ib_sel
-- 2010-10-17 333 1.4 use ibus V2 interface
-- 2010-06-20 307 1.3.7 rename cpacc to cacc in mmu_cntl_type
-- 2009-05-30 220 1.3.6 final removal of snoopers (were already commented)
-- 2009-05-09 213 1.3.5 BUGFIX: tie inst_compl permanentely '0'
-- BUGFIX: set ssr0 trap_mmu even when traps disabled
-- 2008-08-22 161 1.3.4 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
-- 2008-04-27 139 1.3.3 allow ssr1/2 tracing even with mmu_ena=0
-- 2008-04-25 138 1.3.2 add BRESET port, clear ssr0/3 with BRESET
-- 2008-03-02 121 1.3.1 remove snoopers
-- 2008-02-24 119 1.3 return always mapped address in PADDRH; remove
-- cpacc handling; PADDR generation now on _vmbox
-- 2008-01-05 110 1.2.1 rename _mmu_regs -> _mmu_sadr
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2008-01-01 109 1.2 use pdp11_mmu_regs (rather than _regset)
-- 2007-12-31 108 1.1.1 remove SADR memory address mux (-> _mmu_regfile)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_mmu is -- mmu - memory management unit
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CNTL : in mmu_cntl_type; -- control port
VADDR : in slv16; -- virtual address
MONI : in mmu_moni_type; -- monitor port
STAT : out mmu_stat_type; -- status port
PADDRH : out slv16; -- physical address (upper 16 bit)
IB_MREQ: in ib_mreq_type; -- ibus request
IB_SRES: out ib_sres_type -- ibus response
);
end pdp11_mmu;
architecture syn of pdp11_mmu is
constant ibaddr_ssr0 : slv16 := slv(to_unsigned(8#177572#,16));
constant ibaddr_ssr3 : slv16 := slv(to_unsigned(8#172516#,16));
constant ssr0_ibf_abo_nonres : integer := 15;
constant ssr0_ibf_abo_length : integer := 14;
constant ssr0_ibf_abo_rdonly : integer := 13;
constant ssr0_ibf_trap_mmu : integer := 12;
constant ssr0_ibf_ena_trap : integer := 9;
constant ssr0_ibf_inst_compl : integer := 7;
subtype ssr0_ibf_seg_mode is integer range 6 downto 5;
constant ssr0_ibf_dspace : integer := 4;
subtype ssr0_ibf_seg_num is integer range 3 downto 1;
constant ssr0_ibf_ena_mmu : integer := 0;
constant ssr3_ibf_ena_ubmap : integer := 5;
constant ssr3_ibf_ena_22bit : integer := 4;
constant ssr3_ibf_dspace_km : integer := 2;
constant ssr3_ibf_dspace_sm : integer := 1;
constant ssr3_ibf_dspace_um : integer := 0;
signal IBSEL_SSR0 : slbit := '0'; -- ibus select SSR0
signal IBSEL_SSR3 : slbit := '0'; -- ibus select SSR3
signal R_SSR0 : mmu_ssr0_type := mmu_ssr0_init;
signal N_SSR0 : mmu_ssr0_type := mmu_ssr0_init;
signal R_SSR3 : mmu_ssr3_type := mmu_ssr3_init;
signal ASN : slv4 := "0000"; -- augmented segment number (1+3 bit)
signal AIB_WE : slbit := '0'; -- update AIB
signal AIB_SETA : slbit := '0'; -- set A bit in access information bits
signal AIB_SETW : slbit := '0'; -- set W bit in access information bits
signal TRACE : slbit := '0'; -- enable tracing in ssr1/2
signal DSPACE : slbit := '0'; -- use dspace
signal IB_SRES_SADR : ib_sres_type := ib_sres_init;
signal IB_SRES_SSR12 : ib_sres_type := ib_sres_init;
signal IB_SRES_SSR03 : ib_sres_type := ib_sres_init;
signal SARSDR : sarsdr_type := sarsdr_init;
begin
SADR : pdp11_mmu_sadr port map (
CLK => CLK,
MODE => CNTL.mode,
ASN => ASN,
AIB_WE => AIB_WE,
AIB_SETA => AIB_SETA,
AIB_SETW => AIB_SETW,
SARSDR => SARSDR,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SADR);
SSR12 : pdp11_mmu_ssr12 port map (
CLK => CLK,
CRESET => CRESET,
TRACE => TRACE,
MONI => MONI,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SSR12);
SRES_OR : ib_sres_or_3
port map (
IB_SRES_1 => IB_SRES_SADR,
IB_SRES_2 => IB_SRES_SSR12,
IB_SRES_3 => IB_SRES_SSR03,
IB_SRES_OR => IB_SRES);
SEL_SSR0 : ib_sel
generic map (
IB_ADDR => ibaddr_ssr0)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SSR0
);
SEL_SSR3 : ib_sel
generic map (
IB_ADDR => ibaddr_ssr3)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SSR3
);
proc_ibres : process (IBSEL_SSR0, IBSEL_SSR3, IB_MREQ, R_SSR0, R_SSR3)
variable ssr0out : slv16 := (others=>'0');
variable ssr3out : slv16 := (others=>'0');
begin
ssr0out := (others=>'0');
if IBSEL_SSR0 = '1' then
ssr0out(ssr0_ibf_abo_nonres) := R_SSR0.abo_nonres;
ssr0out(ssr0_ibf_abo_length) := R_SSR0.abo_length;
ssr0out(ssr0_ibf_abo_rdonly) := R_SSR0.abo_rdonly;
ssr0out(ssr0_ibf_trap_mmu) := R_SSR0.trap_mmu;
ssr0out(ssr0_ibf_ena_trap) := R_SSR0.ena_trap;
ssr0out(ssr0_ibf_inst_compl) := R_SSR0.inst_compl;
ssr0out(ssr0_ibf_seg_mode) := R_SSR0.seg_mode;
ssr0out(ssr0_ibf_dspace) := R_SSR0.dspace;
ssr0out(ssr0_ibf_seg_num) := R_SSR0.seg_num;
ssr0out(ssr0_ibf_ena_mmu) := R_SSR0.ena_mmu;
end if;
ssr3out := (others=>'0');
if IBSEL_SSR3 = '1' then
ssr3out(ssr3_ibf_ena_ubmap) := R_SSR3.ena_ubmap;
ssr3out(ssr3_ibf_ena_22bit) := R_SSR3.ena_22bit;
ssr3out(ssr3_ibf_dspace_km) := R_SSR3.dspace_km;
ssr3out(ssr3_ibf_dspace_sm) := R_SSR3.dspace_sm;
ssr3out(ssr3_ibf_dspace_um) := R_SSR3.dspace_um;
end if;
IB_SRES_SSR03.dout <= ssr0out or ssr3out;
IB_SRES_SSR03.ack <= (IBSEL_SSR0 or IBSEL_SSR3) and
(IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_SSR03.busy <= '0';
end process proc_ibres;
proc_ssr0 : process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_SSR0 <= mmu_ssr0_init;
else
R_SSR0 <= N_SSR0;
end if;
end if;
end process proc_ssr0;
proc_ssr3 : process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_SSR3 <= mmu_ssr3_init;
elsif IBSEL_SSR3='1' and IB_MREQ.we='1' then
if IB_MREQ.be0 = '1' then
R_SSR3.ena_ubmap <= IB_MREQ.din(ssr3_ibf_ena_ubmap);
R_SSR3.ena_22bit <= IB_MREQ.din(ssr3_ibf_ena_22bit);
R_SSR3.dspace_km <= IB_MREQ.din(ssr3_ibf_dspace_km);
R_SSR3.dspace_sm <= IB_MREQ.din(ssr3_ibf_dspace_sm);
R_SSR3.dspace_um <= IB_MREQ.din(ssr3_ibf_dspace_um);
end if;
end if;
end if;
end process proc_ssr3;
proc_paddr : process (R_SSR0, R_SSR3, CNTL, SARSDR, VADDR)
variable ipaddrh : slv16 := (others=>'0');
variable dspace_ok : slbit := '0';
variable dspace_en : slbit := '0';
variable asf : slv3 := (others=>'0'); -- va: active segment field
variable bn : slv7 := (others=>'0'); -- va: block number
variable iasn : slv4 := (others=>'0');-- augmented segment number
begin
asf := VADDR(15 downto 13);
bn := VADDR(12 downto 6);
dspace_en := '0';
case CNTL.mode is
when "00" => dspace_en := R_SSR3.dspace_km;
when "01" => dspace_en := R_SSR3.dspace_sm;
when "11" => dspace_en := R_SSR3.dspace_um;
when others => null;
end case;
dspace_ok := CNTL.dspace and dspace_en;
iasn(3) := dspace_ok;
iasn(2 downto 0) := asf;
ipaddrh := slv(unsigned("000000000"&bn) + unsigned(SARSDR.saf));
DSPACE <= dspace_ok;
ASN <= iasn;
PADDRH <= ipaddrh;
end process proc_paddr;
proc_nssr0 : process (R_SSR0, R_SSR3, IB_MREQ, IBSEL_SSR0, DSPACE,
CNTL, MONI, SARSDR, VADDR)
variable nssr0 : mmu_ssr0_type := mmu_ssr0_init;
variable asf : slv3 := (others=>'0');
variable bn : slv7 := (others=>'0');
variable abo_nonres : slbit := '0';
variable abo_length : slbit := '0';
variable abo_rdonly : slbit := '0';
variable ssr_freeze : slbit := '0';
variable doabort : slbit := '0';
variable dotrap : slbit := '0';
variable dotrace : slbit := '0';
begin
nssr0 := R_SSR0;
AIB_WE <= '0';
AIB_SETA <= '0';
AIB_SETW <= '0';
ssr_freeze := R_SSR0.abo_nonres or R_SSR0.abo_length or R_SSR0.abo_rdonly;
dotrace := not(CNTL.cacc or ssr_freeze);
asf := VADDR(15 downto 13);
bn := VADDR(12 downto 6);
abo_nonres := '0';
abo_length := '0';
abo_rdonly := '0';
doabort := '0';
dotrap := '0';
if SARSDR.ed = '0' then -- ed=0: upward expansion
if unsigned(bn) > unsigned(SARSDR.slf) then
abo_length := '1';
end if;
else -- ed=0: downward expansion
if unsigned(bn) < unsigned(SARSDR.slf) then
abo_length := '1';
end if;
end if;
case SARSDR.acf is -- evaluate accecc control field
when "000" => -- segment non-resident
abo_nonres := '1';
when "001" => -- read-only; trap on read
if CNTL.wacc='1' or CNTL.macc='1' then
abo_rdonly := '1';
end if;
dotrap := '1';
when "010" => -- read-only
if CNTL.wacc='1' or CNTL.macc='1' then
abo_rdonly := '1';
end if;
when "100" => -- read/write; trap on read&write
dotrap := '1';
when "101" => -- read/write; trap on write
dotrap := CNTL.wacc or CNTL.macc;
when "110" => null; -- read/write;
when others => -- unused codes: abort access
abo_nonres := '1';
end case;
if IBSEL_SSR0='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
nssr0.abo_nonres := IB_MREQ.din(ssr0_ibf_abo_nonres);
nssr0.abo_length := IB_MREQ.din(ssr0_ibf_abo_length);
nssr0.abo_rdonly := IB_MREQ.din(ssr0_ibf_abo_rdonly);
nssr0.trap_mmu := IB_MREQ.din(ssr0_ibf_trap_mmu);
nssr0.ena_trap := IB_MREQ.din(ssr0_ibf_ena_trap);
end if;
if IB_MREQ.be0 = '1' then
nssr0.ena_mmu := IB_MREQ.din(ssr0_ibf_ena_mmu);
end if;
elsif nssr0.ena_mmu='1' and CNTL.cacc='0' then
if dotrace = '1' then
if MONI.istart = '1' then
nssr0.inst_compl := '0';
elsif MONI.idone = '1' then
nssr0.inst_compl := '0'; -- disable instr.compl logic
end if;
end if;
if CNTL.req = '1' then
AIB_WE <= '1';
if ssr_freeze = '0' then
nssr0.abo_nonres := abo_nonres;
nssr0.abo_length := abo_length;
nssr0.abo_rdonly := abo_rdonly;
end if;
doabort := abo_nonres or abo_length or abo_rdonly;
if doabort = '0' then
AIB_SETA <= '1';
AIB_SETW <= CNTL.wacc or CNTL.macc;
end if;
if ssr_freeze = '0' then
nssr0.dspace := DSPACE;
nssr0.seg_num := asf;
nssr0.seg_mode := CNTL.mode;
end if;
end if;
end if;
if CNTL.req='1' and R_SSR0.ena_mmu='1' and CNTL.cacc='0' and
dotrap='1' then
nssr0.trap_mmu := '1';
end if;
nssr0.trace_prev := dotrace;
if MONI.trace_prev = '0' then
TRACE <= dotrace;
else
TRACE <= R_SSR0.trace_prev;
end if;
N_SSR0 <= nssr0;
if R_SSR0.ena_mmu='1' and CNTL.cacc='0' then
STAT.vaok <= not doabort;
else
STAT.vaok <= '1';
end if;
if R_SSR0.ena_mmu='1' and CNTL.cacc='0' and doabort='0' and
R_SSR0.ena_trap='1' and R_SSR0.trap_mmu='0' and dotrap='1' then
STAT.trap <= '1';
else
STAT.trap <= '0';
end if;
STAT.ena_mmu <= R_SSR0.ena_mmu;
STAT.ena_22bit <= R_SSR3.ena_22bit;
STAT.ena_ubmap <= R_SSR3.ena_ubmap;
end process proc_nssr0;
end syn;
|
-- $Id: pdp11_mmu.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_mmu - syn
-- Description: pdp11: mmu - memory management unit
--
-- Dependencies: pdp11_mmu_sadr
-- pdp11_mmu_ssr12
-- ibus/ib_sres_or_3
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.4.2 now numeric_std clean
-- 2010-10-23 335 1.4.1 use ib_sel
-- 2010-10-17 333 1.4 use ibus V2 interface
-- 2010-06-20 307 1.3.7 rename cpacc to cacc in mmu_cntl_type
-- 2009-05-30 220 1.3.6 final removal of snoopers (were already commented)
-- 2009-05-09 213 1.3.5 BUGFIX: tie inst_compl permanentely '0'
-- BUGFIX: set ssr0 trap_mmu even when traps disabled
-- 2008-08-22 161 1.3.4 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
-- 2008-04-27 139 1.3.3 allow ssr1/2 tracing even with mmu_ena=0
-- 2008-04-25 138 1.3.2 add BRESET port, clear ssr0/3 with BRESET
-- 2008-03-02 121 1.3.1 remove snoopers
-- 2008-02-24 119 1.3 return always mapped address in PADDRH; remove
-- cpacc handling; PADDR generation now on _vmbox
-- 2008-01-05 110 1.2.1 rename _mmu_regs -> _mmu_sadr
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2008-01-01 109 1.2 use pdp11_mmu_regs (rather than _regset)
-- 2007-12-31 108 1.1.1 remove SADR memory address mux (-> _mmu_regfile)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_mmu is -- mmu - memory management unit
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CNTL : in mmu_cntl_type; -- control port
VADDR : in slv16; -- virtual address
MONI : in mmu_moni_type; -- monitor port
STAT : out mmu_stat_type; -- status port
PADDRH : out slv16; -- physical address (upper 16 bit)
IB_MREQ: in ib_mreq_type; -- ibus request
IB_SRES: out ib_sres_type -- ibus response
);
end pdp11_mmu;
architecture syn of pdp11_mmu is
constant ibaddr_ssr0 : slv16 := slv(to_unsigned(8#177572#,16));
constant ibaddr_ssr3 : slv16 := slv(to_unsigned(8#172516#,16));
constant ssr0_ibf_abo_nonres : integer := 15;
constant ssr0_ibf_abo_length : integer := 14;
constant ssr0_ibf_abo_rdonly : integer := 13;
constant ssr0_ibf_trap_mmu : integer := 12;
constant ssr0_ibf_ena_trap : integer := 9;
constant ssr0_ibf_inst_compl : integer := 7;
subtype ssr0_ibf_seg_mode is integer range 6 downto 5;
constant ssr0_ibf_dspace : integer := 4;
subtype ssr0_ibf_seg_num is integer range 3 downto 1;
constant ssr0_ibf_ena_mmu : integer := 0;
constant ssr3_ibf_ena_ubmap : integer := 5;
constant ssr3_ibf_ena_22bit : integer := 4;
constant ssr3_ibf_dspace_km : integer := 2;
constant ssr3_ibf_dspace_sm : integer := 1;
constant ssr3_ibf_dspace_um : integer := 0;
signal IBSEL_SSR0 : slbit := '0'; -- ibus select SSR0
signal IBSEL_SSR3 : slbit := '0'; -- ibus select SSR3
signal R_SSR0 : mmu_ssr0_type := mmu_ssr0_init;
signal N_SSR0 : mmu_ssr0_type := mmu_ssr0_init;
signal R_SSR3 : mmu_ssr3_type := mmu_ssr3_init;
signal ASN : slv4 := "0000"; -- augmented segment number (1+3 bit)
signal AIB_WE : slbit := '0'; -- update AIB
signal AIB_SETA : slbit := '0'; -- set A bit in access information bits
signal AIB_SETW : slbit := '0'; -- set W bit in access information bits
signal TRACE : slbit := '0'; -- enable tracing in ssr1/2
signal DSPACE : slbit := '0'; -- use dspace
signal IB_SRES_SADR : ib_sres_type := ib_sres_init;
signal IB_SRES_SSR12 : ib_sres_type := ib_sres_init;
signal IB_SRES_SSR03 : ib_sres_type := ib_sres_init;
signal SARSDR : sarsdr_type := sarsdr_init;
begin
SADR : pdp11_mmu_sadr port map (
CLK => CLK,
MODE => CNTL.mode,
ASN => ASN,
AIB_WE => AIB_WE,
AIB_SETA => AIB_SETA,
AIB_SETW => AIB_SETW,
SARSDR => SARSDR,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SADR);
SSR12 : pdp11_mmu_ssr12 port map (
CLK => CLK,
CRESET => CRESET,
TRACE => TRACE,
MONI => MONI,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SSR12);
SRES_OR : ib_sres_or_3
port map (
IB_SRES_1 => IB_SRES_SADR,
IB_SRES_2 => IB_SRES_SSR12,
IB_SRES_3 => IB_SRES_SSR03,
IB_SRES_OR => IB_SRES);
SEL_SSR0 : ib_sel
generic map (
IB_ADDR => ibaddr_ssr0)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SSR0
);
SEL_SSR3 : ib_sel
generic map (
IB_ADDR => ibaddr_ssr3)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SSR3
);
proc_ibres : process (IBSEL_SSR0, IBSEL_SSR3, IB_MREQ, R_SSR0, R_SSR3)
variable ssr0out : slv16 := (others=>'0');
variable ssr3out : slv16 := (others=>'0');
begin
ssr0out := (others=>'0');
if IBSEL_SSR0 = '1' then
ssr0out(ssr0_ibf_abo_nonres) := R_SSR0.abo_nonres;
ssr0out(ssr0_ibf_abo_length) := R_SSR0.abo_length;
ssr0out(ssr0_ibf_abo_rdonly) := R_SSR0.abo_rdonly;
ssr0out(ssr0_ibf_trap_mmu) := R_SSR0.trap_mmu;
ssr0out(ssr0_ibf_ena_trap) := R_SSR0.ena_trap;
ssr0out(ssr0_ibf_inst_compl) := R_SSR0.inst_compl;
ssr0out(ssr0_ibf_seg_mode) := R_SSR0.seg_mode;
ssr0out(ssr0_ibf_dspace) := R_SSR0.dspace;
ssr0out(ssr0_ibf_seg_num) := R_SSR0.seg_num;
ssr0out(ssr0_ibf_ena_mmu) := R_SSR0.ena_mmu;
end if;
ssr3out := (others=>'0');
if IBSEL_SSR3 = '1' then
ssr3out(ssr3_ibf_ena_ubmap) := R_SSR3.ena_ubmap;
ssr3out(ssr3_ibf_ena_22bit) := R_SSR3.ena_22bit;
ssr3out(ssr3_ibf_dspace_km) := R_SSR3.dspace_km;
ssr3out(ssr3_ibf_dspace_sm) := R_SSR3.dspace_sm;
ssr3out(ssr3_ibf_dspace_um) := R_SSR3.dspace_um;
end if;
IB_SRES_SSR03.dout <= ssr0out or ssr3out;
IB_SRES_SSR03.ack <= (IBSEL_SSR0 or IBSEL_SSR3) and
(IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_SSR03.busy <= '0';
end process proc_ibres;
proc_ssr0 : process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_SSR0 <= mmu_ssr0_init;
else
R_SSR0 <= N_SSR0;
end if;
end if;
end process proc_ssr0;
proc_ssr3 : process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_SSR3 <= mmu_ssr3_init;
elsif IBSEL_SSR3='1' and IB_MREQ.we='1' then
if IB_MREQ.be0 = '1' then
R_SSR3.ena_ubmap <= IB_MREQ.din(ssr3_ibf_ena_ubmap);
R_SSR3.ena_22bit <= IB_MREQ.din(ssr3_ibf_ena_22bit);
R_SSR3.dspace_km <= IB_MREQ.din(ssr3_ibf_dspace_km);
R_SSR3.dspace_sm <= IB_MREQ.din(ssr3_ibf_dspace_sm);
R_SSR3.dspace_um <= IB_MREQ.din(ssr3_ibf_dspace_um);
end if;
end if;
end if;
end process proc_ssr3;
proc_paddr : process (R_SSR0, R_SSR3, CNTL, SARSDR, VADDR)
variable ipaddrh : slv16 := (others=>'0');
variable dspace_ok : slbit := '0';
variable dspace_en : slbit := '0';
variable asf : slv3 := (others=>'0'); -- va: active segment field
variable bn : slv7 := (others=>'0'); -- va: block number
variable iasn : slv4 := (others=>'0');-- augmented segment number
begin
asf := VADDR(15 downto 13);
bn := VADDR(12 downto 6);
dspace_en := '0';
case CNTL.mode is
when "00" => dspace_en := R_SSR3.dspace_km;
when "01" => dspace_en := R_SSR3.dspace_sm;
when "11" => dspace_en := R_SSR3.dspace_um;
when others => null;
end case;
dspace_ok := CNTL.dspace and dspace_en;
iasn(3) := dspace_ok;
iasn(2 downto 0) := asf;
ipaddrh := slv(unsigned("000000000"&bn) + unsigned(SARSDR.saf));
DSPACE <= dspace_ok;
ASN <= iasn;
PADDRH <= ipaddrh;
end process proc_paddr;
proc_nssr0 : process (R_SSR0, R_SSR3, IB_MREQ, IBSEL_SSR0, DSPACE,
CNTL, MONI, SARSDR, VADDR)
variable nssr0 : mmu_ssr0_type := mmu_ssr0_init;
variable asf : slv3 := (others=>'0');
variable bn : slv7 := (others=>'0');
variable abo_nonres : slbit := '0';
variable abo_length : slbit := '0';
variable abo_rdonly : slbit := '0';
variable ssr_freeze : slbit := '0';
variable doabort : slbit := '0';
variable dotrap : slbit := '0';
variable dotrace : slbit := '0';
begin
nssr0 := R_SSR0;
AIB_WE <= '0';
AIB_SETA <= '0';
AIB_SETW <= '0';
ssr_freeze := R_SSR0.abo_nonres or R_SSR0.abo_length or R_SSR0.abo_rdonly;
dotrace := not(CNTL.cacc or ssr_freeze);
asf := VADDR(15 downto 13);
bn := VADDR(12 downto 6);
abo_nonres := '0';
abo_length := '0';
abo_rdonly := '0';
doabort := '0';
dotrap := '0';
if SARSDR.ed = '0' then -- ed=0: upward expansion
if unsigned(bn) > unsigned(SARSDR.slf) then
abo_length := '1';
end if;
else -- ed=0: downward expansion
if unsigned(bn) < unsigned(SARSDR.slf) then
abo_length := '1';
end if;
end if;
case SARSDR.acf is -- evaluate accecc control field
when "000" => -- segment non-resident
abo_nonres := '1';
when "001" => -- read-only; trap on read
if CNTL.wacc='1' or CNTL.macc='1' then
abo_rdonly := '1';
end if;
dotrap := '1';
when "010" => -- read-only
if CNTL.wacc='1' or CNTL.macc='1' then
abo_rdonly := '1';
end if;
when "100" => -- read/write; trap on read&write
dotrap := '1';
when "101" => -- read/write; trap on write
dotrap := CNTL.wacc or CNTL.macc;
when "110" => null; -- read/write;
when others => -- unused codes: abort access
abo_nonres := '1';
end case;
if IBSEL_SSR0='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
nssr0.abo_nonres := IB_MREQ.din(ssr0_ibf_abo_nonres);
nssr0.abo_length := IB_MREQ.din(ssr0_ibf_abo_length);
nssr0.abo_rdonly := IB_MREQ.din(ssr0_ibf_abo_rdonly);
nssr0.trap_mmu := IB_MREQ.din(ssr0_ibf_trap_mmu);
nssr0.ena_trap := IB_MREQ.din(ssr0_ibf_ena_trap);
end if;
if IB_MREQ.be0 = '1' then
nssr0.ena_mmu := IB_MREQ.din(ssr0_ibf_ena_mmu);
end if;
elsif nssr0.ena_mmu='1' and CNTL.cacc='0' then
if dotrace = '1' then
if MONI.istart = '1' then
nssr0.inst_compl := '0';
elsif MONI.idone = '1' then
nssr0.inst_compl := '0'; -- disable instr.compl logic
end if;
end if;
if CNTL.req = '1' then
AIB_WE <= '1';
if ssr_freeze = '0' then
nssr0.abo_nonres := abo_nonres;
nssr0.abo_length := abo_length;
nssr0.abo_rdonly := abo_rdonly;
end if;
doabort := abo_nonres or abo_length or abo_rdonly;
if doabort = '0' then
AIB_SETA <= '1';
AIB_SETW <= CNTL.wacc or CNTL.macc;
end if;
if ssr_freeze = '0' then
nssr0.dspace := DSPACE;
nssr0.seg_num := asf;
nssr0.seg_mode := CNTL.mode;
end if;
end if;
end if;
if CNTL.req='1' and R_SSR0.ena_mmu='1' and CNTL.cacc='0' and
dotrap='1' then
nssr0.trap_mmu := '1';
end if;
nssr0.trace_prev := dotrace;
if MONI.trace_prev = '0' then
TRACE <= dotrace;
else
TRACE <= R_SSR0.trace_prev;
end if;
N_SSR0 <= nssr0;
if R_SSR0.ena_mmu='1' and CNTL.cacc='0' then
STAT.vaok <= not doabort;
else
STAT.vaok <= '1';
end if;
if R_SSR0.ena_mmu='1' and CNTL.cacc='0' and doabort='0' and
R_SSR0.ena_trap='1' and R_SSR0.trap_mmu='0' and dotrap='1' then
STAT.trap <= '1';
else
STAT.trap <= '0';
end if;
STAT.ena_mmu <= R_SSR0.ena_mmu;
STAT.ena_22bit <= R_SSR3.ena_22bit;
STAT.ena_ubmap <= R_SSR3.ena_ubmap;
end process proc_nssr0;
end syn;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:29:34 07/31/2013
-- Design Name:
-- Module Name: wishbone_register - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_wishbone_peripherals_pack.all ;
entity wishbone_register is
generic(
wb_addr_size : natural := 16; -- Address port size for wishbone
wb_size : natural := 16; -- Data port size for wishbone
nb_regs : natural := 1
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_addr_size-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
reg_out : out slv16_array(0 to nb_regs-1);
reg_in : in slv16_array(0 to nb_regs-1)
);
end wishbone_register;
architecture Behavioral of wishbone_register is
signal reg_in_d, reg_out_d : slv16_array(0 to nb_regs-1) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg_out_d <= (others =>(others => '0'));
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
reg_out_d(conv_integer(wbs_address)) <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
reg_out <= reg_out_d ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
reg_in_d <= reg_in ; -- latching inputs
wbs_readdata <= reg_in_d(conv_integer(wbs_address)) ; -- this is not clear if this should only happen in the read part
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
|
-- $Id: iob_reg_o_gen.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_o_gen - syn
-- Description: Registered IOB, output only, vector
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_o_gen is -- registered IOB, output, vector
generic (
DWIDTH : positive := 16; -- data port width
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slv(DWIDTH-1 downto 0); -- output data
PAD : out slv(DWIDTH-1 downto 0) -- i/o pad
);
end iob_reg_o_gen;
architecture syn of iob_reg_o_gen is
signal R_DO : slv(DWIDTH-1 downto 0) := (others=>INIT);
attribute iob : string;
attribute iob of R_DO : signal is "true";
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if CE = '1' then
R_DO <= DO;
end if;
end if;
end process proc_regs;
PAD <= R_DO;
end syn;
|
-- $Id: iob_reg_o_gen.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_o_gen - syn
-- Description: Registered IOB, output only, vector
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_o_gen is -- registered IOB, output, vector
generic (
DWIDTH : positive := 16; -- data port width
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slv(DWIDTH-1 downto 0); -- output data
PAD : out slv(DWIDTH-1 downto 0) -- i/o pad
);
end iob_reg_o_gen;
architecture syn of iob_reg_o_gen is
signal R_DO : slv(DWIDTH-1 downto 0) := (others=>INIT);
attribute iob : string;
attribute iob of R_DO : signal is "true";
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if CE = '1' then
R_DO <= DO;
end if;
end if;
end process proc_regs;
PAD <= R_DO;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
entity decode2alu_reg is
port(
clk, rst: in std_logic;
noop : in std_logic;
A_in : in std_logic_vector(7 downto 0);
B_in : in std_logic_vector(7 downto 0);
operation_in : in std_logic_vector(4 downto 0);
Raddr1_in : in std_logic_vector(3 downto 0);
Raddr2_in : in std_logic_vector(3 downto 0);
Memaddr_in : in std_logic_vector(7 downto 0);
src_select: in std_logic_vector(1 downto 0);
ALU_result: in std_logic_vector(7 downto 0);
A_out : out std_logic_vector(7 downto 0);
B_out : out std_logic_vector(7 downto 0);
operation_out : out std_logic_vector(4 downto 0);
Raddr1_out : out std_logic_vector(3 downto 0);
Raddr2_out : out std_logic_vector(3 downto 0);
Memaddr_out : out std_logic_vector(7 downto 0)
);
end decode2alu_reg;
architecture mixed of decode2alu_reg is
begin
process(clk,rst)
begin
if (rst = '1') then
A_out <= X"00";
B_out <= X"00";
operation_out <= "00000";
Raddr1_out <= X"0";
Raddr2_out <= X"0";
Memaddr_out <= X"00";
elsif rising_edge(clk) then
if (noop = '1') then
A_out <= X"00";
B_out <= X"00";
operation_out <= "00000";
Raddr1_out <= X"0";
Raddr2_out <= X"0";
Memaddr_out <= X"00";
else
if (src_select(0) = '0') then
A_out <= A_in;
else
A_out <= ALU_result;
end if;
if (src_select(1) = '0') then
B_out <= B_in;
else
B_out <= ALU_result;
end if;
operation_out <= operation_in;
Raddr1_out <= Raddr1_in;
Raddr2_out <= Raddr2_in;
Memaddr_out <= Memaddr_in;
end if;
end if;
end process;
end mixed;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:04:14 01/22/2014
-- Design Name:
-- Module Name: /home/tejainece/learnings/xilinx/Multiply16Booth4/Multiply16Booth4_tb.vhd
-- Project Name: Multiply16Booth4
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Multiply16Booth4
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Multiply16Booth4_tb IS
END Multiply16Booth4_tb;
ARCHITECTURE behavior OF Multiply16Booth4_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Multiply16Booth4
PORT(
a : IN std_logic_vector(15 downto 0);
b : IN std_logic_vector(15 downto 0);
o : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(15 downto 0) := (others => '0');
signal b : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal o : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Multiply16Booth4 PORT MAP (
a => a,
b => b,
o => o
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
--a <= "0110101010101010";
--b <= "0000000000100000";
a <= "0100001001000000";
b <= "0101111111000000";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.49d
-- \ \ Application: netgen
-- / / Filename: mbuf_128x72.vhd
-- /___/ /\ Timestamp: Thu Feb 21 12:33:55 2013
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/mbuf_128x72.ngc /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/mbuf_128x72.vhd
-- Device : 7a200tffg1156-2
-- Input file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/mbuf_128x72.ngc
-- Output file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/mbuf_128x72.vhd
-- # of Entities : 2
-- Design Name : mbuf_128x72
-- Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity reset_builtin1 is
port (
CLK : in STD_LOGIC := 'X';
WR_CLK : in STD_LOGIC := 'X';
RD_CLK : in STD_LOGIC := 'X';
INT_CLK : in STD_LOGIC := 'X';
RST : in STD_LOGIC := 'X';
WR_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
RD_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
INT_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end reset_builtin1;
architecture STRUCTURE of reset_builtin1 is
signal wr_rst_reg_2 : STD_LOGIC;
signal wr_rst_reg_GND_25_o_MUX_1_o : STD_LOGIC;
signal wr_rst_fb : STD_LOGIC_VECTOR ( 4 downto 0 );
signal power_on_wr_rst : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NlwRenamedSignal_RD_RST_I : STD_LOGIC_VECTOR ( 0 downto 0 );
signal NlwRenamedSig_OI_n0013 : STD_LOGIC_VECTOR ( 5 downto 5 );
begin
WR_RST_I(1) <= NlwRenamedSignal_RD_RST_I(0);
WR_RST_I(0) <= NlwRenamedSignal_RD_RST_I(0);
RD_RST_I(1) <= NlwRenamedSignal_RD_RST_I(0);
RD_RST_I(0) <= NlwRenamedSignal_RD_RST_I(0);
INT_RST_I(1) <= NlwRenamedSig_OI_n0013(5);
INT_RST_I(0) <= NlwRenamedSig_OI_n0013(5);
XST_GND : GND
port map (
G => NlwRenamedSig_OI_n0013(5)
);
power_on_wr_rst_0 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(1),
Q => power_on_wr_rst(0)
);
power_on_wr_rst_1 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(2),
Q => power_on_wr_rst(1)
);
power_on_wr_rst_2 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(3),
Q => power_on_wr_rst(2)
);
power_on_wr_rst_3 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(4),
Q => power_on_wr_rst(3)
);
power_on_wr_rst_4 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(5),
Q => power_on_wr_rst(4)
);
power_on_wr_rst_5 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => NlwRenamedSig_OI_n0013(5),
Q => power_on_wr_rst(5)
);
wr_rst_reg : FDP
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_reg_GND_25_o_MUX_1_o,
PRE => RST,
Q => wr_rst_reg_2
);
wr_rst_fb_0 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(1),
Q => wr_rst_fb(0)
);
wr_rst_fb_1 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(2),
Q => wr_rst_fb(1)
);
wr_rst_fb_2 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(3),
Q => wr_rst_fb(2)
);
wr_rst_fb_3 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(4),
Q => wr_rst_fb(3)
);
wr_rst_fb_4 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_reg_2,
Q => wr_rst_fb(4)
);
RD_RST_I_0_1 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wr_rst_reg_2,
I1 => power_on_wr_rst(0),
O => NlwRenamedSignal_RD_RST_I(0)
);
Mmux_wr_rst_reg_GND_25_o_MUX_1_o11 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => wr_rst_fb(0),
I1 => wr_rst_reg_2,
O => wr_rst_reg_GND_25_o_MUX_1_o
);
end STRUCTURE;
-- synthesis translate_on
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity mbuf_128x72 is
port (
clk : in STD_LOGIC := 'X';
rst : in STD_LOGIC := 'X';
wr_en : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
full : out STD_LOGIC;
empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 71 downto 0 );
dout : out STD_LOGIC_VECTOR ( 71 downto 0 )
);
end mbuf_128x72;
architecture STRUCTURE of mbuf_128x72 is
component reset_builtin1
port (
CLK : in STD_LOGIC := 'X';
WR_CLK : in STD_LOGIC := 'X';
RD_CLK : in STD_LOGIC := 'X';
INT_CLK : in STD_LOGIC := 'X';
RST : in STD_LOGIC := 'X';
WR_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
RD_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
INT_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component;
signal N1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_19 : STD_LOGIC;
signal NlwRenamedSig_OI_empty : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
empty <= NlwRenamedSig_OI_empty;
prog_full <= U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_19;
XST_GND : GND
port map (
G => N1
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt : reset_builtin1
port map (
CLK => clk,
WR_CLK => N1,
RD_CLK => N1,
INT_CLK => N1,
RST => rst,
WR_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_1_UNCONNECTED,
WR_RST_I(0) => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
RD_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_1_UNCONNECTED,
RD_RST_I(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_0_UNCONNECTED,
INT_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_1_UNCONNECTED,
INT_RST_I(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1 : FIFO36E1
generic map(
ALMOST_EMPTY_OFFSET => X"0002",
ALMOST_FULL_OFFSET => X"0180",
DATA_WIDTH => 72,
DO_REG => 0,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
EN_SYN => TRUE,
FIFO_MODE => "FIFO36_72",
FIRST_WORD_FALL_THROUGH => FALSE,
INIT => X"000000000000000000",
SIM_DEVICE => "7SERIES",
SRVAL => X"000000000000000000"
)
port map (
ALMOSTEMPTY =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED
,
ALMOSTFULL => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED,
EMPTY => NlwRenamedSig_OI_empty,
FULL => full,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
RDCLK => clk,
RDEN => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp,
RDERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED,
REGCE => N1,
RST => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
RSTREG => N1,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED,
WRCLK => clk,
WREN => wr_en,
WRERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED,
DI(63) => din(67),
DI(62) => din(66),
DI(61) => din(65),
DI(60) => din(64),
DI(59) => din(63),
DI(58) => din(62),
DI(57) => din(61),
DI(56) => din(60),
DI(55) => din(59),
DI(54) => din(58),
DI(53) => din(57),
DI(52) => din(56),
DI(51) => din(55),
DI(50) => din(54),
DI(49) => din(53),
DI(48) => din(52),
DI(47) => din(51),
DI(46) => din(50),
DI(45) => din(49),
DI(44) => din(48),
DI(43) => din(47),
DI(42) => din(46),
DI(41) => din(45),
DI(40) => din(44),
DI(39) => din(43),
DI(38) => din(42),
DI(37) => din(41),
DI(36) => din(40),
DI(35) => din(39),
DI(34) => din(38),
DI(33) => din(37),
DI(32) => din(36),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(7) => din(71),
DIP(6) => din(70),
DIP(5) => din(69),
DIP(4) => din(68),
DIP(3) => din(35),
DIP(2) => din(34),
DIP(1) => din(33),
DIP(0) => din(32),
DO(63) => dout(67),
DO(62) => dout(66),
DO(61) => dout(65),
DO(60) => dout(64),
DO(59) => dout(63),
DO(58) => dout(62),
DO(57) => dout(61),
DO(56) => dout(60),
DO(55) => dout(59),
DO(54) => dout(58),
DO(53) => dout(57),
DO(52) => dout(56),
DO(51) => dout(55),
DO(50) => dout(54),
DO(49) => dout(53),
DO(48) => dout(52),
DO(47) => dout(51),
DO(46) => dout(50),
DO(45) => dout(49),
DO(44) => dout(48),
DO(43) => dout(47),
DO(42) => dout(46),
DO(41) => dout(45),
DO(40) => dout(44),
DO(39) => dout(43),
DO(38) => dout(42),
DO(37) => dout(41),
DO(36) => dout(40),
DO(35) => dout(39),
DO(34) => dout(38),
DO(33) => dout(37),
DO(32) => dout(36),
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(7) => dout(71),
DOP(6) => dout(70),
DOP(5) => dout(69),
DOP(4) => dout(68),
DOP(3) => dout(35),
DOP(2) => dout(34),
DOP(1) => dout(33),
DOP(0) => dout(32),
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED
,
RDCOUNT(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED
,
RDCOUNT(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED
,
RDCOUNT(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED
,
RDCOUNT(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED
,
RDCOUNT(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED
,
RDCOUNT(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED
,
RDCOUNT(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED
,
RDCOUNT(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED
,
RDCOUNT(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED
,
RDCOUNT(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED
,
RDCOUNT(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED
,
RDCOUNT(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED
,
RDCOUNT(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED
,
WRCOUNT(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED
,
WRCOUNT(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED
,
WRCOUNT(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED
,
WRCOUNT(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED
,
WRCOUNT(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED
,
WRCOUNT(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED
,
WRCOUNT(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED
,
WRCOUNT(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED
,
WRCOUNT(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED
,
WRCOUNT(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED
,
WRCOUNT(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED
,
WRCOUNT(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED
,
WRCOUNT(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo,
Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_19
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_empty,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp
);
end STRUCTURE;
-- synthesis translate_on
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:22 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_rst_ps7_0_100M_0_stub.vhdl
-- Design : zynq_design_1_rst_ps7_0_100M_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2017.2";
begin
end;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_ed_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ed_e-rtl-conf-c.vhd,v 1.1 2004/04/06 10:50:53 wig Exp $
-- $Date: 2004/04/06 10:50:53 $
-- $Log: inst_ed_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:50:53 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_ed_e_rtl_conf / inst_ed_e
--
configuration inst_ed_e_rtl_conf of inst_ed_e is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_eda : inst_eda_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eda_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_edb : inst_edb_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_edb_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_ed_e_rtl_conf;
--
-- End of Generated Configuration inst_ed_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
------------------------------------------------------------------------------
-- @file {{ tb.file_name }}
-- @see {{ dut.name }}
-------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity {{ tb.name }} is
end;
architecture testbench of {{ tb.name }} is
{{ dut.component }}
{{ dut.signals }}
begin
{{ dut.instance }}
stimulus: process
begin
-- Put initialisation code here
-- Put test bench stimulus code here
wait;
end process;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: VHDL package for component declarations, types and functions
-- associated to the PoC.xil namespace
--
-- Description:
-- ------------------------------------
-- This package declares types and components for
-- - Xilinx ChipScope Pro IPCores (ICON, ILA, VIO)
-- - Xilinx Dynamic Reconfiguration Port (DRP) related types
-- - SystemMonitor for FPGA core temperature measurement and fan control
-- (see PoC.io.FanControl)
-- - Component declarations for Xilinx related modules
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
package xil is
-- ChipScope
-- ==========================================================================
subtype T_XIL_CHIPSCOPE_CONTROL is STD_LOGIC_VECTOR(35 downto 0);
type T_XIL_CHIPSCOPE_CONTROL_VECTOR is array (NATURAL range <>) of T_XIL_CHIPSCOPE_CONTROL;
-- Dynamic Reconfiguration Port (DRP)
-- ==========================================================================
subtype T_XIL_DRP_ADDRESS is T_SLV_16;
subtype T_XIL_DRP_DATA is T_SLV_16;
type T_XIL_DRP_ADDRESS_VECTOR is array (NATURAL range <>) of T_XIL_DRP_ADDRESS;
type T_XIL_DRP_DATA_VECTOR is array (NATURAL range <>) of T_XIL_DRP_DATA;
type T_XIL_DRP_BUS_IN is record
Clock : STD_LOGIC;
Enable : STD_LOGIC;
ReadWrite : STD_LOGIC;
Address : T_XIL_DRP_ADDRESS;
Data : T_XIL_DRP_DATA;
end record;
constant C_XIL_DRP_BUS_IN_EMPTY : T_XIL_DRP_BUS_IN := (
Clock => '0',
Enable => '0',
ReadWrite => '0',
Address => (others => '0'),
Data => (others => '0'));
type T_XIL_DRP_BUS_OUT is record
Data : T_XIL_DRP_DATA;
Ack : STD_LOGIC;
end record;
type T_XIL_DRP_CONFIG is record
Address : T_XIL_DRP_ADDRESS;
Mask : T_XIL_DRP_DATA;
Data : T_XIL_DRP_DATA;
end record;
-- define array indices
constant C_XIL_DRP_MAX_CONFIG_COUNT : POSITIVE := 8;
SUBtype T_XIL_DRP_CONFIG_INDEX IS INTEGER range 0 TO C_XIL_DRP_MAX_CONFIG_COUNT - 1;
type T_XIL_DRP_CONFIG_VECTOR is array (NATURAL range <>) of T_XIL_DRP_CONFIG;
type T_XIL_DRP_CONFIG_SET is record
Configs : T_XIL_DRP_CONFIG_VECTOR(T_XIL_DRP_CONFIG_INDEX);
LastIndex : T_XIL_DRP_CONFIG_INDEX;
end record;
type T_XIL_DRP_CONFIG_ROM is array (NATURAL range <>) of T_XIL_DRP_CONFIG_SET;
constant C_XIL_DRP_CONFIG_EMPTY : T_XIL_DRP_CONFIG := (
Address => (others => '0'),
Data => (others => '0'),
Mask => (others => '0')
);
constant C_XIL_DRP_CONFIG_SET_EMPTY : T_XIL_DRP_CONFIG_SET := (
Configs => (others => C_XIL_DRP_CONFIG_EMPTY),
LastIndex => 0
);
component xil_ChipScopeICON is
generic (
PORTS : POSITIVE
);
port (
ControlBus : inout T_XIL_CHIPSCOPE_CONTROL_VECTOR(PORTS - 1 downto 0)
);
end component;
component xil_SystemMonitor_Virtex6 is
port (
Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic
Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output
Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output
Alarm : out STD_LOGIC; -- OR'ed output of all the alarms
VP : in STD_LOGIC; -- Dedicated analog input pair
VN : in STD_LOGIC
);
end component;
component xil_SystemMonitor_Series7 is
port (
Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic
Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output
Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output
Alarm : out STD_LOGIC; -- OR'ed output of all the alarms
VP : in STD_LOGIC; -- Dedicated analog input pair
VN : in STD_LOGIC
);
end component;
end package;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: VHDL package for component declarations, types and functions
-- associated to the PoC.xil namespace
--
-- Description:
-- ------------------------------------
-- This package declares types and components for
-- - Xilinx ChipScope Pro IPCores (ICON, ILA, VIO)
-- - Xilinx Dynamic Reconfiguration Port (DRP) related types
-- - SystemMonitor for FPGA core temperature measurement and fan control
-- (see PoC.io.FanControl)
-- - Component declarations for Xilinx related modules
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
package xil is
-- ChipScope
-- ==========================================================================
subtype T_XIL_CHIPSCOPE_CONTROL is STD_LOGIC_VECTOR(35 downto 0);
type T_XIL_CHIPSCOPE_CONTROL_VECTOR is array (NATURAL range <>) of T_XIL_CHIPSCOPE_CONTROL;
-- Dynamic Reconfiguration Port (DRP)
-- ==========================================================================
subtype T_XIL_DRP_ADDRESS is T_SLV_16;
subtype T_XIL_DRP_DATA is T_SLV_16;
type T_XIL_DRP_ADDRESS_VECTOR is array (NATURAL range <>) of T_XIL_DRP_ADDRESS;
type T_XIL_DRP_DATA_VECTOR is array (NATURAL range <>) of T_XIL_DRP_DATA;
type T_XIL_DRP_BUS_IN is record
Clock : STD_LOGIC;
Enable : STD_LOGIC;
ReadWrite : STD_LOGIC;
Address : T_XIL_DRP_ADDRESS;
Data : T_XIL_DRP_DATA;
end record;
constant C_XIL_DRP_BUS_IN_EMPTY : T_XIL_DRP_BUS_IN := (
Clock => '0',
Enable => '0',
ReadWrite => '0',
Address => (others => '0'),
Data => (others => '0'));
type T_XIL_DRP_BUS_OUT is record
Data : T_XIL_DRP_DATA;
Ack : STD_LOGIC;
end record;
type T_XIL_DRP_CONFIG is record
Address : T_XIL_DRP_ADDRESS;
Mask : T_XIL_DRP_DATA;
Data : T_XIL_DRP_DATA;
end record;
-- define array indices
constant C_XIL_DRP_MAX_CONFIG_COUNT : POSITIVE := 8;
SUBtype T_XIL_DRP_CONFIG_INDEX IS INTEGER range 0 TO C_XIL_DRP_MAX_CONFIG_COUNT - 1;
type T_XIL_DRP_CONFIG_VECTOR is array (NATURAL range <>) of T_XIL_DRP_CONFIG;
type T_XIL_DRP_CONFIG_SET is record
Configs : T_XIL_DRP_CONFIG_VECTOR(T_XIL_DRP_CONFIG_INDEX);
LastIndex : T_XIL_DRP_CONFIG_INDEX;
end record;
type T_XIL_DRP_CONFIG_ROM is array (NATURAL range <>) of T_XIL_DRP_CONFIG_SET;
constant C_XIL_DRP_CONFIG_EMPTY : T_XIL_DRP_CONFIG := (
Address => (others => '0'),
Data => (others => '0'),
Mask => (others => '0')
);
constant C_XIL_DRP_CONFIG_SET_EMPTY : T_XIL_DRP_CONFIG_SET := (
Configs => (others => C_XIL_DRP_CONFIG_EMPTY),
LastIndex => 0
);
component xil_ChipScopeICON is
generic (
PORTS : POSITIVE
);
port (
ControlBus : inout T_XIL_CHIPSCOPE_CONTROL_VECTOR(PORTS - 1 downto 0)
);
end component;
component xil_SystemMonitor_Virtex6 is
port (
Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic
Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output
Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output
Alarm : out STD_LOGIC; -- OR'ed output of all the alarms
VP : in STD_LOGIC; -- Dedicated analog input pair
VN : in STD_LOGIC
);
end component;
component xil_SystemMonitor_Series7 is
port (
Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic
Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output
Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output
Alarm : out STD_LOGIC; -- OR'ed output of all the alarms
VP : in STD_LOGIC; -- Dedicated analog input pair
VN : in STD_LOGIC
);
end component;
end package;
|
------------------------------------------------------------------------------
-- Title : Systolic High Pass FIR Filter
------------------------------------------------------------------------------
-- Author : Daniel Tavares
-- Company : CNPEM LNLS-DIG
-- Created : 2019-11-23
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Systolic FIR for high pass filter.
-- Coefficients are calculated to meet the specification:
-- - Stopband norm. frequency: 0.04545
-- - Passband norm. frequency: 0.4545
-- - Attenuation at stopband: 60 dB
-- - Attenuation ripple at passband: +/- 0.1 dB
-------------------------------------------------------------------------------
-- Copyright (c) 2019 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2019-11-23 1.0 daniel.tavares Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity hpf_adcinput is
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
ce_i : in std_logic;
data_i : in std_logic_vector (15 downto 0);
data_o : out std_logic_vector (15 downto 0)
);
end hpf_adcinput;
architecture rtl of hpf_adcinput is
type t_coef is array(12 downto 0) of std_logic_vector(24 downto 0);
signal coef : t_coef;
type t_cascade is array(11 downto 0) of std_logic_vector(47 downto 0);
signal cascade : t_cascade;
type t_data_io is array(12 downto 0) of std_logic_vector(17 downto 0);
signal data : t_data_io;
signal data_full : std_logic_vector(47 downto 0);
component mac1reg is
port
(
clk_i : in std_logic;
data_i : in std_logic_vector (17 downto 0);
coef_i : in std_logic_vector (24 downto 0);
data_o : out std_logic_vector (17 downto 0);
mac_o : out std_logic_vector (47 downto 0);
casc_o : out std_logic_vector (47 downto 0)
);
end component;
component mac2reg is
port
(
clk_i : in std_logic;
data_i : in std_logic_vector (17 downto 0);
coef_i : in std_logic_vector (24 downto 0);
casc_i : in std_logic_vector (47 downto 0);
data_o : out std_logic_vector (17 downto 0);
mac_o : out std_logic_vector (47 downto 0);
casc_o : out std_logic_vector (47 downto 0)
);
end component;
signal data_se : std_logic_vector(17 downto 0);
signal data_int : std_logic_vector(data_o'range);
begin
coef <= (
0 => conv_std_logic_vector( 186968, 25),
1 => conv_std_logic_vector( 363532, 25),
2 => conv_std_logic_vector( 192469, 25),
3 => conv_std_logic_vector( -714736, 25),
4 => conv_std_logic_vector( -2294800, 25),
5 => conv_std_logic_vector( -3865066, 25),
6 => conv_std_logic_vector( 12250263, 25),
7 => conv_std_logic_vector( -3865066, 25),
8 => conv_std_logic_vector( -2294800, 25),
9 => conv_std_logic_vector( -714736, 25),
10 => conv_std_logic_vector( 192469, 25),
11 => conv_std_logic_vector( 363532, 25),
12 => conv_std_logic_vector( 186968, 25)
);
cmp_mac_first : mac1reg
port map
(
clk_i => clk_i,
data_i => data_se,
coef_i => coef(0),
data_o => data(0),
casc_o => cascade(0)
);
gen_mac_cascade : for i in 1 to 11 generate
cmp_mac : mac2reg
port map
(
clk_i => clk_i,
data_i => data(i-1),
coef_i => coef(i),
casc_i => cascade(i-1),
data_o => data(i),
mac_o => open,
casc_o => cascade(i)
);
end generate;
cmp_mac_last : mac2reg
port map
(
clk_i => clk_i,
data_i => data(11),
coef_i => coef(12),
casc_i => cascade(11),
data_o => open,
mac_o => data_full,
casc_o => open
);
data_se(15 downto 0) <= data_i;
data_se(17 downto 16) <= (others => data_i(15));
-- Truncate 7 MSB and 25 LSB to achieve better precision at the output
-- TODO: verify if this is the optimal solution
data_o <= data_full(40 downto 25);
end rtl;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of adc
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: adc-struct-a.vhd,v 1.2 2005/04/14 06:53:00 wig Exp $
-- $Date: 2005/04/14 06:53:00 $
-- $Log: adc-struct-a.vhd,v $
-- Revision 1.2 2005/04/14 06:53:00 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Revision: 1.33 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of adc
--
architecture struct of adc is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component adc_ctrl --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for i_adc_ctrl
i_adc_ctrl: adc_ctrl
;
-- End of Generated Instance Port Map for i_adc_ctrl
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SimpleEnum IS
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
s_in0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_in1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF SimpleEnum IS
TYPE fsmT IS (send0, send1);
SIGNAL fsmSt : fsmt := send0;
SIGNAL fsmSt_next : fsmt;
BEGIN
assig_process_fsmSt: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
fsmSt <= send0;
ELSE
fsmSt <= fsmSt_next;
END IF;
END IF;
END PROCESS;
assig_process_fsmSt_next: PROCESS(fsmSt, s_in0, s_in1)
BEGIN
IF fsmSt = send0 THEN
s_out <= s_in0;
fsmSt_next <= send1;
ELSE
s_out <= s_in1;
fsmSt_next <= send0;
END IF;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:23:38 11/11/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/decode/tbdecode.vhd
-- Project Name: decode
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Decode
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tbdecode IS
END tbdecode;
ARCHITECTURE behavior OF tbdecode IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Decode
PORT(
Instruction : IN std_logic_vector(31 downto 0);
posicionin : IN std_logic_vector(31 downto 0);
Regtomemin : IN std_logic_vector(31 downto 0);
cwpin : IN std_logic;
iccin : IN std_logic_vector(3 downto 0);
Resetext : IN std_logic;
ncwpout : OUT std_logic;
callout : OUT std_logic_vector(31 downto 0);
ifout : OUT std_logic_vector(31 downto 0);
rfdestout : OUT std_logic;
rfsourceout : OUT std_logic_vector(1 downto 0);
wrenmen : OUT std_logic;
pcsource : OUT std_logic_vector(1 downto 0);
aluop : OUT std_logic_vector(5 downto 0);
a18 : OUT std_logic_vector(31 downto 0);
crs1out : OUT std_logic_vector(31 downto 0);
op2out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Instruction : std_logic_vector(31 downto 0) := (others => '0');
signal posicionin : std_logic_vector(31 downto 0) := (others => '0');
signal Regtomemin : std_logic_vector(31 downto 0) := (others => '0');
signal cwpin : std_logic := '0';
signal iccin : std_logic_vector(3 downto 0) := (others => '0');
signal Resetext : std_logic := '0';
--Outputs
signal ncwpout : std_logic;
signal callout : std_logic_vector(31 downto 0);
signal ifout : std_logic_vector(31 downto 0);
signal rfdestout : std_logic;
signal rfsourceout : std_logic_vector(1 downto 0);
signal wrenmen : std_logic;
signal pcsource : std_logic_vector(1 downto 0);
signal aluop : std_logic_vector(5 downto 0);
signal a18 : std_logic_vector(31 downto 0);
signal crs1out : std_logic_vector(31 downto 0);
signal op2out : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Decode PORT MAP (
Instruction => Instruction,
posicionin => posicionin,
Regtomemin => Regtomemin,
cwpin => cwpin,
iccin => iccin,
Resetext => Resetext,
ncwpout => ncwpout,
callout => callout,
ifout => ifout,
rfdestout => rfdestout,
rfsourceout => rfsourceout,
wrenmen => wrenmen,
pcsource => pcsource,
aluop => aluop,
a18 => a18,
crs1out => crs1out,
op2out => op2out
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Instruction <= "10100100000100000010000000000101";
posicionin <= "00000000000000000000000000000001";
Regtomemin <= "00000000000000000000000000111111";
cwpin <= '0';
iccin <= "0000";
Resetext <= '1';
wait for 100 ns;
Instruction <= "10100100000100000010000000000101";
posicionin <= "00000000000000000000000000000001";
Regtomemin <= "00000000000000000000000000111111";
cwpin <= '0';
iccin <= "0000";
Resetext <= '0';
wait for 100 ns;
Instruction <= "10100100000100000010000000001111";
posicionin <= "00000000000000000000000000000010";
Regtomemin <= "00000000000000000000000000001111";
cwpin <= '0';
iccin <= "0000";
Resetext <= '0';
-- insert stimulus here
wait;
end process;
END;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_ch_18_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_18_08 is
end entity ch_18_08;
----------------------------------------------------------------
architecture test of ch_18_08 is
begin
process is
use std.textio.all;
file f : text open read_mode is "ch_18_08.dat";
variable L : line;
variable ch : character;
variable s : string(1 to 5);
variable i : integer;
variable r : real;
begin
readline(f, L);
read(L, ch);
report character'image(ch);
read(L, ch);
report character'image(ch);
readline(f, L);
read(L, s);
report '"' & s & '"';
read(L, s);
report '"' & s & '"';
readline(f, L);
-- code from book:
if L'length < s'length then
read(L, s(1 to L'length));
else
read(L, s);
end if;
-- end of code from book
report '"' & s & '"';
readline(f, L);
read(L, i);
report integer'image(i);
read(L, r);
report real'image(r);
wait;
end process;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_ch_18_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_18_08 is
end entity ch_18_08;
----------------------------------------------------------------
architecture test of ch_18_08 is
begin
process is
use std.textio.all;
file f : text open read_mode is "ch_18_08.dat";
variable L : line;
variable ch : character;
variable s : string(1 to 5);
variable i : integer;
variable r : real;
begin
readline(f, L);
read(L, ch);
report character'image(ch);
read(L, ch);
report character'image(ch);
readline(f, L);
read(L, s);
report '"' & s & '"';
read(L, s);
report '"' & s & '"';
readline(f, L);
-- code from book:
if L'length < s'length then
read(L, s(1 to L'length));
else
read(L, s);
end if;
-- end of code from book
report '"' & s & '"';
readline(f, L);
read(L, i);
report integer'image(i);
read(L, r);
report real'image(r);
wait;
end process;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_ch_18_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_18_08 is
end entity ch_18_08;
----------------------------------------------------------------
architecture test of ch_18_08 is
begin
process is
use std.textio.all;
file f : text open read_mode is "ch_18_08.dat";
variable L : line;
variable ch : character;
variable s : string(1 to 5);
variable i : integer;
variable r : real;
begin
readline(f, L);
read(L, ch);
report character'image(ch);
read(L, ch);
report character'image(ch);
readline(f, L);
read(L, s);
report '"' & s & '"';
read(L, s);
report '"' & s & '"';
readline(f, L);
-- code from book:
if L'length < s'length then
read(L, s(1 to L'length));
else
read(L, s);
end if;
-- end of code from book
report '"' & s & '"';
readline(f, L);
read(L, i);
report integer'image(i);
read(L, r);
report real'image(r);
wait;
end process;
end architecture test;
|
library ieee ;
use ieee.std_logic_1164.all ;
library std;
use std.textio.all;
-- Utility package
package util is
procedure nop( signal clock : in std_logic ; count : in natural ) ;
end package ;
package body util is
procedure nop( signal clock : in std_logic ; count : in natural ) is
begin
for i in 1 to count loop
wait until rising_edge( clock ) ;
end loop ;
end procedure ;
end package body ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity data_saver is
generic(
FILENAME : string := "file.dat";
DATA_WIDTH : natural := 16
);
port(
reset : in std_logic;
clock : in std_logic;
data : std_logic_vector(DATA_WIDTH-1 downto 0);
data_valid : std_logic
);
end entity;
architecture arch of data_saver is
begin
handler : process
FILE fp : text;
variable line_data : line;
begin
--
wait until falling_edge(reset);
file_open(fp, FILENAME, WRITE_MODE);
while (reset = '0') loop
wait until rising_edge(data_valid);
write(line_data, data);
writeline(fp,line_data);
end loop;
file_close(fp);
end process;
end architecture;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity signed_saver is
generic(
FILENAME : string := "file.dat";
DATA_WIDTH : natural := 16
);
port(
reset : in std_logic;
clock : in std_logic;
data : signed(DATA_WIDTH-1 downto 0);
data_valid : std_logic
);
end entity;
architecture arch of signed_saver is
begin
handler : process
FILE fp : text;
variable line_data : line;
begin
--
wait until falling_edge(reset);
file_open(fp, FILENAME, WRITE_MODE);
while (reset = '0') loop
wait until rising_edge(clock);
if data_valid = '1' then
write(line_data, (to_integer(data)));
writeline(fp,line_data);
end if;
end loop;
file_close(fp);
end process;
end architecture;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity data_reader is
generic(
FILENAME : string := "file.dat";
DATA_WIDTH : natural := 16
);
port(
reset : in std_logic;
clock : in std_logic;
data_request : in std_logic;
data : out std_logic_vector(DATA_WIDTH-1 downto 0);
data_valid : out std_logic
);
end entity;
architecture arch of data_reader is
type character_array_t is array (natural range <>) of character;
begin
handler : process
variable line_data : line;
variable tmp : integer;
variable c : character;--_array_t(0 to 3);
type bin_t is file of character ;
file fp : bin_t ;
variable fs : file_open_status ;
begin
--
data <= (others => '0');
data_valid <= '0';
wait until falling_edge(reset);
file_open(fs, fp, FILENAME, READ_MODE);
if( fs /= OPEN_OK ) then
report "File open issues" severity failure ;
end if ;
--readline(fp,line_data);
while (reset = '0') loop
wait until rising_edge(clock);
data_valid <= '0';
if data_request = '1' then
read(fp, c);
tmp := integer(natural(character'pos(c)));
data(7 downto 0) <= std_logic_vector(to_unsigned(tmp,8));
read(fp, c);
tmp := integer(natural(character'pos(c)));
data(15 downto 8) <= std_logic_vector(to_unsigned(tmp,8));
read(fp, c);
tmp := integer(natural(character'pos(c)));
data(23 downto 16) <= std_logic_vector(to_unsigned(tmp,8));
read(fp, c);
tmp := integer(natural(character'pos(c)));
data(31 downto 24) <= std_logic_vector(to_unsigned(tmp,8));
data_valid <= '1';
wait until rising_edge(clock);
data_valid <= '0';
end if;
end loop;
file_close(fp);
end process;
end architecture;
|
-------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox is
port(
X0In : in std_logic_vector(15 downto 0);
X1In : in std_logic_vector(15 downto 0);
X2In : in std_logic_vector(15 downto 0);
X3In : in std_logic_vector(15 downto 0);
X4In : in std_logic_vector(15 downto 0);
RoundNr : in std_logic_vector(3 downto 0);
X0Out : out std_logic_vector(15 downto 0);
X1Out : out std_logic_vector(15 downto 0);
X2Out : out std_logic_vector(15 downto 0);
X3Out : out std_logic_vector(15 downto 0);
X4Out : out std_logic_vector(15 downto 0);
Sel : in std_logic_vector(1 downto 0));
end entity Sbox;
architecture structural of Sbox is
begin
Sbox: process(X0In,X1In,X2In,X3In,X4In,RoundNr,Sel) is
-- Procedure for 5-bit Sbox
procedure doSboxPart (
variable SboxPartIn : in std_logic_vector(4 downto 0);
variable SboxPartOut : out std_logic_vector(4 downto 0)) is
-- Temp variable
variable SboxPartTemp : std_logic_vector(17 downto 0);
begin
-- Sbox Interconnections
SboxPartTemp(0) := SboxPartIn(0) xor SboxPartIn(4);
SboxPartTemp(1) := SboxPartIn(2) xor SboxPartIn(1);
SboxPartTemp(2) := SboxPartIn(4) xor SboxPartIn(3);
SboxPartTemp(3) := not SboxPartTemp(0);
SboxPartTemp(4) := not SboxPartIn(1);
SboxPartTemp(5) := not SboxPartTemp(1);
SboxPartTemp(6) := not SboxPartIn(3);
SboxPartTemp(7) := not SboxPartTemp(2);
SboxPartTemp(8) := SboxPartIn(1) and SboxPartTemp(3);
SboxPartTemp(9) := SboxPartTemp(1) and SboxPartTemp(4);
SboxPartTemp(10) := SboxPartIn(3) and SboxPartTemp(5);
SboxPartTemp(11) := SboxPartTemp(2) and SboxPartTemp(6);
SboxPartTemp(12) := SboxPartTemp(0) and SboxPartTemp(7);
SboxPartTemp(13) := SboxPartTemp(0) xor SboxPartTemp(9);
SboxPartTemp(14) := SboxPartIn(1) xor SboxPartTemp(10);
SboxPartTemp(15) := SboxPartTemp(1) xor SboxPartTemp(11);
SboxPartTemp(16) := SboxPartIn(3) xor SboxPartTemp(12);
SboxPartTemp(17) := SboxPartTemp(2) xor SboxPartTemp(8);
SboxPartOut(0) := SboxPartTemp(13) xor SboxPartTemp(17);
SboxPartOut(1) := SboxPartTemp(13) xor SboxPartTemp(14);
SboxPartOut(2) := not SboxPartTemp(15);
SboxPartOut(3) := SboxPartTemp(15) xor SboxPartTemp(16);
SboxPartOut(4) := SboxPartTemp(17);
end procedure doSboxPart;
variable X2TempIn : std_logic_vector(15 downto 0);
variable TempIn,TempOut : std_logic_vector(4 downto 0);
begin
-- Xor with round constants
if Sel = "11" then
X2TempIn(3 downto 0) := X2In(3 downto 0) xor RoundNr;
X2TempIn(7 downto 4) := X2In(7 downto 4) xnor RoundNr;
X2TempIn(15 downto 8) := X2In(15 downto 8);
else
X2TempIn := X2In;
end if;
-- Apply 5-bit Sbox 64 times
for i in X0In'range loop
TempIn(0) := X0In(i);
TempIn(1) := X1In(i);
TempIn(2) := X2TempIn(i);
TempIn(3) := X3In(i);
TempIn(4) := X4In(i);
doSboxPart(TempIn,TempOut);
X0Out(i) <= TempOut(0);
X1Out(i) <= TempOut(1);
X2Out(i) <= TempOut(2);
X3Out(i) <= TempOut(3);
X4Out(i) <= TempOut(4);
end loop;
end process Sbox;
end architecture structural;
|
----------------------------------------------------------------------------------
-- Company: Rat Technologies
-- Engineer: Various Rats
--
-- Create Date: 15:06:58 10/02/2013
-- Design Name:
-- Module Name: mux_4to1_programnCounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Simple pseudo-random number generator based on a linear feedback
-- shift register.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: This was originally written/provided by Jeff Gerfen.
-- Bryan Mealy made a few modificaitons to it in the general hope of making
-- the thing work better.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RandomNumberGenerator is
port ( clk : in std_logic;
random_num : out std_logic_vector (2 downto 0));
end RandomNumberGenerator;
architecture Behavioral of RandomNumberGenerator is
begin
process(clk)
variable rand_temp : std_logic_vector(7 downto 0):= (others => '0');
variable temp0 : std_logic;
variable temp5 : std_logic;
begin
if(rising_edge(clk)) then
temp5 := not rand_temp(2);
temp0 := rand_temp(7) xor rand_temp(6);
rand_temp := rand_temp(4 downto 3) & temp5 & rand_temp(1 downto 0) &
rand_temp(6 downto 5) & temp0;
end if;
random_num <= rand_temp(2 downto 0);
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_bus_bridge is
generic (
g_addr_width : natural := 8 );
port (
clock_a : in std_logic;
reset_a : in std_logic;
req_a : in t_io_req;
resp_a : out t_io_resp;
clock_b : in std_logic;
reset_b : in std_logic;
req_b : out t_io_req;
resp_b : in t_io_resp );
end entity;
architecture rtl of io_bus_bridge is
-- CLOCK_A
signal to_wr_en : std_logic;
signal to_wr_din : std_logic_vector(g_addr_width+8 downto 0);
signal to_wr_full : std_logic;
signal from_rd_en : std_logic;
signal from_rd_dout : std_logic_vector(7 downto 0);
signal from_rd_valid: std_logic;
type t_state_a is (idle, pending_w, pending_r, wait_rdata);
signal state_a : t_state_a;
-- CLOCK B
signal from_wr_en : std_logic;
signal to_rd_en : std_logic;
signal to_rd_dout : std_logic_vector(g_addr_width+8 downto 0);
signal to_rd_valid : std_logic;
type t_state_b is (idle, do_write, do_read);
signal state_b : t_state_b;
begin
-- generate ack
process(clock_a)
begin
if rising_edge(clock_a) then
resp_a.ack <= '0';
resp_a.data <= X"00";
case state_a is
when idle =>
if req_a.write='1' then
if to_wr_full = '1' then
state_a <= pending_w;
else
resp_a.ack <= '1';
end if;
elsif req_a.read='1' then
if to_wr_full = '1' then
state_a <= pending_r;
else
state_a <= wait_rdata;
end if;
end if;
when pending_w =>
if to_wr_full = '0' then
state_a <= idle;
resp_a.ack <= '1';
end if;
when pending_r =>
if to_wr_full = '0' then
state_a <= wait_rdata;
end if;
when wait_rdata =>
if from_rd_valid = '1' then
resp_a.ack <= '1';
resp_a.data <= from_rd_dout;
state_a <= idle;
end if;
when others =>
null;
end case;
if reset_a = '1' then
state_a <= idle;
end if;
end if;
end process;
process (state_a, to_wr_full, from_rd_valid, req_a)
begin
to_wr_en <= '0';
to_wr_din <= std_logic_vector(req_a.address(g_addr_width-1 downto 0)) & '0' & req_a.data;
from_rd_en <= '0';
case state_a is
when idle =>
if to_wr_full = '0' then
to_wr_en <= req_a.write or req_a.read;
to_wr_din(8) <= req_a.write;
end if;
when pending_w =>
if to_wr_full = '0' then
to_wr_en <= '1';
to_wr_din(8) <= '1';
end if;
when pending_r =>
if to_wr_full = '0' then
to_wr_en <= '1';
to_wr_din(8) <= '0';
end if;
when wait_rdata =>
if from_rd_valid='1' then
from_rd_en <= '1';
end if;
end case;
end process;
i_heen: entity work.async_fifo_ft
generic map (
g_data_width => g_addr_width + 9,
g_depth_bits => 3 )
port map (
wr_clock => clock_a,
wr_reset => reset_a,
wr_en => to_wr_en,
wr_din => to_wr_din,
wr_full => to_wr_full,
rd_clock => clock_b,
rd_reset => reset_b,
rd_next => to_rd_en,
rd_dout => to_rd_dout,
rd_valid => to_rd_valid );
i_weer: entity work.async_fifo_ft
generic map (
g_data_width => 8,
g_depth_bits => 3 )
port map (
wr_clock => clock_b,
wr_reset => reset_b,
wr_en => from_wr_en,
wr_din => resp_b.data,
rd_clock => clock_a,
rd_reset => reset_a,
rd_next => from_rd_en,
rd_dout => from_rd_dout,
rd_valid => from_rd_valid );
process(clock_b)
begin
if rising_edge(clock_b) then
req_b.read <= '0';
req_b.write <= '0';
case state_b is
when idle =>
if to_rd_valid='1' then
req_b.address(g_addr_width-1 downto 0) <= unsigned(to_rd_dout(g_addr_width+8 downto 9));
req_b.data <= to_rd_dout(7 downto 0);
if to_rd_dout(8)='1' then
req_b.write <= '1';
state_b <= do_write;
else
req_b.read <= '1';
state_b <= do_read;
end if;
end if;
when do_write =>
if resp_b.ack = '1' then
state_b <= idle;
end if;
when do_read =>
if resp_b.ack = '1' then
state_b <= idle;
end if;
end case;
if reset_b='1' then
state_b <= idle;
req_b <= c_io_req_init;
end if;
end if;
end process;
process(state_b, to_rd_valid, resp_b)
begin
to_rd_en <= '0';
from_wr_en <= '0';
case state_b is
when idle =>
if to_rd_valid = '1' then
to_rd_en <= '1';
end if;
when do_read =>
if resp_b.ack = '1' then
from_wr_en <= '1';
end if;
when others =>
null;
end case;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LOAD_BALANCER is
PORT (
CORE_ID : IN STD_LOGIC;
ADDRESS_A_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_C0 : IN STD_LOGIC;
ADDRESS_A_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_C1 : IN STD_LOGIC;
ADDRESS_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
IO_ENABLE : IN STD_LOGIC;
global_enable : IN STD_LOGIC_VECTOR (5 downto 0);
ADDRESS_A_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_MAG : OUT STD_LOGIC
);
end;
architecture balancer of LOAD_BALANCER is
begin
process (CORE_ID, ADDRESS_A_C0, ADDRESS_B_C0, ADDRESS_C_C0, ADDRESS_0_C0, ADDRESS_1_C0, ADDRESS_W_C0,
ADDRESS_A_C1, ADDRESS_B_C1, ADDRESS_C_C1, ADDRESS_0_C1, ADDRESS_1_C1, ADDRESS_W_C1,
DATA_TO_W_C0, DATA_TO_W_C1, W_EN_C0, W_EN_C1, IO_ENABLE, ADDRESS_IO, DATA_IO, global_enable) begin
if (CORE_ID = '0') then
if (IO_ENABLE = '1') then
ADDRESS_A_MAG <= "00000000000000000000000000000000";
ADDRESS_B_MAG <= "00000000000000000000000000000001";
ADDRESS_C_MAG <= "00000000000000000000000000000010";
ADDRESS_0_MAG <= "00000000000000000000000000000011";
ADDRESS_1_MAG <= "00000000000000000000000000000100";
DATA_TO_W_MAG <= DATA_IO;
ADDRESS_W_MAG <= ADDRESS_IO;
W_EN_MAG <= '1';
else
ADDRESS_A_MAG <= ADDRESS_A_C0;
ADDRESS_B_MAG <= ADDRESS_B_C0;
ADDRESS_C_MAG <= ADDRESS_C_C0;
ADDRESS_0_MAG <= ADDRESS_0_C0;
ADDRESS_1_MAG <= ADDRESS_1_C0;
ADDRESS_W_MAG <= ADDRESS_W_C0;
DATA_TO_W_MAG <= DATA_TO_W_C0;
W_EN_MAG <= W_EN_C0;
end if;
else
if (IO_ENABLE = '1') then
ADDRESS_A_MAG <= "00000000000000000000000000000000";
ADDRESS_B_MAG <= "00000000000000000000000000000001";
ADDRESS_C_MAG <= "00000000000000000000000000000010";
ADDRESS_0_MAG <= "00000000000000000000000000000011";
ADDRESS_1_MAG <= "00000000000000000000000000000100";
DATA_TO_W_MAG <= DATA_IO;
ADDRESS_W_MAG <= ADDRESS_IO;
W_EN_MAG <= '1';
else
ADDRESS_A_MAG <= ADDRESS_A_C1;
ADDRESS_B_MAG <= ADDRESS_B_C1;
ADDRESS_C_MAG <= ADDRESS_C_C1;
ADDRESS_0_MAG <= ADDRESS_0_C1;
ADDRESS_1_MAG <= ADDRESS_1_C1;
ADDRESS_W_MAG <= ADDRESS_W_C1;
DATA_TO_W_MAG <= DATA_TO_W_C1;
W_EN_MAG <= W_EN_C1;
end if;
end if;
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LOAD_BALANCER is
PORT (
CORE_ID : IN STD_LOGIC;
ADDRESS_A_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_C0 : IN STD_LOGIC;
ADDRESS_A_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_C1 : IN STD_LOGIC;
ADDRESS_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
IO_ENABLE : IN STD_LOGIC;
global_enable : IN STD_LOGIC_VECTOR (5 downto 0);
ADDRESS_A_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_MAG : OUT STD_LOGIC
);
end;
architecture balancer of LOAD_BALANCER is
begin
process (CORE_ID, ADDRESS_A_C0, ADDRESS_B_C0, ADDRESS_C_C0, ADDRESS_0_C0, ADDRESS_1_C0, ADDRESS_W_C0,
ADDRESS_A_C1, ADDRESS_B_C1, ADDRESS_C_C1, ADDRESS_0_C1, ADDRESS_1_C1, ADDRESS_W_C1,
DATA_TO_W_C0, DATA_TO_W_C1, W_EN_C0, W_EN_C1, IO_ENABLE, ADDRESS_IO, DATA_IO, global_enable) begin
if (CORE_ID = '0') then
if (IO_ENABLE = '1') then
ADDRESS_A_MAG <= "00000000000000000000000000000000";
ADDRESS_B_MAG <= "00000000000000000000000000000001";
ADDRESS_C_MAG <= "00000000000000000000000000000010";
ADDRESS_0_MAG <= "00000000000000000000000000000011";
ADDRESS_1_MAG <= "00000000000000000000000000000100";
DATA_TO_W_MAG <= DATA_IO;
ADDRESS_W_MAG <= ADDRESS_IO;
W_EN_MAG <= '1';
else
ADDRESS_A_MAG <= ADDRESS_A_C0;
ADDRESS_B_MAG <= ADDRESS_B_C0;
ADDRESS_C_MAG <= ADDRESS_C_C0;
ADDRESS_0_MAG <= ADDRESS_0_C0;
ADDRESS_1_MAG <= ADDRESS_1_C0;
ADDRESS_W_MAG <= ADDRESS_W_C0;
DATA_TO_W_MAG <= DATA_TO_W_C0;
W_EN_MAG <= W_EN_C0;
end if;
else
if (IO_ENABLE = '1') then
ADDRESS_A_MAG <= "00000000000000000000000000000000";
ADDRESS_B_MAG <= "00000000000000000000000000000001";
ADDRESS_C_MAG <= "00000000000000000000000000000010";
ADDRESS_0_MAG <= "00000000000000000000000000000011";
ADDRESS_1_MAG <= "00000000000000000000000000000100";
DATA_TO_W_MAG <= DATA_IO;
ADDRESS_W_MAG <= ADDRESS_IO;
W_EN_MAG <= '1';
else
ADDRESS_A_MAG <= ADDRESS_A_C1;
ADDRESS_B_MAG <= ADDRESS_B_C1;
ADDRESS_C_MAG <= ADDRESS_C_C1;
ADDRESS_0_MAG <= ADDRESS_0_C1;
ADDRESS_1_MAG <= ADDRESS_1_C1;
ADDRESS_W_MAG <= ADDRESS_W_C1;
DATA_TO_W_MAG <= DATA_TO_W_C1;
W_EN_MAG <= W_EN_C1;
end if;
end if;
end process;
end; |
---------------------------------------------------------------------
-- TITLE: NoC_Node
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- ORIGNAL FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity provides a simple NoC node with plasma as its processor
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
entity NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
log_file : string := "output.txt");
port( reset : in std_logic;
clk : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end; --entity NoC_Node
architecture messed_up of NoC_Node is
constant memory_type : string :=
"TRI_PORT_X";
-- "DUAL_PORT_";
-- "ALTERA_LPM";
-- "XILINX_16X";
signal interrupt : std_logic := '0';
signal mem_write : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal pause1 : std_logic := '0';
signal pause2 : std_logic := '0';
signal pause : std_logic;
signal no_ddr_start: std_logic;
signal no_ddr_stop : std_logic;
signal byte_we : std_logic_vector(3 downto 0);
signal uart_write : std_logic;
signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
--signal credit_in, valid_in: std_logic := '0';
--signal credit_out, valid_out: std_logic := '0';
--signal RX: std_logic_vector(31 downto 0) := (others => '0');
--signal TX: std_logic_vector(31 downto 0) := (others => '0');
-- signal credit_counter_out_0: std_logic_vector (1 downto 0);
begin --architecture
--pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
pause1 <= '0';
--pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
pause2 <= '0';
pause <= pause1 or pause2;
--gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
--gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
--gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
--gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
u1_plasma: plasma
generic map (memory_type => memory_type,
ethernet => '0',
use_cache => '0',
log_file => log_file,
current_address => current_address,
stim_file => stim_file)
PORT MAP (
clk => clk,
reset => reset,
uart_read => uart_write,
uart_write => uart_write,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
mem_pause_in => pause,
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
gpio0_out => open,
gpioA_in => gpioA_in,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX,
link_faults => link_faults,
turn_faults => turn_faults,
Rxy_reconf_PE => Rxy_reconf_PE,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command
);
dram_proc: process(clk, address, byte_we, data_write, pause)
constant ADDRESS_WIDTH : natural := 16;
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of
std_logic_vector(31 downto 0);
variable storage : storage_array;
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
begin
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if byte_we(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if byte_we(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if byte_we(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if byte_we(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
if rising_edge(clk) then
if address(30 downto 28) = "001" and byte_we /= "0000" then
storage(index) := data;
end if;
end if;
if pause = '0' then
data_read <= data;
end if;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: NoC_Node
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- ORIGNAL FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity provides a simple NoC node with plasma as its processor
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
entity NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
log_file : string := "output.txt");
port( reset : in std_logic;
clk : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end; --entity NoC_Node
architecture messed_up of NoC_Node is
constant memory_type : string :=
"TRI_PORT_X";
-- "DUAL_PORT_";
-- "ALTERA_LPM";
-- "XILINX_16X";
signal interrupt : std_logic := '0';
signal mem_write : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal pause1 : std_logic := '0';
signal pause2 : std_logic := '0';
signal pause : std_logic;
signal no_ddr_start: std_logic;
signal no_ddr_stop : std_logic;
signal byte_we : std_logic_vector(3 downto 0);
signal uart_write : std_logic;
signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
--signal credit_in, valid_in: std_logic := '0';
--signal credit_out, valid_out: std_logic := '0';
--signal RX: std_logic_vector(31 downto 0) := (others => '0');
--signal TX: std_logic_vector(31 downto 0) := (others => '0');
-- signal credit_counter_out_0: std_logic_vector (1 downto 0);
begin --architecture
--pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
pause1 <= '0';
--pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
pause2 <= '0';
pause <= pause1 or pause2;
--gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
--gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
--gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
--gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
u1_plasma: plasma
generic map (memory_type => memory_type,
ethernet => '0',
use_cache => '0',
log_file => log_file,
current_address => current_address,
stim_file => stim_file)
PORT MAP (
clk => clk,
reset => reset,
uart_read => uart_write,
uart_write => uart_write,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
mem_pause_in => pause,
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
gpio0_out => open,
gpioA_in => gpioA_in,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX,
link_faults => link_faults,
turn_faults => turn_faults,
Rxy_reconf_PE => Rxy_reconf_PE,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command
);
dram_proc: process(clk, address, byte_we, data_write, pause)
constant ADDRESS_WIDTH : natural := 16;
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of
std_logic_vector(31 downto 0);
variable storage : storage_array;
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
begin
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if byte_we(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if byte_we(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if byte_we(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if byte_we(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
if rising_edge(clk) then
if address(30 downto 28) = "001" and byte_we /= "0000" then
storage(index) := data;
end if;
end if;
if pause = '0' then
data_read <= data;
end if;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: NoC_Node
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- ORIGNAL FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity provides a simple NoC node with plasma as its processor
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
entity NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
log_file : string := "output.txt");
port( reset : in std_logic;
clk : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end; --entity NoC_Node
architecture messed_up of NoC_Node is
constant memory_type : string :=
"TRI_PORT_X";
-- "DUAL_PORT_";
-- "ALTERA_LPM";
-- "XILINX_16X";
signal interrupt : std_logic := '0';
signal mem_write : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal pause1 : std_logic := '0';
signal pause2 : std_logic := '0';
signal pause : std_logic;
signal no_ddr_start: std_logic;
signal no_ddr_stop : std_logic;
signal byte_we : std_logic_vector(3 downto 0);
signal uart_write : std_logic;
signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
--signal credit_in, valid_in: std_logic := '0';
--signal credit_out, valid_out: std_logic := '0';
--signal RX: std_logic_vector(31 downto 0) := (others => '0');
--signal TX: std_logic_vector(31 downto 0) := (others => '0');
-- signal credit_counter_out_0: std_logic_vector (1 downto 0);
begin --architecture
--pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
pause1 <= '0';
--pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
pause2 <= '0';
pause <= pause1 or pause2;
--gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
--gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
--gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
--gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
u1_plasma: plasma
generic map (memory_type => memory_type,
ethernet => '0',
use_cache => '0',
log_file => log_file,
current_address => current_address,
stim_file => stim_file)
PORT MAP (
clk => clk,
reset => reset,
uart_read => uart_write,
uart_write => uart_write,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
mem_pause_in => pause,
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
gpio0_out => open,
gpioA_in => gpioA_in,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX,
link_faults => link_faults,
turn_faults => turn_faults,
Rxy_reconf_PE => Rxy_reconf_PE,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command
);
dram_proc: process(clk, address, byte_we, data_write, pause)
constant ADDRESS_WIDTH : natural := 16;
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of
std_logic_vector(31 downto 0);
variable storage : storage_array;
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
begin
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if byte_we(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if byte_we(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if byte_we(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if byte_we(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
if rising_edge(clk) then
if address(30 downto 28) = "001" and byte_we /= "0000" then
storage(index) := data;
end if;
end if;
if pause = '0' then
data_read <= data;
end if;
end process;
end; --architecture logic
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: atcpads_gen
-- File: atcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Atmel ATC18 pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package atcpads is
-- input pad
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
-- input pad with pull-up
component pc33d00uz port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad
component pc33d20z port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad with pull-up
component pt33d20uz port (pad : inout std_logic; cin : out std_logic); end component;
-- output pads
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
-- tri-state output pads
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
-- tri-state output pads with pull-up
component pt33t01uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08uz port (i, oen : in std_logic; pad : out std_logic); end component;
-- bidirectional pads
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
-- bidirectional pads with pull-up
component pt33b01uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
--PCI pads
component pp33o01z
port (i : in std_logic; pad : out std_logic);
end component;
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pc33d00z;
-- pragma translate_on
entity atc18_inpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_inpad is
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
begin
pci0 : if level = pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33b01z;
use atc18.pt33b01z;
use atc18.pt33b02z;
use atc18.pt33b08z;
use atc18.pt33b04z;
-- pragma translate_on
entity atc18_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of atc18_iopad is
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
begin
pci0 : if level = pci33 generate
op : pp33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
f1 : if (strength <= 4) generate
op : pt33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f2 : if (strength > 4) and (strength <= 8) generate
op : pt33b02z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f3 : if (strength > 8) and (strength <= 16) generate
op : pt33b04z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f4 : if (strength > 16) generate
op : pt33b08z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33o01z;
use atc18.pt33o02z;
use atc18.pt33o04z;
use atc18.pt33o08z;
-- pragma translate_on
entity atc18_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of atc18_outpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
signal gnd : std_logic;
begin
gnd <= '0';
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => gnd, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33o01z port map (i => i, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33o02z port map (i => i, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33o04z port map (i => i, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33o08z port map (i => i, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33t01z;
use atc18.pt33t02z;
use atc18.pt33t04z;
use atc18.pt33t08z;
-- pragma translate_on
entity atc18_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of atc18_toutpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
begin
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => en, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33t01z port map (i => i, oen => en, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33t02z port map (i => i, oen => en, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33t04z port map (i => i, oen => en, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33t08z port map (i => i, oen => en, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity atc18_clkpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_clkpad is
begin
o <= pad;
end;
|
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_disp.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : Block memory-based Decoder disparity logic
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY decode_8b10b;
USE decode_8b10b.decode_8b10b_pkg.ALL;
------------------------------------------------------------------------------
--Entity Declaration
------------------------------------------------------------------------------
ENTITY decode_8b10b_disp IS
GENERIC(
C_SINIT_DOUT : STRING := "00000000";
C_SINIT_RUN_DISP : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0
);
PORT(
CE : IN STD_LOGIC := '0';
CLK : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
SYM_DISP : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
DISP_IN : IN STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
USER_SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0')
);
END decode_8b10b_disp;
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_disp IS
----------------------------------------------------------------------------
-- Signal Declarations
----------------------------------------------------------------------------
SIGNAL run_disp_q : STD_LOGIC := '0';
SIGNAL run_disp_d : STD_LOGIC := '0';
SIGNAL disp_in_q : STD_LOGIC := '0';
SIGNAL disp_err_i : STD_LOGIC := '0';
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
BEGIN
gmndi : IF (C_HAS_DISP_IN/=1 AND (C_HAS_RUN_DISP = 1 OR
C_HAS_SYM_DISP = 1 OR
C_HAS_DISP_ERR = 1)) GENERATE
-- store the current running disparity in run_disp_q as a mux selector for
-- the next code's run_disp and disp_err
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
run_disp_q <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSE
run_disp_q <= run_disp_d AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- mux the sym_disp bus and decode it into disp_err and run_disp
gde1 : IF (C_HAS_DISP_ERR = 1 OR C_HAS_SYM_DISP = 1) GENERATE
PROCESS (run_disp_q, SYM_DISP)
BEGIN
IF (run_disp_q = '1') THEN
disp_err_i <= SYM_DISP(3);
ELSE
disp_err_i <= SYM_DISP(1);
END IF;
END PROCESS;
END GENERATE gde1;
grd1 : IF (C_HAS_RUN_DISP = 1 OR C_HAS_SYM_DISP = 1 OR
C_HAS_DISP_ERR = 1) GENERATE
PROCESS (run_disp_q, SYM_DISP)
BEGIN
IF (run_disp_q = '1') THEN
run_disp_d <= SYM_DISP(2);
ELSE
run_disp_d <= SYM_DISP(0);
END IF;
END PROCESS;
END GENERATE grd1;
END GENERATE gmndi;
gmdi: IF (C_HAS_DISP_IN = 1 AND (C_HAS_RUN_DISP = 1 OR
C_HAS_SYM_DISP = 1 OR
C_HAS_DISP_ERR = 1)) GENERATE
-- use the current disp_in as a mux selector for the next code's run_disp
-- and disp_err
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
disp_in_q <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSE
disp_in_q <= DISP_IN AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- mux the sym_disp bus and decode it into disp_err and run_disp
gde2 : IF (C_HAS_DISP_ERR = 1 OR C_HAS_SYM_DISP = 1) GENERATE
PROCESS (disp_in_q, SYM_DISP)
BEGIN
IF (disp_in_q = '1') THEN
disp_err_i <= SYM_DISP(3);
ELSE
disp_err_i <= SYM_DISP(1);
END IF;
END PROCESS;
END GENERATE gde2;
grd2 : IF (C_HAS_RUN_DISP = 1 OR C_HAS_SYM_DISP = 1) GENERATE
PROCESS (disp_in_q, SYM_DISP)
BEGIN
IF (disp_in_q = '1') THEN
run_disp_d <= SYM_DISP(2);
ELSE
run_disp_d <= SYM_DISP(0);
END IF;
END PROCESS;
END GENERATE grd2;
END GENERATE gmdi;
-- map internal signals to outputs
DISP_ERR <= disp_err_i;
RUN_DISP <= run_disp_d;
USER_SYM_DISP(1) <= disp_err_i;
USER_SYM_DISP(0) <= run_disp_d;
END xilinx;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
library work;
use work.sqrt_package.all;
entity euclidean is
port(
input1values, input2values : in std_logic_vector(127 downto 0);
distance : out std_logic_vector(31 downto 0)
);
end euclidean;
architecture behavioural of euclidean is
signal operand : unsigned(31 downto 0);
signal input0bin0, input0bin1, input0bin2, input0bin3, input0bin4, input0bin5, input0bin6, input0bin7 : signed(15 downto 0);
signal input1bin0, input1bin1, input1bin2, input1bin3, input1bin4, input1bin5, input1bin6, input1bin7 : signed(15 downto 0);
begin
process(input1values, input2values)
begin
input0bin0 <= signed(input1values(15 downto 0));
input0bin1 <= signed(input1values(31 downto 16));
input0bin2 <= signed(input1values(47 downto 32));
input0bin3 <= signed(input1values(63 downto 48));
input0bin4 <= signed(input1values(78 downto 64));
input0bin5 <= signed(input1values(95 downto 79));
input0bin6 <= signed(input1values(111 downto 96));
input0bin7 <= signed(input1values(127 downto 112));
input1bin0 <= signed(input1values(15 downto 0));
input1bin1 <= signed(input1values(31 downto 16));
input1bin2 <= signed(input1values(47 downto 32));
input1bin3 <= signed(input1values(63 downto 48));
input1bin4 <= signed(input1values(78 downto 64));
input1bin5 <= signed(input1values(95 downto 79));
input1bin6 <= signed(input1values(111 downto 96));
input1bin7 <= signed(input1values(127 downto 112));
end process;
process(input0bin0, input0bin1, input0bin2, input0bin3, input0bin4, input0bin5, input0bin6, input0bin7, input1bin0, input1bin1, input1bin2, input1bin3, input1bin4, input1bin5, input1bin6, input1bin7)
begin
distance <= std_logic_vector(sqrt(to_unsigned((to_integer(input0bin0 - input1bin0)**2)
+ (to_integer(input0bin1 - input1bin1)**2)
+ (to_integer(input0bin2 - input1bin2)**2)
+ (to_integer(input0bin3 - input1bin3)**2)
+ (to_integer(input0bin4 - input1bin4)**2)
+ (to_integer(input0bin5 - input1bin5)**2)
+ (to_integer(input0bin6 - input1bin6)**2)
+ (to_integer(input0bin7 - input1bin7)**2), 32)));
end process;
end behavioural; |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rawUVCfifo_pkg.ALL;
ENTITY rawUVCfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF rawUVCfifo_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:rawUVCfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rawUVCfifo_pkg.ALL;
ENTITY rawUVCfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF rawUVCfifo_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:rawUVCfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rawUVCfifo_pkg.ALL;
ENTITY rawUVCfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF rawUVCfifo_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:rawUVCfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
architecture rtl of fifo is
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_types.all;
entity VGA_ROM is
generic (
contents : vga_memory
);
port (
clock : in std_logic;
enable : in std_logic;
address : in natural range vga_memory'range;
data : out std_logic
);
end entity VGA_ROM;
architecture behavioural of VGA_ROM is
constant storage : vga_memory := contents;
begin
process(clock)
begin
if rising_edge(clock) then
if enable = '1' then
data <= storage(address);
else
data <= '0';
end if;
end if;
end process;
end behavioural;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_ps2 is
end tb_ps2;
architecture behav of tb_ps2 is
component clk_res_gen is
port(
clk_50 : out std_logic;
rst : out std_logic
);
end component clk_res_gen;
component keyboardSig is
port(
ps2c : out std_logic;
ps2d : out std_logic
);
end component keyboardSig;
component ps2Receiver is
port(
clk : in std_logic;
rst : in std_logic;
-- data
rxData : out std_logic_vector(7 downto 0);
-- module sync signals
dataReady : out std_logic;
dataFetched : in std_logic;
-- ps2 pins
ps2Data : in std_logic;
ps2Clk : in std_logic
);
end component ps2Receiver;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal rxData : std_logic_vector(7 downto 0) := (others => '0');
signal dataReady : std_logic := '0';
signal dataFetched : std_logic := '1';
signal ps2Data : std_logic := '0';
signal ps2Clk : std_logic := '0';
begin
process
begin
wait for 7 ms;
assert false report "done" severity failure;
wait;
end process;
clk_res: clk_res_gen
port map(
clk_50 => clk,
rst => rst
);
keyboard: keyboardSig
port map(
ps2c => ps2Clk,
ps2d => ps2Data
);
rec: ps2Receiver
port map(
clk => clk,
rst => rst,
rxData => rxData,
dataReady => dataReady,
dataFetched => dataFetched,
ps2Data => ps2Data,
ps2Clk => ps2Clk
);
end behav;
|
-- ----------------------------------------------------------------------------
-- Entity for final bitmap representation
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity FINAL_BITMAP is
generic(
DATA_WIDTH : integer := 8
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
SET : in std_logic_vector(DATA_WIDTH - 1 downto 0);
-- output data interface
BITMAP : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity FINAL_BITMAP;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of FINAL_BITMAP is
begin
gen_reg: for i in 0 to DATA_WIDTH - 1 generate
reg: process(CLK)
begin
if (CLK'event and CLK = '1') then
if (RESET = '1') then
BITMAP(i) <= '0';
else
if SET(i) = '1' then
BITMAP(i) <= '1';
end if;
end if;
end if;
end process reg;
end generate gen_reg;
end architecture full;
|
-- NEED RESULT: ARCH00307: Record types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00307
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 3.2.2 (1)
-- 3.2.2 (2)
-- 3.2.2 (3)
-- 3.2.2 (4)
-- 3.2.2 (5)
-- 3.2.2 (6)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00307(ARCH00307)
-- ENT00307_Test_Bench(ARCH00307_Test_Bench)
--
-- REVISION HISTORY:
--
-- 27-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00307 is
generic ( gen1 : integer := 2;
gen2 : integer := 4) ;
end ENT00307 ;
architecture ARCH00307 of ENT00307 is
-- this tests 3.2.2 (6)
function f ( v1, v2 : integer ) return integer is
type t1 is array (v1 to 10) of boolean;
type t2 is array (v1 to v2) of bit;
type t3 is array (1 to v2) of integer;
type rec is record
a1 : t1 ;
a2 : t2 ;
a3 : t3 ;
end record ;
variable x1 : t1 ;
variable x2 : t2 ;
variable x3 : t3 ;
variable r : rec ;
variable z : integer := 0 ;
begin
for i in v1 to 10 loop
x1(i) := boolean'val( i mod 2) ;
end loop ;
for i in v1 to v2 loop
if x1(i) then
x2(i) := '1' ;
else
x2(i) := '0' ;
end if ;
end loop ;
for i in 1 to v2 loop
x3(i) := i ;
end loop ;
r.a1 := x1 ;
r.a2 := x2 ;
r.a3 := x3 ;
for i in 1 to v2 loop
z := z + r.a3(i) ;
end loop ;
if (r.a1(v1) = true) or (r.a1(v1+1) = false) then
return 0 ;
elsif (r.a2(v1) = '1') or (r.a2(v2) = '0') then
return 0 ;
else
return z ;
end if ;
end f ;
begin
P :
process
type t1 is array (1 to 10) of boolean;
type t2 is array (gen1 to gen2) of bit;
-- this tests 3.2.2 (1) and 3.2.2 (3)
type record_with_one_decl is record
b : boolean ;
end record ;
variable r_1 : record_with_one_decl ;
-- this tests 3.2.2 (2)
type record_with_many_decls is record
bi : bit ;
bo : boolean ;
i : integer ;
c : character ;
e : t_enum1 ;
end record ;
variable r_2 : record_with_many_decls ;
-- this tests 3.2.2 (4)
type record_with_one_decl_many_elements is record
b1,b2,b3 : boolean ;
end record ;
variable r_1_2 : record_with_one_decl_many_elements ;
-- this tests 3.2.2 (5)
type record_with_array_elements is record
a1 : t1 ;
a2 : t2 ;
end record ;
variable r_2a : record_with_array_elements ;
begin
r_1.b := true ;
r_2.bi := '1' ;
r_2.bo := true ;
r_2.i := 5 ;
r_2.c := 'x' ;
r_2.e := en3 ;
r_1_2.b1 := true ;
r_1_2.b2 := false ;
r_1_2.b3 := true ;
for i in 1 to 10 loop
r_2a.a1(i) := boolean'val( i mod 2) ;
end loop ;
for i in gen1 to gen2 loop
if r_2a.a1(i) then
r_2a.a2(i) := '1' ;
else
r_2a.a2(i) := '0' ;
end if ;
end loop ;
test_report ( "ARCH00307" ,
"Record types" ,
(f (2, 3) = 6) and
(r_1.b = true ) and
(r_2.bi = '1') and
(r_2.bo = true) and
(r_2.i = 5) and
(r_2.c = 'x') and
(r_2.e = en3) and
(r_1_2.b1 = true) and
(r_1_2.b2 = false) and
(r_1_2.b3 = true) and
(r_2a.a1(1) = true) and
(r_2a.a1(2) = false) and
(r_2a.a1(9) = true) and
(r_2a.a1(10) = false) and
(r_2a.a2(gen1) = '0') and
(r_2a.a2(gen1+1) = '1') and
(r_2a.a2(gen2) = '0')
) ;
wait ;
end process P ;
end ARCH00307 ;
entity ENT00307_Test_Bench is
end ENT00307_Test_Bench ;
architecture ARCH00307_Test_Bench of ENT00307_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00307 ( ARCH00307 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00307_Test_Bench ;
|
-------------------------------------------------------------------------------
-- Title : Title String Testbench
-------------------------------------------------------------------------------
-- Author : AUTHOR
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013, AUTHOR
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity entity_name_tb is
end entity entity_name_tb;
-------------------------------------------------------------------------------
architecture behavourial of entity_name_tb is
-- component generics
constant PARAM : natural := 42;
-- component ports
-- clock
signal Clk : std_logic := '1';
begin -- architecture behavourial
-- component instantiation
DUT: entity work.entity_name
generic map (
PARAM => PARAM)
port map (
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc: process
begin
-- insert signal assignments here
wait until Clk = '1';
end process WaveGen_Proc;
end architecture behavourial;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2175.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02175ent IS
END c07s02b05x00p01n01i02175ent;
ARCHITECTURE c07s02b05x00p01n01i02175arch OF c07s02b05x00p01n01i02175ent IS
BEGIN
TESTING: PROCESS
constant x1: real := + 10.0;
BEGIN
assert NOT(x1=+10.0)
report "***PASSED TEST: c07s02b05x00p01n01i02175"
severity NOTE;
assert (x1=+10.0)
report "***FAILED TEST: c07s02b05x00p01n01i02175 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02175arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2175.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02175ent IS
END c07s02b05x00p01n01i02175ent;
ARCHITECTURE c07s02b05x00p01n01i02175arch OF c07s02b05x00p01n01i02175ent IS
BEGIN
TESTING: PROCESS
constant x1: real := + 10.0;
BEGIN
assert NOT(x1=+10.0)
report "***PASSED TEST: c07s02b05x00p01n01i02175"
severity NOTE;
assert (x1=+10.0)
report "***FAILED TEST: c07s02b05x00p01n01i02175 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02175arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2175.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02175ent IS
END c07s02b05x00p01n01i02175ent;
ARCHITECTURE c07s02b05x00p01n01i02175arch OF c07s02b05x00p01n01i02175ent IS
BEGIN
TESTING: PROCESS
constant x1: real := + 10.0;
BEGIN
assert NOT(x1=+10.0)
report "***PASSED TEST: c07s02b05x00p01n01i02175"
severity NOTE;
assert (x1=+10.0)
report "***FAILED TEST: c07s02b05x00p01n01i02175 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02175arch;
|
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2
-- Module Version: 5.7
--/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll_4_usb -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 12.000 -mdiv 1 -ndiv 4 -trimp 0 -phasep 0 -trimp_r -adiv 16 -phase_cntl STATIC -rst -fb_mode 1 -fracn 6292
-- Tue Jul 17 16:59:57 2018
library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library MACHXO3L;
use MACHXO3L.components.all;
-- synopsys translate_on
entity pll_4_usb is
port (
CLKI: in std_logic;
RST: in std_logic;
CLKOP: out std_logic);
end pll_4_usb;
architecture Structure of pll_4_usb is
-- internal signal declarations
signal LOCK: std_logic;
signal CLKOP_t: std_logic;
signal scuba_vlo: std_logic;
-- local component declarations
component VLO
port (Z: out std_logic);
end component;
component EHXPLLJ
generic (INTFB_WAKE : in String; DDRST_ENA : in String;
DCRST_ENA : in String; MRST_ENA : in String;
PLLRST_ENA : in String; DPHASE_SOURCE : in String;
STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String;
OUTDIVIDER_MUXC2 : in String;
OUTDIVIDER_MUXB2 : in String;
OUTDIVIDER_MUXA2 : in String;
PREDIVIDER_MUXD1 : in Integer;
PREDIVIDER_MUXC1 : in Integer;
PREDIVIDER_MUXB1 : in Integer;
PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String;
PLL_LOCK_MODE : in Integer;
CLKOS_TRIM_DELAY : in Integer;
CLKOS_TRIM_POL : in String;
CLKOP_TRIM_DELAY : in Integer;
CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer;
FRACN_ENABLE : in String; FEEDBK_PATH : in String;
CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer;
CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer;
CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer;
CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer;
VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String;
VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String;
CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String;
CLKOS_ENABLE : in String; CLKOP_ENABLE : in String;
CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer;
CLKOS_DIV : in Integer; CLKOP_DIV : in Integer;
CLKFB_DIV : in Integer; CLKI_DIV : in Integer);
port (CLKI: in std_logic; CLKFB: in std_logic;
PHASESEL1: in std_logic; PHASESEL0: in std_logic;
PHASEDIR: in std_logic; PHASESTEP: in std_logic;
LOADREG: in std_logic; STDBY: in std_logic;
PLLWAKESYNC: in std_logic; RST: in std_logic;
RESETM: in std_logic; RESETC: in std_logic;
RESETD: in std_logic; ENCLKOP: in std_logic;
ENCLKOS: in std_logic; ENCLKOS2: in std_logic;
ENCLKOS3: in std_logic; PLLCLK: in std_logic;
PLLRST: in std_logic; PLLSTB: in std_logic;
PLLWE: in std_logic; PLLADDR4: in std_logic;
PLLADDR3: in std_logic; PLLADDR2: in std_logic;
PLLADDR1: in std_logic; PLLADDR0: in std_logic;
PLLDATI7: in std_logic; PLLDATI6: in std_logic;
PLLDATI5: in std_logic; PLLDATI4: in std_logic;
PLLDATI3: in std_logic; PLLDATI2: in std_logic;
PLLDATI1: in std_logic; PLLDATI0: in std_logic;
CLKOP: out std_logic; CLKOS: out std_logic;
CLKOS2: out std_logic; CLKOS3: out std_logic;
LOCK: out std_logic; INTLOCK: out std_logic;
REFCLK: out std_logic; CLKINTFB: out std_logic;
DPHSRC: out std_logic; PLLACK: out std_logic;
PLLDATO7: out std_logic; PLLDATO6: out std_logic;
PLLDATO5: out std_logic; PLLDATO4: out std_logic;
PLLDATO3: out std_logic; PLLDATO2: out std_logic;
PLLDATO1: out std_logic; PLLDATO0: out std_logic);
end component;
attribute FREQUENCY_PIN_CLKOP : string;
attribute FREQUENCY_PIN_CLKI : string;
attribute ICP_CURRENT : string;
attribute LPF_RESISTOR : string;
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "49.152100";
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "12.000000";
attribute ICP_CURRENT of PLLInst_0 : label is "5";
attribute LPF_RESISTOR of PLLInst_0 : label is "16";
attribute syn_keep : boolean;
attribute NGD_DRC_MASK : integer;
attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
PLLInst_0: EHXPLLJ
generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED",
MRST_ENA=> "DISABLED", PLLRST_ENA=> "ENABLED", INTFB_WAKE=> "DISABLED",
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0,
CLKOS2_FPHASE=> 0, CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0,
CLKOS_CPHASE=> 0, CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 15,
PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=> 6292,
FRACN_ENABLE=> "ENABLED", OUTDIVIDER_MUXD2=> "DIVD",
PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "DISABLED",
OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED",
CLKOS2_ENABLE=> "DISABLED", OUTDIVIDER_MUXB2=> "DIVB",
PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "DISABLED",
OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "DISABLED",
CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, CLKOS2_DIV=> 1,
CLKOS_DIV=> 1, CLKOP_DIV=> 16, CLKFB_DIV=> 4, CLKI_DIV=> 1,
FEEDBK_PATH=> "CLKOP")
port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo,
PLLWAKESYNC=>scuba_vlo, RST=>RST, RESETM=>scuba_vlo,
RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo,
ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo,
PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo,
PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo,
PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo,
PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo,
PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo,
PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo,
PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo,
PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open,
CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
REFCLK=>open, CLKINTFB=>open, DPHSRC=>open, PLLACK=>open,
PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open,
PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open,
PLLDATO1=>open, PLLDATO0=>open);
CLKOP <= CLKOP_t;
end Structure;
-- synopsys translate_off
library MACHXO3L;
configuration Structure_CON of pll_4_usb is
for Structure
for all:VLO use entity MACHXO3L.VLO(V); end for;
for all:EHXPLLJ use entity MACHXO3L.EHXPLLJ(V); end for;
end for;
end Structure_CON;
-- synopsys translate_on
|
entity test is
type type_test is range 0 to 2#1.1#2; -- here is the missing e between 2nd hash and 2
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: blk_mem_40K_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY blk_mem_40K_tb IS
END ENTITY;
ARCHITECTURE blk_mem_40K_tb_ARCH OF blk_mem_40K_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
blk_mem_40K_synth_inst:ENTITY work.blk_mem_40K_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: blk_mem_40K_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY blk_mem_40K_tb IS
END ENTITY;
ARCHITECTURE blk_mem_40K_tb_ARCH OF blk_mem_40K_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
blk_mem_40K_synth_inst:ENTITY work.blk_mem_40K_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
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