content stringlengths 1 1.04M ⌀ |
|---|
context IEEE_BIT_CONTEXT is
library IEEE;
use IEEE.NUMERIC_BIT.all;
end context IEEE_BIT_CONTEXT;
|
context IEEE_BIT_CONTEXT is
library IEEE;
use IEEE.NUMERIC_BIT.all;
end context IEEE_BIT_CONTEXT;
|
context IEEE_BIT_CONTEXT is
library IEEE;
use IEEE.NUMERIC_BIT.all;
end context IEEE_BIT_CONTEXT;
|
--
-- File Name: TranscriptPkg.vhd
-- Design Unit Name: TranscriptPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
--
-- Description:
-- Define file identifier TranscriptFile... |
-----------------------------------------------------------------------------------------------------------
--
-- MILK COPROCESSOR BASIC DEFINITIONS
--
-- This file contains basic parameters definitions.
--
-- Created by Claudio Brunelli, 2004
--
---------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity dft_out_fsm is
port (
reset : in std_logic;
clk : in std_logic;
dft_ce : out std_logic;
dft_dout : in std_logic_vector(31 downto 0);
dft_fd_out : in std_logic;
fifo_data : out std_logic_... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lifo is
port (
x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0) :="0000";
clk : in std_logic;
wr : in std_logic; -- wr =1 to write wr = 0 to read
empty, full : out std_logic... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ArithmeticalLogicalLeftShifter_x16 is
Port (
input : STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end ArithmeticalLogicalLeftShifter_x16;
architecture skeleton of ArithmeticalLogicalLeftShifter_x16 is
begin
process(input) is... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use I... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 - 2012 Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_985 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_985;
architecture augh of cmp_985 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_985 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_985;
architecture augh of cmp_985 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief This file implements RF-controller entity axi_rfctrl.
------------------------------------------... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief This file implements RF-controller entity axi_rfctrl.
------------------------------------------... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:45:06 2014
-- Host : CE-2013-124 running 64-bit Service Pa... |
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your opti... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
------------------------------------------------------------------------------------------------------------------------
-- Simple Port I/O
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions... |
------------------------------------------------------------------------------------------------------------------------
-- Simple Port I/O
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions... |
------------------------------------------------------------------------------------------------------------------------
-- Simple Port I/O
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions... |
-------------------------------------------------------------------------------
-- Entity: mcu_pkg
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- VHDL package for definition of design parameters and types used throughout
-- the MCU.
--------------------... |
library ieee;
use ieee.std_logic_1164.all;
entity mux_2to1_11bit is
port ( data0: in std_logic_vector (10 downto 0);
data1: in std_logic_vector (10 downto 0);
sel: in std_logic;
data_out: out std_logic_vector(10 downto 0));
end mux_2to1_11bit;
architecture B... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific con... |
entity block1 is
end entity;
architecture test of block1 is
signal u, v, w: integer;
begin
process is
begin
u <= 1;
wait for 1 ns;
u <= 2;
wait;
end process;
a: block is
signal x : integer;
begin
x <= u + 2;
v <= x;
end block;
b... |
entity block1 is
end entity;
architecture test of block1 is
signal u, v, w: integer;
begin
process is
begin
u <= 1;
wait for 1 ns;
u <= 2;
wait;
end process;
a: block is
signal x : integer;
begin
x <= u + 2;
v <= x;
end block;
b... |
entity block1 is
end entity;
architecture test of block1 is
signal u, v, w: integer;
begin
process is
begin
u <= 1;
wait for 1 ns;
u <= 2;
wait;
end process;
a: block is
signal x : integer;
begin
x <= u + 2;
v <= x;
end block;
b... |
entity block1 is
end entity;
architecture test of block1 is
signal u, v, w: integer;
begin
process is
begin
u <= 1;
wait for 1 ns;
u <= 2;
wait;
end process;
a: block is
signal x : integer;
begin
x <= u + 2;
v <= x;
end block;
b... |
entity block1 is
end entity;
architecture test of block1 is
signal u, v, w: integer;
begin
process is
begin
u <= 1;
wait for 1 ns;
u <= 2;
wait;
end process;
a: block is
signal x : integer;
begin
x <= u + 2;
v <= x;
end block;
b... |
-------------------------------------------------------------------------------
-- Title : UART Testbench support procedures
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright ... |
-------------------------------------------------------------------------------
-- Title : UART Testbench support procedures
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright ... |
-------------------------------------------------------------------------------
-- axi_cdma_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- -------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 15.1
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
package wishbone_pkg is
constant c_wishbone_address_width : integer := 32;
constant c_wishbone_data_width : integer := 32;
subtype t_wishbone_address is
std_logic_vector(c_wishbone_address_width... |
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture RTL;
-- This should not fail
arc... |
----------------------------------------------------------------------
-- brdLexSwx (for Fusion Embeded Dev Kit )
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
--------------------------------------------------------... |
architecture RTL of ErrorBit is
signal ErrorBitSet : STD_LOGIC;
begin
ErrorInd: process (Clk_i, Reset_i_n, ErrorReset_i)
begin
if (Reset_i_n ='0') then
ErrorBitSet <= '0';
elsif(rising_edge(Clk_i)) then
if (ErrorReset_i = '1') then
ErrorBitSet <= '0';
else
-- hold statu... |
entity toplevel2 is
generic (
I : integer;
S : string );
end entity;
architecture test of toplevel2 is
begin
process is
begin
assert I = integer'value(S);
wait;
end process;
end architecture;
|
entity toplevel2 is
generic (
I : integer;
S : string );
end entity;
architecture test of toplevel2 is
begin
process is
begin
assert I = integer'value(S);
wait;
end process;
end architecture;
|
entity toplevel2 is
generic (
I : integer;
S : string );
end entity;
architecture test of toplevel2 is
begin
process is
begin
assert I = integer'value(S);
wait;
end process;
end architecture;
|
entity toplevel2 is
generic (
I : integer;
S : string );
end entity;
architecture test of toplevel2 is
begin
process is
begin
assert I = integer'value(S);
wait;
end process;
end architecture;
|
entity toplevel2 is
generic (
I : integer;
S : string );
end entity;
architecture test of toplevel2 is
begin
process is
begin
assert I = integer'value(S);
wait;
end process;
end architecture;
|
-- $Id: pdp11_mmu.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
-- $Id: pdp11_mmu.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
-- $Id: iob_reg_o_gen.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
-- $Id: iob_reg_o_gen.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
entity decode2alu_reg is
port(
clk, rst: in std_logic;
noop : in std_logic;
A_in : in std_logic_vector(7 downto 0);
B_in : in std_logic_vector(7 downto 0);
operation_in : in std_logic_vector(4 downto 0);
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:04:14 01/22/2014
-- Design Name:
-- Module Name: /home/tejainece/learnings/xilinx/Multiply16Booth4/Multiply16Booth4_tb.vhd
-- Project Name: Multiply16Booth4
-- Target Device:
-- Too... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.49... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:22 2017
-- Host : DarkCube running 64-bit major re... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_ed_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig ... |
------------------------------------------------------------------------------
-- @file {{ tb.file_name }}
-- @see {{ dut.name }}
-------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity {{ tb.name }} is
end;
architec... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: VHDL package for compone... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: VHDL package for compone... |
------------------------------------------------------------------------------
-- Title : Systolic High Pass FIR Filter
------------------------------------------------------------------------------
-- Author : Daniel Tavares
-- Company : CNPEM LNLS-DIG
-- Created : 2019-11-23
-- Platform : FPGA-generi... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of adc
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SimpleEnum IS
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
s_in0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_in1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:23:38 11/11/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/decode/tbdecode.vhd
-- Project Name: decode
-- Target Device:
-- Tool versions:
-- Description: ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee ;
use ieee.std_logic_1164.all ;
library std;
use std.textio.all;
-- Utility package
package util is
procedure nop( signal clock : in std_logic ; count : in natural ) ;
end package ;
package body util is
procedure nop( signal clock : in std_logic ; count : in natural ) is
begin
... |
-------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may... |
----------------------------------------------------------------------------------
-- Company: Rat Technologies
-- Engineer: Various Rats
--
-- Create Date: 15:06:58 10/02/2013
-- Design Name:
-- Module Name: mux_4to1_programnCounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Des... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_bus_bridge is
generic (
g_addr_width : natural := 8 );
port (
clock_a : in std_logic;
reset_a : in std_logic;
req_a : in t_io_req;
resp_a : out t_io_resp;
c... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LOAD_BALANCER is
PORT (
CORE_ID : IN STD_LOGIC;
ADDRESS_A_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LOAD_BALANCER is
PORT (
CORE_ID : IN STD_LOGIC;
ADDRESS_A_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_... |
---------------------------------------------------------------------
-- TITLE: NoC_Node
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- ORIGNAL FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without war... |
---------------------------------------------------------------------
-- TITLE: NoC_Node
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- ORIGNAL FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without war... |
---------------------------------------------------------------------
-- TITLE: NoC_Node
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- ORIGNAL FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without war... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_disp.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : Block memory-based Decoder disparity logic
--
-- Company : Xilinx... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
library work;
use work.sqrt_package.all;
entity euclidean is
port(
input1values, input2values : in std_logic_vector(127 downto 0);
distance : out std_logic_vector(31 downto 0)
);
end euclidean;
architecture behavioural of euclidean is
signal... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
architecture rtl of fifo is
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_types.all;
entity VGA_ROM is
generic (
contents : vga_memory
);
port (
clock : in std_logic;
enable : in std_logic;
address : in natural range vga_memory'range;
data : out std_logic
);
end entity VGA_ROM;
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_ps2 is
end tb_ps2;
architecture behav of tb_ps2 is
component clk_res_gen is
port(
clk_50 : out std_logic;
rst : ou... |
-- ----------------------------------------------------------------------------
-- Entity for final bitmap representation
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- --------... |
-- NEED RESULT: ARCH00307: Record types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TES... |
-------------------------------------------------------------------------------
-- Title : Title String Testbench
-------------------------------------------------------------------------------
-- Author : AUTHOR
-- Standard : VHDL'93/02
-----------------------------------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2
-- Module Version: 5.7
--/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll_4_usb -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 12.000 -mdiv 1 -ndiv 4 -trimp 0 -phasep 0 -trimp_r -adiv 16 -phase_cntl STATIC -rst -fb_mode 1 -fracn 629... |
entity test is
type type_test is range 0 to 2#1.1#2; -- here is the missing e between 2nd hash and 2
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file co... |
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