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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.io_bus_pkg.all;
package io_bus_bfm_pkg is
type t_io_bus_bfm_object;
type p_io_bus_bfm_object is access t_io_bus_bfm_object;
type t_io_bfm_command is ( e_io_none, e_io_read, e_io_write );
type t_io_bus_bfm_object is record
next_bfm : p_io_bus_bfm_object;
name : string(1 to 256);
command : t_io_bfm_command;
address : unsigned(19 downto 0);
data : std_logic_vector(7 downto 0);
end record;
------------------------------------------------------------------------------------
shared variable io_bus_bfms : p_io_bus_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
procedure bind_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
------------------------------------------------------------------------------------
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
procedure io_read_32(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(31 downto 0));
procedure io_write_32(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(31 downto 0));
end io_bus_bfm_pkg;
package body io_bus_bfm_pkg is
procedure register_io_bus_bfm(named : string;
variable pntr : inout p_io_bus_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_io_bus_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name(named'range) := named;
-- add this pointer to the head of the linked list
if io_bus_bfms = null then -- first entry
io_bus_bfms := pntr;
else -- insert new entry
pntr.next_bfm := io_bus_bfms;
io_bus_bfms := pntr;
end if;
end register_io_bus_bfm;
procedure bind_io_bus_bfm(named : string;
variable pntr : inout p_io_bus_bfm_object) is
variable p : p_io_bus_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := io_bus_bfms; -- start at the root
L1: while p /= null loop
if p.name(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_io_bus_bfm;
------------------------------------------------------------------------------
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(19 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
io.address := a_i;
io.command := e_io_read;
while io.command /= e_io_none loop
wait for 10 ns;
end loop;
data := io.data;
end procedure;
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(19 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
io.address := a_i;
io.command := e_io_write;
io.data := data;
while io.command /= e_io_none loop
wait for 10 ns;
end loop;
end procedure;
procedure io_write_32(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : std_logic_vector(31 downto 0)) is
begin
io_write(io, addr+0, data(7 downto 0));
io_write(io, addr+1, data(15 downto 8));
io_write(io, addr+2, data(23 downto 16));
io_write(io, addr+3, data(31 downto 24));
end procedure;
procedure io_read_32(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : out std_logic_vector(31 downto 0)) is
begin
io_read(io, addr+0, data(7 downto 0));
io_read(io, addr+1, data(15 downto 8));
io_read(io, addr+2, data(23 downto 16));
io_read(io, addr+3, data(31 downto 24));
end procedure;
end;
------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- $Id: opb_slave.vhd,v 1.1.2.1 2008/12/17 19:04:49 mlovejoy Exp $
-------------------------------------------------------------------------------
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2006, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-- Filename: opb_slave.vhd
--
-- Description: This block maintains state about the current status of
-- plbv46 write operations, the state of plbv46 read
-- operations and the availability of prefetch data in the
-- LocalLink read buffer. It also provides a transaction
-- timeout timer in the event that read data is never claimed
-- or write data can't make it onto the PLBv46 bus.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
--
--
-------------------------------------------------------------------------------
-- Author: TRD
-- Revision: $Revision: 1.1.2.1 $
-- Date: $11/06/2006$
--
-- History:
-- TRD 11/06/2006 Initial V46 Version
-- MLL 09/02/2008 Rev`d to proc_common v3, added coverage/off/on
-- statements, new v1.01.a version and CHANGELOG
-- removed
-- MLL 12/17/2008 Legal header updated and Changelog
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY proc_common_v3_00_a;
USE proc_common_v3_00_a.family.ALL; -- need C_FAMILY definitions
-------------------------------------------------------------------------------
ENTITY opb_slave IS
GENERIC (
-- OPB Address range definition
C_NUM_ADDR_RNG : integer RANGE 1 TO 4 := 1; -- Number of Address Ranges
C_RNG0_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG0_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG1_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG1_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG2_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG2_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG3_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG3_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
-- BRIDGE CONFIGURATION
C_BUS_CLOCK_PERIOD_RATIO : integer RANGE 1 TO 2 := 1;
-- PLB I/O Specification
C_FAMILY : string := "virtex4" -- Xilinx FPGA Family Type spartan3, virtex4,virtex5
);
PORT (
-- OPB slave to Bridge Interface
brdg_block : IN std_logic; -- bridge block
brdg_prefetch_cmplt : IN std_logic; -- bridge prefetch complete
brdg_prefetch_status : IN std_logic; -- bridge prefetch status
opbs_prefetch_req : OUT std_logic; -- opb slave prefetch request
opbs_type : OUT std_logic; -- opb slave transaction request type
opbs_prefetch_clr : OUT std_logic; -- opb slave prefetch clear
opbs_postedwr_clr : OUT std_logic; -- opb slave posted write clear
opbs_trans_addr : OUT std_logic_vector(0 TO 31); -- opb slave transaction address
opbs_length : OUT std_logic_vector(0 TO 11); -- opb slave transaction length
opbs_postedwrt_req : OUT std_logic; -- opb slave posted write request
opbs_be : OUT std_logic_vector(0 TO 3); -- opb slave byte enable
-- Local Link Read Buffer
bfs_data : IN std_logic_vector(0 TO 31); -- Read data output to user logic
bfs_sof_n : IN std_logic; -- Active low signal indicating the starting data beat of a read local link transfer (unused by slave)
bfs_eof_n : IN std_logic; -- Active low signal indicating the ending data beat of a Read local link transfer. (Unused by slave)
bfs_src_rdy_n : IN std_logic; -- Asserts active low to indicate the presence of valid data on signal bfs_data.
bfs_src_dsc_n : IN std_logic; -- Active low signal indicating that the read local link source (master) needs to discontinue the transfer. (Unused. Drive high)
bfs_dst_rdy_n : OUT std_logic; -- Destination (ie the slave) asserts active low to signal it is ready to take valid data on bfs_data.
bfs_dst_dsc_n : OUT std_logic; -- Active low signal that the read local link destination needs to discontinue the transfer.
-- Local Link Write Buffer
bfd_data : OUT std_logic_vector(0 TO 31);
bfd_sof_n : OUT std_logic;
bfd_eof_n : OUT std_logic;
bfd_src_rdy_n : OUT std_logic;
bfd_src_dsc_n : OUT std_logic;
bfd_dst_rdy_n : IN std_logic;
bfd_dst_dsc_n : IN std_logic;
-- OPB Slave Interface
OPB_Select : IN std_logic; -- OPB Master select
OPB_RNW : IN std_logic; -- OPB Read not Write
OPB_BE : IN std_logic_vector(0 TO (32/8)-1); -- OPB transaction byte enables
OPB_seqAddr : IN std_logic; -- OPB sequential address
OPB_DBus : IN std_logic_vector(0 TO 32-1); -- OPB master data bus
OPB_ABus : IN std_logic_vector(0 TO 32-1); -- OPB Slave address bus
Sl_xferAck : OUT std_logic; -- OPB Slave transfer acknowledgement
Sl_errAck : OUT std_logic; -- OPB Slave transaction error acknowledgement
Sl_retry : OUT std_logic; -- OPB Slave transaction retry
Sl_ToutSup : OUT std_logic; -- OPB Slave timeout suppress
Sl_DBus : OUT std_logic_vector(0 TO 32-1); -- OPB Slave data bus
-- System Interface
MPLB_rst : IN std_logic; -- plb reset
MPLB_clk : IN std_logic; -- plb clock
SOPB_rst : IN std_logic; -- OPB reset
SOPB_clk : IN std_logic -- OPB clock
);
END ENTITY opb_slave;
LIBRARY ieee;
USE ieee.numeric_std.ALL;
ARCHITECTURE syn OF opb_slave IS
-- Asserts high when OPB_ABus matches one of the proscribed address ranges
SIGNAL arng_match_ns : std_logic; -- address range match
-- Max Number of words that can be read or written in PLBv46 master burst
-- transaction. This becomes the ack_count as the burst is processed.
SIGNAL max_words_ns : unsigned(0 TO 5-1);
SIGNAL ack_count_ns, ack_count_cs : unsigned(0 TO 5-1);
SIGNAL transaction_addr_cs : std_logic_vector(0 TO 31);
SIGNAL transaction_be_cs : std_logic_vector(0 TO 3);
SIGNAL capture_transaction_addr_ns : std_logic;
SIGNAL prefetch_match_ns : std_logic;
SIGNAL post_writedata_ns : std_logic;
SIGNAL accept_trans_ns : std_logic; -- accept transaction
SIGNAL deny_trans_ns : std_logic; -- deny transaction
SIGNAL retry_read_prefetch_ns, retry_read_prefetch_cs : std_logic;
SIGNAL opbs_postedwrt_req_ns, opbs_postedwrt_req_cs : std_logic;
SIGNAL opbs_prefetch_clr_ns , opbs_prefetch_clr_cs : std_logic;
SIGNAL opbs_postedwr_clr_ns , opbs_postedwr_clr_cs : std_logic;
SIGNAL opbs_prefetch_req_ns , opbs_prefetch_req_cs : std_logic;
SIGNAL opbs_type_ns , opbs_type_cs : std_logic;
SIGNAL opbs_length_ns , opbs_length_cs : unsigned(0 TO 11);
SIGNAL Sl_xferAck_ns, Sl_xferAck_cs : std_logic;
SIGNAL Sl_errAck_ns , Sl_errAck_cs : std_logic;
SIGNAL Sl_retry_ns , Sl_retry_cs : std_logic;
SIGNAL bfs_dst_rdy_n_ns, bfs_dst_rdy_n_cs : std_logic;
SIGNAL bfs_data_cs : std_logic_vector(0 TO 32-1);
SIGNAL bfd_sof_n_ns, bfd_sof_n_cs : std_logic;
SIGNAL bfd_eof_n_ns, bfd_eof_n_cs : std_logic;
SIGNAL bfd_src_rdy_n_ns, bfd_src_rdy_n_cs : std_logic;
SIGNAL bfd_data_cs : std_logic_vector(0 TO 32-1);
BEGIN
----------------------------------------------------------------------------
-- ABUS_DECODE
--
-- An internal block rather then an external block (entity+arch) makes good
-- sense here because the internal workings are relevant to the state
-- machine operation. Placing the logic externally makes the guts harder to
-- reference. Plus we get a new namespace for the necessary
-- functions+signals.
----------------------------------------------------------------------------
abus_decode : BLOCK IS
--
-- 0 31
-- | |
-- +---------------------------------+
-- | j | k | OPB_Abus breakdown
-- +---------------------------------+
-- | Bits to | memory range |
-- | Compare | block size |
FUNCTION Addr_Bits (x, y : std_logic_vector(0 TO 32-1))
-- Find the number of unique address bits necessary for an address range.
-- This is equal to (32 - block size). For example baseaddr=0x0f00_0000 and
-- highaddr=0x0fff_ffff then the first '1' bit of the xor operation is found at
-- bit index 8. The block size is therefore 2**(32-8) = 2**24.
RETURN integer IS
VARIABLE addr_nor : std_logic_vector(0 TO 32-1);
BEGIN
addr_nor := x XOR y;
FOR i IN 0 TO 32-1 LOOP
IF addr_nor(i) = '1' THEN
RETURN i;
END IF;
END LOOP;
--coverage off
RETURN(32);
--coverage on
END FUNCTION Addr_Bits;
FUNCTION min_j (
CONSTANT j0, j1, j2, j3 : integer RANGE 0 TO 32;
CONSTANT C_NUM_ADDR_RNG : IN integer)
RETURN integer IS
VARIABLE m : integer := 33;
-- The min_j function returns the minimum number of bits used in an address
-- range size calculation amongst the four address ranges. A given "J"
-- value can only participate in the MIN operation if it is enabled. That
-- means C_NUM_ADDR_RNG is high enough to include the given J sub n.
BEGIN
IF (j0 < m AND C_NUM_ADDR_RNG >= 1) THEN m := j0; END IF;
--coverage off
IF (j1 < m AND C_NUM_ADDR_RNG >= 2) THEN m := j1; END IF;
IF (j2 < m AND C_NUM_ADDR_RNG >= 3) THEN m := j2; END IF;
IF (j3 < m AND C_NUM_ADDR_RNG >= 4) THEN m := j3; END IF;
--coverage on
RETURN m;
END FUNCTION min_j;
FUNCTION abus_match (
SIGNAL opb_abus : std_logic_vector;
CONSTANT baseaddr : std_logic_vector;
CONSTANT j : integer RANGE 0 TO 32;
CONSTANT num_addr_rng : integer RANGE 1 TO 4;
CONSTANT rng_num : integer RANGE 0 TO 3)
RETURN std_logic IS
BEGIN
IF (rng_num < num_addr_rng) THEN
-- The baseaddr is valid and can be used in matching. This is
-- necessary because if the address pair isn't used the baseaddr and
-- highaddr don't require values that make sense. This condition
-- protects the elaboration from bad vector ranges.
IF (j = 0) THEN
-- This is the degenerate matching case. it implies that the
-- range is the entire 32-bits so any address will be in the
-- baseaddr to highaddr range.
--coverage off
RETURN '1';
--coverage on
ELSE
IF (OPB_ABus(0 TO j-1) = baseaddr(0 TO J-1)) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END IF;
ELSE
-- baseaddr+highaddr pair isn't in use so no match possible.
RETURN '0';
END IF;
END FUNCTION abus_match;
CONSTANT j0 : integer := addr_bits(C_RNG0_BASEADDR, C_RNG0_HIGHADDR);
CONSTANT j1 : integer := addr_bits(C_RNG1_BASEADDR, C_RNG1_HIGHADDR);
CONSTANT j2 : integer := addr_bits(C_RNG2_BASEADDR, C_RNG2_HIGHADDR);
CONSTANT j3 : integer := addr_bits(C_RNG3_BASEADDR, C_RNG3_HIGHADDR);
CONSTANT minimum_j : integer := min_j(j0, j1, j2, j3, C_NUM_ADDR_RNG);
CONSTANT maximum_k : integer := 32-minimum_j;
CONSTANT d : std_logic_vector(0 TO 32*4-1) := C_RNG0_HIGHADDR & C_RNG1_HIGHADDR & C_RNG2_HIGHADDR & C_RNG3_HIGHADDR;
SIGNAL highaddr_ns, highaddr_cs : std_logic_vector(0 TO 32-1); -- selected high addr range value
SIGNAL s : std_logic_vector(0 TO 4-1);
-- Max K size is when rng is 0 to FFFFFFFF. So the max number of words is
-- 2^(32-2). However, the length is 1-based. IE 1 to 16 not 0 to 15. So we
-- need one more bit to represent the actual number of words. (The decimal
-- value 16 requires 5-bits to represent 10000=16). So the expression for the
-- width must be 2^(32-2+1)
SIGNAL words_to_highaddr : unsigned(1 TO maximum_k-2+1); -- Dealing in words so need -2
SIGNAL OPB_ABus_dly1 : std_logic_vector(0 TO 31);
BEGIN
ASSERT FALSE REPORT "C_NUM_ADDR_RNG = " & integer'image(C_NUM_ADDR_RNG) SEVERITY NOTE;
ASSERT C_NUM_ADDR_RNG < 1 REPORT "rng0 bits to match j0 = " & integer'image(j0) SEVERITY NOTE;
ASSERT C_NUM_ADDR_RNG < 2 REPORT "rng1 bits to match j1 = " & integer'image(j1) SEVERITY NOTE;
ASSERT C_NUM_ADDR_RNG < 3 REPORT "rng2 bits to match j2 = " & integer'image(j2) SEVERITY NOTE;
ASSERT C_NUM_ADDR_RNG < 4 REPORT "rng3 bits to match j3 = " & integer'image(j3) SEVERITY NOTE;
ASSERT FALSE REPORT "minimum j = " & integer'image(minimum_j) SEVERITY NOTE;
ASSERT FALSE REPORT "maximum k = " & integer'image(maximum_k) SEVERITY NOTE;
--coverage off
ASSERT (maximum_k >= 6)
REPORT "The smallest address range must be greater then or equal to 64 bytes in size"
SEVERITY error;
--coverage on
abus_reg : PROCESS (SOPB_clk, SOPB_rst) IS
BEGIN
IF (SOPB_rst = '1') THEN
OPB_ABus_dly1 <= (OTHERS => '0');
ELSIF (rising_edge(SOPB_clk)) THEN
OPB_ABus_dly1 <= OPB_ABus;
END IF;
END PROCESS abus_reg;
-- The address ranges are supposed to be non-overlapping so these
-- comparisons result in a one-hot (or no-hot) signal.
s(0) <= abus_match(OPB_ABus_dly1, C_RNG0_BASEADDR, J0, C_NUM_ADDR_RNG, 0);
s(1) <= abus_match(OPB_ABus_dly1, C_RNG1_BASEADDR, J1, C_NUM_ADDR_RNG, 1);
s(2) <= abus_match(OPB_ABus_dly1, C_RNG2_BASEADDR, J2, C_NUM_ADDR_RNG, 2);
s(3) <= abus_match(OPB_ABus_dly1, C_RNG3_BASEADDR, J3, C_NUM_ADDR_RNG, 3);
arng_match_ns <= s(0) OR s(1) OR s(2) OR s(3);
x_mux_onehot_f : ENTITY proc_common_v3_00_a.mux_onehot_f
GENERIC MAP (
C_DW => 32, -- [integer]
C_NB => 4, -- [integer]
C_FAMILY => C_FAMILY) -- [string]
PORT MAP (
D => D, -- [in std_logic_vector(0 to C_DW*C_NB-1)]
S => S, -- [in std_logic_vector(0 to C_NB-1)]
Y => highaddr_ns); -- [out std_logic_vector(0 to C_DW-1)]
wha_reg : PROCESS (SOPB_clk, SOPB_rst) IS
-- The transaction address register does double duty. It gets captured
-- at a read prefetch or at the start of a write.
BEGIN
IF (SOPB_rst = '1') THEN
words_to_highaddr <= (OTHERS => '0');
highaddr_cs <= (others => '0');
ELSIF (rising_edge(SOPB_clk)) THEN
-- This is kind of a mystical expression. The goal is to count the number
-- of words using the smallest size subtractor that will work
-- irrespective of the size of the address range block of the address
-- range that matched the incoming OPB_ABus value. The one hot mux
-- selects amongst the high addr range constants based on which addr
-- range matched. The "-2" in the express insures that words are
-- counted and not bytes. The "+ 1" is because the count is used in the
-- command request to the plbv46_master and it requires a non-zero based count.
words_to_highaddr <= unsigned('0'&highaddr_cs(minimum_j TO (32-1) -2))
- unsigned('0'&OPB_ABus_dly1(minimum_j TO (32-1) -2))
+ 1;
-- Pipelineing added to meet spartan3e timing requirements.
highaddr_cs <= highaddr_ns;
END IF;
END PROCESS wha_reg;
-- Now, the length of the desired read or write operation that will not
-- overrun the end of the address range is given by min(16,
-- words_to_highaddr). It is a min 16 operation because that is the
-- largest prefetch read or posted write that can be done.
-- Irregardless of the vector width of words_to_highaddr only the least
-- significant 5 bits are needed.
max_words_ns <= words_to_highaddr(maximum_k-2+1-4 TO maximum_k-2+1) WHEN 16 > words_to_highaddr ELSE
to_unsigned(16, 5) AFTER 1 NS;
transAdr_reg : PROCESS (SOPB_clk, SOPB_rst) IS
-- The transaction address register does double duty. It gets captured
-- at a read prefetch or at the start of a write.
BEGIN
IF (SOPB_rst = '1') THEN
transaction_addr_cs <= (OTHERS => '0');
ELSIF (rising_edge(SOPB_clk)) THEN
IF (capture_transaction_addr_ns = '1') THEN
transaction_addr_cs <= OPB_ABus;
transaction_be_cs <= OPB_BE;
END IF;
END IF;
END PROCESS transAdr_reg;
prefetch_match_ns <= '1' WHEN (OPB_ABus_dly1 = transaction_addr_cs)
AND brdg_prefetch_cmplt = '1' ELSE
'0';
post_writedata_ns <= arng_match_ns AND NOT brdg_block AND NOT OPB_RNW;
accept_trans_ns <= post_writedata_ns OR prefetch_match_ns;
deny_trans_ns <= arng_match_ns AND brdg_block AND NOT brdg_prefetch_cmplt;
retry_read_prefetch_ns <= arng_match_ns AND NOT brdg_block AND OPB_RNW;
END BLOCK abus_decode;
-------------------------------------------------------------------------
--
-------------------------------------------------------------------------
sm : BLOCK IS
TYPE state_type IS (IDLE, DECODE, PIPEDLY1, PIPEDLY2, BURST1, BURST, SINGLE, RETRY);
SIGNAL slave_ns, slave_cs : state_type;
BEGIN
NS : PROCESS (
OPB_RNW, OPB_Select, OPB_seqAddr, Sl_errAck_cs, Sl_retry_cs,
Sl_xferAck_cs, accept_trans_ns, ack_count_cs, bfd_dst_rdy_n,
bfs_src_rdy_n, brdg_prefetch_status, brdg_prefetch_cmplt,
deny_trans_ns, max_words_ns,
opbs_length_cs, opbs_postedwr_clr_cs, opbs_postedwrt_req_cs,
opbs_prefetch_clr_cs, opbs_prefetch_req_cs, opbs_type_cs,
retry_read_prefetch_cs, retry_read_prefetch_ns, slave_cs) IS
VARIABLE terminal_ack_count : std_logic;
BEGIN
slave_ns <= slave_cs; -- Always hold state by default
-- Always hold output state by default
opbs_postedwrt_req_ns <= opbs_postedwrt_req_cs;
opbs_prefetch_clr_ns <= opbs_prefetch_clr_cs;
opbs_postedwr_clr_ns <= opbs_postedwr_clr_cs;
opbs_prefetch_req_ns <= opbs_prefetch_req_cs;
opbs_type_ns <= opbs_type_cs;
opbs_length_ns <= opbs_length_cs;
ack_count_ns <= ack_count_cs;
capture_transaction_addr_ns <= '0';
Sl_xferAck_ns <= Sl_xferAck_cs;
Sl_errAck_ns <= Sl_errAck_cs;
Sl_retry_ns <= Sl_retry_cs;
bfs_dst_rdy_n_ns <= '1';
--keep--bfd_src_rdy_n_ns <= '1';
bfd_sof_n_ns <= '1';
bfd_eof_n_ns <= '1';
CASE slave_cs IS
WHEN IDLE =>
opbs_postedwrt_req_ns <= '0';
opbs_prefetch_clr_ns <= '0';
opbs_postedwr_clr_ns <= '0';
opbs_prefetch_req_ns <= '0';
Sl_xferAck_ns <= '0';
Sl_errAck_ns <= '0';
Sl_retry_ns <= '0';
IF (OPB_Select = '1') THEN
slave_ns <= DECODE;
END IF;
WHEN DECODE =>
-- This state is a pipeline delay to match the registering of OPB_ABus
-- (which is necessary to allow enough cycle time for the
-- combinatorial decode logic.)
slave_ns <= PIPEDLY1;
WHEN PIPEDLY1 =>
-- This state is a pipeline delay to match the registering
-- of the length calculation used in computing the number of
-- words to the highaddr of the range. It also represents the
-- delay on the pipeline stage on the input data bus OPB_data
bfd_sof_n_ns <= '0'; -- will be first word if this is a write
IF (NOT OPB_Select) = '1' THEN
-- Better luck next time
slave_ns <= IDLE;
ELSIF (deny_trans_ns = '1') THEN
-- Better luck next time
Sl_retry_ns <= '1';
slave_ns <= RETRY;
ELSE
capture_transaction_addr_ns <= '1';
IF (retry_read_prefetch_ns = '1') THEN
-- We have a winner. Issue the prefetch request to the
-- bridge and retry the transaction to the OPB master.
-- If the OPB read request was issued with seqAddr de-asserted
-- then only request the plbv46_master_burst get a single
-- word as well. This is a fairly high probability
-- asssumption about the behaviour of Xilinx OPB masters.
Sl_retry_ns <= '1';
opbs_type_ns <= OPB_seqAddr;
slave_ns <= PIPEDLY2;
ELSE
IF (accept_trans_ns = '1') THEN
-- Bridge is ready with prefetch data or waiting for a
-- full write buffer.
Sl_retry_ns <= '0';
-- Pass on read prefetch error status
Sl_errAck_ns <= brdg_prefetch_status;
-- The expression should reduce to a '1' but is not
-- strictly reducible to a '1' at all time. This
-- might be a little overkill in trying to be too
-- precise but it exactly matches the necessary
-- LocalLink semantics. Note that the expression
-- should read (not bfd_dst_rdy_n and not
-- bfd_src_rdy_n) or (not bfs_dst_rdy_n and not
-- bfs_srcy_rdy_n). (Ignore the "nots" which are
-- appropriate for the active low signals when
-- reading this to understand.) Both terms just
-- state that a source & destination are ready so
-- the transfer can occur. That is what we need for
-- the acknowledgement!
-- Also, the OPB_seqAddr term is necessary for writes
-- to prevent early assertion of the xferAck. This is a
-- nasty corner case protection term. When a burst
-- write is requested at the last word of a range the
-- only way to know is by checking the max transfer
-- count. That won't be available until after the
-- pipedly state (max_words is pipelined)
Sl_xferAck_ns <= (NOT bfd_dst_rdy_n AND NOT OPB_RNW AND NOT OPB_seqAddr)
OR (OPB_RNW AND NOT bfs_src_rdy_n AND NOT OPB_seqAddr);
slave_ns <= PIPEDLY2;
ELSE
-- Just hang tight waiting for an address match or a
-- de-select or a prefetch match.
NULL;
END IF;
END IF;
END IF;
WHEN PIPEDLY2 =>
-- This state is a pipeline delay to match the registering
-- of the length calculation used in computing the number of
-- words to the highaddr of the range.
capture_transaction_addr_ns <= '0';
IF (OPB_RNW = '1') THEN
-- The plbv46_master_burst ignores the IP2Bus_Mst_length WHEN
-- IP2Bus_Mst_type=0 indicating a single.
opbs_length_ns <= "00000" & max_words_ns & "00";
ELSE
-- Pipelined, so starting with zero insures the proper count
-- at the end of the burst when the posted_wrt_req is made.
opbs_length_ns <= X"000";
END IF;
ack_count_ns <= max_words_ns;
--keep--bfd_src_rdy_n_ns <= '1';
-- Use of the retry_read_prefetch_cs (registered) version of
-- the combinatorial (_ns) signal eliminates a critical path on
-- bfs_dst_rdy_n_ns which becomes a fifo read signal.
IF (retry_read_prefetch_cs = '1') THEN
-- We have a winner. Issue the prefetch request to the
-- bridge and retry the transaction to the OPB master.
-- If the OPB read request was issued with seqAddr de-asserted
-- then only request the plbv46_master_burst get a single
-- word as well. This is a fairly high probability
-- asssumption about the behaviour of Xilinx OPB masters. The
-- prefetch request must assert here rather then in DECODE to
-- avoid a problem in 1:2 clock ratio mode where the
-- assertion caused the brdg_block to assert prematurely
-- (from the faster clock domain) thus cutting off
-- opbs_prefetch_req_ns before the PIPEDLY state was entered.
Sl_retry_ns <= '0';
opbs_type_ns <= OPB_seqAddr;
-- Don't issue the prefetch request if master aborts
-- transaction in this clock. (IE OPB_Select='0')
opbs_prefetch_req_ns <= OPB_Select;
slave_ns <= IDLE;
ELSE
-- For OPB Master aborts
-- 1) the state transition must be to idle
-- 2) the read prefetch buffer must not be touched and the
-- master must still come back and claim the data
-- 3) Nothing has been written to the posted write buffer (bfd)
-- yet so it doesn't have to be cleared
-- 4) prefetch buffer should be cleared since it has data in
-- it.
IF (OPB_seqAddr = '1') THEN
opbs_type_ns <= '1'; -- specify a "burst"
-- Sl_xferAck_cs is qualified by opb_select for the abort
-- case elsewhere.
Sl_xferAck_ns <= (NOT bfd_dst_rdy_n AND NOT OPB_RNW)
OR (OPB_RNW AND NOT bfs_src_rdy_n);
bfs_dst_rdy_n_ns <= NOT OPB_RNW; -- ready to read data
IF (opb_select='1') THEN
slave_ns <= BURST1;
ELSE
slave_ns <= IDLE;
END IF;
ELSE
opbs_type_ns <= '0'; -- specify a "single"
bfs_dst_rdy_n_ns <= NOT OPB_RNW; -- ready to read data
bfd_sof_n_ns <= '0'; -- Is first since this is a single
bfd_eof_n_ns <= '0'; -- Is last since this is a single
opbs_postedwrt_req_ns <= NOT OPB_RNW AND OPB_Select;
opbs_prefetch_clr_ns <= '1';
Sl_xferAck_ns <= '0';
IF (opb_select='1') THEN
slave_ns <= SINGLE;
ELSE
slave_ns <= IDLE;
END IF;
END IF;
END IF;
WHEN BURST1 =>
opbs_length_ns <= opbs_length_cs + 4; -- 1 word = 4 bytes
ack_count_ns <= ack_count_cs - 1;
IF (NOT OPB_Select) = '1' THEN
-- Burst terminated prematurely (Master abort?)
Sl_retry_ns <= '0';
Sl_xferAck_ns <= '0';
opbs_prefetch_clr_ns <= OPB_RNW;
opbs_postedwr_clr_ns <= NOT OPB_RNW;
--keep--bfd_src_rdy_n_ns <= '1'; -- clean shutdown of writes
bfs_dst_rdy_n_ns <= '1'; -- although who cares! buffer is reset momentarily
slave_ns <= IDLE;
ELSE
Sl_retry_ns <= '0';
Sl_xferAck_ns <= (NOT bfd_dst_rdy_n AND NOT OPB_RNW)
OR (OPB_RNW AND NOT bfs_src_rdy_n);
bfs_dst_rdy_n_ns <= NOT OPB_RNW; -- ready to read data
--keep--bfd_src_rdy_n_ns <= OPB_RNW; -- ready to write
bfd_sof_n_ns <= '0';
slave_ns <= burst;
END IF;
WHEN BURST =>
ack_count_ns <= ack_count_cs - 1;
IF (ack_count_cs = 1) THEN
terminal_ack_count := '1';
ELSE
terminal_ack_count := '0';
END IF;
-- issue a retry if there isn't enough data in the fifo to
-- satisfy the request. This might happen if a read meant to
-- claim prefetch data has OPB_seqAddr asserted but the
-- original read had OPB_seqAddr deasserted.
Sl_retry_ns <= '0';
Sl_xferAck_ns <= (NOT bfd_dst_rdy_n AND NOT OPB_RNW)
OR (OPB_RNW AND NOT bfs_src_rdy_n);
bfs_dst_rdy_n_ns <= NOT OPB_RNW; -- ready to read data
--keep--bfd_src_rdy_n_ns <= OPB_RNW; -- ready to write
bfd_sof_n_ns <= '1';
IF (terminal_ack_count='1' OR OPB_SeqAddr = '0' OR OPB_Select = '0') THEN
-- Since xferAck is pipelined (Sl_xferAck<=Sl_xferAck_cs)
-- the ack must turn off here for a burst otherwise it
-- will clobber the next back-to-back transaction.
-- (Supposedly the Xilinx OPB doesn't permit these type of
-- b2b transactions but they fail in simulation without
-- this.) The condition of OPB_Select=0 (master
-- abort) must be handled elsewhere by gating the registered
-- xferAck with OPB_Select.
Sl_xferAck_ns <= '0';
-- HEY! This will be the last ack so make sure the Local Link
-- EOF is set properly. This only works for the lookahead
-- conditions (terminal_ack_count=1 or OPB_seqAddr=0). The
-- condition of OPB_Select=0 (master abort if no xferAcks
-- accepted yet) must be handled elsewhere by gating the
-- registered bfd_eof_n with OPB_Select.
bfd_eof_n_ns <= '0';
--keep--bfd_src_rdy_n_ns <= '1'; -- done w/ writing (using pipelined sig)
opbs_postedwrt_req_ns <=
-- brdg_prefetch_complete=1 would indicate that a read
-- burst was being satisfied. An opb master abort
-- typically causes OPB_RNW -> 0 which can cause an
-- unintentional opbs_postedwrt_req assertion in this
-- state because it thinks a write to the buffer is done.
-- The qualification by brdg_prefetch_complete rather then
-- opb_rnw will prevent that.
NOT brdg_prefetch_cmplt
AND (
-- Make request because
-- ... end of burst
(NOT OPB_seqAddr AND OPB_select)
-- ... master abort. Write data
-- already xferAck'd
OR (NOT OPB_Select)
-- ... buffer will
-- overflow if anymore accepted
OR (terminal_ack_count)
);
opbs_prefetch_clr_ns <= '1';
slave_ns <= IDLE;
IF (OPB_select)='1' THEN
opbs_length_ns <= opbs_length_cs + 4; -- 1 word = 4 bytes
ELSE
-- master abort occured (IE OPB_Select dropped prior to
-- first xferAck) or the Master simply dropped OPB_Select
-- without first dropping OPB_seqAddr so the very last xferAck IS
-- disabled, and the last word is not written to the local
-- link destination buffer (bfd). So length should not get
-- incremented.
null;
END IF;
ELSE
opbs_length_ns <= opbs_length_cs + 4; -- 1 word = 4 bytes
END IF;
WHEN SINGLE =>
opbs_prefetch_clr_ns <= '1';
opbs_postedwrt_req_ns <= '0';
--keep--bfd_src_rdy_n_ns <= '1';
bfd_eof_n_ns <= '0';
bfs_dst_rdy_n_ns <= '1';
Sl_xferAck_ns <= '0';
Sl_retry_ns <= '0';
slave_ns <= IDLE;
WHEN RETRY =>
-- This state is different then the SINGLE state in that the
-- prefetch buffer is not cleared. A retry acknowledgement
-- ends a transaction just like an xferAck does -- just
-- nothing was transfered.
Sl_retry_ns <= '0';
slave_ns <= IDLE;
--coverage off
WHEN OTHERS => NULL;
--coverage on
END CASE;
END PROCESS NS;
cs : PROCESS (SOPB_clk, SOPB_rst) IS
BEGIN
IF (SOPB_rst = '1') THEN
slave_cs <= IDLE;
ack_count_cs <= (OTHERS => '0');
opbs_length_cs <= (OTHERS => '0');
opbs_prefetch_clr_cs <= '0';
opbs_prefetch_req_cs <= '0';
opbs_postedwrt_req_cs <= '0';
opbs_type_cs <= '0';
Sl_xferAck_cs <= '0';
Sl_errAck_cs <= '0';
Sl_retry_cs <= '0';
bfd_sof_n_cs <= '1';
bfd_eof_n_cs <= '1';
bfd_src_rdy_n_cs <= '1';
retry_read_prefetch_cs <= '0';
ELSIF (rising_edge(SOPB_clk)) THEN
slave_cs <= slave_ns;
ack_count_cs <= ack_count_ns;
opbs_length_cs <= opbs_length_ns;
opbs_prefetch_clr_cs <= opbs_prefetch_clr_ns;
opbs_postedwr_clr_cs <= opbs_postedwr_clr_ns;
opbs_prefetch_req_cs <= opbs_prefetch_req_ns;
opbs_postedwrt_req_cs <= opbs_postedwrt_req_ns;
opbs_type_cs <= opbs_type_ns;
Sl_xferAck_cs <= Sl_xferAck_ns;
Sl_errAck_cs <= Sl_errAck_ns;
Sl_retry_cs <= Sl_retry_ns;
bfd_sof_n_cs <= bfd_sof_n_ns;
bfd_eof_n_cs <= bfd_eof_n_ns;
-- bfd_src_rdy_n_cs began to track the Sl_xferAck directly
-- to avoid having the state machine manage it. A later bug
-- fix identified the need to have xferAck drop with OPB_select
-- deasserting (thus signaling an OPB master abort). This necessitated
-- the addition of the OPB_select qualifier here as well. Otherwise,
-- a bug is introduced where a word gets written into the
-- destination buffer even though the xferAck got cut off. That
-- extra word gums up the works for the next transfer.
--keep--bfd_src_rdy_n_cs <= bfd_src_rdy_n_ns;
bfd_src_rdy_n_cs <= NOT (Sl_xferAck_cs AND OPB_Select) OR OPB_RNW;
-- Use of the registered version of the retry_read_prefetch SIGNAL
-- eliminates a critical path inside the PIPEDLY state for reading
-- data out of the Local Link buffer source (prefetch buffer).
retry_read_prefetch_cs <= retry_read_prefetch_ns;
END IF;
END PROCESS cs;
END BLOCK sm;
bfs_dly1 : PROCESS (SOPB_clk) IS
BEGIN
-- The data from local link is registered here and qualified by the
-- combinatorial slave xfer ack condition so that zero is driven when
-- invalid data is present. bfs_data_cs drives the Sl_DBus directly so it
-- must be zero at all other times to avoid clobbering data on the
-- OPB_Dbus distributed to all other opb peripherals (including this one
-- during write operations!) Note that the qualifier expression is
-- redundant. sl_xferack_ns is already conditioned on opb_rnw but for
-- both the read and write case. This redundancy will be removed during
-- synthesis but is convienient here as the concept of sl_xferack as the
-- qualifier is more clear then the underlying expression is.
IF (rising_edge(SOPB_clk)) THEN
IF ( (sl_xferack_ns AND OPB_rnw)='1') THEN
bfs_data_cs <= bfs_data;
ELSE
bfs_data_cs <= (others => '0');
END IF;
END IF;
END PROCESS bfs_dly1;
bfd_dly1 : PROCESS (SOPB_clk) IS
BEGIN
IF (rising_edge(SOPB_clk)) THEN
bfd_data_cs <= OPB_DBus;
END IF;
END PROCESS bfd_dly1;
----------------------------------------------------------------------------
-- Final output assignments from internal combinatorial or registered,
-- control or data paths.
----------------------------------------------------------------------------
-- The slave acknowledgements must be registed by Xilinx convention.
-- Unfortunately, to cover the Master abort case the ack's must be
-- qualified by OPB_Select combinatorially. No way around this.
Sl_xferAck <= Sl_xferAck_cs AND OPB_Select;
Sl_errAck <= Sl_errAck_cs AND OPB_Select;
Sl_retry <= Sl_retry_cs AND OPB_Select;
-- Since the Xilinx implementation of the OPB BUS arbiter and bus structure
-- differs then the true IBM implementation (in order to save on resources)
-- the Sl_DBus must be qualified such that it is all '0' when this slave
-- is not actively outputing data. The primary qualifier is thus Sl_xferAck.
-- The qualification must include OPB_Select as well to account for the CASE
-- of a master abort. bfs_data_cs includes a synchronous reset in the case
-- that Sl_xferAck is deasserted or OPB_rnw=write.
Sl_DBus <= bfs_data_cs WHEN (OPB_Select)='1'
ELSE (OTHERS => '0');
Sl_ToutSup <= '0';
-- The clr signal doesn't need clock domain transition pulse conditioning
-- because remaining on for two MPLB_clk periods (in 1:2 clock period ratio
-- situation) is not a problem. No read transaction can be activated in that
-- time period.
opbs_prefetch_req <= opbs_prefetch_req_cs;
-- pass through - no cross domain conditioning required.
opbs_trans_addr <= transaction_addr_cs;
opbs_be <= transaction_be_cs;
opbs_prefetch_clr <= opbs_prefetch_clr_cs;
opbs_postedwr_clr <= opbs_postedwr_clr_cs;
opbs_type <= opbs_type_cs;
opbs_length <= std_logic_vector(opbs_length_cs);
opbs_postedwrt_req <= opbs_postedwrt_req_cs;
-- LocalLink buffer destination (the posted write buffer) connections
bfd_sof_n <= bfd_sof_n_cs;
-- This "or" gate ensures that, on occasion of na OPB master abort, the last
-- word of data put into the fifo has its end of frame flag set.
bfd_eof_n <= bfd_eof_n_cs AND OPB_select ;
bfd_data <= bfd_data_cs;
bfd_src_dsc_n <= '1'; -- never DISCONNECT
bfd_gen1 : IF (C_BUS_CLOCK_PERIOD_RATIO = 1) GENERATE
-- The registered version of src_rdy is used to track the registered
-- version of OPB_xferAck
bfd_src_rdy_n <= bfd_src_rdy_n_cs;
END GENERATE bfd_gen1;
bfd_gen2 : IF (C_BUS_CLOCK_PERIOD_RATIO = 2) GENERATE
-- This flip flop toggles for one MPLB_clk period whenver the SOPB_clk
-- domain signal is asserted. Note that both signals are active low so an
-- "OR" is used to be an active low input/output AND function.
reg : PROCESS (MPLB_clk) IS
VARIABLE reg_n : std_logic := '0';
BEGIN
IF (rising_edge(MPLB_clk)) THEN
reg_n := NOT reg_n OR bfd_src_rdy_n_cs;
END IF;
bfd_src_rdy_n <= reg_n;
END PROCESS reg;
END GENERATE bfd_gen2;
-- LocalLink buffer source (the read prefetch buffer) connections
bfs_dst_dsc_n <= '1'; -- never DISCONNECT
bfs_gen1 : IF (C_BUS_CLOCK_PERIOD_RATIO = 1) GENERATE
bfs_dst_rdy_n <= bfs_dst_rdy_n_ns;
END GENERATE bfs_gen1;
bfs_gen2 : IF (C_BUS_CLOCK_PERIOD_RATIO = 2) GENERATE
-- This flip flop toggles for one MPLB_clk period whenver the SOPB_clk
-- domain signal is asserted. Note that both signals are active low so an
-- "OR" is used to be an active low input/output AND function.
reg : PROCESS (MPLB_clk) IS
VARIABLE reg_n : std_logic := '0';
BEGIN
IF (rising_edge(MPLB_clk)) THEN
reg_n := NOT reg_n OR bfs_dst_rdy_n_ns;
END IF;
bfs_dst_rdy_n <= reg_n;
END PROCESS reg;
END GENERATE bfs_gen2;
END ARCHITECTURE syn;
|
-------------------------------------------------------------------------------
-- $Id: opb_slave.vhd,v 1.1.2.1 2008/12/17 19:04:49 mlovejoy Exp $
-------------------------------------------------------------------------------
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2006, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-- Filename: opb_slave.vhd
--
-- Description: This block maintains state about the current status of
-- plbv46 write operations, the state of plbv46 read
-- operations and the availability of prefetch data in the
-- LocalLink read buffer. It also provides a transaction
-- timeout timer in the event that read data is never claimed
-- or write data can't make it onto the PLBv46 bus.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
--
--
-------------------------------------------------------------------------------
-- Author: TRD
-- Revision: $Revision: 1.1.2.1 $
-- Date: $11/06/2006$
--
-- History:
-- TRD 11/06/2006 Initial V46 Version
-- MLL 09/02/2008 Rev`d to proc_common v3, added coverage/off/on
-- statements, new v1.01.a version and CHANGELOG
-- removed
-- MLL 12/17/2008 Legal header updated and Changelog
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY proc_common_v3_00_a;
USE proc_common_v3_00_a.family.ALL; -- need C_FAMILY definitions
-------------------------------------------------------------------------------
ENTITY opb_slave IS
GENERIC (
-- OPB Address range definition
C_NUM_ADDR_RNG : integer RANGE 1 TO 4 := 1; -- Number of Address Ranges
C_RNG0_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG0_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG1_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG1_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG2_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG2_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG3_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG3_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
-- BRIDGE CONFIGURATION
C_BUS_CLOCK_PERIOD_RATIO : integer RANGE 1 TO 2 := 1;
-- PLB I/O Specification
C_FAMILY : string := "virtex4" -- Xilinx FPGA Family Type spartan3, virtex4,virtex5
);
PORT (
-- OPB slave to Bridge Interface
brdg_block : IN std_logic; -- bridge block
brdg_prefetch_cmplt : IN std_logic; -- bridge prefetch complete
brdg_prefetch_status : IN std_logic; -- bridge prefetch status
opbs_prefetch_req : OUT std_logic; -- opb slave prefetch request
opbs_type : OUT std_logic; -- opb slave transaction request type
opbs_prefetch_clr : OUT std_logic; -- opb slave prefetch clear
opbs_postedwr_clr : OUT std_logic; -- opb slave posted write clear
opbs_trans_addr : OUT std_logic_vector(0 TO 31); -- opb slave transaction address
opbs_length : OUT std_logic_vector(0 TO 11); -- opb slave transaction length
opbs_postedwrt_req : OUT std_logic; -- opb slave posted write request
opbs_be : OUT std_logic_vector(0 TO 3); -- opb slave byte enable
-- Local Link Read Buffer
bfs_data : IN std_logic_vector(0 TO 31); -- Read data output to user logic
bfs_sof_n : IN std_logic; -- Active low signal indicating the starting data beat of a read local link transfer (unused by slave)
bfs_eof_n : IN std_logic; -- Active low signal indicating the ending data beat of a Read local link transfer. (Unused by slave)
bfs_src_rdy_n : IN std_logic; -- Asserts active low to indicate the presence of valid data on signal bfs_data.
bfs_src_dsc_n : IN std_logic; -- Active low signal indicating that the read local link source (master) needs to discontinue the transfer. (Unused. Drive high)
bfs_dst_rdy_n : OUT std_logic; -- Destination (ie the slave) asserts active low to signal it is ready to take valid data on bfs_data.
bfs_dst_dsc_n : OUT std_logic; -- Active low signal that the read local link destination needs to discontinue the transfer.
-- Local Link Write Buffer
bfd_data : OUT std_logic_vector(0 TO 31);
bfd_sof_n : OUT std_logic;
bfd_eof_n : OUT std_logic;
bfd_src_rdy_n : OUT std_logic;
bfd_src_dsc_n : OUT std_logic;
bfd_dst_rdy_n : IN std_logic;
bfd_dst_dsc_n : IN std_logic;
-- OPB Slave Interface
OPB_Select : IN std_logic; -- OPB Master select
OPB_RNW : IN std_logic; -- OPB Read not Write
OPB_BE : IN std_logic_vector(0 TO (32/8)-1); -- OPB transaction byte enables
OPB_seqAddr : IN std_logic; -- OPB sequential address
OPB_DBus : IN std_logic_vector(0 TO 32-1); -- OPB master data bus
OPB_ABus : IN std_logic_vector(0 TO 32-1); -- OPB Slave address bus
Sl_xferAck : OUT std_logic; -- OPB Slave transfer acknowledgement
Sl_errAck : OUT std_logic; -- OPB Slave transaction error acknowledgement
Sl_retry : OUT std_logic; -- OPB Slave transaction retry
Sl_ToutSup : OUT std_logic; -- OPB Slave timeout suppress
Sl_DBus : OUT std_logic_vector(0 TO 32-1); -- OPB Slave data bus
-- System Interface
MPLB_rst : IN std_logic; -- plb reset
MPLB_clk : IN std_logic; -- plb clock
SOPB_rst : IN std_logic; -- OPB reset
SOPB_clk : IN std_logic -- OPB clock
);
END ENTITY opb_slave;
LIBRARY ieee;
USE ieee.numeric_std.ALL;
ARCHITECTURE syn OF opb_slave IS
-- Asserts high when OPB_ABus matches one of the proscribed address ranges
SIGNAL arng_match_ns : std_logic; -- address range match
-- Max Number of words that can be read or written in PLBv46 master burst
-- transaction. This becomes the ack_count as the burst is processed.
SIGNAL max_words_ns : unsigned(0 TO 5-1);
SIGNAL ack_count_ns, ack_count_cs : unsigned(0 TO 5-1);
SIGNAL transaction_addr_cs : std_logic_vector(0 TO 31);
SIGNAL transaction_be_cs : std_logic_vector(0 TO 3);
SIGNAL capture_transaction_addr_ns : std_logic;
SIGNAL prefetch_match_ns : std_logic;
SIGNAL post_writedata_ns : std_logic;
SIGNAL accept_trans_ns : std_logic; -- accept transaction
SIGNAL deny_trans_ns : std_logic; -- deny transaction
SIGNAL retry_read_prefetch_ns, retry_read_prefetch_cs : std_logic;
SIGNAL opbs_postedwrt_req_ns, opbs_postedwrt_req_cs : std_logic;
SIGNAL opbs_prefetch_clr_ns , opbs_prefetch_clr_cs : std_logic;
SIGNAL opbs_postedwr_clr_ns , opbs_postedwr_clr_cs : std_logic;
SIGNAL opbs_prefetch_req_ns , opbs_prefetch_req_cs : std_logic;
SIGNAL opbs_type_ns , opbs_type_cs : std_logic;
SIGNAL opbs_length_ns , opbs_length_cs : unsigned(0 TO 11);
SIGNAL Sl_xferAck_ns, Sl_xferAck_cs : std_logic;
SIGNAL Sl_errAck_ns , Sl_errAck_cs : std_logic;
SIGNAL Sl_retry_ns , Sl_retry_cs : std_logic;
SIGNAL bfs_dst_rdy_n_ns, bfs_dst_rdy_n_cs : std_logic;
SIGNAL bfs_data_cs : std_logic_vector(0 TO 32-1);
SIGNAL bfd_sof_n_ns, bfd_sof_n_cs : std_logic;
SIGNAL bfd_eof_n_ns, bfd_eof_n_cs : std_logic;
SIGNAL bfd_src_rdy_n_ns, bfd_src_rdy_n_cs : std_logic;
SIGNAL bfd_data_cs : std_logic_vector(0 TO 32-1);
BEGIN
----------------------------------------------------------------------------
-- ABUS_DECODE
--
-- An internal block rather then an external block (entity+arch) makes good
-- sense here because the internal workings are relevant to the state
-- machine operation. Placing the logic externally makes the guts harder to
-- reference. Plus we get a new namespace for the necessary
-- functions+signals.
----------------------------------------------------------------------------
abus_decode : BLOCK IS
--
-- 0 31
-- | |
-- +---------------------------------+
-- | j | k | OPB_Abus breakdown
-- +---------------------------------+
-- | Bits to | memory range |
-- | Compare | block size |
FUNCTION Addr_Bits (x, y : std_logic_vector(0 TO 32-1))
-- Find the number of unique address bits necessary for an address range.
-- This is equal to (32 - block size). For example baseaddr=0x0f00_0000 and
-- highaddr=0x0fff_ffff then the first '1' bit of the xor operation is found at
-- bit index 8. The block size is therefore 2**(32-8) = 2**24.
RETURN integer IS
VARIABLE addr_nor : std_logic_vector(0 TO 32-1);
BEGIN
addr_nor := x XOR y;
FOR i IN 0 TO 32-1 LOOP
IF addr_nor(i) = '1' THEN
RETURN i;
END IF;
END LOOP;
--coverage off
RETURN(32);
--coverage on
END FUNCTION Addr_Bits;
FUNCTION min_j (
CONSTANT j0, j1, j2, j3 : integer RANGE 0 TO 32;
CONSTANT C_NUM_ADDR_RNG : IN integer)
RETURN integer IS
VARIABLE m : integer := 33;
-- The min_j function returns the minimum number of bits used in an address
-- range size calculation amongst the four address ranges. A given "J"
-- value can only participate in the MIN operation if it is enabled. That
-- means C_NUM_ADDR_RNG is high enough to include the given J sub n.
BEGIN
IF (j0 < m AND C_NUM_ADDR_RNG >= 1) THEN m := j0; END IF;
--coverage off
IF (j1 < m AND C_NUM_ADDR_RNG >= 2) THEN m := j1; END IF;
IF (j2 < m AND C_NUM_ADDR_RNG >= 3) THEN m := j2; END IF;
IF (j3 < m AND C_NUM_ADDR_RNG >= 4) THEN m := j3; END IF;
--coverage on
RETURN m;
END FUNCTION min_j;
FUNCTION abus_match (
SIGNAL opb_abus : std_logic_vector;
CONSTANT baseaddr : std_logic_vector;
CONSTANT j : integer RANGE 0 TO 32;
CONSTANT num_addr_rng : integer RANGE 1 TO 4;
CONSTANT rng_num : integer RANGE 0 TO 3)
RETURN std_logic IS
BEGIN
IF (rng_num < num_addr_rng) THEN
-- The baseaddr is valid and can be used in matching. This is
-- necessary because if the address pair isn't used the baseaddr and
-- highaddr don't require values that make sense. This condition
-- protects the elaboration from bad vector ranges.
IF (j = 0) THEN
-- This is the degenerate matching case. it implies that the
-- range is the entire 32-bits so any address will be in the
-- baseaddr to highaddr range.
--coverage off
RETURN '1';
--coverage on
ELSE
IF (OPB_ABus(0 TO j-1) = baseaddr(0 TO J-1)) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END IF;
ELSE
-- baseaddr+highaddr pair isn't in use so no match possible.
RETURN '0';
END IF;
END FUNCTION abus_match;
CONSTANT j0 : integer := addr_bits(C_RNG0_BASEADDR, C_RNG0_HIGHADDR);
CONSTANT j1 : integer := addr_bits(C_RNG1_BASEADDR, C_RNG1_HIGHADDR);
CONSTANT j2 : integer := addr_bits(C_RNG2_BASEADDR, C_RNG2_HIGHADDR);
CONSTANT j3 : integer := addr_bits(C_RNG3_BASEADDR, C_RNG3_HIGHADDR);
CONSTANT minimum_j : integer := min_j(j0, j1, j2, j3, C_NUM_ADDR_RNG);
CONSTANT maximum_k : integer := 32-minimum_j;
CONSTANT d : std_logic_vector(0 TO 32*4-1) := C_RNG0_HIGHADDR & C_RNG1_HIGHADDR & C_RNG2_HIGHADDR & C_RNG3_HIGHADDR;
SIGNAL highaddr_ns, highaddr_cs : std_logic_vector(0 TO 32-1); -- selected high addr range value
SIGNAL s : std_logic_vector(0 TO 4-1);
-- Max K size is when rng is 0 to FFFFFFFF. So the max number of words is
-- 2^(32-2). However, the length is 1-based. IE 1 to 16 not 0 to 15. So we
-- need one more bit to represent the actual number of words. (The decimal
-- value 16 requires 5-bits to represent 10000=16). So the expression for the
-- width must be 2^(32-2+1)
SIGNAL words_to_highaddr : unsigned(1 TO maximum_k-2+1); -- Dealing in words so need -2
SIGNAL OPB_ABus_dly1 : std_logic_vector(0 TO 31);
BEGIN
ASSERT FALSE REPORT "C_NUM_ADDR_RNG = " & integer'image(C_NUM_ADDR_RNG) SEVERITY NOTE;
ASSERT C_NUM_ADDR_RNG < 1 REPORT "rng0 bits to match j0 = " & integer'image(j0) SEVERITY NOTE;
ASSERT C_NUM_ADDR_RNG < 2 REPORT "rng1 bits to match j1 = " & integer'image(j1) SEVERITY NOTE;
ASSERT C_NUM_ADDR_RNG < 3 REPORT "rng2 bits to match j2 = " & integer'image(j2) SEVERITY NOTE;
ASSERT C_NUM_ADDR_RNG < 4 REPORT "rng3 bits to match j3 = " & integer'image(j3) SEVERITY NOTE;
ASSERT FALSE REPORT "minimum j = " & integer'image(minimum_j) SEVERITY NOTE;
ASSERT FALSE REPORT "maximum k = " & integer'image(maximum_k) SEVERITY NOTE;
--coverage off
ASSERT (maximum_k >= 6)
REPORT "The smallest address range must be greater then or equal to 64 bytes in size"
SEVERITY error;
--coverage on
abus_reg : PROCESS (SOPB_clk, SOPB_rst) IS
BEGIN
IF (SOPB_rst = '1') THEN
OPB_ABus_dly1 <= (OTHERS => '0');
ELSIF (rising_edge(SOPB_clk)) THEN
OPB_ABus_dly1 <= OPB_ABus;
END IF;
END PROCESS abus_reg;
-- The address ranges are supposed to be non-overlapping so these
-- comparisons result in a one-hot (or no-hot) signal.
s(0) <= abus_match(OPB_ABus_dly1, C_RNG0_BASEADDR, J0, C_NUM_ADDR_RNG, 0);
s(1) <= abus_match(OPB_ABus_dly1, C_RNG1_BASEADDR, J1, C_NUM_ADDR_RNG, 1);
s(2) <= abus_match(OPB_ABus_dly1, C_RNG2_BASEADDR, J2, C_NUM_ADDR_RNG, 2);
s(3) <= abus_match(OPB_ABus_dly1, C_RNG3_BASEADDR, J3, C_NUM_ADDR_RNG, 3);
arng_match_ns <= s(0) OR s(1) OR s(2) OR s(3);
x_mux_onehot_f : ENTITY proc_common_v3_00_a.mux_onehot_f
GENERIC MAP (
C_DW => 32, -- [integer]
C_NB => 4, -- [integer]
C_FAMILY => C_FAMILY) -- [string]
PORT MAP (
D => D, -- [in std_logic_vector(0 to C_DW*C_NB-1)]
S => S, -- [in std_logic_vector(0 to C_NB-1)]
Y => highaddr_ns); -- [out std_logic_vector(0 to C_DW-1)]
wha_reg : PROCESS (SOPB_clk, SOPB_rst) IS
-- The transaction address register does double duty. It gets captured
-- at a read prefetch or at the start of a write.
BEGIN
IF (SOPB_rst = '1') THEN
words_to_highaddr <= (OTHERS => '0');
highaddr_cs <= (others => '0');
ELSIF (rising_edge(SOPB_clk)) THEN
-- This is kind of a mystical expression. The goal is to count the number
-- of words using the smallest size subtractor that will work
-- irrespective of the size of the address range block of the address
-- range that matched the incoming OPB_ABus value. The one hot mux
-- selects amongst the high addr range constants based on which addr
-- range matched. The "-2" in the express insures that words are
-- counted and not bytes. The "+ 1" is because the count is used in the
-- command request to the plbv46_master and it requires a non-zero based count.
words_to_highaddr <= unsigned('0'&highaddr_cs(minimum_j TO (32-1) -2))
- unsigned('0'&OPB_ABus_dly1(minimum_j TO (32-1) -2))
+ 1;
-- Pipelineing added to meet spartan3e timing requirements.
highaddr_cs <= highaddr_ns;
END IF;
END PROCESS wha_reg;
-- Now, the length of the desired read or write operation that will not
-- overrun the end of the address range is given by min(16,
-- words_to_highaddr). It is a min 16 operation because that is the
-- largest prefetch read or posted write that can be done.
-- Irregardless of the vector width of words_to_highaddr only the least
-- significant 5 bits are needed.
max_words_ns <= words_to_highaddr(maximum_k-2+1-4 TO maximum_k-2+1) WHEN 16 > words_to_highaddr ELSE
to_unsigned(16, 5) AFTER 1 NS;
transAdr_reg : PROCESS (SOPB_clk, SOPB_rst) IS
-- The transaction address register does double duty. It gets captured
-- at a read prefetch or at the start of a write.
BEGIN
IF (SOPB_rst = '1') THEN
transaction_addr_cs <= (OTHERS => '0');
ELSIF (rising_edge(SOPB_clk)) THEN
IF (capture_transaction_addr_ns = '1') THEN
transaction_addr_cs <= OPB_ABus;
transaction_be_cs <= OPB_BE;
END IF;
END IF;
END PROCESS transAdr_reg;
prefetch_match_ns <= '1' WHEN (OPB_ABus_dly1 = transaction_addr_cs)
AND brdg_prefetch_cmplt = '1' ELSE
'0';
post_writedata_ns <= arng_match_ns AND NOT brdg_block AND NOT OPB_RNW;
accept_trans_ns <= post_writedata_ns OR prefetch_match_ns;
deny_trans_ns <= arng_match_ns AND brdg_block AND NOT brdg_prefetch_cmplt;
retry_read_prefetch_ns <= arng_match_ns AND NOT brdg_block AND OPB_RNW;
END BLOCK abus_decode;
-------------------------------------------------------------------------
--
-------------------------------------------------------------------------
sm : BLOCK IS
TYPE state_type IS (IDLE, DECODE, PIPEDLY1, PIPEDLY2, BURST1, BURST, SINGLE, RETRY);
SIGNAL slave_ns, slave_cs : state_type;
BEGIN
NS : PROCESS (
OPB_RNW, OPB_Select, OPB_seqAddr, Sl_errAck_cs, Sl_retry_cs,
Sl_xferAck_cs, accept_trans_ns, ack_count_cs, bfd_dst_rdy_n,
bfs_src_rdy_n, brdg_prefetch_status, brdg_prefetch_cmplt,
deny_trans_ns, max_words_ns,
opbs_length_cs, opbs_postedwr_clr_cs, opbs_postedwrt_req_cs,
opbs_prefetch_clr_cs, opbs_prefetch_req_cs, opbs_type_cs,
retry_read_prefetch_cs, retry_read_prefetch_ns, slave_cs) IS
VARIABLE terminal_ack_count : std_logic;
BEGIN
slave_ns <= slave_cs; -- Always hold state by default
-- Always hold output state by default
opbs_postedwrt_req_ns <= opbs_postedwrt_req_cs;
opbs_prefetch_clr_ns <= opbs_prefetch_clr_cs;
opbs_postedwr_clr_ns <= opbs_postedwr_clr_cs;
opbs_prefetch_req_ns <= opbs_prefetch_req_cs;
opbs_type_ns <= opbs_type_cs;
opbs_length_ns <= opbs_length_cs;
ack_count_ns <= ack_count_cs;
capture_transaction_addr_ns <= '0';
Sl_xferAck_ns <= Sl_xferAck_cs;
Sl_errAck_ns <= Sl_errAck_cs;
Sl_retry_ns <= Sl_retry_cs;
bfs_dst_rdy_n_ns <= '1';
--keep--bfd_src_rdy_n_ns <= '1';
bfd_sof_n_ns <= '1';
bfd_eof_n_ns <= '1';
CASE slave_cs IS
WHEN IDLE =>
opbs_postedwrt_req_ns <= '0';
opbs_prefetch_clr_ns <= '0';
opbs_postedwr_clr_ns <= '0';
opbs_prefetch_req_ns <= '0';
Sl_xferAck_ns <= '0';
Sl_errAck_ns <= '0';
Sl_retry_ns <= '0';
IF (OPB_Select = '1') THEN
slave_ns <= DECODE;
END IF;
WHEN DECODE =>
-- This state is a pipeline delay to match the registering of OPB_ABus
-- (which is necessary to allow enough cycle time for the
-- combinatorial decode logic.)
slave_ns <= PIPEDLY1;
WHEN PIPEDLY1 =>
-- This state is a pipeline delay to match the registering
-- of the length calculation used in computing the number of
-- words to the highaddr of the range. It also represents the
-- delay on the pipeline stage on the input data bus OPB_data
bfd_sof_n_ns <= '0'; -- will be first word if this is a write
IF (NOT OPB_Select) = '1' THEN
-- Better luck next time
slave_ns <= IDLE;
ELSIF (deny_trans_ns = '1') THEN
-- Better luck next time
Sl_retry_ns <= '1';
slave_ns <= RETRY;
ELSE
capture_transaction_addr_ns <= '1';
IF (retry_read_prefetch_ns = '1') THEN
-- We have a winner. Issue the prefetch request to the
-- bridge and retry the transaction to the OPB master.
-- If the OPB read request was issued with seqAddr de-asserted
-- then only request the plbv46_master_burst get a single
-- word as well. This is a fairly high probability
-- asssumption about the behaviour of Xilinx OPB masters.
Sl_retry_ns <= '1';
opbs_type_ns <= OPB_seqAddr;
slave_ns <= PIPEDLY2;
ELSE
IF (accept_trans_ns = '1') THEN
-- Bridge is ready with prefetch data or waiting for a
-- full write buffer.
Sl_retry_ns <= '0';
-- Pass on read prefetch error status
Sl_errAck_ns <= brdg_prefetch_status;
-- The expression should reduce to a '1' but is not
-- strictly reducible to a '1' at all time. This
-- might be a little overkill in trying to be too
-- precise but it exactly matches the necessary
-- LocalLink semantics. Note that the expression
-- should read (not bfd_dst_rdy_n and not
-- bfd_src_rdy_n) or (not bfs_dst_rdy_n and not
-- bfs_srcy_rdy_n). (Ignore the "nots" which are
-- appropriate for the active low signals when
-- reading this to understand.) Both terms just
-- state that a source & destination are ready so
-- the transfer can occur. That is what we need for
-- the acknowledgement!
-- Also, the OPB_seqAddr term is necessary for writes
-- to prevent early assertion of the xferAck. This is a
-- nasty corner case protection term. When a burst
-- write is requested at the last word of a range the
-- only way to know is by checking the max transfer
-- count. That won't be available until after the
-- pipedly state (max_words is pipelined)
Sl_xferAck_ns <= (NOT bfd_dst_rdy_n AND NOT OPB_RNW AND NOT OPB_seqAddr)
OR (OPB_RNW AND NOT bfs_src_rdy_n AND NOT OPB_seqAddr);
slave_ns <= PIPEDLY2;
ELSE
-- Just hang tight waiting for an address match or a
-- de-select or a prefetch match.
NULL;
END IF;
END IF;
END IF;
WHEN PIPEDLY2 =>
-- This state is a pipeline delay to match the registering
-- of the length calculation used in computing the number of
-- words to the highaddr of the range.
capture_transaction_addr_ns <= '0';
IF (OPB_RNW = '1') THEN
-- The plbv46_master_burst ignores the IP2Bus_Mst_length WHEN
-- IP2Bus_Mst_type=0 indicating a single.
opbs_length_ns <= "00000" & max_words_ns & "00";
ELSE
-- Pipelined, so starting with zero insures the proper count
-- at the end of the burst when the posted_wrt_req is made.
opbs_length_ns <= X"000";
END IF;
ack_count_ns <= max_words_ns;
--keep--bfd_src_rdy_n_ns <= '1';
-- Use of the retry_read_prefetch_cs (registered) version of
-- the combinatorial (_ns) signal eliminates a critical path on
-- bfs_dst_rdy_n_ns which becomes a fifo read signal.
IF (retry_read_prefetch_cs = '1') THEN
-- We have a winner. Issue the prefetch request to the
-- bridge and retry the transaction to the OPB master.
-- If the OPB read request was issued with seqAddr de-asserted
-- then only request the plbv46_master_burst get a single
-- word as well. This is a fairly high probability
-- asssumption about the behaviour of Xilinx OPB masters. The
-- prefetch request must assert here rather then in DECODE to
-- avoid a problem in 1:2 clock ratio mode where the
-- assertion caused the brdg_block to assert prematurely
-- (from the faster clock domain) thus cutting off
-- opbs_prefetch_req_ns before the PIPEDLY state was entered.
Sl_retry_ns <= '0';
opbs_type_ns <= OPB_seqAddr;
-- Don't issue the prefetch request if master aborts
-- transaction in this clock. (IE OPB_Select='0')
opbs_prefetch_req_ns <= OPB_Select;
slave_ns <= IDLE;
ELSE
-- For OPB Master aborts
-- 1) the state transition must be to idle
-- 2) the read prefetch buffer must not be touched and the
-- master must still come back and claim the data
-- 3) Nothing has been written to the posted write buffer (bfd)
-- yet so it doesn't have to be cleared
-- 4) prefetch buffer should be cleared since it has data in
-- it.
IF (OPB_seqAddr = '1') THEN
opbs_type_ns <= '1'; -- specify a "burst"
-- Sl_xferAck_cs is qualified by opb_select for the abort
-- case elsewhere.
Sl_xferAck_ns <= (NOT bfd_dst_rdy_n AND NOT OPB_RNW)
OR (OPB_RNW AND NOT bfs_src_rdy_n);
bfs_dst_rdy_n_ns <= NOT OPB_RNW; -- ready to read data
IF (opb_select='1') THEN
slave_ns <= BURST1;
ELSE
slave_ns <= IDLE;
END IF;
ELSE
opbs_type_ns <= '0'; -- specify a "single"
bfs_dst_rdy_n_ns <= NOT OPB_RNW; -- ready to read data
bfd_sof_n_ns <= '0'; -- Is first since this is a single
bfd_eof_n_ns <= '0'; -- Is last since this is a single
opbs_postedwrt_req_ns <= NOT OPB_RNW AND OPB_Select;
opbs_prefetch_clr_ns <= '1';
Sl_xferAck_ns <= '0';
IF (opb_select='1') THEN
slave_ns <= SINGLE;
ELSE
slave_ns <= IDLE;
END IF;
END IF;
END IF;
WHEN BURST1 =>
opbs_length_ns <= opbs_length_cs + 4; -- 1 word = 4 bytes
ack_count_ns <= ack_count_cs - 1;
IF (NOT OPB_Select) = '1' THEN
-- Burst terminated prematurely (Master abort?)
Sl_retry_ns <= '0';
Sl_xferAck_ns <= '0';
opbs_prefetch_clr_ns <= OPB_RNW;
opbs_postedwr_clr_ns <= NOT OPB_RNW;
--keep--bfd_src_rdy_n_ns <= '1'; -- clean shutdown of writes
bfs_dst_rdy_n_ns <= '1'; -- although who cares! buffer is reset momentarily
slave_ns <= IDLE;
ELSE
Sl_retry_ns <= '0';
Sl_xferAck_ns <= (NOT bfd_dst_rdy_n AND NOT OPB_RNW)
OR (OPB_RNW AND NOT bfs_src_rdy_n);
bfs_dst_rdy_n_ns <= NOT OPB_RNW; -- ready to read data
--keep--bfd_src_rdy_n_ns <= OPB_RNW; -- ready to write
bfd_sof_n_ns <= '0';
slave_ns <= burst;
END IF;
WHEN BURST =>
ack_count_ns <= ack_count_cs - 1;
IF (ack_count_cs = 1) THEN
terminal_ack_count := '1';
ELSE
terminal_ack_count := '0';
END IF;
-- issue a retry if there isn't enough data in the fifo to
-- satisfy the request. This might happen if a read meant to
-- claim prefetch data has OPB_seqAddr asserted but the
-- original read had OPB_seqAddr deasserted.
Sl_retry_ns <= '0';
Sl_xferAck_ns <= (NOT bfd_dst_rdy_n AND NOT OPB_RNW)
OR (OPB_RNW AND NOT bfs_src_rdy_n);
bfs_dst_rdy_n_ns <= NOT OPB_RNW; -- ready to read data
--keep--bfd_src_rdy_n_ns <= OPB_RNW; -- ready to write
bfd_sof_n_ns <= '1';
IF (terminal_ack_count='1' OR OPB_SeqAddr = '0' OR OPB_Select = '0') THEN
-- Since xferAck is pipelined (Sl_xferAck<=Sl_xferAck_cs)
-- the ack must turn off here for a burst otherwise it
-- will clobber the next back-to-back transaction.
-- (Supposedly the Xilinx OPB doesn't permit these type of
-- b2b transactions but they fail in simulation without
-- this.) The condition of OPB_Select=0 (master
-- abort) must be handled elsewhere by gating the registered
-- xferAck with OPB_Select.
Sl_xferAck_ns <= '0';
-- HEY! This will be the last ack so make sure the Local Link
-- EOF is set properly. This only works for the lookahead
-- conditions (terminal_ack_count=1 or OPB_seqAddr=0). The
-- condition of OPB_Select=0 (master abort if no xferAcks
-- accepted yet) must be handled elsewhere by gating the
-- registered bfd_eof_n with OPB_Select.
bfd_eof_n_ns <= '0';
--keep--bfd_src_rdy_n_ns <= '1'; -- done w/ writing (using pipelined sig)
opbs_postedwrt_req_ns <=
-- brdg_prefetch_complete=1 would indicate that a read
-- burst was being satisfied. An opb master abort
-- typically causes OPB_RNW -> 0 which can cause an
-- unintentional opbs_postedwrt_req assertion in this
-- state because it thinks a write to the buffer is done.
-- The qualification by brdg_prefetch_complete rather then
-- opb_rnw will prevent that.
NOT brdg_prefetch_cmplt
AND (
-- Make request because
-- ... end of burst
(NOT OPB_seqAddr AND OPB_select)
-- ... master abort. Write data
-- already xferAck'd
OR (NOT OPB_Select)
-- ... buffer will
-- overflow if anymore accepted
OR (terminal_ack_count)
);
opbs_prefetch_clr_ns <= '1';
slave_ns <= IDLE;
IF (OPB_select)='1' THEN
opbs_length_ns <= opbs_length_cs + 4; -- 1 word = 4 bytes
ELSE
-- master abort occured (IE OPB_Select dropped prior to
-- first xferAck) or the Master simply dropped OPB_Select
-- without first dropping OPB_seqAddr so the very last xferAck IS
-- disabled, and the last word is not written to the local
-- link destination buffer (bfd). So length should not get
-- incremented.
null;
END IF;
ELSE
opbs_length_ns <= opbs_length_cs + 4; -- 1 word = 4 bytes
END IF;
WHEN SINGLE =>
opbs_prefetch_clr_ns <= '1';
opbs_postedwrt_req_ns <= '0';
--keep--bfd_src_rdy_n_ns <= '1';
bfd_eof_n_ns <= '0';
bfs_dst_rdy_n_ns <= '1';
Sl_xferAck_ns <= '0';
Sl_retry_ns <= '0';
slave_ns <= IDLE;
WHEN RETRY =>
-- This state is different then the SINGLE state in that the
-- prefetch buffer is not cleared. A retry acknowledgement
-- ends a transaction just like an xferAck does -- just
-- nothing was transfered.
Sl_retry_ns <= '0';
slave_ns <= IDLE;
--coverage off
WHEN OTHERS => NULL;
--coverage on
END CASE;
END PROCESS NS;
cs : PROCESS (SOPB_clk, SOPB_rst) IS
BEGIN
IF (SOPB_rst = '1') THEN
slave_cs <= IDLE;
ack_count_cs <= (OTHERS => '0');
opbs_length_cs <= (OTHERS => '0');
opbs_prefetch_clr_cs <= '0';
opbs_prefetch_req_cs <= '0';
opbs_postedwrt_req_cs <= '0';
opbs_type_cs <= '0';
Sl_xferAck_cs <= '0';
Sl_errAck_cs <= '0';
Sl_retry_cs <= '0';
bfd_sof_n_cs <= '1';
bfd_eof_n_cs <= '1';
bfd_src_rdy_n_cs <= '1';
retry_read_prefetch_cs <= '0';
ELSIF (rising_edge(SOPB_clk)) THEN
slave_cs <= slave_ns;
ack_count_cs <= ack_count_ns;
opbs_length_cs <= opbs_length_ns;
opbs_prefetch_clr_cs <= opbs_prefetch_clr_ns;
opbs_postedwr_clr_cs <= opbs_postedwr_clr_ns;
opbs_prefetch_req_cs <= opbs_prefetch_req_ns;
opbs_postedwrt_req_cs <= opbs_postedwrt_req_ns;
opbs_type_cs <= opbs_type_ns;
Sl_xferAck_cs <= Sl_xferAck_ns;
Sl_errAck_cs <= Sl_errAck_ns;
Sl_retry_cs <= Sl_retry_ns;
bfd_sof_n_cs <= bfd_sof_n_ns;
bfd_eof_n_cs <= bfd_eof_n_ns;
-- bfd_src_rdy_n_cs began to track the Sl_xferAck directly
-- to avoid having the state machine manage it. A later bug
-- fix identified the need to have xferAck drop with OPB_select
-- deasserting (thus signaling an OPB master abort). This necessitated
-- the addition of the OPB_select qualifier here as well. Otherwise,
-- a bug is introduced where a word gets written into the
-- destination buffer even though the xferAck got cut off. That
-- extra word gums up the works for the next transfer.
--keep--bfd_src_rdy_n_cs <= bfd_src_rdy_n_ns;
bfd_src_rdy_n_cs <= NOT (Sl_xferAck_cs AND OPB_Select) OR OPB_RNW;
-- Use of the registered version of the retry_read_prefetch SIGNAL
-- eliminates a critical path inside the PIPEDLY state for reading
-- data out of the Local Link buffer source (prefetch buffer).
retry_read_prefetch_cs <= retry_read_prefetch_ns;
END IF;
END PROCESS cs;
END BLOCK sm;
bfs_dly1 : PROCESS (SOPB_clk) IS
BEGIN
-- The data from local link is registered here and qualified by the
-- combinatorial slave xfer ack condition so that zero is driven when
-- invalid data is present. bfs_data_cs drives the Sl_DBus directly so it
-- must be zero at all other times to avoid clobbering data on the
-- OPB_Dbus distributed to all other opb peripherals (including this one
-- during write operations!) Note that the qualifier expression is
-- redundant. sl_xferack_ns is already conditioned on opb_rnw but for
-- both the read and write case. This redundancy will be removed during
-- synthesis but is convienient here as the concept of sl_xferack as the
-- qualifier is more clear then the underlying expression is.
IF (rising_edge(SOPB_clk)) THEN
IF ( (sl_xferack_ns AND OPB_rnw)='1') THEN
bfs_data_cs <= bfs_data;
ELSE
bfs_data_cs <= (others => '0');
END IF;
END IF;
END PROCESS bfs_dly1;
bfd_dly1 : PROCESS (SOPB_clk) IS
BEGIN
IF (rising_edge(SOPB_clk)) THEN
bfd_data_cs <= OPB_DBus;
END IF;
END PROCESS bfd_dly1;
----------------------------------------------------------------------------
-- Final output assignments from internal combinatorial or registered,
-- control or data paths.
----------------------------------------------------------------------------
-- The slave acknowledgements must be registed by Xilinx convention.
-- Unfortunately, to cover the Master abort case the ack's must be
-- qualified by OPB_Select combinatorially. No way around this.
Sl_xferAck <= Sl_xferAck_cs AND OPB_Select;
Sl_errAck <= Sl_errAck_cs AND OPB_Select;
Sl_retry <= Sl_retry_cs AND OPB_Select;
-- Since the Xilinx implementation of the OPB BUS arbiter and bus structure
-- differs then the true IBM implementation (in order to save on resources)
-- the Sl_DBus must be qualified such that it is all '0' when this slave
-- is not actively outputing data. The primary qualifier is thus Sl_xferAck.
-- The qualification must include OPB_Select as well to account for the CASE
-- of a master abort. bfs_data_cs includes a synchronous reset in the case
-- that Sl_xferAck is deasserted or OPB_rnw=write.
Sl_DBus <= bfs_data_cs WHEN (OPB_Select)='1'
ELSE (OTHERS => '0');
Sl_ToutSup <= '0';
-- The clr signal doesn't need clock domain transition pulse conditioning
-- because remaining on for two MPLB_clk periods (in 1:2 clock period ratio
-- situation) is not a problem. No read transaction can be activated in that
-- time period.
opbs_prefetch_req <= opbs_prefetch_req_cs;
-- pass through - no cross domain conditioning required.
opbs_trans_addr <= transaction_addr_cs;
opbs_be <= transaction_be_cs;
opbs_prefetch_clr <= opbs_prefetch_clr_cs;
opbs_postedwr_clr <= opbs_postedwr_clr_cs;
opbs_type <= opbs_type_cs;
opbs_length <= std_logic_vector(opbs_length_cs);
opbs_postedwrt_req <= opbs_postedwrt_req_cs;
-- LocalLink buffer destination (the posted write buffer) connections
bfd_sof_n <= bfd_sof_n_cs;
-- This "or" gate ensures that, on occasion of na OPB master abort, the last
-- word of data put into the fifo has its end of frame flag set.
bfd_eof_n <= bfd_eof_n_cs AND OPB_select ;
bfd_data <= bfd_data_cs;
bfd_src_dsc_n <= '1'; -- never DISCONNECT
bfd_gen1 : IF (C_BUS_CLOCK_PERIOD_RATIO = 1) GENERATE
-- The registered version of src_rdy is used to track the registered
-- version of OPB_xferAck
bfd_src_rdy_n <= bfd_src_rdy_n_cs;
END GENERATE bfd_gen1;
bfd_gen2 : IF (C_BUS_CLOCK_PERIOD_RATIO = 2) GENERATE
-- This flip flop toggles for one MPLB_clk period whenver the SOPB_clk
-- domain signal is asserted. Note that both signals are active low so an
-- "OR" is used to be an active low input/output AND function.
reg : PROCESS (MPLB_clk) IS
VARIABLE reg_n : std_logic := '0';
BEGIN
IF (rising_edge(MPLB_clk)) THEN
reg_n := NOT reg_n OR bfd_src_rdy_n_cs;
END IF;
bfd_src_rdy_n <= reg_n;
END PROCESS reg;
END GENERATE bfd_gen2;
-- LocalLink buffer source (the read prefetch buffer) connections
bfs_dst_dsc_n <= '1'; -- never DISCONNECT
bfs_gen1 : IF (C_BUS_CLOCK_PERIOD_RATIO = 1) GENERATE
bfs_dst_rdy_n <= bfs_dst_rdy_n_ns;
END GENERATE bfs_gen1;
bfs_gen2 : IF (C_BUS_CLOCK_PERIOD_RATIO = 2) GENERATE
-- This flip flop toggles for one MPLB_clk period whenver the SOPB_clk
-- domain signal is asserted. Note that both signals are active low so an
-- "OR" is used to be an active low input/output AND function.
reg : PROCESS (MPLB_clk) IS
VARIABLE reg_n : std_logic := '0';
BEGIN
IF (rising_edge(MPLB_clk)) THEN
reg_n := NOT reg_n OR bfs_dst_rdy_n_ns;
END IF;
bfs_dst_rdy_n <= reg_n;
END PROCESS reg;
END GENERATE bfs_gen2;
END ARCHITECTURE syn;
|
architecture RTL of ENTITY1 is
subtype range_st is integer range 0 to 9;
subtype width_st is integer range 16 to 128;
subtype range_subt is integer range 0 to 9;
subtype width_subt is integer range 16 to 128;
subtype rangest is integer range 0 to 9;
subtype widthst is integer range 16 to 128;
begin
end architecture RTL;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library cmos_lib; use cmos_lib.bulk_cmos_nfet;
configuration full of notch_filter is
for opamp_based -- architecture of notch_filter
for all : simple_opamp
use entity work.opamp(struct);
for struct -- architecture of opamp
for m1, m2 : nfet
use entity bulk_cmos_nfet(detailed);
end for;
for others : nfet
use entity bulk_cmos_nfet(basic);
end for;
-- ...
end for; -- end of architecture struct
end for;
-- ... -- bindings for other component instances
end for; -- end of architecture opamp_based
end configuration full;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library cmos_lib; use cmos_lib.bulk_cmos_nfet;
configuration full of notch_filter is
for opamp_based -- architecture of notch_filter
for all : simple_opamp
use entity work.opamp(struct);
for struct -- architecture of opamp
for m1, m2 : nfet
use entity bulk_cmos_nfet(detailed);
end for;
for others : nfet
use entity bulk_cmos_nfet(basic);
end for;
-- ...
end for; -- end of architecture struct
end for;
-- ... -- bindings for other component instances
end for; -- end of architecture opamp_based
end configuration full;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library cmos_lib; use cmos_lib.bulk_cmos_nfet;
configuration full of notch_filter is
for opamp_based -- architecture of notch_filter
for all : simple_opamp
use entity work.opamp(struct);
for struct -- architecture of opamp
for m1, m2 : nfet
use entity bulk_cmos_nfet(detailed);
end for;
for others : nfet
use entity bulk_cmos_nfet(basic);
end for;
-- ...
end for; -- end of architecture struct
end for;
-- ... -- bindings for other component instances
end for; -- end of architecture opamp_based
end configuration full;
|
--------------------------------------------------------------------------------
-- Copyright 2014 Madhu Siddalingaiah
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Entity: ProgramMemoryTest
-- Date: 2014-10-09
-- Author: Madhu
--
-- Description:
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Avoid using ieee.std_logic_arith.all
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ProgramMemoryTest is
generic (
DATA_WIDTH : integer := 16;
ADDRESS_WIDTH : integer := 16;
DEPTH : natural := 1024
);
end ProgramMemoryTest;
architecture arch of ProgramMemoryTest is
component ProgramMemory
generic (
DATA_WIDTH : integer;
ADDRESS_WIDTH : integer;
DEPTH : natural
);
port (
reset : in std_logic;
clock : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
pc_in : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
pc_out : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
memory_write : in std_logic;
pc_write : in std_logic
);
end component;
signal reset : std_logic := '0';
signal clock : std_logic := '0';
signal data_in : std_logic_vector (DATA_WIDTH - 1 downto 0 );
signal pc_in : std_logic_vector (ADDRESS_WIDTH - 1 downto 0 );
signal data_out : std_logic_vector (DATA_WIDTH - 1 downto 0 );
signal pc_out : std_logic_vector (ADDRESS_WIDTH - 1 downto 0 );
signal memory_write : std_logic;
signal pc_write : std_logic;
signal runSimulation : std_logic := '1';
begin
dut : ProgramMemory
generic map(
DATA_WIDTH => DATA_WIDTH,
ADDRESS_WIDTH => ADDRESS_WIDTH,
DEPTH => DEPTH
)
port map(
reset => reset,
clock => clock,
data_in => data_in,
pc_in => pc_in,
data_out => data_out,
pc_out => pc_out,
memory_write => memory_write,
pc_write => pc_write
);
process begin
wait for 5 ns;
clock <= not clock;
if runSimulation = '0' then
wait;
end if;
end process;
stimulus : process
procedure doReset is begin
pc_in <= (others => '0');
data_in <= (others => '0');
pc_write <= '0';
memory_write <= '0';
wait for 2 ns;
reset <= '1';
wait for 6 ns;
reset <= '0';
end doReset;
procedure write_inst(dIn : std_logic_vector(DATA_WIDTH-1 downto 0)) is
begin
data_in <= dIn;
memory_write <= '1';
wait until rising_edge(clock);
memory_write <= '0';
end write_inst;
begin
doReset;
wait until rising_edge(clock);
write_inst(x"000a");
write_inst(x"000b");
write_inst(x"000c");
write_inst(x"000d");
pc_in <= (others => '0');
pc_write <= '1';
wait until rising_edge(clock);
pc_write <= '0';
wait until rising_edge(clock);
wait until rising_edge(clock);
wait until rising_edge(clock);
wait until rising_edge(clock);
wait until rising_edge(clock);
runSimulation <= '0';
wait;
end process stimulus;
end arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: util
-- File: util.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Misc utilities
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity report_version is
generic (msg1, msg2, msg3, msg4 : string := ""; mdel : integer := 4);
end;
architecture beh of report_version is
begin
x : process
begin
wait for mdel * 1 ns;
if (msg1 /= "") then print(msg1); end if;
if (msg2 /= "") then print(msg2); end if;
if (msg3 /= "") then print(msg3); end if;
if (msg4 /= "") then print(msg4); end if;
wait;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity report_design is
generic (msg1, fabtech, memtech : string := ""; mdel : integer := 4);
end;
architecture beh of report_design is
begin
x : report_version
generic map (
msg1 => msg1,
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & fabtech & ", memory library: " & memtech,
mdel => mdel);
end;
-- pragma translate_on
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
-- file: clock_divider_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______144.719____114.212
-- CLK_OUT2_____7.143______0.000______50.0______244.806____114.212
-- CLK_OUT3____25.000______0.000______50.0______191.696____114.212
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock_divider_clk_wiz is
port
(-- Clock in ports
CLOCK_PLL : in std_logic;
-- Clock out ports
CLOCK_100 : out std_logic;
CLOCK_7_143 : out std_logic;
CLOCK_25 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end clock_divider_clk_wiz;
architecture xilinx of clock_divider_clk_wiz is
-- Input clock buffering / unused connectors
signal CLOCK_PLL_clock_divider : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_clock_divider : std_logic;
signal clkfbout_buf_clock_divider : std_logic;
signal clkfboutb_unused : std_logic;
signal CLOCK_100_clock_divider : std_logic;
signal clkout0b_unused : std_logic;
signal CLOCK_7_143_clock_divider : std_logic;
signal clkout1b_unused : std_logic;
signal CLOCK_25_clock_divider : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
signal reset_high : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_ibufg : IBUF
port map
(O => CLOCK_PLL_clock_divider,
I => CLOCK_PLL);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
plle2_adv_inst : PLLE2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 112,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 32,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 10.0)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_clock_divider,
CLKOUT0 => CLOCK_100_clock_divider,
CLKOUT1 => CLOCK_7_143_clock_divider,
CLKOUT2 => CLOCK_25_clock_divider,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_clock_divider,
CLKIN1 => CLOCK_PLL_clock_divider,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Other control and status signals
LOCKED => locked_int,
PWRDWN => '0',
RST => reset_high);
reset_high <= reset;
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_clock_divider,
I => clkfbout_clock_divider);
clkout1_buf : BUFG
port map
(O => CLOCK_100,
I => CLOCK_100_clock_divider);
clkout2_buf : BUFG
port map
(O => CLOCK_7_143,
I => CLOCK_7_143_clock_divider);
clkout3_buf : BUFG
port map
(O => CLOCK_25,
I => CLOCK_25_clock_divider);
end xilinx;
|
-- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: rs232out.vhd 322 2015-05-29 06:43:59Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/rs232out.vhd $
-- $Author : Ivan Auge (Email: auge@ensiie.fr)
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
-------------------------------------------------------------------------------
-- ATTENTION:
-- Ceci un template, les trous marqués "..." doivent être comblés pour
-- pouvoir être compilé, puis fonctionné.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Ce module sérialise l'entrée DATA de 8 bits sur la sortie TX.
--
-- le format écrit est:
-- - 1 start bit
-- - 8 bit de données
-- - 1 stop bits
--
-- La sortie BUSY indique que le module est en train de sérialiser.
--
-- Pour sérialiser une nouvelle valeur, il faut:
-- * attendre que BUSY soit nul.
-- * la positionner sur DATA et mettre NDATA à 1 au moins 1 cycle.
--
-- Pour fixer le BAUD du composant utilisez les paramètres génériques
-- BAUD et FREQ ci dessous.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity rs232out is
generic(
FREQ : integer := 50000000; -- Frequence de clk
BAUD : integer := 9600); -- Baud de Rx
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Tx : out STD_LOGIC;
Data : in STD_LOGIC_VECTOR(7 downto 0);
Ndata : in STD_LOGIC;
Busy : out STD_LOGIC);
end rs232out;
architecture montage of rs232out is
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
type T_CMD_i is (NOOP, COUNT, INIT);
signal CMD_i : T_CMD_i ;
signal R_i : integer RANGE 0 TO 15;
signal VT_endLoop: STD_LOGIC;
type T_CMD_baud is (NOOP, COUNT, INIT);
signal CMD_baud : T_CMD_baud ;
signal R_baud: integer RANGE 0 TO (FREQ)/BAUD;
signal VT_endbaud: STD_LOGIC;
type T_CMD_data is (NOOP, SHIFT, INIT);
signal CMD_data : T_CMD_data ;
signal R_data : STD_LOGIC_VECTOR(8 downto 0); -- 0 : 1 start bit
-- 8:1 : 8 data bits
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
--Description des états
type STATE_TYPE is (ST_BEGIN, ST_FOR, ST_ATT, ST_ADV);
signal state : STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
process (clk)
begin if clk'event and clk = '1' then
-- R_i
if ( CMD_i = INIT ) then
R_i <= 11 ;
elsif ( CMD_i = COUNT ) then
R_i <= R_i - 1;
else
R_i <= R_i;
end if;
-- R_baud
if ( CMD_baud = INIT ) then
R_baud <= FREQ/BAUD ;
elsif ( CMD_baud = COUNT ) then
R_baud <= R_baud - 1;
else
R_baud <= R_baud;
end if;
-- R_data
if ( CMD_data = INIT ) then
-- V = E + '0'
R_data(8 downto 1) <= Data;
R_data(0) <= '0';
elsif ( CMD_data = SHIFT ) then
-- v = '1' + (v >> 1)
R_data(7 downto 0) <= R_data(8 downto 1);
R_data(8) <= '1';
else
R_data <= R_data;
end if ;
end if; end process;
VT_endbaud <= '1' WHEN R_Baud = 0 ELSE '0' ;
VT_endLoop <= '1' WHEN R_i = 0 ELSE '0' ;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: Ndata VT_endLoop VT_endBaud
-- Outputs: Tx Busy CMD_i CMD_baud CMD_data
-------------------------------------------------------------------------------
-- fonction de transitition
process (reset,clk)
begin
if reset = '1' then
state <= ST_BEGIN;
elsif clk'event and clk = '1' then
case state is
when ST_BEGIN =>
-- si go, alors on commence à serialiser
if Ndata = '0' then
state <= ST_FOR;
end if;
when ST_FOR =>
if VT_endLoop = '1' then
state <= ST_BEGIN;
else
state <= ST_ATT;
end if;
when ST_ATT =>
if VT_endbaud = '1' then
state <= ST_ADV;
end if;
when ST_ADV =>
state <= ST_FOR;
end case;
end if;
end process;
-- fonction de sortie
with state select tx <=
'1' when ST_BEGIN,
R_Data(0) when others
;
with state select busy <=
'0' when ST_BEGIN,
'1' when others
;
with state select CMD_i <=
INIT when ST_BEGIN,
COUNT when ST_ADV,
NOOP when others
;
with state select CMD_baud <=
COUNT when ST_ATT,
INIT when others
;
with state select CMD_data <=
INIT when ST_BEGIN,
SHIFT when ST_ADV,
NOOP when others
;
end montage;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3076.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03076pkg is
type integer_cons_vector is array (15 downto 0) of integer;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector;
constant C19 : integer_cons_vectorofvector := (others => (others => 3));
end c12s06b02x00p06n01i03076pkg;
use work.c12s06b02x00p06n01i03076pkg.all;
ENTITY c12s06b02x00p06n01i03076ent_a IS
PORT
(
F1: OUT integer ;
F3: IN integer_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03076ent_a;
ARCHITECTURE c12s06b02x00p06n01i03076arch_a OF c12s06b02x00p06n01i03076ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03076arch_a;
use work.c12s06b02x00p06n01i03076pkg.all;
ENTITY c12s06b02x00p06n01i03076ent IS
END c12s06b02x00p06n01i03076ent;
ARCHITECTURE c12s06b02x00p06n01i03076arch OF c12s06b02x00p06n01i03076ent IS
function scalar_complex(s : integer) return integer_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN integer_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03076ent_a(c12s06b02x00p06n01i03076arch_a);
signal S1 : integer_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03076"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03076 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03076arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3076.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03076pkg is
type integer_cons_vector is array (15 downto 0) of integer;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector;
constant C19 : integer_cons_vectorofvector := (others => (others => 3));
end c12s06b02x00p06n01i03076pkg;
use work.c12s06b02x00p06n01i03076pkg.all;
ENTITY c12s06b02x00p06n01i03076ent_a IS
PORT
(
F1: OUT integer ;
F3: IN integer_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03076ent_a;
ARCHITECTURE c12s06b02x00p06n01i03076arch_a OF c12s06b02x00p06n01i03076ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03076arch_a;
use work.c12s06b02x00p06n01i03076pkg.all;
ENTITY c12s06b02x00p06n01i03076ent IS
END c12s06b02x00p06n01i03076ent;
ARCHITECTURE c12s06b02x00p06n01i03076arch OF c12s06b02x00p06n01i03076ent IS
function scalar_complex(s : integer) return integer_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN integer_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03076ent_a(c12s06b02x00p06n01i03076arch_a);
signal S1 : integer_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03076"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03076 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03076arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3076.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03076pkg is
type integer_cons_vector is array (15 downto 0) of integer;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector;
constant C19 : integer_cons_vectorofvector := (others => (others => 3));
end c12s06b02x00p06n01i03076pkg;
use work.c12s06b02x00p06n01i03076pkg.all;
ENTITY c12s06b02x00p06n01i03076ent_a IS
PORT
(
F1: OUT integer ;
F3: IN integer_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03076ent_a;
ARCHITECTURE c12s06b02x00p06n01i03076arch_a OF c12s06b02x00p06n01i03076ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03076arch_a;
use work.c12s06b02x00p06n01i03076pkg.all;
ENTITY c12s06b02x00p06n01i03076ent IS
END c12s06b02x00p06n01i03076ent;
ARCHITECTURE c12s06b02x00p06n01i03076arch OF c12s06b02x00p06n01i03076ent IS
function scalar_complex(s : integer) return integer_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN integer_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03076ent_a(c12s06b02x00p06n01i03076arch_a);
signal S1 : integer_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03076"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03076 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03076arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2973.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p03n01i02973ent IS
END c02s03b01x00p03n01i02973ent;
ARCHITECTURE c02s03b01x00p03n01i02973arch OF c02s03b01x00p03n01i02973ent IS
type newt is (one,two,three,four);
function "+" (constant c1,c2 : in integer) return newt is
begin
assert (c1=10)
report "Error in association of left binary + operator"
severity failure;
assert (c2=20)
report "Error in association of right binary + operator"
severity failure;
assert NOT( c1=10 and c2=20 )
report "***PASSED TEST: c02s03b01x00p03n01i02973"
severity NOTE;
assert ( c1=10 and c2=20 )
report "***FAILED TEST: c02s03b01x00p03n01i02973 - Error in + overloading as binary operator."
severity ERROR;
return three;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
n1 := two;
assert (n1=two)
report "Error in initial conditions detected"
severity failure;
n1:= 10 + 20;
assert (n1=three)
report "Error in call to overloaded binary + operator"
severity failure;
wait;
END PROCESS TESTING;
END c02s03b01x00p03n01i02973arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2973.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p03n01i02973ent IS
END c02s03b01x00p03n01i02973ent;
ARCHITECTURE c02s03b01x00p03n01i02973arch OF c02s03b01x00p03n01i02973ent IS
type newt is (one,two,three,four);
function "+" (constant c1,c2 : in integer) return newt is
begin
assert (c1=10)
report "Error in association of left binary + operator"
severity failure;
assert (c2=20)
report "Error in association of right binary + operator"
severity failure;
assert NOT( c1=10 and c2=20 )
report "***PASSED TEST: c02s03b01x00p03n01i02973"
severity NOTE;
assert ( c1=10 and c2=20 )
report "***FAILED TEST: c02s03b01x00p03n01i02973 - Error in + overloading as binary operator."
severity ERROR;
return three;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
n1 := two;
assert (n1=two)
report "Error in initial conditions detected"
severity failure;
n1:= 10 + 20;
assert (n1=three)
report "Error in call to overloaded binary + operator"
severity failure;
wait;
END PROCESS TESTING;
END c02s03b01x00p03n01i02973arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2973.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p03n01i02973ent IS
END c02s03b01x00p03n01i02973ent;
ARCHITECTURE c02s03b01x00p03n01i02973arch OF c02s03b01x00p03n01i02973ent IS
type newt is (one,two,three,four);
function "+" (constant c1,c2 : in integer) return newt is
begin
assert (c1=10)
report "Error in association of left binary + operator"
severity failure;
assert (c2=20)
report "Error in association of right binary + operator"
severity failure;
assert NOT( c1=10 and c2=20 )
report "***PASSED TEST: c02s03b01x00p03n01i02973"
severity NOTE;
assert ( c1=10 and c2=20 )
report "***FAILED TEST: c02s03b01x00p03n01i02973 - Error in + overloading as binary operator."
severity ERROR;
return three;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
n1 := two;
assert (n1=two)
report "Error in initial conditions detected"
severity failure;
n1:= 10 + 20;
assert (n1=three)
report "Error in call to overloaded binary + operator"
severity failure;
wait;
END PROCESS TESTING;
END c02s03b01x00p03n01i02973arch;
|
library work;
use work.isp_hal.all;
use work.isp_drv.all;
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity drv_tb is
end drv_tb;
architecture TB_ARCHITECTURE of drv_tb is
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal clk : STD_LOGIC;
signal reset : STD_LOGIC;
signal otg_data : STD_LOGIC_VECTOR(15 downto 0);
signal otg_i : isp_hal_in_t;
signal otg_o : isp_hal_out_t;
signal drv_i : isp_drv_in_t;
signal drv_o : isp_drv_out_t;
--local signals
signal slowclk_en : bit;
signal isp_emu_data : std_logic_vector(15 downto 0);
--------------------------------------------------------------
-- clock cycle
constant period : time := 20 ns;
--------------------------------------------------------------
begin
--I/O
otg_i.drv <= drv_o.hal;
h: hal generic map(3) port map (clk, reset, otg_data , otg_i, otg_o);
--driver
drv_i.hal <= otg_o.drv;
d: drv port map(clk,reset, drv_i , drv_o);
----------------------------------------------------
-- clock
process
begin
clk <= '0';
wait for period/2;
clk <= '1';
wait for period/2;
end process;
--produces 25MHz clock enable for OTG
p_slowclk_en: process
begin
wait until rising_edge(clk);
slowclk_en <= not(slowclk_en);
end process;
otg_i.slowclk_en <= slowclk_en;
----------------------------------------------------
-- resets
process
begin
reset <= '1';
wait for period;
reset <= '0';
wait;
end process;
----------------------------------------------------
-- ISP read emulation
----------------------------------------------------
process
begin
otg_data <= (others => 'Z');
wait until falling_edge(otg_o.rd_n);
wait for 22 ns;
otg_data <= isp_emu_data;
wait until rising_edge(otg_o.cs_n);
wait for 3 ns;
end process;
----------------------------------------------------
-- ISP write emulation
----------------------------------------------------
process
begin
wait until falling_edge(otg_o.wr_n);
wait until rising_edge(otg_o.wr_n);
wait for 3 ns;
isp_emu_data <= otg_data;
end process;
end TB_ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXIinterfacefor65816_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
clk : in std_logic;
tru_clk: in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end AXIinterfacefor65816_v1_0_S00_AXI;
architecture arch_imp of AXIinterfacefor65816_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 4;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 32
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
--
--
-- CUSTOM INTERFACE PORTS AND SIGNALS
--
--
COMPONENT Soft_65C816
PORT(
clk : IN std_logic;
tru_clk : IN std_logic;
reset : IN std_logic;
Addr_Bus : OUT std_logic_vector(23 downto 0);
D_BUS : IN std_logic_vector(31 downto 0);
EMULATION_SELECT : OUT std_logic;
RDY : out std_logic;
DATA_RDY: in std_logic;
REG_A : OUT std_logic_vector(15 downto 0);
REG_X : OUT std_logic_vector(15 downto 0);
REG_Y : OUT std_logic_vector(15 downto 0);
REG_SP : OUT std_logic_vector(15 downto 0);
REG_PC : OUT std_logic_vector(15 downto 0);
REG_Proc : OUT std_logic_vector(7 downto 0);
REG_DBR : OUT std_logic_vector(7 downto 0);
VPB : OUT std_logic
);
END COMPONENT;
--Component Inputs
signal reset : std_logic := '0'; -- Goes to slave register #9
signal D_BUS : std_logic_vector(31 downto 0) := (others => 'Z'); -- Goes to slave register #10
signal DATA_RDY: std_logic := '1'; -- Goes to slave register #11
--Component Outputs
signal Addr_Bus : std_logic_vector(23 downto 0) := (others => '0');
signal EMULATION_SELECT : std_logic;
signal REG_A : std_logic_vector(15 downto 0);
signal REG_X : std_logic_vector(15 downto 0);
signal REG_Y : std_logic_vector(15 downto 0);
signal REG_SP : std_logic_vector(15 downto 0);
signal REG_PC : std_logic_vector(15 downto 0);
signal REG_Proc : std_logic_vector(7 downto 0);
signal REG_DBR : std_logic_vector(7 downto 0);
signal VPB : std_logic;
signal RDY : std_logic;
--Entity Inputs Signals
--Entity Output Signals
signal Output_Addr_Bus : std_logic_vector(23 downto 0) := (others => '0'); -- Goes to slave register #0
signal Output_EMULATION_SELECT : std_logic; -- Goes to slave register #1
signal Output_REG_A : std_logic_vector(15 downto 0); -- Goes to slave register #2
signal Output_REG_X : std_logic_vector(15 downto 0); -- Goes to slave register #3
signal Output_REG_Y : std_logic_vector(15 downto 0); -- Goes to slave register #4
signal Output_REG_SP : std_logic_vector(15 downto 0); -- Goes to slave register #5
signal Output_REG_PC : std_logic_vector(15 downto 0); -- Goes to slave register #6
signal Output_REG_Proc : std_logic_vector(7 downto 0); -- Goes to slave register #7
signal Output_REG_DBR : std_logic_vector(7 downto 0); -- Goes to slave register #8
--Internal Signals
begin
-- BEGIN User designated port maps
-- Instantiate the Soft 65816 Unit to be implemented
HEART: Soft_65C816 PORT MAP (
clk => clk,
tru_clk => tru_clk,
reset => reset,
Addr_Bus => Addr_Bus,
D_BUS => D_BUS,
EMULATION_SELECT => EMULATION_SELECT,
RDY => RDY,
DATA_RDY => DATA_RDY,
REG_A => REG_A,
REG_X => REG_X,
REG_Y => REG_Y,
REG_SP => REG_SP,
REG_PC => REG_PC,
REG_Proc => REG_Proc,
REG_DBR => REG_DBR,
VPB => VPB
);
reset <= slv_reg9(0);
D_BUS <= slv_reg10;
DATA_RDY <= slv_reg11(0);
-- END User designated port maps
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 20
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 21
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 22
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 23
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 24
slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 25
slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 26
slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 27
slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 28
slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 29
slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 30
slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 31
slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
slv_reg24 <= slv_reg24;
slv_reg25 <= slv_reg25;
slv_reg26 <= slv_reg26;
slv_reg27 <= slv_reg27;
slv_reg28 <= slv_reg28;
slv_reg29 <= slv_reg29;
slv_reg30 <= slv_reg30;
slv_reg31 <= slv_reg31;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00000" =>
reg_data_out <= std_logic_vector(resize(unsigned(Output_Addr_Bus), C_S_AXI_DATA_WIDTH));
when b"00001" =>
reg_data_out <= X"0000000" & b"000" & Output_EMULATION_SELECT;
when b"00010" =>
reg_data_out <= std_logic_vector(resize(unsigned(Output_REG_A), C_S_AXI_DATA_WIDTH));
when b"00011" =>
reg_data_out <= std_logic_vector(resize(unsigned(Output_REG_X), C_S_AXI_DATA_WIDTH));
when b"00100" =>
reg_data_out <= std_logic_vector(resize(unsigned(Output_REG_Y), C_S_AXI_DATA_WIDTH));
when b"00101" =>
reg_data_out <= std_logic_vector(resize(unsigned(Output_REG_SP), C_S_AXI_DATA_WIDTH));
when b"00110" =>
reg_data_out <= std_logic_vector(resize(unsigned(Output_REG_PC), C_S_AXI_DATA_WIDTH));
when b"00111" =>
reg_data_out <= std_logic_vector(resize(unsigned(Output_REG_Proc), C_S_AXI_DATA_WIDTH));
when b"01000" =>
reg_data_out <= slv_reg8;
when b"01001" =>
reg_data_out <= slv_reg9;
when b"01010" =>
reg_data_out <= slv_reg10;
when b"01011" =>
reg_data_out <= slv_reg11;
when b"01100" =>
reg_data_out <= slv_reg12;
when b"01101" =>
reg_data_out <= slv_reg13;
when b"01110" =>
reg_data_out <= slv_reg14;
when b"01111" =>
reg_data_out <= slv_reg15;
when b"10000" =>
reg_data_out <= slv_reg16;
when b"10001" =>
reg_data_out <= slv_reg17;
when b"10010" =>
reg_data_out <= slv_reg18;
when b"10011" =>
reg_data_out <= slv_reg19;
when b"10100" =>
reg_data_out <= slv_reg20;
when b"10101" =>
reg_data_out <= slv_reg21;
when b"10110" =>
reg_data_out <= slv_reg22;
when b"10111" =>
reg_data_out <= slv_reg23;
when b"11000" =>
reg_data_out <= slv_reg24;
when b"11001" =>
reg_data_out <= slv_reg25;
when b"11010" =>
reg_data_out <= slv_reg26;
when b"11011" =>
reg_data_out <= slv_reg27;
when b"11100" =>
reg_data_out <= slv_reg28;
when b"11101" =>
reg_data_out <= slv_reg29;
when b"11110" =>
reg_data_out <= slv_reg30;
when b"11111" =>
reg_data_out <= X"DEADBEEF";
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
--PROC_for_65816_syncronization:
-- process (clk) is
-- begin
-- if rising_edge(clk) then
-- end if;
-- end process;
-- User logic ends
end arch_imp;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= hex_to_std_logic_vector("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (8191 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
0,
"no_coe_file_loaded",
DEFAULT_DATA,
32,
8192);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>8192 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(12 DOWNTO 0) <= READ_ADDR(12 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 8192 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2798.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity FILE is
end FILE;
ENTITY c13s09b00x00p99n01i02798ent IS
END c13s09b00x00p99n01i02798ent;
ARCHITECTURE c13s09b00x00p99n01i02798arch OF c13s09b00x00p99n01i02798ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02798 - Reserved word FILE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02798arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2798.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity FILE is
end FILE;
ENTITY c13s09b00x00p99n01i02798ent IS
END c13s09b00x00p99n01i02798ent;
ARCHITECTURE c13s09b00x00p99n01i02798arch OF c13s09b00x00p99n01i02798ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02798 - Reserved word FILE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02798arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2798.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity FILE is
end FILE;
ENTITY c13s09b00x00p99n01i02798ent IS
END c13s09b00x00p99n01i02798ent;
ARCHITECTURE c13s09b00x00p99n01i02798arch OF c13s09b00x00p99n01i02798ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02798 - Reserved word FILE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02798arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Params is
generic (
BOO : boolean:=FALSE;
INT : integer:=0;
LOG : std_logic:='0';
VEC : std_logic_vector(7 downto 0):="00000000";
STR : string:="ABCD";
REA : real:=0.0
);
port (
boo_o : out std_logic;
int_o : out std_logic_vector(7 downto 0);
log_o : out std_logic;
vec_o : out std_logic_vector(7 downto 0);
str_o : out std_logic;
rea_o : out std_logic
);
end entity Params;
architecture RTL of Params is
begin
assert BOO=True report "The boolean is not True" severity note;
assert INT=255 report "The integer is not 255" severity note;
assert LOG='1' report "The std_logic is not '1'" severity note;
assert VEC="11111111" report "The std_logic_vector is not 11111111" severity note;
assert STR="WXYZ" report "The string is not WXYZ" severity note;
-- assert REA=1.1 report "The real is not 1.1" severity note;
boo_o <= '1' when BOO else '0';
int_o <= std_logic_vector(to_unsigned(INT, 8));
log_o <= LOG;
vec_o <= VEC;
str_o <= '1' when STR="WXYZ" else '0';
rea_o <= '1' when REA=1.1 else '0';
end architecture RTL;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_mtf
-- File: pci_mtf.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use gaisler.pcilib.all;
use gaisler.misc.all;
entity pci_mtf is
generic (
memtech : integer := DEFMEMTECH;
hmstndx : integer := 0;
dmamst : integer := NAHBMST;
readpref : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
irq : integer := 0;
irqmask : integer := 0;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0; -- 0 little, 1 big
class_code: integer := 16#0B4000#;
rev : integer := 0;
scanen : integer := 0;
syncrst : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of pci_mtf is
function byte_twist(di : in std_logic_vector(31 downto 0); enable : in std_logic) return std_logic_vector is
variable do : std_logic_vector(31 downto 0);
begin
if enable = '1' then
for i in 0 to 3 loop
do(31-i*8 downto 24-i*8) := di(31-(3-i)*8 downto 24-(3-i)*8);
end loop;
else
do := di;
end if;
return do;
end function;
function nr_of_1(di : in integer) return integer is
variable vec : unsigned(31 downto 0);
variable ones : integer;
begin
ones := 0;
vec := to_unsigned(di,32);
for i in 0 to 31 loop
if vec(i) = '1' then
ones := ones + 1;
end if;
end loop;
return ones;
end function;
constant REVISION : amba_version_type := rev;
constant CSYNC : integer := nsync-1;
constant HADDR_WIDTH : integer := 28;
constant MADDR_WIDTH : integer := abits;
constant DMAMADDR_WIDTH : integer := dmaabits;
constant FIFO_DEPTH : integer := fifodepth;
constant FIFO_FULL : std_logic_vector(FIFO_DEPTH - 2 downto 0) := (others => '1');
constant FIFO_DATA_BITS : integer := 32; -- One valid bit
constant NO_CPU_REGS : integer := 6;
constant NO_PCI_REGS : integer := 6;
constant HMASK_WIDTH : integer := nr_of_1(hmask);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCIFBRG, 0, REVISION, irq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCIFBRG, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, 16#E00#),
others => zero32);
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
gnt : std_logic;
host : std_logic;
end record;
type pci_fifo_in_type is record
ren : std_logic;
raddr : std_logic_vector(FIFO_DEPTH - 1 downto 0);
wen : std_logic;
waddr : std_logic_vector(FIFO_DEPTH - 1 downto 0);
wdata : std_logic_vector(FIFO_DATA_BITS - 1 downto 0);
end record;
type pci_fifo_out_type is record
rdata : std_logic_vector(FIFO_DATA_BITS - 1 downto 0);
end record;
type fifo_type is record
side : std_logic; -- Owner access side. Receiver accesses the other side
raddr : std_logic_vector(FIFO_DEPTH - 2 downto 0);
waddr : std_logic_vector(FIFO_DEPTH - 2 downto 0);
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_master_state_type is (idle, addr, m_data, turn_ar, s_tar, dr_bus);
type pci_master_fifo_state_type is (idle, addr, incr, last1, sync, t_retry, ttermwd, ttermnd, abort, done, wdone);
type pci_target_type is record
state : pci_target_state_type;
cnt : std_logic_vector(2 downto 0);
csel : std_logic; -- Configuration chip select
msel : std_logic; -- Memory hit
barsel : std_logic; -- Memory hit
psel : std_logic; -- Page hit
addr : std_logic_vector(31 downto 0);
laddr : std_logic_vector(31 downto 0);
lsize : std_logic_vector(1 downto 0);
lcbe : std_logic_vector(3 downto 0);
lwrite : std_logic;
lburst : std_logic;
lmult : std_logic;
mult : std_logic;
read : std_logic; -- PCI target read
burst : std_logic;
pending : std_logic;
wdel : std_logic;
last : std_logic;
fifo : fifo_type;
trdy_del : std_logic; -- (delay trdy to send last word in fifo) bug fix ***
end record;
type pci_master_type is record
state : pci_master_state_type;
fstate : pci_master_fifo_state_type;
cnt : std_logic_vector(2 downto 0);
ltim : std_logic_vector(7 downto 0); -- Latency timer
request : std_logic;
hwrite : std_logic;
stop_req : std_logic;
last : std_logic;
valid : std_logic;
split : std_logic;
first : std_logic;
firstw : std_logic;
fifo : fifo_type;
rmdone : std_logic; -- bug fix ***
stopframe: std_logic;
lto : std_logic; -- bug fix latency timer timeout
end record;
type pci_sync_regs is array (0 to NO_PCI_REGS - 1) of std_logic_vector(csync downto 0);
type pci_reg_type is record
pci : pci_sigs_type;
noe_par : std_logic;
noe_ad : std_logic;
noe_ctrl : std_logic;
noe_cbe : std_logic;
noe_frame : std_logic;
noe_irdy : std_logic;
noe_req : std_logic;
noe_perr : std_logic;
m : pci_master_type;
t : pci_target_type;
comm : pci_config_command_type; -- Command register
stat : pci_config_status_type; -- Status register
bar0 : std_logic_vector(31 downto MADDR_WIDTH); -- Base Address register 0
bar1 : std_logic_vector(31 downto DMAMADDR_WIDTH); -- Base Address register 1
bar0_conf : std_logic;
bar1_conf : std_logic;
page : std_logic_vector(31 downto MADDR_WIDTH-1); -- AHB page
bt_enable : std_logic; -- Byte twist enable, page0 bit 0
ltim : std_logic_vector(7 downto 0); -- Latency timer
cline : std_logic_vector(7 downto 0); -- Cache Line Size
intline : std_logic_vector(7 downto 0); -- Interrupt Line
syncs : pci_sync_regs;
trans : std_logic_vector(NO_CPU_REGS - 1 downto 0);
end record;
type cpu_master_state_type is (idle, cbe_prepare, write, read_w, read, stop);
type cpu_slave_state_type is (idle, w_wait, t_data, r_hold, r_wait, w_done, t_done);
type cpu_master_type is record
state : cpu_master_state_type; -- AMBA master state machine
dmaddr : std_logic_vector(31 downto 0);
fifo : fifo_type;
cbe_fifo : fifo_type;
cur_cbe : std_logic_vector(3 downto 0);
cbe_prep_cnt : std_ulogic;
read_half : std_logic;
last_side_wr : std_ulogic;
end record;
type cpu_slave_type is record
state : cpu_slave_state_type; -- AMBA slave state machine
maddr : std_logic_vector(31 downto 0);
mdata : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0);
perror : std_logic;
hresp : std_logic_vector(1 downto 0);
hready : std_logic;
htrans : std_logic_vector(1 downto 0);
hmaster : std_logic_vector(3 downto 0);
pcicomm : std_logic_vector(3 downto 0);
hold : std_logic;
fifos_write : std_logic;
fifo : fifo_type;
last_side : std_logic;
end record;
type cpu_sync_regs is array (0 to NO_CPU_REGS - 1) of std_logic_vector(csync downto 0);
type cpu_reg_type is record
m : cpu_master_type;
s : cpu_slave_type;
syncs : cpu_sync_regs;
trans : std_logic_vector(NO_PCI_REGS - 1 downto 0);
pciba : std_logic_vector(HMASK_WIDTH-1 downto 0);
cfto : std_logic;
wcomm : std_logic;
rcomm : std_logic;
werr : std_logic;
clscnt : std_logic_vector(8 downto 0);
dmapage : std_logic_vector(31 downto DMAMADDR_WIDTH); -- DMA page
ioba : std_logic_vector(15 downto 0);
pciirq : std_logic_vector(1 downto 0);
bus_nr : std_logic_vector(3 downto 0);
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal fifo1i, fifo2i, fifo3i, fifo4i, cbe_fifoi : pci_fifo_in_type;
signal fifo1o, fifo2o, fifo3o, fifo4o, cbe_fifoo : pci_fifo_out_type;
signal roe_ad, rioe_ad : std_logic_vector(31 downto 0);
signal pcirst : std_logic;
signal prrst : std_logic;
attribute sync_set_reset : string;
attribute sync_set_reset of prrst : signal is "true";
attribute async_set_reset : string;
attribute async_set_reset of pcirst : signal is "true";
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
begin
-----------------------------------------------
-- Back-end state machine (AHB clock domain) --
-----------------------------------------------
comb : process (rst, r2, r, dmao, ahbsi, fifo2o, fifo4o, apbi)
variable vdmai : ahb_dma_in_type;
variable v : cpu_reg_type;
variable hready : std_logic;
variable hresp, hsize : std_logic_vector(1 downto 0);
variable p_done, wsdone, wmdone, rtdone, rmdone : std_logic;
variable pstart, habort, hstart_ack : std_logic;
variable hstart, pabort, pstart_ack, pcidc : std_logic;
variable i : integer range 0 to NO_CPU_REGS;
variable fifom_write, fifos_write : std_logic;
variable prdata : std_logic_vector(31 downto 0);
variable wmvalid, wsvalid, rmvalid, rsvalid, burst_read, hold : std_logic;
variable fifors_limit, fifows_limit,fiform_limit, fifowm_limit, fifows_stop : std_logic;
variable comp, request, s_read_side, m_read_side : std_logic;
variable ahb_access : std_logic; -- *** access control fix
variable start, single_access : std_logic;
variable next_cbe : std_logic_vector(3 downto 0);
variable byteaddr : std_logic_vector(1 downto 0);
begin
v := r2;
vdmai.start := '0';
vdmai.irq := '0'; vdmai.busy := '0'; vdmai.burst := '1';
vdmai.wdata := fifo2o.rdata(31 downto 0); vdmai.write := r.t.lwrite;
rmvalid := '1'; wmvalid := '1'; request := '0'; hold := '0';
rsvalid := '1'; wsvalid := '1'; burst_read := '0';
hready := '1'; hresp := HRESP_OKAY; hsize := "10";
fifom_write := '0'; v.s.fifos_write := '0';
comp := '0'; prdata := (others => '0'); v.s.hold := '0';
s_read_side := not r.m.fifo.side; m_read_side := not r.t.fifo.side;
ahb_access := '0'; -- *** access control fix
-- Synch registers
pstart := r2.trans(0);
habort := r2.trans(1);
hstart_ack := r2.trans(2);
-- fifows_limit := r2.trans(3);
wsdone := r2.trans(4);
wmdone := r2.trans(5);
for i in 0 to NO_CPU_REGS - 1 loop
v.syncs(i)(csync) := r.trans(i);
if csync /= 0 then v.syncs(i)(0) := r2.syncs(i)(csync); end if;
end loop;
hstart := r2.syncs(0)(0);
pabort := r2.syncs(1)(0);
pstart_ack := r2.syncs(2)(0);
pcidc := r2.syncs(3)(0);
rtdone := r2.syncs(4)(0);
rmdone := r2.syncs(5)(0);
p_done := pstart_ack or pabort;
if r2.m.fifo.raddr = FIFO_FULL then fiform_limit := '1'; else fiform_limit := '0'; end if;
if r2.m.fifo.waddr = FIFO_FULL then fifowm_limit := '1'; else fifowm_limit := '0'; end if;
if r2.s.fifo.raddr = FIFO_FULL then fifors_limit := '1'; else fifors_limit := '0'; end if;
if r2.s.fifo.waddr = FIFO_FULL then fifows_limit := '1'; else fifows_limit := '0'; end if;
if r2.s.fifo.waddr(FIFO_DEPTH - 2 downto 1) = FIFO_FULL(FIFO_DEPTH - 2 downto 1) then fifows_stop := '1'; else fifows_stop := '0'; end if;
-----------------------------------
---- APB Control & Status regs ----
-----------------------------------
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
if apbi.pwrite = '1' then
v.pciba := apbi.pwdata(31 downto 31-HMASK_WIDTH+1);
v.bus_nr := apbi.pwdata(26 downto 23);
v.werr := r2.werr and not apbi.pwdata(14);
v.wcomm := apbi.pwdata(10) and r.comm.mwie;
v.rcomm := apbi.pwdata(9);
end if;
prdata(31 downto 31-HMASK_WIDTH+1) := r2.pciba;
prdata(26 downto 23) := r2.bus_nr;
prdata(22 downto 0) := r.ltim & r2.werr & not pr.host & r.comm.msen & r.comm.men & r2.wcomm & r2.rcomm & r2.cfto & r.cline;
when "001" =>
prdata := r.bar0(31 downto MADDR_WIDTH) & addzero(MADDR_WIDTH-1 downto 0);
when "010" =>
prdata := r.page(31 downto MADDR_WIDTH-1) & addzero(MADDR_WIDTH-2 downto 1) & r.bt_enable;
when "011" =>
prdata := r.bar1(31 downto DMAMADDR_WIDTH) & addzero(DMAMADDR_WIDTH-1 downto 0);
when "100" =>
if apbi.pwrite = '1' then
v.dmapage(31 downto DMAMADDR_WIDTH) := apbi.pwdata(31 downto DMAMADDR_WIDTH);
end if;
prdata := r2.dmapage(31 downto DMAMADDR_WIDTH) & addzero(DMAMADDR_WIDTH-1 downto 0);
when "101" =>
if apbi.pwrite = '1' then
v.ioba := apbi.pwdata(31 downto 16);
end if;
prdata := r2.ioba & addzero(15 downto 4) & hstart & hstart_ack & pstart & pstart_ack;
when "110" =>
prdata(1) := r.comm.men; prdata(2) := r.comm.msen;
prdata(4) := r.comm.mwie; prdata(6) := r.comm.per;
prdata(24) := r.stat.dped; prdata(26) := '1';
prdata(27) := r.stat.sta; prdata(28) := r.stat.rta;
prdata(29) := r.stat.rma; prdata(31) := r.stat.dpe;
when others =>
end case;
end if;
---------------------
---- AHB MASTER ----
---------------------
-- Burst control
if (r2.m.state = read or r2.m.state = read_w) then
if r.t.lmult = '1' then
comp := fifowm_limit and r2.m.fifo.side;
elsif r.t.lburst = '1' then
if r2.clscnt(8) = '1' then comp := '1';
else v.clscnt := r2.clscnt - (dmao.active and dmao.ready); end if;
else comp := '1'; end if;
else
v.clscnt := '0' & (r.cline - '1'); -- set burst counter to cache line size
end if;
if (rtdone = '1' and (r2.m.fifo.raddr + '1') = r.t.fifo.waddr) then rmvalid := '0'; end if;
-- step DMA address
if dmao.ready = '1' then
v.m.dmaddr(31 downto 2) := r2.m.dmaddr(31 downto 2) + '1';
end if;
-- Translate current CBE to hsize and address
byteaddr := "00";
if endian = 0 then -- pci is little endian
case r2.m.cur_cbe is
when "0000" => -- 32 bit access
vdmai.size := "10"; byteaddr := "00";
when "1100" => -- 16 bit
vdmai.size := "01"; byteaddr := "00";
when "0011" =>
vdmai.size := "01"; byteaddr := "10";
when "1110" => -- 8 bit
vdmai.size := "00"; byteaddr := "00";
when "1101" =>
vdmai.size := "00"; byteaddr := "01";
when "1011" =>
vdmai.size := "00"; byteaddr := "10";
when "0111" =>
vdmai.size := "00"; byteaddr := "11";
when others => vdmai.size := "10";
end case;
else -- big endian
case r2.m.cur_cbe is
when "0000" => -- 32 bit access
vdmai.size := "10"; byteaddr := "00";
when "0011" => -- 16 bit
vdmai.size := "01"; byteaddr := "00";
when "1100" =>
vdmai.size := "01"; byteaddr := "10";
when "0111" => -- 8 bit
vdmai.size := "00"; byteaddr := "00";
when "1011" =>
vdmai.size := "00"; byteaddr := "01";
when "1101" =>
vdmai.size := "00"; byteaddr := "10";
when "1110" =>
vdmai.size := "00"; byteaddr := "11";
when others => vdmai.size := "10";
end case;
end if;
vdmai.address := r2.m.dmaddr(31 downto 2) & byteaddr;
next_cbe := cbe_fifoo.rdata(3 downto 0);
-- AHB master state machine
case r2.m.state is
when idle =>
v.m.read_half := '0';
v.m.last_side_wr := '0';
v.m.cur_cbe := (others => '0');
v.m.fifo.waddr := (others => '0');
if hstart = '1' then
wmdone := '0';
fifowm_limit := '0';
-- v.m.fifo.waddr := (others => '0');
if r.t.lwrite = '1' then
v.m.dmaddr := r.t.laddr;
v.m.state := write;
v.m.cur_cbe := cbe_fifoo.rdata(3 downto 0);
-- burst access
if rtdone = '0' or conv_integer(r.t.fifo.waddr) /= 1 then
v.m.cbe_fifo.raddr := r2.m.cbe_fifo.raddr + 1;
v.m.state := cbe_prepare;
v.m.cbe_prep_cnt := '1';
end if;
-- vdmai.busy := '1';
-- if rmvalid = '1' then v.m.state := write;
-- else vdmai.start := '0'; v.m.state := stop; end if;
else
vdmai.start := '1';
v.m.state := read_w;
end if;
else v.m.dmaddr := r.t.laddr; end if;
when cbe_prepare =>
v.m.cur_cbe := next_cbe;
-- Need to wait for correct cycle to sample next
-- cbe if we have switched FIFO side.
if r2.m.cbe_prep_cnt = '1' then
v.m.state := write;
else
v.m.cbe_prep_cnt := '1';
end if;
when write =>
start := '0';
--if fiform_limit = '1' then
if fiform_limit = '1' and dmao.start = '1' then -- 1k bug fix (store last word in first
v.m.read_half := '1'; -- fifo half if addr = 0x400 ...)
end if;
-- Don't start again until PCI side is done filling second half of fifo (bug fix kc)
if r2.m.read_half = '1' then
if rtdone = '1' then
start := ((rmvalid and not fiform_limit) or (not dmao.active and not rmvalid));
end if;
else
-- vdmai.start := ((rmvalid and not fiform_limit) or (not dmao.active and not rmvalid));
-- 1k bug fix (store last word in first fifo half if addr = 0x400 ...)
start := ((rmvalid and not v.m.read_half) or (not dmao.active and not rmvalid));
end if;
-- Burst CBE handling
if rtdone = '0' or conv_integer(r.t.fifo.waddr) /= 1 then
-- Current or access is subword. Must be forced to single access
if r2.m.cur_cbe /= "0000" then
vdmai.burst := '0';
if dmao.active = '1' then
start := '0';
end if;
end if;
-- Next access is subword. Make current access last in burst
if rmvalid = '1' and next_cbe /= "0000" then
if dmao.active = '1' then
start := '0';
end if;
end if;
end if;
vdmai.start := start;
-- End of data phase for access with cur_cbe
if (dmao.active and dmao.ready) = '1' then
v.m.fifo.raddr := r2.m.fifo.raddr + (rmvalid and not fiform_limit and not dmao.mexc);
v.m.cbe_fifo.raddr := r2.m.cbe_fifo.raddr + (rmvalid and not fiform_limit and not dmao.mexc);
v.m.last_side_wr := m_read_side;
-- First half of FIFO
if v.m.read_half = '0' then
v.m.cur_cbe := next_cbe;
-- FIFO side switch
elsif r2.m.read_half = '0' then
v.m.cbe_prep_cnt := '0';
v.m.state := cbe_prepare;
elsif v.m.last_side_wr = '0' then
v.m.cbe_prep_cnt := '0';
v.m.state := cbe_prepare;
-- Second side of FIFO
else
v.m.cur_cbe := next_cbe;
end if;
if (dmao.mexc = '1' or rmvalid = '0') then
habort := dmao.mexc and not r.t.lwrite;
v.werr := r2.werr or (dmao.mexc and r.t.lwrite);
v.m.state := stop;
end if;
end if;
when read_w =>
vdmai.start := not (comp and dmao.active);
if dmao.mexc = '1' then
habort := not r.t.lwrite;
v.werr := '1';
v.m.state := stop;
elsif dmao.ready = '1' then
fifom_write := '1';
wmvalid := not (comp or dmao.mexc);
if comp = '1' then
v.m.state := stop;
v.m.fifo.waddr := r2.m.fifo.waddr + '1';
else
v.m.fifo.waddr := r2.m.fifo.waddr + (not fifowm_limit);
v.m.state := read; end if;
end if;
when read =>
vdmai.start := not (comp and dmao.active);
fifom_write := dmao.ready; wmvalid := not (comp or dmao.mexc);
-- if ((comp and dmao.ready) or dmao.retry) = '1' then
if (comp and dmao.ready) = '1' then
v.m.state := stop; v.m.fifo.waddr := r2.m.fifo.waddr + '1';
elsif (dmao.active and dmao.ready) = '1' then
v.m.fifo.waddr := r2.m.fifo.waddr + (not dmao.mexc and not fifowm_limit);
if dmao.mexc = '1' then habort := not r.t.lwrite; v.werr := r2.werr or r.t.lwrite; v.m.state := stop; end if;
end if;
when stop =>
if hstart = '0' and ((r.t.lwrite and not fiform_limit) = '1' or wmdone = '1') then
v.m.state := idle; hstart_ack := '0';
v.m.fifo.side := '0'; habort := '0';
v.m.fifo.raddr := (others => '0');
v.m.cbe_fifo.raddr := (others => '0');
else
comp := '1';
fiform_limit := r.t.lwrite;
fifowm_limit := not r.t.lwrite;
end if;
end case;
-- FIFO control
if fifowm_limit = '1' then
-- if (((r2.m.fifo.side or hstart_ack or (not hstart)) = '0' and not (dmao.active and not dmao.ready) = '1')
if (((r2.m.fifo.side or hstart_ack or (not hstart)) = '0' and (dmao.ready or comp) = '1')
or ((hstart_ack and not hstart) = '1' and v.m.state = stop)) then
if v.m.state = stop then wmdone := '1';
else v.m.fifo.waddr := (others => '0'); end if;
hstart_ack := '1';
v.m.fifo.side := not r2.m.fifo.side;
end if;
elsif fiform_limit = '1' then
-- if dmao.active = '0' then
if dmao.active = '0' and dmai.start = '0' then -- 1k bug fix ***
m_read_side := '1';
hstart_ack := '1';
-- v.m.fifo.raddr := (others => hstart);
v.m.fifo.raddr := (others => '0'); -- 1k bug fix ***
v.m.cbe_fifo.raddr := conv_std_logic_vector(1, FIFO_DEPTH-1);
end if;
end if;
-----------------------
--- AHB MASTER END ----
-----------------------
-------------------
---- AHB SLAVE ----
-------------------
-- if MASTER = 1 then
-- Access decode
if (ahbsi.hready and ahbsi.hsel(hslvndx)) = '1' then
if (ahbsi.hmbsel(0) or ahbsi.hmbsel(1)) = '1' then
hsize := ahbsi.hsize(1 downto 0); v.s.htrans := ahbsi.htrans;
--if (v.s.htrans(1) and r.comm.msen) = '1' then request := '1'; end if;
if (v.s.htrans(1) and r.comm.msen) = '1' then -- fix access control ***
ahb_access := '1';
--if (r2.s.state /= r_wait and r2.s.state /= r_hold) or r2.s.hmaster = ahbsi.hmaster then
--if (r2.s.state = idle or r2.s.state = t_done) or r2.s.hmaster = ahbsi.hmaster then
if (r2.s.state = idle) or r2.s.hmaster = ahbsi.hmaster then
request := '1';
end if;
end if;
end if;
end if;
-- Access latches
if (request = '1' and r2.s.state = idle) then
if ahbsi.hmbsel(1) = '1' then
if ahbsi.haddr(16) = '1' then -- Configuration cycles
v.s.maddr := (others => '0');
if r2.bus_nr = "0000" then -- Type 0
v.s.maddr(conv_integer(ahbsi.haddr(15 downto 11)) + 10) := '1';
v.s.maddr(10 downto 0) := ahbsi.haddr(10 downto 2) & "00";
else -- Type 1
v.s.maddr(19 downto 0) := r2.bus_nr & ahbsi.haddr(15 downto 2) & "01";
end if;
v.s.pcicomm := "101" & ahbsi.hwrite;
else -- I/O space access
v.s.maddr(31 downto 16) := r2.ioba;
v.s.maddr(15 downto 0) := ahbsi.haddr(15 downto 0);
v.s.pcicomm := "001" & ahbsi.hwrite;
end if;
else -- Memory space access
if conv_integer(ahbsi.hmaster) = dmamst then
v.s.maddr := ahbsi.haddr;
else
v.s.maddr := r2.pciba & ahbsi.haddr(31-HMASK_WIDTH downto 2) & "00";
end if;
if ahbsi.hwrite = '1' then
v.s.pcicomm := r2.wcomm & "111";
else
v.s.pcicomm := ahbsi.hburst(0) & '1' & (r2.rcomm or not ahbsi.hburst(0)) & '0';
end if;
end if;
-- Decode HSIZE and HADDR
if endian = 0 then -- pci is little endian
case hsize is
when "00" => -- Decode byte enable
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "1110";
when "01" => v.s.be := "1101";
when "10" => v.s.be := "1011";
when "11" => v.s.be := "0111";
when others => v.s.be := "1111";
end case;
when "01" =>
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "1100";
when "10" => v.s.be := "0011";
when others => v.s.be := "1111";
end case;
when "10" => v.s.be := "0000";
when others => v.s.be := "1111";
end case;
else -- pci is big endian
case hsize is
when "00" => -- Decode byte enable
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "0111";
when "01" => v.s.be := "1011";
when "10" => v.s.be := "1101";
when "11" => v.s.be := "1110";
when others => v.s.be := "1111";
end case;
when "01" =>
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "0011";
when "10" => v.s.be := "1100";
when others => v.s.be := "1111";
end case;
when "10" => v.s.be := "0000";
when others => v.s.be := "1111";
end case;
end if;
end if;
if ((rmdone and not r2.s.pcicomm(0)) = '1' and (r2.s.fifo.raddr + '1' + pcidc) = r.m.fifo.waddr) then rsvalid := '0'; end if;
-- FIFO address counters
-- if (r2.s.state = t_data or r2.s.state = w_wait) then
if (r2.s.state = t_data or r2.s.state = w_wait or -- bug fix ***
(r2.s.state = r_hold and fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1')) then -- (r_hold -> t_data) bug fix ***
v.s.fifos_write := r2.s.pcicomm(0) and r2.s.htrans(1);
v.s.fifo.waddr := r2.s.fifo.waddr + r2.s.fifos_write;
v.s.fifo.raddr := r2.s.fifo.raddr + ((ahbsi.htrans(1) and not r2.s.pcicomm(0) and not fifors_limit and rsvalid) or not ahbsi.hready);
end if;
if pstart_ack = '1' then
if pabort = '1' then
if (r2.s.pcicomm = CONF_WRITE or r2.s.pcicomm = CONF_READ) then v.cfto := '1';
else v.s.perror := '1'; end if;
else v.s.perror := '0'; v.cfto := '0'; end if;
end if;
--
-- AHB slave state machine
case r2.s.state is
when idle =>
if request = '1' and p_done = '0' then
if ahbsi.hwrite = '1' then
v.s.state := w_wait;
v.s.fifo.side := '0';
else
pstart := '1'; v.s.state := r_wait;
end if;
v.s.hmaster := ahbsi.hmaster;
end if;
when w_wait =>
if ((ahbsi.hready and not ahbsi.htrans(0)) = '1') then
v.s.state := w_done; fifows_limit := not wsvalid;
else
v.s.state := t_data;
end if;
when t_data =>
burst_read := ahbsi.htrans(1) and not fifors_limit;
if (fifows_stop and r2.s.fifos_write) = '1' then
if r2.s.fifo.side = '1' then
v.s.state := w_done;
end if;
elsif ((fifors_limit or not rsvalid) = '1' and v.s.htrans(1) = '1') then
if (r.m.fifo.side = '0') or (rsvalid = '0') then
v.s.state := t_done;
else v.s.state := r_hold; end if;
end if;
if ((ahbsi.hready and not ahbsi.htrans(0)) = '1') then
if r2.s.pcicomm(0) = '1' then
--v.s.state := w_done; wsvalid := '0';
v.s.state := w_done;
if ahbsi.htrans /= "00" then wsvalid := '0'; end if; -- fix dont set wsvalid if amba idle
else -- (if wsvalid = 0 side is changed before last write
v.s.state := t_done; -- to fifo if hrans = 00)
wsvalid := '0'; -- Bug fix, must give RETRY here! /KC
end if;
end if;
when r_hold =>
s_read_side := '1';
if fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1' then
if rmdone = '0' then -- bug fix ***
v.s.state := t_data;
burst_read := ahbsi.htrans(1) and not fifors_limit; -- bug fix ***
else
v.s.state := t_done;
end if;
elsif (ahbsi.hready = '1' and ahbsi.htrans = "00" and r2.s.hresp = HRESP_OKAY) then -- (idle -> t_done) bug fix ***
v.s.state := t_done;
else v.s.hold := '1'; end if;
when r_wait =>
s_read_side := '0';
if (pstart_ack and request) = '1' then
v.s.state := t_data; hready := '0';
end if;
if r2.s.hmaster /= ahbsi.hmaster and conv_integer(ahbsi.hmaster) = dmamst and pstart_ack = '1' then -- if pcidma cancel read
v.s.state := t_done;
end if;
when w_done =>
v.s.state := t_done; wsvalid := '0';
-- if (r2.s.htrans(1) or not fifows_limit) = '1' then
-- if (r2.s.htrans(1) and fifows_limit) = '1' then
v.s.fifo.waddr := r2.s.fifo.waddr + r2.s.fifos_write;
-- end if;
fifows_limit := '1';
when t_done =>
wsvalid := '0';
fifors_limit := not r2.s.pcicomm(0);
if (pstart or pstart_ack) = '0' then
v.s.state := idle; v.s.perror := '0';
v.s.fifo.waddr := (others => '0'); wsdone := '0'; fifows_limit := '0';
v.s.pcicomm := (0 => '1', others => '0'); -- default write
else fifows_limit := r2.s.pcicomm(0); end if;
end case;
-- Respond encoder
if v.s.state = t_data
or (v.s.state = r_hold and v.s.hold = '0') -- bug fix ***
or (v.s.state = t_done and r2.s.state = t_data) -- (end of trans) bug fix ***
or (v.s.state = w_wait and ahbsi.hwrite = '1') then
if r2.s.perror = '1' then hresp := HRESP_ERROR;
elsif wsvalid = '1' then hresp := HRESP_OKAY;
else hresp := HRESP_RETRY; end if;
v.s.perror := '0';
else hresp := HRESP_RETRY; end if;
if r.comm.msen = '0' then hresp := HRESP_ERROR; end if; -- Master disabled
--if (v.s.htrans(1) and request) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE
if (v.s.htrans(1) and ahb_access) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE -- *** access control fix
if (hresp /= HRESP_OKAY or hready = '0') then v.s.hready := '0'; else v.s.hready := '1'; end if;
-- Dont change hresp during wait states
if ahbsi.hready = '0' then hresp := r2.s.hresp; end if;
v.s.hresp := hresp;
-- FIFO controller
if fifows_limit = '1' then
if (r2.s.fifos_write or not wsvalid) = '1' and (r2.s.fifo.side = '0' or pstart_ack = '1') then
--if wsvalid = '0' then wsdone := '1';
if wsvalid = '0' or v.s.state = w_done then wsdone := '1'; -- fix set wsdone and pstart at the same time
else v.s.fifo.waddr := (others => '0'); end if;
pstart := not pstart_ack;
v.s.fifo.side := pstart;
end if;
elsif ((r2.s.state = t_done or r2.s.state = r_hold) and fifors_limit = '1') then
if pstart_ack = '1' then pstart := '0'; v.s.fifo.raddr := (others => '0');
else v.s.fifo.raddr := (others => '0'); end if;
end if;
-- Set last fifo side written so that PCI master knows when to stop
if (r2.s.fifos_write = '1') then
v.s.last_side := r2.s.fifo.side;
end if;
-- end if;
-----------------------
---- AHB SLAVE END ----
-----------------------
-- Sync registers
v.trans(0) := pstart;
v.trans(1) := habort;
v.trans(2) := hstart_ack;
v.trans(3) := fifows_limit;
v.trans(4) := wsdone;
v.trans(5) := wmdone;
-- input data for write accesses
if r2.s.pcicomm(0) = '1' then v.s.mdata := ahbsi.hwdata; end if;
-- output data for read accesses
-- if (ahbsi.htrans(1) and not r2.s.hold and not r2.s.pcicomm(0)) = '1' then v.s.mdata := fifo4o.rdata(31 downto 0); end if;
if (ahbsi.htrans(1) and not r2.s.pcicomm(0)) = '1' then v.s.mdata := fifo4o.rdata(31 downto 0); end if; -- bug fix ***
-- irq
apbo.pirq <= (others => '0');
if irq /= 0 then
if to_x01(pcii.host) = '0' then
apbo.pirq(irq) <= orv((not pcii.int) and conv_std_logic_vector(irqmask,4));
end if;
end if;
if rst = '0' then
v.s.state := idle;
v.m.state := idle;
v.s.perror := '0';
v.pciba := (others => '0');
v.trans := (others => '0');
v.m.cbe_fifo.waddr := (others => '0');
v.m.cbe_fifo.raddr := (others => '0');
v.m.fifo.waddr := (others => '0');
v.m.fifo.raddr := (others => '0');
v.s.fifo.waddr := (others => '0');
v.s.fifo.raddr := (others => '0');
v.m.fifo.side := '0';
v.s.fifo.side := '0';
v.wcomm := '0';
v.rcomm := '0';
v.werr := '0';
v.cfto := '0';
v.dmapage := (others => '0');
v.ioba := (others => '0');
v.pciirq := "11";
v.bus_nr := (others => '0');
end if;
apbo.prdata <= prdata;
ahbso.hready <= r2.s.hready;
ahbso.hresp <= r2.s.hresp;
ahbso.hrdata <= byte_twist(r2.s.mdata, r.bt_enable);
ahbso.hindex <= hslvndx;
fifo1i.wen <= fifom_write;
fifo1i.waddr <= r2.m.fifo.side & r2.m.fifo.waddr;
fifo1i.wdata <= dmao.rdata;
fifo2i.ren <= '1';
fifo2i.raddr <= m_read_side & (r2.m.fifo.raddr + dmao.ready);
fifo3i.wen <= r2.s.fifos_write;
fifo3i.waddr <= r2.s.fifo.side & r2.s.fifo.waddr;
fifo3i.wdata <= byte_twist(r2.s.mdata, r.bt_enable);
fifo4i.ren <= '1';
fifo4i.raddr <= s_read_side & (r2.s.fifo.raddr + burst_read);
cbe_fifoi.ren <= '1';
cbe_fifoi.raddr <= m_read_side & (r2.m.cbe_fifo.raddr + dmao.ready); -- read one cycle before data fifo
r2in <= v; dmai <= vdmai;
end process;
ahbso.hconfig <= hconfig when MASTER = 1 else (others => zero32);
ahbso.hcache <= '0';
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
---------------------------------
-- PCI core (PCI clock domain) --
---------------------------------
pcicomb : process(pr, pcii, r, r2, fifo1o, fifo3o, roe_ad, prrst)
variable v : pci_reg_type;
variable chit, mhit0, mhit1, phit, hit, hosthit, ready, cwrite, retry : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable comp : std_logic; -- Last transaction cycle on PCI bus
variable mto, tto, term, ben_err, lto : std_logic;
variable i : integer range 0 to NO_PCI_REGS;
variable tad, mad : std_logic_vector(31 downto 0);
variable pstart, habort, hstart_ack, wsdone, wmdone : std_logic;
variable hstart, pabort, pstart_ack, pcidc, rtdone, rmdone : std_logic;
variable fifort_limit, fifowt_limit, fiform_limit, fifowm_limit, fifowm_stop, t_valid : std_logic;
variable d_ready, tabort, backendnr : std_logic;
variable m_fifo_write, t_fifo_write, grant : std_logic;
variable write_access, memwrite, memread, read_match, m_read_side, t_read_side : std_logic;
variable readt_dly : std_logic; -- 1 turnaround cycle
variable bus_idle, data_transfer, data_transfer_r, data_phase, targ_d_w_data, targ_abort, m_request : std_logic;
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_par : std_logic;
variable oe_ad : std_logic;
variable oe_ctrl : std_logic;
variable oe_cbe : std_logic;
variable oe_frame : std_logic;
variable oe_irdy : std_logic;
variable oe_req : std_logic;
variable oe_perr : std_logic;
begin
-- Process defaults
v := r; v.pci.trdy := '1'; v.pci.stop := '1'; v.pci.frame := '1';
v.pci.oe_ad := '1'; v.pci.devsel := '1'; v.pci.oe_frame := '1';
v.pci.irdy := '1'; v.pci.req := '1'; hosthit := '0'; m_request := '0';
v.pci.oe_req := '0'; v.pci.oe_cbe := '1'; v.pci.oe_irdy := '1';
mto := '0'; tto := '0'; v.m.stop_req := '0'; lto := '0';
cdata := (others => '0'); retry := '0'; t_fifo_write := '0';
chit := '0'; phit := '0'; mhit0 := '0'; mhit1 := '0'; tabort := '0';
readt_dly := '0'; m_fifo_write := '0'; voe_ad := roe_ad;
tad := r.pci.ad; mad := r.pci.ad; grant := pcii.gnt; d_ready := '0';
m_read_side := not r2.s.fifo.side; t_read_side := not r2.m.fifo.side;
v.m.rmdone := '0';
write_access := not r.t.read and not pr.irdy and not pr.trdy;
memwrite := r.t.msel and r.t.lwrite and not r.t.read;
memread := r.t.msel and not r.t.lwrite and r.t.read;
-- Synch registers
hstart := r.trans(0);
pabort := r.trans(1);
pstart_ack := r.trans(2);
pcidc := r.trans(3);
rtdone := r.trans(4);
rmdone := r.trans(5);
for i in 0 to NO_PCI_REGS - 1 loop
v.syncs(i)(csync) := r2.trans(i);
if csync /= 0 then v.syncs(i)(0) := r.syncs(i)(csync); end if;
end loop;
pstart := r.syncs(0)(0);
habort := r.syncs(1)(0);
hstart_ack := r.syncs(2)(0);
backendnr := r.syncs(3)(0);
wsdone := r.syncs(4)(0);
wmdone := r.syncs(5)(0);
-- FIFO limit detector
if r.t.fifo.raddr = FIFO_FULL then fifort_limit := '1'; else fifort_limit := '0'; end if;
if r.t.fifo.waddr = FIFO_FULL then fifowt_limit := '1'; else fifowt_limit := '0'; end if;
if r.m.fifo.raddr = FIFO_FULL then fiform_limit := '1'; else fiform_limit := '0'; end if;
if r.m.fifo.waddr = FIFO_FULL then fifowm_limit := '1'; else fifowm_limit := '0'; end if;
if r.m.fifo.waddr(FIFO_DEPTH - 2 downto 1) = FIFO_FULL(FIFO_DEPTH - 2 downto 1) then fifowm_stop := '1'; else fifowm_stop := '0'; end if;
-- useful control variables
--if (r.t.laddr = r.page & r.t.addr(MADDR_WIDTH-2 downto 0) or r.t.laddr = r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 0))
if (r.t.laddr(31 downto 2) = r.page & r.t.addr(MADDR_WIDTH-2 downto 2) -- bug fix match if byte access
or r.t.laddr(31 downto 2) = r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 2))
and (r.t.lcbe = pr.cbe) -- bug fix match byte access
and (r.t.lburst = r.t.burst) then read_match := r.t.pending; else read_match := r.t.csel or r.t.psel; end if;
-- if (pr.cbe = "0000" and r.t.lsize = "10") or (pr.cbe = "1100" and r.t.lsize = "01") or (pr.cbe = "1110" and r.t.lsize = "00")
-- pragma translate_off
-- or (pr.cbe = "XXXX") -- For simulation purposes
-- pragma translate_on
-- then ben_err := '0'; else ben_err := '1'; end if;
ben_err := '0';
if r.stat.dpe = '0' then v.stat.dpe := not r.pci.perr; end if;
-------------------------
----- PCI TARGET --------
-------------------------
-- Data valid?
if ((wmdone and not r.t.lwrite) = '1' and (r.t.fifo.raddr + '1') = r2.m.fifo.waddr) then t_valid := '0';
else t_valid := not fifowt_limit or not r.t.fifo.side; end if;
-- Step addresses
if (r.t.state = s_data or r.t.state = turn_ar or r.t.state = backoff) then
if (pcii.irdy or r.pci.trdy) = '0' then
v.t.addr := r.t.addr + ((r.t.csel and r.t.read) & "00");
readt_dly := '1';
if r.t.msel = '1' then
v.t.wdel := (fifort_limit and r2.m.fifo.side) or r.t.lwrite;
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and not fifort_limit and t_valid);
end if;
end if;
if write_access = '1' then
v.t.fifo.waddr := r.t.fifo.waddr + (r.t.msel and not r.t.read and not ben_err);
t_fifo_write := r.t.msel;
v.t.addr := r.t.addr + ((r.t.csel and not r.t.read) & "00");
end if;
tabort := habort;
else v.t.wdel := '0'; end if;
-- Config space read access
case r.t.addr(7 downto 2) is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.comm.men; cdata(2) := r.comm.msen;
cdata(4) := r.comm.mwie; cdata(6) := r.comm.per;
cdata(24) := r.stat.dped; cdata(26) := '1';
cdata(27) := r.stat.sta; cdata(28) := r.stat.rta;
cdata(29) := r.stat.rma; cdata(31) := r.stat.dpe;
when "000010" => -- 0x08, class code & revision
cdata(31 downto 0) := conv_std_logic_vector(CLASS_CODE,24) & conv_std_logic_vector(REV,8) ;
when "000011" => -- 0x0C, latency & cacheline size
cdata(7 downto 0) := r.cline;
cdata(15 downto 8) := r.ltim;
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when "000101" => -- 0x14, BAR1
cdata(31 downto DMAMADDR_WIDTH) := r.bar1;
when "001111" => -- 0x3C, Interrupts & Latency timer settings
cdata(7 downto 0) := r.intline; -- Interrupt line
cdata(8) := '1'; -- Use interrupt pin INTA#
if fifodepth < 11 then cdata(fifodepth+13) := '1'; end if; --Define wanted burst period
when others =>
end case;
-- Config space write access
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if (r.t.csel and write_access) = '1' then
case r.t.addr(7 downto 2) is
when "000001" => -- 0x04, status & command
v.comm.men := cwdata(1);
if MASTER = 1 then v.comm.msen := cwdata(2); end if;
v.comm.mwie := cwdata(4); v.comm.per := cwdata(6);
v.stat.dped := r.stat.dped and not cwdata(24); -- Sticky bit
v.stat.sta := r.stat.sta and not cwdata(27); -- Sticky bit
v.stat.rta := r.stat.rta and not cwdata(28); -- Sticky bit
v.stat.rma := r.stat.rma and not cwdata(29); -- Sticky bit
v.stat.dpe := r.stat.dpe and not cwdata(31); -- Sticky bit
when "000011" => -- 0x0c, latency & cacheline size
if FIFO_DEPTH <= 7 then v.cline(FIFO_DEPTH - 1 downto 0) := cwdata(FIFO_DEPTH - 1 downto 0);
else v.cline := cwdata(7 downto 0); end if;
v.ltim := cwdata(15 downto 8);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
if v.bar0 = zero(31 downto MADDR_WIDTH) then v.bar0_conf := '0'; else v.bar0_conf := '1'; end if;
when "000101" => -- 0x14, BAR1
v.bar1 := cwdata(31 downto DMAMADDR_WIDTH);
if v.bar1 = zero(31 downto DMAMADDR_WIDTH) then v.bar1_conf := '0'; else v.bar1_conf := '1'; end if;
when "001111" => -- 0x3C, Interrupts & Latency timer settings
v.intline := cwdata(7 downto 0); -- Interrupt line
when others =>
end case;
end if;
-- Page bar write
if (r.t.psel and write_access) = '1' then
v.page := pr.ad(31 downto MADDR_WIDTH - 1);
v.bt_enable := pr.ad(0);
end if;
-- Command and address decode
case pr.cbe is
when CONF_READ | CONF_WRITE =>
if pr.ad(1 downto 0) = "00" then chit := '1'; end if;
if pr.host = '0' then --Active low
if pr.ad(31 downto 11) = "000000000000000000000" then hosthit := '1'; end if;
end if;
when MEM_READ | MEM_WRITE =>
if pr.ad(31 downto MADDR_WIDTH) = r.bar0 then
phit := r.bar0_conf and pr.ad(MADDR_WIDTH - 1);
mhit0 := r.bar0_conf and not pr.ad(MADDR_WIDTH - 1);
elsif pr.ad(31 downto DMAMADDR_WIDTH) = r.bar1 then
mhit1 := r.bar1_conf;
end if;
when MEM_R_MULT | MEM_R_LINE | MEM_W_INV =>
if pr.ad(31 downto MADDR_WIDTH - 1) = r.bar0 & '0' then mhit0 := r.bar0_conf;
elsif pr.ad(31 downto DMAMADDR_WIDTH) = r.bar1 then mhit1 := r.bar1_conf; end if;
when others => phit := '0'; mhit0 := '0'; chit := '0'; mhit1 := '0';
end case;
-- Hit detect
hit := r.t.csel or r.t.msel or r.t.psel;
if (hstart and r.pci.devsel) = '1' then
if (r.t.pending or r.t.lwrite) = '0' then
hstart := not hstart_ack;
v.t.fifo.raddr := (others => '0');
end if;
end if;
-- Ready to transfer data
if ((r.t.csel and not readt_dly) or r.t.psel) = '1'
or ((((memwrite and not r.pci.devsel) = '1')
or (memread = '1' and not (hstart_ack and v.t.wdel) = '1')) and ben_err = '0')
then ready := '1'; else ready := '0'; t_read_side := r.t.read and not hstart; end if;
-- Target timeout counter
--if (hit and pr.trdy and not (pr.frame and pr.irdy)) = '1' then
--if (hit and pr.trdy and not (pr.frame and pr.irdy) and v.t.wdel) = '1' then
if (hit and pr.trdy and not (pr.frame and pr.irdy) and not ready) = '1' then
if r.t.cnt /= "000" then v.t.cnt := r.t.cnt - 1;
else tto := '1'; end if;
else v.t.cnt := (0 => '0', others => '1'); end if;
-- -- Ready to transfer data
-- if ((r.t.csel and not readt_dly) or r.t.psel) = '1'
-- or ((((memwrite and not r.pci.devsel) = '1')
-- or (memread = '1' and not (hstart_ack and v.t.wdel) = '1')) and ben_err = '0')
-- then ready := '1'; else ready := '0'; t_read_side := r.t.read and not hstart; end if;
-- Terminate current transaction
if (((r.t.fifo.waddr >= (FIFO_FULL - "10") and r.t.fifo.side = '1')
or (t_valid = '0') or r.pci.stop = '0') and pcii.frame = '0')
or ((r.t.read xor r.t.lwrite) = '0' and r.pci.devsel = '0')
or (tto = '1') or (ben_err = '1')
then
term := '1';
else term := '0'; end if;
-- Retry transfer
if r.t.state = b_busy then
if not ((r.t.read and not r.t.lwrite and hstart_ack and read_match) = '1'
or (r.t.read or hstart or hstart_ack) = '0'
or ((r.t.csel or r.t.psel) and not hstart and not hstart_ack) = '1')
then
retry := '1';
end if;
end if;
-- target state machine
case r.t.state is
when idle =>
if pr.frame = '0' then v.t.state := b_busy; end if; -- !HIT ?
v.t.addr := pr.ad;
if readpref = 1 then v.t.burst := '1';
else v.t.burst := pr.cbe(3); end if;
v.t.read := not pr.cbe(0); v.t.mult := not pr.cbe(1);
v.t.csel := (pr.idsel or hosthit) and chit; v.t.psel := phit;
v.t.msel := r.comm.men and (mhit0 or mhit1); v.t.barsel := mhit1;
when turn_ar =>
if pr.frame = '1' then
v.t.state := idle;
v.t.fifo.raddr := (others => '0'); -- fix reset fifo read address
else v.t.state := b_busy; end if; -- !HIT ?
v.t.addr := pr.ad; v.t.wdel := '1';
if readpref = 1 then v.t.burst := '1';
else v.t.burst := pr.cbe(3); end if;
v.t.read := not pr.cbe(0); v.t.mult := not pr.cbe(1);
v.t.csel := (pr.idsel or hosthit) and chit; v.t.psel := phit;
v.t.msel := r.comm.men and (mhit0 or mhit1); v.t.barsel := mhit1;
when b_busy =>
if (pr.frame and pr.irdy) = '1' then
v.t.state := idle;
elsif hit = '1' then
v.t.state := s_data;
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and r.t.msel);
readt_dly := '1';
if r.t.pending = '0' then
v.t.pending := retry and not hstart_ack;
end if;
end if;
-- else v.t.state := backoff; end if;
-- We should not go to back off if the access wasn't to us
when s_data =>
if r.t.pending = '1' then v.t.pending := not ((habort or not r.pci.trdy) and read_match); end if;
if (pcii.frame = '0' and r.pci.stop ='0' and (r.pci.trdy or not pcii.irdy) = '1') then
v.t.state := backoff;
if r.t.last = '0' then v.t.last := r.t.msel and r.t.lwrite and v.t.wdel; end if;
v.t.fifo.raddr := r.t.fifo.raddr - (r.t.read and r.t.msel and not fifort_limit);
-- elsif (pcii.frame = '1' and (r.pci.trdy = '0' or r.pci.stop = '0')) then
elsif (pcii.frame = '1' and (r.t.trdy_del = '0' or r.pci.stop = '0')) then -- (send last word in fifo) bug fix ***
v.t.state := turn_ar;
if r.t.last = '0' then v.t.last := r.t.msel and r.t.lwrite and v.t.wdel; end if;
v.t.fifo.raddr := r.t.fifo.raddr - (r.t.read and r.t.msel and not fifort_limit);
end if;
when backoff =>
if pcii.frame = '1' then v.t.state := turn_ar; end if;
end case;
-- #TRDY assert
if (v.t.state = s_data and habort = '0' and ready = '1' and retry = '0') then v.pci.trdy := '0'; end if;
-- #STOP assert
if (v.t.state = backoff or (v.t.state = s_data and ((tabort or ((term or retry) and not habort)) = '1'))) then
v.pci.stop := '0'; end if;
-- #DEVSEL assert
if (((v.t.state = backoff and r.pci.devsel = '0') or v.t.state = s_data) and (read_match and tabort) = '0') then v.pci.devsel := '0'; end if;
-- Enable #TRDY, #STOP and #DEVSEL
if (v.t.state = s_data) or (v.t.state = backoff) or (v.t.state = turn_ar) then
v.pci.oe_ctrl := not hit;
else v.pci.oe_ctrl := '1'; end if;
-- Signaled target abort
if (r.pci.devsel and not (r.pci.stop or r.pci.oe_ctrl)) = '1' then v.stat.sta := '1'; end if;
if r.t.state = s_data and v.t.state = s_data and r.pci.trdy = '0'
and v.pci.trdy = '1' and v.t.wdel = '1' and pcii.frame = '0' then -- (send last word in fifo) bug fix ***
v.t.trdy_del := '0';
else
v.t.trdy_del := v.pci.trdy;
end if;
if r.t.state = s_data and r.pci.trdy = '1' and v.pci.trdy = '0' and pcii.frame = '0' then -- bug fix ***
readt_dly := '1';
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and not fifort_limit and t_valid);
end if;
-- Latched signals to AHB backend
if (r.t.state = b_busy) then
if (hstart or hstart_ack) = '0' then -- must be idle
v.t.lwrite := not r.t.read;
if r.t.msel = '1' then
v.t.lburst := r.t.burst;
v.t.lcbe := pr.cbe;
if r.t.barsel = '0' then v.t.laddr := r.page & r.t.addr(MADDR_WIDTH-2 downto 2) & "00";
else v.t.laddr := r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 2) & "00"; end if;
v.t.lmult := r.t.mult;
rtdone := '0'; v.t.fifo.waddr := (others => '0');
hstart := r.t.read and r.t.msel;
end if;
end if;
end if;
-- Read data mux
if r.t.csel = '1' then tad := cdata;
elsif r.t.psel = '1' then
tad(31 downto MADDR_WIDTH-1) := r.page;
tad(MADDR_WIDTH-2 downto 0) := zero32(MADDR_WIDTH-2 downto 1) & r.bt_enable;
-- elsif (r.t.state = b_busy or (r.pci.trdy or pcii.irdy) = '0') then tad := fifo1o.rdata(31 downto 0);
elsif (r.t.state = b_busy or (r.pci.trdy or pcii.irdy) = '0' or r.t.wdel = '1') then tad := byte_twist(fifo1o.rdata(31 downto 0), r.bt_enable); -- bug fix ***
end if;
-- FIFO controller
if ((fifowt_limit and write_access) = '1' or (r.t.last or rtdone) = '1') then
if hstart = hstart_ack then
if rtdone = '0' then hstart := not hstart_ack; v.t.fifo.side := hstart; end if;
if r.t.last = '1' then rtdone := '1'; v.t.last := '0';
else v.t.fifo.waddr := (others => '0');
if rtdone = '1' then
rtdone := '0'; hstart := '0'; v.t.fifo.side := '0';
end if;
end if;
end if;
end if;
if (fifort_limit and v.t.wdel) = '1' then
if hstart_ack = '1' then hstart := '0'; v.t.fifo.raddr := (others => '0');
else v.t.fifo.raddr := (others => '0'); end if;
end if;
----------------------
--- PCI TARGET END ---
----------------------
------------------
--- PCI MASTER ---
------------------
if MASTER = 1 then
bus_idle := pcii.frame and pcii.irdy;
data_transfer := not (pcii.trdy or r.pci.irdy);
data_transfer_r := not (pr.trdy or pr.irdy);
data_phase := not ((pcii.trdy and pcii.stop) or r.pci.irdy);
targ_d_w_data := not (pr.stop or pr.trdy);
targ_abort := pr.devsel and not pr.stop;
-- Request from AHB backend to start PCI transaction
if (pstart and not pstart_ack) = '1' then
if (r.m.fstate = idle and r.m.request = '0') then
v.m.request := '1';
rmdone := '0'; v.m.valid := '1';
v.m.fifo.waddr := (others => '0');
v.m.hwrite := r2.s.pcicomm(0);
end if;
end if;
-- Master timeout and DEVSEL timeout
if ((pr.irdy and not pr.frame) or (pr.devsel and not r.pci.oe_frame)) = '1' then
if r.m.cnt /= "000" then v.m.cnt := r.m.cnt - 1;
else mto := '1'; end if;
else v.m.cnt := (others => '1'); end if;
-- Latency counter
if r.pci.frame = '0' then
if r.m.ltim > "00000000" then v.m.ltim := r.m.ltim - '1';
else lto := '1'; end if;
else
v.m.ltim := r.ltim;
end if;
-- Last data
case r2.s.pcicomm is
when MEM_R_MULT | MEM_R_LINE =>
if (r.m.fifo.waddr >= (FIFO_FULL - "10") and r.m.fifo.side = '1') then
comp := '1';
else comp := '0'; end if;
when MEM_WRITE | MEM_W_INV => comp := not r.m.valid;
when others => comp := '1';
end case;
-- Minimun latency
--if lto = '0' then grant := '0'; end if;
if lto = '0' then grant := '0'; -- latency timer bug fix
elsif pcii.gnt = '1' then v.m.lto := '1'; end if;
-- Data parity error detected
if (r.m.fstate /= idle and r.stat.dped = '0') then v.stat.dped := r.comm.per and not pcii.perr; end if;
-- FIFO control state machine
case r.m.fstate is
when idle =>
v.m.lto := '0';
if (r.m.request and bus_idle and not pcii.gnt) = '1' and (r.m.state = idle or r.m.state = dr_bus) then
v.m.fstate := addr; v.m.fifo.waddr := (others => '0'); v.m.fifo.side := '0'; m_request := '1';
end if;
when addr =>
-- if (wsdone = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (wsdone = '1' and ((r.m.fifo.raddr + '1') = r2.s.fifo.waddr) and (m_read_side = r2.s.last_side)) then v.m.valid := '0'; end if; --bug fix kc
if fiform_limit = '1' then v.m.fstate := last1;
else v.m.fstate := incr; end if;
v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
v.m.first := '1'; v.m.firstw := '1';
when incr =>
d_ready := '1';
if r.m.valid = '0' then v.m.lto := '0'; end if; -- dont look at latency timer if done
if data_transfer = '1' then
--if fiform_limit = '1' then v.m.fstate := last1; v.m.split := not backendnr; end if;
if fiform_limit = '1' and r.m.lto = '0' then v.m.fstate := last1; v.m.split := not backendnr; end if; -- bug fix latency timer
-- if (wsdone = '1' and (r.m.fifo.raddr + pcii.stop) = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (wsdone = '1' and ((r.m.fifo.raddr + pcii.stop) = r2.s.fifo.waddr) and (m_read_side = r2.s.last_side)) then v.m.valid := '0'; end if; --bug fix kc
v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
v.m.first := '0';
end if;
if data_transfer_r = '1' then
if fifowm_stop = '1' then
if r.m.firstw = '1' then
if (fifowm_limit and pr.stop) = '1' then v.m.fifo.side := not r.m.fifo.side; v.m.firstw := '0'; pstart_ack := pstart; end if;
end if;
end if;
v.m.fifo.waddr := r.m.fifo.waddr + (not r.m.hwrite);
end if;
if pr.stop = '0' then
if targ_abort = '1' then v.m.fstate := abort;
elsif targ_d_w_data = '1' then v.m.fstate := ttermwd;
elsif r.m.first = '1' then v.m.fstate := t_retry;
-- else v.m.fstate := ttermnd; end if;
else -- bug fix ***
-- if r.m.fifo.waddr = "0000000" then v.m.rmdone := '1'; end if;
if r.m.fifo.waddr = zero32(FIFO_DEPTH - 2 downto 0) then v.m.rmdone := '1'; end if;
v.m.fstate := ttermnd;
end if;
elsif mto = '1' then v.m.fstate := abort;
--elsif grant = '1' then -- pci_gnt bug fix
-- if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
-- else v.m.fstate := idle; end if;
--elsif (pr.frame and not r.m.first) = '1' then
elsif (pr.frame and not pr.trdy and not r.m.first) = '1' then -- not done if target not ready *** bug fix
if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
--else v.m.fstate := done; pstart_ack := pstart; end if;
else
if r.m.lto = '1' then -- latency timer bug fix
v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite;
v.m.fstate := idle;
else
v.m.fstate := done; pstart_ack := pstart;
end if;
end if;
elsif (pr.devsel and not r.m.first) = '1' then
if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
else v.m.fstate := idle; end if;
end if;
when last1 =>
if (pr.trdy and not pr.stop) = '1' then
if targ_abort = '1' then v.m.fstate := abort;
elsif targ_d_w_data = '1' then v.m.fstate := ttermwd;
else v.m.fstate := ttermnd; v.m.valid := '1'; end if;
--elsif (pr.frame and not r.m.first and not r.m.split) = '1' then v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart;
-- not done if target not ready *** bug fix
elsif (pr.frame and not pr.trdy and not r.m.first and not r.m.split) = '1' then v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart;
elsif data_transfer = '1' then
if r.m.valid = '1' then v.m.fstate := sync; pstart_ack := pstart;
else v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart; end if;
else d_ready := '1';
end if;
when sync =>
if pstart = not pstart_ack then
v.m.split := '0';
if ((r.m.split or (pr.trdy and not pr.stop and not r.m.split)) = '1' or r.m.state /= m_data) then v.m.fstate := idle; d_ready := '1';
else
--if (wsdone = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (r2.trans(4) = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if; -- not synced wsdone
v.m.fstate := incr; data_transfer := '1'; v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite; d_ready := '1';
end if;
else m_read_side := '1';
end if;
when t_retry =>
v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite; v.m.fstate := idle;
when ttermwd =>
if data_transfer = '1' then v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
elsif pr.trdy = '1' then v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite;
if (r.m.hwrite and r.m.valid) = '1' then v.m.fstate := idle;
else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
end if;
when ttermnd =>
if r.m.hwrite = '1' then
v.m.fifo.raddr := r.m.fifo.raddr - '1';
-- if (r.m.fifo.raddr /= (r2.s.fifo.waddr + '1') or wsdone = '0') then v.m.valid := '1'; v.m.fstate := idle; -- bug fix ***
if (r.m.fifo.raddr /= (r2.s.fifo.waddr + '1') or wsdone = '0' or r.m.valid = '1') then v.m.valid := '1'; v.m.fstate := idle;
else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
-- else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
else v.m.fstate := done; rmdone := (not r.m.fifo.side or r.m.rmdone); v.m.fifo.side := '1'; pstart_ack := pstart; end if; -- bug fix ***
when abort =>
v.m.fifo.raddr := (others => '0'); v.m.fifo.waddr := (others => '0');
v.m.fstate := done; pstart_ack := pstart; pabort := '1';
when done =>
d_ready := '1'; comp := '1'; v.m.request := '0';
if (pstart or pstart_ack) = '0' then
v.m.fstate := wdone; v.m.fifo.raddr := (others => '0'); v.m.fifo.side := '0'; rmdone := '1';
else pstart_ack := pstart; end if;
when wdone =>
d_ready := '1'; comp := '1';
if (r.m.state = idle or r.m.state = dr_bus) then v.m.fstate := idle; pabort := '0'; end if;
end case;
-- PCI master state machine
case r.m.state is
when idle => -- Master idle
v.m.stopframe := '0';
if (pcii.gnt = '0' and bus_idle = '1') then
if m_request = '1' then v.m.state := addr;
else v.m.state := dr_bus; end if;
end if;
when addr => -- Always one address cycle at the beginning of an transaction
v.m.stopframe := '0';
v.m.state := m_data;
when m_data => -- Master transfers data
if r.pci.frame = '1' then v.m.stopframe := '1'; end if; -- ***
if (r.pci.frame = '0') or ((r.pci.frame and pcii.trdy and pcii.stop and not mto) = '1') then
v.m.state := m_data;
if (r.pci.frame and not d_ready) = '1' then d_ready := '1'; end if;
elsif ((r.pci.frame and (mto or not pcii.stop)) = '1') then
v.m.state := s_tar;
v.m.stop_req := '1';
else v.m.state := turn_ar; end if;
when turn_ar => -- Transaction complete
if pcii.gnt = '0' then
if m_request = '1' then v.m.state := addr;
else v.m.state := dr_bus; end if;
else v.m.state := idle; end if;
when s_tar => -- Stop was asserted
if pcii.gnt = '0' then v.m.state := dr_bus;
else v.m.state := idle; end if;
when dr_bus => -- Drive bus when parked on this agent
if pcii.gnt = '1' then v.m.state := idle;
elsif m_request = '1' then v.m.state := addr; end if;
end case;
-- FIFO write strobe
m_fifo_write := not r.m.hwrite and not pr.irdy and not (pr.trdy and (pr.stop or not r.trans(3))) and not r.pci.oe_irdy;
-- PCI data mux
if v.m.state = addr then
if r.m.hwrite = '1' then mad := (r2.s.maddr + ((((not r2.s.fifo.side) & r.m.fifo.raddr)) & "00"));
else mad := r2.s.maddr; end if;
elsif (r.m.state = addr or data_transfer = '1') then mad := fifo3o.rdata(31 downto 0);
end if;
-- Target abort
if ((pr.devsel and pr.trdy and not pr.gnt and not pr.stop) = '1') then v.stat.rta := '1'; end if;
-- Master abort
if mto = '1' then v.stat.rma := '1'; end if;
-- Drive FRAME# and IRDY#
if (v.m.state = addr or v.m.state = m_data) then v.pci.oe_frame := '0'; end if;
-- Drive CBE#
if (v.m.state = addr or v.m.state = m_data or v.m.state = dr_bus) then v.pci.oe_cbe := '0'; end if;
-- Drive IRDY# (FRAME# delayed one pciclk)
v.pci.oe_irdy := r.pci.oe_frame;
-- FRAME# assert
if (v.m.state = addr or (v.m.state = m_data and mto = '0' and v.m.stopframe = '0' -- stopframe fix frame when pci_gnt is deasserted
--and ((((pcii.stop or not d_ready) and not (comp or v.m.split or not v.m.valid)) and not grant)) = '1')) -- dont change frame when gnt = 1 if not irdy and trdy or stop
and ((((pcii.stop or not d_ready) and not (comp or v.m.split or not v.m.valid)) and not (grant and not pr.irdy and (not pcii.trdy or not pcii.stop) ) )) = '1'))
then
v.pci.frame := '0';
end if;
-- IRDY# assert
if (v.m.state = m_data and ((d_ready or mto or (not r.m.valid) or (v.pci.frame and not r.pci.frame)) = '1')) then v.pci.irdy := '0'; end if;
-- REQ# assert
if ((v.m.request = '1' and (r.m.fstate = idle or comp = '0')) and (v.m.stop_req or r.m.stop_req) = '0') then v.pci.req := '0'; end if;
-- C/BE# assert
if v.m.state = addr then v.pci.cbe := r2.s.pcicomm; else v.pci.cbe := r2.s.be; end if;
end if;
---------------------
---PCI MASTER END ---
---------------------
----------------------
--- SHARED SIGNALS ---
----------------------
-- Default assertions
v.pci.oe_par := r.pci.oe_ad; --Delayed one clock
v.pci.oe_perr := not(r.comm.per and not r.pci.oe_par and not (pr.irdy and pr.trdy)) and (r.pci.oe_perr or r.pci.perr);
v.pci.par := xorv(r.pci.ad & r.pci.cbe); -- Default asserted by master
v.pci.ad := mad; -- Default asserted by master
v.pci.perr := not (pcii.par xor xorv(pr.ad & pr.cbe)) or pr.irdy or pr.trdy; -- Detect parity error
-- Drive AD
-- Master
if (v.m.state = addr or (v.m.state = m_data and r.m.hwrite = '1') or v.m.state = dr_bus) then
v.pci.oe_ad := '0';
end if;
-- Target
if r.t.read = '1' then
if v.t.state = s_data then
v.pci.oe_ad := '0';
v.pci.ad := tad; end if;
if r.t.state = s_data then
v.pci.par := xorv(r.pci.ad & pcii.cbe);
end if;
end if;
v.noe_ad := not v.pci.oe_ad; v.noe_ctrl := not v.pci.oe_ctrl;
v.noe_par := not v.pci.oe_par; v.noe_req := not v.pci.oe_req;
v.noe_frame := not v.pci.oe_frame; v.noe_cbe := not v.pci.oe_cbe;
v.noe_irdy := not v.pci.oe_irdy; v.noe_perr := not v.pci.oe_perr;
if (scanen = 1) and (syncrst = 1) and (ahbmi.testen = '1') then
voe_ad := (others => ahbmi.testoen); oe_ad := '1'; oe_ctrl := '1';
oe_par := '1'; oe_req := '1'; oe_frame := '1'; oe_cbe := '1';
oe_irdy := '1'; oe_perr := '1';
elsif oepol = 0 then
if (syncrst = 1) and (pcii.rst = '0') then
voe_ad := (others => '1'); oe_ad := '1'; oe_ctrl := '1';
oe_par := '1'; oe_req := '1'; oe_frame := '1'; oe_cbe := '1';
oe_irdy := '1'; oe_perr := '1';
else
voe_ad := (others => v.pci.oe_ad);
oe_ad := r.pci.oe_ad; oe_ctrl := r.pci.oe_ctrl;
oe_par := r.pci.oe_par; oe_req := r.pci.oe_req;
oe_frame := r.pci.oe_frame; oe_cbe := r.pci.oe_cbe;
oe_irdy := r.pci.oe_irdy; oe_perr := r.pci.oe_perr;
end if;
else
if (syncrst = 1) and (pcii.rst = '0') then
voe_ad := (others => '0'); oe_ad := '0'; oe_ctrl := '0';
oe_par := '0'; oe_req := '0'; oe_frame := '0'; oe_cbe := '0';
oe_irdy := '0'; oe_perr := '0';
else
voe_ad := (others => v.noe_ad);
oe_ad := r.noe_ad; oe_ctrl := r.noe_ctrl;
oe_par := r.noe_par; oe_req := r.noe_req;
oe_frame := r.noe_frame; oe_cbe := r.noe_cbe;
oe_irdy := r.noe_irdy; oe_perr := r.noe_perr;
end if;
end if;
--------------------------
--- SHARED SIGNALS END ---
--------------------------
v.trans(0) := hstart;
v.trans(1) := pabort;
v.trans(2) := pstart_ack;
v.trans(3) := pcidc;
v.trans(4) := rtdone;
v.trans(5) := rmdone;
if prrst = '0' then
v.t.state := idle; v.m.state := idle; v.m.fstate := idle;
v.bar0 := (others => '0'); v.bar0_conf := '0';
v.bar1 := (others => '0'); v.bar1_conf := '0';
v.t.msel := '0'; v.t.csel := '0';
v.t.pending := '0'; v.t.lwrite := '0';
v.bt_enable := '1'; -- twisting enabled by default, changed through page0
v.page(31 downto 30) := "01";
v.page(29 downto MADDR_WIDTH-1) := zero32(29 downto MADDR_WIDTH-1);
v.pci.par := '0';
v.comm.msen := not pr.host; v.comm.men := '0';
v.comm.mwie := '0'; v.comm.per := '0';
v.stat.rta := '0'; v.stat.rma := '0';
v.stat.sta := '0'; v.stat.dped := '0';
v.stat.dpe := '0';
v.cline := (others => '0');
v.ltim := (others => '0');
v.intline := (others => '0');
v.trans := (others => '0');
v.t.fifo.waddr := (others => '0');
v.t.fifo.raddr := (others => '0');
v.m.fifo.waddr := (others => '0');
v.m.fifo.raddr := (others => '0');
v.t.fifo.side := '0';
v.m.fifo.side := '0';
v.m.request := '0';
v.m.hwrite := '0';
v.m.valid := '1';
v.m.split := '0';
v.m.last := '0'; v.t.last := '0';
end if;
cbe_fifoi.wen <= t_fifo_write;
cbe_fifoi.waddr <= r.t.fifo.side & r.t.fifo.waddr;
cbe_fifoi.wdata(3 downto 0) <= pr.cbe;
fifo2i.wen <= t_fifo_write;
fifo2i.waddr <= r.t.fifo.side & r.t.fifo.waddr;
fifo2i.wdata <= byte_twist(pr.ad, r.bt_enable);
fifo1i.ren <= '1';
fifo1i.raddr <= t_read_side & (r.t.fifo.raddr + readt_dly);
fifo4i.wen <= m_fifo_write;
fifo4i.waddr <= r.m.fifo.side & r.m.fifo.waddr;
fifo4i.wdata <= pr.ad;
fifo3i.ren <= '1';
fifo3i.raddr <= m_read_side & (r.m.fifo.raddr + data_transfer);
rin <= v;
rioe_ad <= voe_ad;
pcio.cbeen <= (others => oe_cbe);
pcio.cbe <= r.pci.cbe;
pcio.vaden <= roe_ad;
pcio.aden <= oe_ad;
pcio.ad <= r.pci.ad;
-- pcio.trdy <= r.pci.trdy;
pcio.trdy <= r.t.trdy_del; -- (send last word in fifo) bug fix ***
pcio.ctrlen <= oe_ctrl;
pcio.trdyen <= oe_ctrl;
pcio.devselen <= oe_ctrl;
pcio.stopen <= oe_ctrl;
pcio.stop <= r.pci.stop;
pcio.devsel <= r.pci.devsel;
pcio.par <= r.pci.par;
pcio.paren <= oe_par;
pcio.perren <= oe_perr;
pcio.perr <= r.pci.perr;
pcio.reqen <= oe_req;
pcio.req <= r.pci.req;
pcio.frameen <= oe_frame;
pcio.frame <= r.pci.frame;
pcio.irdyen <= oe_irdy;
pcio.irdy <= r.pci.irdy;
end process;
pcirst <= ahbmi.testrst when (scanen = 1) and (ahbmi.testen = '1')
else pcii.rst;
pr_regs : process (pciclk)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
prrst <= to_x01(pcii.rst);
pr.gnt <= to_x01(pcii.gnt);
pr.host <= to_x01(pcii.host);
end if;
end process;
regs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
r <= rin;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
r.pci.oe_ad <= '1'; r.pci.oe_ctrl <= '1'; r.pci.oe_par <= '1';
r.pci.oe_req <= '1'; r.pci.oe_frame <= '1'; r.pci.oe_cbe <= '1';
r.pci.oe_irdy <= '1'; r.pci.oe_perr <= '1';
r.noe_ad <= '0'; r.noe_ctrl <= '0'; r.noe_par <= '0';
r.noe_req <= '0'; r.noe_frame <= '0'; r.noe_cbe <= '0';
r.noe_irdy <= '0'; r.noe_perr <= '0';
end if;
end process;
oeregs_pol0 : if oepol = 0 generate
oeregs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
roe_ad <= rioe_ad;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
roe_ad <= (others => '1');
end if;
end process;
end generate;
oeregs_pol1 : if oepol = 1 generate
oeregs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
roe_ad <= rioe_ad;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
roe_ad <= (others => '0');
end if;
end process;
end generate;
cpur : process (clk)
begin
if rising_edge (clk) then
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.serren <= '1';
pcio.inten <= '1';
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.serren <= '0';
pcio.inten <= '0';
pcio.locken <= '0';
end generate;
pcio.serr <= '1';
pcio.int <= '1';
pcio.lock <= '1';
pcio.power_state <= (others => '0');
pcio.pme_enable <= '0';
pcio.pme_clear <= '0';
msttgt : if MASTER = 1 generate
ahbmst0 : pciahbmst generic map (hindex => hmstndx, devid => GAISLER_PCIFBRG, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo1i.ren, fifo1i.raddr, fifo1o.rdata, clk, fifo1i.wen, fifo1i.waddr, fifo1i.wdata);
fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo2i.ren, fifo2i.raddr, fifo2o.rdata, pciclk, fifo2i.wen, fifo2i.waddr, fifo2i.wdata);
fifo3 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo3i.ren, fifo3i.raddr, fifo3o.rdata, clk, fifo3i.wen, fifo3i.waddr, fifo3i.wdata);
fifo4 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo4i.ren, fifo4i.raddr, fifo4o.rdata, pciclk, fifo4i.wen, fifo4i.waddr, fifo4i.wdata);
cbe_fifo : syncram_2p generic map (tech => 0, abits => FIFO_DEPTH, dbits => 4, sepclk => 1)
port map (clk, cbe_fifoi.ren, cbe_fifoi.raddr, cbe_fifoo.rdata(3 downto 0), pciclk, cbe_fifoi.wen, cbe_fifoi.waddr, cbe_fifoi.wdata(3 downto 0));
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mtf" & tost(hslvndx) &
": 32-bit PCI/AHB bridge rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR, " &
tost(2**FIFO_DEPTH) & "-word FIFOs" );
-- pragma translate_on
end generate;
tgtonly : if MASTER = 0 generate
ahbmst0 : pciahbmst generic map (hindex => hmstndx, devid => GAISLER_PCIFBRG, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo1i.ren, fifo1i.raddr, fifo1o.rdata, clk, fifo1i.wen, fifo1i.waddr, fifo1i.wdata);
fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo2i.ren, fifo2i.raddr, fifo2o.rdata, pciclk, fifo2i.wen, fifo2i.waddr, fifo2i.wdata);
cbe_fifo : syncram_2p generic map (tech => 0, abits => FIFO_DEPTH, dbits => 4, sepclk => 1)
port map (clk, cbe_fifoi.ren, cbe_fifoi.raddr, cbe_fifoo.rdata(3 downto 0), pciclk, cbe_fifoi.wen, cbe_fifoi.waddr, cbe_fifoi.wdata(3 downto 0));
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mtf" & tost(hmstndx) &
": 32-bit PCI/AHB bridge rev, target-only, " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR, " &
tost(2**FIFO_DEPTH) & "-word FIFOs" );
-- pragma translate_on
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_mtf
-- File: pci_mtf.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use gaisler.pcilib.all;
use gaisler.misc.all;
entity pci_mtf is
generic (
memtech : integer := DEFMEMTECH;
hmstndx : integer := 0;
dmamst : integer := NAHBMST;
readpref : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
irq : integer := 0;
irqmask : integer := 0;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0; -- 0 little, 1 big
class_code: integer := 16#0B4000#;
rev : integer := 0;
scanen : integer := 0;
syncrst : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of pci_mtf is
function byte_twist(di : in std_logic_vector(31 downto 0); enable : in std_logic) return std_logic_vector is
variable do : std_logic_vector(31 downto 0);
begin
if enable = '1' then
for i in 0 to 3 loop
do(31-i*8 downto 24-i*8) := di(31-(3-i)*8 downto 24-(3-i)*8);
end loop;
else
do := di;
end if;
return do;
end function;
function nr_of_1(di : in integer) return integer is
variable vec : unsigned(31 downto 0);
variable ones : integer;
begin
ones := 0;
vec := to_unsigned(di,32);
for i in 0 to 31 loop
if vec(i) = '1' then
ones := ones + 1;
end if;
end loop;
return ones;
end function;
constant REVISION : amba_version_type := rev;
constant CSYNC : integer := nsync-1;
constant HADDR_WIDTH : integer := 28;
constant MADDR_WIDTH : integer := abits;
constant DMAMADDR_WIDTH : integer := dmaabits;
constant FIFO_DEPTH : integer := fifodepth;
constant FIFO_FULL : std_logic_vector(FIFO_DEPTH - 2 downto 0) := (others => '1');
constant FIFO_DATA_BITS : integer := 32; -- One valid bit
constant NO_CPU_REGS : integer := 6;
constant NO_PCI_REGS : integer := 6;
constant HMASK_WIDTH : integer := nr_of_1(hmask);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCIFBRG, 0, REVISION, irq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCIFBRG, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, 16#E00#),
others => zero32);
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
gnt : std_logic;
host : std_logic;
end record;
type pci_fifo_in_type is record
ren : std_logic;
raddr : std_logic_vector(FIFO_DEPTH - 1 downto 0);
wen : std_logic;
waddr : std_logic_vector(FIFO_DEPTH - 1 downto 0);
wdata : std_logic_vector(FIFO_DATA_BITS - 1 downto 0);
end record;
type pci_fifo_out_type is record
rdata : std_logic_vector(FIFO_DATA_BITS - 1 downto 0);
end record;
type fifo_type is record
side : std_logic; -- Owner access side. Receiver accesses the other side
raddr : std_logic_vector(FIFO_DEPTH - 2 downto 0);
waddr : std_logic_vector(FIFO_DEPTH - 2 downto 0);
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_master_state_type is (idle, addr, m_data, turn_ar, s_tar, dr_bus);
type pci_master_fifo_state_type is (idle, addr, incr, last1, sync, t_retry, ttermwd, ttermnd, abort, done, wdone);
type pci_target_type is record
state : pci_target_state_type;
cnt : std_logic_vector(2 downto 0);
csel : std_logic; -- Configuration chip select
msel : std_logic; -- Memory hit
barsel : std_logic; -- Memory hit
psel : std_logic; -- Page hit
addr : std_logic_vector(31 downto 0);
laddr : std_logic_vector(31 downto 0);
lsize : std_logic_vector(1 downto 0);
lcbe : std_logic_vector(3 downto 0);
lwrite : std_logic;
lburst : std_logic;
lmult : std_logic;
mult : std_logic;
read : std_logic; -- PCI target read
burst : std_logic;
pending : std_logic;
wdel : std_logic;
last : std_logic;
fifo : fifo_type;
trdy_del : std_logic; -- (delay trdy to send last word in fifo) bug fix ***
end record;
type pci_master_type is record
state : pci_master_state_type;
fstate : pci_master_fifo_state_type;
cnt : std_logic_vector(2 downto 0);
ltim : std_logic_vector(7 downto 0); -- Latency timer
request : std_logic;
hwrite : std_logic;
stop_req : std_logic;
last : std_logic;
valid : std_logic;
split : std_logic;
first : std_logic;
firstw : std_logic;
fifo : fifo_type;
rmdone : std_logic; -- bug fix ***
stopframe: std_logic;
lto : std_logic; -- bug fix latency timer timeout
end record;
type pci_sync_regs is array (0 to NO_PCI_REGS - 1) of std_logic_vector(csync downto 0);
type pci_reg_type is record
pci : pci_sigs_type;
noe_par : std_logic;
noe_ad : std_logic;
noe_ctrl : std_logic;
noe_cbe : std_logic;
noe_frame : std_logic;
noe_irdy : std_logic;
noe_req : std_logic;
noe_perr : std_logic;
m : pci_master_type;
t : pci_target_type;
comm : pci_config_command_type; -- Command register
stat : pci_config_status_type; -- Status register
bar0 : std_logic_vector(31 downto MADDR_WIDTH); -- Base Address register 0
bar1 : std_logic_vector(31 downto DMAMADDR_WIDTH); -- Base Address register 1
bar0_conf : std_logic;
bar1_conf : std_logic;
page : std_logic_vector(31 downto MADDR_WIDTH-1); -- AHB page
bt_enable : std_logic; -- Byte twist enable, page0 bit 0
ltim : std_logic_vector(7 downto 0); -- Latency timer
cline : std_logic_vector(7 downto 0); -- Cache Line Size
intline : std_logic_vector(7 downto 0); -- Interrupt Line
syncs : pci_sync_regs;
trans : std_logic_vector(NO_CPU_REGS - 1 downto 0);
end record;
type cpu_master_state_type is (idle, cbe_prepare, write, read_w, read, stop);
type cpu_slave_state_type is (idle, w_wait, t_data, r_hold, r_wait, w_done, t_done);
type cpu_master_type is record
state : cpu_master_state_type; -- AMBA master state machine
dmaddr : std_logic_vector(31 downto 0);
fifo : fifo_type;
cbe_fifo : fifo_type;
cur_cbe : std_logic_vector(3 downto 0);
cbe_prep_cnt : std_ulogic;
read_half : std_logic;
last_side_wr : std_ulogic;
end record;
type cpu_slave_type is record
state : cpu_slave_state_type; -- AMBA slave state machine
maddr : std_logic_vector(31 downto 0);
mdata : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0);
perror : std_logic;
hresp : std_logic_vector(1 downto 0);
hready : std_logic;
htrans : std_logic_vector(1 downto 0);
hmaster : std_logic_vector(3 downto 0);
pcicomm : std_logic_vector(3 downto 0);
hold : std_logic;
fifos_write : std_logic;
fifo : fifo_type;
last_side : std_logic;
end record;
type cpu_sync_regs is array (0 to NO_CPU_REGS - 1) of std_logic_vector(csync downto 0);
type cpu_reg_type is record
m : cpu_master_type;
s : cpu_slave_type;
syncs : cpu_sync_regs;
trans : std_logic_vector(NO_PCI_REGS - 1 downto 0);
pciba : std_logic_vector(HMASK_WIDTH-1 downto 0);
cfto : std_logic;
wcomm : std_logic;
rcomm : std_logic;
werr : std_logic;
clscnt : std_logic_vector(8 downto 0);
dmapage : std_logic_vector(31 downto DMAMADDR_WIDTH); -- DMA page
ioba : std_logic_vector(15 downto 0);
pciirq : std_logic_vector(1 downto 0);
bus_nr : std_logic_vector(3 downto 0);
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal fifo1i, fifo2i, fifo3i, fifo4i, cbe_fifoi : pci_fifo_in_type;
signal fifo1o, fifo2o, fifo3o, fifo4o, cbe_fifoo : pci_fifo_out_type;
signal roe_ad, rioe_ad : std_logic_vector(31 downto 0);
signal pcirst : std_logic;
signal prrst : std_logic;
attribute sync_set_reset : string;
attribute sync_set_reset of prrst : signal is "true";
attribute async_set_reset : string;
attribute async_set_reset of pcirst : signal is "true";
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
begin
-----------------------------------------------
-- Back-end state machine (AHB clock domain) --
-----------------------------------------------
comb : process (rst, r2, r, dmao, ahbsi, fifo2o, fifo4o, apbi)
variable vdmai : ahb_dma_in_type;
variable v : cpu_reg_type;
variable hready : std_logic;
variable hresp, hsize : std_logic_vector(1 downto 0);
variable p_done, wsdone, wmdone, rtdone, rmdone : std_logic;
variable pstart, habort, hstart_ack : std_logic;
variable hstart, pabort, pstart_ack, pcidc : std_logic;
variable i : integer range 0 to NO_CPU_REGS;
variable fifom_write, fifos_write : std_logic;
variable prdata : std_logic_vector(31 downto 0);
variable wmvalid, wsvalid, rmvalid, rsvalid, burst_read, hold : std_logic;
variable fifors_limit, fifows_limit,fiform_limit, fifowm_limit, fifows_stop : std_logic;
variable comp, request, s_read_side, m_read_side : std_logic;
variable ahb_access : std_logic; -- *** access control fix
variable start, single_access : std_logic;
variable next_cbe : std_logic_vector(3 downto 0);
variable byteaddr : std_logic_vector(1 downto 0);
begin
v := r2;
vdmai.start := '0';
vdmai.irq := '0'; vdmai.busy := '0'; vdmai.burst := '1';
vdmai.wdata := fifo2o.rdata(31 downto 0); vdmai.write := r.t.lwrite;
rmvalid := '1'; wmvalid := '1'; request := '0'; hold := '0';
rsvalid := '1'; wsvalid := '1'; burst_read := '0';
hready := '1'; hresp := HRESP_OKAY; hsize := "10";
fifom_write := '0'; v.s.fifos_write := '0';
comp := '0'; prdata := (others => '0'); v.s.hold := '0';
s_read_side := not r.m.fifo.side; m_read_side := not r.t.fifo.side;
ahb_access := '0'; -- *** access control fix
-- Synch registers
pstart := r2.trans(0);
habort := r2.trans(1);
hstart_ack := r2.trans(2);
-- fifows_limit := r2.trans(3);
wsdone := r2.trans(4);
wmdone := r2.trans(5);
for i in 0 to NO_CPU_REGS - 1 loop
v.syncs(i)(csync) := r.trans(i);
if csync /= 0 then v.syncs(i)(0) := r2.syncs(i)(csync); end if;
end loop;
hstart := r2.syncs(0)(0);
pabort := r2.syncs(1)(0);
pstart_ack := r2.syncs(2)(0);
pcidc := r2.syncs(3)(0);
rtdone := r2.syncs(4)(0);
rmdone := r2.syncs(5)(0);
p_done := pstart_ack or pabort;
if r2.m.fifo.raddr = FIFO_FULL then fiform_limit := '1'; else fiform_limit := '0'; end if;
if r2.m.fifo.waddr = FIFO_FULL then fifowm_limit := '1'; else fifowm_limit := '0'; end if;
if r2.s.fifo.raddr = FIFO_FULL then fifors_limit := '1'; else fifors_limit := '0'; end if;
if r2.s.fifo.waddr = FIFO_FULL then fifows_limit := '1'; else fifows_limit := '0'; end if;
if r2.s.fifo.waddr(FIFO_DEPTH - 2 downto 1) = FIFO_FULL(FIFO_DEPTH - 2 downto 1) then fifows_stop := '1'; else fifows_stop := '0'; end if;
-----------------------------------
---- APB Control & Status regs ----
-----------------------------------
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
if apbi.pwrite = '1' then
v.pciba := apbi.pwdata(31 downto 31-HMASK_WIDTH+1);
v.bus_nr := apbi.pwdata(26 downto 23);
v.werr := r2.werr and not apbi.pwdata(14);
v.wcomm := apbi.pwdata(10) and r.comm.mwie;
v.rcomm := apbi.pwdata(9);
end if;
prdata(31 downto 31-HMASK_WIDTH+1) := r2.pciba;
prdata(26 downto 23) := r2.bus_nr;
prdata(22 downto 0) := r.ltim & r2.werr & not pr.host & r.comm.msen & r.comm.men & r2.wcomm & r2.rcomm & r2.cfto & r.cline;
when "001" =>
prdata := r.bar0(31 downto MADDR_WIDTH) & addzero(MADDR_WIDTH-1 downto 0);
when "010" =>
prdata := r.page(31 downto MADDR_WIDTH-1) & addzero(MADDR_WIDTH-2 downto 1) & r.bt_enable;
when "011" =>
prdata := r.bar1(31 downto DMAMADDR_WIDTH) & addzero(DMAMADDR_WIDTH-1 downto 0);
when "100" =>
if apbi.pwrite = '1' then
v.dmapage(31 downto DMAMADDR_WIDTH) := apbi.pwdata(31 downto DMAMADDR_WIDTH);
end if;
prdata := r2.dmapage(31 downto DMAMADDR_WIDTH) & addzero(DMAMADDR_WIDTH-1 downto 0);
when "101" =>
if apbi.pwrite = '1' then
v.ioba := apbi.pwdata(31 downto 16);
end if;
prdata := r2.ioba & addzero(15 downto 4) & hstart & hstart_ack & pstart & pstart_ack;
when "110" =>
prdata(1) := r.comm.men; prdata(2) := r.comm.msen;
prdata(4) := r.comm.mwie; prdata(6) := r.comm.per;
prdata(24) := r.stat.dped; prdata(26) := '1';
prdata(27) := r.stat.sta; prdata(28) := r.stat.rta;
prdata(29) := r.stat.rma; prdata(31) := r.stat.dpe;
when others =>
end case;
end if;
---------------------
---- AHB MASTER ----
---------------------
-- Burst control
if (r2.m.state = read or r2.m.state = read_w) then
if r.t.lmult = '1' then
comp := fifowm_limit and r2.m.fifo.side;
elsif r.t.lburst = '1' then
if r2.clscnt(8) = '1' then comp := '1';
else v.clscnt := r2.clscnt - (dmao.active and dmao.ready); end if;
else comp := '1'; end if;
else
v.clscnt := '0' & (r.cline - '1'); -- set burst counter to cache line size
end if;
if (rtdone = '1' and (r2.m.fifo.raddr + '1') = r.t.fifo.waddr) then rmvalid := '0'; end if;
-- step DMA address
if dmao.ready = '1' then
v.m.dmaddr(31 downto 2) := r2.m.dmaddr(31 downto 2) + '1';
end if;
-- Translate current CBE to hsize and address
byteaddr := "00";
if endian = 0 then -- pci is little endian
case r2.m.cur_cbe is
when "0000" => -- 32 bit access
vdmai.size := "10"; byteaddr := "00";
when "1100" => -- 16 bit
vdmai.size := "01"; byteaddr := "00";
when "0011" =>
vdmai.size := "01"; byteaddr := "10";
when "1110" => -- 8 bit
vdmai.size := "00"; byteaddr := "00";
when "1101" =>
vdmai.size := "00"; byteaddr := "01";
when "1011" =>
vdmai.size := "00"; byteaddr := "10";
when "0111" =>
vdmai.size := "00"; byteaddr := "11";
when others => vdmai.size := "10";
end case;
else -- big endian
case r2.m.cur_cbe is
when "0000" => -- 32 bit access
vdmai.size := "10"; byteaddr := "00";
when "0011" => -- 16 bit
vdmai.size := "01"; byteaddr := "00";
when "1100" =>
vdmai.size := "01"; byteaddr := "10";
when "0111" => -- 8 bit
vdmai.size := "00"; byteaddr := "00";
when "1011" =>
vdmai.size := "00"; byteaddr := "01";
when "1101" =>
vdmai.size := "00"; byteaddr := "10";
when "1110" =>
vdmai.size := "00"; byteaddr := "11";
when others => vdmai.size := "10";
end case;
end if;
vdmai.address := r2.m.dmaddr(31 downto 2) & byteaddr;
next_cbe := cbe_fifoo.rdata(3 downto 0);
-- AHB master state machine
case r2.m.state is
when idle =>
v.m.read_half := '0';
v.m.last_side_wr := '0';
v.m.cur_cbe := (others => '0');
v.m.fifo.waddr := (others => '0');
if hstart = '1' then
wmdone := '0';
fifowm_limit := '0';
-- v.m.fifo.waddr := (others => '0');
if r.t.lwrite = '1' then
v.m.dmaddr := r.t.laddr;
v.m.state := write;
v.m.cur_cbe := cbe_fifoo.rdata(3 downto 0);
-- burst access
if rtdone = '0' or conv_integer(r.t.fifo.waddr) /= 1 then
v.m.cbe_fifo.raddr := r2.m.cbe_fifo.raddr + 1;
v.m.state := cbe_prepare;
v.m.cbe_prep_cnt := '1';
end if;
-- vdmai.busy := '1';
-- if rmvalid = '1' then v.m.state := write;
-- else vdmai.start := '0'; v.m.state := stop; end if;
else
vdmai.start := '1';
v.m.state := read_w;
end if;
else v.m.dmaddr := r.t.laddr; end if;
when cbe_prepare =>
v.m.cur_cbe := next_cbe;
-- Need to wait for correct cycle to sample next
-- cbe if we have switched FIFO side.
if r2.m.cbe_prep_cnt = '1' then
v.m.state := write;
else
v.m.cbe_prep_cnt := '1';
end if;
when write =>
start := '0';
--if fiform_limit = '1' then
if fiform_limit = '1' and dmao.start = '1' then -- 1k bug fix (store last word in first
v.m.read_half := '1'; -- fifo half if addr = 0x400 ...)
end if;
-- Don't start again until PCI side is done filling second half of fifo (bug fix kc)
if r2.m.read_half = '1' then
if rtdone = '1' then
start := ((rmvalid and not fiform_limit) or (not dmao.active and not rmvalid));
end if;
else
-- vdmai.start := ((rmvalid and not fiform_limit) or (not dmao.active and not rmvalid));
-- 1k bug fix (store last word in first fifo half if addr = 0x400 ...)
start := ((rmvalid and not v.m.read_half) or (not dmao.active and not rmvalid));
end if;
-- Burst CBE handling
if rtdone = '0' or conv_integer(r.t.fifo.waddr) /= 1 then
-- Current or access is subword. Must be forced to single access
if r2.m.cur_cbe /= "0000" then
vdmai.burst := '0';
if dmao.active = '1' then
start := '0';
end if;
end if;
-- Next access is subword. Make current access last in burst
if rmvalid = '1' and next_cbe /= "0000" then
if dmao.active = '1' then
start := '0';
end if;
end if;
end if;
vdmai.start := start;
-- End of data phase for access with cur_cbe
if (dmao.active and dmao.ready) = '1' then
v.m.fifo.raddr := r2.m.fifo.raddr + (rmvalid and not fiform_limit and not dmao.mexc);
v.m.cbe_fifo.raddr := r2.m.cbe_fifo.raddr + (rmvalid and not fiform_limit and not dmao.mexc);
v.m.last_side_wr := m_read_side;
-- First half of FIFO
if v.m.read_half = '0' then
v.m.cur_cbe := next_cbe;
-- FIFO side switch
elsif r2.m.read_half = '0' then
v.m.cbe_prep_cnt := '0';
v.m.state := cbe_prepare;
elsif v.m.last_side_wr = '0' then
v.m.cbe_prep_cnt := '0';
v.m.state := cbe_prepare;
-- Second side of FIFO
else
v.m.cur_cbe := next_cbe;
end if;
if (dmao.mexc = '1' or rmvalid = '0') then
habort := dmao.mexc and not r.t.lwrite;
v.werr := r2.werr or (dmao.mexc and r.t.lwrite);
v.m.state := stop;
end if;
end if;
when read_w =>
vdmai.start := not (comp and dmao.active);
if dmao.mexc = '1' then
habort := not r.t.lwrite;
v.werr := '1';
v.m.state := stop;
elsif dmao.ready = '1' then
fifom_write := '1';
wmvalid := not (comp or dmao.mexc);
if comp = '1' then
v.m.state := stop;
v.m.fifo.waddr := r2.m.fifo.waddr + '1';
else
v.m.fifo.waddr := r2.m.fifo.waddr + (not fifowm_limit);
v.m.state := read; end if;
end if;
when read =>
vdmai.start := not (comp and dmao.active);
fifom_write := dmao.ready; wmvalid := not (comp or dmao.mexc);
-- if ((comp and dmao.ready) or dmao.retry) = '1' then
if (comp and dmao.ready) = '1' then
v.m.state := stop; v.m.fifo.waddr := r2.m.fifo.waddr + '1';
elsif (dmao.active and dmao.ready) = '1' then
v.m.fifo.waddr := r2.m.fifo.waddr + (not dmao.mexc and not fifowm_limit);
if dmao.mexc = '1' then habort := not r.t.lwrite; v.werr := r2.werr or r.t.lwrite; v.m.state := stop; end if;
end if;
when stop =>
if hstart = '0' and ((r.t.lwrite and not fiform_limit) = '1' or wmdone = '1') then
v.m.state := idle; hstart_ack := '0';
v.m.fifo.side := '0'; habort := '0';
v.m.fifo.raddr := (others => '0');
v.m.cbe_fifo.raddr := (others => '0');
else
comp := '1';
fiform_limit := r.t.lwrite;
fifowm_limit := not r.t.lwrite;
end if;
end case;
-- FIFO control
if fifowm_limit = '1' then
-- if (((r2.m.fifo.side or hstart_ack or (not hstart)) = '0' and not (dmao.active and not dmao.ready) = '1')
if (((r2.m.fifo.side or hstart_ack or (not hstart)) = '0' and (dmao.ready or comp) = '1')
or ((hstart_ack and not hstart) = '1' and v.m.state = stop)) then
if v.m.state = stop then wmdone := '1';
else v.m.fifo.waddr := (others => '0'); end if;
hstart_ack := '1';
v.m.fifo.side := not r2.m.fifo.side;
end if;
elsif fiform_limit = '1' then
-- if dmao.active = '0' then
if dmao.active = '0' and dmai.start = '0' then -- 1k bug fix ***
m_read_side := '1';
hstart_ack := '1';
-- v.m.fifo.raddr := (others => hstart);
v.m.fifo.raddr := (others => '0'); -- 1k bug fix ***
v.m.cbe_fifo.raddr := conv_std_logic_vector(1, FIFO_DEPTH-1);
end if;
end if;
-----------------------
--- AHB MASTER END ----
-----------------------
-------------------
---- AHB SLAVE ----
-------------------
-- if MASTER = 1 then
-- Access decode
if (ahbsi.hready and ahbsi.hsel(hslvndx)) = '1' then
if (ahbsi.hmbsel(0) or ahbsi.hmbsel(1)) = '1' then
hsize := ahbsi.hsize(1 downto 0); v.s.htrans := ahbsi.htrans;
--if (v.s.htrans(1) and r.comm.msen) = '1' then request := '1'; end if;
if (v.s.htrans(1) and r.comm.msen) = '1' then -- fix access control ***
ahb_access := '1';
--if (r2.s.state /= r_wait and r2.s.state /= r_hold) or r2.s.hmaster = ahbsi.hmaster then
--if (r2.s.state = idle or r2.s.state = t_done) or r2.s.hmaster = ahbsi.hmaster then
if (r2.s.state = idle) or r2.s.hmaster = ahbsi.hmaster then
request := '1';
end if;
end if;
end if;
end if;
-- Access latches
if (request = '1' and r2.s.state = idle) then
if ahbsi.hmbsel(1) = '1' then
if ahbsi.haddr(16) = '1' then -- Configuration cycles
v.s.maddr := (others => '0');
if r2.bus_nr = "0000" then -- Type 0
v.s.maddr(conv_integer(ahbsi.haddr(15 downto 11)) + 10) := '1';
v.s.maddr(10 downto 0) := ahbsi.haddr(10 downto 2) & "00";
else -- Type 1
v.s.maddr(19 downto 0) := r2.bus_nr & ahbsi.haddr(15 downto 2) & "01";
end if;
v.s.pcicomm := "101" & ahbsi.hwrite;
else -- I/O space access
v.s.maddr(31 downto 16) := r2.ioba;
v.s.maddr(15 downto 0) := ahbsi.haddr(15 downto 0);
v.s.pcicomm := "001" & ahbsi.hwrite;
end if;
else -- Memory space access
if conv_integer(ahbsi.hmaster) = dmamst then
v.s.maddr := ahbsi.haddr;
else
v.s.maddr := r2.pciba & ahbsi.haddr(31-HMASK_WIDTH downto 2) & "00";
end if;
if ahbsi.hwrite = '1' then
v.s.pcicomm := r2.wcomm & "111";
else
v.s.pcicomm := ahbsi.hburst(0) & '1' & (r2.rcomm or not ahbsi.hburst(0)) & '0';
end if;
end if;
-- Decode HSIZE and HADDR
if endian = 0 then -- pci is little endian
case hsize is
when "00" => -- Decode byte enable
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "1110";
when "01" => v.s.be := "1101";
when "10" => v.s.be := "1011";
when "11" => v.s.be := "0111";
when others => v.s.be := "1111";
end case;
when "01" =>
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "1100";
when "10" => v.s.be := "0011";
when others => v.s.be := "1111";
end case;
when "10" => v.s.be := "0000";
when others => v.s.be := "1111";
end case;
else -- pci is big endian
case hsize is
when "00" => -- Decode byte enable
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "0111";
when "01" => v.s.be := "1011";
when "10" => v.s.be := "1101";
when "11" => v.s.be := "1110";
when others => v.s.be := "1111";
end case;
when "01" =>
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "0011";
when "10" => v.s.be := "1100";
when others => v.s.be := "1111";
end case;
when "10" => v.s.be := "0000";
when others => v.s.be := "1111";
end case;
end if;
end if;
if ((rmdone and not r2.s.pcicomm(0)) = '1' and (r2.s.fifo.raddr + '1' + pcidc) = r.m.fifo.waddr) then rsvalid := '0'; end if;
-- FIFO address counters
-- if (r2.s.state = t_data or r2.s.state = w_wait) then
if (r2.s.state = t_data or r2.s.state = w_wait or -- bug fix ***
(r2.s.state = r_hold and fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1')) then -- (r_hold -> t_data) bug fix ***
v.s.fifos_write := r2.s.pcicomm(0) and r2.s.htrans(1);
v.s.fifo.waddr := r2.s.fifo.waddr + r2.s.fifos_write;
v.s.fifo.raddr := r2.s.fifo.raddr + ((ahbsi.htrans(1) and not r2.s.pcicomm(0) and not fifors_limit and rsvalid) or not ahbsi.hready);
end if;
if pstart_ack = '1' then
if pabort = '1' then
if (r2.s.pcicomm = CONF_WRITE or r2.s.pcicomm = CONF_READ) then v.cfto := '1';
else v.s.perror := '1'; end if;
else v.s.perror := '0'; v.cfto := '0'; end if;
end if;
--
-- AHB slave state machine
case r2.s.state is
when idle =>
if request = '1' and p_done = '0' then
if ahbsi.hwrite = '1' then
v.s.state := w_wait;
v.s.fifo.side := '0';
else
pstart := '1'; v.s.state := r_wait;
end if;
v.s.hmaster := ahbsi.hmaster;
end if;
when w_wait =>
if ((ahbsi.hready and not ahbsi.htrans(0)) = '1') then
v.s.state := w_done; fifows_limit := not wsvalid;
else
v.s.state := t_data;
end if;
when t_data =>
burst_read := ahbsi.htrans(1) and not fifors_limit;
if (fifows_stop and r2.s.fifos_write) = '1' then
if r2.s.fifo.side = '1' then
v.s.state := w_done;
end if;
elsif ((fifors_limit or not rsvalid) = '1' and v.s.htrans(1) = '1') then
if (r.m.fifo.side = '0') or (rsvalid = '0') then
v.s.state := t_done;
else v.s.state := r_hold; end if;
end if;
if ((ahbsi.hready and not ahbsi.htrans(0)) = '1') then
if r2.s.pcicomm(0) = '1' then
--v.s.state := w_done; wsvalid := '0';
v.s.state := w_done;
if ahbsi.htrans /= "00" then wsvalid := '0'; end if; -- fix dont set wsvalid if amba idle
else -- (if wsvalid = 0 side is changed before last write
v.s.state := t_done; -- to fifo if hrans = 00)
wsvalid := '0'; -- Bug fix, must give RETRY here! /KC
end if;
end if;
when r_hold =>
s_read_side := '1';
if fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1' then
if rmdone = '0' then -- bug fix ***
v.s.state := t_data;
burst_read := ahbsi.htrans(1) and not fifors_limit; -- bug fix ***
else
v.s.state := t_done;
end if;
elsif (ahbsi.hready = '1' and ahbsi.htrans = "00" and r2.s.hresp = HRESP_OKAY) then -- (idle -> t_done) bug fix ***
v.s.state := t_done;
else v.s.hold := '1'; end if;
when r_wait =>
s_read_side := '0';
if (pstart_ack and request) = '1' then
v.s.state := t_data; hready := '0';
end if;
if r2.s.hmaster /= ahbsi.hmaster and conv_integer(ahbsi.hmaster) = dmamst and pstart_ack = '1' then -- if pcidma cancel read
v.s.state := t_done;
end if;
when w_done =>
v.s.state := t_done; wsvalid := '0';
-- if (r2.s.htrans(1) or not fifows_limit) = '1' then
-- if (r2.s.htrans(1) and fifows_limit) = '1' then
v.s.fifo.waddr := r2.s.fifo.waddr + r2.s.fifos_write;
-- end if;
fifows_limit := '1';
when t_done =>
wsvalid := '0';
fifors_limit := not r2.s.pcicomm(0);
if (pstart or pstart_ack) = '0' then
v.s.state := idle; v.s.perror := '0';
v.s.fifo.waddr := (others => '0'); wsdone := '0'; fifows_limit := '0';
v.s.pcicomm := (0 => '1', others => '0'); -- default write
else fifows_limit := r2.s.pcicomm(0); end if;
end case;
-- Respond encoder
if v.s.state = t_data
or (v.s.state = r_hold and v.s.hold = '0') -- bug fix ***
or (v.s.state = t_done and r2.s.state = t_data) -- (end of trans) bug fix ***
or (v.s.state = w_wait and ahbsi.hwrite = '1') then
if r2.s.perror = '1' then hresp := HRESP_ERROR;
elsif wsvalid = '1' then hresp := HRESP_OKAY;
else hresp := HRESP_RETRY; end if;
v.s.perror := '0';
else hresp := HRESP_RETRY; end if;
if r.comm.msen = '0' then hresp := HRESP_ERROR; end if; -- Master disabled
--if (v.s.htrans(1) and request) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE
if (v.s.htrans(1) and ahb_access) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE -- *** access control fix
if (hresp /= HRESP_OKAY or hready = '0') then v.s.hready := '0'; else v.s.hready := '1'; end if;
-- Dont change hresp during wait states
if ahbsi.hready = '0' then hresp := r2.s.hresp; end if;
v.s.hresp := hresp;
-- FIFO controller
if fifows_limit = '1' then
if (r2.s.fifos_write or not wsvalid) = '1' and (r2.s.fifo.side = '0' or pstart_ack = '1') then
--if wsvalid = '0' then wsdone := '1';
if wsvalid = '0' or v.s.state = w_done then wsdone := '1'; -- fix set wsdone and pstart at the same time
else v.s.fifo.waddr := (others => '0'); end if;
pstart := not pstart_ack;
v.s.fifo.side := pstart;
end if;
elsif ((r2.s.state = t_done or r2.s.state = r_hold) and fifors_limit = '1') then
if pstart_ack = '1' then pstart := '0'; v.s.fifo.raddr := (others => '0');
else v.s.fifo.raddr := (others => '0'); end if;
end if;
-- Set last fifo side written so that PCI master knows when to stop
if (r2.s.fifos_write = '1') then
v.s.last_side := r2.s.fifo.side;
end if;
-- end if;
-----------------------
---- AHB SLAVE END ----
-----------------------
-- Sync registers
v.trans(0) := pstart;
v.trans(1) := habort;
v.trans(2) := hstart_ack;
v.trans(3) := fifows_limit;
v.trans(4) := wsdone;
v.trans(5) := wmdone;
-- input data for write accesses
if r2.s.pcicomm(0) = '1' then v.s.mdata := ahbsi.hwdata; end if;
-- output data for read accesses
-- if (ahbsi.htrans(1) and not r2.s.hold and not r2.s.pcicomm(0)) = '1' then v.s.mdata := fifo4o.rdata(31 downto 0); end if;
if (ahbsi.htrans(1) and not r2.s.pcicomm(0)) = '1' then v.s.mdata := fifo4o.rdata(31 downto 0); end if; -- bug fix ***
-- irq
apbo.pirq <= (others => '0');
if irq /= 0 then
if to_x01(pcii.host) = '0' then
apbo.pirq(irq) <= orv((not pcii.int) and conv_std_logic_vector(irqmask,4));
end if;
end if;
if rst = '0' then
v.s.state := idle;
v.m.state := idle;
v.s.perror := '0';
v.pciba := (others => '0');
v.trans := (others => '0');
v.m.cbe_fifo.waddr := (others => '0');
v.m.cbe_fifo.raddr := (others => '0');
v.m.fifo.waddr := (others => '0');
v.m.fifo.raddr := (others => '0');
v.s.fifo.waddr := (others => '0');
v.s.fifo.raddr := (others => '0');
v.m.fifo.side := '0';
v.s.fifo.side := '0';
v.wcomm := '0';
v.rcomm := '0';
v.werr := '0';
v.cfto := '0';
v.dmapage := (others => '0');
v.ioba := (others => '0');
v.pciirq := "11";
v.bus_nr := (others => '0');
end if;
apbo.prdata <= prdata;
ahbso.hready <= r2.s.hready;
ahbso.hresp <= r2.s.hresp;
ahbso.hrdata <= byte_twist(r2.s.mdata, r.bt_enable);
ahbso.hindex <= hslvndx;
fifo1i.wen <= fifom_write;
fifo1i.waddr <= r2.m.fifo.side & r2.m.fifo.waddr;
fifo1i.wdata <= dmao.rdata;
fifo2i.ren <= '1';
fifo2i.raddr <= m_read_side & (r2.m.fifo.raddr + dmao.ready);
fifo3i.wen <= r2.s.fifos_write;
fifo3i.waddr <= r2.s.fifo.side & r2.s.fifo.waddr;
fifo3i.wdata <= byte_twist(r2.s.mdata, r.bt_enable);
fifo4i.ren <= '1';
fifo4i.raddr <= s_read_side & (r2.s.fifo.raddr + burst_read);
cbe_fifoi.ren <= '1';
cbe_fifoi.raddr <= m_read_side & (r2.m.cbe_fifo.raddr + dmao.ready); -- read one cycle before data fifo
r2in <= v; dmai <= vdmai;
end process;
ahbso.hconfig <= hconfig when MASTER = 1 else (others => zero32);
ahbso.hcache <= '0';
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
---------------------------------
-- PCI core (PCI clock domain) --
---------------------------------
pcicomb : process(pr, pcii, r, r2, fifo1o, fifo3o, roe_ad, prrst)
variable v : pci_reg_type;
variable chit, mhit0, mhit1, phit, hit, hosthit, ready, cwrite, retry : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable comp : std_logic; -- Last transaction cycle on PCI bus
variable mto, tto, term, ben_err, lto : std_logic;
variable i : integer range 0 to NO_PCI_REGS;
variable tad, mad : std_logic_vector(31 downto 0);
variable pstart, habort, hstart_ack, wsdone, wmdone : std_logic;
variable hstart, pabort, pstart_ack, pcidc, rtdone, rmdone : std_logic;
variable fifort_limit, fifowt_limit, fiform_limit, fifowm_limit, fifowm_stop, t_valid : std_logic;
variable d_ready, tabort, backendnr : std_logic;
variable m_fifo_write, t_fifo_write, grant : std_logic;
variable write_access, memwrite, memread, read_match, m_read_side, t_read_side : std_logic;
variable readt_dly : std_logic; -- 1 turnaround cycle
variable bus_idle, data_transfer, data_transfer_r, data_phase, targ_d_w_data, targ_abort, m_request : std_logic;
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_par : std_logic;
variable oe_ad : std_logic;
variable oe_ctrl : std_logic;
variable oe_cbe : std_logic;
variable oe_frame : std_logic;
variable oe_irdy : std_logic;
variable oe_req : std_logic;
variable oe_perr : std_logic;
begin
-- Process defaults
v := r; v.pci.trdy := '1'; v.pci.stop := '1'; v.pci.frame := '1';
v.pci.oe_ad := '1'; v.pci.devsel := '1'; v.pci.oe_frame := '1';
v.pci.irdy := '1'; v.pci.req := '1'; hosthit := '0'; m_request := '0';
v.pci.oe_req := '0'; v.pci.oe_cbe := '1'; v.pci.oe_irdy := '1';
mto := '0'; tto := '0'; v.m.stop_req := '0'; lto := '0';
cdata := (others => '0'); retry := '0'; t_fifo_write := '0';
chit := '0'; phit := '0'; mhit0 := '0'; mhit1 := '0'; tabort := '0';
readt_dly := '0'; m_fifo_write := '0'; voe_ad := roe_ad;
tad := r.pci.ad; mad := r.pci.ad; grant := pcii.gnt; d_ready := '0';
m_read_side := not r2.s.fifo.side; t_read_side := not r2.m.fifo.side;
v.m.rmdone := '0';
write_access := not r.t.read and not pr.irdy and not pr.trdy;
memwrite := r.t.msel and r.t.lwrite and not r.t.read;
memread := r.t.msel and not r.t.lwrite and r.t.read;
-- Synch registers
hstart := r.trans(0);
pabort := r.trans(1);
pstart_ack := r.trans(2);
pcidc := r.trans(3);
rtdone := r.trans(4);
rmdone := r.trans(5);
for i in 0 to NO_PCI_REGS - 1 loop
v.syncs(i)(csync) := r2.trans(i);
if csync /= 0 then v.syncs(i)(0) := r.syncs(i)(csync); end if;
end loop;
pstart := r.syncs(0)(0);
habort := r.syncs(1)(0);
hstart_ack := r.syncs(2)(0);
backendnr := r.syncs(3)(0);
wsdone := r.syncs(4)(0);
wmdone := r.syncs(5)(0);
-- FIFO limit detector
if r.t.fifo.raddr = FIFO_FULL then fifort_limit := '1'; else fifort_limit := '0'; end if;
if r.t.fifo.waddr = FIFO_FULL then fifowt_limit := '1'; else fifowt_limit := '0'; end if;
if r.m.fifo.raddr = FIFO_FULL then fiform_limit := '1'; else fiform_limit := '0'; end if;
if r.m.fifo.waddr = FIFO_FULL then fifowm_limit := '1'; else fifowm_limit := '0'; end if;
if r.m.fifo.waddr(FIFO_DEPTH - 2 downto 1) = FIFO_FULL(FIFO_DEPTH - 2 downto 1) then fifowm_stop := '1'; else fifowm_stop := '0'; end if;
-- useful control variables
--if (r.t.laddr = r.page & r.t.addr(MADDR_WIDTH-2 downto 0) or r.t.laddr = r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 0))
if (r.t.laddr(31 downto 2) = r.page & r.t.addr(MADDR_WIDTH-2 downto 2) -- bug fix match if byte access
or r.t.laddr(31 downto 2) = r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 2))
and (r.t.lcbe = pr.cbe) -- bug fix match byte access
and (r.t.lburst = r.t.burst) then read_match := r.t.pending; else read_match := r.t.csel or r.t.psel; end if;
-- if (pr.cbe = "0000" and r.t.lsize = "10") or (pr.cbe = "1100" and r.t.lsize = "01") or (pr.cbe = "1110" and r.t.lsize = "00")
-- pragma translate_off
-- or (pr.cbe = "XXXX") -- For simulation purposes
-- pragma translate_on
-- then ben_err := '0'; else ben_err := '1'; end if;
ben_err := '0';
if r.stat.dpe = '0' then v.stat.dpe := not r.pci.perr; end if;
-------------------------
----- PCI TARGET --------
-------------------------
-- Data valid?
if ((wmdone and not r.t.lwrite) = '1' and (r.t.fifo.raddr + '1') = r2.m.fifo.waddr) then t_valid := '0';
else t_valid := not fifowt_limit or not r.t.fifo.side; end if;
-- Step addresses
if (r.t.state = s_data or r.t.state = turn_ar or r.t.state = backoff) then
if (pcii.irdy or r.pci.trdy) = '0' then
v.t.addr := r.t.addr + ((r.t.csel and r.t.read) & "00");
readt_dly := '1';
if r.t.msel = '1' then
v.t.wdel := (fifort_limit and r2.m.fifo.side) or r.t.lwrite;
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and not fifort_limit and t_valid);
end if;
end if;
if write_access = '1' then
v.t.fifo.waddr := r.t.fifo.waddr + (r.t.msel and not r.t.read and not ben_err);
t_fifo_write := r.t.msel;
v.t.addr := r.t.addr + ((r.t.csel and not r.t.read) & "00");
end if;
tabort := habort;
else v.t.wdel := '0'; end if;
-- Config space read access
case r.t.addr(7 downto 2) is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.comm.men; cdata(2) := r.comm.msen;
cdata(4) := r.comm.mwie; cdata(6) := r.comm.per;
cdata(24) := r.stat.dped; cdata(26) := '1';
cdata(27) := r.stat.sta; cdata(28) := r.stat.rta;
cdata(29) := r.stat.rma; cdata(31) := r.stat.dpe;
when "000010" => -- 0x08, class code & revision
cdata(31 downto 0) := conv_std_logic_vector(CLASS_CODE,24) & conv_std_logic_vector(REV,8) ;
when "000011" => -- 0x0C, latency & cacheline size
cdata(7 downto 0) := r.cline;
cdata(15 downto 8) := r.ltim;
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when "000101" => -- 0x14, BAR1
cdata(31 downto DMAMADDR_WIDTH) := r.bar1;
when "001111" => -- 0x3C, Interrupts & Latency timer settings
cdata(7 downto 0) := r.intline; -- Interrupt line
cdata(8) := '1'; -- Use interrupt pin INTA#
if fifodepth < 11 then cdata(fifodepth+13) := '1'; end if; --Define wanted burst period
when others =>
end case;
-- Config space write access
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if (r.t.csel and write_access) = '1' then
case r.t.addr(7 downto 2) is
when "000001" => -- 0x04, status & command
v.comm.men := cwdata(1);
if MASTER = 1 then v.comm.msen := cwdata(2); end if;
v.comm.mwie := cwdata(4); v.comm.per := cwdata(6);
v.stat.dped := r.stat.dped and not cwdata(24); -- Sticky bit
v.stat.sta := r.stat.sta and not cwdata(27); -- Sticky bit
v.stat.rta := r.stat.rta and not cwdata(28); -- Sticky bit
v.stat.rma := r.stat.rma and not cwdata(29); -- Sticky bit
v.stat.dpe := r.stat.dpe and not cwdata(31); -- Sticky bit
when "000011" => -- 0x0c, latency & cacheline size
if FIFO_DEPTH <= 7 then v.cline(FIFO_DEPTH - 1 downto 0) := cwdata(FIFO_DEPTH - 1 downto 0);
else v.cline := cwdata(7 downto 0); end if;
v.ltim := cwdata(15 downto 8);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
if v.bar0 = zero(31 downto MADDR_WIDTH) then v.bar0_conf := '0'; else v.bar0_conf := '1'; end if;
when "000101" => -- 0x14, BAR1
v.bar1 := cwdata(31 downto DMAMADDR_WIDTH);
if v.bar1 = zero(31 downto DMAMADDR_WIDTH) then v.bar1_conf := '0'; else v.bar1_conf := '1'; end if;
when "001111" => -- 0x3C, Interrupts & Latency timer settings
v.intline := cwdata(7 downto 0); -- Interrupt line
when others =>
end case;
end if;
-- Page bar write
if (r.t.psel and write_access) = '1' then
v.page := pr.ad(31 downto MADDR_WIDTH - 1);
v.bt_enable := pr.ad(0);
end if;
-- Command and address decode
case pr.cbe is
when CONF_READ | CONF_WRITE =>
if pr.ad(1 downto 0) = "00" then chit := '1'; end if;
if pr.host = '0' then --Active low
if pr.ad(31 downto 11) = "000000000000000000000" then hosthit := '1'; end if;
end if;
when MEM_READ | MEM_WRITE =>
if pr.ad(31 downto MADDR_WIDTH) = r.bar0 then
phit := r.bar0_conf and pr.ad(MADDR_WIDTH - 1);
mhit0 := r.bar0_conf and not pr.ad(MADDR_WIDTH - 1);
elsif pr.ad(31 downto DMAMADDR_WIDTH) = r.bar1 then
mhit1 := r.bar1_conf;
end if;
when MEM_R_MULT | MEM_R_LINE | MEM_W_INV =>
if pr.ad(31 downto MADDR_WIDTH - 1) = r.bar0 & '0' then mhit0 := r.bar0_conf;
elsif pr.ad(31 downto DMAMADDR_WIDTH) = r.bar1 then mhit1 := r.bar1_conf; end if;
when others => phit := '0'; mhit0 := '0'; chit := '0'; mhit1 := '0';
end case;
-- Hit detect
hit := r.t.csel or r.t.msel or r.t.psel;
if (hstart and r.pci.devsel) = '1' then
if (r.t.pending or r.t.lwrite) = '0' then
hstart := not hstart_ack;
v.t.fifo.raddr := (others => '0');
end if;
end if;
-- Ready to transfer data
if ((r.t.csel and not readt_dly) or r.t.psel) = '1'
or ((((memwrite and not r.pci.devsel) = '1')
or (memread = '1' and not (hstart_ack and v.t.wdel) = '1')) and ben_err = '0')
then ready := '1'; else ready := '0'; t_read_side := r.t.read and not hstart; end if;
-- Target timeout counter
--if (hit and pr.trdy and not (pr.frame and pr.irdy)) = '1' then
--if (hit and pr.trdy and not (pr.frame and pr.irdy) and v.t.wdel) = '1' then
if (hit and pr.trdy and not (pr.frame and pr.irdy) and not ready) = '1' then
if r.t.cnt /= "000" then v.t.cnt := r.t.cnt - 1;
else tto := '1'; end if;
else v.t.cnt := (0 => '0', others => '1'); end if;
-- -- Ready to transfer data
-- if ((r.t.csel and not readt_dly) or r.t.psel) = '1'
-- or ((((memwrite and not r.pci.devsel) = '1')
-- or (memread = '1' and not (hstart_ack and v.t.wdel) = '1')) and ben_err = '0')
-- then ready := '1'; else ready := '0'; t_read_side := r.t.read and not hstart; end if;
-- Terminate current transaction
if (((r.t.fifo.waddr >= (FIFO_FULL - "10") and r.t.fifo.side = '1')
or (t_valid = '0') or r.pci.stop = '0') and pcii.frame = '0')
or ((r.t.read xor r.t.lwrite) = '0' and r.pci.devsel = '0')
or (tto = '1') or (ben_err = '1')
then
term := '1';
else term := '0'; end if;
-- Retry transfer
if r.t.state = b_busy then
if not ((r.t.read and not r.t.lwrite and hstart_ack and read_match) = '1'
or (r.t.read or hstart or hstart_ack) = '0'
or ((r.t.csel or r.t.psel) and not hstart and not hstart_ack) = '1')
then
retry := '1';
end if;
end if;
-- target state machine
case r.t.state is
when idle =>
if pr.frame = '0' then v.t.state := b_busy; end if; -- !HIT ?
v.t.addr := pr.ad;
if readpref = 1 then v.t.burst := '1';
else v.t.burst := pr.cbe(3); end if;
v.t.read := not pr.cbe(0); v.t.mult := not pr.cbe(1);
v.t.csel := (pr.idsel or hosthit) and chit; v.t.psel := phit;
v.t.msel := r.comm.men and (mhit0 or mhit1); v.t.barsel := mhit1;
when turn_ar =>
if pr.frame = '1' then
v.t.state := idle;
v.t.fifo.raddr := (others => '0'); -- fix reset fifo read address
else v.t.state := b_busy; end if; -- !HIT ?
v.t.addr := pr.ad; v.t.wdel := '1';
if readpref = 1 then v.t.burst := '1';
else v.t.burst := pr.cbe(3); end if;
v.t.read := not pr.cbe(0); v.t.mult := not pr.cbe(1);
v.t.csel := (pr.idsel or hosthit) and chit; v.t.psel := phit;
v.t.msel := r.comm.men and (mhit0 or mhit1); v.t.barsel := mhit1;
when b_busy =>
if (pr.frame and pr.irdy) = '1' then
v.t.state := idle;
elsif hit = '1' then
v.t.state := s_data;
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and r.t.msel);
readt_dly := '1';
if r.t.pending = '0' then
v.t.pending := retry and not hstart_ack;
end if;
end if;
-- else v.t.state := backoff; end if;
-- We should not go to back off if the access wasn't to us
when s_data =>
if r.t.pending = '1' then v.t.pending := not ((habort or not r.pci.trdy) and read_match); end if;
if (pcii.frame = '0' and r.pci.stop ='0' and (r.pci.trdy or not pcii.irdy) = '1') then
v.t.state := backoff;
if r.t.last = '0' then v.t.last := r.t.msel and r.t.lwrite and v.t.wdel; end if;
v.t.fifo.raddr := r.t.fifo.raddr - (r.t.read and r.t.msel and not fifort_limit);
-- elsif (pcii.frame = '1' and (r.pci.trdy = '0' or r.pci.stop = '0')) then
elsif (pcii.frame = '1' and (r.t.trdy_del = '0' or r.pci.stop = '0')) then -- (send last word in fifo) bug fix ***
v.t.state := turn_ar;
if r.t.last = '0' then v.t.last := r.t.msel and r.t.lwrite and v.t.wdel; end if;
v.t.fifo.raddr := r.t.fifo.raddr - (r.t.read and r.t.msel and not fifort_limit);
end if;
when backoff =>
if pcii.frame = '1' then v.t.state := turn_ar; end if;
end case;
-- #TRDY assert
if (v.t.state = s_data and habort = '0' and ready = '1' and retry = '0') then v.pci.trdy := '0'; end if;
-- #STOP assert
if (v.t.state = backoff or (v.t.state = s_data and ((tabort or ((term or retry) and not habort)) = '1'))) then
v.pci.stop := '0'; end if;
-- #DEVSEL assert
if (((v.t.state = backoff and r.pci.devsel = '0') or v.t.state = s_data) and (read_match and tabort) = '0') then v.pci.devsel := '0'; end if;
-- Enable #TRDY, #STOP and #DEVSEL
if (v.t.state = s_data) or (v.t.state = backoff) or (v.t.state = turn_ar) then
v.pci.oe_ctrl := not hit;
else v.pci.oe_ctrl := '1'; end if;
-- Signaled target abort
if (r.pci.devsel and not (r.pci.stop or r.pci.oe_ctrl)) = '1' then v.stat.sta := '1'; end if;
if r.t.state = s_data and v.t.state = s_data and r.pci.trdy = '0'
and v.pci.trdy = '1' and v.t.wdel = '1' and pcii.frame = '0' then -- (send last word in fifo) bug fix ***
v.t.trdy_del := '0';
else
v.t.trdy_del := v.pci.trdy;
end if;
if r.t.state = s_data and r.pci.trdy = '1' and v.pci.trdy = '0' and pcii.frame = '0' then -- bug fix ***
readt_dly := '1';
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and not fifort_limit and t_valid);
end if;
-- Latched signals to AHB backend
if (r.t.state = b_busy) then
if (hstart or hstart_ack) = '0' then -- must be idle
v.t.lwrite := not r.t.read;
if r.t.msel = '1' then
v.t.lburst := r.t.burst;
v.t.lcbe := pr.cbe;
if r.t.barsel = '0' then v.t.laddr := r.page & r.t.addr(MADDR_WIDTH-2 downto 2) & "00";
else v.t.laddr := r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 2) & "00"; end if;
v.t.lmult := r.t.mult;
rtdone := '0'; v.t.fifo.waddr := (others => '0');
hstart := r.t.read and r.t.msel;
end if;
end if;
end if;
-- Read data mux
if r.t.csel = '1' then tad := cdata;
elsif r.t.psel = '1' then
tad(31 downto MADDR_WIDTH-1) := r.page;
tad(MADDR_WIDTH-2 downto 0) := zero32(MADDR_WIDTH-2 downto 1) & r.bt_enable;
-- elsif (r.t.state = b_busy or (r.pci.trdy or pcii.irdy) = '0') then tad := fifo1o.rdata(31 downto 0);
elsif (r.t.state = b_busy or (r.pci.trdy or pcii.irdy) = '0' or r.t.wdel = '1') then tad := byte_twist(fifo1o.rdata(31 downto 0), r.bt_enable); -- bug fix ***
end if;
-- FIFO controller
if ((fifowt_limit and write_access) = '1' or (r.t.last or rtdone) = '1') then
if hstart = hstart_ack then
if rtdone = '0' then hstart := not hstart_ack; v.t.fifo.side := hstart; end if;
if r.t.last = '1' then rtdone := '1'; v.t.last := '0';
else v.t.fifo.waddr := (others => '0');
if rtdone = '1' then
rtdone := '0'; hstart := '0'; v.t.fifo.side := '0';
end if;
end if;
end if;
end if;
if (fifort_limit and v.t.wdel) = '1' then
if hstart_ack = '1' then hstart := '0'; v.t.fifo.raddr := (others => '0');
else v.t.fifo.raddr := (others => '0'); end if;
end if;
----------------------
--- PCI TARGET END ---
----------------------
------------------
--- PCI MASTER ---
------------------
if MASTER = 1 then
bus_idle := pcii.frame and pcii.irdy;
data_transfer := not (pcii.trdy or r.pci.irdy);
data_transfer_r := not (pr.trdy or pr.irdy);
data_phase := not ((pcii.trdy and pcii.stop) or r.pci.irdy);
targ_d_w_data := not (pr.stop or pr.trdy);
targ_abort := pr.devsel and not pr.stop;
-- Request from AHB backend to start PCI transaction
if (pstart and not pstart_ack) = '1' then
if (r.m.fstate = idle and r.m.request = '0') then
v.m.request := '1';
rmdone := '0'; v.m.valid := '1';
v.m.fifo.waddr := (others => '0');
v.m.hwrite := r2.s.pcicomm(0);
end if;
end if;
-- Master timeout and DEVSEL timeout
if ((pr.irdy and not pr.frame) or (pr.devsel and not r.pci.oe_frame)) = '1' then
if r.m.cnt /= "000" then v.m.cnt := r.m.cnt - 1;
else mto := '1'; end if;
else v.m.cnt := (others => '1'); end if;
-- Latency counter
if r.pci.frame = '0' then
if r.m.ltim > "00000000" then v.m.ltim := r.m.ltim - '1';
else lto := '1'; end if;
else
v.m.ltim := r.ltim;
end if;
-- Last data
case r2.s.pcicomm is
when MEM_R_MULT | MEM_R_LINE =>
if (r.m.fifo.waddr >= (FIFO_FULL - "10") and r.m.fifo.side = '1') then
comp := '1';
else comp := '0'; end if;
when MEM_WRITE | MEM_W_INV => comp := not r.m.valid;
when others => comp := '1';
end case;
-- Minimun latency
--if lto = '0' then grant := '0'; end if;
if lto = '0' then grant := '0'; -- latency timer bug fix
elsif pcii.gnt = '1' then v.m.lto := '1'; end if;
-- Data parity error detected
if (r.m.fstate /= idle and r.stat.dped = '0') then v.stat.dped := r.comm.per and not pcii.perr; end if;
-- FIFO control state machine
case r.m.fstate is
when idle =>
v.m.lto := '0';
if (r.m.request and bus_idle and not pcii.gnt) = '1' and (r.m.state = idle or r.m.state = dr_bus) then
v.m.fstate := addr; v.m.fifo.waddr := (others => '0'); v.m.fifo.side := '0'; m_request := '1';
end if;
when addr =>
-- if (wsdone = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (wsdone = '1' and ((r.m.fifo.raddr + '1') = r2.s.fifo.waddr) and (m_read_side = r2.s.last_side)) then v.m.valid := '0'; end if; --bug fix kc
if fiform_limit = '1' then v.m.fstate := last1;
else v.m.fstate := incr; end if;
v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
v.m.first := '1'; v.m.firstw := '1';
when incr =>
d_ready := '1';
if r.m.valid = '0' then v.m.lto := '0'; end if; -- dont look at latency timer if done
if data_transfer = '1' then
--if fiform_limit = '1' then v.m.fstate := last1; v.m.split := not backendnr; end if;
if fiform_limit = '1' and r.m.lto = '0' then v.m.fstate := last1; v.m.split := not backendnr; end if; -- bug fix latency timer
-- if (wsdone = '1' and (r.m.fifo.raddr + pcii.stop) = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (wsdone = '1' and ((r.m.fifo.raddr + pcii.stop) = r2.s.fifo.waddr) and (m_read_side = r2.s.last_side)) then v.m.valid := '0'; end if; --bug fix kc
v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
v.m.first := '0';
end if;
if data_transfer_r = '1' then
if fifowm_stop = '1' then
if r.m.firstw = '1' then
if (fifowm_limit and pr.stop) = '1' then v.m.fifo.side := not r.m.fifo.side; v.m.firstw := '0'; pstart_ack := pstart; end if;
end if;
end if;
v.m.fifo.waddr := r.m.fifo.waddr + (not r.m.hwrite);
end if;
if pr.stop = '0' then
if targ_abort = '1' then v.m.fstate := abort;
elsif targ_d_w_data = '1' then v.m.fstate := ttermwd;
elsif r.m.first = '1' then v.m.fstate := t_retry;
-- else v.m.fstate := ttermnd; end if;
else -- bug fix ***
-- if r.m.fifo.waddr = "0000000" then v.m.rmdone := '1'; end if;
if r.m.fifo.waddr = zero32(FIFO_DEPTH - 2 downto 0) then v.m.rmdone := '1'; end if;
v.m.fstate := ttermnd;
end if;
elsif mto = '1' then v.m.fstate := abort;
--elsif grant = '1' then -- pci_gnt bug fix
-- if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
-- else v.m.fstate := idle; end if;
--elsif (pr.frame and not r.m.first) = '1' then
elsif (pr.frame and not pr.trdy and not r.m.first) = '1' then -- not done if target not ready *** bug fix
if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
--else v.m.fstate := done; pstart_ack := pstart; end if;
else
if r.m.lto = '1' then -- latency timer bug fix
v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite;
v.m.fstate := idle;
else
v.m.fstate := done; pstart_ack := pstart;
end if;
end if;
elsif (pr.devsel and not r.m.first) = '1' then
if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
else v.m.fstate := idle; end if;
end if;
when last1 =>
if (pr.trdy and not pr.stop) = '1' then
if targ_abort = '1' then v.m.fstate := abort;
elsif targ_d_w_data = '1' then v.m.fstate := ttermwd;
else v.m.fstate := ttermnd; v.m.valid := '1'; end if;
--elsif (pr.frame and not r.m.first and not r.m.split) = '1' then v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart;
-- not done if target not ready *** bug fix
elsif (pr.frame and not pr.trdy and not r.m.first and not r.m.split) = '1' then v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart;
elsif data_transfer = '1' then
if r.m.valid = '1' then v.m.fstate := sync; pstart_ack := pstart;
else v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart; end if;
else d_ready := '1';
end if;
when sync =>
if pstart = not pstart_ack then
v.m.split := '0';
if ((r.m.split or (pr.trdy and not pr.stop and not r.m.split)) = '1' or r.m.state /= m_data) then v.m.fstate := idle; d_ready := '1';
else
--if (wsdone = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (r2.trans(4) = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if; -- not synced wsdone
v.m.fstate := incr; data_transfer := '1'; v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite; d_ready := '1';
end if;
else m_read_side := '1';
end if;
when t_retry =>
v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite; v.m.fstate := idle;
when ttermwd =>
if data_transfer = '1' then v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
elsif pr.trdy = '1' then v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite;
if (r.m.hwrite and r.m.valid) = '1' then v.m.fstate := idle;
else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
end if;
when ttermnd =>
if r.m.hwrite = '1' then
v.m.fifo.raddr := r.m.fifo.raddr - '1';
-- if (r.m.fifo.raddr /= (r2.s.fifo.waddr + '1') or wsdone = '0') then v.m.valid := '1'; v.m.fstate := idle; -- bug fix ***
if (r.m.fifo.raddr /= (r2.s.fifo.waddr + '1') or wsdone = '0' or r.m.valid = '1') then v.m.valid := '1'; v.m.fstate := idle;
else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
-- else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
else v.m.fstate := done; rmdone := (not r.m.fifo.side or r.m.rmdone); v.m.fifo.side := '1'; pstart_ack := pstart; end if; -- bug fix ***
when abort =>
v.m.fifo.raddr := (others => '0'); v.m.fifo.waddr := (others => '0');
v.m.fstate := done; pstart_ack := pstart; pabort := '1';
when done =>
d_ready := '1'; comp := '1'; v.m.request := '0';
if (pstart or pstart_ack) = '0' then
v.m.fstate := wdone; v.m.fifo.raddr := (others => '0'); v.m.fifo.side := '0'; rmdone := '1';
else pstart_ack := pstart; end if;
when wdone =>
d_ready := '1'; comp := '1';
if (r.m.state = idle or r.m.state = dr_bus) then v.m.fstate := idle; pabort := '0'; end if;
end case;
-- PCI master state machine
case r.m.state is
when idle => -- Master idle
v.m.stopframe := '0';
if (pcii.gnt = '0' and bus_idle = '1') then
if m_request = '1' then v.m.state := addr;
else v.m.state := dr_bus; end if;
end if;
when addr => -- Always one address cycle at the beginning of an transaction
v.m.stopframe := '0';
v.m.state := m_data;
when m_data => -- Master transfers data
if r.pci.frame = '1' then v.m.stopframe := '1'; end if; -- ***
if (r.pci.frame = '0') or ((r.pci.frame and pcii.trdy and pcii.stop and not mto) = '1') then
v.m.state := m_data;
if (r.pci.frame and not d_ready) = '1' then d_ready := '1'; end if;
elsif ((r.pci.frame and (mto or not pcii.stop)) = '1') then
v.m.state := s_tar;
v.m.stop_req := '1';
else v.m.state := turn_ar; end if;
when turn_ar => -- Transaction complete
if pcii.gnt = '0' then
if m_request = '1' then v.m.state := addr;
else v.m.state := dr_bus; end if;
else v.m.state := idle; end if;
when s_tar => -- Stop was asserted
if pcii.gnt = '0' then v.m.state := dr_bus;
else v.m.state := idle; end if;
when dr_bus => -- Drive bus when parked on this agent
if pcii.gnt = '1' then v.m.state := idle;
elsif m_request = '1' then v.m.state := addr; end if;
end case;
-- FIFO write strobe
m_fifo_write := not r.m.hwrite and not pr.irdy and not (pr.trdy and (pr.stop or not r.trans(3))) and not r.pci.oe_irdy;
-- PCI data mux
if v.m.state = addr then
if r.m.hwrite = '1' then mad := (r2.s.maddr + ((((not r2.s.fifo.side) & r.m.fifo.raddr)) & "00"));
else mad := r2.s.maddr; end if;
elsif (r.m.state = addr or data_transfer = '1') then mad := fifo3o.rdata(31 downto 0);
end if;
-- Target abort
if ((pr.devsel and pr.trdy and not pr.gnt and not pr.stop) = '1') then v.stat.rta := '1'; end if;
-- Master abort
if mto = '1' then v.stat.rma := '1'; end if;
-- Drive FRAME# and IRDY#
if (v.m.state = addr or v.m.state = m_data) then v.pci.oe_frame := '0'; end if;
-- Drive CBE#
if (v.m.state = addr or v.m.state = m_data or v.m.state = dr_bus) then v.pci.oe_cbe := '0'; end if;
-- Drive IRDY# (FRAME# delayed one pciclk)
v.pci.oe_irdy := r.pci.oe_frame;
-- FRAME# assert
if (v.m.state = addr or (v.m.state = m_data and mto = '0' and v.m.stopframe = '0' -- stopframe fix frame when pci_gnt is deasserted
--and ((((pcii.stop or not d_ready) and not (comp or v.m.split or not v.m.valid)) and not grant)) = '1')) -- dont change frame when gnt = 1 if not irdy and trdy or stop
and ((((pcii.stop or not d_ready) and not (comp or v.m.split or not v.m.valid)) and not (grant and not pr.irdy and (not pcii.trdy or not pcii.stop) ) )) = '1'))
then
v.pci.frame := '0';
end if;
-- IRDY# assert
if (v.m.state = m_data and ((d_ready or mto or (not r.m.valid) or (v.pci.frame and not r.pci.frame)) = '1')) then v.pci.irdy := '0'; end if;
-- REQ# assert
if ((v.m.request = '1' and (r.m.fstate = idle or comp = '0')) and (v.m.stop_req or r.m.stop_req) = '0') then v.pci.req := '0'; end if;
-- C/BE# assert
if v.m.state = addr then v.pci.cbe := r2.s.pcicomm; else v.pci.cbe := r2.s.be; end if;
end if;
---------------------
---PCI MASTER END ---
---------------------
----------------------
--- SHARED SIGNALS ---
----------------------
-- Default assertions
v.pci.oe_par := r.pci.oe_ad; --Delayed one clock
v.pci.oe_perr := not(r.comm.per and not r.pci.oe_par and not (pr.irdy and pr.trdy)) and (r.pci.oe_perr or r.pci.perr);
v.pci.par := xorv(r.pci.ad & r.pci.cbe); -- Default asserted by master
v.pci.ad := mad; -- Default asserted by master
v.pci.perr := not (pcii.par xor xorv(pr.ad & pr.cbe)) or pr.irdy or pr.trdy; -- Detect parity error
-- Drive AD
-- Master
if (v.m.state = addr or (v.m.state = m_data and r.m.hwrite = '1') or v.m.state = dr_bus) then
v.pci.oe_ad := '0';
end if;
-- Target
if r.t.read = '1' then
if v.t.state = s_data then
v.pci.oe_ad := '0';
v.pci.ad := tad; end if;
if r.t.state = s_data then
v.pci.par := xorv(r.pci.ad & pcii.cbe);
end if;
end if;
v.noe_ad := not v.pci.oe_ad; v.noe_ctrl := not v.pci.oe_ctrl;
v.noe_par := not v.pci.oe_par; v.noe_req := not v.pci.oe_req;
v.noe_frame := not v.pci.oe_frame; v.noe_cbe := not v.pci.oe_cbe;
v.noe_irdy := not v.pci.oe_irdy; v.noe_perr := not v.pci.oe_perr;
if (scanen = 1) and (syncrst = 1) and (ahbmi.testen = '1') then
voe_ad := (others => ahbmi.testoen); oe_ad := '1'; oe_ctrl := '1';
oe_par := '1'; oe_req := '1'; oe_frame := '1'; oe_cbe := '1';
oe_irdy := '1'; oe_perr := '1';
elsif oepol = 0 then
if (syncrst = 1) and (pcii.rst = '0') then
voe_ad := (others => '1'); oe_ad := '1'; oe_ctrl := '1';
oe_par := '1'; oe_req := '1'; oe_frame := '1'; oe_cbe := '1';
oe_irdy := '1'; oe_perr := '1';
else
voe_ad := (others => v.pci.oe_ad);
oe_ad := r.pci.oe_ad; oe_ctrl := r.pci.oe_ctrl;
oe_par := r.pci.oe_par; oe_req := r.pci.oe_req;
oe_frame := r.pci.oe_frame; oe_cbe := r.pci.oe_cbe;
oe_irdy := r.pci.oe_irdy; oe_perr := r.pci.oe_perr;
end if;
else
if (syncrst = 1) and (pcii.rst = '0') then
voe_ad := (others => '0'); oe_ad := '0'; oe_ctrl := '0';
oe_par := '0'; oe_req := '0'; oe_frame := '0'; oe_cbe := '0';
oe_irdy := '0'; oe_perr := '0';
else
voe_ad := (others => v.noe_ad);
oe_ad := r.noe_ad; oe_ctrl := r.noe_ctrl;
oe_par := r.noe_par; oe_req := r.noe_req;
oe_frame := r.noe_frame; oe_cbe := r.noe_cbe;
oe_irdy := r.noe_irdy; oe_perr := r.noe_perr;
end if;
end if;
--------------------------
--- SHARED SIGNALS END ---
--------------------------
v.trans(0) := hstart;
v.trans(1) := pabort;
v.trans(2) := pstart_ack;
v.trans(3) := pcidc;
v.trans(4) := rtdone;
v.trans(5) := rmdone;
if prrst = '0' then
v.t.state := idle; v.m.state := idle; v.m.fstate := idle;
v.bar0 := (others => '0'); v.bar0_conf := '0';
v.bar1 := (others => '0'); v.bar1_conf := '0';
v.t.msel := '0'; v.t.csel := '0';
v.t.pending := '0'; v.t.lwrite := '0';
v.bt_enable := '1'; -- twisting enabled by default, changed through page0
v.page(31 downto 30) := "01";
v.page(29 downto MADDR_WIDTH-1) := zero32(29 downto MADDR_WIDTH-1);
v.pci.par := '0';
v.comm.msen := not pr.host; v.comm.men := '0';
v.comm.mwie := '0'; v.comm.per := '0';
v.stat.rta := '0'; v.stat.rma := '0';
v.stat.sta := '0'; v.stat.dped := '0';
v.stat.dpe := '0';
v.cline := (others => '0');
v.ltim := (others => '0');
v.intline := (others => '0');
v.trans := (others => '0');
v.t.fifo.waddr := (others => '0');
v.t.fifo.raddr := (others => '0');
v.m.fifo.waddr := (others => '0');
v.m.fifo.raddr := (others => '0');
v.t.fifo.side := '0';
v.m.fifo.side := '0';
v.m.request := '0';
v.m.hwrite := '0';
v.m.valid := '1';
v.m.split := '0';
v.m.last := '0'; v.t.last := '0';
end if;
cbe_fifoi.wen <= t_fifo_write;
cbe_fifoi.waddr <= r.t.fifo.side & r.t.fifo.waddr;
cbe_fifoi.wdata(3 downto 0) <= pr.cbe;
fifo2i.wen <= t_fifo_write;
fifo2i.waddr <= r.t.fifo.side & r.t.fifo.waddr;
fifo2i.wdata <= byte_twist(pr.ad, r.bt_enable);
fifo1i.ren <= '1';
fifo1i.raddr <= t_read_side & (r.t.fifo.raddr + readt_dly);
fifo4i.wen <= m_fifo_write;
fifo4i.waddr <= r.m.fifo.side & r.m.fifo.waddr;
fifo4i.wdata <= pr.ad;
fifo3i.ren <= '1';
fifo3i.raddr <= m_read_side & (r.m.fifo.raddr + data_transfer);
rin <= v;
rioe_ad <= voe_ad;
pcio.cbeen <= (others => oe_cbe);
pcio.cbe <= r.pci.cbe;
pcio.vaden <= roe_ad;
pcio.aden <= oe_ad;
pcio.ad <= r.pci.ad;
-- pcio.trdy <= r.pci.trdy;
pcio.trdy <= r.t.trdy_del; -- (send last word in fifo) bug fix ***
pcio.ctrlen <= oe_ctrl;
pcio.trdyen <= oe_ctrl;
pcio.devselen <= oe_ctrl;
pcio.stopen <= oe_ctrl;
pcio.stop <= r.pci.stop;
pcio.devsel <= r.pci.devsel;
pcio.par <= r.pci.par;
pcio.paren <= oe_par;
pcio.perren <= oe_perr;
pcio.perr <= r.pci.perr;
pcio.reqen <= oe_req;
pcio.req <= r.pci.req;
pcio.frameen <= oe_frame;
pcio.frame <= r.pci.frame;
pcio.irdyen <= oe_irdy;
pcio.irdy <= r.pci.irdy;
end process;
pcirst <= ahbmi.testrst when (scanen = 1) and (ahbmi.testen = '1')
else pcii.rst;
pr_regs : process (pciclk)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
prrst <= to_x01(pcii.rst);
pr.gnt <= to_x01(pcii.gnt);
pr.host <= to_x01(pcii.host);
end if;
end process;
regs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
r <= rin;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
r.pci.oe_ad <= '1'; r.pci.oe_ctrl <= '1'; r.pci.oe_par <= '1';
r.pci.oe_req <= '1'; r.pci.oe_frame <= '1'; r.pci.oe_cbe <= '1';
r.pci.oe_irdy <= '1'; r.pci.oe_perr <= '1';
r.noe_ad <= '0'; r.noe_ctrl <= '0'; r.noe_par <= '0';
r.noe_req <= '0'; r.noe_frame <= '0'; r.noe_cbe <= '0';
r.noe_irdy <= '0'; r.noe_perr <= '0';
end if;
end process;
oeregs_pol0 : if oepol = 0 generate
oeregs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
roe_ad <= rioe_ad;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
roe_ad <= (others => '1');
end if;
end process;
end generate;
oeregs_pol1 : if oepol = 1 generate
oeregs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
roe_ad <= rioe_ad;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
roe_ad <= (others => '0');
end if;
end process;
end generate;
cpur : process (clk)
begin
if rising_edge (clk) then
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.serren <= '1';
pcio.inten <= '1';
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.serren <= '0';
pcio.inten <= '0';
pcio.locken <= '0';
end generate;
pcio.serr <= '1';
pcio.int <= '1';
pcio.lock <= '1';
pcio.power_state <= (others => '0');
pcio.pme_enable <= '0';
pcio.pme_clear <= '0';
msttgt : if MASTER = 1 generate
ahbmst0 : pciahbmst generic map (hindex => hmstndx, devid => GAISLER_PCIFBRG, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo1i.ren, fifo1i.raddr, fifo1o.rdata, clk, fifo1i.wen, fifo1i.waddr, fifo1i.wdata);
fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo2i.ren, fifo2i.raddr, fifo2o.rdata, pciclk, fifo2i.wen, fifo2i.waddr, fifo2i.wdata);
fifo3 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo3i.ren, fifo3i.raddr, fifo3o.rdata, clk, fifo3i.wen, fifo3i.waddr, fifo3i.wdata);
fifo4 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo4i.ren, fifo4i.raddr, fifo4o.rdata, pciclk, fifo4i.wen, fifo4i.waddr, fifo4i.wdata);
cbe_fifo : syncram_2p generic map (tech => 0, abits => FIFO_DEPTH, dbits => 4, sepclk => 1)
port map (clk, cbe_fifoi.ren, cbe_fifoi.raddr, cbe_fifoo.rdata(3 downto 0), pciclk, cbe_fifoi.wen, cbe_fifoi.waddr, cbe_fifoi.wdata(3 downto 0));
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mtf" & tost(hslvndx) &
": 32-bit PCI/AHB bridge rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR, " &
tost(2**FIFO_DEPTH) & "-word FIFOs" );
-- pragma translate_on
end generate;
tgtonly : if MASTER = 0 generate
ahbmst0 : pciahbmst generic map (hindex => hmstndx, devid => GAISLER_PCIFBRG, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo1i.ren, fifo1i.raddr, fifo1o.rdata, clk, fifo1i.wen, fifo1i.waddr, fifo1i.wdata);
fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo2i.ren, fifo2i.raddr, fifo2o.rdata, pciclk, fifo2i.wen, fifo2i.waddr, fifo2i.wdata);
cbe_fifo : syncram_2p generic map (tech => 0, abits => FIFO_DEPTH, dbits => 4, sepclk => 1)
port map (clk, cbe_fifoi.ren, cbe_fifoi.raddr, cbe_fifoo.rdata(3 downto 0), pciclk, cbe_fifoi.wen, cbe_fifoi.waddr, cbe_fifoi.wdata(3 downto 0));
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mtf" & tost(hmstndx) &
": 32-bit PCI/AHB bridge rev, target-only, " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR, " &
tost(2**FIFO_DEPTH) & "-word FIFOs" );
-- pragma translate_on
end generate;
end;
|
--FPGA application for this system.
--copyright(c) 2014 dtysky
--This program is free software; you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation; either version 2 of the License, or
--(at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License along
--with this program; if not, write to the Free Software Foundation, Inc.,
--51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
------------------------------------------------------------------------
--数据传输结束确定后进入LOCK状态，usb_end置1
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity USB_RAM_BUFFER is
port
(
clk_usb_lock,clk_ram_lock:in std_logic;
clk_usb_p,clk_usb_o_p:in std_logic;
clk_ram_p:in std_logic;
usb_clk:out std_logic;
usb_full,usb_empty:in std_logic;
sloe:out std_logic:='0';
slrd,pktend:out std_logic:='0';
slwr:out std_logic:='0';
fifoadr:out std_logic_vector(1 downto 0);
usb_data_in:in std_logic_vector(15 downto 0);
usb_data_out:out std_logic_vector(15 downto 0):=x"0000";
usb_data_en:out std_logic:='0';
pc_rqu:in std_logic;
usb_in:in std_logic;
w_rqu,r_rqu:out std_logic;
w_ready,r_ready:in std_logic;
w_end,r_end:in std_logic;
ram_dm:out std_logic_vector(3 downto 0):="0011";
w_num,r_num:out std_logic_vector(15 downto 0);
ram_bank:out std_logic_vector(2 downto 0);
ram_addr_row:out std_logic_vector(12 downto 0);
ram_addr_col:out std_logic_vector(9 downto 0);
ram_data_in:in std_logic_vector(15 downto 0);
ram_data_out:out std_logic_vector(15 downto 0);
ram_reset:out std_logic:='0';
usb_end:out std_logic:='0'
);
end entity;
architecture bufferx of usb_RAM_BUFFER is
component FIFO_TO_OTHER is
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component;
component FIFO_TO_USB is
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
end component;
component COUNTER_TIMEOUT IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
end component;
----------------fifo例化----------------
signal data_from_ram,data_to_ram:std_logic_vector(15 downto 0);
signal fifo_utr_write,fifo_utr_read:std_logic:='0';
signal fifo_utr_aclr:std_logic:='0';
signal data_from_usb:std_logic_vector(7 downto 0);
signal data_to_usb:std_logic_vector(7 downto 0);
signal clk_from_ram,clk_to_usb:std_logic:='0';
signal fifo_rtu_write,fifo_rtu_read:std_logic:='0';
signal fifo_rtu_aclr:std_logic:='0';
--------------fifo已写/可读数据-----------
signal fifo_utr_num_w:std_logic_vector(9 downto 0);
signal fifo_utr_num_r:std_logic_vector(8 downto 0);
signal fifo_utr_num_w_buffer:std_logic_vector(9 downto 0);
signal fifo_utr_num_r_buffer:std_logic_vector(8 downto 0);
signal fifo_rtu_num_w:std_logic_vector(10 downto 0);
signal fifo_rtu_num_w_buffer:std_logic_vector(10 downto 0);
signal fifo_rtu_num_r:std_logic_vector(11 downto 0);
----------------pc cmd------------------
signal command:std_logic_vector(15 downto 0);
------------------usb-------------------
signal usb_in_rqu,usb_out_rqu:std_logic:='0';
signal usb_in_rqu_last:std_logic:='0';
signal usb_in_ready,usb_out_ready:std_logic:='0';
signal usb_in_ready_last,usb_out_ready_last:std_logic:='0';
signal usb_in_allow:std_logic:='0';
signal usb_out_allow:std_logic:='0';
signal usb_check:std_logic_vector(15 downto 0);
signal usb_check_o:std_logic_vector(7 downto 0);
-------------------ram-------------------
signal w_num_s:std_logic_vector(15 downto 0):=x"0000";
signal ram_bank_s:std_logic_vector(2 downto 0):="000";
signal ram_addr_row_s:std_logic_vector(12 downto 0):="0000000000000";
signal ram_addr_col_s:std_logic_vector(9 downto 0):="0000000000";
signal r_num_s:std_logic_vector(15 downto 0):=x"0000";
signal trans_no:std_logic_vector(31 downto 0):=x"00000000";
signal r_ready_s:std_logic;
------------------timeout----------------
signal timeout_aclr:std_logic:='1';
signal timeout_clken:std_logic:='0';
signal timeout_q:std_logic_vector(11 downto 0);
signal timeout_buffer:std_logic_vector(11 downto 0);
-----------------flags-------------------
type ustates is (free,trans,collect,full,judge,ack,reset,lock);
type rstates is (free,trans,collect,judge,ack,reset,lock);
signal usb_state,usb_state_buffer:ustates:=free;
signal ram_state:rstates:=free;
begin
usb_clk<=clk_usb_o_p;
buffer_usb:FIFO_TO_OTHER
port map
(
aclr=>fifo_utr_aclr,
data=>data_from_usb,q(7 downto 0)=>data_to_ram(15 downto 8),q(15 downto 8)=>data_to_ram(7 downto 0),
wrclk=>clk_usb_p,rdclk=>clk_ram_p,
wrreq=>fifo_utr_write,rdreq=>fifo_utr_read,
wrusedw=>fifo_utr_num_w,rdusedw=>fifo_utr_num_r
);
buffer_ram:FIFO_TO_USB
port map
(
aclr=>fifo_rtu_aclr,
data=>data_from_ram,q=>data_to_usb,
wrclk=>clk_ram_p,rdclk=>clk_usb_p,
wrreq=>fifo_rtu_write,rdreq=>fifo_rtu_read,
wrusedw=>fifo_rtu_num_w,rdusedw=>fifo_rtu_num_r
);
timeout:COUNTER_TIMEOUT
port map
(
aclr=>timeout_aclr,
clk_en=>timeout_clken,
clock=>clk_ram_p,
q=>timeout_q
);
--------------USB------------
usb_control:process(clk_usb_p,clk_usb_lock)
variable con_full:integer range 0 to 7:=0;
variable con_collect:integer range 0 to 3:=0;
variable con_ack:integer range 0 to 7:=0;
begin
if clk_usb_p'event and clk_usb_p='1' and clk_usb_lock='1' then
case usb_state is
-----------IDLE------------
when free =>
fifo_rtu_aclr<='0';
pktend<='0';
if usb_full='1' then
usb_state<=full;
else
usb_state<=free;
end if;
-----------FULL------------
when full =>
case con_full is
when 0 =>
usb_data_en<='0';
fifo_utr_write<='0';
sloe<='0';
slrd<='0';
fifoadr<="00";
con_full:=con_full+1;
when 1 =>
sloe<='1';
con_full:=con_full+1;
when 2 =>
con_full:=con_full+1;
when 3 =>
slrd<='1';
fifo_utr_write<='1';
con_full:=con_full+1;
when others =>
case fifo_utr_num_w_buffer is
when "0111111100" =>
usb_check(7 downto 0)<=usb_data_in(7 downto 0);
when "0111111101" =>
usb_check(15 downto 8)<=usb_data_in(7 downto 0);
sloe<='0';
slrd<='0';
fifo_utr_write<='0';
when "1000000000" =>
usb_state<=judge;
con_full:=0;
when others =>
fifo_utr_write<=fifo_utr_write;
end case;
end case;
-------------JUDGE------------
when judge =>
case ram_state is
when collect =>
if fifo_rtu_num_w_buffer="10000000000" then
usb_state<=collect;
else
usb_state<=judge;
end if;
when trans =>
usb_state<=trans;
when judge =>
usb_state<=judge;
when others =>
usb_state<=reset;
end case;
-----------TRANS------------
when trans =>
case ram_state is
when ack =>
usb_state<=ack;
when trans =>
usb_state<=trans;
when others =>
usb_state<=reset;
end case;
-------------ACK------------
when ack =>
case con_ack is
when 0 =>
usb_data_en<='1';
fifoadr<="10";
slwr<='0';
pktend<='0';
con_ack:=con_ack+1;
when 2 =>
usb_check_o<=usb_check(7 downto 0);
slwr<='1';
con_ack:=con_ack+1;
when 3=>
usb_check_o<=usb_check(15 downto 8);
con_ack:=con_ack+1;
when 4 =>
slwr<='0';
pktend<='1';
con_ack:=con_ack+1;
when 5 =>
usb_data_en<='0';
pktend<='0';
usb_state<=free;
con_ack:=0;
when others =>
con_ack:=con_ack+1;
end case;
-----------COLLECT----------
when collect =>
if ram_state=reset or usb_full='1' then
usb_state<=reset;
else
case con_collect is
when 0 =>
usb_data_en<='1';
fifoadr<="10";
con_collect:=con_collect+1;
when 1 =>
fifo_rtu_read<='1';
con_collect:=con_collect+1;
when 2 =>
slwr<='1';
con_collect:=con_collect+1;
when others =>
if usb_in='0' and fifo_rtu_num_r(7 downto 0)=x"01" then
usb_data_en<='0';
fifo_rtu_read<='0';
elsif usb_in='0' and fifo_rtu_num_r(7 downto 0)=x"00" then
slwr<='0';
elsif usb_in='1' and fifo_rtu_num_r(11)='0' then
case fifo_rtu_num_r(10 downto 9) is
when "00" =>
usb_state<=free;
when others =>
usb_data_en<='1';
fifo_rtu_read<='1';
slwr<='1';
end case;
else
fifo_rtu_read<=fifo_rtu_read;
end if;
-- if fifo_rtu_num_r="0000000000" then
-- usb_data_en<='0';
-- fifo_rtu_read<='0';
-- slwr<='0';
-- usb_state<=free;
-- con_collect:=0;
-- else
-- fifo_rtu_read<='1';
-- end if;
end case;
end if;
-----------RESET-----------
when reset =>
con_full:=0;
con_ack:=0;
con_collect:=0;
fifo_rtu_aclr<='1';
usb_data_en<='0';
fifo_rtu_read<='0';
slwr<='0';
usb_state<=free;
-----------LOCK------------
when lock =>
fifo_rtu_aclr<='1';
-----------ERROR-----------
when others =>
usb_state<=reset;
end case;
fifo_utr_num_w_buffer<=fifo_utr_num_w;
end if;
end process;
data_from_usb<=usb_data_in(7 downto 0);
--data_from_usb(15 downto 8)<=usb_data_in(7 downto 0);
with usb_state select
usb_data_out(7 downto 0)<=usb_check_o when ack,
data_to_usb when collect,
x"00" when others;
--------------RAM------------
ram_control:process(clk_ram_p,clk_ram_lock)
variable con_judge:integer range 0 to 7:=0;
variable con_collect:integer range 0 to 3:=0;
variable con_trans:integer range 0 to 3:=0;
begin
if clk_ram_p'event and clk_ram_p='1' and clk_ram_lock='1' then
case ram_state is
-------------IDLE-------------
when free =>
fifo_utr_aclr<='0';
ram_reset<='0';
if usb_state_buffer=judge then
ram_state<=judge;
else
ram_state<=free;
end if;
-------------JUDGE------------
when judge =>
case con_judge is
when 0 =>
fifo_utr_read<='1';
con_judge:=con_judge+1;
when 1 =>
con_judge:=con_judge+1;
when 2 =>
command<=data_to_ram;
con_judge:=con_judge+1;
when 3 =>
w_num_s<=data_to_ram;
r_num_s<=data_to_ram;
con_judge:=con_judge+1;
when 4 =>
trans_no(15 downto 8)<=data_to_ram(7 downto 0);
trans_no(7 downto 0)<=data_to_ram(15 downto 8);
con_judge:=con_judge+1;
when 5 =>
fifo_utr_read<='0';
trans_no(31 downto 24)<=data_to_ram(7 downto 0);
trans_no(23 downto 16)<=data_to_ram(15 downto 8);
con_judge:=con_judge+1;
when 6 =>
con_judge:=0;
case command is
when "1000011110000110" => --UTF8-采集-8786
ram_state<=collect;
fifo_utr_aclr<='1';
when "1010000010000001" => --UTF8-传送-A081
ram_state<=trans;
when "1001010101011101" => --UTF8-锁定-955B
--ram_state<=lock;
null;
when others =>
ram_state<=reset;
end case;
when others =>
ram_state<=reset;
end case;
-----------TRANS------------
when trans =>
if timeout_buffer=2500 then
ram_reset<='1';
fifo_utr_read<='0';
w_rqu<='0';
ram_state<=reset;
else
case con_trans is
when 0 =>
case trans_no(1 downto 0) is
when "00" =>
ram_addr_col_s<="0000000000";
when "01" =>
ram_addr_col_s<="0011111011"; --251
when "10" =>
ram_addr_col_s<="0111110110"; --502
when "11" =>
ram_addr_col_s<="1011110001"; --753
when others =>
null;
end case;
ram_addr_row_s<=trans_no(14 downto 2);
ram_bank_s<=trans_no(17 downto 15);
if trans_no(18)='1' then
ram_dm<="0011";
else
ram_dm<="1100";
end if;
con_trans:=con_trans+1;
when 1 =>
timeout_clken<='1';
timeout_aclr<='0';
w_rqu<='1';
w_num<=w_num_s;
ram_bank<=ram_bank_s;
ram_addr_col<=ram_addr_col_s;
ram_addr_row<=ram_addr_row_s;
con_trans:=con_trans+1;
when others =>
if w_ready='1' then
fifo_utr_read<='1';
elsif fifo_utr_num_r_buffer<"000100000" then
timeout_clken<='0';
timeout_aclr<='1';
fifo_utr_read<='0';
w_rqu<='0';
fifo_utr_aclr<='1';
ram_state<=ack;
con_trans:=0;
else
ram_state<=trans;
end if;
end case;
end if;
-------------ACK------------
when ack =>
case usb_state_buffer is
when free =>
ram_state<=free;
when ack =>
ram_state<=ack;
when trans =>
ram_state<=ack;
when others =>
ram_state<=reset;
end case;
-----------COLLECT----------
when collect =>
if timeout_buffer=4090 then
ram_reset<='1';
fifo_rtu_write<='0';
r_rqu<='0';
ram_state<=reset;
else
case con_collect is
when 0 =>
ram_addr_col_s<="0000000000";
ram_addr_row_s<=trans_no(12 downto 0);
ram_bank_s<=trans_no(15 downto 13);
if trans_no(16)='1' then
ram_dm<="0011";
else
ram_dm<="1100";
end if;
con_trans:=con_trans+1;
con_collect:=con_collect+1;
when 1 =>
timeout_clken<='1';
timeout_aclr<='0';
r_rqu<='1';
r_num<=r_num_s;
ram_bank<=ram_bank_s;
ram_addr_col<=ram_addr_col_s;
ram_addr_row<=ram_addr_row_s;
con_collect:=con_collect+1;
when others =>
case r_ready_s is
when '1' =>
fifo_rtu_write<='1';
when others =>
--if fifo_rtu_num_w_buffer(9 downto 2)=r_num_s(7 downto 0) then
if usb_state_buffer=collect then
timeout_clken<='0';
timeout_aclr<='1';
ram_state<=free;
con_collect:=0;
else
con_collect:=con_collect;
end if;
end case;
if fifo_rtu_num_w_buffer="10000000000" then
fifo_rtu_write<='0';
r_rqu<='0';
else
r_rqu<='1';
end if;
end case;
end if;
-----------RESET------------
when reset =>
fifo_utr_aclr<='1';
ram_reset<='1';
con_judge:=0;
con_trans:=0;
con_collect:=0;
if usb_state_buffer=free then
ram_state<=free;
else
null;
end if;
------------LOCK------------
when lock =>
fifo_utr_aclr<='1';
usb_end<='1';
------------ERROR-----------
when others =>
ram_state<=reset;
end case;
fifo_utr_num_r_buffer<=fifo_utr_num_r;
fifo_rtu_num_w_buffer<=fifo_rtu_num_w;
timeout_buffer<=timeout_q;
usb_state_buffer<=usb_state;
r_ready_s<=r_ready;
end if;
end process;
ram_data_out<=data_to_ram;
data_from_ram<=ram_data_in;
end bufferx;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: GC_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity GC_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(12-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(13-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(13-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(13-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end GC_fifo_top_wrapper;
architecture xilinx of GC_fifo_top_wrapper is
SIGNAL clk_i : std_logic;
component GC_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : GC_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.6e-06,
W => Wdiff_0,
Wdiff_0init => 1.7e-06,
scope => private
)
port map(
D => net5,
G => in1,
S => net3
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.6e-06,
W => Wdiff_0,
Wdiff_0init => 1.7e-06,
scope => private
)
port map(
D => net4,
G => in2,
S => net3
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => W_0,
W_0init => 4.455e-05
)
port map(
D => net3,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => Wcursrc_1,
Wcursrc_1init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => Wcursrc_1,
Wcursrc_1init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => L_2,
L_2init => 5e-06,
W => Wsrc_2,
Wsrc_2init => 7.085e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net1,
G => net4,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => L_3,
L_3init => 5.7e-06,
W => Wsrc_2,
Wsrc_2init => 7.085e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net2,
G => net5,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 5e-07,
W => Wcm_3,
Wcm_3init => 3.05e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 5e-07,
W => Wcmout_3,
Wcmout_3init => 7.135e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net1,
S => vdd
);
subnet0_subnet5_c1 : entity cap(behave)
generic map(
C => C_4,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net1
);
subnet0_subnet6_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 5e-07,
W => Wcm_3,
Wcm_3init => 3.05e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet6_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 5e-07,
W => Wcmout_3,
Wcmout_3init => 7.135e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out2,
G => net2,
S => vdd
);
subnet0_subnet6_c1 : entity cap(behave)
generic map(
C => C_5,
symmetry_scope => sym_5
)
port map(
P => out2,
N => net2
);
subnet0_subnet7_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => Wcursrc_4,
Wcursrc_4init => 2.375e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet8_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => Wcursrc_4,
Wcursrc_4init => 2.375e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net6,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net6,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net9,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net8,
N => net6
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => W_1,
W_1init => 1.205e-05
)
port map(
D => net7,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 6.9e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 4.945e-05,
scope => private
)
port map(
D => net9,
G => vref,
S => net7
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 6.9e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 4.945e-05,
scope => private
)
port map(
D => net8,
G => net6,
S => net7
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 9.55e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 2.75e-06,
scope => private
)
port map(
D => net8,
G => net8,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 9.55e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 2.75e-06,
scope => private
)
port map(
D => net9,
G => net8,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 9e-07,
W => Wcmbias_0,
Wcmbias_0init => 6.825e-05,
scope => private
)
port map(
D => out1,
G => net9,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 9e-07,
W => Wcmbias_0,
Wcmbias_0init => 6.825e-05,
scope => private
)
port map(
D => out2,
G => net9,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => (pfak)*(WBias),
WBiasinit => 1.75e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.85e-06,
W => (pfak)*(WBias),
WBiasinit => 1.75e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.85e-06,
W => WBias,
WBiasinit => 1.75e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => WBias,
WBiasinit => 1.75e-05
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => WBias,
WBiasinit => 1.75e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => WBias,
WBiasinit => 1.75e-05
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:20:42 10/06/2016
-- Design Name:
-- Module Name: C:/Users/utp.CRIE/Desktop/sparcv8-monocicle/Test_signExtUnit.vhd
-- Project Name: monocicle-sparcv8
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: sign_ext_unit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_signExtUnit IS
END Test_signExtUnit;
ARCHITECTURE behavior OF Test_signExtUnit IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sign_ext_unit
PORT(
entrada : IN std_logic_vector(12 downto 0);
salida : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal entrada : std_logic_vector(12 downto 0) := (others => '0');
--Outputs
signal salida : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sign_ext_unit PORT MAP (
entrada => entrada,
salida => salida
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
entrada <= "1111111111111";
wait for 100 ns;
entrada <= "0011111111111";
wait for 100 ns;
entrada <= "1010101010101";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
-- $Id: s7_cmt_sfs_2_gsim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: s7_cmt_sfs_2 - sim
-- Description: Series-7 CMT for dual-channel frequency synthesis
-- simple vhdl model, without Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Series-7
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-18 1072 1.0 Initial version (derived from s7_cmt_sfs_3_gsim)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity s7_cmt_sfs_2 is -- 7-Series CMT for dual freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT0_DIVIDE : positive := 1; -- output 0 divide
OUT1_DIVIDE : positive := 1; -- output 1 divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKOUT0 : out slbit; -- clock output 0
CLKOUT1 : out slbit; -- clock output 1
LOCKED : out slbit -- pll/mmcm locked
);
end s7_cmt_sfs_2;
architecture sim of s7_cmt_sfs_2 is
signal LOCKED0 : slbit := '1';
signal LOCKED1 : slbit := '1';
begin
proc_init : process
-- currently frequency limits taken from Artix-7 speed grade -1
constant f_vcomin_pll : integer := 800;
constant f_vcomax_pll : integer := 1600;
constant f_pdmin_pll : integer := 19;
constant f_pdmax_pll : integer := 450;
constant f_vcomin_mmcm : integer := 600;
constant f_vcomax_mmcm : integer := 1200;
constant f_pdmin_mmcm : integer := 10;
constant f_pdmax_mmcm : integer := 450;
variable t_vco : Delay_length := 0 ns;
variable t_vcomin : Delay_length := 0 ns;
variable t_vcomax : Delay_length := 0 ns;
variable t_pd : Delay_length := 0 ns;
variable t_pdmin : Delay_length := 0 ns;
variable t_pdmax : Delay_length := 0 ns;
begin
-- validate generics
if not (GEN_TYPE = "PLL" or GEN_TYPE = "MMCM") then
report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
severity failure;
end if;
if VCO_DIVIDE/=1 or VCO_MULTIPLY/=1 or
OUT0_DIVIDE/=1 or OUT1_DIVIDE/=1 then
if GEN_TYPE = "PLL" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>56 or
VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
OUT0_DIVIDE<1 or OUT0_DIVIDE>128 or
OUT1_DIVIDE<1 or OUT1_DIVIDE>128
then
report
"assert(VCO_DIVIDE in 1:56 VCO_MULTIPLY in 2:64 OUTx_DIVIDE in 1:128)"
severity failure;
end if;
-- setup VCO and PD range check boundaries
t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps;
t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps;
t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps;
t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps;
end if; -- GEN_TYPE = "PLL"
if GEN_TYPE = "MMCM" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>106 or
VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
OUT0_DIVIDE<1 or OUT0_DIVIDE>128 or
OUT1_DIVIDE<1 or OUT1_DIVIDE>128
then
report
"assert(VCO_DIVIDE in 1:106 VCO_MULTIPLY in 2:64 OUTx_DIVIDE in 1:128)"
severity failure;
end if;
-- setup VCO and PD range check boundaries
t_vcomin := (1000 ns / f_vcomax_mmcm) - 1 ps;
t_vcomax := (1000 ns / f_vcomin_mmcm) + 1 ps;
t_pdmin := (1000 ns / f_pdmax_mmcm) - 1 ps;
t_pdmax := (1000 ns / f_pdmin_mmcm) + 1 ps;
end if; -- GEN_TYPE = "MMCM"
-- now common check whether VCO and PD frequency is in range
t_pd := (1 ps * (1000.0*CLKIN_PERIOD)) * VCO_DIVIDE;
t_vco := t_pd / VCO_MULTIPLY;
if t_vco<t_vcomin or t_vco>t_vcomax then
report "assert(VCO frequency out of range)"
severity failure;
end if;
if t_pd<t_pdmin or t_pd>t_pdmax then
report "assert(PD frequency out of range)"
severity failure;
end if;
end if; -- one factor /= 1
wait;
end process proc_init;
-- generate clock
SFS0: sfs_gsim_core
generic map (
VCO_DIVIDE => VCO_DIVIDE,
VCO_MULTIPLY => VCO_MULTIPLY,
OUT_DIVIDE => OUT0_DIVIDE)
port map (
CLKIN => CLKIN,
CLKFX => CLKOUT0,
LOCKED => LOCKED0
);
SFS1: sfs_gsim_core
generic map (
VCO_DIVIDE => VCO_DIVIDE,
VCO_MULTIPLY => VCO_MULTIPLY,
OUT_DIVIDE => OUT1_DIVIDE)
port map (
CLKIN => CLKIN,
CLKFX => CLKOUT1,
LOCKED => LOCKED1
);
LOCKED <= LOCKED0 and LOCKED1;
end sim;
|
-- rgb_line_buff.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library rgb_shreg_v1_00_a;
use rgb_shreg_v1_00_a.rgb_shreg;
---
-- Line buffer. Works as a shift register but provides
-- access to more then only one value. It is intended
-- for construction of sliding window mechanism.
--
-- Holds line of WIDTH pixels.
---
entity rgb_line_buff is
generic (
WIDTH : integer := 800;
FIELDS : integer := 3
);
port (
CLK : in std_logic;
CE : in std_logic;
IN_R : in std_logic_vector(7 downto 0);
IN_G : in std_logic_vector(7 downto 0);
IN_B : in std_logic_vector(7 downto 0);
IN_DE : in std_logic;
IN_HS : in std_logic;
IN_VS : in std_logic;
FIELD_R : out std_logic_vector(FIELDS * 8 - 1 downto 0);
FIELD_G : out std_logic_vector(FIELDS * 8 - 1 downto 0);
FIELD_B : out std_logic_vector(FIELDS * 8 - 1 downto 0);
FIELD_DE : out std_logic_vector(FIELDS - 1 downto 0);
FIELD_HS : out std_logic_vector(FIELDS - 1 downto 0);
FIELD_VS : out std_logic_vector(FIELDS - 1 downto 0);
OUT_R : out std_logic_vector(7 downto 0);
OUT_G : out std_logic_vector(7 downto 0);
OUT_B : out std_logic_vector(7 downto 0);
OUT_DE : out std_logic;
OUT_HS : out std_logic;
OUT_VS : out std_logic
);
end entity;
---
-- Implementation uses rgb_shreg unit to store first WIDTH - FIELDS
-- pixels. The rest is used to provide the readable fields.
---
architecture full of rgb_line_buff is
type color_t is array(0 to FIELDS) of std_logic_vector(7 downto 0);
signal fields_r : color_t;
signal fields_g : color_t;
signal fields_b : color_t;
signal fields_de : std_logic_vector(FIELDS downto 0);
signal fields_hs : std_logic_vector(FIELDS downto 0);
signal fields_vs : std_logic_vector(FIELDS downto 0);
begin
rgb_shreg_i : entity rgb_shreg_v1_00_a.rgb_shreg
generic map (
DEPTH => WIDTH - FIELDS
)
port map (
CLK => CLK,
CE => CE,
IN_R => IN_R,
IN_G => IN_G,
IN_B => IN_B,
IN_DE => IN_DE,
IN_HS => IN_HS,
IN_VS => IN_VS,
OUT_R => fields_r(0),
OUT_G => fields_g(0),
OUT_B => fields_b(0),
OUT_DE => fields_de(0),
OUT_HS => fields_hs(0),
OUT_VS => fields_vs(0)
);
----------------------------
gen_fields: for i in 1 to FIELDS
generate
field_i : entity rgb_shreg_v1_00_a.rgb_shreg
generic map (
DEPTH => 1
)
port map (
CLK => CLK,
CE => CE,
IN_R => fields_r (i - 1),
IN_G => fields_g (i - 1),
IN_B => fields_b (i - 1),
IN_DE => fields_de(i - 1),
IN_HS => fields_hs(i - 1),
IN_VS => fields_vs(i - 1),
OUT_R => fields_r (i),
OUT_G => fields_g (i),
OUT_B => fields_b (i),
OUT_DE => fields_de(i),
OUT_HS => fields_hs(i),
OUT_VS => fields_vs(i)
);
FIELD_R (i * 8 - 1 downto (i - 1) * 8) <= fields_r(i - 1);
FIELD_G (i * 8 - 1 downto (i - 1) * 8) <= fields_g(i - 1);
FIELD_B (i * 8 - 1 downto (i - 1) * 8) <= fields_b(i - 1);
FIELD_DE(i - 1) <= fields_de(i - 1);
FIELD_HS(i - 1) <= fields_hs(i - 1);
FIELD_VS(i - 1) <= fields_vs(i - 1);
end generate;
----------------------------
OUT_R <= fields_r (FIELDS);
OUT_G <= fields_g (FIELDS);
OUT_B <= fields_b (FIELDS);
OUT_DE <= fields_de(FIELDS);
OUT_HS <= fields_hs(FIELDS);
OUT_VS <= fields_vs(FIELDS);
end architecture;
|
-- ***********************************************
-- ** PROYECTO PDUA **
-- ** Modulo: BANCO **
-- ** Creacion: Julio 07 **
-- ** Revisión: Marzo 08 **
-- ** Por: MGH-CMUA-UNIANDES **
-- ***********************************************
-- Descripcion:
-- Banco de registros
-- reset_n HR (Habilitador)
-- _|___|_
-- clk -->| PC |
-- | SP |
-- | DPTR |
-- | A |--> BUSB
-- BUSC -->| VI |--> BUSA
-- | CTE1 |
-- | ACC |
-- |_______|
-- | |
-- SC SB
-- Selector de destino Selector de Origen
-- reg <--BUSC BUSB <-- reg
-- ***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity banco is
Port ( CLK : in std_logic;
RESET_n: in std_logic;
HR : in std_logic;
SC,SB : in std_logic_vector(2 downto 0);
BUSC : in std_logic_vector(7 downto 0);
BUSA,BUSB : out std_logic_vector(7 downto 0)
);
end banco;
architecture Behavioral of banco is
SIGNAL PC,SP,DPTR,A,VI,TEMP,CTE1,ACC : std_logic_vector(7 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '0') then
if RESET_n = '0' then
PC <= "00000000";
SP <= "10000000"; -- Primera posición de RAM
DPTR <= "00000000";
A <= "00000000";
VI <= "00000010"; -- Vector de Interrupcion
TEMP <= "00000000";
CTE1 <= "11111111"; -- Constante Menos 1 (Compl. a 2)
ACC <= "00000000";
elsif HR = '1' then
case SC is
when "000" => PC <= BUSC;
when "001" => SP <= BUSC;
when "010" => DPTR <= BUSC;
when "011" => A <= BUSC;
-- when "100" => B <= BUSC; -- B es constante (vector de Int)
when "101" => TEMP <= BUSC;
-- when "110" => CTE 1 -- Es constante (menos 1)
when "111" => ACC <= BUSC;
when others => CTE1 <= "11111111";
end case;
end if;
end if;
end process;
process(SB,PC,SP,DPTR,A,VI,TEMP,ACC)
begin
case SB is
when "000" => BUSB <= PC;
when "001" => BUSB <= SP;
when "010" => BUSB <= DPTR;
when "011" => BUSB <= A;
when "100" => BUSB <= VI;
when "101" => BUSB <= TEMP;
when "110" => BUSB <= CTE1;
when "111" => BUSB <= ACC;
when others=> BUSB <= ACC;
end case;
end process;
BUSA <= ACC;
end Behavioral;
|
-- This application calculates the differential electric voltage between two points, showing the output in two 7-segment displays. The hardware to use this, is a FPGA with an AD (analog to digital converter) expansion kit.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Use ieee.std_logic_arith.All;
Use ieee.std_logic_unsigned.All;
ENTITY voltimetro IS
PORT (
display1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
-- unidades en el display de 7seg
display2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
-- decenas en el display de 7seg
display_punto : OUT STD_LOGIC;
-- punto decimal en el display de 7seg
selector : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
-- selector de entrada a convertir
mode : OUT STD_LOGIC;
-- señal para el tipo de funcionamiento del conversor
cs : OUT STD_LOGIC;
-- señal de control del conversor
rd : OUT STD_LOGIC;
-- señal de control del conversor
digin : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- entrada digital
int : IN STD_LOGIC;
-- señal de control del conversor
clk : IN STD_LOGIC
-- reloj de la placa
);
END voltimetro;
ARCHITECTURE voltimetro OF voltimetro IS
SIGNAL leer : STD_LOGIC; -- señal auxiliar para controlar cs y rd
SIGNAL cont_clk: INTEGER range 0 to 25200; -- contador del reloj de la placa
SIGNAL voltaje : STD_LOGIC_VECTOR(7 DOWNTO 0); -- valor digital del voltaje
SIGNAL volt_unidades: INTEGER range 0 to 9; -- cifra unidades del voltaje
SIGNAL volt_decenas: INTEGER range 0 to 9; -- cifra decenas del voltaje
BEGIN
-- Invierte la señal leer cada milisegundo
proceso_reloj: PROCESS (clk)
BEGIN
IF clk'event AND clk='1' THEN
cont_clk<=cont_clk+1;
IF cont_clk>=25175 THEN
leer<=NOT leer;
cont_clk<= 0;
END IF;
END IF;
END PROCESS;
-- Seleccionamos el MODE_0 de operacion del conversor
mode<='0';
-- Seleccionamos la entrada analógica 0
selector<="000";
-- Al asignar el valor de leer a cs y rd, cada vez que estas dos señales se pongan
-- a cero se indica al conversor que se debe efectuar la conversion
cs<=leer;
rd<=leer;
-- Queremos mostrar el punto decimal en el display
display_punto <='1';
-- Cuando se produce un flanco de bajada en int significa que la conversion se ha
-- efectuado correctamente y el valor digital de voltaje está listo en la entrada
proceso_escribir: PROCESS (int)
BEGIN
IF int'event AND int='0' THEN
-- calculamos la conversion a voltios sobre la marcha
-- las unidades son decivoltios
volt_unidades <= (((conv_integer(digin))*50)/255)/10;
-- las decenas son voltios
volt_decenas <= (((conv_integer(digin))*50)/255) mod 10;
END IF;
END PROCESS;
-- mostramos los valores digitales obtenidos por los displays
proceso_mostrar: PROCESS(volt_unidades,volt_decenas)
BEGIN
CASE(volt_unidades) IS
WHEN 0 => display1 <= "1000000"; --0
WHEN 1 => display1 <= "1111001"; --1
WHEN 2 => display1 <= "0100100"; --2
WHEN 3 => display1 <= "0110000"; --3
WHEN 4 => display1 <= "0011001"; --4
WHEN 5 => display1 <= "0010010"; --5
WHEN 6 => display1 <= "0000010"; --6
WHEN 7 => display1 <= "1111000"; --7
WHEN 8 => display1 <= "0000000"; --8
WHEN 9 => display1 <= "0011000"; --9
WHEN OTHERS => display1 <= "0111111"; --resto
END CASE;
CASE(volt_decenas) IS
WHEN 0 => display2 <= "1000000"; --0
WHEN 1 => display2 <= "1111001"; --1
WHEN 2 => display2 <= "0100100"; --2
WHEN 3 => display2 <= "0110000"; --3
WHEN 4 => display2 <= "0011001"; --4
WHEN 5 => display2 <= "0010010"; --5
WHEN 6 => display2 <= "0000010"; --6
WHEN 7 => display2 <= "1111000"; --7
WHEN 8 => display2 <= "0000000"; --8
WHEN 9 => display2 <= "0011000"; --9
WHEN OTHERS => display2 <= "0111111"; --resto
END CASE;
END PROCESS;
END voltimetro;
|
-------------------------------------------------------------------------------
-- FILE NAME : TrailUnit.vhd
-- MODULE NAME : TrailUnit
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : bogdan.ardelean@yahoo.com
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-2 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : Unit that executes the trail(a) WAM ancillary operation
--
-------------------------------------------------------------------------------
library ieee;
library xil_defaultlib;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FpwamPkg.all;
entity TrailUnit is
generic
(
kAddressWidth : natural := kWamAddressWidth
);
port
(
trail : in std_logic;
trail_address : in std_logic_vector(kAddressWidth -1 downto 0);
H : in std_logic_vector(kAddressWidth -1 downto 0);
HB : in std_logic_vector(kAddressWidth -1 downto 0);
B : in std_logic_vector(kAddressWidth -1 downto 0);
a : out std_logic_vector(kAddressWidth -1 downto 0);
do_trail : out std_logic
);
end TrailUnit;
architecture Behavioral of TrailUnit is
begin
a <= trail_address;
DOTRAIL: process(trail, trail_address, H, HB, B)
begin
do_trail <= '0';
if trail = '1' then
if (unsigned(trail_address) < unsigned(HB))
or ((unsigned(H) < unsigned(trail_address)) and (unsigned(trail_address) < unsigned(B))) then
do_trail <= '1';
end if;
end if;
end process;
end Behavioral;
|
-- NEED RESULT: ARCH00264: Scalar types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00264
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 3.1 (1)
-- 3.1 (2)
-- 3.1 (3)
-- 3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00264)
-- ENT00264_Test_Bench(ARCH00264_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
-- 14-JUN-1988 - EL - arrays must be initialized to values within the
-- element subtype
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00264 of E00000 is
-- these test 3.1 (1)
function f ( ary : t_arr1 ) return integer is
begin
return ary'right ;
end f ;
-- these test 3.1 (2) and 3.1 (3)
type ascending_range is range 0 to 10 ;
type descending_range is range 10 downto 0 ;
-- these test 3.1 (4)
subtype ascending_subrange is descending_range range 2 to 5 ;
subtype descending_subrange is ascending_range range 5 downto 2 ;
begin
P :
process
variable ascending_array : t_arr1 (5 to 7) := (10,10,10);
variable descending_array : t_arr1 (20 downto 17) := (10,10,10,10);
begin
test_report ( "ARCH00264" ,
"Scalar types" ,
(ascending_range'left = 0) and
(descending_range'left = 10) and
(ascending_subrange'right = 5) and
(descending_subrange'right = 2) and
(f(ascending_array) = 7) and
(f(descending_array) = 17)
) ;
wait ;
end process P ;
end ARCH00264 ;
entity ENT00264_Test_Bench is
end ENT00264_Test_Bench ;
architecture ARCH00264_Test_Bench of ENT00264_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00264 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00264_Test_Bench ;
|
-------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_datapath is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : in std_logic; -- biggest round is 12
sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0);
sel0 : in std_logic_vector(2 downto 0);
selout : in std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic;
ActivateGen : in std_logic;
GenSize : in std_logic_vector(2 downto 0);
-- Data signals
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(127 downto 0)
);
end entity Ascon_StateUpdate_datapath;
architecture structural of Ascon_StateUpdate_datapath is
-- constants
constant EXTRAIV : std_logic_vector(63 downto 0) := x"80400c0600000000"; -- used in the initialization
constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001";
constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000";
-- Register signals
signal Reg0In,Reg1In,Reg2In,Reg3In,Reg4In : std_logic_vector(63 downto 0);
signal Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : std_logic_vector(63 downto 0);
signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0);
-- Internal signals on datapath
signal DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4 : std_logic_vector(63 downto 0);
signal XorReg01,XorReg02,XorReg12,XorReg13,XorReg22 : std_logic_vector(63 downto 0);
signal XorReg2,XorReg31,XorReg4 : std_logic_vector(63 downto 0);
signal OutSig0: std_logic_vector(63 downto 0);
signal OutSig1: std_logic_vector(127 downto 0);
begin
-- declare and connect all sub entities
rounds: entity work.Fullrounds port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr,DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4);
outpgen: entity work.OutputGenerator port map(Reg0Out,DataIn,GenSize,ActivateGen,XorReg01,OutSig0); -- ActivateGen is a bit that indicates decryption or not
---------------------------------------------
------ Combinatorial logic for a round ------
---------------------------------------------
datapath: process(IV,Key,DataIn,Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RegOutOut, -- inputs blocks and registers
DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4, -- internal signals
XorReg01,XorReg02,XorReg12,XorReg13,XorReg22,XorReg2,XorReg31,XorReg4,OutSig0,OutSig1, -- internal signals
RoundNr,sel0,sel1,sel2,sel3,sel4,ActivateGen,selout,GenSize) is -- control signals
begin
-- Set correct inputs in registers
if sel0 = "000" then
Reg0In <= DiffOut0;
elsif sel0 = "001" then
Reg0In <= EXTRAIV;
elsif sel0 = "010" then
Reg0In <= XorReg01;
elsif sel0 = "011" then
Reg0In <= XorReg02;
else
Reg0In <= Reg0Out xor ADCONSTANT;
end if;
if sel1 = "00" then
Reg1In <= DiffOut1;
elsif sel1 = "01" then
Reg1In <= Key(127 downto 64);
elsif sel1 = "10" then
Reg1In <= XorReg13;
else
Reg1In <= XorReg12;
end if;
if sel2 = "00" then
Reg2In <= DiffOut2;
elsif sel2 = "01" then
Reg2In <= Key(63 downto 0);
elsif sel2 = "10" then
Reg2In <= XorReg2;
else
Reg2In <= XorReg22;
end if;
if sel3 = "00" then
Reg3In <= DiffOut3;
elsif sel3 = "01" then
Reg3In <= IV(127 downto 64);
else
Reg3In <= XorReg31;
end if;
if sel4 = "00" then
Reg4In <= DiffOut4;
elsif sel4 = "01" then
Reg4In <= IV(63 downto 0);
elsif sel4 = "10" then
Reg4In <= XorReg4;
else
Reg4In <= Reg4Out xor SEPCONSTANT;
end if;
XorReg02 <= Reg0Out xor Key(127 downto 64);
XorReg12 <= Reg1Out xor Key(63 downto 0);
XorReg13 <= Reg1Out xor Key(127 downto 64);
XorReg22 <= Reg2Out xor Key(63 downto 0);
XorReg31 <= Reg3Out xor Key(127 downto 64);
XorReg4 <= Reg4Out xor Key(63 downto 0);
-- Set output
OutSig1(127 downto 64) <= XorReg31;
OutSig1(63 downto 0) <= XorReg4;
if selout = '0' then
RegOutIn(127 downto 64) <= (others => '0');
RegOutIn(63 downto 0) <= OutSig0;
else
RegOutIn <= OutSig1;
end if;
DataOut <= RegOutOut;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk,Reset) is
begin
if(Clk = '1' and Clk'event) then
if Reset = '1' then -- synchronous reset
Reg0Out <= (others => '0');
Reg1Out <= (others => '0');
Reg2Out <= (others => '0');
Reg3Out <= (others => '0');
Reg4Out <= (others => '0');
RegOutOut <= (others => '0');
else
-- update registers with enable
if Reg0En = '1' then
Reg0Out <= Reg0In;
end if;
if Reg1En = '1' then
Reg1Out <= Reg1In;
end if;
if Reg2En = '1' then
Reg2Out <= Reg2In;
end if;
if Reg3En = '1' then
Reg3Out <= Reg3In;
end if;
if Reg4En = '1' then
Reg4Out <= Reg4In;
end if;
if RegOutEn = '1' then
RegOutOut <= RegOutIn;
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1743.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p03n01i01743ent IS
END c09s05b00x00p03n01i01743ent;
ARCHITECTURE c09s05b00x00p03n01i01743arch OF c09s05b00x00p03n01i01743ent IS
signal err : bit;
BEGIN
B : block
begin
err <= transport guarded '1';
assert FALSE
report "***FAILED TEST: c09s05b00x00p03n01i01743 - Reserved word guarded must appear precede transport."
severity ERROR;
end block B;
END c09s05b00x00p03n01i01743arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1743.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p03n01i01743ent IS
END c09s05b00x00p03n01i01743ent;
ARCHITECTURE c09s05b00x00p03n01i01743arch OF c09s05b00x00p03n01i01743ent IS
signal err : bit;
BEGIN
B : block
begin
err <= transport guarded '1';
assert FALSE
report "***FAILED TEST: c09s05b00x00p03n01i01743 - Reserved word guarded must appear precede transport."
severity ERROR;
end block B;
END c09s05b00x00p03n01i01743arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1743.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p03n01i01743ent IS
END c09s05b00x00p03n01i01743ent;
ARCHITECTURE c09s05b00x00p03n01i01743arch OF c09s05b00x00p03n01i01743ent IS
signal err : bit;
BEGIN
B : block
begin
err <= transport guarded '1';
assert FALSE
report "***FAILED TEST: c09s05b00x00p03n01i01743 - Reserved word guarded must appear precede transport."
severity ERROR;
end block B;
END c09s05b00x00p03n01i01743arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
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BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
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fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26976)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztlHgsA7XTu3se9+qgRV127JNzgqDsqOZmnkbTLpgbje5vj
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524oxgypSEjMeVHq9PEyg/r44Si457VsQiXzwgf8Jlr3igQ/6AXcZCzPiaxMwnuADYQiDGzV27ls
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yiUBBWTJBV5tP8QPLZ2sT6XmRmHTuqIUcrIe9+eLxnWTxJwzhx1WpgbEITpehiG0dsdsGXSxCOrr
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`protect end_protected
|
------------------------------------------------------------------------------
-- Testbench for reg_clr_en.vhd
--
-- Project :
-- File : tb_reg_clr_en.vhd
-- Author : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/02/12
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_Reg_clr_en is
end tb_Reg_clr_en;
architecture arch of tb_Reg_clr_en is
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, done, en, dis, clr, clr_en);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal ClrxE : std_logic;
signal EnxE : std_logic;
signal DinxD : std_logic_vector(WIDTH-1 downto 0);
signal DoutxD : std_logic_vector(WIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : Reg_Clr_En
generic map (
WIDTH => WIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxEI => ClrxE,
EnxEI => EnxE,
DinxDI => DinxD,
DoutxDO => DoutxD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
ClrxE <= '0';
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(0, WIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= en;
ClrxE <= '0';
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(1, WIDTH));
wait for CLK_PERIOD;
tbStatus <= dis;
ClrxE <= '0';
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(2, WIDTH));
wait for CLK_PERIOD;
tbStatus <= en;
ClrxE <= '0';
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(3, WIDTH));
wait for CLK_PERIOD;
tbStatus <= dis;
ClrxE <= '0';
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(4, WIDTH));
wait for CLK_PERIOD;
tbStatus <= clr;
ClrxE <= '1';
EnxE <= '0';
DinxD <= (others => '0');
wait for CLK_PERIOD;
tbStatus <= en;
ClrxE <= '0';
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(5, WIDTH));
wait for CLK_PERIOD;
tbStatus <= dis;
ClrxE <= '0';
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(6, WIDTH));
wait for CLK_PERIOD;
tbStatus <= clr_en;
ClrxE <= '1';
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(7, WIDTH));
wait for CLK_PERIOD;
tbStatus <= done;
ClrxE <= '0';
EnxE <= '0';
DinxD <= (others => '0');
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
|
entity bug is end entity;
architecture arch of bug is
component comp is port(a :in bit_vector); end component;
constant DATAPATH :natural := 16;
signal a :bit_vector(DATAPATH-1 downto 0);
begin
i_comp: comp port map(a);
end architecture;
entity comp is port(a :in bit_vector); end entity;
architecture arch of comp is
constant DATAPATH :natural := a'length;
signal state :natural;
signal tmp :bit_vector(31 downto 0);
begin
process(a) begin
case DATAPATH is
when 8=>
case state is
when 0=> tmp(1*DATAPATH-1 downto 0*DATAPATH)<=a;
when 1=> tmp(2*DATAPATH-1 downto 1*DATAPATH)<=a;
-- When DATAPATH>10 this range violates bounds, but this code should not be reached because "case DATAPATH is when 8=>"
when 2=> tmp(3*DATAPATH-1 downto 2*DATAPATH)<=a;
when 3=> tmp(4*DATAPATH-1 downto 3*DATAPATH)<=a;
when others=>
end case;
when 16=>
case state is
when 0=> tmp(1*DATAPATH-1 downto 0*DATAPATH)<=a;
when 1=> tmp(2*DATAPATH-1 downto 1*DATAPATH)<=a;
when others=>
end case;
when others=>
end case;
end process;
end architecture;
|
entity bug is end entity;
architecture arch of bug is
component comp is port(a :in bit_vector); end component;
constant DATAPATH :natural := 16;
signal a :bit_vector(DATAPATH-1 downto 0);
begin
i_comp: comp port map(a);
end architecture;
entity comp is port(a :in bit_vector); end entity;
architecture arch of comp is
constant DATAPATH :natural := a'length;
signal state :natural;
signal tmp :bit_vector(31 downto 0);
begin
process(a) begin
case DATAPATH is
when 8=>
case state is
when 0=> tmp(1*DATAPATH-1 downto 0*DATAPATH)<=a;
when 1=> tmp(2*DATAPATH-1 downto 1*DATAPATH)<=a;
-- When DATAPATH>10 this range violates bounds, but this code should not be reached because "case DATAPATH is when 8=>"
when 2=> tmp(3*DATAPATH-1 downto 2*DATAPATH)<=a;
when 3=> tmp(4*DATAPATH-1 downto 3*DATAPATH)<=a;
when others=>
end case;
when 16=>
case state is
when 0=> tmp(1*DATAPATH-1 downto 0*DATAPATH)<=a;
when 1=> tmp(2*DATAPATH-1 downto 1*DATAPATH)<=a;
when others=>
end case;
when others=>
end case;
end process;
end architecture;
|
entity bug is end entity;
architecture arch of bug is
component comp is port(a :in bit_vector); end component;
constant DATAPATH :natural := 16;
signal a :bit_vector(DATAPATH-1 downto 0);
begin
i_comp: comp port map(a);
end architecture;
entity comp is port(a :in bit_vector); end entity;
architecture arch of comp is
constant DATAPATH :natural := a'length;
signal state :natural;
signal tmp :bit_vector(31 downto 0);
begin
process(a) begin
case DATAPATH is
when 8=>
case state is
when 0=> tmp(1*DATAPATH-1 downto 0*DATAPATH)<=a;
when 1=> tmp(2*DATAPATH-1 downto 1*DATAPATH)<=a;
-- When DATAPATH>10 this range violates bounds, but this code should not be reached because "case DATAPATH is when 8=>"
when 2=> tmp(3*DATAPATH-1 downto 2*DATAPATH)<=a;
when 3=> tmp(4*DATAPATH-1 downto 3*DATAPATH)<=a;
when others=>
end case;
when 16=>
case state is
when 0=> tmp(1*DATAPATH-1 downto 0*DATAPATH)<=a;
when 1=> tmp(2*DATAPATH-1 downto 1*DATAPATH)<=a;
when others=>
end case;
when others=>
end case;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc739.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x01p04n03i00739ent_a is
generic (
constant gc1 : integer;
constant gc2 : natural;
constant gc3 : positive
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n03i00739ent_a;
architecture arch of c01s01b01x01p04n03i00739ent_a is
begin
assert false
report "FAIL: should not compile";
end arch;
ENTITY c01s01b01x01p04n03i00739ent IS
generic ( constant gen_con : natural := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n03i00739ent;
ARCHITECTURE c01s01b01x01p04n03i00739arch OF c01s01b01x01p04n03i00739ent IS
signal s1 : integer;
signal s2 : natural;
signal s3 : positive;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : natural;
constant dgc3 : positive
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use entity work.c01s01b01x01p04n03i00739ent_a(arch)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
port map (ee1,ee2);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n03i00739 - Formal generic should have actual map correspoding to."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p04n03i00739arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc739.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x01p04n03i00739ent_a is
generic (
constant gc1 : integer;
constant gc2 : natural;
constant gc3 : positive
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n03i00739ent_a;
architecture arch of c01s01b01x01p04n03i00739ent_a is
begin
assert false
report "FAIL: should not compile";
end arch;
ENTITY c01s01b01x01p04n03i00739ent IS
generic ( constant gen_con : natural := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n03i00739ent;
ARCHITECTURE c01s01b01x01p04n03i00739arch OF c01s01b01x01p04n03i00739ent IS
signal s1 : integer;
signal s2 : natural;
signal s3 : positive;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : natural;
constant dgc3 : positive
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use entity work.c01s01b01x01p04n03i00739ent_a(arch)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
port map (ee1,ee2);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n03i00739 - Formal generic should have actual map correspoding to."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p04n03i00739arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc739.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x01p04n03i00739ent_a is
generic (
constant gc1 : integer;
constant gc2 : natural;
constant gc3 : positive
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n03i00739ent_a;
architecture arch of c01s01b01x01p04n03i00739ent_a is
begin
assert false
report "FAIL: should not compile";
end arch;
ENTITY c01s01b01x01p04n03i00739ent IS
generic ( constant gen_con : natural := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n03i00739ent;
ARCHITECTURE c01s01b01x01p04n03i00739arch OF c01s01b01x01p04n03i00739ent IS
signal s1 : integer;
signal s2 : natural;
signal s3 : positive;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : natural;
constant dgc3 : positive
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use entity work.c01s01b01x01p04n03i00739ent_a(arch)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
port map (ee1,ee2);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n03i00739 - Formal generic should have actual map correspoding to."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p04n03i00739arch;
|
package config_types is
constant cfg_width : integer := 1;
type config_vec_t is array (0 to 16) of integer;
end package;
-------------------------------------------------------------------------------
use work.config_types.all;
package config is
constant cfg_vec : config_vec_t := (
cfg_width => 2,
others => 0);
end package;
-------------------------------------------------------------------------------
use work.config.all;
use work.config_types.all;
package types is
constant width : integer := 2 * cfg_vec(cfg_width);
type rec is record
x : bit_vector(1 to width);
end record;
end package;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24704)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6224)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8336)
`protect data_block
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`protect end_protected
|
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