content stringlengths 1 1.04M ⌀ |
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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8336)
`protect data_block
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|
`protect begin_protected
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32GPfpUuF9UAl2MRD+YlN5Xy+fCtjlIwrWj0U6wxtInMN1TQ/deHRr2EA/KJCN8AokU2rT2WQX8c
ecD/6qzso3E0jCZafZgw+RNwSKqkQp5ZfbltD6Py0NmIRhk6hKAnPgeNNPWms4L0uU6DjGaB3D+h
v6I6KTb16wXO3UFHyGrGJsLw0ahaF7SarJxdf8a3b31wCOuHGMCqvLhPYmN+oeNZciBDJk3Ownpg
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Y4FGYOTWtHe6R06PakA=
`protect end_protected
|
constant bitdataLength : integer := 1282;
constant bitdataCfg : std_logic_vector(bitdataLength-1 downto 0) := "0000000000000000001000000101000011111111000000000000000000001000100000000000000000000011000011000000000000000000000000000000000000000001000000000000000000000000000000000010001000100000000000000000000000000000000000000010001011000000000000000000000000000100100000000000001000011000000000000000000000000100000000000001001000000000000000000000000100001000001000000000000000000000000000000000000000000000000000000001110110100000000000000000000000000000000000000110101011100000000000011110000000000001000000000000000101100000000000000000000000000000000000000000100011001000110001100011000110001100011000110100001101000000100010000000000000001001000000101100100000000000000000000000000000000000000101101100110001000000000000000000000000001010001000000000000000000000000000000000000000110100000000000000000000010000000010000000000000000000000000100000000000000000000000000011010011100000000000001000000000000000000000000000000000000000000000000000001000100110001110000000011001110000000000000000000000000000011001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001011000100000011100000000000000001110000010000001101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
-- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_out
-- ============================================================
-- File Name: output_dqs_iobuf_inst.vhd
-- Megafunction Name(s):
-- altiobuf_out
--
-- Simulation Library Files(s):
-- stratixiii
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.0 Build 231 07/10/2008 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altiobuf_out CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix III" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="TRUE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b oe
--VERSION_BEGIN 8.0SP1 cbx_altiobuf_in 2008:06:02:292401 cbx_mgl 2008:06:02:292401 cbx_stratixiii 2008:06:18:296807 VERSION_END
LIBRARY stratixiii;
USE stratixiii.all;
--synthesis_resources = stratixiii_io_obuf 2 stratixiii_pseudo_diff_out 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY output_dqs_iobuf_inst_iobuf_out_sdp IS
PORT
(
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1');
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1')
);
END output_dqs_iobuf_inst_iobuf_out_sdp;
ARCHITECTURE RTL OF output_dqs_iobuf_inst_iobuf_out_sdp IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_obuf_ba_o : STD_LOGIC;
SIGNAL wire_obufa_o : STD_LOGIC;
SIGNAL wire_pseudo_diffa_o : STD_LOGIC;
SIGNAL wire_pseudo_diffa_obar : STD_LOGIC;
--SIGNAL oe_b : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT stratixiii_io_obuf
GENERIC
(
bus_hold : STRING := "false";
open_drain_output : STRING := "false";
shift_series_termination_control : STRING := "false";
sim_dynamic_termination_control_is_connected : STRING := "false";
lpm_type : STRING := "stratixiii_io_obuf"
);
PORT
(
dynamicterminationcontrol : IN STD_LOGIC := '0';
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
parallelterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
seriesterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT stratixiii_pseudo_diff_out
PORT
(
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
dataout(0) <= wire_obufa_o;
dataout_b(0) <= wire_obuf_ba_o;
--oe_b <= (OTHERS => '1');
obuf_ba : stratixiii_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
i => wire_pseudo_diffa_obar,
o => wire_obuf_ba_o,
oe => oe_b(0)
);
obufa : stratixiii_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
i => wire_pseudo_diffa_o,
o => wire_obufa_o,
oe => oe(0)
);
pseudo_diffa : stratixiii_pseudo_diff_out
PORT MAP (
i => datain(0),
o => wire_pseudo_diffa_o,
obar => wire_pseudo_diffa_obar
);
END RTL; --output_dqs_iobuf_inst_iobuf_out_sdp
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY output_dqs_iobuf_inst IS
PORT
(
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END output_dqs_iobuf_inst;
ARCHITECTURE RTL OF output_dqs_iobuf_inst IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT output_dqs_iobuf_inst_iobuf_out_sdp
PORT (
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(0 DOWNTO 0);
dataout_b <= sub_wire1(0 DOWNTO 0);
output_dqs_iobuf_inst_iobuf_out_sdp_component : output_dqs_iobuf_inst_iobuf_out_sdp
PORT MAP (
datain => datain,
oe => oe,
oe_b => oe_b,
dataout => sub_wire0,
dataout_b => sub_wire1
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
-- Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
-- Retrieval info: CONSTANT: pseudo_differential_mode STRING "TRUE"
-- Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"
-- Retrieval info: CONSTANT: use_oe STRING "TRUE"
-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
-- Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
-- Retrieval info: USED_PORT: dataout_b 0 0 1 0 OUTPUT NODEFVAL "dataout_b[0..0]"
-- Retrieval info: USED_PORT: oe 0 0 1 0 INPUT NODEFVAL "oe[0..0]"
-- Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
-- Retrieval info: CONNECT: dataout_b 0 0 1 0 @dataout_b 0 0 1 0
-- Retrieval info: CONNECT: @oe 0 0 1 0 oe 0 0 1 0
-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst.cmp FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst_inst.vhd FALSE FALSE
-- Retrieval info: LIB_FILE: stratixiii
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grethc
-- File: grethc.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity grethc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of grethc is
procedure sel_op_mode(
capbil : in std_logic_vector(4 downto 0);
speed : out std_ulogic;
duplex : out std_ulogic) is
variable vspeed : std_ulogic;
variable vduplex : std_ulogic;
begin
vspeed := '0'; vduplex := '0';
vspeed := orv(capbil(4 downto 2));
vduplex := (vspeed and capbil(3)) or ((not vspeed) and capbil(1));
speed := vspeed;
duplex := vduplex;
end procedure;
--host constants
constant fabits : integer := log2(fifosize);
constant burstlength : integer := setburstlength(fifosize);
constant burstbits : integer := log2(burstlength);
constant ctrlopcode : std_logic_vector(15 downto 0) := X"8808";
constant broadcast : std_logic_vector(47 downto 0) := X"FFFFFFFFFFFF";
-- constant maxsizetx : integer := 1514;
constant index : integer := log2(edclbufsz);
constant receiveOK : std_logic_vector(3 downto 0) := "0000";
constant frameCheckError : std_logic_vector(3 downto 0) := "0100";
constant alignmentError : std_logic_vector(3 downto 0) := "0001";
constant frameTooLong : std_logic_vector(3 downto 0) := "0010";
constant overrun : std_logic_vector(3 downto 0) := "1000";
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
--mdio constants
constant divisor : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(mdcscaler, 8);
--receiver constants
constant maxsizerx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18 - 4, 16);
--tranceiver constants
constant maxsizetx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18 - 4, 16);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant blbits : szvct := (6, 7, 7, 8, 8, 8, 8);
constant winsz : szvct := (4, 4, 8, 8, 16, 32, 64);
constant macaddrt : std_logic_vector(47 downto 0) :=
conv_std_logic_vector(macaddrh, 24) & conv_std_logic_vector(macaddrl, 24);
constant bpbits : integer := blbits(log2(edclbufsz));
constant wsz : integer := winsz(log2(edclbufsz));
constant bselbits : integer := log2(wsz);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufmax : std_logic_vector(bpbits-1 downto 0) := (others => '1');
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant txfifosizev : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(txfifosize, txfabits+1);
constant rxburstlen : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(burstlength, fabits+1);
constant txburstlen : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(burstlength, txfabits+1);
type edclrstate_type is (idle, wrda, wrdsa, wrsa, wrtype, ip, ipdata,
oplength, arp, iplength, ipcrc, arpop, udp, spill);
type duplexstate_type is (start, waitop, nextop, selmode, done);
--host types
type txd_state_type is (idle, read_desc, check_desc, req, fill_fifo,
check_result, write_result, readhdr, start, wrbus1,
etdone, getlen, ahberror, fill_fifo2, wrbus2);
type rxd_state_type is (idle, read_desc, check_desc, read_req, read_fifo,
discard, write_status, write_status2);
--mdio types
type mdio_state_type is (idle, preamble, startst, op, op2, phyadr, regadr,
ta, ta2, ta3, data, dataend);
type ctrl_reg_type is record
txen : std_ulogic;
rxen : std_ulogic;
tx_irqen : std_ulogic;
rx_irqen : std_ulogic;
full_duplex : std_ulogic;
prom : std_ulogic;
reset : std_ulogic;
speed : std_ulogic;
pstatirqen : std_ulogic;
mcasten : std_ulogic;
ramdebugen : std_ulogic;
edcldis : std_ulogic;
end record;
type status_reg_type is record
tx_int : std_ulogic;
rx_int : std_ulogic;
rx_err : std_ulogic;
tx_err : std_ulogic;
txahberr : std_ulogic;
rxahberr : std_ulogic;
toosmall : std_ulogic;
invaddr : std_ulogic;
phystat : std_ulogic;
end record;
type mdio_ctrl_reg_type is record
phyadr : std_logic_vector(4 downto 0);
regadr : std_logic_vector(4 downto 0);
write : std_ulogic;
read : std_ulogic;
data : std_logic_vector(15 downto 0);
busy : std_ulogic;
linkfail : std_ulogic;
end record;
subtype mac_addr_reg_type is std_logic_vector(47 downto 0);
type fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(fabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(fabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(txfabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(txfabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type edcl_ram_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(eabits-1 downto 0);
writem : std_ulogic;
writel : std_ulogic;
waddressm : std_logic_vector(eabits-1 downto 0);
waddressl : std_logic_vector(eabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type edcl_ram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type reg_type is record
--user registers
ctrl : ctrl_reg_type;
status : status_reg_type;
mdio_ctrl : mdio_ctrl_reg_type;
mac_addr : mac_addr_reg_type;
hash : std_logic_vector(63 downto 0);
txdesc : std_logic_vector(31 downto 10);
rxdesc : std_logic_vector(31 downto 10);
edclip : std_logic_vector(31 downto 0);
--master tx interface
txdsel : std_logic_vector(9 downto 3);
tmsto : eth_tx_ahb_in_type;
tmsto2 : eth_tx_ahb_in_type;
txdstate : txd_state_type;
txwrap : std_ulogic;
txden : std_ulogic;
txirq : std_ulogic;
txaddr : std_logic_vector(31 downto 2);
txlength : std_logic_vector(10 downto 0);
txburstcnt : std_logic_vector(burstbits downto 0);
tfwpnt : std_logic_vector(txfabits-1 downto 0);
tfrpnt : std_logic_vector(txfabits-1 downto 0);
tfcnt : std_logic_vector(txfabits downto 0);
txcnt : std_logic_vector(10 downto 0);
txstart : std_ulogic;
txirqgen : std_ulogic;
txstatus : std_logic_vector(1 downto 0);
txvalid : std_ulogic;
txdata : std_logic_vector(31 downto 0);
writeok : std_ulogic;
txread : std_logic_vector(nsync-1 downto 0);
txrestart : std_logic_vector(nsync downto 0);
txdone : std_logic_vector(nsync downto 0);
txstart_sync : std_ulogic;
txreadack : std_ulogic;
txdataav : std_ulogic;
txburstav : std_ulogic;
--master rx interface
rxrenable : std_ulogic;
rxdsel : std_logic_vector(9 downto 3);
rmsto : eth_rx_ahb_in_type;
rxdstate : rxd_state_type;
rxstatus : std_logic_vector(4 downto 0);
rxaddr : std_logic_vector(31 downto 2);
rxlength : std_logic_vector(10 downto 0);
rxbytecount : std_logic_vector(10 downto 0);
rxwrap : std_ulogic;
rxirq : std_ulogic;
rfwpnt : std_logic_vector(fabits-1 downto 0);
rfrpnt : std_logic_vector(fabits-1 downto 0);
rfcnt : std_logic_vector(fabits downto 0);
rxcnt : std_logic_vector(10 downto 0);
rxdoneold : std_ulogic;
rxdoneack : std_ulogic;
rxdone : std_logic_vector(nsync-1 downto 0);
rxstart : std_logic_vector(nsync downto 0);
rxwrite : std_logic_vector(nsync-1 downto 0);
rxwriteack : std_ulogic;
rxburstcnt : std_logic_vector(burstbits downto 0);
addrok : std_ulogic;
addrdone : std_ulogic;
ctrlpkt : std_ulogic;
check : std_ulogic;
checkdata : std_logic_vector(31 downto 0);
usesizefield : std_ulogic;
rxden : std_ulogic;
gotframe : std_ulogic;
bcast : std_ulogic;
msbgood : std_ulogic;
rxburstav : std_ulogic;
hashlookup : std_ulogic;
mcast : std_ulogic;
mcastacc : std_ulogic;
--mdio
mdccnt : std_logic_vector(7 downto 0);
mdioclk : std_ulogic;
mdioclkold : std_logic_vector(mdiohold-1 downto 0);
mdio_state : mdio_state_type;
mdioo : std_ulogic;
mdioi : std_ulogic;
mdioen : std_ulogic;
cnt : std_logic_vector(4 downto 0);
duplexstate : duplexstate_type;
disableduplex : std_ulogic;
init_busy : std_ulogic;
ext : std_ulogic;
extcap : std_ulogic;
regaddr : std_logic_vector(4 downto 0);
phywr : std_ulogic;
rstphy : std_ulogic;
capbil : std_logic_vector(4 downto 0);
rstaneg : std_ulogic;
mdint_sync : std_logic_vector(2 downto 0);
--edcl
erenable : std_ulogic;
edclrstate : edclrstate_type;
edclactive : std_ulogic;
nak : std_ulogic;
ewr : std_ulogic;
write : std_logic_vector(wsz-1 downto 0);
seq : std_logic_vector(13 downto 0);
abufs : std_logic_vector(bselbits downto 0);
tpnt : std_logic_vector(bselbits-1 downto 0);
rpnt : std_logic_vector(bselbits-1 downto 0);
tcnt : std_logic_vector(bpbits-1 downto 0);
rcntm : std_logic_vector(bpbits-1 downto 0);
rcntl : std_logic_vector(bpbits-1 downto 0);
ipcrc : std_logic_vector(17 downto 0);
applength : std_logic_vector(15 downto 0);
oplen : std_logic_vector(9 downto 0);
udpsrc : std_logic_vector(15 downto 0);
ecnt : std_logic_vector(3 downto 0);
tarp : std_ulogic;
tnak : std_ulogic;
tedcl : std_ulogic;
edclbcast : std_ulogic;
etxidle : std_ulogic;
erxidle : std_ulogic;
emacaddr : std_logic_vector(47 downto 0);
edclsepahb : std_ulogic;
end record;
--host signals
signal arst : std_ulogic;
signal irst : std_ulogic;
signal vcc : std_ulogic;
signal tmsto : eth_tx_ahb_in_type;
signal tmsti : eth_tx_ahb_out_type;
signal tmsto2 : eth_tx_ahb_in_type;
signal tmsti2 : eth_tx_ahb_out_type;
signal rmsto : eth_rx_ahb_in_type;
signal rmsti : eth_rx_ahb_out_type;
signal ahbmi : ahbc_mst_in_type;
signal ahbmo : ahbc_mst_out_type;
signal ahbmi2 : ahbc_mst_in_type;
signal ahbmo2 : ahbc_mst_out_type;
signal txi : host_tx_type;
signal txo : tx_host_type;
signal rxi : host_rx_type;
signal rxo : rx_host_type;
signal r, rin : reg_type;
attribute sync_set_reset of irst : signal is "true";
attribute async_set_reset of arst : signal is "true";
begin
--reset generators for transmitter and receiver
vcc <= '1';
arst <= testrst when (scanen = 1) and (testen = '1')
else rst and not r.ctrl.reset;
irst <= rst and not r.ctrl.reset;
comb : process(rst, irst, r, rmsti, tmsti, txo, rxo, psel, paddr, penable,
erdata, pwrite, pwdata, rxrdata, txrdata, mdio_i, phyrstaddr,
testen, testrst, edcladdr, mdint, tmsti2, edcldisable,
edclsepahb) is
variable v : reg_type;
variable vpirq : std_ulogic;
variable vprdata : std_logic_vector(31 downto 0);
variable txvalid : std_ulogic;
variable vtxfi : tx_fifo_access_in_type;
variable vrxfi : fifo_access_in_type;
variable lengthav : std_ulogic;
variable txdone : std_ulogic;
variable txread : std_ulogic;
variable txrestart : std_ulogic;
variable rxstart : std_ulogic;
variable rxdone : std_ulogic;
variable vrxwrite : std_ulogic;
variable ovrunstop : std_ulogic;
variable edcldbgread : std_ulogic;
--mdio
variable mdioindex : integer range 0 to 31;
variable mclk : std_ulogic; --rising mdio clk edge
variable nmclk : std_ulogic; --falling mdio clk edge
variable mclkvec : std_logic_vector(mdiohold downto 0);
--edcl
variable veri : edcl_ram_in_type;
variable swap : std_ulogic;
variable setmz : std_ulogic;
variable ipcrctmp : std_logic_vector(15 downto 0);
variable ipcrctmp2 : std_logic_vector(17 downto 0);
variable vrxenable : std_ulogic;
variable crctmp : std_ulogic;
variable vecnt : integer;
begin
v := r; vprdata := (others => '0'); vpirq := '0';
v.check := '0'; lengthav := r.rxdoneold;-- or r.usesizefield;
ovrunstop := '0'; vrxfi.raddress := v.rfrpnt;
if edcl /= 0 then
veri.renable := r.erenable;
veri.datain := rxo.dataout;
veri.writem := '0'; veri.writel := '0';
veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl;
end if;
vtxfi.renable := '0';
vtxfi.datain := tmsti.data;
vtxfi.raddress := r.tfrpnt; vtxfi.write := '0';
vtxfi.waddress := r.tfwpnt;
vrxfi.datain := rxo.dataout;
vrxfi.write := '0'; vrxfi.waddress := r.rfwpnt;
vrxfi.renable := r.rxrenable; vrxenable := r.ctrl.rxen;
--synchronization
v.txdone(0) := txo.done;
v.txread(0) := txo.read;
v.txrestart(0) := txo.restart;
v.rxstart(0) := rxo.start;
v.rxdone(0) := rxo.done;
v.rxwrite(0) := rxo.write;
if nsync = 2 then
v.txdone(1) := r.txdone(0);
v.txread(1) := r.txread(0);
v.txrestart(1) := r.txrestart(0);
v.rxstart(1) := r.rxstart(0);
v.rxdone(1) := r.rxdone(0);
v.rxwrite(1) := r.rxwrite(0);
end if;
if enable_mdint = 1 then
v.mdint_sync(0) := mdint;
v.mdint_sync(1) := r.mdint_sync(0);
v.mdint_sync(2) := r.mdint_sync(1);
end if;
txdone := r.txdone(nsync) xor r.txdone(nsync-1);
txread := r.txreadack xor r.txread(nsync-1);
txrestart := r.txrestart(nsync) xor r.txrestart(nsync-1);
rxstart := r.rxstart(nsync) xor r.rxstart(nsync-1);
rxdone := r.rxdoneack xor r.rxdone(nsync-1);
vrxwrite := r.rxwriteack xor r.rxwrite(nsync-1);
if txdone = '1' then
v.txstatus := txo.status;
end if;
-------------------------------------------------------------------------------
-- HOST INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--SLAVE INTERFACE
if ramdebug = 2 then
edcldbgread := '0';
end if;
--write
if (psel and penable and pwrite) = '1' then
if (ramdebug = 0) or (paddr(17 downto 16) = "00") then
case paddr(5 downto 2) is
when "0000" => --ctrl reg
if ramdebug /= 0 then
v.ctrl.ramdebugen := pwdata(13);
end if;
if edcl /= 0 then
v.ctrl.edcldis := pwdata(14);
v.disableduplex := pwdata(12);
end if;
if multicast = 1 then
v.ctrl.mcasten := pwdata(11);
end if;
if enable_mdint = 1 then
v.ctrl.pstatirqen := pwdata(10);
end if;
if rmii = 1 then
v.ctrl.speed := pwdata(7);
end if;
v.ctrl.reset := pwdata(6);
v.ctrl.prom := pwdata(5);
v.ctrl.full_duplex := pwdata(4);
v.ctrl.rx_irqen := pwdata(3);
v.ctrl.tx_irqen := pwdata(2);
v.ctrl.rxen := pwdata(1);
v.ctrl.txen := pwdata(0);
when "0001" => --status/int source reg
if enable_mdint = 1 then
if pwdata(8) = '1' then v.status.phystat := '0'; end if;
end if;
if pwdata(7) = '1' then v.status.invaddr := '0'; end if;
if pwdata(6) = '1' then v.status.toosmall := '0'; end if;
if pwdata(5) = '1' then v.status.txahberr := '0'; end if;
if pwdata(4) = '1' then v.status.rxahberr := '0'; end if;
if pwdata(3) = '1' then v.status.tx_int := '0'; end if;
if pwdata(2) = '1' then v.status.rx_int := '0'; end if;
if pwdata(1) = '1' then v.status.tx_err := '0'; end if;
if pwdata(0) = '1' then v.status.rx_err := '0'; end if;
when "0010" => --mac addr msb
v.mac_addr(47 downto 32) := pwdata(15 downto 0);
when "0011" => --mac addr lsb
v.mac_addr(31 downto 0) := pwdata(31 downto 0);
when "0100" => --mdio ctrl/status
if enable_mdio = 1 then
if r.mdio_ctrl.busy = '0' then
v.mdio_ctrl.data := pwdata(31 downto 16);
v.mdio_ctrl.phyadr := pwdata(15 downto 11);
v.mdio_ctrl.regadr := pwdata(10 downto 6);
v.mdio_ctrl.read := pwdata(1);
v.mdio_ctrl.write := pwdata(0);
v.mdio_ctrl.busy := pwdata(1) or pwdata(0);
end if;
end if;
when "0101" => --tx descriptor
v.txdesc := pwdata(31 downto 10);
v.txdsel := pwdata(9 downto 3);
when "0110" => --rx descriptor
v.rxdesc := pwdata(31 downto 10);
v.rxdsel := pwdata(9 downto 3);
when "0111" => --edcl ip
if (edcl /= 0) then
v.edclip := pwdata;
end if;
when "1000" => --hash msb
if multicast = 1 then
v.hash(63 downto 32) := pwdata;
end if;
when "1001" => --hash lsb
if multicast = 1 then
v.hash(31 downto 0) := pwdata;
end if;
when "1010" =>
if edcl /= 0 then
v.emacaddr(47 downto 32) := pwdata(15 downto 0);
end if;
when "1011" =>
if edcl /= 0 then
v.emacaddr(31 downto 0) := pwdata;
end if;
when others => null;
end case;
elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "01")) then
if r.ctrl.ramdebugen = '1' then
vtxfi.write := '1';
vtxfi.waddress := paddr(txfabits+1 downto 2);
vtxfi.datain := pwdata;
end if;
elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "10")) then
if r.ctrl.ramdebugen = '1' then
vrxfi.write := '1';
vrxfi.waddress := paddr(fabits+1 downto 2);
vrxfi.datain := pwdata;
end if;
elsif ((ramdebug = 2) and (edcl /= 0) and (paddr(17 downto 16) = "11")) then
if r.ctrl.ramdebugen = '1' then
veri.datain := pwdata;
veri.waddressm := paddr(eabits+1 downto 2);
veri.waddressl := paddr(eabits+1 downto 2);
veri.writem := '1';
veri.writel := '1';
end if;
end if;
end if;
--read
if (ramdebug = 0) or (paddr(17 downto 16) = "00") then
case paddr(5 downto 2) is
when "0000" => --ctrl reg
if ramdebug /= 0 then
vprdata(13) := r.ctrl.ramdebugen;
end if;
if (edcl /= 0) then
vprdata(31) := '1';
vprdata(30 downto 28) := bufsize;
vprdata(14) := r.ctrl.edcldis;
vprdata(12) := r.disableduplex;
end if;
if enable_mdint = 1 then
vprdata(26) := '1';
vprdata(10) := r.ctrl.pstatirqen;
end if;
if multicast = 1 then
vprdata(25) := '1';
vprdata(11) := r.ctrl.mcasten;
end if;
if rmii = 1 then
vprdata(7) := r.ctrl.speed;
end if;
vprdata(6) := r.ctrl.reset;
vprdata(5) := r.ctrl.prom;
vprdata(4) := r.ctrl.full_duplex;
vprdata(3) := r.ctrl.rx_irqen;
vprdata(2) := r.ctrl.tx_irqen;
vprdata(1) := r.ctrl.rxen;
vprdata(0) := r.ctrl.txen;
when "0001" => --status/int source reg
vprdata(9) := not (r.etxidle or r.erxidle);
if enable_mdint = 1 then
vprdata(8) := r.status.phystat;
end if;
vprdata(7) := r.status.invaddr;
vprdata(6) := r.status.toosmall;
vprdata(5) := r.status.txahberr;
vprdata(4) := r.status.rxahberr;
vprdata(3) := r.status.tx_int;
vprdata(2) := r.status.rx_int;
vprdata(1) := r.status.tx_err;
vprdata(0) := r.status.rx_err;
when "0010" => --mac addr msb/mdio address
vprdata(15 downto 0) := r.mac_addr(47 downto 32);
when "0011" => --mac addr lsb
vprdata := r.mac_addr(31 downto 0);
when "0100" => --mdio ctrl/status
vprdata(31 downto 16) := r.mdio_ctrl.data;
vprdata(15 downto 11) := r.mdio_ctrl.phyadr;
vprdata(10 downto 6) := r.mdio_ctrl.regadr;
vprdata(3) := r.mdio_ctrl.busy;
vprdata(2) := r.mdio_ctrl.linkfail;
vprdata(1) := r.mdio_ctrl.read;
vprdata(0) := r.mdio_ctrl.write;
when "0101" => --tx descriptor
vprdata(31 downto 10) := r.txdesc;
vprdata(9 downto 3) := r.txdsel;
when "0110" => --rx descriptor
vprdata(31 downto 10) := r.rxdesc;
vprdata(9 downto 3) := r.rxdsel;
when "0111" => --edcl ip
if (edcl /= 0) then
vprdata := r.edclip;
end if;
when "1000" =>
if multicast = 1 then
vprdata := r.hash(63 downto 32);
end if;
when "1001" =>
if multicast = 1 then
vprdata := r.hash(31 downto 0);
end if;
when "1010" =>
if edcl /= 0 then
vprdata(15 downto 0) := r.emacaddr(47 downto 32);
end if;
when "1011" =>
if edcl /= 0 then
vprdata := r.emacaddr(31 downto 0);
end if;
when others => null;
end case;
elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "01")) then
if r.ctrl.ramdebugen = '1' then
vtxfi.renable := '1';
vtxfi.raddress := paddr(txfabits+1 downto 2);
vprdata := txrdata;
end if;
elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "10")) then
if r.ctrl.ramdebugen = '1' then
vrxfi.renable := '1';
vrxfi.raddress := paddr(fabits+1 downto 2);
vprdata := rxrdata;
end if;
elsif ((ramdebug = 2) and (edcl /= 0) and (paddr(17 downto 16) = "11")) then
if r.ctrl.ramdebugen = '1' then
edcldbgread := '1';
veri.renable := '1';
veri.raddress := paddr(eabits+1 downto 2);
vprdata := erdata;
end if;
end if;
--PHY STATUS DETECTION
if enable_mdint = 1 then
if mdint_pol = 0 then
if (r.mdint_sync(2) and not r.mdint_sync(1)) = '1' then
v.status.phystat := '1';
if r.ctrl.pstatirqen = '1' then
vpirq := '1';
end if;
end if;
else
if (r.mdint_sync(1) and not r.mdint_sync(2)) = '1' then
v.status.phystat := '1';
if r.ctrl.pstatirqen = '1' then
vpirq := '1';
end if;
end if;
end if;
end if;
--MASTER INTERFACE
v.txburstav := '0';
if (txfifosizev - r.tfcnt) >= txburstlen then
v.txburstav := '1';
end if;
if (conv_integer(r.abufs) /= 0) then
v.etxidle := '0';
else
v.etxidle := '1';
end if;
--tx dma fsm
case r.txdstate is
when idle =>
v.txcnt := (others => '0'); v.txburstcnt := (others => '0');
if (edcl /= 0) then
v.tedcl := '0'; v.erenable := '0';
end if;
if (edcl /= 0) and (conv_integer(r.abufs) /= 0) and
(r.ctrl.edcldis = '0') then
v.erenable := '1'; v.etxidle := '0';
if r.erenable = '1' then
v.txdstate := getlen;
end if;
v.tcnt := conv_std_logic_vector(10, bpbits);
elsif r.ctrl.txen = '1' then
v.txdstate := read_desc; v.tmsto.write := '0';
v.tmsto.addr := r.txdesc & r.txdsel & "000"; v.tmsto.req := '1';
end if;
if r.txirqgen = '1' then
vpirq := '1'; v.txirqgen := '0';
end if;
if txrestart = '1' then
v.txrestart(nsync) := r.txrestart(nsync-1);
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
end if;
when read_desc =>
v.tmsto.write := '0'; v.txstatus := (others => '0');
v.tfwpnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfcnt := (others => '0');
if tmsti.grant = '1' then
v.txburstcnt := r.txburstcnt + 1; v.tmsto.addr := r.tmsto.addr + 4;
if r.txburstcnt(0) = '1' then
v.tmsto.req := '0';
end if;
end if;
if tmsti.ready = '1' then
v.txcnt := r.txcnt + 1;
case r.txcnt(1 downto 0) is
when "00" =>
v.txlength := tmsti.data(10 downto 0);
v.txden := tmsti.data(11);
v.txwrap := tmsti.data(12);
v.txirq := tmsti.data(13);
v.ctrl.txen := tmsti.data(11);
when "01" =>
v.txaddr := tmsti.data(31 downto 2);
v.txdstate := check_desc;
when others => null;
end case;
end if;
when check_desc =>
v.txstart := '0';
v.txburstcnt := (others => '0');
if r.txden = '1' then
if (unsigned(r.txlength) > unsigned(maxsizetx)) or
(conv_integer(r.txlength) = 0) then
v.txdstate := write_result; v.tmsto.req := '1';
v.tmsto.write := '1'; v.tmsto.addr := r.txdesc & r.txdsel & "000";
v.tmsto.data := (others => '0');
else
v.txdstate := req;
v.tmsto.addr := r.txaddr & "00"; v.txcnt(10 downto 0) := r.txlength;
end if;
else
v.txdstate := idle;
end if;
when req =>
if txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := idle;
end if;
elsif txdone = '1' then
v.txdstate := check_result;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone;
end if;
elsif conv_integer(r.txcnt) = 0 then
v.txdstate := check_result;
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone; v.txstart_sync := not r.txstart_sync;
end if;
elsif (r.txburstav = '1') or (r.tedcl = '1') then
if (edclsepahbg = 0) or (edcl = 0) or
(r.edclsepahb = '0') or (r.tedcl = '0') then
v.tmsto.req := '1'; v.txdstate := fill_fifo;
else
v.tmsto2.req := '1'; v.txdstate := fill_fifo2;
end if;
end if;
v.txburstcnt := (others => '0');
when fill_fifo =>
v.txburstav := '0';
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) or
((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) then
v.tmsto.req := '0';
end if;
v.txburstcnt := r.txburstcnt + 1;
if (conv_integer(r.txburstcnt) = burstlength-1) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti.error) = '1') then
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1';
if r.tmsto.req = '0' then
v.txdstate := req;
if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then
v.txstart := '1'; v.txstart_sync := not r.txstart_sync;
end if;
end if;
if conv_integer(r.txcnt) > 3 then
v.txcnt := r.txcnt - 4;
else
v.txcnt := (others => '0');
end if;
end if;
when fill_fifo2 =>
if edclsepahbg = 1 then
v.txburstav := '0';
vtxfi.datain := tmsti2.data;
if tmsti2.grant = '1' then
v.tmsto2.addr := r.tmsto2.addr + 4;
if ((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) or
((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) then
v.tmsto2.req := '0';
end if;
v.txburstcnt := r.txburstcnt + 1;
if (conv_integer(r.txburstcnt) = burstlength-1) then
v.tmsto2.req := '0';
end if;
end if;
if (tmsti2.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti2.error) = '1') then
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1';
if r.tmsto2.req = '0' then
v.txdstate := req;
if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then
v.txstart := '1'; v.txstart_sync := not r.txstart_sync;
end if;
end if;
if conv_integer(r.txcnt) > 3 then
v.txcnt := r.txcnt - 4;
else
v.txcnt := (others => '0');
end if;
end if;
end if;
when check_result =>
if txdone = '1' then
v.txdstate := write_result; v.tmsto.req := '1'; v.txstart := '0';
v.tmsto.write := '1'; v.tmsto.addr := r.txdesc & r.txdsel & "000";
v.tmsto.data(31 downto 16) := (others => '0');
v.tmsto.data(15 downto 14) := v.txstatus;
v.tmsto.data(13 downto 0) := (others => '0');
v.txdone(nsync) := r.txdone(nsync-1);
elsif txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
end if;
when write_result =>
if tmsti.grant = '1' then
v.tmsto.req := '0'; v.tmsto.addr := r.tmsto.addr + 4;
end if;
if tmsti.ready = '1' then
v.txdstate := idle;
v.txirqgen := r.ctrl.tx_irqen and r.txirq;
if r.txwrap = '0' then v.txdsel := r.txdsel + 1;
else v.txdsel := (others => '0'); end if;
if conv_integer(r.txstatus) = 0 then v.status.tx_int := '1';
else v.status.tx_err := '1'; end if;
end if;
when ahberror =>
v.tfcnt := (others => '0'); v.tfwpnt := (others => '0');
v.tfrpnt := (others => '0');
v.status.txahberr := '1'; v.ctrl.txen := '0';
if not ((edcl /= 0) and (r.tedcl = '1')) then
if r.txstart = '1' then
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
end if;
else
v.txdstate := idle;
end if;
else
v.txdstate := idle;
v.abufs := r.abufs - 1; v.tpnt := r.tpnt + 1;
end if;
when others =>
null;
end case;
--tx fifo read
v.txdataav := '0';
if conv_integer(r.tfcnt) /= 0 then
v.txdataav := '1';
end if;
if txread = '1' then
v.txreadack := not r.txreadack;
if r.txdataav = '1' then
if conv_integer(r.tfcnt) < 2 then
v.txdataav := '0';
end if;
v.txvalid := '1';
v.tfcnt := v.tfcnt - 1; v.tfrpnt := r.tfrpnt + 1;
else
v.txvalid := '0';
end if;
v.txdata := txrdata;
end if;
v.rxburstav := '0';
if r.rfcnt >= rxburstlen then
v.rxburstav := '1';
end if;
if ramdebug = 0 then
vtxfi.renable := v.txdataav;
else
vtxfi.renable := vtxfi.renable or v.txdataav;
end if;
--rx dma fsm
case r.rxdstate is
when idle =>
v.rmsto.req := '0'; v.rmsto.write := '0'; v.addrok := '0';
v.rxburstcnt := (others => '0'); v.addrdone := '0';
v.rxcnt := (others => '0'); v.rxdoneold := '0';
v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0';
v.msbgood := '0'; v.rxrenable := '0';
if multicast = 1 then
v.mcast := '0'; v.mcastacc := '0';
end if;
if r.ctrl.rxen = '1' then
v.rxdstate := read_desc; v.rmsto.req := '1';
v.rmsto.addr := r.rxdesc & r.rxdsel & "000";
elsif rxstart = '1' then
v.rxstart(nsync) := r.rxstart(nsync-1);
v.rxdstate := discard;
end if;
when read_desc =>
v.rxstatus := (others => '0');
if rmsti.grant = '1' then
v.rxburstcnt := r.rxburstcnt + 1; v.rmsto.addr := r.rmsto.addr + 4;
if r.rxburstcnt(0) = '1' then
v.rmsto.req := '0';
end if;
end if;
if rmsti.ready = '1' then
v.rxcnt := r.rxcnt + 1;
case r.rxcnt(1 downto 0) is
when "00" =>
v.ctrl.rxen := rmsti.data(11);
v.rxden := rmsti.data(11);
v.rxwrap := rmsti.data(12);
v.rxirq := rmsti.data(13);
when "01" =>
v.rxaddr := rmsti.data(31 downto 2);
v.rxdstate := check_desc;
v.rxrenable := '1';
when others =>
null;
end case;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.ctrl.rxen := '0';
end if;
when check_desc =>
v.rxcnt := (others => '0'); v.usesizefield := '0'; v.rmsto.write := '1';
if r.rxden = '1' then
if rxstart = '1' then
v.rxdstate := read_req; v.rxstart(nsync) := r.rxstart(nsync-1);
end if;
else
v.rxdstate := idle;
end if;
v.rmsto.addr := r.rxaddr & "00";
when read_req =>
if r.edclactive = '1' then
v.rxdstate := discard;
elsif (r.rxdoneold and r.rxstatus(3)) = '1' then
v.rxdstate := write_status;
v.rfcnt := (others => '0'); v.rfwpnt := (others => '0');
v.rfrpnt := (others => '0'); v.writeok := '1';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
elsif ((r.addrdone and not r.addrok) or r.ctrlpkt) = '1' then
v.rxdstate := discard; v.status.invaddr := '1';
elsif ((r.rxdoneold = '1') and r.rxcnt >= r.rxlength) then
if r.gotframe = '1' then
v.rxdstate := write_status;
else
v.rxdstate := discard; v.status.toosmall := '1';
end if;
elsif (r.rxburstav or r.rxdoneold) = '1' then
v.rmsto.req := '1'; v.rxdstate := read_fifo;
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
end if;
v.rxburstcnt := (others => '0'); v.rmsto.data := rxrdata;
when read_fifo =>
v.rxburstav := '0';
if rmsti.grant = '1' then
v.rmsto.addr := r.rmsto.addr + 4;
if (lengthav = '1') then
if ((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 8)) and (rmsti.ready = '1')) or
((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 4)) and (rmsti.ready = '0')) then
v.rmsto.req := '0';
end if;
end if;
v.rxburstcnt := r.rxburstcnt + 1;
if (conv_integer(r.rxburstcnt) = burstlength-1) then
v.rmsto.req := '0';
end if;
end if;
if rmsti.ready = '1' then
v.rmsto.data := rxrdata;
v.rxcnt := r.rxcnt + 4;
if r.rmsto.req = '0' then
v.rxdstate := read_req;
else
v.rfcnt := r.rfcnt - 1; v.rfrpnt := r.rfrpnt + 1;
end if;
v.check := '1'; v.checkdata := r.rmsto.data;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := discard;
v.rxcnt := r.rxcnt + 4;
v.status.rxahberr := '1'; v.ctrl.rxen := '0';
end if;
when write_status =>
v.rmsto.req := '1'; v.rmsto.addr := r.rxdesc & r.rxdsel & "000";
v.rxdstate := write_status2;
if multicast = 1 then
v.rmsto.data := "00000" & r.mcastacc & "0000000" &
r.rxstatus & "000" & r.rxlength;
else
v.rmsto.data := "0000000000000" &
r.rxstatus & "000" & r.rxlength;
end if;
when write_status2 =>
if rmsti.grant = '1' then
v.rmsto.req := '0'; v.rmsto.addr := r.rmsto.addr + 4;
end if;
if rmsti.ready = '1' then
if (r.rxstatus(4) or not r.rxstatus(3)) = '1' then
v.rxdstate := discard;
else
v.rxdstate := idle;
end if;
if (r.ctrl.rx_irqen and r.rxirq) = '1' then
vpirq := '1';
end if;
if conv_integer(r.rxstatus) = 0 then v.status.rx_int := '1';
else v.status.rx_err := '1'; end if;
if r.rxwrap = '1' then
v.rxdsel := (others => '0');
else
v.rxdsel := r.rxdsel + 1;
end if;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.ctrl.rxen := '0';
end if;
when discard =>
if (r.rxdoneold = '0') then
if conv_integer(r.rfcnt) /= 0 then
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
v.rxcnt := r.rxcnt + 4;
end if;
else
if r.rxstatus(3) = '1' then
v.rfcnt := (others => '0'); v.rfwpnt := (others => '0');
v.rfrpnt := (others => '0'); v.writeok := '1';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
v.rxdstate := idle;
elsif (conv_integer(r.rxcnt) < conv_integer(r.rxbytecount)) then
if conv_integer(r.rfcnt) /= 0 then
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
v.rxcnt := r.rxcnt + 4;
end if;
else
v.rxdstate := idle; v.ctrlpkt := '0';
end if;
end if;
when others =>
null;
end case;
--rx address/type check
if r.check = '1' and r.rxcnt(10 downto 5) = "000000" then
case r.rxcnt(4 downto 2) is
when "001" =>
if r.ctrl.prom = '1' then
v.addrok := '1';
end if;
v.mcast := r.checkdata(24);
if r.checkdata = broadcast(47 downto 16) then
v.bcast := '1';
end if;
if r.checkdata = r.mac_addr(47 downto 16) then
v.msbgood := '1';
end if;
when "010" =>
if r.checkdata(31 downto 16) = broadcast(15 downto 0) then
if r.bcast = '1' then
v.addrok := '1';
end if;
else
v.bcast := '0';
end if;
if r.checkdata(31 downto 16) = r.mac_addr(15 downto 0) then
if r.msbgood = '1' then
v.addrok := '1';
end if;
end if;
if multicast = 1 then
v.hashlookup := r.hash(conv_integer(rxo.mcasthash));
end if;
when "011" =>
if multicast = 1 then
if (r.hashlookup and r.ctrl.mcasten and r.mcast) = '1' then
v.addrok := '1';
if r.bcast = '0' then
v.mcastacc := '1';
end if;
end if;
end if;
when "100" =>
if r.checkdata(31 downto 16) = ctrlopcode then v.ctrlpkt := '1'; end if;
v.addrdone := '1';
when others =>
null;
end case;
end if;
--rx packet done
if (rxdone and not rxstart) = '1' then
v.gotframe := rxo.gotframe; v.rxbytecount := rxo.byte_count;
v.rxstatus(3 downto 0) := rxo.status;
if (unsigned(rxo.lentype) > maxsizerx) or (rxo.status /= "0000") then
v.rxlength := rxo.byte_count;
else
v.rxlength := rxo.lentype(10 downto 0);
if (rxo.lentype(10 downto 0) > minpload) and
(rxo.lentype(10 downto 0) /= rxo.byte_count) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
elsif (rxo.lentype(10 downto 0) <= minpload) and
(rxo.byte_count /= minpload) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
end if;
end if;
v.rxdoneold := '1';
v.rxdoneack := not r.rxdoneack;
end if;
--rx fifo write
if vrxwrite = '1' then
v.rxwriteack := not r.rxwriteack;
if (not r.rfcnt(fabits)) = '1' then
v.rfwpnt := r.rfwpnt + 1; v.rfcnt := v.rfcnt + 1; v.writeok := '1';
vrxfi.write := '1';
else
v.writeok := '0';
end if;
end if;
--must be placed here because it uses variable
if (ramdebug = 0) or (r.ctrl.ramdebugen = '0') then
vrxfi.raddress := v.rfrpnt;
end if;
-------------------------------------------------------------------------------
-- MDIO INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--mdio commands
if enable_mdio = 1 then
mclkvec := r.mdioclkold & r.mdioclk;
mclk := mclkvec(mdiohold-1) and not mclkvec(mdiohold);
nmclk := mclkvec(1) and not mclkvec(0);
v.mdioclkold := mclkvec(mdiohold-1 downto 0);
if r.mdccnt = "00000000" then
v.mdccnt := divisor;
v.mdioclk := not r.mdioclk;
else
v.mdccnt := r.mdccnt - 1;
end if;
mdioindex := conv_integer(r.cnt); v.mdioi := mdio_i;
case r.mdio_state is
when idle =>
if (enable_mdio = 1) and (edcl = 0) and (r.ctrl.reset = '1') then
v.mdio_state := idle; v.mdio_ctrl.read := '0';
v.mdio_ctrl.write := '0'; v.mdio_ctrl.busy := '0';
v.mdio_ctrl.data := (others => '0');
v.mdio_ctrl.regadr := (others => '0');
v.ctrl.reset := '0';
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
end if;
if mclk = '1' then
v.cnt := (others => '0');
if r.mdio_ctrl.busy = '1' then
v.mdio_ctrl.linkfail := '0';
if r.mdio_ctrl.read = '1' then
v.mdio_ctrl.write := '0';
end if;
v.mdio_state := preamble; v.mdioo := '1';
if OEPOL = 0 then v.mdioen := '0'; else v.mdioen := '1'; end if;
end if;
end if;
when preamble =>
if mclk = '1' then
v.cnt := r.cnt + 1;
if r.cnt = "11111" then
v.mdioo := '0'; v.mdio_state := startst;
end if;
end if;
when startst =>
if mclk = '1' then
v.mdioo := '1'; v.mdio_state := op; v.cnt := (others => '0');
end if;
when op =>
if mclk = '1' then
v.mdio_state := op2;
if r.mdio_ctrl.read = '1' then v.mdioo := '1';
else v.mdioo := '0'; end if;
end if;
when op2 =>
if mclk = '1' then
v.mdioo := not r.mdioo; v.mdio_state := phyadr;
v.cnt := (others => '0');
end if;
when phyadr =>
if mclk = '1' then
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := r.mdio_ctrl.phyadr(4);
when 1 => v.mdioo := r.mdio_ctrl.phyadr(3);
when 2 => v.mdioo := r.mdio_ctrl.phyadr(2);
when 3 => v.mdioo := r.mdio_ctrl.phyadr(1);
when 4 => v.mdioo := r.mdio_ctrl.phyadr(0);
v.mdio_state := regadr; v.cnt := (others => '0');
when others => null;
end case;
end if;
when regadr =>
if mclk = '1' then
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := r.mdio_ctrl.regadr(4);
when 1 => v.mdioo := r.mdio_ctrl.regadr(3);
when 2 => v.mdioo := r.mdio_ctrl.regadr(2);
when 3 => v.mdioo := r.mdio_ctrl.regadr(1);
when 4 => v.mdioo := r.mdio_ctrl.regadr(0);
v.mdio_state := ta; v.cnt := (others => '0');
when others => null;
end case;
end if;
when ta =>
if mclk = '1' then
v.mdio_state := ta2;
if r.mdio_ctrl.read = '1' then
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
else v.mdioo := '1'; end if;
end if;
when ta2 =>
if mclk = '1' then
v.cnt := "01111"; v.mdio_state := ta3;
if r.mdio_ctrl.write = '1' then v.mdioo := '0'; v.mdio_state := data; end if;
end if;
when ta3 =>
if mclk = '1' then
v.mdio_state := data;
end if;
if nmclk = '1' then
if r.mdioi /= '0' then
v.mdio_ctrl.linkfail := '1';
end if;
end if;
when data =>
if mclk = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "00000" then
v.mdio_state := dataend;
end if;
if r.mdio_ctrl.read = '0' then
v.mdioo := r.mdio_ctrl.data(mdioindex);
end if;
end if;
if nmclk = '1' then
if r.mdio_ctrl.read = '1' then
v.mdio_ctrl.data(mdioindex) := r.mdioi;
end if;
end if;
when dataend =>
if mclk = '1' then
if (rmii = 1) or (edcl /= 0) then
v.init_busy := '0';
if (r.duplexstate = done or r.ctrl.edcldis = '1' or r.disableduplex = '1') then
v.mdio_ctrl.busy := '0';
end if;
else
v.mdio_ctrl.busy := '0';
end if;
v.mdio_ctrl.read := '0';
v.mdio_ctrl.write := '0'; v.mdio_state := idle;
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
end if;
when others =>
null;
end case;
end if;
-------------------------------------------------------------------------------
-- EDCL -----------------------------------------------------------------------
-------------------------------------------------------------------------------
if (edcl /= 0) then
if (ramdebug /= 2) or (r.ctrl.ramdebugen = '0') then
veri.renable := r.erenable; veri.writem := '0'; veri.writel := '0';
veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl;
vrxenable := '1';
end if;
swap := '0'; vecnt := conv_integer(r.ecnt); setmz := '0';
if vrxwrite = '1' then
if r.ctrl.edcldis = '0' then
v.rxwriteack := not r.rxwriteack;
end if;
end if;
--edcl receiver
case r.edclrstate is
when idle =>
v.edclbcast := '0'; v.erxidle := '1';
if (ramdebug /= 2) or (r.ctrl.ramdebugen = '0') then
if (rxstart and not r.ctrl.edcldis) = '1' then
v.edclrstate := wrda; v.edclactive := '0'; v.erxidle := '0';
v.rcntm := conv_std_logic_vector(2, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
end if;
end if;
when wrda =>
if vrxwrite = '1' then
v.edclrstate := wrdsa;
veri.writem := '1'; veri.writel := '1';
swap := '1';
v.rcntm := r.rcntm - 2; v.rcntl := r.rcntl + 1;
if (r.emacaddr(47 downto 16) /= rxo.dataout) and
(X"FFFFFFFF" /= rxo.dataout) then
v.edclrstate := spill;
elsif (X"FFFFFFFF" = rxo.dataout) then
v.edclbcast := '1';
end if;
if conv_integer(r.abufs) = wsz then
v.edclrstate := spill;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrdsa =>
if vrxwrite = '1' then
v.edclrstate := wrsa; swap := '1';
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl - 2;
if (r.emacaddr(15 downto 0) /= rxo.dataout(31 downto 16)) and
(X"FFFF" /= rxo.dataout(31 downto 16)) then
v.edclrstate := spill;
elsif (X"FFFF" = rxo.dataout(31 downto 16)) then
v.edclbcast := r.edclbcast;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrsa =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.edclrstate := wrtype; swap := '1';
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 3;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrtype =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if X"0800" = rxo.dataout(31 downto 16) and (r.edclbcast = '0') then
v.edclrstate := ip;
elsif X"0806" = rxo.dataout(31 downto 16) and (r.edclbcast = '1') then
v.edclrstate := arp;
else
v.edclrstate := spill;
end if;
end if;
v.ecnt := (others => '0'); v.ipcrc := (others => '0');
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ip =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 1 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 2;
when 2 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl - 1;
when 3 =>
v.rcntm := r.rcntm - 1; v.rcntl := r.rcntl + 2;
when 4 =>
v.udpsrc := rxo.dataout(15 downto 0);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 1;
when 5 =>
setmz := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 6 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 7 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if (rxo.dataout(31 downto 18) = r.seq) then
v.nak := '0';
else
v.nak := '1';
veri.datain(31 downto 18) := r.seq;
end if;
veri.datain(17) := v.nak; v.ewr := rxo.dataout(17);
if (rxo.dataout(17) or v.nak) = '1' then
veri.datain(16 downto 7) := (others => '0');
end if;
v.oplen := rxo.dataout(16 downto 7);
v.applength := "000000" & veri.datain(16 downto 7);
v.ipcrc :=
crcadder(v.applength + 38, r.ipcrc);
v.write(conv_integer(r.rpnt)) := rxo.dataout(17);
when 8 =>
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc :=
crcadder(ipcrctmp, ipcrctmp2);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
v.edclrstate := ipdata;
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ipdata =>
if (vrxwrite and r.ewr and not r.nak) = '1' and
(r.rcntm /= ebufmax) then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
end if;
if rxdone = '1' then
v.edclrstate := ipcrc; v.rcntm := conv_std_logic_vector(6, bpbits);
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc := crcadder(ipcrctmp, ipcrctmp2);
if conv_integer(v.rxstatus(3 downto 0)) /= 0 then
v.edclrstate := idle;
end if;
end if;
when ipcrc =>
veri.writem := '1'; veri.datain(31 downto 16) := not r.ipcrc(15 downto 0);
v.edclrstate := udp; v.rcntm := conv_std_logic_vector(9, bpbits);
v.rcntl := conv_std_logic_vector(9, bpbits);
when udp =>
veri.writem := '1'; veri.writel := '1';
v.edclrstate := iplength;
veri.datain(31 downto 16) := r.udpsrc;
veri.datain(15 downto 0) := r.applength + 18;
v.rcntm := conv_std_logic_vector(4, bpbits);
when iplength =>
veri.writem := '1';
veri.datain(31 downto 16) := r.applength + 38;
v.edclrstate := oplength;
v.rcntm := conv_std_logic_vector(10, bpbits);
v.rcntl := conv_std_logic_vector(10, bpbits);
when oplength =>
if rxstart = '0' then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
veri.writel := '1'; veri.writem := '1';
end if;
if r.nak = '0' then
v.seq := r.seq + 1;
end if;
v.edclrstate := idle;
veri.datain(31 downto 0) := (others => '0');
veri.datain(15 downto 0) := "00000" & r.nak & r.oplen;
when arp =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.rcntm := r.rcntm + 4;
when 1 =>
swap := '1'; veri.writel := '0';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 4;
when 2 =>
swap := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 3 =>
swap := '1';
v.rcntm := r.rcntm - 4; v.rcntl := r.rcntl - 4;
when 4 =>
veri.datain := r.emacaddr(31 downto 16) & r.emacaddr(47 downto 32);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 5 =>
v.rcntl := r.rcntl + 1;
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := r.emacaddr(15 downto 0);
if rxo.dataout(15 downto 0) /= r.edclip(31 downto 16) then
v.edclrstate := spill;
end if;
when 6 =>
swap := '1'; veri.writem := '0';
v.rcntm := conv_std_logic_vector(5, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
if rxo.dataout(31 downto 16) /= r.edclip(15 downto 0) then
v.edclrstate := spill;
else
v.edclactive := '1';
end if;
when 7 =>
veri.writem := '0';
veri.datain(15 downto 0) := r.emacaddr(47 downto 32);
v.rcntl := r.rcntl + 1;
v.rcntm := conv_std_logic_vector(2, bpbits);
when 8 =>
v.edclrstate := arpop;
veri.datain := r.emacaddr(31 downto 0);
v.rcntm := conv_std_logic_vector(5, bpbits);
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when arpop =>
veri.writem := '1'; veri.datain(31 downto 16) := X"0002";
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
if conv_integer(v.rxstatus) = 0 and (rxo.gotframe = '1') then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
end if;
end if;
when spill =>
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
end case;
--edcl transmitter
case r.txdstate is
when getlen =>
v.tcnt := r.tcnt + 1;
if conv_integer(r.tcnt) = 10 then
v.txlength := '0' & erdata(9 downto 0);
v.tnak := erdata(10);
v.txcnt := v.txlength;
if (r.write(conv_integer(r.tpnt)) or v.tnak) = '1' then
v.txlength := (others => '0');
end if;
end if;
if conv_integer(r.tcnt) = 11 then
v.txdstate := readhdr;
v.tcnt := (others => '0');
end if;
when readhdr =>
v.tcnt := r.tcnt + 1; vtxfi.write := '1';
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := v.tfcnt + 1;
vtxfi.datain := erdata;
if conv_integer(r.tcnt) = 12 then
v.txaddr := erdata(31 downto 2);
end if;
if conv_integer(r.tcnt) = 3 then
if erdata(31 downto 16) = X"0806" then
v.tarp := '1'; v.txlength := conv_std_logic_vector(42, 11);
else
v.tarp := '0'; v.txlength := r.txlength + 52;
end if;
end if;
if r.tarp = '0' then
if conv_integer(r.tcnt) = 12 then
v.txdstate := start;
end if;
else
if conv_integer(r.tcnt) = 10 then
v.txdstate := start;
end if;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when start =>
v.tmsto.addr := r.txaddr & "00";
v.tmsto.write := r.write(conv_integer(r.tpnt));
if (edclsepahbg /= 0) and (edcl /= 0) then
v.tmsto2.addr := r.txaddr & "00";
v.tmsto2.write := r.write(conv_integer(r.tpnt));
end if;
if (conv_integer(r.txcnt) = 0) or (r.tarp or r.tnak) = '1' then
v.txdstate := etdone;
v.txstart_sync := not r.txstart_sync;
v.tmsto.req := '0';
if (edclsepahbg /= 0) and (edcl /= 0) then
v.tmsto2.req := '0';
end if;
elsif r.write(conv_integer(r.tpnt)) = '0' then
v.txdstate := req; v.tedcl := '1';
else
v.txstart_sync := not r.txstart_sync;
v.tedcl := '1';
v.tcnt := r.tcnt + 1;
if (edclsepahbg = 0) or (edcl = 0) or (r.edclsepahb = '0') then
v.tmsto.req := '1'; v.tmsto.data := erdata;
v.txdstate := wrbus1;
else
v.tmsto2.req := '1'; v.tmsto2.data := erdata;
v.txdstate := wrbus2;
end if;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when wrbus1 =>
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) or
((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready or tmsti.error) = '1' then
v.tmsto.data := erdata; v.tcnt := r.tcnt + 1;
v.txcnt := r.txcnt - 4;
if r.tmsto.req = '0' then
v.txdstate := etdone;
end if;
end if;
if tmsti.retry = '1' then
v.tmsto.addr := r.tmsto.addr - 4; v.tmsto.req := '1';
end if;
when wrbus2 =>
if tmsti2.grant = '1' then
v.tmsto2.addr := r.tmsto2.addr + 4;
if ((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) or
((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) then
v.tmsto2.req := '0';
end if;
end if;
if (tmsti2.ready or tmsti2.error) = '1' then
v.tmsto2.data := erdata; v.tcnt := r.tcnt + 1;
v.txcnt := r.txcnt - 4;
if r.tmsto2.req = '0' then
v.txdstate := etdone;
end if;
end if;
if tmsti2.retry = '1' then
v.tmsto2.addr := r.tmsto2.addr - 4; v.tmsto2.req := '1';
end if;
when etdone =>
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
v.abufs := v.abufs - 1; v.tpnt := r.tpnt + 1;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
elsif txrestart = '1' then
v.txdstate := idle;
end if;
when others =>
null;
end case;
if swap = '1' then
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := rxo.dataout(31 downto 16);
end if;
if setmz = '1' then
veri.datain(31 downto 16) := (others => '0');
end if;
if (ramdebug /= 2) or (edcl = 0) or (edcldbgread = '0') then
veri.raddress := r.tpnt & v.tcnt;
end if;
end if;
--edcl duplex mode read
if (rmii = 1) or (edcl /= 0) then
--edcl, gbit link mode check
case r.duplexstate is
when start =>
if (r.ctrl.edcldis = '0' and r.disableduplex = '0') then
v.mdio_ctrl.regadr := r.regaddr; v.init_busy := '1';
v.mdio_ctrl.busy := '1'; v.duplexstate := waitop;
if (r.phywr or r.rstphy) = '1' then
v.mdio_ctrl.write := '1';
else
v.mdio_ctrl.read := '1';
end if;
if r.rstphy = '1' then
v.mdio_ctrl.data := X"9000";
end if;
end if;
when waitop =>
if r.init_busy = '0' then
if r.mdio_ctrl.linkfail = '1' then
v.duplexstate := start;
elsif r.rstphy = '1' then
v.duplexstate := start; v.rstphy := '0';
else
v.duplexstate := nextop;
end if;
end if;
when nextop =>
case r.regaddr is
when "00000" =>
if r.mdio_ctrl.data(15) = '1' then --rst not finished
v.duplexstate := start;
elsif (r.phywr and not r.rstaneg) = '1' then --forced to 10 Mbit HD
v.duplexstate := selmode;
elsif r.mdio_ctrl.data(12) = '0' then --no auto neg
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data := (others => '0');
else
v.duplexstate := start; v.regaddr := "00001";
end if;
if r.rstaneg = '1' then
v.phywr := '0';
end if;
if r.disableduplex = '1' then
v.duplexstate := done; v.mdio_ctrl.busy := '0';
end if;
when "00001" =>
v.ext := r.mdio_ctrl.data(8); --extended status register
v.extcap := r.mdio_ctrl.data(1); --extended register capabilities
v.duplexstate := start;
if r.mdio_ctrl.data(0) = '0' then
--no extended register capabilites, unable to read aneg config
--forcing 10 Mbit
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data := (others => '0');
v.regaddr := (others => '0');
elsif (r.mdio_ctrl.data(8) and not r.rstaneg) = '1' then
--phy gbit capable, disable gbit
v.regaddr := "01001";
elsif r.mdio_ctrl.data(5) = '1' then --auto neg completed
v.regaddr := "00100";
end if;
if r.disableduplex = '1' then
v.duplexstate := done; v.mdio_ctrl.busy := '0';
end if;
when "00100" =>
v.duplexstate := start; v.regaddr := "00101";
v.capbil(4 downto 0) := r.mdio_ctrl.data(9 downto 5);
when "00101" =>
v.duplexstate := selmode;
v.capbil(4 downto 0) :=
r.capbil(4 downto 0) and r.mdio_ctrl.data(9 downto 5);
when "01001" =>
if r.phywr = '0' then
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data(9 downto 8) := (others => '0');
else
v.regaddr := "00000";
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data := X"3300"; v.rstaneg := '1';
end if;
when others =>
null;
end case;
when selmode =>
v.duplexstate := done; v.mdio_ctrl.busy := '0';
if r.phywr = '1' then
v.ctrl.full_duplex := '0'; v.ctrl.speed := '0';
else
sel_op_mode(r.capbil, v.ctrl.speed, v.ctrl.full_duplex);
end if;
when done =>
null;
end case;
-- MDIO Disable
if r.ctrl.edcldis = '1' or r.disableduplex = '1' then
if v.duplexstate /= start then
v.duplexstate := start;
v.mdio_ctrl.regadr := (others => '0');
v.mdio_ctrl.busy := '0';
v.init_busy := '0';
v.mdio_ctrl.write := '0';
v.mdio_ctrl.read := '0';
v.mdio_ctrl.data := X"0000";
end if;
end if;
end if;
--transmitter retry
if tmsti.retry = '1' then
v.tmsto.req := '1'; v.tmsto.addr := r.tmsto.addr - 4;
v.txburstcnt := r.txburstcnt - 1;
end if;
--transmitter AHB error
if tmsti.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then
v.tmsto.req := '0'; v.txdstate := ahberror;
end if;
if (edclsepahbg /= 0) and (edcl /= 0) then
--transmitter retry
if tmsti2.retry = '1' then
v.tmsto2.req := '1'; v.tmsto2.addr := r.tmsto2.addr - 4;
v.txburstcnt := r.txburstcnt - 1;
end if;
--transmitter AHB error
if tmsti2.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then
v.tmsto2.req := '0'; v.txdstate := ahberror;
end if;
end if;
--receiver retry
if rmsti.retry = '1' then
v.rmsto.req := '1'; v.rmsto.addr := r.rmsto.addr - 4;
v.rxburstcnt := r.rxburstcnt - 1;
end if;
------------------------------------------------------------------------------
-- RESET ----------------------------------------------------------------------
-------------------------------------------------------------------------------
if irst = '0' then
v.txdstate := idle; v.rxdstate := idle; v.rfrpnt := (others => '0');
v.tmsto.req := '0'; v.tmsto2.req := '0'; v.rfwpnt := (others => '0');
v.rfcnt := (others => '0');
v.ctrl.txen := '0';
v.txirqgen := '0'; v.ctrl.rxen := '0';
v.txdsel := (others => '0'); v.txstart_sync := '0';
v.txread := (others => '0'); v.txrestart := (others => '0');
v.txdone := (others => '0'); v.txreadack := '0';
v.rxdsel := (others => '0'); v.rxdone := (others => '0');
v.rxdoneold := '0'; v.rxdoneack := '0'; v.rxwriteack := '0';
v.rxstart := (others => '0'); v.rxwrite := (others => '0');
v.status.invaddr := '0'; v.status.toosmall := '0';
v.ctrl.full_duplex := '0'; v.writeok := '1';
if (enable_mdio = 0) or (edcl /= 0) then
v.ctrl.reset := '0';
end if;
if enable_mdint = 1 then
v.status.phystat := '0'; v.ctrl.pstatirqen := '0';
end if;
if (edcl /= 0) then
v.tpnt := (others => '0'); v.rpnt := (others => '0');
v.tcnt := (others => '0'); v.edclactive := '0';
v.tarp := '0'; v.abufs := (others => '0');
v.edclrstate := idle;
v.emacaddr := macaddrt;
end if;
if (rmii = 1) then
v.ctrl.speed := '1';
else
v.ctrl.speed := '1';
end if;
v.ctrl.tx_irqen := '0';
v.ctrl.rx_irqen := '0';
v.ctrl.prom := '0';
if multicast = 1 then
v.ctrl.mcasten := '0';
end if;
if ramdebug /= 0 then
v.ctrl.ramdebugen := '0';
end if;
end if;
if edcl = 0 then
v.edclrstate := idle; v.edclactive := '0'; v.nak := '0'; v.ewr := '0';
v.write := (others => '0'); v.seq := (others => '0'); v.abufs := (others => '0');
v.tpnt := (others => '0'); v.rpnt := (others => '0'); v.tcnt := (others => '0');
v.rcntm := (others => '0'); v.rcntl := (others => '0'); v.ipcrc := (others => '0');
v.applength := (others => '0'); v.oplen := (others => '0');
v.udpsrc := (others => '0'); v.ecnt := (others => '0'); v.tarp := '0';
v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0';
end if;
--some parts of edcl are only affected by hw reset
if rst = '0' then
v.edclip := conv_std_logic_vector(ipaddrh, 16) &
conv_std_logic_vector(ipaddrl, 16);
if edcl > 1 then
v.edclip(3 downto 0) := edcladdr;
v.emacaddr(3 downto 0) := edcladdr;
end if;
v.duplexstate := start; v.regaddr := (others => '0');
v.phywr := '0'; v.rstphy := '1'; v.rstaneg := '0';
if phyrstadr /= 32 then
v.mdio_ctrl.phyadr := conv_std_logic_vector(phyrstadr, 5);
else
v.mdio_ctrl.phyadr := phyrstaddr;
end if;
v.seq := (others => '0');
if (enable_mdio = 1) then
v.mdccnt := divisor; v.mdioclk := '0';
end if;
if edcl /= 0 then
v.disableduplex := '0';
end if;
if edcl = 3 then
v.ctrl.edcldis := edcldisable;
elsif edcl /= 0 then
v.ctrl.edcldis := '0';
end if;
v.ctrl.reset := '0';
if (enable_mdio = 1) then
v.mdio_state := idle; v.mdio_ctrl.read := '0';
v.mdio_ctrl.write := '0'; v.mdio_ctrl.busy := '0';
v.mdio_ctrl.data := (others => '0');
v.mdio_ctrl.regadr := (others => '0');
v.ctrl.reset := '0'; v.mdio_ctrl.linkfail := '1';
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
v.cnt := (others => '0');
end if;
if edclsepahbg /= 0 then
v.edclsepahb := edclsepahb;
end if;
v.txcnt := (others => '0'); v.txburstcnt := (others => '0');
v.tedcl := '0'; v.erenable := '0';
v.rmsto.req := '0'; v.rmsto.write := '0'; v.addrok := '0';
v.rxburstcnt := (others => '0'); v.addrdone := '0';
v.rxcnt := (others => '0'); v.rxdoneold := '0';
v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0';
v.msbgood := '0'; v.rxrenable := '0';
if multicast = 1 then
v.mcast := '0'; v.mcastacc := '0';
end if;
v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0';
v.gotframe := '0';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
v.txburstav := '0'; v.txdataav := '0';
v.txstatus := (others => '0'); v.txstart := '0';
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0'); v.txaddr := (others => '0');
v.cnt := (others => '0');
v.rxaddr := (others => '0');
v.rxstatus := (others => '0');
v.rxwrap := '0'; v.rxden := '0';
v.rmsto.addr := (others => '0');
v.tmsto.addr := (others => '0');
v.nak := '0'; v.ewr := '0';
v.write := (others => '0');
v.applength := (others => '0');
v.oplen := (others => '0');
v.udpsrc := (others => '0'); v.ecnt := (others => '0');
v.rcntm := (others => '0'); v.rcntl := (others => '0');
end if;
-------------------------------------------------------------------------------
-- SIGNAL ASSIGNMENTS ---------------------------------------------------------
-------------------------------------------------------------------------------
rin <= v;
prdata <= vprdata;
irq <= vpirq;
--rx ahb fifo
rxrenable <= vrxfi.renable;
rxraddress(10 downto fabits) <= (others => '0');
rxraddress(fabits-1 downto 0) <= vrxfi.raddress;
rxwrite <= vrxfi.write;
rxwdata <= vrxfi.datain;
rxwaddress(10 downto fabits) <= (others => '0');
rxwaddress(fabits-1 downto 0) <= vrxfi.waddress;
--tx ahb fifo
txrenable <= vtxfi.renable;
txraddress(10 downto txfabits) <= (others => '0');
txraddress(txfabits-1 downto 0) <= vtxfi.raddress;
txwrite <= vtxfi.write;
txwdata <= vtxfi.datain;
txwaddress(10 downto txfabits) <= (others => '0');
txwaddress(txfabits-1 downto 0) <= vtxfi.waddress;
--edcl buf
erenable <= veri.renable;
eraddress(15 downto eabits) <= (others => '0');
eraddress(eabits-1 downto 0) <= veri.raddress;
ewritem <= veri.writem;
ewritel <= veri.writel;
ewaddressm(15 downto eabits) <= (others => '0');
ewaddressm(eabits-1 downto 0) <= veri.waddressm(eabits-1 downto 0);
ewaddressl(15 downto eabits) <= (others => '0');
ewaddressl(eabits-1 downto 0) <= veri.waddressl(eabits-1 downto 0);
ewdata <= veri.datain;
rxi.enable <= vrxenable;
end process;
rxi.writeack <= r.rxwriteack;
rxi.doneack <= r.rxdoneack;
rxi.speed <= r.ctrl.speed;
rxi.writeok <= r.writeok;
rxi.rxd <= rxd;
rxi.rx_dv <= rx_dv;
rxi.rx_crs <= rx_crs;
rxi.rx_er <= rx_er;
rxi.rx_en <= rx_en;
txi.rx_col <= rx_col;
txi.rx_crs <= rx_crs;
txi.full_duplex <= r.ctrl.full_duplex;
txi.start <= r.txstart_sync;
txi.readack <= r.txreadack;
txi.speed <= r.ctrl.speed;
txi.data <= r.txdata;
txi.valid <= r.txvalid;
txi.len <= r.txlength;
txi.datavalid <= tx_dv;
mdc <= r.mdioclk;
mdio_o <= r.mdioo;
mdio_oe <= testoen when (scanen/=0 and testen/='0') else r.mdioen;
tmsto <= r.tmsto;
rmsto <= r.rmsto;
tmsto2 <= r.tmsto2;
txd <= txo.txd;
tx_en <= txo.tx_en;
tx_er <= txo.tx_er;
ahbmi.hgrant <= hgrant;
ahbmi.hready <= hready;
ahbmi.hresp <= hresp;
ahbmi.hrdata <= hrdata;
hbusreq <= ahbmo.hbusreq;
hlock <= ahbmo.hlock;
htrans <= ahbmo.htrans;
haddr <= ahbmo.haddr;
hwrite <= ahbmo.hwrite;
hsize <= ahbmo.hsize;
hburst <= ahbmo.hburst;
hprot <= ahbmo.hprot;
hwdata <= ahbmo.hwdata;
ahbmi2.hgrant <= ehgrant;
ahbmi2.hready <= ehready;
ahbmi2.hresp <= ehresp;
ahbmi2.hrdata <= ehrdata;
ehbusreq <= ahbmo2.hbusreq;
ehlock <= ahbmo2.hlock;
ehtrans <= ahbmo2.htrans;
ehaddr <= ahbmo2.haddr;
ehwrite <= ahbmo2.hwrite;
ehsize <= ahbmo2.hsize;
ehburst <= ahbmo2.hburst;
ehprot <= ahbmo2.hprot;
ehwdata <= ahbmo2.hwdata;
speed <= r.ctrl.speed;
reset <= irst;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-------------------------------------------------------------------------------
-- TRANSMITTER-----------------------------------------------------------------
-------------------------------------------------------------------------------
tx_rmii0 : if rmii = 0 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => tx_clk,
txi => txi,
txo => txo);
end generate;
tx_rmii1 : if rmii = 1 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => rmii_clk,
txi => txi,
txo => txo);
end generate;
-------------------------------------------------------------------------------
-- RECEIVER -------------------------------------------------------------------
-------------------------------------------------------------------------------
rx_rmii0 : if rmii = 0 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii,
multicast => multicast,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => rx_clk,
rxi => rxi,
rxo => rxo);
end generate;
rx_rmii1 : if rmii = 1 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii,
multicast => multicast,
maxsize => maxsize,
gmiimode => gmiimode)
port map(
rst => arst,
clk => rmii_clk,
rxi => rxi,
rxo => rxo);
end generate;
-------------------------------------------------------------------------------
-- AHB MST INTERFACE ----------------------------------------------------------
-------------------------------------------------------------------------------
ahb0 : eth_ahb_mst
port map(rst, clk, ahbmi, ahbmo, tmsto, tmsti, rmsto, rmsti);
edclmst : if edclsepahbg = 1 generate
ahb1 : eth_edcl_ahb_mst
port map(rst, clk, ahbmi2, ahbmo2, tmsto2, tmsti2);
end generate;
end architecture;
|
entity sub is
generic ( n : natural );
end entity;
architecture test of sub is
function get_n return integer is
begin
return n;
end function;
constant x : natural := get_n;
begin
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
architecture test of top is
begin
sub_1: entity work.sub generic map ( 5 );
sub_2: entity work.sub generic map ( 10 );
end architecture;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file addsb_11_0_3537d66a2361cd1e.vhd when simulating
-- the core, addsb_11_0_3537d66a2361cd1e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY addsb_11_0_3537d66a2361cd1e IS
PORT (
a : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END addsb_11_0_3537d66a2361cd1e;
ARCHITECTURE addsb_11_0_3537d66a2361cd1e_a OF addsb_11_0_3537d66a2361cd1e IS
-- synthesis translate_off
COMPONENT wrapped_addsb_11_0_3537d66a2361cd1e
PORT (
a : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_addsb_11_0_3537d66a2361cd1e USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 26,
c_add_mode => 0,
c_ainit_val => "0",
c_b_constant => 0,
c_b_type => 0,
c_b_value => "00000000000000000000000000",
c_b_width => 26,
c_borrow_low => 1,
c_bypass_low => 0,
c_ce_overrides_bypass => 1,
c_ce_overrides_sclr => 0,
c_has_bypass => 0,
c_has_c_in => 0,
c_has_c_out => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_implementation => 0,
c_latency => 0,
c_out_width => 26,
c_sclr_overrides_sset => 0,
c_sinit_val => "0",
c_verbosity => 0,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_addsb_11_0_3537d66a2361cd1e
PORT MAP (
a => a,
b => b,
s => s
);
-- synthesis translate_on
END addsb_11_0_3537d66a2361cd1e_a;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/05/2017 02:01:44 PM
-- Design Name:
-- Module Name: game_logic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity game_logic is
port(
clk : in STD_LOGIC;
usb_bt_clk : in STD_LOGIC;
save_button_input : in STD_LOGIC;
keyboard_input : in STD_LOGIC_VECTOR(7 downto 0);
x_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
y_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
usb_bt_input : in STD_LOGIC_VECTOR(7 downto 0);
reset_output : out STD_LOGIC;
screen_size_output : out STD_LOGIC;
pen_width_output : out STD_LOGIC_VECTOR(2 downto 0);
x_pos_output : out STD_LOGIC_VECTOR(7 downto 0);
y_pos_output : out STD_LOGIC_VECTOR(7 downto 0);
tricolor_led_output : out STD_LOGIC_VECTOR(11 downto 0);
usb_bt_output : out STD_LOGIC_VECTOR(15 downto 0);
color_output : out STD_LOGIC_VECTOR(23 downto 0);
ram_we_output : out STD_LOGIC_VECTOR(0 downto 0);
ram_val_output : out STD_LOGIC_VECTOR(11 downto 0);
ram_addr_output : out STD_LOGIC_VECTOR(16 downto 0)
);
end game_logic;
architecture Behavioral of game_logic is
-- Font ROM component
component font_rom is
port(
clk : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR(10 downto 0);
data : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
-- RAM clock divider component
component clock_divider is
generic(count_max : INTEGER := 8); -- FIX THIS?
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_output : out STD_LOGIC
);
end component;
-- System properties
signal pc_connected : STD_LOGIC := '0';
signal screen_size : STD_LOGIC := '0';
signal reset : STD_LOGIC := '0';
signal pen_width : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal ascii_char : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal color : STD_LOGIC_VECTOR(23 downto 0) := x"000000";
--USB/bluetooth control send signals
signal prev_screen_size : STD_LOGIC := '0';
signal prev_save : STD_LOGIC := '0';
signal prev_reset : STD_LOGIC := '0';
signal prev_pen_width : STD_LOGIC_VECTOR(2 downto 0):= "000";
signal prev_ascii_char : STD_LOGIC_VECTOR(7 downto 0):= x"00";
signal prev_x_pos, prev_y_pos : STD_LOGIC_VECTOR(7 downto 0):= x"00";
signal prev_color : STD_LOGIC_VECTOR(23 downto 0):= x"000000";
--USB/Bluetooth control receive signals
signal prev_connections : STD_LOGIC_VECTOR(7 downto 0);
-- Keyboard control signals
signal num_values_input : INTEGER := 0;
signal prev_pc_connected : STD_LOGIC := '0';
signal changing_item : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [color, pen_width, screen_size]
signal hex_input : STD_LOGIC_VECTOR(3 downto 0) := x"0";
signal temp_hex_input : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal input_values : STD_LOGIC_VECTOR(23 downto 0) := x"000000";
-- Font Rom signals
signal font_rom_addr : UNSIGNED(10 downto 0) := x"00" & "000";
signal font_rom_data : STD_LOGIC_VECTOR(7 downto 0) := x"00";
-- RAM clock divider signals
signal ram_divider_counter : INTEGER := 0;
signal ram_clk : STD_LOGIC := '0';
-- RAM Signals
signal x_pos_int : INTEGER := 0;
signal y_pos_int : INTEGER := 0;
-- RAM fast update signals
signal ram_update_count : INTEGER := 0;
signal ram_update_x_count : INTEGER := 0;
signal ram_update_y_count : INTEGER := 0;
signal ram_update_slow_int : INTEGER := 0;
signal ram_update : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [pos, sys_text, user_text]
signal ram_update_slow : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal ram_update_pos_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal ram_update_sys_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal ram_update_user_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
-- RAM slow control signals
signal x_addr_count, y_addr_count : INTEGER := 0;
-- RAM reset signals
signal ram_reset : STD_LOGIC := '0';
signal ram_reset_slow : STD_LOGIC := '0';
signal ram_reset_count : UNSIGNED(15 downto 0) := x"0000";
signal prev_ram_resets : STD_LOGIC_VECTOR(7 downto 0) := x"00";
begin
screen_size_output <= screen_size;
pen_width_output <= pen_width;
x_pos_output <= x_pos_input;
y_pos_output <= y_pos_input;
tricolor_led_output <= color(11 downto 0);
color_output <= color;
ram_we_output <= "1";
--ram_we_output <= "0";
reset_output <= reset;
-- Previous signal generation process
process(clk)
begin
prev_pc_connected <= pc_connected;
prev_x_pos <= x_pos_input;
prev_y_pos <= y_pos_input;
prev_color <= color;
prev_ascii_char <= ascii_char;
prev_screen_size <= screen_size;
prev_pen_width <= pen_width;
prev_save <= save_button_input;
prev_reset <= reset;
end process;
-- USB/Bluetooth control process
process(clk, usb_bt_clk, prev_x_pos, prev_y_pos) -- FIX THIS (add update method)
begin
-- Sending Data
if rising_edge(clk) then
if reset /= prev_reset then
usb_bt_output(15 downto 12) <= "1111";
usb_bt_output(1) <= save_button_input;
usb_bt_output(0) <= reset;
elsif prev_x_pos /= x_pos_input then
usb_bt_output(15 downto 14) <= "10";
usb_bt_output(8) <= '0';
usb_bt_output(7 downto 0) <= x_pos_input;
elsif prev_y_pos /= y_pos_input then
usb_bt_output(15 downto 14) <= "10";
usb_bt_output(8) <= '1';
usb_bt_output(7 downto 0) <= y_pos_input;
elsif prev_color /= color then
usb_bt_output(15 downto 12) <= "1100";
usb_bt_output(11 downto 0) <= color(11 downto 0); -- change to 24 bit?
elsif prev_screen_size /= screen_size or prev_pen_width /= pen_width then
usb_bt_output(15 downto 12) <= "1110";
usb_bt_output(3) <= screen_size;
usb_bt_output(2 downto 0) <= pen_width;
elsif prev_ascii_char /= ascii_char then
usb_bt_output(15 downto 12) <= "1101";
usb_bt_output(7 downto 0) <= ascii_char;
elsif prev_save /= save_button_input then
usb_bt_output(15 downto 12) <= "1111";
usb_bt_output(1) <= save_button_input;
usb_bt_output(0) <= reset;
else
usb_bt_output <= x"0000";
end if;
end if;
-- Recieving Data
if rising_edge(usb_bt_clk) then
prev_connections <= prev_connections(6 downto 0) & usb_bt_input(0);
if prev_connections = x"00" then
pc_connected <= '0';
else
pc_connected <= '1';
end if;
end if;
end process;
-- Keyboard control process
hex_input <= temp_hex_input(3 downto 0);
process(clk)
begin
-- Keyboard control
if rising_edge(clk) then
if reset = '0' then
if keyboard_input = x"77" and changing_item = "000" then -- input w and changing color
ascii_char <= x"77";
changing_item <= "100";
num_values_input <= 1;
elsif keyboard_input = x"63" and changing_item = "000" then -- input c and changing pen_width
ascii_char <= x"63";
changing_item <= "010";
num_values_input <= 1;
elsif keyboard_input = x"73" and changing_item = "000" then -- input s and changing screen_size
ascii_char <= x"73";
changing_item <= "001";
num_values_input <= 1;
elsif keyboard_input = x"72" and changing_item = "000" then -- input r
reset <= '1';
color <= x"FFFFFF";
pen_width <= "000";
screen_size <= '0';
elsif keyboard_input = x"71" and changing_item /= "000" then -- input q and exit command
ascii_char <= x"71";
-- FIX THIS
elsif keyboard_input = x"08" and num_values_input = 1 then -- input backspace
ascii_char <= x"08";
num_values_input <= 0;
changing_item <= "000";
elsif changing_item /= "000" then
-- Ascii to hex converter
if (keyboard_input >= x"30" and keyboard_input <= x"39") then
temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"30");
elsif (keyboard_input >= x"61" and keyboard_input <= x"66") then
temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"57");
else
temp_hex_input <= x"FF";
end if;
-- User keyboard input restrictions
if changing_item = "100" and hex_input <= x"F" then -- Limit color
input_values(((num_values_input * 4)-1) downto ((num_values_input-1) * 4)) <= hex_input;
num_values_input <= num_values_input + 1;
elsif changing_item = "010" and hex_input >= x"1" and hex_input <= x"7" then -- Limit pen_width
input_values(3 downto 0) <= hex_input;
num_values_input <= num_values_input + 1;
elsif changing_item = "001" and hex_input <= x"1" then -- Limit screen_size
input_values(3 downto 0) <= hex_input;
num_values_input <= num_values_input + 1;
end if;
elsif keyboard_input = x"0A" then -- input enter
ascii_char <= x"0A";
if changing_item = "100" and num_values_input = 7 then -- new color
color <= input_values;
changing_item <= "000";
elsif changing_item = "010" and num_values_input = 1 then -- new pen_width
pen_width <= input_values(2 downto 0);
changing_item <= "000";
elsif changing_item = "001" and num_values_input = 1 then -- new screen_size
screen_size <= input_values(0);
changing_item <= "000";
end if;
end if;
end if;
-- Reset handling
if reset = '1' and prev_reset = '1' and ram_reset = '0' then
reset <= '0';
color <= x"000000";
end if;
end if;
end process;
-- Font ROM port map
ram_font_rom : font_rom
port map(
clk => clk,
addr => std_logic_vector(font_rom_addr),
data => font_rom_data
);
-- RAM clock divider port map
ram_clock_divider : clock_divider
generic map(count_max => 2) -- CHANGE VALUE
port map(
clk => clk,
reset => '0',
clk_output => ram_clk
);
x_pos_int <= to_integer(unsigned(x_pos_input));
y_pos_int <= to_integer(unsigned(y_pos_input));
-- RAM control process
process(clk, ram_clk)
begin
-- When to update RAM
if rising_edge(clk) then
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
if (x_pos_input /= prev_x_pos or y_pos_input /= prev_y_pos) then
ram_update(2) <= '1'; -- pos
ram_update_slow_int <= 1;
-- elsif (color /= prev_color or pen_width /= prev_pen_width
-- or pc_connected /= prev_pc_connected) then
-- ram_update(1) <= '1'; -- sys_text
-- elsif (ascii_char /= prev_ascii_char) then
-- ram_update(0) <= '1'; -- user_text
end if;
if ram_update_slow_int = std_logic_vector(to_unsigned(2048, 17)) then
ram_update_slow_int <= 0;
elsif ram_update_slow_int > 0 then
ram_update_slow_int <= ram_update_slow_int + 1;
ram_update(2) <= '1';
else
ram_update(2) <= '0';
end if;
-- if ram_update_pos_slow = x"00" then
-- ram_update(2) <= '0';
-- end if;
-- if ram_update_sys_text_slow = x"00" then
-- ram_update(1) <= '0';
-- end if;
-- if ram_update_user_text_slow = x"00" then
-- ram_update(0) <= '0';
-- end if;
-- if reset = '1' and ram_reset = '0' then
-- ram_reset <= '1';
-- prev_ram_resets <= prev_ram_resets(6 downto 0) & ram_reset;
-- end if;
--
-- if ram_reset_slow = '0' and prev_ram_resets = x"FF" then
-- ram_reset <= '0';
-- end if;
-- end if;
-- Draw to RAM
--if rising_edge(ram_clk) then
--if rising_edge(clk) then
--if ram_reset = '0' then
if ram_update(2) = '1' then -- pos
--if(true) then
--ram_we_output <= "1";
ram_val_output <= color(23 downto 20) & color(15 downto 12) & color(7 downto 4);
--ram_update_slow(2) <= '1';
--ram_update(2) <= '0';
-- if (y_addr_count < unsigned(pen_width)) and
-- ((y_pos_int + y_addr_count) < 256) and
-- ((y_pos_int + y_addr_count) >= 0) then
-- if (x_addr_count < unsigned(pen_width)) and
-- ((x_pos_int + x_addr_count) < 256) and
-- ((x_pos_int + x_addr_count) >= 0) then
ram_addr_output <= std_logic_vector(to_unsigned( ((x_pos_int+x_addr_count) + ((y_pos_int+y_addr_count) * 256)) , 17));
else
ram_val_output <= x"F00";
ram_addr_output <= std_logic_vector(to_unsigned(66666, 17));
--ram_update(2) <= '1';
-- else
-- x_addr_count <= 0;
-- end if;
-- y_addr_count <= y_addr_count + 1;
-- else
-- y_addr_count <= 0;
-- end if;
--elsif prev_x_pos /= x_pos_input and prev_y_pos /= y_pos_input then --Not needed?
--ram_update(1) <= '0';
--ram_we_output <= "0"; --Not needed?
--ram_update(2) <= '0'; --Not needed?
-- elsif ram_update(2 downto 1) = "01" then -- sys_text
-- ram_update_slow(2 downto 1) <= "01";
-- if ram_update_count < 3 then
-- if ram_update_y_count < 16 then
-- if ram_update_x_count < 8 then
-- if ram_update_count = 1 then -- Update color
-- ram_addr_output <= std_logic_vector(to_unsigned(65618 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- ram_val_output <= color(11 downto 0);
-- elsif ram_update_count = 2 then -- Update pen_width
-- ram_addr_output <= std_logic_vector(to_unsigned(65768 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= "000" & (x"30" + unsigned("0000" & pen_width)); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- else -- Update pc_connnection
-- ram_addr_output <= std_logic_vector(to_unsigned(65888 + ram_update_x_count
-- + (ram_update_count * 10)
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= "00" & (x"30" + "0000000" & pc_connected); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- end if;
-- ram_update_x_count <= ram_update_x_count + 1;
-- else
-- ram_update_x_count <= 0;
-- end if;
-- ram_update_y_count <= ram_update_x_count + 1;
-- else
-- ram_update_y_count <= 0;
-- end if;
-- ram_update_count <= ram_update_count + 1;
-- else
-- ram_update_slow(1) <= '0';
-- ram_update_count <= 0;
-- end if;
-- elsif ram_update = "001" then -- user_text
-- ram_update_slow <= "001";
-- if ram_update_count < 8 then
-- if ram_update_y_count < 16 then
-- if ram_update_x_count < 8 then
-- ram_addr_output <= std_logic_vector(to_unsigned(66102 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= unsigned("000" & ascii_char); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- ram_update_x_count <= ram_update_x_count + 1;
-- else
-- ram_update_x_count <= 0;
-- end if;
-- ram_update_y_count <= ram_update_x_count + 1;
-- else
-- ram_update_y_count <= 0;
-- end if;
-- ram_update_count <= ram_update_count + 1;
-- else
-- ram_update_slow(0) <= '0';
-- ram_update_count <= 0;
-- end if;
-- else
-- ram_update_slow <= "000";
--end if;
---- else -- ram_reset = 1
---- -- Drawing Screen (sys_text and user_text update automatically)
---- if ram_reset_count < 65536 then
---- ram_reset_slow <= '1';
---- ram_reset_count <= ram_reset_count + 1;
---- ram_addr_output <= "0" & std_logic_vector(ram_reset_count);
---- else
---- ram_reset_slow <= '0';
---- ram_reset_count <= x"0000";
---- end if;
end if;
end if;
end process;
end Behavioral;
|
use ieee.std_logic.1164;
use ieee.std_logic.1164, ieee.std_logic_arith.all;
use ieee.std_logic."ceil";
use ieee.std_logic."ceil", ieee.std_logic."ceil";
|
-- AHB ROM
constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
|
-- AHB ROM
constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
|
-- AHB ROM
constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
|
-- AHB ROM
constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
|
-- AHB ROM
constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
|
-- AHB ROM
constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
|
library ieee;
use ieee.std_logic_1164.all;
entity e is
port (
clk : in std_logic;
rst : in std_logic;
q : out std_logic);
end e;
architecture a of e is
signal r : std_logic;
function invert (
i : std_logic)
return std_logic is
begin
return not i;
end invert;
begin
q <= r;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
r <= '0';
else
r <= invert(r);
end if;
end if;
end process;
end a;
|
library ieee;
use ieee.std_logic_1164.all;
entity e is
port (
clk : in std_logic;
rst : in std_logic;
q : out std_logic);
end e;
architecture a of e is
signal r : std_logic;
function invert (
i : std_logic)
return std_logic is
begin
return not i;
end invert;
begin
q <= r;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
r <= '0';
else
r <= invert(r);
end if;
end if;
end process;
end a;
|
library ieee;
use ieee.std_logic_1164.all;
entity e is
port (
clk : in std_logic;
rst : in std_logic;
q : out std_logic);
end e;
architecture a of e is
signal r : std_logic;
function invert (
i : std_logic)
return std_logic is
begin
return not i;
end invert;
begin
q <= r;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
r <= '0';
else
r <= invert(r);
end if;
end if;
end process;
end a;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity id is
port(
clk: in std_logic;
res: in std_logic;
instr_opcode: in std_logic_vector(7 downto 0);
flag: in std_logic;
ack: in std_logic;
int: in std_logic;
swirq: out std_logic;
we: out std_logic;
oe: out std_logic;
int_accept: out std_logic;
int_completed: out std_logic;
data_c_sel: out std_logic_vector(2 downto 0);
data_a_sel: out std_logic_vector(3 downto 0);
data_b_sel: out std_logic_vector(2 downto 0);
force_we_reg_14: out std_logic;
inc_r14: out std_logic;
inc_r15: out std_logic;
dec_r15: out std_logic;
instruction_we: out std_logic;
regfile_c_we: out std_logic
);
end entity id;
architecture id_arch of id is
type id_state_type is (
start, start_inc, start_inc_intcmp, start_dec, start_wait, start_decode, start_calli, start_call,
intrq, intrq_set, intrq_inc, intrq_inc_set, intrq_dec, intrq_dec_set, intrq_calli, intrq_call,
ret, reti, swi,
call, calli,
pop, push,
ld, ldi, st, sti,
bz_bnz_set, bzi_bnzi_set,
mvil, mvih, mvia, barrel, alu,
cmp,
div, div_w0, div_w1, div_w2, div_w3, div_w4, div_w5, div_w6, div_w7,
div_w8, div_w9, div_w10, div_w11, div_w12, div_w13, div_w14, div_done,
faddsub, faddsub_done,
fdiv, fdiv_w0, fdiv_w1, fdiv_w2, fdiv_w3, fdiv_w4, fdiv_w5, fdiv_w6, fdiv_done,
fmul, fmul_w0, fmul_done
);
signal id_state: id_state_type;
constant data_a_arg_mvia: std_logic_vector(3 downto 0) := "0000";
constant data_a_arg_branch: std_logic_vector(3 downto 0) := "0001";
constant data_a_arg_st: std_logic_vector(3 downto 0) := "0010";
constant data_a_arg_mvi: std_logic_vector(3 downto 0) := "0011";
constant data_a_int_addr: std_logic_vector(3 downto 0) := "0100";
constant data_a_pc: std_logic_vector(3 downto 0) := "0101";
constant data_a_sp: std_logic_vector(3 downto 0) := "0110";
constant data_a_sp_plus: std_logic_vector(3 downto 0) := "0111";
constant data_a_sp_minus: std_logic_vector(3 downto 0) := "1000";
constant data_a_regfile: std_logic_vector(3 downto 0) := "1001";
constant data_b_regfile: std_logic_vector(2 downto 0) := "000";
constant data_b_regfile_a: std_logic_vector(2 downto 0) := "001";
constant data_b_pc: std_logic_vector(2 downto 0) := "010";
constant data_b_arg_call: std_logic_vector(2 downto 0) := "011";
constant data_b_reg0: std_logic_vector(2 downto 0) := "100";
constant data_c_fpu: std_logic_vector(2 downto 0) := "000";
constant data_c_cmp: std_logic_vector(2 downto 0) := "001";
constant data_c_alu: std_logic_vector(2 downto 0) := "010";
constant data_c_barrel: std_logic_vector(2 downto 0) := "011";
constant data_c_miso: std_logic_vector(2 downto 0) := "100";
constant data_c_mvil: std_logic_vector(2 downto 0) := "101";
constant data_c_mvih: std_logic_vector(2 downto 0) := "110";
constant data_c_aorb: std_logic_vector(2 downto 0) := "111";
constant data_a_dontcare: std_logic_vector(3 downto 0) := "----";
constant data_b_dontcare: std_logic_vector(2 downto 0) := "---";
constant data_c_dontcare: std_logic_vector(2 downto 0) := "---";
begin
decoder: process(clk) is
begin
if rising_edge(clk) then
if res = '1' then
id_state <= start;
else
case id_state is
when start =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_inc =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_calli =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_call =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_inc_intcmp =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_dec =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_wait =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_decode =>
case instr_opcode(7) is
when '1' =>
case instr_opcode(6 downto 4) is
when "000" => id_state <= call;
when "001" => id_state <= ld;
when "010" => id_state <= st;
when "011" =>
case flag is
when '1' => id_state <= bz_bnz_set;
when others =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
when "100" =>
case flag is
when '0' => id_state <= bz_bnz_set;
when others =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
when "101" => id_state <= mvia;
when others => id_state <= start;
end case;
when others =>
case instr_opcode(4 downto 0) is
when "00001" => id_state <= ret;
when "00010" => id_state <= reti;
when "00011" => id_state <= calli;
when "00100" => id_state <= push;
when "00101" => id_state <= pop;
when "00110" => id_state <= ldi;
when "00111" => id_state <= sti;
when "01000" =>
case flag is
when '0' => id_state <= bzi_bnzi_set;
when others =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
when "01001" =>
case flag is
when '1' => id_state <= bzi_bnzi_set;
when others =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
when "01010" => id_state <= cmp;
when "01011" => id_state <= cmp;
when "01100" => id_state <= alu;
when "01101" => id_state <= div;
when "01110" => id_state <= barrel;
when "01111" => id_state <= faddsub;
when "10000" => id_state <= fmul;
when "10001" => id_state <= fdiv;
when "10010" => id_state <= mvil;
when "10011" => id_state <= mvih;
when "10100" => id_state <= swi;
when others => id_state <= start;
end case;
end case;
when intrq =>
case ack is
when '1' => id_state <= intrq_set;
when others => id_state <= intrq;
end case;
when intrq_set =>
id_state <= start;
when intrq_calli =>
case ack is
when '1' => id_state <= intrq_set;
when others => id_state <= intrq_calli;
end case;
when intrq_call =>
case ack is
when '1' => id_state <= intrq_set;
when others => id_state <= intrq_call;
end case;
when intrq_inc =>
case ack is
when '1' => id_state <= intrq_inc_set;
when others => id_state <= intrq_inc;
end case;
when intrq_inc_set =>
id_state <= start_inc;
when intrq_dec =>
case ack is
when '1' => id_state <= intrq_dec_set;
when others => id_state <= intrq_dec;
end case;
when intrq_dec_set =>
id_state <= start;
when ret =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_inc;
when others => id_state <= start_inc;
end case;
when others => id_state <= ret;
end case;
when reti =>
case ack is
when '1' => id_state <= start_inc_intcmp;
when others => id_state <= reti;
end case;
when call =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_call;
when others => id_state <= start_call;
end case;
when others => id_state <= call;
end case;
when calli =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_calli;
when others => id_state <= start_calli;
end case;
when others => id_state <= calli;
end case;
when pop =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_inc;
when others => id_state <= start_inc;
end case;
when others => id_state <= pop;
end case;
when push =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_dec;
when others => id_state <= start_dec;
end case;
when others => id_state <= push;
end case;
when ld =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when others => id_state <= ld;
end case;
when ldi =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when others => id_state <= ldi;
end case;
when st =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when others => id_state <= st;
end case;
when sti =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when others => id_state <= sti;
end case;
when bz_bnz_set =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when bzi_bnzi_set =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when mvil =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when mvih =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when mvia =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when barrel =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when alu =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when cmp =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when div => id_state <= div_w0;
when div_w0 => id_state <= div_w1;
when div_w1 => id_state <= div_w2;
when div_w2 => id_state <= div_w3;
when div_w3 => id_state <= div_w4;
when div_w4 => id_state <= div_w5;
when div_w5 => id_state <= div_w6;
when div_w6 => id_state <= div_w7;
when div_w7 => id_state <= div_w8;
when div_w8 => id_state <= div_w9;
when div_w9 => id_state <= div_w10;
when div_w10 => id_state <= div_w11;
when div_w11 => id_state <= div_w12;
when div_w12 => id_state <= div_w13;
when div_w13 => id_state <= div_w14;
when div_w14 => id_state <= div_done;
when div_done =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when faddsub => id_state <= faddsub_done;
when faddsub_done =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when fmul => id_state <= fmul_w0;
when fmul_w0 => id_state <= fmul_done;
when fmul_done =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when fdiv => id_state <= fdiv_w0;
when fdiv_w0 => id_state <= fdiv_w1;
when fdiv_w1 => id_state <= fdiv_w2;
when fdiv_w2 => id_state <= fdiv_w3;
when fdiv_w3 => id_state <= fdiv_w4;
when fdiv_w4 => id_state <= fdiv_w5;
when fdiv_w5 => id_state <= fdiv_w6;
when fdiv_w6 => id_state <= fdiv_done;
when fdiv_done =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when swi =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
end if;
end if;
end process;
outputs: process(id_state) is begin
case id_state is
when start =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_inc =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '1'; dec_r15 <= '0';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_inc_intcmp =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '1';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '1'; dec_r15 <= '0';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_dec =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_wait =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_decode =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '1'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_dontcare;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_calli =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when start_call =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_arg_mvia;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when ret =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_plus;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '0';
when reti =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_plus;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '0';
when call =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when calli =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when pop =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_plus;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '1';
when push =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when ld =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_mvia;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '1';
when ldi =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '1';
when st =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_st;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when sti =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when bz_bnz_set =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_branch;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when bzi_bnzi_set =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when mvil =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_mvi;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_mvil;
regfile_c_we <= '1';
when mvih =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_mvi;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_mvih;
regfile_c_we <= '1';
when mvia =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_mvia;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '1';
when barrel =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_barrel;
regfile_c_we <= '1';
when alu =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '1';
when cmp =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_cmp;
regfile_c_we <= '1';
when div =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w0 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w1 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w2 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w3 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w4 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w5 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w6 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w7 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w8 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w9 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w10 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w11 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w12 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w13 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w14 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_done =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '1';
when faddsub =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when faddsub_done =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '1';
when fdiv =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w0 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w1 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w2 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w3 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w4 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w5 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w6 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_done =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '1';
when fmul =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fmul_w0 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fmul_done =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '1';
when intrq =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when intrq_set =>
we <= '0'; oe <= '0'; int_accept <= '1'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_int_addr;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when intrq_inc =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_plus;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when intrq_inc_set =>
we <= '0'; oe <= '0'; int_accept <= '1'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_int_addr;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when intrq_dec =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_minus;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when intrq_dec_set =>
we <= '0'; oe <= '0'; int_accept <= '1'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_int_addr;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when intrq_call =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_arg_call;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when intrq_calli =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_regfile_a;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when swi =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '1'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_dontcare;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
end case;
end process;
end architecture id_arch;
|
-- $Id: pdp11_lunit.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_lunit - syn
-- Description: pdp11: logic unit for data (lunit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-09-18 300 1.1 renamed from lbox
-- 2008-03-30 131 1.0.2 BUGFIX: SXT clears V condition code
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_lunit is -- logic unit for data (lunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CCIN : in slv4; -- condition codes in
FUNC : in slv4; -- function
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end pdp11_lunit;
architecture syn of pdp11_lunit is
-- --------------------------------------
begin
process (DSRC, DDST, CCIN, FUNC, BYTOP)
variable iout : slv16 := (others=>'0');
variable inzstd : slbit := '0';
variable ino : slbit := '0';
variable izo : slbit := '0';
variable ivo : slbit := '0';
variable ico : slbit := '0';
alias DSRC_L : slv8 is DSRC(7 downto 0);
alias DSRC_H : slv8 is DSRC(15 downto 8);
alias DDST_L : slv8 is DDST(7 downto 0);
alias DDST_H : slv8 is DDST(15 downto 8);
alias NI : slbit is CCIN(3);
alias ZI : slbit is CCIN(2);
alias VI : slbit is CCIN(1);
alias CI : slbit is CCIN(0);
alias iout_l : slv8 is iout(7 downto 0);
alias iout_h : slv8 is iout(15 downto 8);
begin
iout := (others=>'0');
inzstd := '1'; -- use standard logic by default
ino := '0';
izo := '0';
ivo := '0';
ico := '0';
--
-- the decoding of FUNC is done "manually" to get a structure based on
-- a 8->1 pattern. This matches the opcode structure and seems most
-- efficient.
--
if FUNC(3) = '0' then
if BYTOP = '0' then
case FUNC(2 downto 0) is
when "000" => -- ASR
iout := DDST(15) & DDST(15 downto 1);
ico := DDST(0);
ivo := iout(15) xor ico;
when "001" => -- ASL
iout := DDST(14 downto 0) & '0';
ico := DDST(15);
ivo := iout(15) xor ico;
when "010" => -- ROR
iout := CI & DDST(15 downto 1);
ico := DDST(0);
ivo := iout(15) xor ico;
when "011" => -- ROL
iout := DDST(14 downto 0) & CI;
ico := DDST(15);
ivo := iout(15) xor ico;
when "100" => -- BIS
iout := DDST or DSRC;
ico := CI;
when "101" => -- BIC
iout := DDST and not DSRC;
ico := CI;
when "110" => -- BIT
iout := DDST and DSRC;
ico := CI;
when "111" => -- MOV
iout := DSRC;
ico := CI;
when others => null;
end case;
else
case FUNC(2 downto 0) is
when "000" => -- ASRB
iout_l := DDST_L(7) & DDST_L(7 downto 1);
ico := DDST_L(0);
ivo := iout_l(7) xor ico;
when "001" => -- ASLB
iout_l := DDST(6 downto 0) & '0';
ico := DDST(7);
ivo := iout_l(7) xor ico;
when "010" => -- RORB
iout_l := CI & DDST_L(7 downto 1);
ico := DDST_L(0);
ivo := iout_l(7) xor ico;
when "011" => -- ROLB
iout_l := DDST_L(6 downto 0) & CI;
ico := DDST_L(7);
ivo := iout_l(7) xor ico;
when "100" => -- BISB
iout_l := DDST_L or DSRC_L;
ico := CI;
when "101" => -- BICB
iout_l := DDST_L and not DSRC_L;
ico := CI;
when "110" => -- BITB
iout_l := DDST_L and DSRC_L;
ico := CI;
when "111" => -- MOVB
iout_l := DSRC_L;
iout_h := (others=>DSRC_L(7));
ico := CI;
when others => null;
end case;
end if;
else
case FUNC(2 downto 0) is
when "000" => -- SXT
iout := (others=>NI);
inzstd := '0';
ino := NI;
izo := not NI;
ivo := '0';
ico := CI;
when "001" => -- SWAP
iout := DDST_L & DDST_H;
inzstd := '0';
ino := iout(7);
if unsigned(iout(7 downto 0)) = 0 then
izo := '1';
else
izo := '0';
end if;
when "010" => -- XOR
iout := DDST xor DSRC;
ico := CI;
when others => null;
end case;
end if;
DOUT <= iout;
if inzstd = '1' then
if BYTOP = '1' then
ino := iout(7);
if unsigned(iout(7 downto 0)) = 0 then
izo := '1';
else
izo := '0';
end if;
else
ino := iout(15);
if unsigned(iout) = 0 then
izo := '1';
else
izo := '0';
end if;
end if;
end if;
CCOUT(3) <= ino;
CCOUT(2) <= izo;
CCOUT(1) <= ivo;
CCOUT(0) <= ico;
end process;
end syn;
|
-- $Id: pdp11_lunit.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_lunit - syn
-- Description: pdp11: logic unit for data (lunit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-09-18 300 1.1 renamed from lbox
-- 2008-03-30 131 1.0.2 BUGFIX: SXT clears V condition code
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_lunit is -- logic unit for data (lunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CCIN : in slv4; -- condition codes in
FUNC : in slv4; -- function
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end pdp11_lunit;
architecture syn of pdp11_lunit is
-- --------------------------------------
begin
process (DSRC, DDST, CCIN, FUNC, BYTOP)
variable iout : slv16 := (others=>'0');
variable inzstd : slbit := '0';
variable ino : slbit := '0';
variable izo : slbit := '0';
variable ivo : slbit := '0';
variable ico : slbit := '0';
alias DSRC_L : slv8 is DSRC(7 downto 0);
alias DSRC_H : slv8 is DSRC(15 downto 8);
alias DDST_L : slv8 is DDST(7 downto 0);
alias DDST_H : slv8 is DDST(15 downto 8);
alias NI : slbit is CCIN(3);
alias ZI : slbit is CCIN(2);
alias VI : slbit is CCIN(1);
alias CI : slbit is CCIN(0);
alias iout_l : slv8 is iout(7 downto 0);
alias iout_h : slv8 is iout(15 downto 8);
begin
iout := (others=>'0');
inzstd := '1'; -- use standard logic by default
ino := '0';
izo := '0';
ivo := '0';
ico := '0';
--
-- the decoding of FUNC is done "manually" to get a structure based on
-- a 8->1 pattern. This matches the opcode structure and seems most
-- efficient.
--
if FUNC(3) = '0' then
if BYTOP = '0' then
case FUNC(2 downto 0) is
when "000" => -- ASR
iout := DDST(15) & DDST(15 downto 1);
ico := DDST(0);
ivo := iout(15) xor ico;
when "001" => -- ASL
iout := DDST(14 downto 0) & '0';
ico := DDST(15);
ivo := iout(15) xor ico;
when "010" => -- ROR
iout := CI & DDST(15 downto 1);
ico := DDST(0);
ivo := iout(15) xor ico;
when "011" => -- ROL
iout := DDST(14 downto 0) & CI;
ico := DDST(15);
ivo := iout(15) xor ico;
when "100" => -- BIS
iout := DDST or DSRC;
ico := CI;
when "101" => -- BIC
iout := DDST and not DSRC;
ico := CI;
when "110" => -- BIT
iout := DDST and DSRC;
ico := CI;
when "111" => -- MOV
iout := DSRC;
ico := CI;
when others => null;
end case;
else
case FUNC(2 downto 0) is
when "000" => -- ASRB
iout_l := DDST_L(7) & DDST_L(7 downto 1);
ico := DDST_L(0);
ivo := iout_l(7) xor ico;
when "001" => -- ASLB
iout_l := DDST(6 downto 0) & '0';
ico := DDST(7);
ivo := iout_l(7) xor ico;
when "010" => -- RORB
iout_l := CI & DDST_L(7 downto 1);
ico := DDST_L(0);
ivo := iout_l(7) xor ico;
when "011" => -- ROLB
iout_l := DDST_L(6 downto 0) & CI;
ico := DDST_L(7);
ivo := iout_l(7) xor ico;
when "100" => -- BISB
iout_l := DDST_L or DSRC_L;
ico := CI;
when "101" => -- BICB
iout_l := DDST_L and not DSRC_L;
ico := CI;
when "110" => -- BITB
iout_l := DDST_L and DSRC_L;
ico := CI;
when "111" => -- MOVB
iout_l := DSRC_L;
iout_h := (others=>DSRC_L(7));
ico := CI;
when others => null;
end case;
end if;
else
case FUNC(2 downto 0) is
when "000" => -- SXT
iout := (others=>NI);
inzstd := '0';
ino := NI;
izo := not NI;
ivo := '0';
ico := CI;
when "001" => -- SWAP
iout := DDST_L & DDST_H;
inzstd := '0';
ino := iout(7);
if unsigned(iout(7 downto 0)) = 0 then
izo := '1';
else
izo := '0';
end if;
when "010" => -- XOR
iout := DDST xor DSRC;
ico := CI;
when others => null;
end case;
end if;
DOUT <= iout;
if inzstd = '1' then
if BYTOP = '1' then
ino := iout(7);
if unsigned(iout(7 downto 0)) = 0 then
izo := '1';
else
izo := '0';
end if;
else
ino := iout(15);
if unsigned(iout) = 0 then
izo := '1';
else
izo := '0';
end if;
end if;
end if;
CCOUT(3) <= ino;
CCOUT(2) <= izo;
CCOUT(1) <= ivo;
CCOUT(0) <= ico;
end process;
end syn;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: MMU
-- File: mmu.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: Leon3 MMU top level entity
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu is
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end mmu;
architecture rtl of mmu is
constant MMUCTX_BITS : integer := M_CTX_SZ;
constant M_TLB_TYPE : integer range 0 to 1 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(1,2)); -- eather split or combined
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
type mmu_op is record
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
end record;
type mmu_cmbpctrl is record
tlbowner : mmu_idcache;
tlbactive : std_logic;
op : mmu_op;
end record;
type mmu_rtype is record
cmb_s1 : mmu_cmbpctrl;
cmb_s2 : mmu_cmbpctrl;
splt_is1 : mmu_cmbpctrl;
splt_is2 : mmu_cmbpctrl;
splt_ds1 : mmu_cmbpctrl;
splt_ds2 : mmu_cmbpctrl;
twactive : std_logic; -- split tlb
twowner : mmu_idcache; -- split tlb
flush : std_logic;
mmctrl2 : mmctrl_type2;
end record;
signal r, c : mmu_rtype;
-- tlb
component mmutlb
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 32 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type
);
end component;
signal tlbi_a0 : mmutlb_in_type;
signal tlbi_a1 : mmutlb_in_type;
signal tlbo_a0 : mmutlb_out_type;
signal tlbo_a1 : mmutlb_out_type;
signal twi_a : mmutwi_a(1 downto 0);
signal two_a : mmutwo_a(1 downto 0);
-- table walk
component mmutw
port (
rst : in std_logic;
clk : in std_logic;
mmctrl1 : in mmctrl_type1;
twi : in mmutw_in_type;
two : out mmutw_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end component;
signal twi : mmutw_in_type;
signal two : mmutw_out_type;
signal mmctrl1 : mmctrl_type1;
begin
p1: process (clk)
begin if rising_edge(clk) then r <= c; end if;
end process p1;
p0: process (rst, r, c, mmudci, mmuici, mcmmo, tlbo_a0, tlbo_a1, tlbi_a0, tlbi_a1, two_a, twi_a, two)
variable cmbtlbin : mmuidc_data_in_type;
variable cmbtlbout : mmutlb_out_type;
variable spltitlbin : mmuidc_data_in_type;
variable spltdtlbin : mmuidc_data_in_type;
variable spltitlbout : mmutlb_out_type;
variable spltdtlbout : mmutlb_out_type;
variable mmuico_transdata : mmuidc_data_out_type;
variable mmudco_transdata : mmuidc_data_out_type;
variable mmuico_grant : std_logic;
variable mmudco_grant : std_logic;
variable v : mmu_rtype;
variable twiv : mmutw_in_type;
variable twod, twoi : mmutw_out_type;
variable fault : mmutlbfault_out_type;
variable wbtransdata : mmuidc_data_out_type;
variable fs : mmctrl_fs_type;
variable fa : std_logic_vector(VA_I_SZ-1 downto 0);
begin
v := r;
wbtransdata.finish := '0';
wbtransdata.data := (others => '0');
wbtransdata.cache := '0';
wbtransdata.accexc := '0';
if (M_TLB_TYPE = 0) and (M_TLB_FASTWRITE /= 0) then
wbtransdata := tlbo_a1.wbtransdata;
end if;
cmbtlbin.data := (others => '0');
cmbtlbin.su := '0';
cmbtlbin.read := '0';
cmbtlbin.isid := id_dcache;
cmbtlbout.transdata.finish := '0';
cmbtlbout.transdata.data := (others => '0');
cmbtlbout.transdata.cache := '0';
cmbtlbout.transdata.accexc := '0';
cmbtlbout.fault.fault_pro := '0';
cmbtlbout.fault.fault_pri := '0';
cmbtlbout.fault.fault_access := '0';
cmbtlbout.fault.fault_mexc := '0';
cmbtlbout.fault.fault_trans := '0';
cmbtlbout.fault.fault_inv := '0';
cmbtlbout.fault.fault_lvl := (others => '0');
cmbtlbout.fault.fault_su := '0';
cmbtlbout.fault.fault_read := '0';
cmbtlbout.fault.fault_isid := id_dcache;
cmbtlbout.fault.fault_addr := (others => '0');
cmbtlbout.nexttrans := '0';
cmbtlbout.s1finished := '0';
mmuico_transdata.finish := '0';
mmuico_transdata.data := (others => '0');
mmuico_transdata.cache := '0';
mmuico_transdata.accexc := '0';
mmudco_transdata.finish := '0';
mmudco_transdata.data := (others => '0');
mmudco_transdata.cache := '0';
mmudco_transdata.accexc := '0';
mmuico_grant := '0';
mmudco_grant := '0';
twiv.walk_op_ur := '0';
twiv.areq_ur := '0';
twiv.data := (others => '0');
twiv.adata := (others => '0');
twiv.aaddr := (others => '0');
twod.finish := '0';
twod.data := (others => '0');
twod.addr := (others => '0');
twod.lvl := (others => '0');
twod.fault_mexc := '0';
twod.fault_trans := '0';
twod.fault_inv := '0';
twod.fault_lvl := (others => '0');
twoi.finish := '0';
twoi.data := (others => '0');
twoi.addr := (others => '0');
twoi.lvl := (others => '0');
twoi.fault_mexc := '0';
twoi.fault_trans := '0';
twoi.fault_inv := '0';
twoi.fault_lvl := (others => '0');
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
fs.ow := '0';
fs.fav := '0';
fs.ft := (others => '0');
fs.at_ls := '0';
fs.at_id := '0';
fs.at_su := '0';
fs.l := (others => '0');
fs.ebe := (others => '0');
fa := (others => '0');
if M_TLB_TYPE = 0 then
spltitlbout := tlbo_a0;
spltdtlbout := tlbo_a1;
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
spltdtlbin := mmudci.transdata;
spltitlbin := mmuici.transdata;
mmudco_transdata := spltdtlbout.transdata;
mmuico_transdata := spltitlbout.transdata;
-- d-tlb
if ((not r.splt_ds1.tlbactive) or spltdtlbout.s1finished) = '1' then
v.splt_ds1.tlbactive := '0';
v.splt_ds1.op.trans_op := '0';
v.splt_ds1.op.flush_op := '0';
if mmudci.trans_op = '1' then
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
v.flush := '1';
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.flush_op := '1';
end if;
end if;
-- i-tlb
if ((not r.splt_is1.tlbactive) or spltitlbout.s1finished) = '1' then
v.splt_is1.tlbactive := '0';
v.splt_is1.op.trans_op := '0';
v.splt_is1.op.flush_op := '0';
if v.flush = '1' then
v.flush := '0';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.flush_op := '1';
elsif mmuici.trans_op = '1' then
mmuico_grant := '1';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.trans_op := '1';
end if;
end if;
if spltitlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
fault := spltitlbout.fault;
end if;
if spltdtlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
if (spltdtlbout.fault.fault_mexc or
spltdtlbout.fault.fault_trans or
spltdtlbout.fault.fault_inv or
spltdtlbout.fault.fault_pro or
spltdtlbout.fault.fault_pri or
spltdtlbout.fault.fault_access) = '1' then
fault := spltdtlbout.fault; -- overwrite icache fault
end if;
end if;
if spltitlbout.s1finished = '1' then
v.splt_is2 := r.splt_is1;
end if;
if spltdtlbout.s1finished = '1' then
v.splt_ds2 := r.splt_ds1;
end if;
if ( r.splt_is2.op.flush_op ) = '1' then
mmuico_transdata.finish := '0';
end if;
-- share tw
if two.finish = '1' then
v.twactive := '0';
end if;
if r.twowner = id_icache then
twiv := twi_a(0);
twoi.finish := two.finish;
else
twiv := twi_a(1);
twod.finish := two.finish;
end if;
if (v.twactive) = '0' then
if (twi_a(1).areq_ur or twi_a(1).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_dcache;
elsif (twi_a(0).areq_ur or twi_a(0).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_icache;
end if;
end if;
else
--# combined i/d cache: 1 tlb, 1 tw
-- share one tlb among i and d cache
cmbtlbout := tlbo_a0;
mmuico_grant := '0'; mmudco_grant := '0';
mmuico_transdata.finish := '0'; mmudco_transdata.finish := '0';
twiv := twi_a(0);
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
-- twod.finish := two.finish;
twoi.finish := two.finish;
if ((not v.cmb_s1.tlbactive) or cmbtlbout.s1finished) = '1' then
v.cmb_s1.tlbactive := '0';
v.cmb_s1.op.trans_op := '0';
v.cmb_s1.op.flush_op := '0';
if (mmudci.trans_op or mmudci.flush_op or mmuici.trans_op) = '1' then
v.cmb_s1.tlbactive := '1';
end if;
if mmudci.trans_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.flush_op := '1';
elsif mmuici.trans_op = '1' then
mmuico_grant := '1';
v.cmb_s1.tlbowner := id_icache;
v.cmb_s1.op.trans_op := '1';
end if;
end if;
if (r.cmb_s1.tlbactive and not r.cmb_s2.tlbactive) = '1' then
end if;
if cmbtlbout.s1finished = '1' then
v.cmb_s2 := r.cmb_s1;
end if;
if r.cmb_s1.tlbowner = id_dcache then
cmbtlbin := mmudci.transdata;
else
cmbtlbin := mmuici.transdata;
end if;
if r.cmb_s2.tlbowner = id_dcache then
mmudco_transdata := cmbtlbout.transdata;
else
mmuico_transdata := cmbtlbout.transdata;
end if;
if cmbtlbout.transdata.finish = '1' and (r.cmb_s2.op.flush_op = '0') then
fault := cmbtlbout.fault;
end if;
end if;
-- # fault status register
if (mmudci.fsread) = '1' then
v.mmctrl2.valid := '0'; v.mmctrl2.fs.fav := '0';
end if;
if (fault.fault_mexc) = '1' then
fs.ft := FS_FT_TRANS;
elsif (fault.fault_trans) = '1' then
fs.ft := FS_FT_INV;
elsif (fault.fault_inv) = '1' then
fs.ft := FS_FT_INV;
elsif (fault.fault_pri) = '1' then
fs.ft := FS_FT_PRI;
elsif (fault.fault_pro) = '1' then
fs.ft := FS_FT_PRO;
elsif (fault.fault_access) = '1' then
fs.ft := FS_FT_BUS;
else
fs.ft := FS_FT_NONE;
end if;
fs.ow := '0';
fs.l := fault.fault_lvl;
if fault.fault_isid = id_dcache then
fs.at_id := '0';
else
fs.at_id := '1';
end if;
fs.at_su := fault.fault_su;
fs.at_ls := not fault.fault_read;
fs.fav := '1';
fs.ebe := (others => '0');
fa := fault.fault_addr(VA_I_U downto VA_I_D);
if (fault.fault_mexc or
fault.fault_trans or
fault.fault_inv or
fault.fault_pro or
fault.fault_pri or
fault.fault_access) = '1' then
--# priority
if v.mmctrl2.valid = '1'then
if (fault.fault_mexc) = '1' then
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
if (r.mmctrl2.fs.ft /= FS_FT_INV) then
if fault.fault_isid = id_dcache then
-- dcache
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
-- icache
if (not r.mmctrl2.fs.at_id) = '0' then
fs.ow := '1';
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
end if;
end if;
end if;
end if;
else
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
v.mmctrl2.valid := '1';
end if;
if (fault.fault_isid) = id_dcache then
mmudco_transdata.accexc := '1';
else
mmuico_transdata.accexc := '1';
end if;
end if;
-- # reset
if ( rst = '0' ) then
if M_TLB_TYPE = 0 then
v.splt_is1.tlbactive := '0';
v.splt_is2.tlbactive := '0';
v.splt_ds1.tlbactive := '0';
v.splt_ds2.tlbactive := '0';
v.splt_is1.op.trans_op := '0';
v.splt_is2.op.trans_op := '0';
v.splt_ds1.op.trans_op := '0';
v.splt_ds2.op.trans_op := '0';
v.splt_is1.op.flush_op := '0';
v.splt_is2.op.flush_op := '0';
v.splt_ds1.op.flush_op := '0';
v.splt_ds2.op.flush_op := '0';
else
v.cmb_s1.tlbactive := '0';
v.cmb_s2.tlbactive := '0';
v.cmb_s1.op.trans_op := '0';
v.cmb_s2.op.trans_op := '0';
v.cmb_s1.op.flush_op := '0';
v.cmb_s2.op.flush_op := '0';
end if;
v.flush := '0';
v.mmctrl2.valid := '0';
v.twactive := '0';
v.twowner := id_icache;
end if;
-- drive signals
if M_TLB_TYPE = 0 then
tlbi_a0.trans_op <= r.splt_is1.op.trans_op;
tlbi_a0.flush_op <= r.splt_is1.op.flush_op;
tlbi_a0.transdata <= spltitlbin;
tlbi_a0.s2valid <= r.splt_is2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
tlbi_a1.trans_op <= r.splt_ds1.op.trans_op;
tlbi_a1.flush_op <= r.splt_ds1.op.flush_op;
tlbi_a1.transdata <= spltdtlbin;
tlbi_a1.s2valid <= r.splt_ds2.tlbactive;
tlbi_a1.mmctrl1 <= mmudci.mmctrl1;
tlbi_a1.wb_op <= mmudci.wb_op;
else
tlbi_a0.trans_op <= r.cmb_s1.op.trans_op;
tlbi_a0.flush_op <= r.cmb_s1.op.flush_op;
tlbi_a0.transdata <= cmbtlbin;
tlbi_a0.s2valid <= r.cmb_s2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
end if;
tlbi_a0.tlbcami <= (others => mmutlbcam_in_type_none);
tlbi_a1.tlbcami <= (others => mmutlbcam_in_type_none);
mmudco.transdata <= mmudco_transdata;
mmuico.transdata <= mmuico_transdata;
mmudco.grant <= mmudco_grant;
mmuico.grant <= mmuico_grant;
mmudco.mmctrl2 <= r.mmctrl2;
mmudco.wbtransdata <= wbtransdata;
twi <= twiv;
two_a(0) <= twoi;
two_a(1) <= twod;
mmctrl1 <= mmudci.mmctrl1;
c <= v;
end process p0;
tlbcomb0: if M_TLB_TYPE = 1 generate
-- i/d tlb
ctlb0 : mmutlb
generic map ( tech, M_ENT_C, 0, tlb_rep )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0));
end generate tlbcomb0;
tlbsplit0: if M_TLB_TYPE = 0 generate
-- i tlb
itlb0 : mmutlb
generic map ( tech, M_ENT_I, 0, tlb_rep )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0));
-- d tlb
dtlb0 : mmutlb
generic map ( tech, M_ENT_D, tlb_type, tlb_rep )
port map (rst, clk, tlbi_a1, tlbo_a1, two_a(1), twi_a(1));
end generate tlbsplit0;
-- table walk component
tw0 : mmutw
port map (rst, clk, mmctrl1, twi, two, mcmmo, mcmmi);
-- pragma translate_off
chk : process
begin
assert not ((M_TLB_TYPE = 1) and (M_TLB_FASTWRITE /= 0)) report
"Fast writebuffer only supported for combined cache"
severity failure;
wait;
end process;
-- pragma translate_on
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: MMU
-- File: mmu.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: Leon3 MMU top level entity
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu is
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end mmu;
architecture rtl of mmu is
constant MMUCTX_BITS : integer := M_CTX_SZ;
constant M_TLB_TYPE : integer range 0 to 1 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(1,2)); -- eather split or combined
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
type mmu_op is record
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
end record;
type mmu_cmbpctrl is record
tlbowner : mmu_idcache;
tlbactive : std_logic;
op : mmu_op;
end record;
type mmu_rtype is record
cmb_s1 : mmu_cmbpctrl;
cmb_s2 : mmu_cmbpctrl;
splt_is1 : mmu_cmbpctrl;
splt_is2 : mmu_cmbpctrl;
splt_ds1 : mmu_cmbpctrl;
splt_ds2 : mmu_cmbpctrl;
twactive : std_logic; -- split tlb
twowner : mmu_idcache; -- split tlb
flush : std_logic;
mmctrl2 : mmctrl_type2;
end record;
signal r, c : mmu_rtype;
-- tlb
component mmutlb
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 32 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type
);
end component;
signal tlbi_a0 : mmutlb_in_type;
signal tlbi_a1 : mmutlb_in_type;
signal tlbo_a0 : mmutlb_out_type;
signal tlbo_a1 : mmutlb_out_type;
signal twi_a : mmutwi_a(1 downto 0);
signal two_a : mmutwo_a(1 downto 0);
-- table walk
component mmutw
port (
rst : in std_logic;
clk : in std_logic;
mmctrl1 : in mmctrl_type1;
twi : in mmutw_in_type;
two : out mmutw_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end component;
signal twi : mmutw_in_type;
signal two : mmutw_out_type;
signal mmctrl1 : mmctrl_type1;
begin
p1: process (clk)
begin if rising_edge(clk) then r <= c; end if;
end process p1;
p0: process (rst, r, c, mmudci, mmuici, mcmmo, tlbo_a0, tlbo_a1, tlbi_a0, tlbi_a1, two_a, twi_a, two)
variable cmbtlbin : mmuidc_data_in_type;
variable cmbtlbout : mmutlb_out_type;
variable spltitlbin : mmuidc_data_in_type;
variable spltdtlbin : mmuidc_data_in_type;
variable spltitlbout : mmutlb_out_type;
variable spltdtlbout : mmutlb_out_type;
variable mmuico_transdata : mmuidc_data_out_type;
variable mmudco_transdata : mmuidc_data_out_type;
variable mmuico_grant : std_logic;
variable mmudco_grant : std_logic;
variable v : mmu_rtype;
variable twiv : mmutw_in_type;
variable twod, twoi : mmutw_out_type;
variable fault : mmutlbfault_out_type;
variable wbtransdata : mmuidc_data_out_type;
variable fs : mmctrl_fs_type;
variable fa : std_logic_vector(VA_I_SZ-1 downto 0);
begin
v := r;
wbtransdata.finish := '0';
wbtransdata.data := (others => '0');
wbtransdata.cache := '0';
wbtransdata.accexc := '0';
if (M_TLB_TYPE = 0) and (M_TLB_FASTWRITE /= 0) then
wbtransdata := tlbo_a1.wbtransdata;
end if;
cmbtlbin.data := (others => '0');
cmbtlbin.su := '0';
cmbtlbin.read := '0';
cmbtlbin.isid := id_dcache;
cmbtlbout.transdata.finish := '0';
cmbtlbout.transdata.data := (others => '0');
cmbtlbout.transdata.cache := '0';
cmbtlbout.transdata.accexc := '0';
cmbtlbout.fault.fault_pro := '0';
cmbtlbout.fault.fault_pri := '0';
cmbtlbout.fault.fault_access := '0';
cmbtlbout.fault.fault_mexc := '0';
cmbtlbout.fault.fault_trans := '0';
cmbtlbout.fault.fault_inv := '0';
cmbtlbout.fault.fault_lvl := (others => '0');
cmbtlbout.fault.fault_su := '0';
cmbtlbout.fault.fault_read := '0';
cmbtlbout.fault.fault_isid := id_dcache;
cmbtlbout.fault.fault_addr := (others => '0');
cmbtlbout.nexttrans := '0';
cmbtlbout.s1finished := '0';
mmuico_transdata.finish := '0';
mmuico_transdata.data := (others => '0');
mmuico_transdata.cache := '0';
mmuico_transdata.accexc := '0';
mmudco_transdata.finish := '0';
mmudco_transdata.data := (others => '0');
mmudco_transdata.cache := '0';
mmudco_transdata.accexc := '0';
mmuico_grant := '0';
mmudco_grant := '0';
twiv.walk_op_ur := '0';
twiv.areq_ur := '0';
twiv.data := (others => '0');
twiv.adata := (others => '0');
twiv.aaddr := (others => '0');
twod.finish := '0';
twod.data := (others => '0');
twod.addr := (others => '0');
twod.lvl := (others => '0');
twod.fault_mexc := '0';
twod.fault_trans := '0';
twod.fault_inv := '0';
twod.fault_lvl := (others => '0');
twoi.finish := '0';
twoi.data := (others => '0');
twoi.addr := (others => '0');
twoi.lvl := (others => '0');
twoi.fault_mexc := '0';
twoi.fault_trans := '0';
twoi.fault_inv := '0';
twoi.fault_lvl := (others => '0');
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
fs.ow := '0';
fs.fav := '0';
fs.ft := (others => '0');
fs.at_ls := '0';
fs.at_id := '0';
fs.at_su := '0';
fs.l := (others => '0');
fs.ebe := (others => '0');
fa := (others => '0');
if M_TLB_TYPE = 0 then
spltitlbout := tlbo_a0;
spltdtlbout := tlbo_a1;
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
spltdtlbin := mmudci.transdata;
spltitlbin := mmuici.transdata;
mmudco_transdata := spltdtlbout.transdata;
mmuico_transdata := spltitlbout.transdata;
-- d-tlb
if ((not r.splt_ds1.tlbactive) or spltdtlbout.s1finished) = '1' then
v.splt_ds1.tlbactive := '0';
v.splt_ds1.op.trans_op := '0';
v.splt_ds1.op.flush_op := '0';
if mmudci.trans_op = '1' then
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
v.flush := '1';
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.flush_op := '1';
end if;
end if;
-- i-tlb
if ((not r.splt_is1.tlbactive) or spltitlbout.s1finished) = '1' then
v.splt_is1.tlbactive := '0';
v.splt_is1.op.trans_op := '0';
v.splt_is1.op.flush_op := '0';
if v.flush = '1' then
v.flush := '0';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.flush_op := '1';
elsif mmuici.trans_op = '1' then
mmuico_grant := '1';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.trans_op := '1';
end if;
end if;
if spltitlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
fault := spltitlbout.fault;
end if;
if spltdtlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
if (spltdtlbout.fault.fault_mexc or
spltdtlbout.fault.fault_trans or
spltdtlbout.fault.fault_inv or
spltdtlbout.fault.fault_pro or
spltdtlbout.fault.fault_pri or
spltdtlbout.fault.fault_access) = '1' then
fault := spltdtlbout.fault; -- overwrite icache fault
end if;
end if;
if spltitlbout.s1finished = '1' then
v.splt_is2 := r.splt_is1;
end if;
if spltdtlbout.s1finished = '1' then
v.splt_ds2 := r.splt_ds1;
end if;
if ( r.splt_is2.op.flush_op ) = '1' then
mmuico_transdata.finish := '0';
end if;
-- share tw
if two.finish = '1' then
v.twactive := '0';
end if;
if r.twowner = id_icache then
twiv := twi_a(0);
twoi.finish := two.finish;
else
twiv := twi_a(1);
twod.finish := two.finish;
end if;
if (v.twactive) = '0' then
if (twi_a(1).areq_ur or twi_a(1).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_dcache;
elsif (twi_a(0).areq_ur or twi_a(0).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_icache;
end if;
end if;
else
--# combined i/d cache: 1 tlb, 1 tw
-- share one tlb among i and d cache
cmbtlbout := tlbo_a0;
mmuico_grant := '0'; mmudco_grant := '0';
mmuico_transdata.finish := '0'; mmudco_transdata.finish := '0';
twiv := twi_a(0);
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
-- twod.finish := two.finish;
twoi.finish := two.finish;
if ((not v.cmb_s1.tlbactive) or cmbtlbout.s1finished) = '1' then
v.cmb_s1.tlbactive := '0';
v.cmb_s1.op.trans_op := '0';
v.cmb_s1.op.flush_op := '0';
if (mmudci.trans_op or mmudci.flush_op or mmuici.trans_op) = '1' then
v.cmb_s1.tlbactive := '1';
end if;
if mmudci.trans_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.flush_op := '1';
elsif mmuici.trans_op = '1' then
mmuico_grant := '1';
v.cmb_s1.tlbowner := id_icache;
v.cmb_s1.op.trans_op := '1';
end if;
end if;
if (r.cmb_s1.tlbactive and not r.cmb_s2.tlbactive) = '1' then
end if;
if cmbtlbout.s1finished = '1' then
v.cmb_s2 := r.cmb_s1;
end if;
if r.cmb_s1.tlbowner = id_dcache then
cmbtlbin := mmudci.transdata;
else
cmbtlbin := mmuici.transdata;
end if;
if r.cmb_s2.tlbowner = id_dcache then
mmudco_transdata := cmbtlbout.transdata;
else
mmuico_transdata := cmbtlbout.transdata;
end if;
if cmbtlbout.transdata.finish = '1' and (r.cmb_s2.op.flush_op = '0') then
fault := cmbtlbout.fault;
end if;
end if;
-- # fault status register
if (mmudci.fsread) = '1' then
v.mmctrl2.valid := '0'; v.mmctrl2.fs.fav := '0';
end if;
if (fault.fault_mexc) = '1' then
fs.ft := FS_FT_TRANS;
elsif (fault.fault_trans) = '1' then
fs.ft := FS_FT_INV;
elsif (fault.fault_inv) = '1' then
fs.ft := FS_FT_INV;
elsif (fault.fault_pri) = '1' then
fs.ft := FS_FT_PRI;
elsif (fault.fault_pro) = '1' then
fs.ft := FS_FT_PRO;
elsif (fault.fault_access) = '1' then
fs.ft := FS_FT_BUS;
else
fs.ft := FS_FT_NONE;
end if;
fs.ow := '0';
fs.l := fault.fault_lvl;
if fault.fault_isid = id_dcache then
fs.at_id := '0';
else
fs.at_id := '1';
end if;
fs.at_su := fault.fault_su;
fs.at_ls := not fault.fault_read;
fs.fav := '1';
fs.ebe := (others => '0');
fa := fault.fault_addr(VA_I_U downto VA_I_D);
if (fault.fault_mexc or
fault.fault_trans or
fault.fault_inv or
fault.fault_pro or
fault.fault_pri or
fault.fault_access) = '1' then
--# priority
if v.mmctrl2.valid = '1'then
if (fault.fault_mexc) = '1' then
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
if (r.mmctrl2.fs.ft /= FS_FT_INV) then
if fault.fault_isid = id_dcache then
-- dcache
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
-- icache
if (not r.mmctrl2.fs.at_id) = '0' then
fs.ow := '1';
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
end if;
end if;
end if;
end if;
else
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
v.mmctrl2.valid := '1';
end if;
if (fault.fault_isid) = id_dcache then
mmudco_transdata.accexc := '1';
else
mmuico_transdata.accexc := '1';
end if;
end if;
-- # reset
if ( rst = '0' ) then
if M_TLB_TYPE = 0 then
v.splt_is1.tlbactive := '0';
v.splt_is2.tlbactive := '0';
v.splt_ds1.tlbactive := '0';
v.splt_ds2.tlbactive := '0';
v.splt_is1.op.trans_op := '0';
v.splt_is2.op.trans_op := '0';
v.splt_ds1.op.trans_op := '0';
v.splt_ds2.op.trans_op := '0';
v.splt_is1.op.flush_op := '0';
v.splt_is2.op.flush_op := '0';
v.splt_ds1.op.flush_op := '0';
v.splt_ds2.op.flush_op := '0';
else
v.cmb_s1.tlbactive := '0';
v.cmb_s2.tlbactive := '0';
v.cmb_s1.op.trans_op := '0';
v.cmb_s2.op.trans_op := '0';
v.cmb_s1.op.flush_op := '0';
v.cmb_s2.op.flush_op := '0';
end if;
v.flush := '0';
v.mmctrl2.valid := '0';
v.twactive := '0';
v.twowner := id_icache;
end if;
-- drive signals
if M_TLB_TYPE = 0 then
tlbi_a0.trans_op <= r.splt_is1.op.trans_op;
tlbi_a0.flush_op <= r.splt_is1.op.flush_op;
tlbi_a0.transdata <= spltitlbin;
tlbi_a0.s2valid <= r.splt_is2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
tlbi_a1.trans_op <= r.splt_ds1.op.trans_op;
tlbi_a1.flush_op <= r.splt_ds1.op.flush_op;
tlbi_a1.transdata <= spltdtlbin;
tlbi_a1.s2valid <= r.splt_ds2.tlbactive;
tlbi_a1.mmctrl1 <= mmudci.mmctrl1;
tlbi_a1.wb_op <= mmudci.wb_op;
else
tlbi_a0.trans_op <= r.cmb_s1.op.trans_op;
tlbi_a0.flush_op <= r.cmb_s1.op.flush_op;
tlbi_a0.transdata <= cmbtlbin;
tlbi_a0.s2valid <= r.cmb_s2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
end if;
tlbi_a0.tlbcami <= (others => mmutlbcam_in_type_none);
tlbi_a1.tlbcami <= (others => mmutlbcam_in_type_none);
mmudco.transdata <= mmudco_transdata;
mmuico.transdata <= mmuico_transdata;
mmudco.grant <= mmudco_grant;
mmuico.grant <= mmuico_grant;
mmudco.mmctrl2 <= r.mmctrl2;
mmudco.wbtransdata <= wbtransdata;
twi <= twiv;
two_a(0) <= twoi;
two_a(1) <= twod;
mmctrl1 <= mmudci.mmctrl1;
c <= v;
end process p0;
tlbcomb0: if M_TLB_TYPE = 1 generate
-- i/d tlb
ctlb0 : mmutlb
generic map ( tech, M_ENT_C, 0, tlb_rep )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0));
end generate tlbcomb0;
tlbsplit0: if M_TLB_TYPE = 0 generate
-- i tlb
itlb0 : mmutlb
generic map ( tech, M_ENT_I, 0, tlb_rep )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0));
-- d tlb
dtlb0 : mmutlb
generic map ( tech, M_ENT_D, tlb_type, tlb_rep )
port map (rst, clk, tlbi_a1, tlbo_a1, two_a(1), twi_a(1));
end generate tlbsplit0;
-- table walk component
tw0 : mmutw
port map (rst, clk, mmctrl1, twi, two, mcmmo, mcmmi);
-- pragma translate_off
chk : process
begin
assert not ((M_TLB_TYPE = 1) and (M_TLB_FASTWRITE /= 0)) report
"Fast writebuffer only supported for combined cache"
severity failure;
wait;
end process;
-- pragma translate_on
end rtl;
|
--------------------------------------------------------------------------------
-- Company: University of Cyprus, Department of Computer Science
-- Engineer: Dr. Petros Panayi
--
-- Create Date: 23:49:58 03/23/2007
-- Design Name: myPCRegister
-- Module Name: C:/Xilinx91i/PetrosProjects/MIPS32/myPCRegister_tb.vhd
-- Project Name: MIPS32
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: myPCRegister
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY myPCRegister_tb_vhd IS
END myPCRegister_tb_vhd;
ARCHITECTURE behavior OF myPCRegister_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT myPCRegister
PORT(
PC_INPUT : IN std_logic_vector(9 downto 0);
clk : IN std_logic;
RESET : IN std_logic;
PC_OUTPUT : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL RESET : std_logic := '0';
SIGNAL PC_INPUT : std_logic_vector(9 downto 0) := (others=>'0');
--Outputs
SIGNAL PC_OUTPUT : std_logic_vector(9 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: myPCRegister PORT MAP(
PC_INPUT => PC_INPUT,
PC_OUTPUT => PC_OUTPUT,
clk => clk,
RESET => RESET
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
PC_INPUT <= "0000000001";
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
clk <= '0';
PC_INPUT <= "1000000001";
wait for 10 ns;
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
END;
|
--YUV2RGB entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.MYTYPE.ALL;
ENTITY YUV2RGB IS
PORT(CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
FIXED_Y_IN: IN COLOR;
U_IN: IN COLOR;
V_IN: IN COLOR;
R_OUT: OUT COLOR;
G_OUT: OUT COLOR;
B_OUT: OUT COLOR);
END ENTITY YUV2RGB;
ARCHITECTURE ART1 OF YUV2RGB IS
BEGIN
CLOCK: PROCESS(CLK,RESET)
VARIABLE R_REG: COLOR;
VARIABLE G_REG: COLOR;
VARIABLE B_REG: COLOR;
VARIABLE TEMP: INTEGER RANGE -512 TO 512;
BEGIN
IF(RESET='1') THEN
R_OUT<=0;
G_OUT<=0;
B_OUT<=0;
ELSIF(CLK'EVENT AND CLK='1') THEN
TEMP:= FIXED_Y_IN + 113983*(V_IN-128)/100000;
--调整
IF(TEMP<0) THEN
R_REG:=0;
ELSIF(TEMP>255) THEN
R_REG:=255;
ELSE
R_REG:=TEMP;
END IF;
TEMP:=FIXED_Y_IN - 39465*(U_IN-128)/100000 - 58060*(V_IN-128)/100000;
--调整
IF(TEMP<0) THEN
G_REG:=0;
ELSIF(TEMP>255) THEN
G_REG:=255;
ELSE
G_REG:=TEMP;
END IF;
TEMP:=FIXED_Y_IN + 203211*(U_IN-128)/100000;
--调整
IF(TEMP<0) THEN
B_REG:=0;
ELSIF(TEMP>255) THEN
B_REG:=255;
ELSE
B_REG:=TEMP;
END IF;
R_OUT<=R_REG;
G_OUT<=G_REG;
B_OUT<=B_REG;
END IF;
END PROCESS;
END ARCHITECTURE ART1;
|
--! @file subtractor.vhd
--!
--! @authors Salvatore Barone <salvator.barone@gmail.com> <br>
--! Alfonso Di Martino <alfonsodimartino160989@gmail.com> <br>
--! Sossio Fiorillo <fsossio@gmail.com> <br>
--! Pietro Liguori <pie.liguori@gmail.com> <br>
--!
--! @date 01 07 2017
--!
--! @copyright
--! Copyright 2017 Salvatore Barone <salvator.barone@gmail.com> <br>
--! Alfonso Di Martino <alfonsodimartino160989@gmail.com> <br>
--! Sossio Fiorillo <fsossio@gmail.com> <br>
--! Pietro Liguori <pie.liguori@gmail.com> <br>
--!
--! This file is part of Linear-Regression.
--!
--! Linear-Regression is free software; you can redistribute it and/or modify it under the terms of
--! the GNU General Public License as published by the Free Software Foundation; either version 3 of
--! the License, or any later version.
--!
--! Linear-Regression is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
--! without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--! You should have received a copy of the GNU General Public License along with this program; if not,
--! write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
--! USA.
--!
--! @addtogroup Subtractor
--! @{
--! @brief Subtractor per la sottrazione di due espressi con numero di bit variabile.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Sottrattore di due numeri.
--!
--! Il sottrattore permette di effettuare una differenza di due numeri espressi su un certo numero di bit.
--! La differenza dei due valori viene espressa sullo stesso numero di bit.
entity subtractor is
generic ( nbits : natural := 32); --! Numero di bit su cui sottraendo e minuendo sono espressi.
--! La differenza sarà espressa sul medesimo numero di bit
port ( sub1 : in std_logic_vector(nbits-1 downto 0); --! minuendo
sub2 : in std_logic_vector(nbits-1 downto 0); --! sottraendo
diff : out std_logic_vector(nbits-1 downto 0)); --! differenza dei valori: diff = sub1-sub2
end subtractor;
architecture structural of subtractor is
begin
diff <= std_logic_vector(signed(sub1) - signed(sub2));
end structural;
--! @}
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SEU_tb IS
END SEU_tb;
ARCHITECTURE behavior OF SEU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SEU
PORT(
imm13 : IN std_logic_vector(12 downto 0);
SEUimm : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal imm13 : std_logic_vector(12 downto 0) := (others => '0');
--Outputs
signal SEUimm : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SEU PORT MAP (
imm13 => imm13,
SEUimm => SEUimm
);
-- Stimulus process
stim_proc: process
begin
imm13<="0100101001110";
wait for 20 ns;
imm13<="1011000101011";
wait for 20 ns;
imm13<="0000000000001";
wait for 20 ns;
imm13<="1000000000000";
wait;
end process;
END;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SEU_tb IS
END SEU_tb;
ARCHITECTURE behavior OF SEU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SEU
PORT(
imm13 : IN std_logic_vector(12 downto 0);
SEUimm : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal imm13 : std_logic_vector(12 downto 0) := (others => '0');
--Outputs
signal SEUimm : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SEU PORT MAP (
imm13 => imm13,
SEUimm => SEUimm
);
-- Stimulus process
stim_proc: process
begin
imm13<="0100101001110";
wait for 20 ns;
imm13<="1011000101011";
wait for 20 ns;
imm13<="0000000000001";
wait for 20 ns;
imm13<="1000000000000";
wait;
end process;
END;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_0_0 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_0_0;
ARCHITECTURE DemoInterconnect_axi_spi_master_0_0_arch OF DemoInterconnect_axi_spi_master_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_0_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_0_0 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_0_0;
ARCHITECTURE DemoInterconnect_axi_spi_master_0_0_arch OF DemoInterconnect_axi_spi_master_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_0_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_0_0_arch;
|
-------------------------------------------------------------------------------
-- Title : Configurable Cordic core
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_core.vhd
-- Author : Aylons <aylons@aylons-yoga2>
-- Company :
-- Created : 2014-05-03
-- Last update: 2015-03-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This CORDIC allow configuration of its number of stages and
-- accepts any bus size for its inputs and ouputs. The calculation to be done
-- is defined by a generic value, and there's no need for external codes due to
-- any parameter change.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014 Aylons Hazzud
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-03 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-------------------------------------------------------------------------------
entity cordic_core is
generic (
g_stages : natural := 20;
g_bit_growth : natural := 2;
g_mode : string := "rect_to_polar"
);
-- x represents the x axis in rectangular coordinates or amplitude in polar
-- y represents the y axis in rectangular coordinates
-- z represents phase in polar coordinates
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
valid_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed;
valid_o : out std_logic
);
end entity cordic_core;
-------------------------------------------------------------------------------
architecture str of cordic_core is
constant c_width : natural := x_i'length + g_bit_growth + 2;
type wiring is array (0 to g_stages) of signed(c_width-1 downto 0);
type control_wiring is array (0 to g_stages) of boolean;
type z_wiring is array (0 to g_stages) of signed(x_i'length-1 downto 0);
signal x_inter : wiring := (others => (others => '0'));
signal y_inter : wiring := (others => (others => '0'));
signal z_inter : z_wiring := (others => (others => '0'));
signal x_shifted : wiring := (others => (others => '0'));
signal y_shifted : wiring := (others => (others => '0'));
signal control_x : control_wiring := (others => false);
signal control_y : control_wiring := (others => false);
component addsub is
port (
a_i : in signed;
b_i : in signed;
sub_i : in boolean;
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
result_o : out signed;
positive_o : out boolean;
negative_o : out boolean);
end component addsub;
component pipeline is
generic (
g_width : natural;
g_depth : natural);
port (
data_i : in std_logic_vector(g_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
data_o : out std_logic_vector(g_width-1 downto 0));
end component pipeline;
function stage_constant(mode, stage, width : natural) return signed is
variable const_vector : signed(width-1 downto 0) := (others => '0');
begin
-- Each iteration must sum or subtract arctg(1/(2^(stage-1)))
-- Only works for cordics up to 32 bits. Wider constants require
-- pre-generated tables, due to limitations in most VHDL tool's
const_vector := to_signed(integer(arctan(2.0**(real(1-stage)))/(MATH_2_PI)*(2.0**real(width))), width);
return const_vector;
end function;
begin -- architecture str
--TODO: for now, it only generates a rect_to_polar CORDIC. Adapt so we can
--generate other algorithms while reusing as much code as possible, so it
--will be easy to maintain and evolve - hardware is already hard enough.
x_inter(0) <= resize(x_i, x_i'length+2) & (g_bit_growth-1 downto 0 => '0');
y_inter(0) <= resize(y_i, y_i'length+2) & (g_bit_growth-1 downto 0 => '0');
z_inter(0) <= z_i; -- left aligned
control_x(0) <= y_i(y_i'left) = '1';
control_y(0) <= y_i(y_i'left) = '0';
cmp_valid_pipe : pipeline
generic map (
g_width => 1,
g_depth => g_stages)
port map (
data_i(0) => valid_i,
clk_i => clk_i,
ce_i => ce_i,
data_o(0) => valid_o);
CORE_STAGES : for stage in 1 to g_stages generate
--control_x(stage) <= y_inter(stage-1) < 0;
--control_y(stage) <= y_inter(stage-1) > 0;
x_shifted(stage) <= shift_right(x_inter(stage-1), stage-1);
y_shifted(stage) <= shift_right(y_inter(stage-1), stage-1);
cmp_x_stage : addsub
port map(
a_i => x_inter(stage-1),
b_i => y_shifted(stage),
sub_i => control_x(stage-1),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
result_o => x_inter(stage),
positive_o => open,
negative_o => open);
cmp_y_stage : addsub
port map(
a_i => y_inter(stage-1),
b_i => x_shifted(stage),
sub_i => control_y(stage-1),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
result_o => y_inter(stage),
positive_o => control_y(stage),
negative_o => control_x(stage));
cmp_z_stage : addsub
port map (
a_i => z_inter(stage-1),
b_i => stage_constant(1, stage, x_i'length),
sub_i => control_x(stage-1),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
result_o => z_inter(stage),
positive_o => open,
negative_o => open);
end generate;
--TODO: Round the output
x_o <= x_inter(g_stages)(c_width-1 downto g_bit_growth+2);
y_o <= y_inter(g_stages)(c_width-1 downto g_bit_growth+2);
z_o <= z_inter(g_stages);
end architecture str;
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_c7 (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.1; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-11 912 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clksys_outdivide : positive := 9; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clkser_outdivide : positive := 6; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants
constant sys_conf_clksys : integer :=
((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity intra_prediction_node is
generic (
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--debugging
s_intra_idle : out std_logic;
s_intra_data_rxd : out std_logic;
s_intra_write_sample : out std_logic;
s_intra_start_pred : out std_logic;
s_intra_start_tx_loop : out std_logic;
s_intra_start_tx_loop_hold : out std_logic;
s_intra_tx : out std_logic;
s_intra_tx_hold : out std_logic;
s_intra_tx_gen_next : out std_logic;
s_intra_dequeue_rx : out std_logic
);
end entity intra_prediction_node;
architecture fsmd of intra_prediction_node is
---------------------------------------------------------------------------
--- Constants -------------------------------------------------------------
---------------------------------------------------------------------------
constant size_of_byte : integer := 8;
--- for parsing cmd byte --------------------------------------------------
constant cmd_start : integer := 0;
constant cmd_bytes : integer := 1;
constant cmd_end : integer := cmd_start + cmd_bytes * size_of_byte - 1;
--- for parsing set samples command ---------------------------------------
constant wr_addr_start : integer := cmd_end + 1;
constant wr_addr_bytes : integer := 1;
constant wr_addr_end : integer := wr_addr_start + wr_addr_bytes * size_of_byte - 1;
constant samples_start : integer := wr_addr_end + 1;
constant samples_bytes : integer := 4;
constant samples_end : integer := samples_start + samples_bytes * size_of_byte - 1;
--- for parsing perform prediction command --------------------------------
constant block_size_start : integer := cmd_end + 1;
constant block_size_bytes : integer := 1;
constant block_size_end : integer := block_size_start + block_size_bytes * size_of_byte - 1;
constant mode_start : integer := block_size_end + 1;
constant mode_bytes : integer := 1;
constant mode_end : integer := mode_start + mode_bytes * size_of_byte - 1;
constant availible_mask_start : integer := mode_end + 1;
constant availible_mask_bytes : integer := 4;
constant availible_mask_end : integer := availible_mask_start + availible_mask_bytes * size_of_byte - 1;
constant identifier_start : integer := availible_mask_end + 1;
constant identifier_bytes : integer := 1;
constant identifier_end : integer := identifier_start + identifier_bytes * size_of_byte - 1;
--- commands
constant cmd_write_sample : std_logic_vector(7 downto 0) := "00000001";
constant cmd_predict : std_logic_vector(7 downto 0) := "00000010";
--- tx constants ----------------------------------------------------------
constant flit_size : integer := data_width;
constant tx_len_16x16 : integer := 32; --todo --(16*16)/(flit_size/size_of_byte);
constant tx_len_8x8 : integer := 16; --todo --(8*8)/(flit_size/size_of_byte);
constant tx_len_4x4 : integer := 8; --todo --todo
constant tx_loop_max_16x16 : integer := tx_len_16x16;--integer( real(tx_len_16x16) / real(flit_size/size_of_byte) + 0.5 );
constant tx_loop_max_8x8 : integer := tx_len_8x8 ;--integer( real(tx_len_8x8 ) / real(flit_size/size_of_byte) + 0.5 );
constant tx_loop_max_4x4 : integer := tx_len_4x4 ;--integer( real(tx_len_4x4 ) / real(flit_size/size_of_byte) + 0.5 );
constant header_pad_size : integer := 0;
constant header_pad : std_logic_vector := std_logic_vector(to_unsigned(0, header_pad_size));
---------------------------------------------------------------------------
--- Components ------------------------------------------------------------
---------------------------------------------------------------------------
component intra_prediction_core is
port(
clk : in std_logic;
rst : in std_logic;
--interface to enable "set samples" command
sample_data : in std_logic_vector(31 downto 0);
sample_write_addr : in unsigned(7 downto 0);
sample_write_enable : in std_logic;
--interface to enable "perform prediction" command
block_size : in unsigned(7 downto 0);
mode : in unsigned(7 downto 0);
row_addr : in unsigned(7 downto 0);
availible_mask : in std_logic_vector(31 downto 0);
row_data : out unsigned(127 downto 0)
);
end component intra_prediction_core;
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
---------------------------------------------------------------------------
-- Types ------------------------------------------------------------------
---------------------------------------------------------------------------
type intra_node_ctrl_states is ( intra_idle,
intra_data_rxd,
intra_write_sample,
intra_start_pred,
intra_start_tx_loop,
intra_start_tx_loop_hold,
intra_tx,
intra_tx_hold,
intra_tx_gen_next,
intra_tx_gen_next_hold,
intra_dequeue_rx );
---------------------------------------------------------------------------
--- Signals ---------------------------------------------------------------
---------------------------------------------------------------------------
signal sample_data : std_logic_vector(31 downto 0);
signal sample_write_addr : unsigned(7 downto 0);
signal sample_write_enable : std_logic;
signal block_size : unsigned(7 downto 0);
signal mode : unsigned(7 downto 0);
signal row_addr : unsigned(7 downto 0);
signal availible_mask : std_logic_vector(31 downto 0);
signal row_data : unsigned(127 downto 0);
signal wr_sample_data : std_logic;
signal wr_sample_write_addr : std_logic;
signal wr_sample_write_enable : std_logic;
signal wr_block_size : std_logic;
signal wr_mode : std_logic;
signal wr_row_addr : std_logic;
signal wr_availible_mask : std_logic;
signal wr_row_data : std_logic;
signal parsed_cmd : std_logic_vector(7 downto 0);
signal parsed_wr_addr : std_logic_vector(7 downto 0);
signal parsed_samples : std_logic_vector(31 downto 0);
signal parsed_block_size : std_logic_vector(7 downto 0);
signal parsed_mode : std_logic_vector(7 downto 0);
signal parsed_availible_mask : std_logic_vector(31 downto 0);
signal parsed_identifier : std_logic_vector(7 downto 0);
signal tx_loop_count_q : unsigned(7 downto 0);
signal tx_loop_count_d : unsigned(7 downto 0);
signal tx_loop_done : std_logic;
signal last_loop : std_logic;
signal send_data_internal : std_logic_vector(flit_size-1 downto 0);
signal intra_state : intra_node_ctrl_states;
signal next_intra_state : intra_node_ctrl_states;
signal selected_vc_encoder : std_logic_vector(vc_sel_width-1 downto 0);
signal row_seg_full : std_logic_vector(127 downto 0);
signal row_seg : std_logic_vector(flit_size-1 downto 0);
signal selected_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal padded_id : std_logic_vector(31 downto 0);
signal padded_block_size : std_logic_vector(31 downto 0);
begin
---------------------------------------------------------------------------
--- Datapath --------------------------------------------------------------
---------------------------------------------------------------------------
--- instantiate the intra prediction core --------------------------------
core0: component intra_prediction_core port map(
clk => clk ,
rst => rst ,
sample_data => sample_data ,
sample_write_addr => sample_write_addr ,
sample_write_enable => sample_write_enable ,
block_size => block_size ,
mode => mode ,
row_addr => row_addr ,
availible_mask => availible_mask ,
row_data => row_data
);
-- instantiate priority_encoder for vc selection
encoded0: component priority_encoder generic map (
encoded_word_size => vc_sel_width
) Port map(
input => data_in_buffer,
output => selected_vc_encoder
);
--- implement data parser -------------------------------------------------
parsed_cmd <= recv_data(cmd_end downto cmd_start );
parsed_wr_addr <= recv_data(wr_addr_end downto wr_addr_start );
parsed_samples <= recv_data(samples_end downto samples_start );
parsed_block_size <= recv_data(block_size_end downto block_size_start );
parsed_mode <= recv_data(mode_end downto mode_start );
parsed_availible_mask <= recv_data(availible_mask_end downto availible_mask_start);
parsed_identifier <= recv_data(identifier_end downto identifier_start);
--- hook up parsed data to intra prediction core --------------------------
sample_data <= parsed_samples;
sample_write_addr <= unsigned(parsed_wr_addr);
block_size <= unsigned(parsed_block_size);
mode <= unsigned(parsed_mode);
availible_mask <= parsed_availible_mask;
--- data path registers ---------------------------------------------------
dp_regs: process(clk, rst) begin
if rst = '1' then
tx_loop_count_q <= (others => '0');
selected_vc_q <= (others => '0');
elsif rising_edge(clk) then
tx_loop_count_q <= tx_loop_count_d;
selected_vc_q <= selected_vc_d;
end if;
end process;
--- tx loop check ---------------------------------------------------------
tx_loop_done <= '0' when tx_loop_count_q < tx_loop_max_16x16 and block_size = to_unsigned(16, 8) else
'0' when tx_loop_count_q < tx_loop_max_8x8 and block_size = to_unsigned(8, 8) else
'0' when tx_loop_count_q < tx_loop_max_4x4 and block_size = to_unsigned(4, 8) else
'1';
last_loop <= '0' when tx_loop_count_q < (tx_loop_max_16x16 - 1) and block_size = to_unsigned(16, 8) else
'0' when tx_loop_count_q < (tx_loop_max_8x8 - 1) and block_size = to_unsigned(8, 8) else
'0' when tx_loop_count_q < (tx_loop_max_4x4 - 1) and block_size = to_unsigned(4, 8) else
'1';
--- row read address generator --------------------------------------------
-- supports 128, 64, and 32 bit flit data feilds
assert flit_size = 128 or flit_size = 64 or flit_size = 32 report "intra_prediction_node: unsupported flit size" severity failure;
row_addr <= tx_loop_count_q when flit_size = 128 else -- tx's full row per flit
shift_right(tx_loop_count_q, 1) when flit_size = 64 else -- tx's half row per flit
shift_right(tx_loop_count_q, 2) when flit_size = 32 else -- tx's quarter row per flit
(others => '0');
--- row segment selection -------------------------------------------------
row_seg_full <= std_logic_vector(row_data) when flit_size = 128 else
std_logic_vector(to_unsigned(0, 64)) & std_logic_vector(row_data(127 downto 64)) when flit_size = 64 and tx_loop_count_q(0) = '0' else
std_logic_vector(to_unsigned(0, 64)) & std_logic_vector(row_data(63 downto 0)) when flit_size = 64 and tx_loop_count_q(0) = '1' else
std_logic_vector(to_unsigned(0, 96)) & std_logic_vector(row_data(127 downto 96)) when flit_size = 32 and tx_loop_count_q(1 downto 0) = "00" else
std_logic_vector(to_unsigned(0, 96)) & std_logic_vector(row_data(95 downto 64)) when flit_size = 32 and tx_loop_count_q(1 downto 0) = "01" else
std_logic_vector(to_unsigned(0, 96)) & std_logic_vector(row_data(63 downto 32)) when flit_size = 32 and tx_loop_count_q(1 downto 0) = "10" else
std_logic_vector(to_unsigned(0, 96)) & std_logic_vector(row_data(31 downto 0) ) when flit_size = 32 and tx_loop_count_q(1 downto 0) = "11" else
(others => '0');
row_seg <= row_seg_full(flit_size-1 downto 0);
--- misc assignments ------------------------------------------------------
select_vc_read <= selected_vc_q;
padded_id <= std_logic_vector(to_unsigned(0, 24)) & parsed_identifier;
padded_block_size <= std_logic_vector(to_unsigned(0, 24)) & parsed_block_size;
---------------------------------------------------------------------------
--- State Machine ---------------------------------------------------------
---------------------------------------------------------------------------
--- FSM State Register ----------------------------------------------------
state_reg: process(clk, rst) begin
if rst = '1' then
intra_state <= intra_idle;
elsif rising_edge(clk) then
intra_state <= next_intra_state;
end if;
end process;
--- FSM Update Logic ------------------------------------------------------
state_update: process(parsed_cmd, intra_state, tx_loop_done) begin
-- default
next_intra_state <= intra_state;
-- wait for new data to arrive
if intra_state = intra_idle and or_reduce(data_in_buffer) = '1' then
next_intra_state <= intra_data_rxd;
end if;
-- write samples to intra_core
if intra_state = intra_data_rxd and parsed_cmd = cmd_write_sample then
next_intra_state <= intra_write_sample;
end if;
if intra_state = intra_write_sample then
next_intra_state <= intra_dequeue_rx;
end if;
-- perform prediction
if intra_state = intra_data_rxd and parsed_cmd = cmd_predict then
next_intra_state <= intra_start_pred;
end if;
if intra_state = intra_start_pred and ready_to_send = '1' then
next_intra_state <= intra_start_tx_loop;
end if;
--transmit result
if intra_state = intra_start_tx_loop then
next_intra_state <= intra_start_tx_loop_hold;
end if;
if intra_state = intra_start_tx_loop_hold and ready_to_send = '1' then
next_intra_state <= intra_tx;
end if;
if intra_state = intra_tx then
next_intra_state <= intra_tx_hold;
end if;
if intra_state = intra_tx_hold and tx_loop_done = '0' then
next_intra_state <= intra_tx_gen_next;
end if;
if intra_state = intra_tx_hold and tx_loop_done = '1' then
next_intra_state <= intra_dequeue_rx;
end if;
if intra_state = intra_tx_gen_next then
next_intra_state <= intra_tx_gen_next_hold;
end if;
if intra_state = intra_tx_gen_next_hold and ready_to_send = '1' then
next_intra_state <= intra_tx;
end if;
if intra_state = intra_dequeue_rx then
next_intra_state <= intra_idle;
end if;
end process;
--- FSM output logic ------------------------------------------------------
sample_write_enable <= '1' when intra_state = intra_write_sample else '0';
tx_loop_count_d <= (others => '0') when intra_state = intra_start_pred else
tx_loop_count_q + to_unsigned(1, 8) when intra_state = intra_tx else
tx_loop_count_q;
send_data <= header_pad & padded_block_size & padded_id when intra_state = intra_start_tx_loop or intra_state = intra_start_tx_loop_hold else
row_seg;
selected_vc_d <= selected_vc_encoder when intra_state = intra_data_rxd else selected_vc_q;
dequeue <= "01" when selected_vc_q = "0" and intra_state = intra_dequeue_rx else
"10" when selected_vc_q = "1" and intra_state = intra_dequeue_rx else
"00";
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
set_tail_flit <= '1' when last_loop = '1' else '0';
send_flit <= '1' when intra_state = intra_start_tx_loop else
'1' when intra_state = intra_tx else
'0';
--- debug outputs ---------------------------------------------------------
--tx <= '1' when intra_state = intra_start_tx_loop or intra_state = intra_tx else '0';
--rx <= or_reduce(data_in_buffer);
--idle <= '1' when intra_state = intra_idle else '0';
--wr_ing <= '1' when intra_state = intra_write_sample else '0';
--pred_ing <= '1' when intra_state = intra_start_pred or intra_state = intra_tx_gen_next else '0';
s_intra_idle <= '1' when intra_state = intra_idle else '0';
s_intra_data_rxd <= '1' when intra_state = intra_data_rxd else '0';
s_intra_write_sample <= '1' when intra_state = intra_write_sample else '0';
s_intra_start_pred <= '1' when intra_state = intra_start_pred else '0';
s_intra_start_tx_loop <= '1' when intra_state = intra_start_tx_loop else '0';
s_intra_start_tx_loop_hold <= '1' when intra_state = intra_start_tx_loop_hold else '0';
s_intra_tx <= '1' when intra_state = intra_tx else '0';
s_intra_tx_hold <= '1' when intra_state = intra_tx_hold else '0';
s_intra_tx_gen_next <= '1' when intra_state = intra_tx_gen_next else '0';
s_intra_dequeue_rx <= '1' when intra_state = intra_dequeue_rx else '0';
end architecture fsmd; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 16:36:06 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul17_16_stub.vhdl
-- Design : mul17_16
-- Purpose : Stub declaration of top-level module interface
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 16 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 16 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,A[16:0],B[15:0],P[16:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0_12,Vivado 2016.4";
begin
end;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_ok_1_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_ok_1_e-c.vhd,v 1.1 2006/11/22 10:40:10 wig Exp $
-- $Date: 2006/11/22 10:40:10 $
-- $Log: inst_shadow_ok_1_e-c.vhd,v $
-- Revision 1.1 2006/11/22 10:40:10 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_ok_1_rtl_conf / inst_shadow_ok_1_e
--
configuration inst_shadow_ok_1_rtl_conf of inst_shadow_ok_1_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_ok_1_rtl_conf;
--
-- End of Generated Configuration inst_shadow_ok_1_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: utt.fr:hls:doHistStretch:1.0
-- IP Revision: 1606210026
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_doHistStretch_0_0 IS
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END design_1_doHistStretch_0_0;
ARCHITECTURE design_1_doHistStretch_0_0_arch OF design_1_doHistStretch_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_doHistStretch_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT doHistStretch IS
GENERIC (
C_S_AXI_CTRL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_BUS_DATA_WIDTH : INTEGER
);
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT doHistStretch;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TID";
BEGIN
U0 : doHistStretch
GENERIC MAP (
C_S_AXI_CTRL_BUS_ADDR_WIDTH => 5,
C_S_AXI_CTRL_BUS_DATA_WIDTH => 32
)
PORT MAP (
s_axi_CTRL_BUS_AWADDR => s_axi_CTRL_BUS_AWADDR,
s_axi_CTRL_BUS_AWVALID => s_axi_CTRL_BUS_AWVALID,
s_axi_CTRL_BUS_AWREADY => s_axi_CTRL_BUS_AWREADY,
s_axi_CTRL_BUS_WDATA => s_axi_CTRL_BUS_WDATA,
s_axi_CTRL_BUS_WSTRB => s_axi_CTRL_BUS_WSTRB,
s_axi_CTRL_BUS_WVALID => s_axi_CTRL_BUS_WVALID,
s_axi_CTRL_BUS_WREADY => s_axi_CTRL_BUS_WREADY,
s_axi_CTRL_BUS_BRESP => s_axi_CTRL_BUS_BRESP,
s_axi_CTRL_BUS_BVALID => s_axi_CTRL_BUS_BVALID,
s_axi_CTRL_BUS_BREADY => s_axi_CTRL_BUS_BREADY,
s_axi_CTRL_BUS_ARADDR => s_axi_CTRL_BUS_ARADDR,
s_axi_CTRL_BUS_ARVALID => s_axi_CTRL_BUS_ARVALID,
s_axi_CTRL_BUS_ARREADY => s_axi_CTRL_BUS_ARREADY,
s_axi_CTRL_BUS_RDATA => s_axi_CTRL_BUS_RDATA,
s_axi_CTRL_BUS_RRESP => s_axi_CTRL_BUS_RRESP,
s_axi_CTRL_BUS_RVALID => s_axi_CTRL_BUS_RVALID,
s_axi_CTRL_BUS_RREADY => s_axi_CTRL_BUS_RREADY,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
inStream_TVALID => inStream_TVALID,
inStream_TREADY => inStream_TREADY,
inStream_TDATA => inStream_TDATA,
inStream_TDEST => inStream_TDEST,
inStream_TKEEP => inStream_TKEEP,
inStream_TSTRB => inStream_TSTRB,
inStream_TUSER => inStream_TUSER,
inStream_TLAST => inStream_TLAST,
inStream_TID => inStream_TID,
outStream_TVALID => outStream_TVALID,
outStream_TREADY => outStream_TREADY,
outStream_TDATA => outStream_TDATA,
outStream_TDEST => outStream_TDEST,
outStream_TKEEP => outStream_TKEEP,
outStream_TSTRB => outStream_TSTRB,
outStream_TUSER => outStream_TUSER,
outStream_TLAST => outStream_TLAST,
outStream_TID => outStream_TID
);
END design_1_doHistStretch_0_0_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: utt.fr:hls:doHistStretch:1.0
-- IP Revision: 1606210026
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_doHistStretch_0_0 IS
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END design_1_doHistStretch_0_0;
ARCHITECTURE design_1_doHistStretch_0_0_arch OF design_1_doHistStretch_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_doHistStretch_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT doHistStretch IS
GENERIC (
C_S_AXI_CTRL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_BUS_DATA_WIDTH : INTEGER
);
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT doHistStretch;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TID";
BEGIN
U0 : doHistStretch
GENERIC MAP (
C_S_AXI_CTRL_BUS_ADDR_WIDTH => 5,
C_S_AXI_CTRL_BUS_DATA_WIDTH => 32
)
PORT MAP (
s_axi_CTRL_BUS_AWADDR => s_axi_CTRL_BUS_AWADDR,
s_axi_CTRL_BUS_AWVALID => s_axi_CTRL_BUS_AWVALID,
s_axi_CTRL_BUS_AWREADY => s_axi_CTRL_BUS_AWREADY,
s_axi_CTRL_BUS_WDATA => s_axi_CTRL_BUS_WDATA,
s_axi_CTRL_BUS_WSTRB => s_axi_CTRL_BUS_WSTRB,
s_axi_CTRL_BUS_WVALID => s_axi_CTRL_BUS_WVALID,
s_axi_CTRL_BUS_WREADY => s_axi_CTRL_BUS_WREADY,
s_axi_CTRL_BUS_BRESP => s_axi_CTRL_BUS_BRESP,
s_axi_CTRL_BUS_BVALID => s_axi_CTRL_BUS_BVALID,
s_axi_CTRL_BUS_BREADY => s_axi_CTRL_BUS_BREADY,
s_axi_CTRL_BUS_ARADDR => s_axi_CTRL_BUS_ARADDR,
s_axi_CTRL_BUS_ARVALID => s_axi_CTRL_BUS_ARVALID,
s_axi_CTRL_BUS_ARREADY => s_axi_CTRL_BUS_ARREADY,
s_axi_CTRL_BUS_RDATA => s_axi_CTRL_BUS_RDATA,
s_axi_CTRL_BUS_RRESP => s_axi_CTRL_BUS_RRESP,
s_axi_CTRL_BUS_RVALID => s_axi_CTRL_BUS_RVALID,
s_axi_CTRL_BUS_RREADY => s_axi_CTRL_BUS_RREADY,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
inStream_TVALID => inStream_TVALID,
inStream_TREADY => inStream_TREADY,
inStream_TDATA => inStream_TDATA,
inStream_TDEST => inStream_TDEST,
inStream_TKEEP => inStream_TKEEP,
inStream_TSTRB => inStream_TSTRB,
inStream_TUSER => inStream_TUSER,
inStream_TLAST => inStream_TLAST,
inStream_TID => inStream_TID,
outStream_TVALID => outStream_TVALID,
outStream_TREADY => outStream_TREADY,
outStream_TDATA => outStream_TDATA,
outStream_TDEST => outStream_TDEST,
outStream_TKEEP => outStream_TKEEP,
outStream_TSTRB => outStream_TSTRB,
outStream_TUSER => outStream_TUSER,
outStream_TLAST => outStream_TLAST,
outStream_TID => outStream_TID
);
END design_1_doHistStretch_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
package types is
type aes_mode is (ENCRYPT, DECRYPT, EXPAND_KEY);
attribute enum_encoding : string;
attribute enum_encoding of aes_mode : type is "00 01 10";
subtype byte is std_logic_vector(7 downto 0);
subtype state is std_logic_vector(127 downto 0);
subtype word is std_logic_vector(31 downto 0);
type s_list is array(0 to 15) of byte;
type w_list is array(0 to 3) of byte;
type matrix is array(0 to 3, 0 to 3) of byte;
type lut is array(0 to 255) of byte;
function to_state(din : s_list) return state;
function to_state(din : matrix) return state;
function state_column(din : state; i : integer) return word;
function to_word(din : w_list) return word;
function to_s_list(din : state) return s_list;
function to_w_list(din : word) return w_list;
function to_matrix(din : state) return matrix;
end types;
package body types is
function to_state(din : s_list) return state is
variable ret : state;
begin
for i in 0 to 15 loop
ret(128-i*8-1 downto 128-(i+1)*8) := din(i);
end loop;
return ret;
end to_state;
function to_state(din : matrix) return state is
variable ret : state;
variable i : integer;
begin
for row in 0 to 3 loop
for col in 0 to 3 loop
i := row + col * 4;
ret(128-i*8-1 downto 128-(i+1)*8) := din(row, col);
end loop;
end loop;
return ret;
end to_state;
function state_column(din : state; i : integer) return word is
variable ret : word;
begin
ret := din(128-i*32-1 downto 128-(i+1)*32);
return ret;
end state_column;
function to_s_list(din : state) return s_list is
variable ret : s_list;
begin
for i in 0 to 15 loop
ret(i) := din(128-i*8-1 downto 128-(i+1)*8);
end loop;
return ret;
end to_s_list;
function to_word(din : w_list) return word is
variable ret : word;
begin
for i in 0 to 3 loop
ret(32-i*8-1 downto 32-(i+1)*8) := din(i);
end loop;
return ret;
end to_word;
function to_w_list(din : word) return w_list is
variable ret : w_list;
begin
for i in 0 to 3 loop
ret(i) := din(32-i*8-1 downto 32-(i+1)*8);
end loop;
return ret;
end to_w_list;
function to_matrix(din : state) return matrix is
variable ret : matrix;
variable i : integer;
begin
for row in 0 to 3 loop
for col in 0 to 3 loop
i := row + col * 4;
ret(row, col) := din(128-i*8-1 downto 128-(i+1)*8);
end loop;
end loop;
return ret;
end to_matrix;
end types;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2096.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02096ent IS
END c07s02b04x00p20n01i02096ent;
ARCHITECTURE c07s02b04x00p20n01i02096arch OF c07s02b04x00p20n01i02096ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4 is boolean_v (1 to 4);
SUBTYPE boolean_8 is boolean_v (1 to 8);
constant l_operand : boolean_4 := (true,false,true,false);
constant r_operand : boolean_4 := (false,false,true,true);
BEGIN
l : block
generic ( info : boolean_8 );
generic map ( l_operand & r_operand );
begin
assert NOT(info = (true,false,true,false,false,false,true,true))
report "***PASSED TEST: c07s02b04x00p20n01i02096"
severity NOTE;
assert (info = (true,false,true,false,false,false,true,true))
report "***FAILED TEST: c07s02b04x00p20n01i02096 - Constant concatenation did not succeed."
severity ERROR;
end block;
END c07s02b04x00p20n01i02096arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2096.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02096ent IS
END c07s02b04x00p20n01i02096ent;
ARCHITECTURE c07s02b04x00p20n01i02096arch OF c07s02b04x00p20n01i02096ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4 is boolean_v (1 to 4);
SUBTYPE boolean_8 is boolean_v (1 to 8);
constant l_operand : boolean_4 := (true,false,true,false);
constant r_operand : boolean_4 := (false,false,true,true);
BEGIN
l : block
generic ( info : boolean_8 );
generic map ( l_operand & r_operand );
begin
assert NOT(info = (true,false,true,false,false,false,true,true))
report "***PASSED TEST: c07s02b04x00p20n01i02096"
severity NOTE;
assert (info = (true,false,true,false,false,false,true,true))
report "***FAILED TEST: c07s02b04x00p20n01i02096 - Constant concatenation did not succeed."
severity ERROR;
end block;
END c07s02b04x00p20n01i02096arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2096.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02096ent IS
END c07s02b04x00p20n01i02096ent;
ARCHITECTURE c07s02b04x00p20n01i02096arch OF c07s02b04x00p20n01i02096ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4 is boolean_v (1 to 4);
SUBTYPE boolean_8 is boolean_v (1 to 8);
constant l_operand : boolean_4 := (true,false,true,false);
constant r_operand : boolean_4 := (false,false,true,true);
BEGIN
l : block
generic ( info : boolean_8 );
generic map ( l_operand & r_operand );
begin
assert NOT(info = (true,false,true,false,false,false,true,true))
report "***PASSED TEST: c07s02b04x00p20n01i02096"
severity NOTE;
assert (info = (true,false,true,false,false,false,true,true))
report "***FAILED TEST: c07s02b04x00p20n01i02096 - Constant concatenation did not succeed."
severity ERROR;
end block;
END c07s02b04x00p20n01i02096arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb888_to_g8:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb888_to_g8_1_0 IS
PORT (
clk : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
g8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END system_rgb888_to_g8_1_0;
ARCHITECTURE system_rgb888_to_g8_1_0_arch OF system_rgb888_to_g8_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb888_to_g8_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb888_to_g8 IS
PORT (
clk : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
g8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT rgb888_to_g8;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb888_to_g8_1_0_arch: ARCHITECTURE IS "rgb888_to_g8,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb888_to_g8_1_0_arch : ARCHITECTURE IS "system_rgb888_to_g8_1_0,rgb888_to_g8,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb888_to_g8_1_0_arch: ARCHITECTURE IS "system_rgb888_to_g8_1_0,rgb888_to_g8,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb888_to_g8,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb888_to_g8
PORT MAP (
clk => clk,
rgb888 => rgb888,
g8 => g8
);
END system_rgb888_to_g8_1_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb888_to_g8:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb888_to_g8_1_0 IS
PORT (
clk : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
g8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END system_rgb888_to_g8_1_0;
ARCHITECTURE system_rgb888_to_g8_1_0_arch OF system_rgb888_to_g8_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb888_to_g8_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb888_to_g8 IS
PORT (
clk : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
g8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT rgb888_to_g8;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb888_to_g8_1_0_arch: ARCHITECTURE IS "rgb888_to_g8,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb888_to_g8_1_0_arch : ARCHITECTURE IS "system_rgb888_to_g8_1_0,rgb888_to_g8,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb888_to_g8_1_0_arch: ARCHITECTURE IS "system_rgb888_to_g8_1_0,rgb888_to_g8,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb888_to_g8,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb888_to_g8
PORT MAP (
clk => clk,
rgb888 => rgb888,
g8 => g8
);
END system_rgb888_to_g8_1_0_arch;
|
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture arch of ENT00001_Test_Bench is
signal clk : integer := 0;
constant CYCLES : integer := 1000;
begin
main: process(clk)
--{{{
variable a0001 : integer;
variable a0002 : integer;
variable a0003 : integer;
variable a0004 : integer;
variable a0005 : integer;
variable a0006 : integer;
variable a0007 : integer;
variable a0008 : integer;
variable a0009 : integer;
variable a0010 : integer;
variable a0011 : integer;
variable a0012 : integer;
variable a0013 : integer;
variable a0014 : integer;
variable a0015 : integer;
variable a0016 : integer;
variable a0017 : integer;
variable a0018 : integer;
variable a0019 : integer;
variable a0020 : integer;
variable a0021 : integer;
variable a0022 : integer;
variable a0023 : integer;
variable a0024 : integer;
variable a0025 : integer;
variable a0026 : integer;
variable a0027 : integer;
variable a0028 : integer;
variable a0029 : integer;
variable a0030 : integer;
variable a0031 : integer;
variable a0032 : integer;
variable a0033 : integer;
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variable a0035 : integer;
variable a0036 : integer;
variable a0037 : integer;
variable a0038 : integer;
variable a0039 : integer;
variable a0040 : integer;
variable a0041 : integer;
variable a0042 : integer;
variable a0043 : integer;
variable a0044 : integer;
variable a0045 : integer;
variable a0046 : integer;
variable a0047 : integer;
variable a0048 : integer;
variable a0049 : integer;
variable a0050 : integer;
variable a0051 : integer;
variable a0052 : integer;
variable a0053 : integer;
variable a0054 : integer;
variable a0055 : integer;
variable a0056 : integer;
variable a0057 : integer;
variable a0058 : integer;
variable a0059 : integer;
variable a0060 : integer;
variable a0061 : integer;
variable a0062 : integer;
variable a0063 : integer;
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variable a0065 : integer;
variable a0066 : integer;
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variable a0069 : integer;
variable a0070 : integer;
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variable a0075 : integer;
variable a0076 : integer;
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variable a0078 : integer;
variable a0079 : integer;
variable a0080 : integer;
variable a0081 : integer;
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variable a0870 : integer;
variable a0871 : integer;
variable a0872 : integer;
variable a0873 : integer;
variable a0874 : integer;
variable a0875 : integer;
variable a0876 : integer;
variable a0877 : integer;
variable a0878 : integer;
variable a0879 : integer;
variable a0880 : integer;
variable a0881 : integer;
variable a0882 : integer;
variable a0883 : integer;
variable a0884 : integer;
variable a0885 : integer;
variable a0886 : integer;
variable a0887 : integer;
variable a0888 : integer;
variable a0889 : integer;
variable a0890 : integer;
variable a0891 : integer;
variable a0892 : integer;
variable a0893 : integer;
variable a0894 : integer;
variable a0895 : integer;
variable a0896 : integer;
variable a0897 : integer;
variable a0898 : integer;
variable a0899 : integer;
variable a0900 : integer;
variable a0901 : integer;
variable a0902 : integer;
variable a0903 : integer;
variable a0904 : integer;
variable a0905 : integer;
variable a0906 : integer;
variable a0907 : integer;
variable a0908 : integer;
variable a0909 : integer;
variable a0910 : integer;
variable a0911 : integer;
variable a0912 : integer;
variable a0913 : integer;
variable a0914 : integer;
variable a0915 : integer;
variable a0916 : integer;
variable a0917 : integer;
variable a0918 : integer;
variable a0919 : integer;
variable a0920 : integer;
variable a0921 : integer;
variable a0922 : integer;
variable a0923 : integer;
variable a0924 : integer;
variable a0925 : integer;
variable a0926 : integer;
variable a0927 : integer;
variable a0928 : integer;
variable a0929 : integer;
variable a0930 : integer;
variable a0931 : integer;
variable a0932 : integer;
variable a0933 : integer;
variable a0934 : integer;
variable a0935 : integer;
variable a0936 : integer;
variable a0937 : integer;
variable a0938 : integer;
variable a0939 : integer;
variable a0940 : integer;
variable a0941 : integer;
variable a0942 : integer;
variable a0943 : integer;
variable a0944 : integer;
variable a0945 : integer;
variable a0946 : integer;
variable a0947 : integer;
variable a0948 : integer;
variable a0949 : integer;
variable a0950 : integer;
variable a0951 : integer;
variable a0952 : integer;
variable a0953 : integer;
variable a0954 : integer;
variable a0955 : integer;
variable a0956 : integer;
variable a0957 : integer;
variable a0958 : integer;
variable a0959 : integer;
variable a0960 : integer;
variable a0961 : integer;
variable a0962 : integer;
variable a0963 : integer;
variable a0964 : integer;
variable a0965 : integer;
variable a0966 : integer;
variable a0967 : integer;
variable a0968 : integer;
variable a0969 : integer;
variable a0970 : integer;
variable a0971 : integer;
variable a0972 : integer;
variable a0973 : integer;
variable a0974 : integer;
variable a0975 : integer;
variable a0976 : integer;
variable a0977 : integer;
variable a0978 : integer;
variable a0979 : integer;
variable a0980 : integer;
variable a0981 : integer;
variable a0982 : integer;
variable a0983 : integer;
variable a0984 : integer;
variable a0985 : integer;
variable a0986 : integer;
variable a0987 : integer;
variable a0988 : integer;
variable a0989 : integer;
variable a0990 : integer;
variable a0991 : integer;
variable a0992 : integer;
variable a0993 : integer;
variable a0994 : integer;
variable a0995 : integer;
variable a0996 : integer;
variable a0997 : integer;
variable a0998 : integer;
variable a0999 : integer;
variable a1000 : integer;
begin
a0001 := 1;
a0002 := 2;
a0003 := 3;
a0004 := 4;
a0005 := 5;
a0006 := 6;
a0007 := 7;
a0008 := 8;
a0009 := 9;
a0010 := 10;
a0011 := 11;
a0012 := 12;
a0013 := 13;
a0014 := 14;
a0015 := 15;
a0016 := 16;
a0017 := 17;
a0018 := 18;
a0019 := 19;
a0020 := 20;
a0021 := 21;
a0022 := 22;
a0023 := 23;
a0024 := 24;
a0025 := 25;
a0026 := 26;
a0027 := 27;
a0028 := 28;
a0029 := 29;
a0030 := 30;
a0031 := 31;
a0032 := 32;
a0033 := 33;
a0034 := 34;
a0035 := 35;
a0036 := 36;
a0037 := 37;
a0038 := 38;
a0039 := 39;
a0040 := 40;
a0041 := 41;
a0042 := 42;
a0043 := 43;
a0044 := 44;
a0045 := 45;
a0046 := 46;
a0047 := 47;
a0048 := 48;
a0049 := 49;
a0050 := 50;
a0051 := 51;
a0052 := 52;
a0053 := 53;
a0054 := 54;
a0055 := 55;
a0056 := 56;
a0057 := 57;
a0058 := 58;
a0059 := 59;
a0060 := 60;
a0061 := 61;
a0062 := 62;
a0063 := 63;
a0064 := 64;
a0065 := 65;
a0066 := 66;
a0067 := 67;
a0068 := 68;
a0069 := 69;
a0070 := 70;
a0071 := 71;
a0072 := 72;
a0073 := 73;
a0074 := 74;
a0075 := 75;
a0076 := 76;
a0077 := 77;
a0078 := 78;
a0079 := 79;
a0080 := 80;
a0081 := 81;
a0082 := 82;
a0083 := 83;
a0084 := 84;
a0085 := 85;
a0086 := 86;
a0087 := 87;
a0088 := 88;
a0089 := 89;
a0090 := 90;
a0091 := 91;
a0092 := 92;
a0093 := 93;
a0094 := 94;
a0095 := 95;
a0096 := 96;
a0097 := 97;
a0098 := 98;
a0099 := 99;
a0100 := 100;
a0101 := 101;
a0102 := 102;
a0103 := 103;
a0104 := 104;
a0105 := 105;
a0106 := 106;
a0107 := 107;
a0108 := 108;
a0109 := 109;
a0110 := 110;
a0111 := 111;
a0112 := 112;
a0113 := 113;
a0114 := 114;
a0115 := 115;
a0116 := 116;
a0117 := 117;
a0118 := 118;
a0119 := 119;
a0120 := 120;
a0121 := 121;
a0122 := 122;
a0123 := 123;
a0124 := 124;
a0125 := 125;
a0126 := 126;
a0127 := 127;
a0128 := 128;
a0129 := 129;
a0130 := 130;
a0131 := 131;
a0132 := 132;
a0133 := 133;
a0134 := 134;
a0135 := 135;
a0136 := 136;
a0137 := 137;
a0138 := 138;
a0139 := 139;
a0140 := 140;
a0141 := 141;
a0142 := 142;
a0143 := 143;
a0144 := 144;
a0145 := 145;
a0146 := 146;
a0147 := 147;
a0148 := 148;
a0149 := 149;
a0150 := 150;
a0151 := 151;
a0152 := 152;
a0153 := 153;
a0154 := 154;
a0155 := 155;
a0156 := 156;
a0157 := 157;
a0158 := 158;
a0159 := 159;
a0160 := 160;
a0161 := 161;
a0162 := 162;
a0163 := 163;
a0164 := 164;
a0165 := 165;
a0166 := 166;
a0167 := 167;
a0168 := 168;
a0169 := 169;
a0170 := 170;
a0171 := 171;
a0172 := 172;
a0173 := 173;
a0174 := 174;
a0175 := 175;
a0176 := 176;
a0177 := 177;
a0178 := 178;
a0179 := 179;
a0180 := 180;
a0181 := 181;
a0182 := 182;
a0183 := 183;
a0184 := 184;
a0185 := 185;
a0186 := 186;
a0187 := 187;
a0188 := 188;
a0189 := 189;
a0190 := 190;
a0191 := 191;
a0192 := 192;
a0193 := 193;
a0194 := 194;
a0195 := 195;
a0196 := 196;
a0197 := 197;
a0198 := 198;
a0199 := 199;
a0200 := 200;
a0201 := 201;
a0202 := 202;
a0203 := 203;
a0204 := 204;
a0205 := 205;
a0206 := 206;
a0207 := 207;
a0208 := 208;
a0209 := 209;
a0210 := 210;
a0211 := 211;
a0212 := 212;
a0213 := 213;
a0214 := 214;
a0215 := 215;
a0216 := 216;
a0217 := 217;
a0218 := 218;
a0219 := 219;
a0220 := 220;
a0221 := 221;
a0222 := 222;
a0223 := 223;
a0224 := 224;
a0225 := 225;
a0226 := 226;
a0227 := 227;
a0228 := 228;
a0229 := 229;
a0230 := 230;
a0231 := 231;
a0232 := 232;
a0233 := 233;
a0234 := 234;
a0235 := 235;
a0236 := 236;
a0237 := 237;
a0238 := 238;
a0239 := 239;
a0240 := 240;
a0241 := 241;
a0242 := 242;
a0243 := 243;
a0244 := 244;
a0245 := 245;
a0246 := 246;
a0247 := 247;
a0248 := 248;
a0249 := 249;
a0250 := 250;
a0251 := 251;
a0252 := 252;
a0253 := 253;
a0254 := 254;
a0255 := 255;
a0256 := 256;
a0257 := 257;
a0258 := 258;
a0259 := 259;
a0260 := 260;
a0261 := 261;
a0262 := 262;
a0263 := 263;
a0264 := 264;
a0265 := 265;
a0266 := 266;
a0267 := 267;
a0268 := 268;
a0269 := 269;
a0270 := 270;
a0271 := 271;
a0272 := 272;
a0273 := 273;
a0274 := 274;
a0275 := 275;
a0276 := 276;
a0277 := 277;
a0278 := 278;
a0279 := 279;
a0280 := 280;
a0281 := 281;
a0282 := 282;
a0283 := 283;
a0284 := 284;
a0285 := 285;
a0286 := 286;
a0287 := 287;
a0288 := 288;
a0289 := 289;
a0290 := 290;
a0291 := 291;
a0292 := 292;
a0293 := 293;
a0294 := 294;
a0295 := 295;
a0296 := 296;
a0297 := 297;
a0298 := 298;
a0299 := 299;
a0300 := 300;
a0301 := 301;
a0302 := 302;
a0303 := 303;
a0304 := 304;
a0305 := 305;
a0306 := 306;
a0307 := 307;
a0308 := 308;
a0309 := 309;
a0310 := 310;
a0311 := 311;
a0312 := 312;
a0313 := 313;
a0314 := 314;
a0315 := 315;
a0316 := 316;
a0317 := 317;
a0318 := 318;
a0319 := 319;
a0320 := 320;
a0321 := 321;
a0322 := 322;
a0323 := 323;
a0324 := 324;
a0325 := 325;
a0326 := 326;
a0327 := 327;
a0328 := 328;
a0329 := 329;
a0330 := 330;
a0331 := 331;
a0332 := 332;
a0333 := 333;
a0334 := 334;
a0335 := 335;
a0336 := 336;
a0337 := 337;
a0338 := 338;
a0339 := 339;
a0340 := 340;
a0341 := 341;
a0342 := 342;
a0343 := 343;
a0344 := 344;
a0345 := 345;
a0346 := 346;
a0347 := 347;
a0348 := 348;
a0349 := 349;
a0350 := 350;
a0351 := 351;
a0352 := 352;
a0353 := 353;
a0354 := 354;
a0355 := 355;
a0356 := 356;
a0357 := 357;
a0358 := 358;
a0359 := 359;
a0360 := 360;
a0361 := 361;
a0362 := 362;
a0363 := 363;
a0364 := 364;
a0365 := 365;
a0366 := 366;
a0367 := 367;
a0368 := 368;
a0369 := 369;
a0370 := 370;
a0371 := 371;
a0372 := 372;
a0373 := 373;
a0374 := 374;
a0375 := 375;
a0376 := 376;
a0377 := 377;
a0378 := 378;
a0379 := 379;
a0380 := 380;
a0381 := 381;
a0382 := 382;
a0383 := 383;
a0384 := 384;
a0385 := 385;
a0386 := 386;
a0387 := 387;
a0388 := 388;
a0389 := 389;
a0390 := 390;
a0391 := 391;
a0392 := 392;
a0393 := 393;
a0394 := 394;
a0395 := 395;
a0396 := 396;
a0397 := 397;
a0398 := 398;
a0399 := 399;
a0400 := 400;
a0401 := 401;
a0402 := 402;
a0403 := 403;
a0404 := 404;
a0405 := 405;
a0406 := 406;
a0407 := 407;
a0408 := 408;
a0409 := 409;
a0410 := 410;
a0411 := 411;
a0412 := 412;
a0413 := 413;
a0414 := 414;
a0415 := 415;
a0416 := 416;
a0417 := 417;
a0418 := 418;
a0419 := 419;
a0420 := 420;
a0421 := 421;
a0422 := 422;
a0423 := 423;
a0424 := 424;
a0425 := 425;
a0426 := 426;
a0427 := 427;
a0428 := 428;
a0429 := 429;
a0430 := 430;
a0431 := 431;
a0432 := 432;
a0433 := 433;
a0434 := 434;
a0435 := 435;
a0436 := 436;
a0437 := 437;
a0438 := 438;
a0439 := 439;
a0440 := 440;
a0441 := 441;
a0442 := 442;
a0443 := 443;
a0444 := 444;
a0445 := 445;
a0446 := 446;
a0447 := 447;
a0448 := 448;
a0449 := 449;
a0450 := 450;
a0451 := 451;
a0452 := 452;
a0453 := 453;
a0454 := 454;
a0455 := 455;
a0456 := 456;
a0457 := 457;
a0458 := 458;
a0459 := 459;
a0460 := 460;
a0461 := 461;
a0462 := 462;
a0463 := 463;
a0464 := 464;
a0465 := 465;
a0466 := 466;
a0467 := 467;
a0468 := 468;
a0469 := 469;
a0470 := 470;
a0471 := 471;
a0472 := 472;
a0473 := 473;
a0474 := 474;
a0475 := 475;
a0476 := 476;
a0477 := 477;
a0478 := 478;
a0479 := 479;
a0480 := 480;
a0481 := 481;
a0482 := 482;
a0483 := 483;
a0484 := 484;
a0485 := 485;
a0486 := 486;
a0487 := 487;
a0488 := 488;
a0489 := 489;
a0490 := 490;
a0491 := 491;
a0492 := 492;
a0493 := 493;
a0494 := 494;
a0495 := 495;
a0496 := 496;
a0497 := 497;
a0498 := 498;
a0499 := 499;
a0500 := 500;
a0501 := 501;
a0502 := 502;
a0503 := 503;
a0504 := 504;
a0505 := 505;
a0506 := 506;
a0507 := 507;
a0508 := 508;
a0509 := 509;
a0510 := 510;
a0511 := 511;
a0512 := 512;
a0513 := 513;
a0514 := 514;
a0515 := 515;
a0516 := 516;
a0517 := 517;
a0518 := 518;
a0519 := 519;
a0520 := 520;
a0521 := 521;
a0522 := 522;
a0523 := 523;
a0524 := 524;
a0525 := 525;
a0526 := 526;
a0527 := 527;
a0528 := 528;
a0529 := 529;
a0530 := 530;
a0531 := 531;
a0532 := 532;
a0533 := 533;
a0534 := 534;
a0535 := 535;
a0536 := 536;
a0537 := 537;
a0538 := 538;
a0539 := 539;
a0540 := 540;
a0541 := 541;
a0542 := 542;
a0543 := 543;
a0544 := 544;
a0545 := 545;
a0546 := 546;
a0547 := 547;
a0548 := 548;
a0549 := 549;
a0550 := 550;
a0551 := 551;
a0552 := 552;
a0553 := 553;
a0554 := 554;
a0555 := 555;
a0556 := 556;
a0557 := 557;
a0558 := 558;
a0559 := 559;
a0560 := 560;
a0561 := 561;
a0562 := 562;
a0563 := 563;
a0564 := 564;
a0565 := 565;
a0566 := 566;
a0567 := 567;
a0568 := 568;
a0569 := 569;
a0570 := 570;
a0571 := 571;
a0572 := 572;
a0573 := 573;
a0574 := 574;
a0575 := 575;
a0576 := 576;
a0577 := 577;
a0578 := 578;
a0579 := 579;
a0580 := 580;
a0581 := 581;
a0582 := 582;
a0583 := 583;
a0584 := 584;
a0585 := 585;
a0586 := 586;
a0587 := 587;
a0588 := 588;
a0589 := 589;
a0590 := 590;
a0591 := 591;
a0592 := 592;
a0593 := 593;
a0594 := 594;
a0595 := 595;
a0596 := 596;
a0597 := 597;
a0598 := 598;
a0599 := 599;
a0600 := 600;
a0601 := 601;
a0602 := 602;
a0603 := 603;
a0604 := 604;
a0605 := 605;
a0606 := 606;
a0607 := 607;
a0608 := 608;
a0609 := 609;
a0610 := 610;
a0611 := 611;
a0612 := 612;
a0613 := 613;
a0614 := 614;
a0615 := 615;
a0616 := 616;
a0617 := 617;
a0618 := 618;
a0619 := 619;
a0620 := 620;
a0621 := 621;
a0622 := 622;
a0623 := 623;
a0624 := 624;
a0625 := 625;
a0626 := 626;
a0627 := 627;
a0628 := 628;
a0629 := 629;
a0630 := 630;
a0631 := 631;
a0632 := 632;
a0633 := 633;
a0634 := 634;
a0635 := 635;
a0636 := 636;
a0637 := 637;
a0638 := 638;
a0639 := 639;
a0640 := 640;
a0641 := 641;
a0642 := 642;
a0643 := 643;
a0644 := 644;
a0645 := 645;
a0646 := 646;
a0647 := 647;
a0648 := 648;
a0649 := 649;
a0650 := 650;
a0651 := 651;
a0652 := 652;
a0653 := 653;
a0654 := 654;
a0655 := 655;
a0656 := 656;
a0657 := 657;
a0658 := 658;
a0659 := 659;
a0660 := 660;
a0661 := 661;
a0662 := 662;
a0663 := 663;
a0664 := 664;
a0665 := 665;
a0666 := 666;
a0667 := 667;
a0668 := 668;
a0669 := 669;
a0670 := 670;
a0671 := 671;
a0672 := 672;
a0673 := 673;
a0674 := 674;
a0675 := 675;
a0676 := 676;
a0677 := 677;
a0678 := 678;
a0679 := 679;
a0680 := 680;
a0681 := 681;
a0682 := 682;
a0683 := 683;
a0684 := 684;
a0685 := 685;
a0686 := 686;
a0687 := 687;
a0688 := 688;
a0689 := 689;
a0690 := 690;
a0691 := 691;
a0692 := 692;
a0693 := 693;
a0694 := 694;
a0695 := 695;
a0696 := 696;
a0697 := 697;
a0698 := 698;
a0699 := 699;
a0700 := 700;
a0701 := 701;
a0702 := 702;
a0703 := 703;
a0704 := 704;
a0705 := 705;
a0706 := 706;
a0707 := 707;
a0708 := 708;
a0709 := 709;
a0710 := 710;
a0711 := 711;
a0712 := 712;
a0713 := 713;
a0714 := 714;
a0715 := 715;
a0716 := 716;
a0717 := 717;
a0718 := 718;
a0719 := 719;
a0720 := 720;
a0721 := 721;
a0722 := 722;
a0723 := 723;
a0724 := 724;
a0725 := 725;
a0726 := 726;
a0727 := 727;
a0728 := 728;
a0729 := 729;
a0730 := 730;
a0731 := 731;
a0732 := 732;
a0733 := 733;
a0734 := 734;
a0735 := 735;
a0736 := 736;
a0737 := 737;
a0738 := 738;
a0739 := 739;
a0740 := 740;
a0741 := 741;
a0742 := 742;
a0743 := 743;
a0744 := 744;
a0745 := 745;
a0746 := 746;
a0747 := 747;
a0748 := 748;
a0749 := 749;
a0750 := 750;
a0751 := 751;
a0752 := 752;
a0753 := 753;
a0754 := 754;
a0755 := 755;
a0756 := 756;
a0757 := 757;
a0758 := 758;
a0759 := 759;
a0760 := 760;
a0761 := 761;
a0762 := 762;
a0763 := 763;
a0764 := 764;
a0765 := 765;
a0766 := 766;
a0767 := 767;
a0768 := 768;
a0769 := 769;
a0770 := 770;
a0771 := 771;
a0772 := 772;
a0773 := 773;
a0774 := 774;
a0775 := 775;
a0776 := 776;
a0777 := 777;
a0778 := 778;
a0779 := 779;
a0780 := 780;
a0781 := 781;
a0782 := 782;
a0783 := 783;
a0784 := 784;
a0785 := 785;
a0786 := 786;
a0787 := 787;
a0788 := 788;
a0789 := 789;
a0790 := 790;
a0791 := 791;
a0792 := 792;
a0793 := 793;
a0794 := 794;
a0795 := 795;
a0796 := 796;
a0797 := 797;
a0798 := 798;
a0799 := 799;
a0800 := 800;
a0801 := 801;
a0802 := 802;
a0803 := 803;
a0804 := 804;
a0805 := 805;
a0806 := 806;
a0807 := 807;
a0808 := 808;
a0809 := 809;
a0810 := 810;
a0811 := 811;
a0812 := 812;
a0813 := 813;
a0814 := 814;
a0815 := 815;
a0816 := 816;
a0817 := 817;
a0818 := 818;
a0819 := 819;
a0820 := 820;
a0821 := 821;
a0822 := 822;
a0823 := 823;
a0824 := 824;
a0825 := 825;
a0826 := 826;
a0827 := 827;
a0828 := 828;
a0829 := 829;
a0830 := 830;
a0831 := 831;
a0832 := 832;
a0833 := 833;
a0834 := 834;
a0835 := 835;
a0836 := 836;
a0837 := 837;
a0838 := 838;
a0839 := 839;
a0840 := 840;
a0841 := 841;
a0842 := 842;
a0843 := 843;
a0844 := 844;
a0845 := 845;
a0846 := 846;
a0847 := 847;
a0848 := 848;
a0849 := 849;
a0850 := 850;
a0851 := 851;
a0852 := 852;
a0853 := 853;
a0854 := 854;
a0855 := 855;
a0856 := 856;
a0857 := 857;
a0858 := 858;
a0859 := 859;
a0860 := 860;
a0861 := 861;
a0862 := 862;
a0863 := 863;
a0864 := 864;
a0865 := 865;
a0866 := 866;
a0867 := 867;
a0868 := 868;
a0869 := 869;
a0870 := 870;
a0871 := 871;
a0872 := 872;
a0873 := 873;
a0874 := 874;
a0875 := 875;
a0876 := 876;
a0877 := 877;
a0878 := 878;
a0879 := 879;
a0880 := 880;
a0881 := 881;
a0882 := 882;
a0883 := 883;
a0884 := 884;
a0885 := 885;
a0886 := 886;
a0887 := 887;
a0888 := 888;
a0889 := 889;
a0890 := 890;
a0891 := 891;
a0892 := 892;
a0893 := 893;
a0894 := 894;
a0895 := 895;
a0896 := 896;
a0897 := 897;
a0898 := 898;
a0899 := 899;
a0900 := 900;
a0901 := 901;
a0902 := 902;
a0903 := 903;
a0904 := 904;
a0905 := 905;
a0906 := 906;
a0907 := 907;
a0908 := 908;
a0909 := 909;
a0910 := 910;
a0911 := 911;
a0912 := 912;
a0913 := 913;
a0914 := 914;
a0915 := 915;
a0916 := 916;
a0917 := 917;
a0918 := 918;
a0919 := 919;
a0920 := 920;
a0921 := 921;
a0922 := 922;
a0923 := 923;
a0924 := 924;
a0925 := 925;
a0926 := 926;
a0927 := 927;
a0928 := 928;
a0929 := 929;
a0930 := 930;
a0931 := 931;
a0932 := 932;
a0933 := 933;
a0934 := 934;
a0935 := 935;
a0936 := 936;
a0937 := 937;
a0938 := 938;
a0939 := 939;
a0940 := 940;
a0941 := 941;
a0942 := 942;
a0943 := 943;
a0944 := 944;
a0945 := 945;
a0946 := 946;
a0947 := 947;
a0948 := 948;
a0949 := 949;
a0950 := 950;
a0951 := 951;
a0952 := 952;
a0953 := 953;
a0954 := 954;
a0955 := 955;
a0956 := 956;
a0957 := 957;
a0958 := 958;
a0959 := 959;
a0960 := 960;
a0961 := 961;
a0962 := 962;
a0963 := 963;
a0964 := 964;
a0965 := 965;
a0966 := 966;
a0967 := 967;
a0968 := 968;
a0969 := 969;
a0970 := 970;
a0971 := 971;
a0972 := 972;
a0973 := 973;
a0974 := 974;
a0975 := 975;
a0976 := 976;
a0977 := 977;
a0978 := 978;
a0979 := 979;
a0980 := 980;
a0981 := 981;
a0982 := 982;
a0983 := 983;
a0984 := 984;
a0985 := 985;
a0986 := 986;
a0987 := 987;
a0988 := 988;
a0989 := 989;
a0990 := 990;
a0991 := 991;
a0992 := 992;
a0993 := 993;
a0994 := 994;
a0995 := 995;
a0996 := 996;
a0997 := 997;
a0998 := 998;
a0999 := 999;
a1000 := 1000;
-- report "tick";
--}}}
end process;
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
-- else
-- report "tick";
end if;
end process;
clk <= (clk+1) after 1 us;
end;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net4
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net4
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net5,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
W => Wsrc_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => net3,
N => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
W => Wsrc_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => out1,
N => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net3
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
|
-- NEED RESULT: ARCH00495: Aggregates with others choice in signal assignment (locally static) passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00495
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2.2 (6)
-- 7.3.2.2 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00495(ARCH00495)
-- ENT00495_Test_Bench(ARCH00495_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00495 is
generic (
constant g_a11 : boolean := false ;
constant g_a12 : boolean := true ;
constant g_a21 : integer := 1 ;
constant g_a22 : integer := 5 ;
constant g_b11 : integer := 0 ;
constant g_b12 : integer := 0 ;
constant g_b21 : integer := -5 ;
constant g_b22 : integer := -3 ;
constant g_c1 : integer := 0 ;
constant g_c2 : integer := 4 ;
constant g_d1 : integer := 3 ;
constant g_d2 : integer := 5 ;
constant g_r1 : integer := 1
) ;
constant r1 : integer := 1 ;
constant a11 : boolean := false ;
constant a12 : boolean := true ;
constant a21 : integer := 1 ;
constant a22 : integer := 5 ;
constant b11 : integer := 0 ;
constant b12 : integer := 0 ;
constant b21 : integer := -5 ;
constant b22 : integer := -3 ;
constant c1 : integer := 0 ;
constant c2 : integer := 4 ;
constant d1 : integer := 3 ;
constant d2 : integer := 5 ;
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - r1 to r1 ;
-- f2 : rec_arr (-r1 to r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-r1 to r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range a11 to a12 ;
subtype arange2 is integer range a21 to a22 ;
subtype brange1 is integer range b11 to b12 ;
subtype brange2 is integer range b21 to b22 ;
subtype crange is integer range c1 to c2 ;
subtype drange is integer range d1 to d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
--
end ENT00495 ;
--
architecture ARCH00495 of ENT00495 is
begin
B1 :
block
signal s_arr_1 : st_arr_1 ;
signal s_time_matrix : st_time_matrix ;
signal s_bit_vector : st_bit_vector ;
signal s_string : st_string ;
signal s_rec_1 : rec_1 ;
signal toggle : boolean := false ;
--
begin
process
variable v_arr_1 : st_arr_1 ;
variable v_time_matrix : st_time_matrix ;
variable v_bit_vector : st_bit_vector ;
variable v_string : st_string ;
variable v_rec_1 : rec_1 ;
variable bool : boolean := true ;
--
begin
s_arr_1 <=
( ( c_rec_1_1, others => c_rec_1_2 ),
others => (others => c_rec_1_1) ) ;
s_time_matrix <=
( st_time_matrix'right(1) =>
( st_time_matrix'right(2) => 10 ns, others => 5 fs),
others => (brange2'left => 10 ps, others => 15ms) ) ;
s_bit_vector <=
( 0 => '1', 2 => '1', others => '0' ) ;
s_string <=
( 3 => 'a', 4 => 'b', others => '0' ) ;
s_rec_1 <=
-- ( f2 => (r1 => true, others => false), f3 => 1, others => 0) ;
( f3 => 1, others => 0) ;
v_arr_1 :=
( ( c_rec_1_1, others => c_rec_1_2 ),
others => (others => c_rec_1_1) ) ;
v_time_matrix :=
( st_time_matrix'right(1) =>
( st_time_matrix'right(2) => 10 ns, others => 5 fs),
others => (brange2'left => 10 ps, others => 15ms) ) ;
v_bit_vector :=
( 0 => '1', 2 => '1', others => '0' ) ;
v_string :=
( 3 => 'a', 4 => 'b', others => '0' ) ;
v_rec_1 :=
-- ( f2 => (r1 => true, others => false), f3 => 1, others => 0) ;
( f3 => 1, others => 0) ;
bool := bool and v_arr_1(false, 1) = c_rec_1_1 ;
for i in 2 to 5 loop
bool := bool and v_arr_1(false, i) = c_rec_1_2 ;
end loop ;
for i in 1 to 5 loop
bool := bool and v_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
bool := bool and v_time_matrix(0, -3) = 10 ns ;
for i in integer'(-5) to -4 loop
bool := bool and v_time_matrix(0, i) = 5 fs ;
end loop ;
--
bool := bool and v_bit_vector = B"10100" ;
--
bool := bool and v_string = "ab0" ;
--
bool := bool and v_rec_1.f1 = 0 and v_rec_1.f4 = 0
and v_rec_1.f3 = 1 ;
-- bool := bool and v_rec_1.f2(1) = true
-- and v_rec_1.f2(0) = false and
-- v_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00495" ,
"Aggregates with others choice in signal assignment"
& " (locally static)" ,
bool ) ;
wait ;
end process ;
process ( toggle )
variable bool : boolean := true ;
begin
if toggle then
bool := bool and s_arr_1(false, 1) = c_rec_1_1 ;
for i in 2 to 5 loop
bool := bool and s_arr_1(false, i) = c_rec_1_2 ;
end loop ;
for i in 1 to 5 loop
bool := bool and s_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
bool := bool and s_time_matrix(0, -3) = 10 ns ;
for i in integer'(-5) to -4 loop
bool := bool and s_time_matrix(0, i) = 5 fs ;
end loop ;
--
bool := bool and s_bit_vector = B"10100" ;
--
bool := bool and s_string = "ab0" ;
--
bool := bool and s_rec_1.f1 = 0 and s_rec_1.f4 = 0
and s_rec_1.f3 = 1 ;
-- bool := bool and s_rec_1.f2(1) = true
-- and s_rec_1.f2(0) = false and
-- s_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00495" ,
"Aggregates with others choice in variable assignment"
& " (locally static)" ,
bool ) ;
end if ;
end process ;
end block B1 ;
end ARCH00495 ;
--
entity ENT00495_Test_Bench is
end ENT00495_Test_Bench ;
--
architecture ARCH00495_Test_Bench of ENT00495_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00495 ( ARCH00495 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00495_Test_Bench ;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_ch_18_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_18_10 is
end entity ch_18_10;
----------------------------------------------------------------
architecture test of ch_18_10 is
begin
process is
use std.textio.all;
variable L : line;
-- code from book:
type speed_category is (stopped, slow, fast, maniacal);
variable speed : speed_category;
-- end of code from book
begin
speed := stopped;
-- code from book:
write ( L, speed_category'image(speed) );
-- end of code from book
writeline(output, L);
speed := slow;
write ( L, speed_category'image(speed) );
writeline(output, L);
speed := fast;
write ( L, speed_category'image(speed) );
writeline(output, L);
speed := maniacal;
write ( L, speed_category'image(speed) );
writeline(output, L);
-- code from book:
readline( input, L );
speed := speed_category'value(L.all);
-- end of code from book
wait;
end process;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_ch_18_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_18_10 is
end entity ch_18_10;
----------------------------------------------------------------
architecture test of ch_18_10 is
begin
process is
use std.textio.all;
variable L : line;
-- code from book:
type speed_category is (stopped, slow, fast, maniacal);
variable speed : speed_category;
-- end of code from book
begin
speed := stopped;
-- code from book:
write ( L, speed_category'image(speed) );
-- end of code from book
writeline(output, L);
speed := slow;
write ( L, speed_category'image(speed) );
writeline(output, L);
speed := fast;
write ( L, speed_category'image(speed) );
writeline(output, L);
speed := maniacal;
write ( L, speed_category'image(speed) );
writeline(output, L);
-- code from book:
readline( input, L );
speed := speed_category'value(L.all);
-- end of code from book
wait;
end process;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_ch_18_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_18_10 is
end entity ch_18_10;
----------------------------------------------------------------
architecture test of ch_18_10 is
begin
process is
use std.textio.all;
variable L : line;
-- code from book:
type speed_category is (stopped, slow, fast, maniacal);
variable speed : speed_category;
-- end of code from book
begin
speed := stopped;
-- code from book:
write ( L, speed_category'image(speed) );
-- end of code from book
writeline(output, L);
speed := slow;
write ( L, speed_category'image(speed) );
writeline(output, L);
speed := fast;
write ( L, speed_category'image(speed) );
writeline(output, L);
speed := maniacal;
write ( L, speed_category'image(speed) );
writeline(output, L);
-- code from book:
readline( input, L );
speed := speed_category'value(L.all);
-- end of code from book
wait;
end process;
end architecture test;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use proc_common_v4_0_2 library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v3_1
-- ~~~~~~
-- - Modified to used proc_common_v4_0_2 library
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
bus2ip_clk : In std_logic;
bus2ip_reset : In std_logic;
bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1);
interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
ipif_reg_interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
ipif_lvl_interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
ip2bus_intrevent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
intr2bus_devintr : Out std_logic;
-- Status Reply Outputs to the Bus
intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
intr2bus_wrack : Out std_logic;
intr2bus_rdack : Out std_logic;
intr2bus_error : Out std_logic;
intr2bus_retry : Out std_logic;
intr2bus_toutsup : Out std_logic
);
end interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use proc_common_v4_0_2 library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v3_1
-- ~~~~~~
-- - Modified to used proc_common_v4_0_2 library
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
bus2ip_clk : In std_logic;
bus2ip_reset : In std_logic;
bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1);
interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
ipif_reg_interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
ipif_lvl_interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
ip2bus_intrevent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
intr2bus_devintr : Out std_logic;
-- Status Reply Outputs to the Bus
intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
intr2bus_wrack : Out std_logic;
intr2bus_rdack : Out std_logic;
intr2bus_error : Out std_logic;
intr2bus_retry : Out std_logic;
intr2bus_toutsup : Out std_logic
);
end interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use proc_common_v4_0_2 library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v3_1
-- ~~~~~~
-- - Modified to used proc_common_v4_0_2 library
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
bus2ip_clk : In std_logic;
bus2ip_reset : In std_logic;
bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1);
interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
ipif_reg_interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
ipif_lvl_interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
ip2bus_intrevent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
intr2bus_devintr : Out std_logic;
-- Status Reply Outputs to the Bus
intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
intr2bus_wrack : Out std_logic;
intr2bus_rdack : Out std_logic;
intr2bus_error : Out std_logic;
intr2bus_retry : Out std_logic;
intr2bus_toutsup : Out std_logic
);
end interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use proc_common_v4_0_2 library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v3_1
-- ~~~~~~
-- - Modified to used proc_common_v4_0_2 library
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
bus2ip_clk : In std_logic;
bus2ip_reset : In std_logic;
bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1);
interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
ipif_reg_interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
ipif_lvl_interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
ip2bus_intrevent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
intr2bus_devintr : Out std_logic;
-- Status Reply Outputs to the Bus
intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
intr2bus_wrack : Out std_logic;
intr2bus_rdack : Out std_logic;
intr2bus_error : Out std_logic;
intr2bus_retry : Out std_logic;
intr2bus_toutsup : Out std_logic
);
end interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
|
-- Tagged sorter
ENTITY TSProject32 IS
PORT
(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
insert : IN STD_LOGIC; -- enqueue trigger
extract : IN STD_LOGIC; -- dequeue trigger
-- enqueuing elements (key & value)
LIkey : IN STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
LIdata : IN STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 );
-- dequeuing elements (key & value)
ROkey : BUFFER STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
ROdata : BUFFER STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 );
Q_FULL : OUT STD_LOGIC;
Q_EMPTY : OUT STD_LOGIC
);
END TSProject32;
|
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Parker Brian Ridd
--
-- Create Date: 10:24:17 02/04/2014
-- Design Name:
-- Module Name: vga_timing - lab_arch
-- Project Name: Lab 5
-- Target Devices: Nexsys 2 by Digilent
-- Tool versions:
-- Description: VGA Controller for the lab 5 assignment
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_timing is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
HS : out STD_LOGIC;
VS : out STD_LOGIC;
pixel_x : out STD_LOGIC_VECTOR (9 downto 0);
pixel_y : out STD_LOGIC_VECTOR (9 downto 0);
last_column : out STD_LOGIC;
last_row : out STD_LOGIC;
blank : out STD_LOGIC);
end vga_timing;
architecture lab_arch of vga_timing is
--create signals for pixel clock
signal pixel_en, pxr_next : STD_LOGIC := '0';
--create signals for horizontal counter
signal hzr_reg, hzr_next: UNSIGNED(9 downto 0) := (others => '0');
signal hz_lastColumn : STD_LOGIC := '0';
--create signals for vertical counter
signal ver_reg, ver_next : UNSIGNED(9 downto 0) := (others => '0');
signal ver_lastRow : STD_LOGIC := '0';
begin
--BASE MODULE OF PIXEL CLOCK
process(clk, rst)
begin
if(rst = '1') then
pixel_en <= '0';
elsif(clk'event and clk = '1') then
pixel_en <= pxr_next;
end if;
end process;
--next state logic for pixel clock
pxr_next <=
not pixel_en;
--HORIZONTAL PIXEL COUNTER
process(clk, rst)
begin
if(rst = '1') then
hzr_reg <= (others => '0');
elsif(clk'event and clk = '1') then
hzr_reg <= hzr_next;
end if;
end process;
--next state logic for horizontal counter
hzr_next <=
(others => '0') when (hzr_reg = 799) and (pixel_en = '1') else
hzr_reg + 1 when pixel_en = '1' else
hzr_reg;
--output signal logic for horizontal counter
hz_lastColumn <=
'1' when hzr_reg = 639 else
'0';
HS <= '0' when (hzr_reg > 655) and (hzr_reg < 752) else
'1';
--VERTICAL PIXEL COUNTER
process(clk, rst)
begin
if(rst = '1') then
ver_reg <= (others => '0');
elsif(clk'event and clk = '1') then
ver_reg <= ver_next;
end if;
end process;
--next state logic for vertical counter
ver_next <=
(others => '0') when (ver_reg = 520) and (hzr_reg = 799) and (pixel_en = '1') else
ver_reg + 1 when (hzr_reg = 799) and (pixel_en = '1') else
ver_reg;
--output signal logic for vertical counter
ver_lastRow <=
'1' when ver_reg = 479 else
'0';
VS <=
'0' when (ver_reg > 489) and (ver_reg < 492) else
'1';
--LOGIC FOR THE BLANK SIGNAL
blank <=
'1' when (ver_reg > 479) else
'1' when (hzr_reg > 639) else
'0';
--OTHER OUTPUT ASSIGNMENTS
pixel_x <= std_logic_vector(hzr_reg);
pixel_y <= std_logic_vector(ver_reg);
last_column <= hz_lastColumn;
last_row <= ver_lastRow;
end lab_arch;
|
library verilog;
use verilog.vl_types.all;
entity altddio_bidir is
generic(
width : integer := 1;
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable: string := "UNUSED";
implement_input_in_lcell: string := "UNUSED";
invert_output : string := "OFF";
intended_device_family: string := "Stratix";
lpm_type : string := "altddio_bidir";
lpm_hint : string := "UNUSED"
);
port(
datain_h : in vl_logic_vector;
datain_l : in vl_logic_vector;
inclock : in vl_logic;
inclocken : in vl_logic;
outclock : in vl_logic;
outclocken : in vl_logic;
aset : in vl_logic;
aclr : in vl_logic;
sset : in vl_logic;
sclr : in vl_logic;
oe : in vl_logic;
dataout_h : out vl_logic_vector;
dataout_l : out vl_logic_vector;
combout : out vl_logic_vector;
oe_out : out vl_logic_vector;
dqsundelayedout : out vl_logic_vector;
padio : inout vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of power_up_high : constant is 1;
attribute mti_svvh_generic_type of oe_reg : constant is 1;
attribute mti_svvh_generic_type of extend_oe_disable : constant is 1;
attribute mti_svvh_generic_type of implement_input_in_lcell : constant is 1;
attribute mti_svvh_generic_type of invert_output : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
end altddio_bidir;
|
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16944)
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16944)
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`protect end_protected
|
-- Std.Textio package declaration. This file is part of GHDL.
-- This file was written from the clause 14.3 of the VHDL LRM.
-- Copyright (C) 2002 - 2014 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING3. If not see
-- <http://www.gnu.org/licenses/>.
package Textio is
-- type definitions for text i/o
-- a LINE is a pointer to a string value.
type Line is access String;
-- A file of variable-length ASCII records.
-- Note: in order to work correctly, the TEXT file type must be declared in
-- the Textio package of library Std. Otherwise, a file of string has a
-- non-ASCII format.
type text is file of String;
type side is (right, left); -- For justifying ouput data within fields.
subtype width is natural; -- For specifying widths of output fields.
-- standard text files
--START-V08
function Justify (Value: String;
Justified : Side := Right;
Field: Width := 0 ) return String;
--END-V08
file input: text is in "STD_INPUT"; --V87
file output: text is out "STD_OUTPUT"; --V87
file input : text open read_mode is "STD_INPUT"; --!V87
file output : text open write_mode is "STD_OUTPUT"; --!V87
-- input routines for standard types
procedure readline (variable f: in text; l: inout line); --V87
procedure readline (file f: text; l: inout line); --!V87
-- For READ procedures:
-- In this implementation, any L is accepted (ie, there is no constraints
-- on direction, or left bound). Therefore, even variable of type LINE
-- not initialized by READLINE are accepted. Strictly speaking, this is
-- not required by LRM, nor prevented. However, other implementations may
-- fail at parsing such Strings.
--
-- Also, in case of error (GOOD is false), this implementation do not
-- modify L (as specified by the LRM) nor VALUE.
--
-- For READ procedures without a GOOD argument, an assertion fails in case
-- of error.
--
-- In case of overflow (ie, if the number is out of the bounds of the type),
-- the procedure will fail with an execution error.
-- FIXME: this should not occur for a bad String.
procedure read (l: inout line; value: out bit; good: out boolean);
procedure read (l: inout line; value: out bit);
procedure read (l: inout line; value: out bit_vector; good: out boolean);
procedure read (l: inout line; value: out bit_vector);
procedure read (l: inout line; value: out boolean; good: out boolean);
procedure read (l: inout line; value: out boolean);
procedure read (l: inout line; value: out character; good: out boolean);
procedure read (l: inout line; value: out character);
procedure read (l: inout line; value: out integer; good: out boolean);
procedure read (l: inout line; value: out integer);
procedure read (l: inout line; value: out real; good: out boolean);
procedure read (l: inout line; value: out real);
procedure read (l: inout line; value: out String; good: out boolean);
procedure read (l: inout line; value: out String);
-- This implementation requires no space after the unit identifier,
-- ie "7.5 nsv" is parsed as 7.5 ns.
-- The unit identifier can be in lower case, upper case or mixed case.
procedure read (l: inout line; value: out time; good: out boolean);
procedure read (l: inout line; value: out time);
--START-V08
procedure Sread (L : inout Line; Value : out String; Strlen : out Natural);
alias STRING_READ is SREAD [LINE, STRING, NATURAL];
alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, BIT_VECTOR];
alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, BIT_VECTOR];
procedure Oread (L : inout Line; Value : out Bit_Vector; Good : out Boolean);
procedure Oread (L : inout Line; Value : out Bit_Vector);
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
procedure Hread (L : inout Line; Value : out Bit_Vector; Good : out Boolean);
procedure Hread (L : inout Line; Value : out Bit_Vector);
alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, BIT_VECTOR];
--END-V08
-- output routines for standard types
procedure writeline (variable f: out text; l: inout line); --V87
procedure writeline (file f: text; l: inout line); --!V87
--START-V08
procedure Tee (file f : Text; L : inout LINE);
--END-V08
-- This implementation accept any value for all the types.
procedure write
(l: inout line; value: in bit;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in bit_vector;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in boolean;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in character;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in integer;
justified: in side := right; field: in width := 0);
procedure write
(L: inout line; value: in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0);
procedure write
(l: inout line; value: in String;
justified: in side := right; field: in width := 0);
-- UNIT must be a unit name declared in std.standard. Of course, no rules
-- in the core VHDL language prevent you from using a value that is not a
-- unit (eg: 10 ns or even 5 fs).
-- An assertion error message is generated in this case, and question mark
-- (?) is written at the place of the unit name.
procedure write
(l: inout line; value : in time;
justified: in side := right; field: in width := 0; unit : in TIME := ns);
--START-V08
alias Swrite is write [Line, String, Side, Width];
alias String_Write is Write [Line, String, Side, Width];
alias Bwrite is write [Line, Bit_Vector, Side, Width];
alias Binary_Write is write [Line, Bit_Vector, Side, Width];
procedure Owrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0);
alias Octal_Write is Owrite [Line, Bit_Vector, Side, Width];
procedure Hwrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0);
alias Hex_Write is Hwrite [Line, Bit_Vector, Side, Width];
--END-V08
end textio;
|
-- Std.Textio package declaration. This file is part of GHDL.
-- This file was written from the clause 14.3 of the VHDL LRM.
-- Copyright (C) 2002 - 2014 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING3. If not see
-- <http://www.gnu.org/licenses/>.
package Textio is
-- type definitions for text i/o
-- a LINE is a pointer to a string value.
type Line is access String;
-- A file of variable-length ASCII records.
-- Note: in order to work correctly, the TEXT file type must be declared in
-- the Textio package of library Std. Otherwise, a file of string has a
-- non-ASCII format.
type text is file of String;
type side is (right, left); -- For justifying ouput data within fields.
subtype width is natural; -- For specifying widths of output fields.
-- standard text files
--START-V08
function Justify (Value: String;
Justified : Side := Right;
Field: Width := 0 ) return String;
--END-V08
file input: text is in "STD_INPUT"; --V87
file output: text is out "STD_OUTPUT"; --V87
file input : text open read_mode is "STD_INPUT"; --!V87
file output : text open write_mode is "STD_OUTPUT"; --!V87
-- input routines for standard types
procedure readline (variable f: in text; l: inout line); --V87
procedure readline (file f: text; l: inout line); --!V87
-- For READ procedures:
-- In this implementation, any L is accepted (ie, there is no constraints
-- on direction, or left bound). Therefore, even variable of type LINE
-- not initialized by READLINE are accepted. Strictly speaking, this is
-- not required by LRM, nor prevented. However, other implementations may
-- fail at parsing such Strings.
--
-- Also, in case of error (GOOD is false), this implementation do not
-- modify L (as specified by the LRM) nor VALUE.
--
-- For READ procedures without a GOOD argument, an assertion fails in case
-- of error.
--
-- In case of overflow (ie, if the number is out of the bounds of the type),
-- the procedure will fail with an execution error.
-- FIXME: this should not occur for a bad String.
procedure read (l: inout line; value: out bit; good: out boolean);
procedure read (l: inout line; value: out bit);
procedure read (l: inout line; value: out bit_vector; good: out boolean);
procedure read (l: inout line; value: out bit_vector);
procedure read (l: inout line; value: out boolean; good: out boolean);
procedure read (l: inout line; value: out boolean);
procedure read (l: inout line; value: out character; good: out boolean);
procedure read (l: inout line; value: out character);
procedure read (l: inout line; value: out integer; good: out boolean);
procedure read (l: inout line; value: out integer);
procedure read (l: inout line; value: out real; good: out boolean);
procedure read (l: inout line; value: out real);
procedure read (l: inout line; value: out String; good: out boolean);
procedure read (l: inout line; value: out String);
-- This implementation requires no space after the unit identifier,
-- ie "7.5 nsv" is parsed as 7.5 ns.
-- The unit identifier can be in lower case, upper case or mixed case.
procedure read (l: inout line; value: out time; good: out boolean);
procedure read (l: inout line; value: out time);
--START-V08
procedure Sread (L : inout Line; Value : out String; Strlen : out Natural);
alias STRING_READ is SREAD [LINE, STRING, NATURAL];
alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, BIT_VECTOR];
alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, BIT_VECTOR];
procedure Oread (L : inout Line; Value : out Bit_Vector; Good : out Boolean);
procedure Oread (L : inout Line; Value : out Bit_Vector);
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
procedure Hread (L : inout Line; Value : out Bit_Vector; Good : out Boolean);
procedure Hread (L : inout Line; Value : out Bit_Vector);
alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, BIT_VECTOR];
--END-V08
-- output routines for standard types
procedure writeline (variable f: out text; l: inout line); --V87
procedure writeline (file f: text; l: inout line); --!V87
--START-V08
procedure Tee (file f : Text; L : inout LINE);
--END-V08
-- This implementation accept any value for all the types.
procedure write
(l: inout line; value: in bit;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in bit_vector;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in boolean;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in character;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in integer;
justified: in side := right; field: in width := 0);
procedure write
(L: inout line; value: in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0);
procedure write
(l: inout line; value: in String;
justified: in side := right; field: in width := 0);
-- UNIT must be a unit name declared in std.standard. Of course, no rules
-- in the core VHDL language prevent you from using a value that is not a
-- unit (eg: 10 ns or even 5 fs).
-- An assertion error message is generated in this case, and question mark
-- (?) is written at the place of the unit name.
procedure write
(l: inout line; value : in time;
justified: in side := right; field: in width := 0; unit : in TIME := ns);
--START-V08
alias Swrite is write [Line, String, Side, Width];
alias String_Write is Write [Line, String, Side, Width];
alias Bwrite is write [Line, Bit_Vector, Side, Width];
alias Binary_Write is write [Line, Bit_Vector, Side, Width];
procedure Owrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0);
alias Octal_Write is Owrite [Line, Bit_Vector, Side, Width];
procedure Hwrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0);
alias Hex_Write is Hwrite [Line, Bit_Vector, Side, Width];
--END-V08
end textio;
|
-- Std.Textio package declaration. This file is part of GHDL.
-- This file was written from the clause 14.3 of the VHDL LRM.
-- Copyright (C) 2002 - 2014 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING3. If not see
-- <http://www.gnu.org/licenses/>.
package Textio is
-- type definitions for text i/o
-- a LINE is a pointer to a string value.
type Line is access String;
-- A file of variable-length ASCII records.
-- Note: in order to work correctly, the TEXT file type must be declared in
-- the Textio package of library Std. Otherwise, a file of string has a
-- non-ASCII format.
type text is file of String;
type side is (right, left); -- For justifying ouput data within fields.
subtype width is natural; -- For specifying widths of output fields.
-- standard text files
--START-V08
function Justify (Value: String;
Justified : Side := Right;
Field: Width := 0 ) return String;
--END-V08
file input: text is in "STD_INPUT"; --V87
file output: text is out "STD_OUTPUT"; --V87
file input : text open read_mode is "STD_INPUT"; --!V87
file output : text open write_mode is "STD_OUTPUT"; --!V87
-- input routines for standard types
procedure readline (variable f: in text; l: inout line); --V87
procedure readline (file f: text; l: inout line); --!V87
-- For READ procedures:
-- In this implementation, any L is accepted (ie, there is no constraints
-- on direction, or left bound). Therefore, even variable of type LINE
-- not initialized by READLINE are accepted. Strictly speaking, this is
-- not required by LRM, nor prevented. However, other implementations may
-- fail at parsing such Strings.
--
-- Also, in case of error (GOOD is false), this implementation do not
-- modify L (as specified by the LRM) nor VALUE.
--
-- For READ procedures without a GOOD argument, an assertion fails in case
-- of error.
--
-- In case of overflow (ie, if the number is out of the bounds of the type),
-- the procedure will fail with an execution error.
-- FIXME: this should not occur for a bad String.
procedure read (l: inout line; value: out bit; good: out boolean);
procedure read (l: inout line; value: out bit);
procedure read (l: inout line; value: out bit_vector; good: out boolean);
procedure read (l: inout line; value: out bit_vector);
procedure read (l: inout line; value: out boolean; good: out boolean);
procedure read (l: inout line; value: out boolean);
procedure read (l: inout line; value: out character; good: out boolean);
procedure read (l: inout line; value: out character);
procedure read (l: inout line; value: out integer; good: out boolean);
procedure read (l: inout line; value: out integer);
procedure read (l: inout line; value: out real; good: out boolean);
procedure read (l: inout line; value: out real);
procedure read (l: inout line; value: out String; good: out boolean);
procedure read (l: inout line; value: out String);
-- This implementation requires no space after the unit identifier,
-- ie "7.5 nsv" is parsed as 7.5 ns.
-- The unit identifier can be in lower case, upper case or mixed case.
procedure read (l: inout line; value: out time; good: out boolean);
procedure read (l: inout line; value: out time);
--START-V08
procedure Sread (L : inout Line; Value : out String; Strlen : out Natural);
alias STRING_READ is SREAD [LINE, STRING, NATURAL];
alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, BIT_VECTOR];
alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, BIT_VECTOR];
procedure Oread (L : inout Line; Value : out Bit_Vector; Good : out Boolean);
procedure Oread (L : inout Line; Value : out Bit_Vector);
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
procedure Hread (L : inout Line; Value : out Bit_Vector; Good : out Boolean);
procedure Hread (L : inout Line; Value : out Bit_Vector);
alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, BIT_VECTOR];
--END-V08
-- output routines for standard types
procedure writeline (variable f: out text; l: inout line); --V87
procedure writeline (file f: text; l: inout line); --!V87
--START-V08
procedure Tee (file f : Text; L : inout LINE);
--END-V08
-- This implementation accept any value for all the types.
procedure write
(l: inout line; value: in bit;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in bit_vector;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in boolean;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in character;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in integer;
justified: in side := right; field: in width := 0);
procedure write
(L: inout line; value: in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0);
procedure write
(l: inout line; value: in String;
justified: in side := right; field: in width := 0);
-- UNIT must be a unit name declared in std.standard. Of course, no rules
-- in the core VHDL language prevent you from using a value that is not a
-- unit (eg: 10 ns or even 5 fs).
-- An assertion error message is generated in this case, and question mark
-- (?) is written at the place of the unit name.
procedure write
(l: inout line; value : in time;
justified: in side := right; field: in width := 0; unit : in TIME := ns);
--START-V08
alias Swrite is write [Line, String, Side, Width];
alias String_Write is Write [Line, String, Side, Width];
alias Bwrite is write [Line, Bit_Vector, Side, Width];
alias Binary_Write is write [Line, Bit_Vector, Side, Width];
procedure Owrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0);
alias Octal_Write is Owrite [Line, Bit_Vector, Side, Width];
procedure Hwrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0);
alias Hex_Write is Hwrite [Line, Bit_Vector, Side, Width];
--END-V08
end textio;
|
-- Std.Textio package declaration. This file is part of GHDL.
-- This file was written from the clause 14.3 of the VHDL LRM.
-- Copyright (C) 2002 - 2014 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING3. If not see
-- <http://www.gnu.org/licenses/>.
package Textio is
-- type definitions for text i/o
-- a LINE is a pointer to a string value.
type Line is access String;
-- A file of variable-length ASCII records.
-- Note: in order to work correctly, the TEXT file type must be declared in
-- the Textio package of library Std. Otherwise, a file of string has a
-- non-ASCII format.
type text is file of String;
type side is (right, left); -- For justifying ouput data within fields.
subtype width is natural; -- For specifying widths of output fields.
-- standard text files
--START-V08
function Justify (Value: String;
Justified : Side := Right;
Field: Width := 0 ) return String;
--END-V08
file input: text is in "STD_INPUT"; --V87
file output: text is out "STD_OUTPUT"; --V87
file input : text open read_mode is "STD_INPUT"; --!V87
file output : text open write_mode is "STD_OUTPUT"; --!V87
-- input routines for standard types
procedure readline (variable f: in text; l: inout line); --V87
procedure readline (file f: text; l: inout line); --!V87
-- For READ procedures:
-- In this implementation, any L is accepted (ie, there is no constraints
-- on direction, or left bound). Therefore, even variable of type LINE
-- not initialized by READLINE are accepted. Strictly speaking, this is
-- not required by LRM, nor prevented. However, other implementations may
-- fail at parsing such Strings.
--
-- Also, in case of error (GOOD is false), this implementation do not
-- modify L (as specified by the LRM) nor VALUE.
--
-- For READ procedures without a GOOD argument, an assertion fails in case
-- of error.
--
-- In case of overflow (ie, if the number is out of the bounds of the type),
-- the procedure will fail with an execution error.
-- FIXME: this should not occur for a bad String.
procedure read (l: inout line; value: out bit; good: out boolean);
procedure read (l: inout line; value: out bit);
procedure read (l: inout line; value: out bit_vector; good: out boolean);
procedure read (l: inout line; value: out bit_vector);
procedure read (l: inout line; value: out boolean; good: out boolean);
procedure read (l: inout line; value: out boolean);
procedure read (l: inout line; value: out character; good: out boolean);
procedure read (l: inout line; value: out character);
procedure read (l: inout line; value: out integer; good: out boolean);
procedure read (l: inout line; value: out integer);
procedure read (l: inout line; value: out real; good: out boolean);
procedure read (l: inout line; value: out real);
procedure read (l: inout line; value: out String; good: out boolean);
procedure read (l: inout line; value: out String);
-- This implementation requires no space after the unit identifier,
-- ie "7.5 nsv" is parsed as 7.5 ns.
-- The unit identifier can be in lower case, upper case or mixed case.
procedure read (l: inout line; value: out time; good: out boolean);
procedure read (l: inout line; value: out time);
--START-V08
procedure Sread (L : inout Line; Value : out String; Strlen : out Natural);
alias STRING_READ is SREAD [LINE, STRING, NATURAL];
alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, BIT_VECTOR];
alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, BIT_VECTOR];
procedure Oread (L : inout Line; Value : out Bit_Vector; Good : out Boolean);
procedure Oread (L : inout Line; Value : out Bit_Vector);
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
procedure Hread (L : inout Line; Value : out Bit_Vector; Good : out Boolean);
procedure Hread (L : inout Line; Value : out Bit_Vector);
alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, BIT_VECTOR];
--END-V08
-- output routines for standard types
procedure writeline (variable f: out text; l: inout line); --V87
procedure writeline (file f: text; l: inout line); --!V87
--START-V08
procedure Tee (file f : Text; L : inout LINE);
--END-V08
-- This implementation accept any value for all the types.
procedure write
(l: inout line; value: in bit;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in bit_vector;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in boolean;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in character;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in integer;
justified: in side := right; field: in width := 0);
procedure write
(L: inout line; value: in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0);
procedure write
(l: inout line; value: in String;
justified: in side := right; field: in width := 0);
-- UNIT must be a unit name declared in std.standard. Of course, no rules
-- in the core VHDL language prevent you from using a value that is not a
-- unit (eg: 10 ns or even 5 fs).
-- An assertion error message is generated in this case, and question mark
-- (?) is written at the place of the unit name.
procedure write
(l: inout line; value : in time;
justified: in side := right; field: in width := 0; unit : in TIME := ns);
--START-V08
alias Swrite is write [Line, String, Side, Width];
alias String_Write is Write [Line, String, Side, Width];
alias Bwrite is write [Line, Bit_Vector, Side, Width];
alias Binary_Write is write [Line, Bit_Vector, Side, Width];
procedure Owrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0);
alias Octal_Write is Owrite [Line, Bit_Vector, Side, Width];
procedure Hwrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0);
alias Hex_Write is Hwrite [Line, Bit_Vector, Side, Width];
--END-V08
end textio;
|
-- ======================================================================
-- CBC-MAC-AES
-- Copyright (C) 2020 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aes_pkg.all;
entity cbcmac_aes is
port (
reset_i : in std_logic; -- low active async reset
clk_i : in std_logic; -- clock
start_i : in std_logic; -- start cbc
key_i : in std_logic_vector(0 to 127); -- key input
data_i : in std_logic_vector(0 to 127); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic; -- input accept
data_o : out std_logic_vector(0 tO 127); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic -- output accept
);
end entity cbcmac_aes;
architecture rtl of cbcmac_aes is
-- CBCMAC must have fix IV for security reasons
constant C_IV : std_logic_vector(0 to 127) := (others => '0');
signal s_aes_datain : std_logic_vector(0 to 127);
signal s_aes_dataout : std_logic_vector(0 to 127);
signal s_aes_dataout_d : std_logic_vector(0 to 127);
signal s_aes_key : std_logic_vector(0 to 127);
signal s_key : std_logic_vector(0 to 127);
signal s_aes_accept : std_logic;
signal s_aes_validout : std_logic;
begin
s_aes_datain <= C_IV xor data_i when start_i = '1' else
s_aes_dataout_d xor data_i;
data_o <= s_aes_dataout;
s_aes_key <= key_i when start_i = '1' else s_key;
accept_o <= s_aes_accept;
valid_o <= s_aes_validout;
inputregister : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_key <= (others => '0');
elsif (rising_edge(clk_i)) then
if (valid_i = '1' and s_aes_accept = '1' and start_i = '1') then
s_key <= key_i;
end if;
end if;
end process inputregister;
outputregister : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_aes_dataout_d <= (others => '0');
elsif (rising_edge(clk_i)) then
if (s_aes_validout = '1') then
s_aes_dataout_d <= s_aes_dataout;
end if;
end if;
end process outputregister;
i_aes : aes_enc
generic map (
design_type => "ITER"
)
port map (
reset_i => reset_i,
clk_i => clk_i,
key_i => s_aes_key,
data_i => s_aes_datain,
valid_i => valid_i,
accept_o => s_aes_accept,
data_o => s_aes_dataout,
valid_o => s_aes_validout,
accept_i => accept_i
);
end architecture rtl;
|
------------------------------------------------------------------------------
-- Testbench for conifgPkg.vhd
--
-- Project :
-- File : tb_configPkg.vhd
-- Author : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/08
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
entity tb_configPkg is
end tb_configPkg;
architecture abstract of tb_configPkg is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (idle, conv_procCfg, conv_routCfg, conv_cellCfg,
conv_rowCfg, conv_gridCfg, conv_ioportCfg,
conv_engineCfg, part_cfg);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
-- configuration signals
signal ProcCfg : procConfigRec;
signal ProcCfgxD : std_logic_vector(PE_CFGLEN-1 downto 0);
signal ProcCfgBck : procConfigRec;
signal RoutCfg : routConfigRec;
signal RoutCfgxD : std_logic_vector(RE_CFGLEN-1 downto 0);
signal RoutCfgBck : routConfigRec;
signal CellCfg : cellConfigRec;
signal CellCfgxD : std_logic_vector(CELL_CFGLEN-1 downto 0);
signal CellCfgBck : cellConfigRec;
signal RowCfg : rowConfigArray;
signal RowCfgxD : std_logic_vector(ROW_CFGLEN-1 downto 0);
signal RowCfgBck : rowConfigArray;
signal GridCfg : gridConfigArray;
signal GridCfgxD : std_logic_vector(GRID_CFGLEN-1 downto 0);
signal GridCfgBck : gridConfigArray;
signal IOPortCfg : ioportConfigRec;
signal IOPortCfgxD : std_logic_vector(PORT_CFGLEN-1 downto 0);
signal IOPortCfgBck : ioportConfigRec;
signal EngnCfg : engineConfigRec;
signal EngnCfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0);
signal EngnCfgBck : engineConfigRec;
signal EngnCfgArr : cfgPartArray;
begin -- abstract
----------------------------------------------------------------------------
-- conversions
----------------------------------------------------------------------------
flat_procConfig : process (ProcCfg)
begin -- process flat_procConfig
ProcCfgxD <= to_procConfig_vec(ProcCfg);
end process flat_procConfig;
struct_procConfig : process (ProcCfgxD)
begin -- process struct_procConfig
ProcCfgBck <= to_procConfig_rec(ProcCfgxD);
end process struct_procConfig;
flat_routConfig : process (RoutCfg)
begin -- process flat_routConfig
RoutCfgxD <= to_routConfig_vec(RoutCfg);
end process flat_routConfig;
struct_routConfig : process (RoutCfgxD)
begin -- process struct_routConfig
RoutCfgBck <= to_routConfig_rec(RoutCfgxD);
end process struct_routConfig;
flat_cellConfig : process (CellCfg)
begin -- process flat_cellConfig
CellCfgxD <= to_cellConfig_vec(CellCfg);
end process flat_cellConfig;
struct_cellConfig : process (CellCfgxD)
begin -- process struct_cellConfig
CellCfgBck <= to_cellConfig_rec(CellCfgxD);
end process struct_cellConfig;
flat_rowConfig : process (RowCfg)
begin -- process flat_rowConfig
RowCfgxD <= to_rowConfig_vec(RowCfg);
end process flat_rowConfig;
struct_rowConfig : process (RowCfgxD)
begin -- process struct_rowConfig
RowCfgBck <= to_rowConfig_arr(RowCfgxD);
end process struct_rowConfig;
flat_gridConfig : process (GridCfg)
begin -- process flat_gridConfig
GridCfgxD <= to_gridConfig_vec(GridCfg);
end process flat_gridConfig;
struct_gridConfig : process (GridCfgxD)
begin -- process struct_gridConfig
GridCfgBck <= to_gridConfig_arr(GridCfgxD);
end process struct_gridConfig;
flat_ioportConfig : process (IOPortCfg)
begin -- process flat_ioportConfig
IOPortCfgxD <= to_ioportConfig_vec(IOPortCfg);
end process flat_ioportConfig;
struct_ioportConfig : process (IOPortCfgxD)
begin -- process struct_ioportConfig
IOPortCfgBck <= to_ioportConfig_rec(IOPortCfgxD);
end process struct_ioportConfig;
flat_engineConfig : process (EngnCfg)
begin -- process flat_engineConfig
EngnCfgxD <= to_engineConfig_vec(EngnCfg);
end process flat_engineConfig;
struct_engineConfig : process (EngnCfgxD)
begin -- process struct_engineConfig
EngnCfgBck <= to_engineConfig_rec(EngnCfgxD);
end process struct_engineConfig;
part_engineConfig : process (EngnCfgxD)
begin -- process part_engineConfig
EngnCfgArr <= partition_config(EngnCfgxD);
end process part_engineConfig;
----------------------------------------------------------------------------
-- checks (assertion statements)
----------------------------------------------------------------------------
check_procConfig : process (ClkxC, ProcCfg, ProcCfgBck)
begin -- process check_procConfig
if ClkxC'event and ClkxC = '1' then
assert (ProcCfg = ProcCfgBck)
report "SIMOUT: ProcCfg's differ (cycle " & int2str(ccount) & ")"
severity failure;
end if;
end process check_procConfig;
check_routConfig : process (ClkxC, RoutCfg, RoutCfgBck)
begin -- process check_routConfig
if ClkxC'event and ClkxC = '1' then
assert (RoutCfg = RoutCfgBck)
report "SIMOUT: RoutCfg's differ (cycle " & int2str(ccount) & ")"
severity failure;
end if;
end process check_routConfig;
check_cellConfig : process (ClkxC, CellCfg, CellCfgBck)
begin -- process check_cellConfig
if ClkxC'event and ClkxC = '1' then
assert (CellCfg = CellCfgBck)
report "SIMOUT: CellCfg's differ (cycle " & int2str(ccount) & ")"
severity failure;
end if;
end process check_cellConfig;
check_rowConfig : process (ClkxC, RowCfg, RowCfgBck)
begin -- process check_rowConfig
if ClkxC'event and ClkxC = '1' then
assert (RowCfg = RowCfgBck)
report "SIMOUT: RowCfg's differ (cycle " & int2str(ccount) & ")"
severity failure;
end if;
end process check_rowConfig;
check_gridConfig : process (ClkxC, GridCfg, GridCfgBck)
begin -- process check_gridConfig
if ClkxC'event and ClkxC = '1' then
assert (GridCfg = GridCfgBck)
report "SIMOUT: GridCfg's differ (cycle " & int2str(ccount) & ")"
severity failure;
end if;
end process check_gridConfig;
check_ioportConfig : process (ClkxC, IOPortCfg, IOPortCfgBck)
begin -- process check_ioportConfig
if ClkxC'event and ClkxC = '1' then
assert (IOPortCfg = IOPortCfgBck)
report "SIMOUT: IOPortCfg's differ (cycle " & int2str(ccount) & ")"
severity failure;
end if;
end process check_ioportConfig;
check_engnConfig : process (ClkxC, EngnCfg, EngnCfgBck)
begin -- process check_engnConfig
if ClkxC'event and ClkxC = '1' then
assert (EngnCfg = EngnCfgBck)
report "SIMOUT: EngnCfg's differ (cycle " & int2str(ccount) & ")"
severity failure;
end if;
end process check_engnConfig;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
procedure init_stimuli (
signal ProcCfg : out procConfigRec;
signal RoutCfg : out routConfigRec;
signal CellCfg : out cellConfigRec;
signal RowCfg : out rowConfigArray;
signal GridCfg : out gridConfigArray;
signal IOPortCfg : out ioportConfigRec;
signal EngnCfg : out engineConfigRec ) is
begin
ProcCfg <= init_procConfig;
RoutCfg <= init_routConfig;
CellCfg <= init_cellConfig;
RowCfg <= init_rowConfig;
GridCfg <= init_gridConfig;
IOPortCfg <= init_ioportConfig;
EngnCfg <= init_engineConfig;
end init_stimuli;
begin -- process stimuliTb
tbStatus <= idle;
init_stimuli(ProcCfg, RoutCfg, CellCfg, RowCfg, GridCfg, IOPortCfg,
EngnCfg);
wait for CLK_PERIOD;
tbStatus <= conv_procCfg;
ProcCfg.Op0MuxS <= "10";
ProcCfg.Op1MuxS <= "01";
ProcCfg.OutMuxS <= '1';
ProcCfg.AluOpxS <= alu_add;
ProcCfg.ConstOpxD <= std_logic_vector(to_unsigned(15, DATAWIDTH));
wait for CLK_PERIOD;
wait for CLK_PERIOD;
ProcCfg.Op0MuxS <= "11";
ProcCfg.Op1MuxS <= "10";
ProcCfg.OutMuxS <= '0';
ProcCfg.AluOpxS <= alu_nand;
ProcCfg.ConstOpxD <= std_logic_vector(to_unsigned(255, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ProcCfg, RoutCfg, CellCfg, RowCfg, GridCfg, IOPortCfg,
EngnCfg);
wait for CLK_PERIOD;
tbStatus <= conv_routCfg;
RoutCfg.Route0MuxS <= "110";
RoutCfg.Route1MuxS <= "001";
RoutCfg.Tri0OExE <= '1';
RoutCfg.Tri1OExE <= '0';
RoutCfg.Tri2OExE <= '1';
wait for CLK_PERIOD;
RoutCfg.Route0MuxS <= "001";
RoutCfg.Tri0OExE <= '0';
RoutCfg.Tri1OExE <= '1';
RoutCfg.Tri2OExE <= '0';
RoutCfg.Route1MuxS <= "100";
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ProcCfg, RoutCfg, CellCfg, RowCfg, GridCfg, IOPortCfg,
EngnCfg);
wait for CLK_PERIOD;
tbStatus <= conv_cellCfg;
CellCfg.procConf.Op0MuxS <= "10";
CellCfg.procConf.Op1MuxS <= "01";
CellCfg.procConf.OutMuxS <= '1';
CellCfg.procConf.AluOpxS <= alu_add;
CellCfg.procConf.ConstOpxD <=
std_logic_vector(to_unsigned(15, DATAWIDTH));
CellCfg.routConf.Route0MuxS <= "110";
CellCfg.routConf.Route1MuxS <= "001";
CellCfg.routConf.Tri0OExE <= '1';
CellCfg.routConf.Tri1OExE <= '0';
CellCfg.routConf.Tri2OExE <= '1';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ProcCfg, RoutCfg, CellCfg, RowCfg, GridCfg, IOPortCfg,
EngnCfg);
wait for CLK_PERIOD;
tbStatus <= conv_rowCfg;
for i in RowCfg'range loop
RowCfg(i).procConf.Op0MuxS <= "10";
RowCfg(i).procConf.Op1MuxS <= "01";
RowCfg(i).procConf.OutMuxS <= '1';
RowCfg(i).procConf.AluOpxS <= alu_add;
RowCfg(i).procConf.ConstOpxD <=
std_logic_vector(to_unsigned(15, DATAWIDTH));
RowCfg(i).routConf.Route0MuxS <= "110";
RowCfg(i).routConf.Route1MuxS <= "001";
RowCfg(i).routConf.Tri0OExE <= '1';
RowCfg(i).routConf.Tri1OExE <= '0';
RowCfg(i).routConf.Tri2OExE <= '1';
end loop; -- i
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ProcCfg, RoutCfg, CellCfg, RowCfg, GridCfg, IOPortCfg,
EngnCfg);
wait for CLK_PERIOD;
tbStatus <= conv_gridCfg;
for i in GridCfg'range loop
for j in GridCfg(i)'range loop
GridCfg(i)(j).procConf.Op0MuxS <= "10";
GridCfg(i)(j).procConf.Op1MuxS <= "01";
GridCfg(i)(j).procConf.OutMuxS <= '1';
GridCfg(i)(j).procConf.AluOpxS <= alu_add;
GridCfg(i)(j).procConf.ConstOpxD <=
std_logic_vector(to_unsigned(15, DATAWIDTH));
GridCfg(i)(j).routConf.Route0MuxS <= "110";
GridCfg(i)(j).routConf.Route1MuxS <= "001";
GridCfg(i)(j).routConf.Tri0OExE <= '1';
GridCfg(i)(j).routConf.Tri1OExE <= '0';
GridCfg(i)(j).routConf.Tri2OExE <= '1';
end loop; -- j
end loop; -- i
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ProcCfg, RoutCfg, CellCfg, RowCfg, GridCfg, IOPortCfg,
EngnCfg);
wait for CLK_PERIOD;
tbStatus <= conv_ioportCfg;
ioportCfg.Cmp0MuxS <= '1';
ioportCfg.Cmp1MuxS <= '1';
ioportCfg.Cmp0ModusxS <= '1';
ioportCfg.Cmp1ModusxS <= '1';
ioportCfg.Cmp0ConstxD <= std_logic_vector(to_unsigned(111, CCNTWIDTH));
ioportCfg.Cmp1ConstxD <= std_logic_vector(to_unsigned(222, CCNTWIDTH));
ioportCfg.LUT4FunctxD <= X"ABCD";
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ProcCfg, RoutCfg, CellCfg, RowCfg, GridCfg, IOPortCfg,
EngnCfg);
wait for CLK_PERIOD;
tbStatus <= conv_engineCfg;
for i in EngnCfg.gridConf'range loop
for j in EngnCfg.gridConf(i)'range loop
EngnCfg.gridConf(i)(j).procConf.Op0MuxS <= "10";
EngnCfg.gridConf(i)(j).procConf.Op1MuxS <= "01";
EngnCfg.gridConf(i)(j).procConf.OutMuxS <= '1';
EngnCfg.gridConf(i)(j).procConf.AluOpxS <= alu_add;
EngnCfg.gridConf(i)(j).procConf.ConstOpxD <=
std_logic_vector(to_unsigned(15, DATAWIDTH));
EngnCfg.gridConf(i)(j).routConf.Route0MuxS <= "110";
EngnCfg.gridConf(i)(j).routConf.Route1MuxS <= "001";
EngnCfg.gridConf(i)(j).routConf.Tri0OExE <= '1';
EngnCfg.gridConf(i)(j).routConf.Tri1OExE <= '0';
EngnCfg.gridConf(i)(j).routConf.Tri2OExE <= '1';
end loop; -- j
end loop; -- i
EngnCfg.Inp0OExE <= "11111111";
EngnCfg.Inp1OExE <= "00000000";
EngnCfg.Out0MuxS <= "110";
EngnCfg.Out1MuxS <= "011";
-- inport0
EngnCfg.inport0Conf.Cmp0MuxS <= '1';
EngnCfg.inport0Conf.Cmp1MuxS <= '1';
EngnCfg.inport0Conf.Cmp0ModusxS <= '1';
EngnCfg.inport0Conf.Cmp1ModusxS <= '1';
EngnCfg.inport0Conf.Cmp0ConstxD <=
std_logic_vector(to_unsigned(111, CCNTWIDTH));
EngnCfg.inport0Conf.Cmp1ConstxD <=
std_logic_vector(to_unsigned(222, CCNTWIDTH));
EngnCfg.inport0Conf.LUT4FunctxD <= X"ABCD";
-- outport1
EngnCfg.outport1Conf.Cmp0MuxS <= '1';
EngnCfg.outport1Conf.Cmp1MuxS <= '1';
EngnCfg.outport1Conf.Cmp0ModusxS <= '1';
EngnCfg.outport1Conf.Cmp1ModusxS <= '1';
EngnCfg.outport1Conf.Cmp0ConstxD <=
std_logic_vector(to_unsigned(3, CCNTWIDTH));
EngnCfg.outport1Conf.Cmp1ConstxD <=
std_logic_vector(to_unsigned(4, CCNTWIDTH));
EngnCfg.outport1Conf.LUT4FunctxD <= X"A2D2";
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ProcCfg, RoutCfg, CellCfg, RowCfg, GridCfg, IOPortCfg,
EngnCfg);
wait for CLK_PERIOD*2;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end abstract;
|
-- Altera Microperipheral Reference Design Version 0802
--------------------------------------------------------
--
-- FILE NAME : a8255tb.vhd
--
-- PROJECT : Altera A8255 UART
-- PURPOSE : This file contains the entity and architecture
-- for the A8255 testbench. All registers and base
-- functionality are tested.
--
--Copyright © 2002 Altera Corporation. All rights reserved. Altera products are
--protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
--other intellectual property laws.
--This reference design file, and your use thereof, is subject to and governed by
--the terms and conditions of the applicable Altera Reference Design License Agreement.
--By using this reference design file, you indicate your acceptance of such terms and
--conditions between you and Altera Corporation. In the event that you do not agree with
--such terms and conditions, you may not use the reference design file. Please promptly
--destroy any copies you have made.
--This reference design file being provided on an "as-is" basis and as an accommodation
--and therefore all warranties, representations or guarantees of any kind
--(whether express, implied or statutory) including, without limitation, warranties of
--merchantability, non-infringement, or fitness for a particular purpose, are
--specifically disclaimed. By making this reference design file available, Altera
--expressly does not recommend, suggest or require that this reference design file be
--used in combination with any other product not provided by Altera.
----------------------------------------------------------
----------------------------
-- Entity Declaration
----------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY a8255tb IS
GENERIC (
CLKOffset : TIME := 0 ns;
CLKPeriod : TIME := 200 ns;
LoopDelay : TIME := 50 ns
);
PORT (
RESET_Stim : OUT std_logic;
CLK_Stim : OUT std_logic;
nCS_Stim : OUT std_logic;
nRD_Stim : OUT std_logic;
nWR_Stim : OUT std_logic;
A_Stim : OUT std_logic_vector (1 DOWNTO 0);
DIN_Stim : OUT std_logic_vector (7 DOWNTO 0);
PAIN_Stim : OUT std_logic_vector (7 DOWNTO 0);
PBIN_Stim : OUT std_logic_vector (7 DOWNTO 0);
PCIN_Stim : OUT std_logic_vector (7 DOWNTO 0);
DOUT_Resp : IN std_logic_vector (7 DOWNTO 0);
PAOUT_Resp : IN std_logic_vector (7 DOWNTO 0);
PAEN_Resp : IN std_logic;
PBOUT_Resp : IN std_logic_vector (7 DOWNTO 0);
PBEN_Resp : IN std_logic;
PCOUT_Resp : IN std_logic_vector (7 DOWNTO 0);
PCEN_Resp : IN std_logic_vector (7 DOWNTO 0)
);
END a8255tb;
-----------------------------
-- Architecture Body
-----------------------------
ARCHITECTURE MainTest OF a8255tb IS
SIGNAL PA : std_logic_vector (7 DOWNTO 0);
SIGNAL PB : std_logic_vector (7 DOWNTO 0);
SIGNAL PC : std_logic_vector (7 DOWNTO 0);
TYPE LoopBackModeType IS (Mode0, Mode1_AToB, Mode1_BToA, Mode2_AToB, Mode2_BToA);
SIGNAL LoopBackMode : LoopBackModeType;
BEGIN
CLKClockPrc : PROCESS
BEGIN
CLK_Stim <= '0';
WAIT FOR CLKOffset;
LOOP
CLK_Stim <= '0';
WAIT FOR CLKPeriod/2;
CLK_Stim <= '1';
WAIT FOR CLKPeriod/2;
END LOOP;
END PROCESS CLKClockPrc;
GeneralStimulus : PROCESS
CONSTANT PortA : std_logic_vector(1 DOWNTO 0) := "00";
CONSTANT PortB : std_logic_vector(1 DOWNTO 0) := "01";
CONSTANT PortC : std_logic_vector(1 DOWNTO 0) := "10";
CONSTANT ControlReg : std_logic_vector(1 DOWNTO 0) := "11";
CONSTANT ChangeBit : std_logic_vector(1 DOWNTO 0) := "11";
-----------------------------------------------------------------------
-- Define procedure to initialize inputs to default values and reset
-----------------------------------------------------------------------
PROCEDURE InitInputsAndReset IS
BEGIN
nCS_Stim <= '1';
nRD_Stim <= '1';
nWR_Stim <= '1';
A_Stim <= "00";
DIN_Stim <= "00000000";
RESET_Stim <= '1';
WAIT FOR CLKPeriod * 2;
RESET_Stim <= '0';
WAIT FOR CLKPeriod * 2;
END InitInputsAndReset;
-----------------------------------------------------------------------
-- Define procedure to read any register and compare to an expected value
-----------------------------------------------------------------------
PROCEDURE ReadReg (Address : IN std_logic_vector(1 DOWNTO 0);
ExpectedData : IN bit_vector(7 DOWNTO 0)
) IS
BEGIN
A_Stim <= Address;
WAIT FOR CLKPeriod;
nCS_Stim <= '0';
nRD_Stim <= '0';
WAIT FOR CLKPeriod;
ASSERT (DOUT_Resp = to_stdlogicvector(ExpectedData))
REPORT "Read Data does not match Expected Data" SEVERITY WARNING;
nCS_Stim <= '1';
nRD_Stim <= '1';
WAIT FOR CLKPeriod;
END ReadReg;
-----------------------------------------------------------------------
-- Define procedure to write any register
-----------------------------------------------------------------------
PROCEDURE WriteReg(Address : IN std_logic_vector(1 DOWNTO 0);
Data : IN bit_vector(7 DOWNTO 0)
) IS
BEGIN
A_Stim <= Address;
nCS_Stim <= '0';
DIN_Stim <= to_stdlogicvector(Data);
WAIT FOR CLKPeriod;
nWR_Stim <= '0';
WAIT FOR CLKPeriod;
nWR_Stim <= '1';
WAIT FOR CLKPeriod * 2;
nCS_Stim <= '1';
WAIT FOR CLKPeriod * 2;
END WriteReg;
---------------------------------------------------------------
-- Main Test Program
---------------------------------------------------------------
BEGIN
ASSERT false REPORT "START MODE 0 TEST" SEVERITY NOTE;
-- Set Loop Back Mode
LoopBackMode <= Mode0;
-- Reset chip and set inputs to default values
InitInputsAndReset;
-- Read Control Reg after reset
ReadReg(ControlReg, x"9B"); -- Resets to Mode 0, all inputs
-- Load Port output registers before changing mode and direction
WriteReg(PortA, x"AA");
WriteReg(PortB, x"55");
WriteReg(PortC, x"F0");
-- Set Mode 0, Port A out, B in, C upper in, C lower out
WriteReg(ControlReg, x"8A");
-- Read all ports
ReadReg(PortA, x"AA");
ReadReg(PortB, x"AA");
ReadReg(PortC, x"00");
-- Set Mode 0, Port A in, B out, C upper out, C lower in
WriteReg(ControlReg, x"98");
WriteReg(ControlReg, x"91");
-- Read all ports
ReadReg(PortA, x"55");
ReadReg(PortB, x"55");
ReadReg(PortC, x"FF");
-- Load Port output registers with inverse
WriteReg(PortA, x"55");
WriteReg(PortB, x"AA");
WriteReg(PortC, x"0F");
-- Read all ports
ReadReg(PortA, x"AA");
ReadReg(PortB, x"AA");
ReadReg(PortC, x"00");
-- Set Mode 0, Port A out, B in, C upper out, C lower in
WriteReg(ControlReg, x"83");
-- Read all ports
ReadReg(PortA, x"55");
ReadReg(PortB, x"55");
ReadReg(PortC, x"00");
-- Test Port C Upper Set/Reset Bit Feature
WriteReg(ChangeBit, x"09"); -- Set Port C (4)
ReadReg(PortC, x"11");
WriteReg(ChangeBit, x"0B"); -- Set Port C (5)
ReadReg(PortC, x"33");
WriteReg(ChangeBit, x"0D"); -- Set Port C (6)
ReadReg(PortC, x"77");
WriteReg(ChangeBit, x"0F"); -- Set Port C (7)
ReadReg(PortC, x"FF");
WriteReg(ChangeBit, x"08"); -- Reset Port C (4)
ReadReg(PortC, x"EE");
WriteReg(ChangeBit, x"0A"); -- Reset Port C (5)
ReadReg(PortC, x"CC");
WriteReg(ChangeBit, x"0C"); -- Reset Port C (6)
ReadReg(PortC, x"88");
WriteReg(ChangeBit, x"0E"); -- Reset Port C (7)
ReadReg(PortC, x"00");
-- Set Mode 0, Port A out, B in, C upper in, C lower out
WriteReg(ControlReg, x"8A");
WriteReg(PortC, x"00");
-- Test Port C Lower Set/Reset Bit Feature
WriteReg(ChangeBit, x"01"); -- Set Port C (0)
ReadReg(PortC, x"11");
WriteReg(ChangeBit, x"03"); -- Set Port C (1)
ReadReg(PortC, x"33");
WriteReg(ChangeBit, x"05"); -- Set Port C (2)
ReadReg(PortC, x"77");
WriteReg(ChangeBit, x"07"); -- Set Port C (3)
ReadReg(PortC, x"FF");
WriteReg(ChangeBit, x"00"); -- Reset Port C (0)
ReadReg(PortC, x"EE");
WriteReg(ChangeBit, x"02"); -- Reset Port C (1)
ReadReg(PortC, x"CC");
WriteReg(ChangeBit, x"04"); -- Reset Port C (2)
ReadReg(PortC, x"88");
WriteReg(ChangeBit, x"06"); -- Reset Port C (3)
ReadReg(PortC, x"00");
------------------------------------------------------------
------------------------------------------------------------
ASSERT false REPORT "START MODE 1 TEST" SEVERITY NOTE;
-- Set Loop Back Mode
LoopBackMode <= Mode1_AToB;
-- Reset chip and set inputs to default values
InitInputsAndReset;
-- Read Control Reg after reset
ReadReg(ControlReg, x"9B"); -- Resets to Mode 0, all inputs
-- Set Mode 1, Port A out, B in and check Port C Status
WriteReg(ControlReg, x"A6");
WriteReg(ChangeBit, x"0F"); -- Set Port C (7)
WriteReg(ChangeBit, x"02"); -- Reset Port C (1)
WriteReg(ChangeBit, x"00"); -- Reset Port C (0)
ReadReg(PortC, x"80"); -- Read Port C Status (only OBFA is set)
-- Load Port output registers
WriteReg(PortA, x"11");
-- Read all ports
ReadReg(PortB, x"11");
ReadReg(PortC, x"80"); -- Read Port C Status (only OBFA is set)
-- Do same test with interrupt enables on
WriteReg(ChangeBit, x"0D"); -- Set Port A Int Enable (Port C (6))
WriteReg(ChangeBit, x"05"); -- Set Port B Int Enable (Port C (2))
ReadReg(PortC, x"C4"); -- Read Port C Status (OBFA, INTEA, and INTEB are set)
WriteReg(PortA, x"88");
ReadReg(PortC, x"C7"); -- Read Port C Status (everything but INTA is set)
ReadReg(PortB, x"88");
ReadReg(PortC, x"CC"); -- Read Port C Status
-- Load Port output registers to bring down INTA
WriteReg(PortA, x"00");
-- REVERSE LOOPBACK DIRECTION
-- Set Loop Back Mode
LoopBackMode <= Mode1_BToA;
-- Reset chip and set inputs to default values
InitInputsAndReset;
-- Read Control Reg after reset
ReadReg(ControlReg, x"9B"); -- Resets to Mode 0, all inputs
-- Set Mode 1, Port A out, B in and check Port C Status
WriteReg(ControlReg, x"B4");
WriteReg(ChangeBit, x"0E"); -- Reset Port C (7)
WriteReg(ChangeBit, x"0C"); -- Reset Port C (6)
WriteReg(ChangeBit, x"0A"); -- Reset Port C (5)
WriteReg(ChangeBit, x"08"); -- Reset Port C (4)
WriteReg(ChangeBit, x"06"); -- Reset Port C (3)
WriteReg(ChangeBit, x"04"); -- Reset Port C (2)
WriteReg(ChangeBit, x"03"); -- Set Port C (1)
WriteReg(ChangeBit, x"00"); -- Reset Port C (0)
ReadReg(PortC, x"02"); -- Read Port C Status (only OBFB is set)
-- Load Port output registers
WriteReg(PortB, x"33");
-- Read all ports
ReadReg(PortA, x"33");
ReadReg(PortC, x"02"); -- Read Port C Status (only OBFB is set)
-- Do same test with interrupt enables on
WriteReg(ChangeBit, x"09"); -- Set Port A Int Enable (Port C (4))
WriteReg(ChangeBit, x"05"); -- Set Port B Int Enable (Port C (2))
ReadReg(PortC, x"16"); -- Read Port C Status (OBFA, INTEA, and INTEB are set)
WriteReg(PortB, x"44");
ReadReg(PortC, x"3E"); -- Read Port C Status (everything but INTB is set)
ReadReg(PortA, x"44");
ReadReg(PortC, x"17"); -- Read Port C Status (INTB and OBFB set)
-- Load Port output registers to bring down INTB
WriteReg(PortB, x"FF");
------------------------------------------------------------
------------------------------------------------------------
ASSERT false REPORT "START MODE 2 TEST" SEVERITY NOTE;
-- Set Loop Back Mode
LoopBackMode <= Mode2_AToB;
-- Reset chip and set inputs to default values
InitInputsAndReset;
-- Read Control Reg after reset
ReadReg(ControlReg, x"9B"); -- Resets to Mode 0, all inputs
-- Set Port A to Mode 2, B in and check Port C Status
WriteReg(ControlReg, x"C6");
WriteReg(ChangeBit, x"0F"); -- Set Port C (7) --OBFA
WriteReg(ChangeBit, x"0C"); -- Reset Port C (6) --INTE1
WriteReg(ChangeBit, x"0A"); -- Reset Port C (5) --IBFA
WriteReg(ChangeBit, x"08"); -- Reset Port C (4) --INTE2
WriteReg(ChangeBit, x"06"); -- Reset Port C (3) --INTRA
WriteReg(ChangeBit, x"04"); -- Reset Port C (2) --INTEB
WriteReg(ChangeBit, x"02"); -- Reset Port C (1) --IBFB
WriteReg(ChangeBit, x"00"); -- Reset Port C (0) --INTRB
ReadReg(PortC, x"80"); -- Read Port C Status (only OBFA is set)
-- Load Port output registers
WriteReg(PortA, x"11");
-- Read all ports
ReadReg(PortB, x"11");
ReadReg(PortC, x"80"); -- Read Port C Status (only OBFA is set)
-- Do same test with interrupt enables on
WriteReg(ChangeBit, x"0D"); -- Set Port A Int Enable (Port C (6))
WriteReg(ChangeBit, x"05"); -- Set Port B Int Enable (Port C (2))
ReadReg(PortC, x"C4"); -- Read Port C Status (OBFA, INTEA, and INTEB are set)
WriteReg(PortA, x"88");
ReadReg(PortC, x"C7"); -- Read Port C Status (everything but INTA is set)
ReadReg(PortB, x"88");
ReadReg(PortC, x"CC"); -- Read Port C Status
-- Load Port output registers to bring down INTA
WriteReg(PortA, x"00");
-- Set Loop Back Mode
LoopBackMode <= Mode2_BToA;
-- Reset chip and set inputs to default values
InitInputsAndReset;
-- Read Control Reg after reset
ReadReg(ControlReg, x"9B"); -- Resets to Mode 0, all inputs
-- Set Port A to Mode 2, B out and check Port C Status
WriteReg(ControlReg, x"C4");
WriteReg(ChangeBit, x"0F"); -- Set Port C (7) --OBFA
WriteReg(ChangeBit, x"0C"); -- Reset Port C (6) --INTE1
WriteReg(ChangeBit, x"0A"); -- Reset Port C (5) --IBFA
WriteReg(ChangeBit, x"08"); -- Reset Port C (4) --INTE2
WriteReg(ChangeBit, x"06"); -- Reset Port C (3) --INTRA
WriteReg(ChangeBit, x"04"); -- Reset Port C (2) --INTEB
WriteReg(ChangeBit, x"03"); -- Set Port C (1) --OBFB
WriteReg(ChangeBit, x"00"); -- Reset Port C (0) --INTRB
ReadReg(PortC, x"82"); -- Read Port C Status (OBFA, OBFB is set)
-- Load Port output registers
WriteReg(PortB, x"66");
-- Read all ports
ReadReg(PortA, x"66");
ReadReg(PortC, x"82"); -- Read Port C Status (only OBFA is set)
-- Do same test with interrupt enables on
WriteReg(ChangeBit, x"09"); -- Set Port A Int Enable (Port C (4))
WriteReg(ChangeBit, x"05"); -- Set Port B Int Enable (Port C (2))
ReadReg(PortC, x"96"); -- Read Port C Status (OBFA, INTEA2, and INTEB are set)
WriteReg(PortB, x"88");
ReadReg(PortC, x"BE"); -- Read Port C Status (everything but INTRB is set)
ReadReg(PortA, x"88");
ReadReg(PortC, x"97"); -- Read Port C Status
-- Load Port output registers to bring down INTA
WriteReg(PortB, x"00");
ASSERT false REPORT "END OF TEST" SEVERITY NOTE;
WAIT;
END PROCESS GeneralStimulus;
------------------------------------------------------------
-- Process to loop PA to PB, and PC upper to PC lower
------------------------------------------------------------
OutputBufferPrc : Process (PAEN_Resp, PBEN_Resp, PCEN_Resp, PAOUT_Resp, PBOUT_Resp, PCOUT_Resp)
BEGIN
IF (PAEN_Resp = '1') THEN
PA <= PAOUT_Resp AFTER LoopDelay;
ELSE
PA <= "ZZZZZZZZ" AFTER LoopDelay;
END IF;
IF (PBEN_Resp = '1') THEN
PB <= PBOUT_Resp AFTER LoopDelay;
ELSE
PB <= "ZZZZZZZZ" AFTER LoopDelay;
END IF;
FOR I IN 0 TO 7 LOOP
IF (PCEN_Resp(I) = '1') THEN
PC(I) <= PCOUT_Resp(I) AFTER LoopDelay;
ELSE
PC(I) <= 'Z' AFTER LoopDelay;
END IF;
END LOOP;
END PROCESS OutputBufferPrc;
-- -- Output buffer assignments
PAIN_Stim <= PA;
PBIN_Stim <= PB;
PCIN_Stim <= PC;
-- Loop back assignments
LoopBackPrc : Process (LoopBackMode, PA, PB, PC)
BEGIN
PAIN_Stim <= PB ;
PBIN_Stim <= PA ;
IF (LoopBackMode = Mode0) THEN
PCIN_Stim (7 DOWNTO 4) <= PC (3 DOWNTO 0) ;
PCIN_Stim (3 DOWNTO 0) <= PC (7 DOWNTO 4) ;
ELSIF (LoopBackMode = Mode1_BToA) THEN
PCIN_Stim (7) <= PC (7) ;
PCIN_Stim (6) <= PC (6) ;
PCIN_Stim (5) <= PC (5) ;
PCIN_Stim (4) <= PC (1) ; -- OBFB to STBA
PCIN_Stim (3) <= PC (3) ;
PCIN_Stim (2) <= NOT PC (5) ; -- IBFA to ACKB
PCIN_Stim (1) <= PC (1) ;
PCIN_Stim (0) <= PC (0) ;
ELSIF (LoopBackMode = Mode2_BToA) THEN
PCIN_Stim (7) <= PC (7) ;
PCIN_Stim (6) <= '1';
PCIN_Stim (5) <= PC (5) ;
PCIN_Stim (4) <= PC (1) ; -- OBFB to STBA
PCIN_Stim (3) <= PC (3) ;
PCIN_Stim (2) <= NOT PC (5) ; -- IBFA to ACKB
PCIN_Stim (1) <= PC (1) ;
PCIN_Stim (0) <= PC (0) ;
ELSIF (LoopBackMode = Mode1_AToB) THEN
PCIN_Stim (0) <= PC (0) ;
PCIN_Stim (1) <= PC (1) ;
PCIN_Stim (2) <= PC (7) ; -- OBFA to STBB
PCIN_Stim (3) <= PC (3) ;
PCIN_Stim (4) <= PC (4) ;
PCIN_Stim (5) <= PC (5) ;
PCIN_Stim (6) <= NOT PC (1) ; -- IBFB to ACKA
PCIN_Stim (7) <= PC (7) ;
ELSIF (LoopBackMode = Mode2_AToB) THEN
PCIN_Stim (0) <= PC (0) ;
PCIN_Stim (1) <= PC (1) ;
PCIN_Stim (2) <= PC (7) ; -- OBFA to STBB
PCIN_Stim (3) <= PC (3) ;
PCIN_Stim (4) <= '1';
PCIN_Stim (5) <= PC (5) ;
PCIN_Stim (6) <= NOT PC (1) ; -- IBFB to ACKA
PCIN_Stim (7) <= PC (7) ;
END IF;
END PROCESS LoopBackPrc;
END MainTest;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Gaisler Research
--
-- Modified by Joris van Rantwijk to support Digilent Atlys board.
--
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- led(6) = dsuact (LED 6 ON when processor in debug mode)
-- led(7) = not errorn (LED 7 ON when processor in error mode)
-- switch(6) = dsubre (SWITCH 6 ON to force DSU break)
-- switch(7) = dsuen (SWITCH 7 ON to enable debug mode)
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
library unisim;
use unisim.vcomponents.OBUFDS;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 100 MHz board clock
-- DDR2 memory
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_we : out std_ulogic;
ddr_ras : out std_ulogic;
ddr_cas : out std_ulogic;
ddr_dm : out std_logic_vector (1 downto 0);
ddr_dqs : inout std_logic_vector (1 downto 0);
ddr_dqsn : inout std_logic_vector (1 downto 0);
ddr_ad : out std_logic_vector (12 downto 0);
ddr_ba : out std_logic_vector (2 downto 0);
ddr_dq : inout std_logic_vector (15 downto 0);
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
-- dsuen : in std_ulogic; -- switch(7)
-- dsubre : in std_ulogic; -- switch(6)
-- dsuact : out std_ulogic; -- led(6)
-- errorn : out std_ulogic; -- led(7)
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
-- GPIO
pmoda : inout std_logic_vector(7 downto 0);
switch : in std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0);
button : in std_logic_vector(4 downto 0);
-- MII Ethernet
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erst : out std_ulogic;
egtxclk : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
emdint : in std_ulogic;
-- PS/2
kbd_clk : inout std_logic;
kbd_data : inout std_logic;
mou_clk : inout std_logic;
mou_data : inout std_logic;
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : inout std_ulogic;
-- HDMI port
tmdstx_clk_p : out std_logic;
tmdstx_clk_n : out std_logic;
tmdstx_dat_p : out std_logic_vector(2 downto 0);
tmdstx_dat_n : out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of leon3mp is
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw : std_ulogic;
signal clk200 : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lock, calib_done, lclk : std_ulogic;
signal rstext : std_ulogic;
signal rstint : std_ulogic;
signal errorp : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddr2clk : std_ulogic;
signal ddr0_clk_fb : std_ulogic;
signal ddr0_clk : std_logic_vector(2 downto 0);
signal ddr0_clkb : std_logic_vector(2 downto 0);
signal ddr0_cke : std_logic_vector(1 downto 0);
signal ddr0_odt : std_logic_vector(1 downto 0);
signal ddr0_ad : std_logic_vector(13 downto 0);
signal ddr0_lock: std_ulogic;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal video_clk : std_logic;
signal video_fastclk : std_logic;
signal video_clksel : std_logic_vector(1 downto 0);
signal tmds_clk : std_logic;
signal tmds_dat : std_logic_vector(2 downto 0);
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
-- constant DDR2_FREQ : integer := 150000; -- DDR2 input frequency in KHz
signal stati : ahbstat_in_type;
signal leon_rstn : std_ulogic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_preserve of ddr2clk : signal is true;
attribute keep of ddr2clk : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of video_fastclk : signal is true;
attribute keep of video_fastclk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (clkin => lclk, pciclkin => lclk,
clk => clkm, clkn => open, clk2x => open,
sdclk => open, pciclk => open,
cgi => cgi, cgo => cgo,
clk4x => open, clk1xu => open, clk2xu => clk200);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rstext);
rst0 : rstgen -- reset generator
port map (rstint, clkm, lock, rstn, rstraw);
lock <= cgo.clklock and ddr0_lock;
-- Generate clean internal reset from external reset and watchdog.
rst1 : process (lclk, rstext) is
variable v_shift: std_logic_vector(3 downto 0);
variable v_wdog: std_logic_vector(2 downto 0);
begin
if rstext = '0' then
rstint <= '0';
v_shift := (others => '0');
v_wdog := (others => '0');
elsif rising_edge(lclk) then
rstint <= v_shift(0);
if CFG_GPT_WDOGEN /= 0 and v_wdog(0) = '1' then
v_shift := (others => '0');
else
v_shift := '1' & v_shift(3 downto 1);
end if;
if CFG_GPT_WDOGEN /= 0 then
v_wdog(0) := v_wdog(2) and not v_wdog(1);
v_wdog(1) := v_wdog(2);
v_wdog(2) := gpto.wdog;
end if;
end if;
end process;
leon_rstn <= rstn and spmo.initialized;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, leon_rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, leon_rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, leon_rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, leon_rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
-- LED(7) = error
errorp <= not dbgo(0).error;
led1_pad : outpad generic map (tech => padtech) port map (led(7), errorp);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
-- SWITCH(7) = dsuen
dsuen_pad : inpad generic map (tech => padtech) port map (switch(7), dsui.enable);
-- SWITCH(6) = dsubre
dsubre_pad : inpad generic map (tech => padtech) port map (switch(6), dsui.break);
-- LED(6) = dsuact
dsuact_pad : outpad generic map (tech => padtech) port map (led(6), dsuo.active);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mctrl_gen : if (CFG_MCTRL_LEON2 /= 0) generate
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
memi.data <= (others => '0'); -- Atlys board has no asynchronous memory bus
memi.sd <= (others => '0'); -- Atlys board has no classic SDRAM
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr_gen : if (CFG_DDR2SP = 1) generate
ddr0: ddr2spa
generic map (
fabtech => fabtech,
memtech => memtech,
rskew => 0,
hindex => 4,
haddr => 16#400#,
hmask => 16#f80#,
ioaddr => 16#001#,
iomask => 16#fff#,
MHz => CPU_FREQ/1000,
TRFC => CFG_DDR2SP_TRFC,
clkmul => 6,
clkdiv => 2,
col => CFG_DDR2SP_COL,
Mbyte => CFG_DDR2SP_SIZE,
rstdel => 200,
pwron => CFG_DDR2SP_INIT,
ddrbits => CFG_DDR2SP_DATAWIDTH,
ahbfreq => CPU_FREQ/1000,
readdly => 1,
norefclk => 0,
odten => 3,
dqsgating => 0,
nosync => CFG_DDR2SP_NOSYNC,
eightbanks => 1,
dqsse => 0,
burstlen => 8,
ft => CFG_DDR2SP_FTEN,
ftbits => CFG_DDR2SP_FTWIDTH,
bigmem => 0,
raspipe => 0 )
port map (
rst_ddr => rstraw,
rst_ahb => rstn,
clk_ddr => clkm,
clk_ahb => clkm,
clkref200 => clk200,
lock => ddr0_lock,
clkddro => ddr2clk,
clkddri => ddr2clk,
ahbsi => ahbsi,
ahbso => ahbso(4),
ddr_clk => ddr0_clk,
ddr_clkb => ddr0_clkb,
ddr_clk_fb_out => ddr0_clk_fb,
ddr_clk_fb => ddr0_clk_fb,
ddr_cke => ddr0_cke,
ddr_csb => open,
ddr_web => ddr_we,
ddr_rasb => ddr_ras,
ddr_casb => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr0_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
ddr_odt => ddr0_odt,
ce => open );
ddr_clk <= ddr0_clk(0);
ddr_clkb <= ddr0_clkb(0);
ddr_cke <= ddr0_cke(0);
ddr_odt <= ddr0_odt(0);
ddr_ad <= ddr0_ad(12 downto 0);
ddr_rzq <= 'Z';
ddr_zio <= 'Z';
end generate;
ddr_nogen : if (CFG_DDR2SP /= 1) generate
ddr0_lock <= '1';
ddrcke_nopad : outpad generic map (tech => padtech) port map (ddr_cke, gnd);
end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
-- Numonyx N25Q12 16 MByte SPI flash memory
-- SPI memory controller is mapped at address 0 if AHBROM is disabled.
-- If AHBROM is enabled then the SPI Flash area is mapped at 0xe0000000
spimc: if CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 11, faddr => 16#e00#*CFG_AHBROMEN,
fmask => 16#ff0#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT,
offset => CFG_SPIMCTRL_OFFSET)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
miso_pad : inpad generic map (tech => padtech)
port map (spi_miso, spmi.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi, spmo.mosioen , spmi.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
spisel_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc : if CFG_SPIMCTRL = 0 generate
spmo.initialized <= '1';
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
u1i.ctsn <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
notxd : if CFG_UART1_ENABLE = 0 and CFG_AHB_UART = 0 generate
notxd_pad : outpad generic map (tech => padtech) port map (txd1, vcc);
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (kbd_clk, kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (kbd_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (mou_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (mou_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map (pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 32)
port map (rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
-- Map GPIO bits 0 to 5 to LEDS 0 to 5.
gpio_led_pads : outpadv
generic map (tech => padtech, width => 6)
port map (led(5 downto 0), gpioo.dout(5 downto 0));
-- Map GPIO bits 8 to 13 to SWITCHES 0 to 5.
gpio_sw_pads : inpadv
generic map (tech => padtech, width => 6)
port map (switch(5 downto 0), gpioi.din(13 downto 8));
-- Map GPIO bits 16 to 20 to BUTTONS 0 to 4.
gpio_button_pads : inpadv
generic map (tech => padtech, width => 5)
port map (button(4 downto 0), gpioi.din(20 downto 16));
-- Map GPIO bits 24 to 31 to PMODA port.
gpio_pmod_pads : for i in 0 to 7 generate
gpio_pmod_padi : iopad
generic map (tech => padtech)
port map (pmoda(i), gpioo.dout(24+i), gpioo.oen(24+i), gpioi.din(24+i));
end generate;
gpioi.din(7 downto 0) <= (others => '0');
gpioi.din(15 downto 14) <= (others => '0');
gpioi.din(23 downto 21) <= (others => '0');
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => 0)
port map (
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
etxc_pad : clkpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, ethi.mdint);
end generate;
eth_nopads : if (CFG_GRETH /= 1) generate -- eth pads
etxd_nopad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, "00000000");
etxen_nopad : outpad generic map (tech => padtech)
port map (etx_en, '0');
etxer_nopad : outpad generic map (tech => padtech)
port map (etx_er, '0');
emdc_nopad : outpad generic map (tech => padtech)
port map (emdc, '0');
emdio_nopad : iopad generic map (tech => padtech)
port map (emdio, '0', '1', open);
end generate;
erst_pad : outpad generic map (tech => padtech)
port map (erst, rstraw);
egtxclk_pad : outpad generic map (tech => padtech)
port map (egtxclk, '0');
ethi.gtx_clk <= '0';
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP )
port map (rstn, clkm, ahbsi, ahbso(6));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- VGA / HDMI ------------------------------------------------------
-----------------------------------------------------------------------
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga
generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao);
video_clksel <= "00"; -- fixed 25 MHz
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl
generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
clk0 => 40000, clk1 => 25000, clk2 => 40000, clk3 => 25000,
burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao,
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH),
video_clksel);
end generate;
tmds : if CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /= 0 generate
vgaclk0 : entity work.vga_clkgen
port map (resetn => rstraw, clk100 => lclk, sel => video_clksel,
vgaclk => video_clk, fastclk => video_fastclk);
tmds0 : entity work.vga2tmds
generic map (tech => fabtech)
port map (vgaclk => video_clk, fastclk => video_fastclk, vgao => vgao,
tmdsclk => tmds_clk, tmdsdat => tmds_dat );
tmdsc_pad : OBUFDS
port map (O => tmdstx_clk_p, OB => tmdstx_clk_n, I => tmds_clk);
tmdsd_pad : for i in 0 to 2 generate
tmdsdi_pad : OBUFDS
port map (O => tmdstx_dat_p(i), OB => tmdstx_dat_n(i), I => tmds_dat(i));
end generate;
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
tmdsc_pad : OBUFDS
port map (O => tmdstx_clk_p, OB => tmdstx_clk_n, I => gnd);
tmdsd_pad : for i in 0 to 2 generate
tmdsdi_pad : OBUFDS
port map (O => tmdstx_dat_p(i), OB => tmdstx_dat_n(i), I => gnd);
end generate;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent-Atlys-XC6SLX45 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end architecture;
|
library ieee ;
use ieee.std_logic_1164.all;
entity hls_toplevel is
port(
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
m_axi_mem_AWVALID : OUT STD_LOGIC;
m_axi_mem_AWREADY : IN STD_LOGIC;
m_axi_mem_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mem_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_mem_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mem_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mem_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_AWLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mem_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_AWREGION : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_WVALID : OUT STD_LOGIC;
m_axi_mem_WREADY : IN STD_LOGIC;
m_axi_mem_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mem_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_WLAST : OUT STD_LOGIC;
m_axi_mem_WID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_mem_ARVALID : OUT STD_LOGIC;
m_axi_mem_ARREADY : IN STD_LOGIC;
m_axi_mem_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mem_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_mem_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mem_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mem_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_ARLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mem_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_ARREGION : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_RVALID : IN STD_LOGIC;
m_axi_mem_RREADY : OUT STD_LOGIC;
m_axi_mem_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mem_RLAST : IN STD_LOGIC;
m_axi_mem_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_mem_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_BVALID : IN STD_LOGIC;
m_axi_mem_BREADY : OUT STD_LOGIC;
m_axi_mem_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
interrupt : OUT STD_LOGIC;
jamaica_syscall : OUT STD_LOGIC;
hold_outputs : IN STD_LOGIC
);
end entity hls_toplevel;
architecture rtl of hls_toplevel is
COMPONENT hls
PORT (
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
m_axi_MAXI_AWVALID : OUT STD_LOGIC;
m_axi_MAXI_AWREADY : IN STD_LOGIC;
m_axi_MAXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_MAXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_MAXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_MAXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_MAXI_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_AWREGION : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_AWUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_WVALID : OUT STD_LOGIC;
m_axi_MAXI_WREADY : IN STD_LOGIC;
m_axi_MAXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_MAXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_WLAST : OUT STD_LOGIC;
m_axi_MAXI_WID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_ARVALID : OUT STD_LOGIC;
m_axi_MAXI_ARREADY : IN STD_LOGIC;
m_axi_MAXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_MAXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_MAXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_MAXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_MAXI_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_ARREGION : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_ARUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_RVALID : IN STD_LOGIC;
m_axi_MAXI_RREADY : OUT STD_LOGIC;
m_axi_MAXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_MAXI_RLAST : IN STD_LOGIC;
m_axi_MAXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_BVALID : IN STD_LOGIC;
m_axi_MAXI_BREADY : OUT STD_LOGIC;
m_axi_MAXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
interrupt : OUT STD_LOGIC;
syscall_interrupt_i : IN STD_LOGIC;
syscall_interrupt_o : OUT STD_LOGIC
);
END COMPONENT;
-- Insert a pipeline stage on hold_outputs
signal reg_hold_outputs : std_logic := '0';
signal sig_s_axi_AXILiteS_AWVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_AWREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_AWADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sig_s_axi_AXILiteS_WVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_WREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_WDATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_s_axi_AXILiteS_WSTRB : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_s_axi_AXILiteS_ARVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_ARREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_ARADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sig_s_axi_AXILiteS_RVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_RREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_RDATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_s_axi_AXILiteS_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_s_axi_AXILiteS_BVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_BREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_ap_clk : STD_LOGIC;
signal sig_ap_rst_n : STD_LOGIC;
signal sig_m_axi_mem_AWVALID : STD_LOGIC;
signal sig_m_axi_mem_AWREADY : STD_LOGIC;
signal sig_m_axi_mem_AWADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_m_axi_mem_AWID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_AWLEN : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sig_m_axi_mem_AWSIZE : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal sig_m_axi_mem_AWBURST : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_AWLOCK : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_AWCACHE : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_AWPROT : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal sig_m_axi_mem_AWQOS : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_AWREGION : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_AWUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_WVALID : STD_LOGIC;
signal sig_m_axi_mem_WREADY : STD_LOGIC;
signal sig_m_axi_mem_WDATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_m_axi_mem_WSTRB : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_WLAST : STD_LOGIC;
signal sig_m_axi_mem_WID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_WUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_ARVALID : STD_LOGIC;
signal sig_m_axi_mem_ARREADY : STD_LOGIC;
signal sig_m_axi_mem_ARADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_m_axi_mem_ARID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_ARLEN : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sig_m_axi_mem_ARSIZE : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal sig_m_axi_mem_ARBURST : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_ARLOCK : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_ARCACHE : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_ARPROT : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal sig_m_axi_mem_ARQOS : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_ARREGION : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_ARUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_RVALID : STD_LOGIC;
signal sig_m_axi_mem_RREADY : STD_LOGIC;
signal sig_m_axi_mem_RDATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_m_axi_mem_RLAST : STD_LOGIC;
signal sig_m_axi_mem_RID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_RUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_BVALID : STD_LOGIC;
signal sig_m_axi_mem_BREADY : STD_LOGIC;
signal sig_m_axi_mem_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_BID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_BUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_interrupt : STD_LOGIC;
signal sig_dummy_user : STD_LOGIC_VECTOR(0 downto 0);
signal sig_syscall_interrupt_o : STD_LOGIC;
attribute S : string;
attribute S of sig_dummy_user : signal is "TRUE";
begin
update_output_hold: process(sig_ap_clk,sig_ap_rst_n)
begin
if (sig_ap_rst_n = '0') then
reg_hold_outputs <= '0';
elsif (sig_ap_clk = '1' and sig_ap_clk'event) then
reg_hold_outputs <= hold_outputs;
end if;
end process;
brg : hls
PORT MAP (
s_axi_AXILiteS_AWVALID => sig_s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY => sig_s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWADDR => sig_s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_WVALID => sig_s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY => sig_s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WDATA => sig_s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB => sig_s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_ARVALID => sig_s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY => sig_s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARADDR => sig_s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_RVALID => sig_s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY => sig_s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RDATA => sig_s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP => sig_s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_BVALID => sig_s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY => sig_s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP => sig_s_axi_AXILiteS_BRESP,
ap_clk => sig_ap_clk,
ap_rst_n => sig_ap_rst_n,
m_axi_MAXI_AWVALID => sig_m_axi_mem_AWVALID,
m_axi_MAXI_AWREADY => sig_m_axi_mem_AWREADY,
m_axi_MAXI_AWADDR => sig_m_axi_mem_AWADDR,
m_axi_MAXI_AWID => sig_m_axi_mem_AWID,
m_axi_MAXI_AWLEN => sig_m_axi_mem_AWLEN,
m_axi_MAXI_AWSIZE => sig_m_axi_mem_AWSIZE,
m_axi_MAXI_AWBURST => sig_m_axi_mem_AWBURST,
m_axi_MAXI_AWLOCK => sig_m_axi_mem_AWLOCK,
m_axi_MAXI_AWCACHE => sig_m_axi_mem_AWCACHE,
m_axi_MAXI_AWPROT => sig_m_axi_mem_AWPROT,
m_axi_MAXI_AWQOS => sig_m_axi_mem_AWQOS,
m_axi_MAXI_AWREGION => sig_m_axi_mem_AWREGION,
m_axi_MAXI_AWUSER => sig_m_axi_mem_AWUSER,
m_axi_MAXI_WVALID => sig_m_axi_mem_WVALID,
m_axi_MAXI_WREADY => sig_m_axi_mem_WREADY,
m_axi_MAXI_WDATA => sig_m_axi_mem_WDATA,
m_axi_MAXI_WSTRB => sig_m_axi_mem_WSTRB,
m_axi_MAXI_WLAST => sig_m_axi_mem_WLAST,
m_axi_MAXI_WID => sig_m_axi_mem_WID,
m_axi_MAXI_WUSER => sig_m_axi_mem_WUSER,
m_axi_MAXI_ARVALID => sig_m_axi_mem_ARVALID,
m_axi_MAXI_ARREADY => sig_m_axi_mem_ARREADY,
m_axi_MAXI_ARADDR => sig_m_axi_mem_ARADDR,
m_axi_MAXI_ARID => sig_m_axi_mem_ARID,
m_axi_MAXI_ARLEN => sig_m_axi_mem_ARLEN,
m_axi_MAXI_ARSIZE => sig_m_axi_mem_ARSIZE,
m_axi_MAXI_ARBURST => sig_m_axi_mem_ARBURST,
m_axi_MAXI_ARLOCK => sig_m_axi_mem_ARLOCK,
m_axi_MAXI_ARCACHE => sig_m_axi_mem_ARCACHE,
m_axi_MAXI_ARPROT => sig_m_axi_mem_ARPROT,
m_axi_MAXI_ARQOS => sig_m_axi_mem_ARQOS,
m_axi_MAXI_ARREGION => sig_m_axi_mem_ARREGION,
m_axi_MAXI_ARUSER => sig_m_axi_mem_ARUSER,
m_axi_MAXI_RVALID => sig_m_axi_mem_RVALID,
m_axi_MAXI_RREADY => sig_m_axi_mem_RREADY,
m_axi_MAXI_RDATA => sig_m_axi_mem_RDATA,
m_axi_MAXI_RLAST => sig_m_axi_mem_RLAST,
m_axi_MAXI_RID => sig_m_axi_mem_RID,
m_axi_MAXI_RUSER => sig_dummy_user,
m_axi_MAXI_RRESP => sig_m_axi_mem_RRESP,
m_axi_MAXI_BVALID => sig_m_axi_mem_BVALID,
m_axi_MAXI_BREADY => sig_m_axi_mem_BREADY,
m_axi_MAXI_BRESP => sig_m_axi_mem_BRESP,
m_axi_MAXI_BID => sig_m_axi_mem_BID,
m_axi_MAXI_BUSER => "0",
interrupt => sig_interrupt,
syscall_interrupt_o => sig_syscall_interrupt_o,
syscall_interrupt_i => '0'
);
s_axi_AXILiteS_AWREADY <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_AWREADY;
s_axi_AXILiteS_WREADY <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_WREADY ;
s_axi_AXILiteS_ARREADY <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_ARREADY;
s_axi_AXILiteS_RVALID <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_RVALID ;
s_axi_AXILiteS_RDATA <= (not (31 downto 0 => reg_hold_outputs)) and sig_s_axi_AXILiteS_RDATA;
s_axi_AXILiteS_RRESP <= (not (1 downto 0 => reg_hold_outputs)) and sig_s_axi_AXILiteS_RRESP;
s_axi_AXILiteS_BVALID <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_BVALID ;
s_axi_AXILiteS_BRESP <= (not (1 downto 0 => reg_hold_outputs)) and sig_s_axi_AXILiteS_BRESP;
m_axi_mem_AWVALID <= (not reg_hold_outputs) and sig_m_axi_mem_AWVALID ;
m_axi_mem_AWADDR <= (not (31 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWADDR ;
m_axi_mem_AWID <= (not (0 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWID ;
m_axi_mem_AWLEN <= (not (7 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWLEN ;
m_axi_mem_AWSIZE <= (not (2 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWSIZE ;
m_axi_mem_AWBURST <= (not (1 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWBURST ;
m_axi_mem_AWLOCK <= (not (1 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWLOCK ;
m_axi_mem_AWCACHE <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWCACHE ;
m_axi_mem_AWPROT <= (not (2 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWPROT ;
m_axi_mem_AWQOS <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWQOS ;
m_axi_mem_AWREGION <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWREGION;
m_axi_mem_WVALID <= (not reg_hold_outputs) and sig_m_axi_mem_WVALID ;
m_axi_mem_WDATA <= (not (31 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_WDATA;
m_axi_mem_WSTRB <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_WSTRB;
m_axi_mem_WLAST <= (not reg_hold_outputs) and sig_m_axi_mem_WLAST ;
m_axi_mem_WID <= (not (0 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_WID;
m_axi_mem_ARVALID <= (not reg_hold_outputs) and sig_m_axi_mem_ARVALID ;
m_axi_mem_ARADDR <= (not (31 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARADDR ;
m_axi_mem_ARID <= (not (0 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARID ;
m_axi_mem_ARLEN <= (not (7 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARLEN ;
m_axi_mem_ARSIZE <= (not (2 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARSIZE ;
m_axi_mem_ARBURST <= (not (1 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARBURST ;
m_axi_mem_ARLOCK <= (not (1 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARLOCK ;
m_axi_mem_ARCACHE <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARCACHE ;
m_axi_mem_ARPROT <= (not (2 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARPROT ;
m_axi_mem_ARQOS <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARQOS ;
m_axi_mem_ARREGION <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARREGION;
m_axi_mem_RREADY <= (not reg_hold_outputs) and sig_m_axi_mem_RREADY ;
m_axi_mem_BREADY <= (not reg_hold_outputs) and sig_m_axi_mem_BREADY ;
interrupt <= (not reg_hold_outputs) and sig_interrupt ;
sig_s_axi_AXILiteS_AWVALID <= s_axi_AXILiteS_AWVALID;
sig_s_axi_AXILiteS_AWADDR <= s_axi_AXILiteS_AWADDR ;
sig_s_axi_AXILiteS_WVALID <= s_axi_AXILiteS_WVALID ;
sig_s_axi_AXILiteS_WDATA <= s_axi_AXILiteS_WDATA ;
sig_s_axi_AXILiteS_WSTRB <= s_axi_AXILiteS_WSTRB ;
sig_s_axi_AXILiteS_ARVALID <= s_axi_AXILiteS_ARVALID;
sig_s_axi_AXILiteS_ARADDR <= s_axi_AXILiteS_ARADDR ;
sig_s_axi_AXILiteS_RREADY <= s_axi_AXILiteS_RREADY ;
sig_s_axi_AXILiteS_BREADY <= s_axi_AXILiteS_BREADY ;
sig_ap_clk <= ap_clk ;
sig_ap_rst_n <= (not reg_hold_outputs) and ap_rst_n; -- Also hold reset when isolated...
sig_m_axi_mem_AWREADY <= m_axi_mem_AWREADY ;
sig_m_axi_mem_WREADY <= m_axi_mem_WREADY ;
sig_m_axi_mem_ARREADY <= m_axi_mem_ARREADY ;
sig_m_axi_mem_RVALID <= m_axi_mem_RVALID ;
sig_m_axi_mem_RDATA <= m_axi_mem_RDATA ;
sig_m_axi_mem_RLAST <= m_axi_mem_RLAST ;
sig_m_axi_mem_RID <= m_axi_mem_RID ;
sig_m_axi_mem_RRESP <= m_axi_mem_RRESP ;
sig_m_axi_mem_BVALID <= m_axi_mem_BVALID ;
sig_m_axi_mem_BRESP <= m_axi_mem_BRESP ;
sig_m_axi_mem_BID <= m_axi_mem_BID ;
sig_dummy_user <= sig_m_axi_mem_AWUSER or sig_m_axi_mem_WUSER or sig_m_axi_mem_ARUSER;
jamaica_syscall <= (not reg_hold_outputs) and sig_syscall_interrupt_o;
end architecture rtl;
|
library ieee ;
use ieee.std_logic_1164.all;
entity hls_toplevel is
port(
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
m_axi_mem_AWVALID : OUT STD_LOGIC;
m_axi_mem_AWREADY : IN STD_LOGIC;
m_axi_mem_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mem_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_mem_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mem_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mem_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_AWLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mem_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_AWREGION : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_WVALID : OUT STD_LOGIC;
m_axi_mem_WREADY : IN STD_LOGIC;
m_axi_mem_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mem_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_WLAST : OUT STD_LOGIC;
m_axi_mem_WID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_mem_ARVALID : OUT STD_LOGIC;
m_axi_mem_ARREADY : IN STD_LOGIC;
m_axi_mem_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mem_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_mem_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mem_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mem_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_ARLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mem_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_ARREGION : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_RVALID : IN STD_LOGIC;
m_axi_mem_RREADY : OUT STD_LOGIC;
m_axi_mem_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mem_RLAST : IN STD_LOGIC;
m_axi_mem_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_mem_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_BVALID : IN STD_LOGIC;
m_axi_mem_BREADY : OUT STD_LOGIC;
m_axi_mem_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
interrupt : OUT STD_LOGIC;
jamaica_syscall : OUT STD_LOGIC;
hold_outputs : IN STD_LOGIC
);
end entity hls_toplevel;
architecture rtl of hls_toplevel is
COMPONENT hls
PORT (
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
m_axi_MAXI_AWVALID : OUT STD_LOGIC;
m_axi_MAXI_AWREADY : IN STD_LOGIC;
m_axi_MAXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_MAXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_MAXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_MAXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_MAXI_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_AWREGION : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_AWUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_WVALID : OUT STD_LOGIC;
m_axi_MAXI_WREADY : IN STD_LOGIC;
m_axi_MAXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_MAXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_WLAST : OUT STD_LOGIC;
m_axi_MAXI_WID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_ARVALID : OUT STD_LOGIC;
m_axi_MAXI_ARREADY : IN STD_LOGIC;
m_axi_MAXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_MAXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_MAXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_MAXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_MAXI_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_ARREGION : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_ARUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_RVALID : IN STD_LOGIC;
m_axi_MAXI_RREADY : OUT STD_LOGIC;
m_axi_MAXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_MAXI_RLAST : IN STD_LOGIC;
m_axi_MAXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_BVALID : IN STD_LOGIC;
m_axi_MAXI_BREADY : OUT STD_LOGIC;
m_axi_MAXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
interrupt : OUT STD_LOGIC;
syscall_interrupt_i : IN STD_LOGIC;
syscall_interrupt_o : OUT STD_LOGIC
);
END COMPONENT;
-- Insert a pipeline stage on hold_outputs
signal reg_hold_outputs : std_logic := '0';
signal sig_s_axi_AXILiteS_AWVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_AWREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_AWADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sig_s_axi_AXILiteS_WVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_WREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_WDATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_s_axi_AXILiteS_WSTRB : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_s_axi_AXILiteS_ARVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_ARREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_ARADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sig_s_axi_AXILiteS_RVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_RREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_RDATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_s_axi_AXILiteS_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_s_axi_AXILiteS_BVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_BREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_ap_clk : STD_LOGIC;
signal sig_ap_rst_n : STD_LOGIC;
signal sig_m_axi_mem_AWVALID : STD_LOGIC;
signal sig_m_axi_mem_AWREADY : STD_LOGIC;
signal sig_m_axi_mem_AWADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_m_axi_mem_AWID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_AWLEN : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sig_m_axi_mem_AWSIZE : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal sig_m_axi_mem_AWBURST : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_AWLOCK : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_AWCACHE : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_AWPROT : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal sig_m_axi_mem_AWQOS : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_AWREGION : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_AWUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_WVALID : STD_LOGIC;
signal sig_m_axi_mem_WREADY : STD_LOGIC;
signal sig_m_axi_mem_WDATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_m_axi_mem_WSTRB : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_WLAST : STD_LOGIC;
signal sig_m_axi_mem_WID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_WUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_ARVALID : STD_LOGIC;
signal sig_m_axi_mem_ARREADY : STD_LOGIC;
signal sig_m_axi_mem_ARADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_m_axi_mem_ARID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_ARLEN : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sig_m_axi_mem_ARSIZE : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal sig_m_axi_mem_ARBURST : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_ARLOCK : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_ARCACHE : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_ARPROT : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal sig_m_axi_mem_ARQOS : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_ARREGION : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_ARUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_RVALID : STD_LOGIC;
signal sig_m_axi_mem_RREADY : STD_LOGIC;
signal sig_m_axi_mem_RDATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_m_axi_mem_RLAST : STD_LOGIC;
signal sig_m_axi_mem_RID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_RUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_BVALID : STD_LOGIC;
signal sig_m_axi_mem_BREADY : STD_LOGIC;
signal sig_m_axi_mem_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_BID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_BUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_interrupt : STD_LOGIC;
signal sig_dummy_user : STD_LOGIC_VECTOR(0 downto 0);
signal sig_syscall_interrupt_o : STD_LOGIC;
attribute S : string;
attribute S of sig_dummy_user : signal is "TRUE";
begin
update_output_hold: process(sig_ap_clk,sig_ap_rst_n)
begin
if (sig_ap_rst_n = '0') then
reg_hold_outputs <= '0';
elsif (sig_ap_clk = '1' and sig_ap_clk'event) then
reg_hold_outputs <= hold_outputs;
end if;
end process;
brg : hls
PORT MAP (
s_axi_AXILiteS_AWVALID => sig_s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY => sig_s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWADDR => sig_s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_WVALID => sig_s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY => sig_s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WDATA => sig_s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB => sig_s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_ARVALID => sig_s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY => sig_s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARADDR => sig_s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_RVALID => sig_s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY => sig_s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RDATA => sig_s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP => sig_s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_BVALID => sig_s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY => sig_s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP => sig_s_axi_AXILiteS_BRESP,
ap_clk => sig_ap_clk,
ap_rst_n => sig_ap_rst_n,
m_axi_MAXI_AWVALID => sig_m_axi_mem_AWVALID,
m_axi_MAXI_AWREADY => sig_m_axi_mem_AWREADY,
m_axi_MAXI_AWADDR => sig_m_axi_mem_AWADDR,
m_axi_MAXI_AWID => sig_m_axi_mem_AWID,
m_axi_MAXI_AWLEN => sig_m_axi_mem_AWLEN,
m_axi_MAXI_AWSIZE => sig_m_axi_mem_AWSIZE,
m_axi_MAXI_AWBURST => sig_m_axi_mem_AWBURST,
m_axi_MAXI_AWLOCK => sig_m_axi_mem_AWLOCK,
m_axi_MAXI_AWCACHE => sig_m_axi_mem_AWCACHE,
m_axi_MAXI_AWPROT => sig_m_axi_mem_AWPROT,
m_axi_MAXI_AWQOS => sig_m_axi_mem_AWQOS,
m_axi_MAXI_AWREGION => sig_m_axi_mem_AWREGION,
m_axi_MAXI_AWUSER => sig_m_axi_mem_AWUSER,
m_axi_MAXI_WVALID => sig_m_axi_mem_WVALID,
m_axi_MAXI_WREADY => sig_m_axi_mem_WREADY,
m_axi_MAXI_WDATA => sig_m_axi_mem_WDATA,
m_axi_MAXI_WSTRB => sig_m_axi_mem_WSTRB,
m_axi_MAXI_WLAST => sig_m_axi_mem_WLAST,
m_axi_MAXI_WID => sig_m_axi_mem_WID,
m_axi_MAXI_WUSER => sig_m_axi_mem_WUSER,
m_axi_MAXI_ARVALID => sig_m_axi_mem_ARVALID,
m_axi_MAXI_ARREADY => sig_m_axi_mem_ARREADY,
m_axi_MAXI_ARADDR => sig_m_axi_mem_ARADDR,
m_axi_MAXI_ARID => sig_m_axi_mem_ARID,
m_axi_MAXI_ARLEN => sig_m_axi_mem_ARLEN,
m_axi_MAXI_ARSIZE => sig_m_axi_mem_ARSIZE,
m_axi_MAXI_ARBURST => sig_m_axi_mem_ARBURST,
m_axi_MAXI_ARLOCK => sig_m_axi_mem_ARLOCK,
m_axi_MAXI_ARCACHE => sig_m_axi_mem_ARCACHE,
m_axi_MAXI_ARPROT => sig_m_axi_mem_ARPROT,
m_axi_MAXI_ARQOS => sig_m_axi_mem_ARQOS,
m_axi_MAXI_ARREGION => sig_m_axi_mem_ARREGION,
m_axi_MAXI_ARUSER => sig_m_axi_mem_ARUSER,
m_axi_MAXI_RVALID => sig_m_axi_mem_RVALID,
m_axi_MAXI_RREADY => sig_m_axi_mem_RREADY,
m_axi_MAXI_RDATA => sig_m_axi_mem_RDATA,
m_axi_MAXI_RLAST => sig_m_axi_mem_RLAST,
m_axi_MAXI_RID => sig_m_axi_mem_RID,
m_axi_MAXI_RUSER => sig_dummy_user,
m_axi_MAXI_RRESP => sig_m_axi_mem_RRESP,
m_axi_MAXI_BVALID => sig_m_axi_mem_BVALID,
m_axi_MAXI_BREADY => sig_m_axi_mem_BREADY,
m_axi_MAXI_BRESP => sig_m_axi_mem_BRESP,
m_axi_MAXI_BID => sig_m_axi_mem_BID,
m_axi_MAXI_BUSER => "0",
interrupt => sig_interrupt,
syscall_interrupt_o => sig_syscall_interrupt_o,
syscall_interrupt_i => '0'
);
s_axi_AXILiteS_AWREADY <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_AWREADY;
s_axi_AXILiteS_WREADY <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_WREADY ;
s_axi_AXILiteS_ARREADY <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_ARREADY;
s_axi_AXILiteS_RVALID <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_RVALID ;
s_axi_AXILiteS_RDATA <= (not (31 downto 0 => reg_hold_outputs)) and sig_s_axi_AXILiteS_RDATA;
s_axi_AXILiteS_RRESP <= (not (1 downto 0 => reg_hold_outputs)) and sig_s_axi_AXILiteS_RRESP;
s_axi_AXILiteS_BVALID <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_BVALID ;
s_axi_AXILiteS_BRESP <= (not (1 downto 0 => reg_hold_outputs)) and sig_s_axi_AXILiteS_BRESP;
m_axi_mem_AWVALID <= (not reg_hold_outputs) and sig_m_axi_mem_AWVALID ;
m_axi_mem_AWADDR <= (not (31 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWADDR ;
m_axi_mem_AWID <= (not (0 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWID ;
m_axi_mem_AWLEN <= (not (7 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWLEN ;
m_axi_mem_AWSIZE <= (not (2 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWSIZE ;
m_axi_mem_AWBURST <= (not (1 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWBURST ;
m_axi_mem_AWLOCK <= (not (1 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWLOCK ;
m_axi_mem_AWCACHE <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWCACHE ;
m_axi_mem_AWPROT <= (not (2 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWPROT ;
m_axi_mem_AWQOS <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWQOS ;
m_axi_mem_AWREGION <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWREGION;
m_axi_mem_WVALID <= (not reg_hold_outputs) and sig_m_axi_mem_WVALID ;
m_axi_mem_WDATA <= (not (31 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_WDATA;
m_axi_mem_WSTRB <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_WSTRB;
m_axi_mem_WLAST <= (not reg_hold_outputs) and sig_m_axi_mem_WLAST ;
m_axi_mem_WID <= (not (0 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_WID;
m_axi_mem_ARVALID <= (not reg_hold_outputs) and sig_m_axi_mem_ARVALID ;
m_axi_mem_ARADDR <= (not (31 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARADDR ;
m_axi_mem_ARID <= (not (0 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARID ;
m_axi_mem_ARLEN <= (not (7 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARLEN ;
m_axi_mem_ARSIZE <= (not (2 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARSIZE ;
m_axi_mem_ARBURST <= (not (1 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARBURST ;
m_axi_mem_ARLOCK <= (not (1 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARLOCK ;
m_axi_mem_ARCACHE <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARCACHE ;
m_axi_mem_ARPROT <= (not (2 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARPROT ;
m_axi_mem_ARQOS <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARQOS ;
m_axi_mem_ARREGION <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARREGION;
m_axi_mem_RREADY <= (not reg_hold_outputs) and sig_m_axi_mem_RREADY ;
m_axi_mem_BREADY <= (not reg_hold_outputs) and sig_m_axi_mem_BREADY ;
interrupt <= (not reg_hold_outputs) and sig_interrupt ;
sig_s_axi_AXILiteS_AWVALID <= s_axi_AXILiteS_AWVALID;
sig_s_axi_AXILiteS_AWADDR <= s_axi_AXILiteS_AWADDR ;
sig_s_axi_AXILiteS_WVALID <= s_axi_AXILiteS_WVALID ;
sig_s_axi_AXILiteS_WDATA <= s_axi_AXILiteS_WDATA ;
sig_s_axi_AXILiteS_WSTRB <= s_axi_AXILiteS_WSTRB ;
sig_s_axi_AXILiteS_ARVALID <= s_axi_AXILiteS_ARVALID;
sig_s_axi_AXILiteS_ARADDR <= s_axi_AXILiteS_ARADDR ;
sig_s_axi_AXILiteS_RREADY <= s_axi_AXILiteS_RREADY ;
sig_s_axi_AXILiteS_BREADY <= s_axi_AXILiteS_BREADY ;
sig_ap_clk <= ap_clk ;
sig_ap_rst_n <= (not reg_hold_outputs) and ap_rst_n; -- Also hold reset when isolated...
sig_m_axi_mem_AWREADY <= m_axi_mem_AWREADY ;
sig_m_axi_mem_WREADY <= m_axi_mem_WREADY ;
sig_m_axi_mem_ARREADY <= m_axi_mem_ARREADY ;
sig_m_axi_mem_RVALID <= m_axi_mem_RVALID ;
sig_m_axi_mem_RDATA <= m_axi_mem_RDATA ;
sig_m_axi_mem_RLAST <= m_axi_mem_RLAST ;
sig_m_axi_mem_RID <= m_axi_mem_RID ;
sig_m_axi_mem_RRESP <= m_axi_mem_RRESP ;
sig_m_axi_mem_BVALID <= m_axi_mem_BVALID ;
sig_m_axi_mem_BRESP <= m_axi_mem_BRESP ;
sig_m_axi_mem_BID <= m_axi_mem_BID ;
sig_dummy_user <= sig_m_axi_mem_AWUSER or sig_m_axi_mem_WUSER or sig_m_axi_mem_ARUSER;
jamaica_syscall <= (not reg_hold_outputs) and sig_syscall_interrupt_o;
end architecture rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:09 02/09/2013
-- Design Name:
-- Module Name: Top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TopRoland is
port (
-- Standard 6847 signals
--
-- expept DA which is now input only
-- except nRP which re-purposed as a nWR
DD : inout std_logic_vector (7 downto 0);
DA : in std_logic_vector (12 downto 0);
nMS : in std_logic;
CSS : in std_logic;
nFS : out std_logic;
nWR : in std_logic; -- Was nRP
AG : in std_logic;
GM : in std_logic_vector (2 downto 0);
-- 5 bit VGA Output
R : out std_logic_vector (0 downto 0);
G : out std_logic_vector (1 downto 0);
B : out std_logic_vector (0 downto 0);
HSYNC : out std_logic;
VSYNC : out std_logic;
-- 1 bit AUDIO Output
AUDIO : out std_logic;
-- Other GODIL specific pins
clock49 : in std_logic;
nRST : in std_logic;
nBXXX : in std_logic;
-- Jumpers
-- Enabled SID Audio
SIDEN : in std_logic;
-- Moves SID from 9FE0 to BDC0
nSIDD : in std_logic;
-- Active low version of the SID Select Signal for disabling the external bus buffers
-- nSIDSEL : out std_logic;
-- PS/2 Mouse
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic;
-- UART
uart_TxD : out std_logic;
uart_RxD : in std_logic
);
end TopRoland;
architecture BEHAVIORAL of TopRoland is
-- clock32 is the main clock
signal clock32 : std_logic;
-- clock25 is a full speed VGA clock
signal clock25 : std_logic;
-- clock15 is just used between two DCMs
signal clock15 : std_logic;
-- Reset signal (active high)
signal reset : std_logic;
-- Reset signal to 6847 (active high), not currently used
signal reset_vid : std_logic;
-- pipelined versions of the address/data/write signals
signal nWR1 : std_logic;
signal nWR2 : std_logic;
signal nMS1 : std_logic;
signal nMS2 : std_logic;
signal nWRMS1 : std_logic;
signal nWRMS2 : std_logic;
signal nBXXX1 : std_logic;
signal nBXXX2 : std_logic;
signal DA1 : std_logic_vector (12 downto 0);
signal DA2 : std_logic_vector (12 downto 0);
signal DD1 : std_logic_vector (7 downto 0);
signal DD2 : std_logic_vector (7 downto 0);
signal DD3 : std_logic_vector (7 downto 0);
signal ram_we : std_logic;
signal addr : std_logic_vector (12 downto 0);
signal din : std_logic_vector (7 downto 0);
-- Dout back to the Atom, that is either VRAM or SID
signal dout : std_logic_vector (7 downto 0);
-- SID sigmals
signal sid_cs : std_logic;
signal sid_we : std_logic;
signal sid_audio : std_logic;
-- UART sigmals
signal uart_cs : std_logic;
signal uart_we : std_logic;
-- Atom extension register signals
signal reg_cs : std_logic;
signal reg_we : std_logic;
signal final_red : std_logic;
signal final_green1 : std_logic;
signal final_green0 : std_logic;
signal final_blue : std_logic;
signal final_vsync : std_logic;
signal final_hsync : std_logic;
signal final_char_a : std_logic_vector (10 downto 0);
component DCM0
port(
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component DCMSID0
port(
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component DCMSID1
port(
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component AtomGodilVideo
generic (
CImplGraphicsExt : boolean;
CImplSoftChar : boolean;
CImplSID : boolean;
CImplVGA80x40 : boolean;
CImplHWScrolling : boolean;
CImplMouse : boolean;
CImplUart : boolean;
MainClockSpeed : integer;
DefaultBaud : integer
);
port (
-- clock_vga is a full speed VGA clock (25MHz ish)
clock_vga : in std_logic;
-- clock_main is the main clock
clock_main : in std_logic;
-- A fixed 32MHz clock for the SID
clock_sid_32MHz : in std_logic;
-- As fast a clock as possible for the SID DAC
clock_sid_dac : in std_logic;
-- Reset signal (active high)
reset : in std_logic;
-- Reset signal to 6847 (active high), not currently used
reset_vid : in std_logic;
-- Main Address / Data Bus
din : in std_logic_vector (7 downto 0);
dout : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (12 downto 0);
-- 6847 Control Signals
CSS : in std_logic;
AG : in std_logic;
GM : in std_logic_vector (2 downto 0);
nFS : out std_logic;
-- RAM signals
ram_we : in std_logic;
-- SID signals
reg_cs : in std_logic;
reg_we : in std_logic;
-- SID signals
sid_cs : in std_logic;
sid_we : in std_logic;
sid_audio : out std_logic;
-- PS/2 Mouse
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic;
-- UART signals
uart_cs : in std_logic;
uart_we : in std_logic;
uart_RxD : in std_logic;
uart_TxD : out std_logic;
uart_escape : out std_logic;
uart_break : out std_logic;
-- VGA Signals
final_red : out std_logic;
final_green1 : out std_logic;
final_green0 : out std_logic;
final_blue : out std_logic;
final_vsync : out std_logic;
final_hsync : out std_logic
);
end component;
begin
reset <= not nRST;
reset_vid <= '0';
-- Currently set at 49.152 * 8 / 31 = 12.684MHz
-- half VGA should be 25.175 / 2 = 12. 5875
-- we could get closer with to cascaded multipliers
Inst_DCM0 : DCM0
port map (
CLKIN_IN => clock49,
CLK0_OUT => clock25,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
Inst_DCMSID0 : DCMSID0
port map (
CLKIN_IN => clock49,
CLK0_OUT => clock15,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
Inst_DCMSID1 : DCMSID1
port map (
CLKIN_IN => clock15,
CLK0_OUT => clock32,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
Inst_AtomGodilVideo : AtomGodilVideo
generic map (
CImplGraphicsExt => true,
CImplSoftChar => true,
CImplSID => true,
CImplVGA80x40 => true,
CImplHWScrolling => true,
CImplMouse => true,
CImplUart => true,
MainClockSpeed => 32000000,
DefaultBaud => 115200
)
port map (
clock_vga => clock25,
clock_main => clock32,
clock_sid_32Mhz => clock32,
clock_sid_dac => clock49,
reset => reset,
reset_vid => reset_vid,
din => din,
dout => dout,
addr => addr,
CSS => CSS,
AG => AG,
GM => GM,
nFS => nFS,
ram_we => ram_we,
reg_cs => reg_cs,
reg_we => reg_we,
sid_cs => sid_cs,
sid_we => sid_we,
sid_audio => sid_audio,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
uart_cs => uart_cs,
uart_we => uart_we,
uart_RxD => uart_RxD,
uart_TxD => uart_TxD,
uart_escape => open,
uart_break => open,
final_red => final_red,
final_green1 => final_green1,
final_green0 => final_green0,
final_blue => final_blue,
final_vsync => final_vsync,
final_hsync => final_hsync
);
-- Pipelined version of address/data/write signals
process (clock32)
begin
if rising_edge(clock32) then
nBXXX2 <= nBXXX1;
nBXXX1 <= nBXXX;
nMS2 <= nMS1;
nMS1 <= nMS;
nWRMS2 <= nWRMS1;
nWRMS1 <= nWR or nMS;
nWR2 <= nWR1;
nWR1 <= nWR;
DD3 <= DD2;
DD2 <= DD1;
DD1 <= DD;
DA2 <= DA1;
DA1 <= DA;
end if;
end process;
-- Signals driving the VRAM
-- Write just before the rising edge of nWR
ram_we <= '1' when (nWRMS1 = '1' and nWRMS2 = '0' and nBXXX2 = '1') else '0';
din <= DD3;
addr <= DA2;
-- Signals driving the internal registers
-- When nSIDD=0 the registers are mapped to BDE0-BDFF
-- When nSIDD=1 the registers are mapped to 9FE0-9FFF
reg_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 5) = "11111111") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 5) = "1101111")
else '0';
reg_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
-- Signals driving the SID
-- When nSIDD=0 the SID is mapped to BDC0-BDDF
-- When nSIDD=1 the SID is mapped to 9FC0-9FDF
sid_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 5) = "11111110") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 5) = "1101110")
else '0';
sid_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
-- Signals driving the UART
-- When nSIDD=0 the UART is mapped to BDB0-BDBF
-- When nSIDD=1 the UART is mapped to 9FB0-9FBF
uart_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 4) = "111111011") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 4) = "11011011")
else '0';
uart_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
AUDIO <= sid_audio when SIDEN = '1' else '0';
-- Output the SID Select Signal so it can be used to disable the bus buffers
-- TODO: this looks incorrect
-- nSIDSEL <= not sid_cs;
-- Tri-state data back to the Atom
DD <= dout when (nMS = '0' and nWR = '1') else (others => 'Z');
-- 1/2/1 Bit RGB Video to GODIL Test Connector
R(0) <= final_red;
G(1) <= final_green1;
G(0) <= final_green0;
B(0) <= final_blue;
VSYNC <= final_vsync;
HSYNC <= final_hsync;
end BEHAVIORAL;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: McEliece_QD-Goppa_Decrypt_v4
-- Module Name: McEliece_QD-Goppa_Decrypt_v4
-- Project Name: McEliece Goppa Decryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit implements McEliece decryption algorithm for binary Goppa codes.
-- The circuit is divided into 3 phases : Syndrome computation, Solving Key Equation and
-- Finding Root.
-- Each circuits waits for the next one to begin computation. All circuits share some
-- input and output memories, therefore is not possible to make a pipeline of this 3 phases.
-- First circuit, polynomial_syndrome_computing_n_v2, computes the syndrome from the ciphertext
-- and private keys, support L and polynomial g(x) (In this case g(L)^-1).
-- Second circuit, solving_key_equation_5, computes polynomial sigma through
-- the syndrome computed by first circuit.
-- Third circuit, polynomial_syndrome_computing_n_v2, find the roots of polynomial sigma
-- and correct respective errors in the ciphertext and obtains plaintext array.
-- Inversion circuit, inv_gf_2_m_pipeline, is only used during solving_key_equation_5.
-- This circuit was made outside of solving_key_equation_5 so it can be used by other circuits.
--
-- The circuits parameters
--
-- number_of_polynomial_evaluator_syndrome_pipelines :
--
-- The number of pipelines in polynomial_syndrome_computing_n_v2 circuit.
-- This number can be 1 or greater.
--
-- polynomial_evaluator_syndrome_pipeline_size :
--
-- This is the number of stages on polynomial_syndrome_computing_n_v2 circuit.
-- This number can be 2 or greater.
--
-- polynomial_evaluator_syndrome_size_pipeline_size :
--
-- The number of bits necessary to hold the number of stages on the pipeline.
-- This is ceil(log2(polynomial_evaluator_syndrome_pipeline_size))
--
-- gf_2_m :
--
-- The size of the finite field extension used in this circuit.
-- This values depends of the Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword in this Goppa code.
-- This values depends of the Goppa code used.
--
-- size_codeword :
--
-- The number of bits necessary to store an array of codeword lengths.
-- This is ceil(log2(length_codeword))
--
-- number_of_errors :
--
-- The number of errors the Goppa code is able to decode.
-- This values depends of the Goppa code used.
--
-- size_number_of_errors :
--
-- The number of bits necessary to store an array of number of errors + 1 length.
-- This is ceil(log2(number_of_errors+1))
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- polynomial_syndrome_computing_n_v2 Rev 1.0
-- solving_key_equation_5 Rev 1.0
-- inv_gf_2_m_pipeline Rev 1.0
-- register_rst_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mceliece_qd_goppa_decrypt_v4 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 28;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 27;
-- size_number_of_errors : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
polynomial_evaluator_syndrome_pipeline_size : integer := 7;
polynomial_evaluator_syndrome_size_pipeline_size : integer := 3;
gf_2_m : integer range 1 to 20 := 13;
length_codeword : integer := 7296;
size_codeword : integer := 13;
number_of_errors : integer := 128;
size_number_of_errors : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
value_s : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_v : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma_evaluated : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC;
address_value_h : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_L : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_codeword : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_s : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_v : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_s : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_v : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_sigma : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_error : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_s : out STD_LOGIC;
write_enable_new_value_v : out STD_LOGIC;
write_enable_new_value_sigma : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_new_value_error : out STD_LOGIC;
write_enable_new_value_sigma_evaluated : out STD_LOGIC;
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_s : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_v : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_error : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0)
);
end mceliece_qd_goppa_decrypt_v4;
architecture Behavioral of mceliece_qd_goppa_decrypt_v4 is
component polynomial_syndrome_computing_n_v2
Generic (
number_of_pipelines : integer := 1;
pipeline_size : integer := 2;
size_pipeline_size : integer := 2;
gf_2_m : integer range 1 to 20 := 13;
number_of_errors : integer := 128;
size_number_of_errors : integer := 8;
number_of_support_elements: integer := 7296;
size_number_of_support_elements : integer := 13
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_h : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
computation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR(((gf_2_m) - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end component;
component solving_key_equation_5
Generic(
gf_2_m : integer range 1 to 20;
final_degree : integer;
size_final_degree : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_s : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_r : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_v : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_u : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_s : out STD_LOGIC;
write_enable_r : out STD_LOGIC;
write_enable_v : out STD_LOGIC;
write_enable_u : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_s : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_v : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_r : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_u : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_value_s : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_r : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_v : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_u : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_s : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_r : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_v : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_u : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end component;
component inv_gf_2_m_pipeline
Generic(gf_2_m : integer range 1 to 20 := 13);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
flag : in STD_LOGIC;
clk : in STD_LOGIC;
oflag : out STD_LOGIC;
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
signal polynomial_evaluator_syndrome_value_x : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_value_polynomial : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_syndrome_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal polynomial_evaluator_syndrome_value_h : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_mode_polynomial_syndrome : STD_LOGIC;
signal polynomial_evaluator_syndrome_rst : STD_LOGIC;
signal polynomial_evaluator_syndrome_computation_finalized : STD_LOGIC;
signal polynomial_evaluator_syndrome_address_value_polynomial : STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_x : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_message : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_message : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
signal polynomial_evaluator_syndrome_address_value_error : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_write_enable_new_value_acc : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_new_value_syndrome : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_new_value_message : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_value_error : STD_LOGIC;
signal polynomial_evaluator_syndrome_new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_syndrome_new_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_new_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal polynomial_evaluator_syndrome_value_error : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal syndrome_finalized : STD_LOGIC;
signal solving_key_equation_rst : STD_LOGIC;
signal solving_key_equation_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_key_equation_found : STD_LOGIC;
signal solving_key_equation_write_enable_F : STD_LOGIC;
signal solving_key_equation_write_enable_G : STD_LOGIC;
signal solving_key_equation_write_enable_B : STD_LOGIC;
signal solving_key_equation_write_enable_C : STD_LOGIC;
signal solving_key_equation_new_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_address_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal inv_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal inv_flag : STD_LOGIC;
signal inv_oflag : STD_LOGIC;
signal inv_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
begin
polynomial_evaluator_syndrome : polynomial_syndrome_computing_n_v2
Generic Map(
number_of_pipelines => number_of_polynomial_evaluator_syndrome_pipelines,
pipeline_size => polynomial_evaluator_syndrome_pipeline_size,
size_pipeline_size => polynomial_evaluator_syndrome_size_pipeline_size,
gf_2_m => gf_2_m,
number_of_errors => number_of_errors,
size_number_of_errors => size_number_of_errors,
number_of_support_elements => length_codeword,
size_number_of_support_elements => size_codeword
)
Port Map(
value_x => polynomial_evaluator_syndrome_value_x,
value_acc => polynomial_evaluator_syndrome_value_acc,
value_polynomial => polynomial_evaluator_syndrome_value_polynomial,
value_message => polynomial_evaluator_syndrome_value_message,
value_h => polynomial_evaluator_syndrome_value_h,
mode_polynomial_syndrome => polynomial_evaluator_syndrome_mode_polynomial_syndrome,
clk => clk,
rst => polynomial_evaluator_syndrome_rst,
computation_finalized => polynomial_evaluator_syndrome_computation_finalized,
address_value_polynomial => polynomial_evaluator_syndrome_address_value_polynomial,
address_value_x => polynomial_evaluator_syndrome_address_value_x,
address_value_acc => polynomial_evaluator_syndrome_address_value_acc,
address_value_message => polynomial_evaluator_syndrome_address_value_message,
address_new_value_message => polynomial_evaluator_syndrome_address_new_value_message,
address_new_value_acc => polynomial_evaluator_syndrome_address_new_value_acc,
address_new_value_syndrome => polynomial_evaluator_syndrome_address_new_value_syndrome,
address_value_error => polynomial_evaluator_syndrome_address_value_error,
write_enable_new_value_acc => polynomial_evaluator_syndrome_write_enable_new_value_acc,
write_enable_new_value_syndrome => polynomial_evaluator_syndrome_write_enable_new_value_syndrome,
write_enable_new_value_message => polynomial_evaluator_syndrome_write_enable_new_value_message,
write_enable_value_error => polynomial_evaluator_syndrome_write_enable_value_error,
new_value_syndrome => polynomial_evaluator_syndrome_new_value_syndrome,
new_value_acc => polynomial_evaluator_syndrome_new_value_acc,
new_value_message => polynomial_evaluator_syndrome_new_value_message,
value_error => polynomial_evaluator_syndrome_value_error
);
solving_key_equation : solving_key_equation_5
Generic Map(
gf_2_m => gf_2_m,
final_degree => number_of_errors,
size_final_degree => size_number_of_errors
)
Port Map(
clk => clk,
rst => solving_key_equation_rst,
ready_inv => inv_oflag,
value_s => solving_key_equation_value_F,
value_r => solving_key_equation_value_G,
value_v => solving_key_equation_value_B,
value_u => solving_key_equation_value_C,
value_inv => inv_o,
signal_inv => inv_flag,
key_equation_found => solving_key_equation_key_equation_found,
write_enable_s => solving_key_equation_write_enable_F,
write_enable_r => solving_key_equation_write_enable_G,
write_enable_v => solving_key_equation_write_enable_B,
write_enable_u => solving_key_equation_write_enable_C,
new_value_inv => inv_a,
new_value_s => solving_key_equation_new_value_F,
new_value_v => solving_key_equation_new_value_B,
new_value_r => solving_key_equation_new_value_G,
new_value_u => solving_key_equation_new_value_C,
address_value_s => solving_key_equation_address_value_F,
address_value_r => solving_key_equation_address_value_G,
address_value_v => solving_key_equation_address_value_B,
address_value_u => solving_key_equation_address_value_C,
address_new_value_s => solving_key_equation_address_new_value_F,
address_new_value_r => solving_key_equation_address_new_value_G,
address_new_value_v => solving_key_equation_address_new_value_B,
address_new_value_u => solving_key_equation_address_new_value_C
);
inverter : inv_gf_2_m_pipeline
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => inv_a,
flag => inv_flag,
clk => clk,
oflag => inv_oflag,
o => inv_o
);
reg_syndrome_finalized : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => "1",
clk => clk,
ce => polynomial_evaluator_syndrome_computation_finalized,
rst => rst,
rst_value => "0",
q(0) => syndrome_finalized
);
polynomial_evaluator_syndrome_value_x <= value_L;
polynomial_evaluator_syndrome_value_acc <= value_sigma_evaluated;
polynomial_evaluator_syndrome_value_polynomial <= value_sigma;
polynomial_evaluator_syndrome_value_message <= value_codeword;
polynomial_evaluator_syndrome_value_h <= value_h;
polynomial_evaluator_syndrome_mode_polynomial_syndrome <= not syndrome_finalized;
polynomial_evaluator_syndrome_rst <= ( (rst) or (syndrome_finalized and (not solving_key_equation_key_equation_found)));
solving_key_equation_rst <= not syndrome_finalized;
solving_key_equation_value_G <= value_syndrome;
solving_key_equation_value_F <= value_s;
solving_key_equation_value_B <= value_v;
solving_key_equation_value_C <= value_sigma;
syndrome_generation_finalized <= syndrome_finalized or polynomial_evaluator_syndrome_computation_finalized;
key_equation_finalized <= solving_key_equation_key_equation_found;
decryption_finalized <= polynomial_evaluator_syndrome_computation_finalized and solving_key_equation_key_equation_found;
address_value_h <= polynomial_evaluator_syndrome_address_value_acc;
address_value_L <= polynomial_evaluator_syndrome_address_value_x;
address_value_syndrome <= solving_key_equation_address_value_G when syndrome_finalized = '1' else
"0" & polynomial_evaluator_syndrome_address_new_value_syndrome;
address_value_codeword <= polynomial_evaluator_syndrome_address_value_message;
address_value_s <= solving_key_equation_address_value_F;
address_value_v <= solving_key_equation_address_value_B;
address_value_sigma <= "00" & polynomial_evaluator_syndrome_address_value_polynomial when solving_key_equation_key_equation_found = '1' else
solving_key_equation_address_value_C;
address_value_sigma_evaluated <= polynomial_evaluator_syndrome_address_value_acc;
new_value_syndrome <= solving_key_equation_new_value_G when syndrome_finalized = '1' else
polynomial_evaluator_syndrome_new_value_syndrome;
new_value_s <= solving_key_equation_new_value_F;
new_value_v <= solving_key_equation_new_value_B;
new_value_sigma <= solving_key_equation_new_value_C;
new_value_message <= polynomial_evaluator_syndrome_new_value_message;
new_value_error <= polynomial_evaluator_syndrome_value_error;
new_value_sigma_evaluated <= polynomial_evaluator_syndrome_new_value_acc;
write_enable_new_value_syndrome <= solving_key_equation_write_enable_G when syndrome_finalized = '1' else
polynomial_evaluator_syndrome_write_enable_new_value_syndrome;
write_enable_new_value_s <= solving_key_equation_write_enable_F;
write_enable_new_value_v <= solving_key_equation_write_enable_B;
write_enable_new_value_sigma <= solving_key_equation_write_enable_C;
write_enable_new_value_message <= polynomial_evaluator_syndrome_write_enable_new_value_message;
write_enable_new_value_error <= polynomial_evaluator_syndrome_write_enable_value_error;
write_enable_new_value_sigma_evaluated <= polynomial_evaluator_syndrome_write_enable_new_value_acc;
address_new_value_syndrome <= solving_key_equation_address_new_value_G when syndrome_finalized = '1' else
"0" & polynomial_evaluator_syndrome_address_new_value_syndrome;
address_new_value_s <= solving_key_equation_address_new_value_F;
address_new_value_v <= solving_key_equation_address_new_value_B;
address_new_value_sigma <= solving_key_equation_address_new_value_C;
address_new_value_message <= polynomial_evaluator_syndrome_address_new_value_message;
address_new_value_error <= polynomial_evaluator_syndrome_address_value_error;
address_new_value_sigma_evaluated <= polynomial_evaluator_syndrome_address_new_value_acc;
end Behavioral; |
-------------------------------------------------------------------------------
-- Title : I2C Bus Arbiter Start/Stop detector
-- Project : White Rabbit Project
-------------------------------------------------------------------------------
-- File : i2c_arbiter_ss_detector.vhd
-- Author : Miguel Jimenez Lopez
-- Company : UGR
-- Created : 2015-09-06
-- Last update: 2015-09-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- This component allows to detect the START and STOP condition in a I2C bus.
--
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2015 UGR
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity i2c_arbiter_ss_detector is
port (
-- Clock & Reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C input buses & ACK
input_sda_i : in std_logic;
input_scl_i : in std_logic;
start_ack_i : in std_logic;
stop_ack_i : in std_logic;
-- Start/Stop outputs
start_state_o : out std_logic;
stop_state_o : out std_logic
);
end i2c_arbiter_ss_detector;
architecture struct of i2c_arbiter_ss_detector is
-- Start FSM signals
type i2c_arb_start_st is (ARB_START_IDLE, ARB_START_WAIT_SDA, ARB_START_DETECTED);
signal arb_start_st : i2c_arb_start_st := ARB_START_IDLE;
-- Stop FSM signals
type i2c_arb_stop_st is (ARB_STOP_IDLE, ARB_STOP_WAIT_SDA, ARB_STOP_DETECTED);
signal arb_stop_st : i2c_arb_stop_st := ARB_STOP_IDLE;
begin
-- Start FSM
start_detector: process(clk_i,rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
arb_start_st <= ARB_START_IDLE;
start_state_o <= '0';
else
case arb_start_st is
when ARB_START_IDLE =>
start_state_o <= '0';
if input_sda_i = '1' and input_scl_i = '1' then
arb_start_st <= ARB_START_WAIT_SDA;
end if;
when ARB_START_WAIT_SDA =>
if input_scl_i = '1' then
if input_sda_i = '0' then
start_state_o <= '1';
arb_start_st <= ARB_START_DETECTED;
end if;
else
start_state_o <= '0';
arb_start_st <= ARB_START_IDLE;
end if;
when ARB_START_DETECTED =>
if start_ack_i = '1' then
start_state_o <= '0';
arb_start_st <= ARB_START_IDLE;
end if;
when others =>
start_state_o <= '0';
arb_start_st <= ARB_START_IDLE;
end case;
end if;
end if;
end process start_detector;
-- Stop FSM
stop_detector: process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
arb_stop_st <= ARB_STOP_IDLE;
stop_state_o <= '0';
else
case arb_stop_st is
when ARB_STOP_IDLE =>
stop_state_o <= '0';
if input_scl_i = '1' and input_sda_i = '0' then
arb_stop_st <= ARB_STOP_WAIT_SDA;
end if;
when ARB_STOP_WAIT_SDA =>
if input_scl_i = '1' then
if input_sda_i = '1' then
stop_state_o <= '1';
arb_stop_st <= ARB_STOP_DETECTED;
end if;
else
stop_state_o <= '0';
arb_stop_st <= ARB_STOP_IDLE;
end if;
when ARB_STOP_DETECTED =>
if stop_ack_i = '1' then
stop_state_o <= '0';
arb_stop_st <= ARB_STOP_IDLE;
end if;
when others =>
stop_state_o <= '0';
arb_stop_st <= ARB_STOP_IDLE;
end case;
end if;
end if;
end process stop_detector;
end struct;
|
------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ----
---- File name: rom_s.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SinglePortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
we_i : in std_logic;
re_i : in std_logic;
addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
write_i : in unsigned(WORD_SIZE-1 downto 0);
read_o : out unsigned(WORD_SIZE-1 downto 0);
busy_o : out std_logic);
end entity SinglePortRAM;
architecture Xilinx of SinglePortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram : ram_type :=
(
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc333.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p06n01i00333ent IS
END c03s02b01x00p06n01i00333ent;
ARCHITECTURE c03s02b01x00p06n01i00333arch OF c03s02b01x00p06n01i00333ent IS
type bit_vctor is array (1 to 8, 1 to 8) of integer;
BEGIN
TESTING: PROCESS
variable k :bit_vctor;
BEGIN
k(1,8) := 56;
assert NOT(k(1,8)=56)
report "***PASSED TEST: c03s02b01x00p06n01i00333"
severity NOTE;
assert (k(1,8)=56)
report "***FAILED TEST: c03s02b01x00p06n01i00333 - The index constraint is a list of discrete ranges enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p06n01i00333arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc333.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p06n01i00333ent IS
END c03s02b01x00p06n01i00333ent;
ARCHITECTURE c03s02b01x00p06n01i00333arch OF c03s02b01x00p06n01i00333ent IS
type bit_vctor is array (1 to 8, 1 to 8) of integer;
BEGIN
TESTING: PROCESS
variable k :bit_vctor;
BEGIN
k(1,8) := 56;
assert NOT(k(1,8)=56)
report "***PASSED TEST: c03s02b01x00p06n01i00333"
severity NOTE;
assert (k(1,8)=56)
report "***FAILED TEST: c03s02b01x00p06n01i00333 - The index constraint is a list of discrete ranges enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p06n01i00333arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc333.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p06n01i00333ent IS
END c03s02b01x00p06n01i00333ent;
ARCHITECTURE c03s02b01x00p06n01i00333arch OF c03s02b01x00p06n01i00333ent IS
type bit_vctor is array (1 to 8, 1 to 8) of integer;
BEGIN
TESTING: PROCESS
variable k :bit_vctor;
BEGIN
k(1,8) := 56;
assert NOT(k(1,8)=56)
report "***PASSED TEST: c03s02b01x00p06n01i00333"
severity NOTE;
assert (k(1,8)=56)
report "***FAILED TEST: c03s02b01x00p06n01i00333 - The index constraint is a list of discrete ranges enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p06n01i00333arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.Numeric_std.all;
entity Divider is
port (
Enable : in std_logic;
Ready : out std_logic;
CLK : in std_logic;
Overflow : out std_logic;
Divisor : in std_logic_vector(31 downto 0);
Dividend : in std_logic_vector(31 downto 0);
Remainder : out std_logic_vector(31 downto 0);
Quotient : out std_logic_vector(31 downto 0));
end Divider;
architecture Behavioral of Divider is
signal Enable_S : std_logic;
signal Ready_S : std_logic;
signal Overflow_S : std_logic;
signal Divisor_S : std_logic_vector(31 downto 0);
signal Quotient_S : std_logic_vector(31 downto 0);
signal Remainder_S : std_logic_vector(31 downto 0);
signal Dividend_S : std_logic_vector(31 downto 0);
begin
Enable_S <= Enable;
Ready <= Ready_S;
Overflow <= Overflow_S;
Divisor_S <= Divisor;
Quotient <= Quotient_S;
Remainder <= Remainder_S;
Dividend_S <= Dividend;
Divide: process (CLK)
begin -- process Divide
if rising_edge(CLK) then
if Enable_S = '1' then
if Divisor_S = "00000000000000000000000000000000" then
Ready_S <= '1';
Overflow_S <= '1';
Quotient_S <= (others => '0');
Remainder_S <= (others => '0');
else
Quotient_S <= std_logic_vector(unsigned(Dividend_S) / unsigned(Divisor_S));
Remainder_S <= std_logic_vector(unsigned(Dividend_S) rem unsigned(Divisor_S));
Ready_S <= '1';
Overflow_S <= '0';
end if;
else
Ready_S <= '0';
Overflow_S <= '0';
Quotient_S <= (others => '0');
Remainder_S <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
-- Btrace 448
-- Output Interface
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
entity outputInterface is
port(clk, rst: in std_logic;
get_pixel: out std_logic; -- Status signal
pixel_x, pixel_y: out std_logic_vector(9 downto 0); -- Address read signal
din: in std_logic_vector(11 downto 0); -- RGB in 1
overlay: in std_logic_vector(11 downto 0);-- RGB in 2
en_overlay: in std_logic;
hsync, vsync: out std_logic;
rgb: out std_logic_vector(11 downto 0));
end outputInterface;
architecture arch of outputInterface is
signal video_on, p_tick: std_logic;
signal s_rgb: std_logic_vector(11 downto 0);
begin
-- VGA sync generator
vga_sync_dev: entity work.vga_sync port map(clk, rst, hsync, vsync, video_on, p_tick, pixel_x, pixel_y);
-- Pixel buffer
process(clk, rst)
begin
if rst = '1' then
s_rgb <= (others => '0');
elsif rising_edge(clk) then
s_rgb <= din;
end if;
end process;
-- Concurrent signal assignment
get_pixel <= p_tick;
--rgb <= s_rgb when overlay else x"000";
rgb <= s_rgb when ((video_on = '1') and (en_overlay = '0')) else
overlay when ((video_on and en_overlay) = '1') else x"000";
end arch;
|
-- -------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 15.1
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from xlr8_float_mult2_0002
-- VHDL created on Tue Mar 29 15:09:51 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity xlr8_float_mult2_0002 is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
en : in std_logic_vector(0 downto 0); -- ufix1
q : out std_logic_vector(31 downto 0); -- float32_m23
clk : in std_logic;
areset : in std_logic
);
end xlr8_float_mult2_0002;
architecture normal of xlr8_float_mult2_0002 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal cstAllOWE_uid10_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstZeroWF_uid11_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal cstAllZWE_uid12_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal excZ_x_uid15_fpMulTest_a : STD_LOGIC_VECTOR (7 downto 0);
signal excZ_x_uid15_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal excZ_x_uid15_fpMulTest_q_i : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_x_uid15_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid16_fpMulTest_a : STD_LOGIC_VECTOR (7 downto 0);
signal expXIsMax_uid16_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expXIsMax_uid16_fpMulTest_q_i : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid16_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid17_fpMulTest_a : STD_LOGIC_VECTOR (22 downto 0);
signal fracXIsZero_uid17_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal fracXIsZero_uid17_fpMulTest_q_i : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid17_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_y_uid29_fpMulTest_a : STD_LOGIC_VECTOR (7 downto 0);
signal excZ_y_uid29_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal excZ_y_uid29_fpMulTest_q_i : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_y_uid29_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid30_fpMulTest_a : STD_LOGIC_VECTOR (7 downto 0);
signal expXIsMax_uid30_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expXIsMax_uid30_fpMulTest_q_i : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid30_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid31_fpMulTest_a : STD_LOGIC_VECTOR (22 downto 0);
signal fracXIsZero_uid31_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal fracXIsZero_uid31_fpMulTest_q_i : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid31_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expSum_uid44_fpMulTest_a : STD_LOGIC_VECTOR (8 downto 0);
signal expSum_uid44_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal expSum_uid44_fpMulTest_o : STD_LOGIC_VECTOR (8 downto 0);
signal expSum_uid44_fpMulTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal biasInc_uid45_fpMulTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal signR_uid48_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal signR_uid48_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signR_uid48_fpMulTest_q_i : STD_LOGIC_VECTOR (0 downto 0);
signal signR_uid48_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal roundBitDetectionConstant_uid63_fpMulTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal oneFracRPostExc2_uid92_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im0_a0 : STD_LOGIC_VECTOR (17 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im0_b0 : STD_LOGIC_VECTOR (17 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im0_s1 : STD_LOGIC_VECTOR (35 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im0_reset : std_logic;
signal prodXY_uid105_prod_uid47_fpMulTest_im0_q : STD_LOGIC_VECTOR (35 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im3_a0 : STD_LOGIC_VECTOR (17 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im3_b0 : STD_LOGIC_VECTOR (5 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im3_s1 : STD_LOGIC_VECTOR (23 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im3_reset : std_logic;
signal prodXY_uid105_prod_uid47_fpMulTest_im3_q : STD_LOGIC_VECTOR (23 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im6_a0 : STD_LOGIC_VECTOR (17 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im6_b0 : STD_LOGIC_VECTOR (5 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im6_s1 : STD_LOGIC_VECTOR (23 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im6_reset : std_logic;
signal prodXY_uid105_prod_uid47_fpMulTest_im6_q : STD_LOGIC_VECTOR (23 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im9_a0 : STD_LOGIC_VECTOR (5 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im9_b0 : STD_LOGIC_VECTOR (5 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im9_s1 : STD_LOGIC_VECTOR (11 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_im9_reset : std_logic;
signal prodXY_uid105_prod_uid47_fpMulTest_im9_q : STD_LOGIC_VECTOR (11 downto 0);
signal redist0_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist1_q : STD_LOGIC_VECTOR (8 downto 0);
signal redist2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist3_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist4_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist5_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist6_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist7_q : STD_LOGIC_VECTOR (0 downto 0);
signal expX_uid6_fpMulTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal expX_uid6_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal signX_uid8_fpMulTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal signX_uid8_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal frac_x_uid14_fpMulTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal frac_x_uid14_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal expY_uid7_fpMulTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal expY_uid7_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal signY_uid9_fpMulTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal signY_uid9_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal frac_y_uid28_fpMulTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal frac_y_uid28_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal fracXIsNotZero_uid18_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid18_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_x_uid19_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excI_x_uid19_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excI_x_uid19_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid20_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid20_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid20_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid21_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid21_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid22_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid22_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_x_uid23_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excR_x_uid23_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excR_x_uid23_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid32_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid32_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_y_uid33_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excI_y_uid33_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excI_y_uid33_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid34_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid34_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid34_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid35_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid35_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid36_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid36_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_y_uid37_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excR_y_uid37_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excR_y_uid37_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expSumMBias_uid46_fpMulTest_a : STD_LOGIC_VECTOR (11 downto 0);
signal expSumMBias_uid46_fpMulTest_b : STD_LOGIC_VECTOR (11 downto 0);
signal expSumMBias_uid46_fpMulTest_o : STD_LOGIC_VECTOR (11 downto 0);
signal expSumMBias_uid46_fpMulTest_q : STD_LOGIC_VECTOR (10 downto 0);
signal excXZAndExcYZ_uid76_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYZ_uid76_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYZ_uid76_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYR_uid77_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYR_uid77_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYR_uid77_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excYZAndExcXR_uid78_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excYZAndExcXR_uid78_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excYZAndExcXR_uid78_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXIAndExcYI_uid81_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excXIAndExcYI_uid81_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excXIAndExcYI_uid81_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXRAndExcYI_uid82_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excXRAndExcYI_uid82_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excXRAndExcYI_uid82_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excYRAndExcXI_uid83_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excYRAndExcXI_uid83_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excYRAndExcXI_uid83_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excYZAndExcXI_uid86_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excYZAndExcXI_uid86_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excYZAndExcXI_uid86_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYI_uid87_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYI_uid87_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYI_uid87_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal ZeroTimesInf_uid88_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal ZeroTimesInf_uid88_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal ZeroTimesInf_uid88_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN_uid89_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN_uid89_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN_uid89_fpMulTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN_uid89_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExcRNaN_uid101_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal invExcRNaN_uid101_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExc_uid102_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExc_uid102_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExc_uid102_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_join_12_q : STD_LOGIC_VECTOR (47 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_align_13_q : STD_LOGIC_VECTOR (41 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_align_13_q_int : STD_LOGIC_VECTOR (41 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_align_15_q : STD_LOGIC_VECTOR (41 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_align_15_q_int : STD_LOGIC_VECTOR (41 downto 0);
signal ofracX_uid40_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal ofracY_uid43_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_result_add_0_0_a : STD_LOGIC_VECTOR (48 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_result_add_0_0_b : STD_LOGIC_VECTOR (48 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_result_add_0_0_o : STD_LOGIC_VECTOR (48 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_result_add_0_0_q : STD_LOGIC_VECTOR (48 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_result_add_1_0_a : STD_LOGIC_VECTOR (49 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_result_add_1_0_b : STD_LOGIC_VECTOR (49 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_result_add_1_0_o : STD_LOGIC_VECTOR (49 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_result_add_1_0_q : STD_LOGIC_VECTOR (49 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_bs1_in : STD_LOGIC_VECTOR (17 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_bs1_b : STD_LOGIC_VECTOR (17 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_bs7_in : STD_LOGIC_VECTOR (23 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_bs7_b : STD_LOGIC_VECTOR (5 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_bs2_in : STD_LOGIC_VECTOR (17 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_bs2_b : STD_LOGIC_VECTOR (17 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_bs5_in : STD_LOGIC_VECTOR (23 downto 0);
signal prodXY_uid105_prod_uid47_fpMulTest_bs5_b : STD_LOGIC_VECTOR (5 downto 0);
signal osig_uid106_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (47 downto 0);
signal osig_uid106_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (47 downto 0);
signal normalizeBit_uid49_fpMulTest_in : STD_LOGIC_VECTOR (47 downto 0);
signal normalizeBit_uid49_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPostNormHigh_uid51_fpMulTest_in : STD_LOGIC_VECTOR (46 downto 0);
signal fracRPostNormHigh_uid51_fpMulTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPostNormLow_uid52_fpMulTest_in : STD_LOGIC_VECTOR (45 downto 0);
signal fracRPostNormLow_uid52_fpMulTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal stickyRange_uid54_fpMulTest_in : STD_LOGIC_VECTOR (21 downto 0);
signal stickyRange_uid54_fpMulTest_b : STD_LOGIC_VECTOR (21 downto 0);
signal extraStickyBitOfProd_uid55_fpMulTest_in : STD_LOGIC_VECTOR (22 downto 0);
signal extraStickyBitOfProd_uid55_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPostNorm_uid53_fpMulTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPostNorm_uid53_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal extraStickyBit_uid56_fpMulTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal extraStickyBit_uid56_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal stickyExtendedRange_uid57_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal fracRPostNorm1dto0_uid61_fpMulTest_in : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostNorm1dto0_uid61_fpMulTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal expFracPreRound_uid66_fpMulTest_q : STD_LOGIC_VECTOR (34 downto 0);
signal stickyRangeComparator_uid59_fpMulTest_a : STD_LOGIC_VECTOR (22 downto 0);
signal stickyRangeComparator_uid59_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal stickyRangeComparator_uid59_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sticky_uid60_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal sticky_uid60_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal lrs_uid62_fpMulTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal roundBitDetectionPattern_uid64_fpMulTest_a : STD_LOGIC_VECTOR (2 downto 0);
signal roundBitDetectionPattern_uid64_fpMulTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal roundBitDetectionPattern_uid64_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal roundBit_uid65_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal roundBit_uid65_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal roundBitAndNormalizationOp_uid68_fpMulTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal expFracRPostRounding_uid69_fpMulTest_a : STD_LOGIC_VECTOR (36 downto 0);
signal expFracRPostRounding_uid69_fpMulTest_b : STD_LOGIC_VECTOR (36 downto 0);
signal expFracRPostRounding_uid69_fpMulTest_o : STD_LOGIC_VECTOR (36 downto 0);
signal expFracRPostRounding_uid69_fpMulTest_q : STD_LOGIC_VECTOR (35 downto 0);
signal fracRPreExc_uid70_fpMulTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPreExc_uid70_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal expRPreExcExt_uid71_fpMulTest_in : STD_LOGIC_VECTOR (35 downto 0);
signal expRPreExcExt_uid71_fpMulTest_b : STD_LOGIC_VECTOR (11 downto 0);
signal expRPreExc_uid72_fpMulTest_in : STD_LOGIC_VECTOR (7 downto 0);
signal expRPreExc_uid72_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expUdf_uid73_fpMulTest_a : STD_LOGIC_VECTOR (14 downto 0);
signal expUdf_uid73_fpMulTest_b : STD_LOGIC_VECTOR (14 downto 0);
signal expUdf_uid73_fpMulTest_o : STD_LOGIC_VECTOR (14 downto 0);
signal expUdf_uid73_fpMulTest_cin : STD_LOGIC_VECTOR (0 downto 0);
signal expUdf_uid73_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal expOvf_uid75_fpMulTest_a : STD_LOGIC_VECTOR (14 downto 0);
signal expOvf_uid75_fpMulTest_b : STD_LOGIC_VECTOR (14 downto 0);
signal expOvf_uid75_fpMulTest_o : STD_LOGIC_VECTOR (14 downto 0);
signal expOvf_uid75_fpMulTest_cin : STD_LOGIC_VECTOR (0 downto 0);
signal expOvf_uid75_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal excZC3_uid79_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excZC3_uid79_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excZC3_uid79_fpMulTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal excZC3_uid79_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal ExcROvfAndInReg_uid84_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal ExcROvfAndInReg_uid84_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal ExcROvfAndInReg_uid84_fpMulTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal ExcROvfAndInReg_uid84_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRZero_uid80_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excRZero_uid80_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excRZero_uid80_fpMulTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal excRZero_uid80_fpMulTest_d : STD_LOGIC_VECTOR (0 downto 0);
signal excRZero_uid80_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInf_uid85_fpMulTest_a : STD_LOGIC_VECTOR (0 downto 0);
signal excRInf_uid85_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal excRInf_uid85_fpMulTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal excRInf_uid85_fpMulTest_d : STD_LOGIC_VECTOR (0 downto 0);
signal excRInf_uid85_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal concExc_uid90_fpMulTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal excREnc_uid91_fpMulTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostExc_uid95_fpMulTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostExc_uid95_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPostExc_uid100_fpMulTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal expRPostExc_uid100_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal R_uid103_fpMulTest_q : STD_LOGIC_VECTOR (31 downto 0);
begin
-- frac_x_uid14_fpMulTest(BITSELECT,13)@0
frac_x_uid14_fpMulTest_in <= a;
frac_x_uid14_fpMulTest_b <= frac_x_uid14_fpMulTest_in(22 downto 0);
-- cstZeroWF_uid11_fpMulTest(CONSTANT,10)
cstZeroWF_uid11_fpMulTest_q <= "00000000000000000000000";
-- fracXIsZero_uid17_fpMulTest(LOGICAL,16)@0
fracXIsZero_uid17_fpMulTest_a <= cstZeroWF_uid11_fpMulTest_q;
fracXIsZero_uid17_fpMulTest_b <= frac_x_uid14_fpMulTest_b;
fracXIsZero_uid17_fpMulTest_q_i <= "1" WHEN fracXIsZero_uid17_fpMulTest_a = fracXIsZero_uid17_fpMulTest_b ELSE "0";
fracXIsZero_uid17_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_q_i, xout => fracXIsZero_uid17_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
-- redist5(DELAY,131)
redist5 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_q, xout => redist5_q, ena => en(0), clk => clk, aclr => areset );
-- cstAllOWE_uid10_fpMulTest(CONSTANT,9)
cstAllOWE_uid10_fpMulTest_q <= "11111111";
-- expX_uid6_fpMulTest(BITSELECT,5)@0
expX_uid6_fpMulTest_in <= a;
expX_uid6_fpMulTest_b <= expX_uid6_fpMulTest_in(30 downto 23);
-- expXIsMax_uid16_fpMulTest(LOGICAL,15)@0
expXIsMax_uid16_fpMulTest_a <= expX_uid6_fpMulTest_b;
expXIsMax_uid16_fpMulTest_b <= cstAllOWE_uid10_fpMulTest_q;
expXIsMax_uid16_fpMulTest_q_i <= "1" WHEN expXIsMax_uid16_fpMulTest_a = expXIsMax_uid16_fpMulTest_b ELSE "0";
expXIsMax_uid16_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid16_fpMulTest_q_i, xout => expXIsMax_uid16_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
-- redist6(DELAY,132)
redist6 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid16_fpMulTest_q, xout => redist6_q, ena => en(0), clk => clk, aclr => areset );
-- excI_x_uid19_fpMulTest(LOGICAL,18)@2
excI_x_uid19_fpMulTest_a <= redist6_q;
excI_x_uid19_fpMulTest_b <= redist5_q;
excI_x_uid19_fpMulTest_q <= excI_x_uid19_fpMulTest_a and excI_x_uid19_fpMulTest_b;
-- cstAllZWE_uid12_fpMulTest(CONSTANT,11)
cstAllZWE_uid12_fpMulTest_q <= "00000000";
-- expY_uid7_fpMulTest(BITSELECT,6)@0
expY_uid7_fpMulTest_in <= b;
expY_uid7_fpMulTest_b <= expY_uid7_fpMulTest_in(30 downto 23);
-- excZ_y_uid29_fpMulTest(LOGICAL,28)@0
excZ_y_uid29_fpMulTest_a <= expY_uid7_fpMulTest_b;
excZ_y_uid29_fpMulTest_b <= cstAllZWE_uid12_fpMulTest_q;
excZ_y_uid29_fpMulTest_q_i <= "1" WHEN excZ_y_uid29_fpMulTest_a = excZ_y_uid29_fpMulTest_b ELSE "0";
excZ_y_uid29_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid29_fpMulTest_q_i, xout => excZ_y_uid29_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
-- redist4(DELAY,130)
redist4 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid29_fpMulTest_q, xout => redist4_q, ena => en(0), clk => clk, aclr => areset );
-- excYZAndExcXI_uid86_fpMulTest(LOGICAL,85)@2
excYZAndExcXI_uid86_fpMulTest_a <= redist4_q;
excYZAndExcXI_uid86_fpMulTest_b <= excI_x_uid19_fpMulTest_q;
excYZAndExcXI_uid86_fpMulTest_q <= excYZAndExcXI_uid86_fpMulTest_a and excYZAndExcXI_uid86_fpMulTest_b;
-- frac_y_uid28_fpMulTest(BITSELECT,27)@0
frac_y_uid28_fpMulTest_in <= b;
frac_y_uid28_fpMulTest_b <= frac_y_uid28_fpMulTest_in(22 downto 0);
-- fracXIsZero_uid31_fpMulTest(LOGICAL,30)@0
fracXIsZero_uid31_fpMulTest_a <= cstZeroWF_uid11_fpMulTest_q;
fracXIsZero_uid31_fpMulTest_b <= frac_y_uid28_fpMulTest_b;
fracXIsZero_uid31_fpMulTest_q_i <= "1" WHEN fracXIsZero_uid31_fpMulTest_a = fracXIsZero_uid31_fpMulTest_b ELSE "0";
fracXIsZero_uid31_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_q_i, xout => fracXIsZero_uid31_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
-- redist2(DELAY,128)
redist2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_q, xout => redist2_q, ena => en(0), clk => clk, aclr => areset );
-- expXIsMax_uid30_fpMulTest(LOGICAL,29)@0
expXIsMax_uid30_fpMulTest_a <= expY_uid7_fpMulTest_b;
expXIsMax_uid30_fpMulTest_b <= cstAllOWE_uid10_fpMulTest_q;
expXIsMax_uid30_fpMulTest_q_i <= "1" WHEN expXIsMax_uid30_fpMulTest_a = expXIsMax_uid30_fpMulTest_b ELSE "0";
expXIsMax_uid30_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid30_fpMulTest_q_i, xout => expXIsMax_uid30_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
-- redist3(DELAY,129)
redist3 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid30_fpMulTest_q, xout => redist3_q, ena => en(0), clk => clk, aclr => areset );
-- excI_y_uid33_fpMulTest(LOGICAL,32)@2
excI_y_uid33_fpMulTest_a <= redist3_q;
excI_y_uid33_fpMulTest_b <= redist2_q;
excI_y_uid33_fpMulTest_q <= excI_y_uid33_fpMulTest_a and excI_y_uid33_fpMulTest_b;
-- excZ_x_uid15_fpMulTest(LOGICAL,14)@0
excZ_x_uid15_fpMulTest_a <= expX_uid6_fpMulTest_b;
excZ_x_uid15_fpMulTest_b <= cstAllZWE_uid12_fpMulTest_q;
excZ_x_uid15_fpMulTest_q_i <= "1" WHEN excZ_x_uid15_fpMulTest_a = excZ_x_uid15_fpMulTest_b ELSE "0";
excZ_x_uid15_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid15_fpMulTest_q_i, xout => excZ_x_uid15_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
-- redist7(DELAY,133)
redist7 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid15_fpMulTest_q, xout => redist7_q, ena => en(0), clk => clk, aclr => areset );
-- excXZAndExcYI_uid87_fpMulTest(LOGICAL,86)@2
excXZAndExcYI_uid87_fpMulTest_a <= redist7_q;
excXZAndExcYI_uid87_fpMulTest_b <= excI_y_uid33_fpMulTest_q;
excXZAndExcYI_uid87_fpMulTest_q <= excXZAndExcYI_uid87_fpMulTest_a and excXZAndExcYI_uid87_fpMulTest_b;
-- ZeroTimesInf_uid88_fpMulTest(LOGICAL,87)@2
ZeroTimesInf_uid88_fpMulTest_a <= excXZAndExcYI_uid87_fpMulTest_q;
ZeroTimesInf_uid88_fpMulTest_b <= excYZAndExcXI_uid86_fpMulTest_q;
ZeroTimesInf_uid88_fpMulTest_q <= ZeroTimesInf_uid88_fpMulTest_a or ZeroTimesInf_uid88_fpMulTest_b;
-- fracXIsNotZero_uid32_fpMulTest(LOGICAL,31)@2
fracXIsNotZero_uid32_fpMulTest_a <= redist2_q;
fracXIsNotZero_uid32_fpMulTest_q <= not (fracXIsNotZero_uid32_fpMulTest_a);
-- excN_y_uid34_fpMulTest(LOGICAL,33)@2
excN_y_uid34_fpMulTest_a <= redist3_q;
excN_y_uid34_fpMulTest_b <= fracXIsNotZero_uid32_fpMulTest_q;
excN_y_uid34_fpMulTest_q <= excN_y_uid34_fpMulTest_a and excN_y_uid34_fpMulTest_b;
-- fracXIsNotZero_uid18_fpMulTest(LOGICAL,17)@2
fracXIsNotZero_uid18_fpMulTest_a <= redist5_q;
fracXIsNotZero_uid18_fpMulTest_q <= not (fracXIsNotZero_uid18_fpMulTest_a);
-- excN_x_uid20_fpMulTest(LOGICAL,19)@2
excN_x_uid20_fpMulTest_a <= redist6_q;
excN_x_uid20_fpMulTest_b <= fracXIsNotZero_uid18_fpMulTest_q;
excN_x_uid20_fpMulTest_q <= excN_x_uid20_fpMulTest_a and excN_x_uid20_fpMulTest_b;
-- excRNaN_uid89_fpMulTest(LOGICAL,88)@2
excRNaN_uid89_fpMulTest_a <= excN_x_uid20_fpMulTest_q;
excRNaN_uid89_fpMulTest_b <= excN_y_uid34_fpMulTest_q;
excRNaN_uid89_fpMulTest_c <= ZeroTimesInf_uid88_fpMulTest_q;
excRNaN_uid89_fpMulTest_q <= excRNaN_uid89_fpMulTest_a or excRNaN_uid89_fpMulTest_b or excRNaN_uid89_fpMulTest_c;
-- invExcRNaN_uid101_fpMulTest(LOGICAL,100)@2
invExcRNaN_uid101_fpMulTest_a <= excRNaN_uid89_fpMulTest_q;
invExcRNaN_uid101_fpMulTest_q <= not (invExcRNaN_uid101_fpMulTest_a);
-- signY_uid9_fpMulTest(BITSELECT,8)@0
signY_uid9_fpMulTest_in <= STD_LOGIC_VECTOR(b);
signY_uid9_fpMulTest_b <= signY_uid9_fpMulTest_in(31 downto 31);
-- signX_uid8_fpMulTest(BITSELECT,7)@0
signX_uid8_fpMulTest_in <= STD_LOGIC_VECTOR(a);
signX_uid8_fpMulTest_b <= signX_uid8_fpMulTest_in(31 downto 31);
-- signR_uid48_fpMulTest(LOGICAL,47)@0
signR_uid48_fpMulTest_a <= signX_uid8_fpMulTest_b;
signR_uid48_fpMulTest_b <= signY_uid9_fpMulTest_b;
signR_uid48_fpMulTest_q_i <= signR_uid48_fpMulTest_a xor signR_uid48_fpMulTest_b;
signR_uid48_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid48_fpMulTest_q_i, xout => signR_uid48_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
-- redist0(DELAY,126)
redist0 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid48_fpMulTest_q, xout => redist0_q, ena => en(0), clk => clk, aclr => areset );
-- xIn(GPIN,3)@0
-- signRPostExc_uid102_fpMulTest(LOGICAL,101)@2
signRPostExc_uid102_fpMulTest_a <= redist0_q;
signRPostExc_uid102_fpMulTest_b <= invExcRNaN_uid101_fpMulTest_q;
signRPostExc_uid102_fpMulTest_q <= signRPostExc_uid102_fpMulTest_a and signRPostExc_uid102_fpMulTest_b;
-- GND(CONSTANT,0)
GND_q <= "0";
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- ofracX_uid40_fpMulTest(BITJOIN,39)@0
ofracX_uid40_fpMulTest_q <= VCC_q & frac_x_uid14_fpMulTest_b;
-- prodXY_uid105_prod_uid47_fpMulTest_bs7(BITSELECT,114)@0
prodXY_uid105_prod_uid47_fpMulTest_bs7_in <= ofracX_uid40_fpMulTest_q;
prodXY_uid105_prod_uid47_fpMulTest_bs7_b <= prodXY_uid105_prod_uid47_fpMulTest_bs7_in(23 downto 18);
-- ofracY_uid43_fpMulTest(BITJOIN,42)@0
ofracY_uid43_fpMulTest_q <= VCC_q & frac_y_uid28_fpMulTest_b;
-- prodXY_uid105_prod_uid47_fpMulTest_bs2(BITSELECT,109)@0
prodXY_uid105_prod_uid47_fpMulTest_bs2_in <= ofracY_uid43_fpMulTest_q(17 downto 0);
prodXY_uid105_prod_uid47_fpMulTest_bs2_b <= prodXY_uid105_prod_uid47_fpMulTest_bs2_in(17 downto 0);
-- prodXY_uid105_prod_uid47_fpMulTest_im6(MULT,113)@0
prodXY_uid105_prod_uid47_fpMulTest_im6_a0 <= prodXY_uid105_prod_uid47_fpMulTest_bs2_b;
prodXY_uid105_prod_uid47_fpMulTest_im6_b0 <= prodXY_uid105_prod_uid47_fpMulTest_bs7_b;
prodXY_uid105_prod_uid47_fpMulTest_im6_reset <= areset;
prodXY_uid105_prod_uid47_fpMulTest_im6_component : lpm_mult
GENERIC MAP (
lpm_widtha => 18,
lpm_widthb => 6,
lpm_widthp => 24,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => prodXY_uid105_prod_uid47_fpMulTest_im6_a0,
datab => prodXY_uid105_prod_uid47_fpMulTest_im6_b0,
clken => en(0),
aclr => prodXY_uid105_prod_uid47_fpMulTest_im6_reset,
clock => clk,
result => prodXY_uid105_prod_uid47_fpMulTest_im6_s1
);
prodXY_uid105_prod_uid47_fpMulTest_im6_q <= prodXY_uid105_prod_uid47_fpMulTest_im6_s1;
-- prodXY_uid105_prod_uid47_fpMulTest_align_15(BITSHIFT,122)@2
prodXY_uid105_prod_uid47_fpMulTest_align_15_q_int <= prodXY_uid105_prod_uid47_fpMulTest_im6_q & "000000000000000000";
prodXY_uid105_prod_uid47_fpMulTest_align_15_q <= prodXY_uid105_prod_uid47_fpMulTest_align_15_q_int(41 downto 0);
-- prodXY_uid105_prod_uid47_fpMulTest_bs5(BITSELECT,112)@0
prodXY_uid105_prod_uid47_fpMulTest_bs5_in <= ofracY_uid43_fpMulTest_q;
prodXY_uid105_prod_uid47_fpMulTest_bs5_b <= prodXY_uid105_prod_uid47_fpMulTest_bs5_in(23 downto 18);
-- prodXY_uid105_prod_uid47_fpMulTest_bs1(BITSELECT,108)@0
prodXY_uid105_prod_uid47_fpMulTest_bs1_in <= ofracX_uid40_fpMulTest_q(17 downto 0);
prodXY_uid105_prod_uid47_fpMulTest_bs1_b <= prodXY_uid105_prod_uid47_fpMulTest_bs1_in(17 downto 0);
-- prodXY_uid105_prod_uid47_fpMulTest_im3(MULT,110)@0
prodXY_uid105_prod_uid47_fpMulTest_im3_a0 <= prodXY_uid105_prod_uid47_fpMulTest_bs1_b;
prodXY_uid105_prod_uid47_fpMulTest_im3_b0 <= prodXY_uid105_prod_uid47_fpMulTest_bs5_b;
prodXY_uid105_prod_uid47_fpMulTest_im3_reset <= areset;
prodXY_uid105_prod_uid47_fpMulTest_im3_component : lpm_mult
GENERIC MAP (
lpm_widtha => 18,
lpm_widthb => 6,
lpm_widthp => 24,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => prodXY_uid105_prod_uid47_fpMulTest_im3_a0,
datab => prodXY_uid105_prod_uid47_fpMulTest_im3_b0,
clken => en(0),
aclr => prodXY_uid105_prod_uid47_fpMulTest_im3_reset,
clock => clk,
result => prodXY_uid105_prod_uid47_fpMulTest_im3_s1
);
prodXY_uid105_prod_uid47_fpMulTest_im3_q <= prodXY_uid105_prod_uid47_fpMulTest_im3_s1;
-- prodXY_uid105_prod_uid47_fpMulTest_align_13(BITSHIFT,120)@2
prodXY_uid105_prod_uid47_fpMulTest_align_13_q_int <= prodXY_uid105_prod_uid47_fpMulTest_im3_q & "000000000000000000";
prodXY_uid105_prod_uid47_fpMulTest_align_13_q <= prodXY_uid105_prod_uid47_fpMulTest_align_13_q_int(41 downto 0);
-- prodXY_uid105_prod_uid47_fpMulTest_im9(MULT,116)@0
prodXY_uid105_prod_uid47_fpMulTest_im9_a0 <= prodXY_uid105_prod_uid47_fpMulTest_bs7_b;
prodXY_uid105_prod_uid47_fpMulTest_im9_b0 <= prodXY_uid105_prod_uid47_fpMulTest_bs5_b;
prodXY_uid105_prod_uid47_fpMulTest_im9_reset <= areset;
prodXY_uid105_prod_uid47_fpMulTest_im9_component : lpm_mult
GENERIC MAP (
lpm_widtha => 6,
lpm_widthb => 6,
lpm_widthp => 12,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => prodXY_uid105_prod_uid47_fpMulTest_im9_a0,
datab => prodXY_uid105_prod_uid47_fpMulTest_im9_b0,
clken => en(0),
aclr => prodXY_uid105_prod_uid47_fpMulTest_im9_reset,
clock => clk,
result => prodXY_uid105_prod_uid47_fpMulTest_im9_s1
);
prodXY_uid105_prod_uid47_fpMulTest_im9_q <= prodXY_uid105_prod_uid47_fpMulTest_im9_s1;
-- prodXY_uid105_prod_uid47_fpMulTest_im0(MULT,107)@0
prodXY_uid105_prod_uid47_fpMulTest_im0_a0 <= prodXY_uid105_prod_uid47_fpMulTest_bs1_b;
prodXY_uid105_prod_uid47_fpMulTest_im0_b0 <= prodXY_uid105_prod_uid47_fpMulTest_bs2_b;
prodXY_uid105_prod_uid47_fpMulTest_im0_reset <= areset;
prodXY_uid105_prod_uid47_fpMulTest_im0_component : lpm_mult
GENERIC MAP (
lpm_widtha => 18,
lpm_widthb => 18,
lpm_widthp => 36,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => prodXY_uid105_prod_uid47_fpMulTest_im0_a0,
datab => prodXY_uid105_prod_uid47_fpMulTest_im0_b0,
clken => en(0),
aclr => prodXY_uid105_prod_uid47_fpMulTest_im0_reset,
clock => clk,
result => prodXY_uid105_prod_uid47_fpMulTest_im0_s1
);
prodXY_uid105_prod_uid47_fpMulTest_im0_q <= prodXY_uid105_prod_uid47_fpMulTest_im0_s1;
-- prodXY_uid105_prod_uid47_fpMulTest_join_12(BITJOIN,119)@2
prodXY_uid105_prod_uid47_fpMulTest_join_12_q <= prodXY_uid105_prod_uid47_fpMulTest_im9_q & prodXY_uid105_prod_uid47_fpMulTest_im0_q;
-- prodXY_uid105_prod_uid47_fpMulTest_result_add_0_0(ADD,124)@2
prodXY_uid105_prod_uid47_fpMulTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0" & prodXY_uid105_prod_uid47_fpMulTest_join_12_q);
prodXY_uid105_prod_uid47_fpMulTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0000000" & prodXY_uid105_prod_uid47_fpMulTest_align_13_q);
prodXY_uid105_prod_uid47_fpMulTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prodXY_uid105_prod_uid47_fpMulTest_result_add_0_0_a) + UNSIGNED(prodXY_uid105_prod_uid47_fpMulTest_result_add_0_0_b));
prodXY_uid105_prod_uid47_fpMulTest_result_add_0_0_q <= prodXY_uid105_prod_uid47_fpMulTest_result_add_0_0_o(48 downto 0);
-- prodXY_uid105_prod_uid47_fpMulTest_result_add_1_0(ADD,125)@2
prodXY_uid105_prod_uid47_fpMulTest_result_add_1_0_a <= STD_LOGIC_VECTOR("0" & prodXY_uid105_prod_uid47_fpMulTest_result_add_0_0_q);
prodXY_uid105_prod_uid47_fpMulTest_result_add_1_0_b <= STD_LOGIC_VECTOR("00000000" & prodXY_uid105_prod_uid47_fpMulTest_align_15_q);
prodXY_uid105_prod_uid47_fpMulTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prodXY_uid105_prod_uid47_fpMulTest_result_add_1_0_a) + UNSIGNED(prodXY_uid105_prod_uid47_fpMulTest_result_add_1_0_b));
prodXY_uid105_prod_uid47_fpMulTest_result_add_1_0_q <= prodXY_uid105_prod_uid47_fpMulTest_result_add_1_0_o(49 downto 0);
-- osig_uid106_prod_uid47_fpMulTest(BITSELECT,105)@2
osig_uid106_prod_uid47_fpMulTest_in <= prodXY_uid105_prod_uid47_fpMulTest_result_add_1_0_q(47 downto 0);
osig_uid106_prod_uid47_fpMulTest_b <= osig_uid106_prod_uid47_fpMulTest_in(47 downto 0);
-- normalizeBit_uid49_fpMulTest(BITSELECT,48)@2
normalizeBit_uid49_fpMulTest_in <= STD_LOGIC_VECTOR(osig_uid106_prod_uid47_fpMulTest_b);
normalizeBit_uid49_fpMulTest_b <= normalizeBit_uid49_fpMulTest_in(47 downto 47);
-- roundBitDetectionConstant_uid63_fpMulTest(CONSTANT,62)
roundBitDetectionConstant_uid63_fpMulTest_q <= "010";
-- fracRPostNormHigh_uid51_fpMulTest(BITSELECT,50)@2
fracRPostNormHigh_uid51_fpMulTest_in <= osig_uid106_prod_uid47_fpMulTest_b(46 downto 0);
fracRPostNormHigh_uid51_fpMulTest_b <= fracRPostNormHigh_uid51_fpMulTest_in(46 downto 23);
-- fracRPostNormLow_uid52_fpMulTest(BITSELECT,51)@2
fracRPostNormLow_uid52_fpMulTest_in <= osig_uid106_prod_uid47_fpMulTest_b(45 downto 0);
fracRPostNormLow_uid52_fpMulTest_b <= fracRPostNormLow_uid52_fpMulTest_in(45 downto 22);
-- fracRPostNorm_uid53_fpMulTest(MUX,52)@2
fracRPostNorm_uid53_fpMulTest_s <= normalizeBit_uid49_fpMulTest_b;
fracRPostNorm_uid53_fpMulTest: PROCESS (fracRPostNorm_uid53_fpMulTest_s, en, fracRPostNormLow_uid52_fpMulTest_b, fracRPostNormHigh_uid51_fpMulTest_b)
BEGIN
CASE (fracRPostNorm_uid53_fpMulTest_s) IS
WHEN "0" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormLow_uid52_fpMulTest_b;
WHEN "1" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormHigh_uid51_fpMulTest_b;
WHEN OTHERS => fracRPostNorm_uid53_fpMulTest_q <= (others => '0');
END CASE;
END PROCESS;
-- fracRPostNorm1dto0_uid61_fpMulTest(BITSELECT,60)@2
fracRPostNorm1dto0_uid61_fpMulTest_in <= fracRPostNorm_uid53_fpMulTest_q(1 downto 0);
fracRPostNorm1dto0_uid61_fpMulTest_b <= fracRPostNorm1dto0_uid61_fpMulTest_in(1 downto 0);
-- extraStickyBitOfProd_uid55_fpMulTest(BITSELECT,54)@2
extraStickyBitOfProd_uid55_fpMulTest_in <= STD_LOGIC_VECTOR(osig_uid106_prod_uid47_fpMulTest_b(22 downto 0));
extraStickyBitOfProd_uid55_fpMulTest_b <= extraStickyBitOfProd_uid55_fpMulTest_in(22 downto 22);
-- extraStickyBit_uid56_fpMulTest(MUX,55)@2
extraStickyBit_uid56_fpMulTest_s <= normalizeBit_uid49_fpMulTest_b;
extraStickyBit_uid56_fpMulTest: PROCESS (extraStickyBit_uid56_fpMulTest_s, en, GND_q, extraStickyBitOfProd_uid55_fpMulTest_b)
BEGIN
CASE (extraStickyBit_uid56_fpMulTest_s) IS
WHEN "0" => extraStickyBit_uid56_fpMulTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid56_fpMulTest_q <= extraStickyBitOfProd_uid55_fpMulTest_b;
WHEN OTHERS => extraStickyBit_uid56_fpMulTest_q <= (others => '0');
END CASE;
END PROCESS;
-- stickyRange_uid54_fpMulTest(BITSELECT,53)@2
stickyRange_uid54_fpMulTest_in <= osig_uid106_prod_uid47_fpMulTest_b(21 downto 0);
stickyRange_uid54_fpMulTest_b <= stickyRange_uid54_fpMulTest_in(21 downto 0);
-- stickyExtendedRange_uid57_fpMulTest(BITJOIN,56)@2
stickyExtendedRange_uid57_fpMulTest_q <= extraStickyBit_uid56_fpMulTest_q & stickyRange_uid54_fpMulTest_b;
-- stickyRangeComparator_uid59_fpMulTest(LOGICAL,58)@2
stickyRangeComparator_uid59_fpMulTest_a <= stickyExtendedRange_uid57_fpMulTest_q;
stickyRangeComparator_uid59_fpMulTest_b <= cstZeroWF_uid11_fpMulTest_q;
stickyRangeComparator_uid59_fpMulTest_q <= "1" WHEN stickyRangeComparator_uid59_fpMulTest_a = stickyRangeComparator_uid59_fpMulTest_b ELSE "0";
-- sticky_uid60_fpMulTest(LOGICAL,59)@2
sticky_uid60_fpMulTest_a <= stickyRangeComparator_uid59_fpMulTest_q;
sticky_uid60_fpMulTest_q <= not (sticky_uid60_fpMulTest_a);
-- lrs_uid62_fpMulTest(BITJOIN,61)@2
lrs_uid62_fpMulTest_q <= fracRPostNorm1dto0_uid61_fpMulTest_b & sticky_uid60_fpMulTest_q;
-- roundBitDetectionPattern_uid64_fpMulTest(LOGICAL,63)@2
roundBitDetectionPattern_uid64_fpMulTest_a <= lrs_uid62_fpMulTest_q;
roundBitDetectionPattern_uid64_fpMulTest_b <= roundBitDetectionConstant_uid63_fpMulTest_q;
roundBitDetectionPattern_uid64_fpMulTest_q <= "1" WHEN roundBitDetectionPattern_uid64_fpMulTest_a = roundBitDetectionPattern_uid64_fpMulTest_b ELSE "0";
-- roundBit_uid65_fpMulTest(LOGICAL,64)@2
roundBit_uid65_fpMulTest_a <= roundBitDetectionPattern_uid64_fpMulTest_q;
roundBit_uid65_fpMulTest_q <= not (roundBit_uid65_fpMulTest_a);
-- roundBitAndNormalizationOp_uid68_fpMulTest(BITJOIN,67)@2
roundBitAndNormalizationOp_uid68_fpMulTest_q <= GND_q & normalizeBit_uid49_fpMulTest_b & cstZeroWF_uid11_fpMulTest_q & roundBit_uid65_fpMulTest_q;
-- biasInc_uid45_fpMulTest(CONSTANT,44)
biasInc_uid45_fpMulTest_q <= "0001111111";
-- expSum_uid44_fpMulTest(ADD,43)@0
expSum_uid44_fpMulTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpMulTest_b);
expSum_uid44_fpMulTest_b <= STD_LOGIC_VECTOR("0" & expY_uid7_fpMulTest_b);
expSum_uid44_fpMulTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid44_fpMulTest_o <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid44_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid44_fpMulTest_a) + UNSIGNED(expSum_uid44_fpMulTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid44_fpMulTest_q <= expSum_uid44_fpMulTest_o(8 downto 0);
-- redist1(DELAY,127)
redist1 : dspba_delay
GENERIC MAP ( width => 9, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expSum_uid44_fpMulTest_q, xout => redist1_q, ena => en(0), clk => clk, aclr => areset );
-- expSumMBias_uid46_fpMulTest(SUB,45)@2
expSumMBias_uid46_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00" & redist1_q));
expSumMBias_uid46_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid45_fpMulTest_q(9)) & biasInc_uid45_fpMulTest_q));
expSumMBias_uid46_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid46_fpMulTest_a) - SIGNED(expSumMBias_uid46_fpMulTest_b));
expSumMBias_uid46_fpMulTest_q <= expSumMBias_uid46_fpMulTest_o(10 downto 0);
-- expFracPreRound_uid66_fpMulTest(BITJOIN,65)@2
expFracPreRound_uid66_fpMulTest_q <= expSumMBias_uid46_fpMulTest_q & fracRPostNorm_uid53_fpMulTest_q;
-- expFracRPostRounding_uid69_fpMulTest(ADD,68)@2
expFracRPostRounding_uid69_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((36 downto 35 => expFracPreRound_uid66_fpMulTest_q(34)) & expFracPreRound_uid66_fpMulTest_q));
expFracRPostRounding_uid69_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "0000000000" & roundBitAndNormalizationOp_uid68_fpMulTest_q));
expFracRPostRounding_uid69_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid69_fpMulTest_a) + SIGNED(expFracRPostRounding_uid69_fpMulTest_b));
expFracRPostRounding_uid69_fpMulTest_q <= expFracRPostRounding_uid69_fpMulTest_o(35 downto 0);
-- expRPreExcExt_uid71_fpMulTest(BITSELECT,70)@2
expRPreExcExt_uid71_fpMulTest_in <= STD_LOGIC_VECTOR(expFracRPostRounding_uid69_fpMulTest_q);
expRPreExcExt_uid71_fpMulTest_b <= expRPreExcExt_uid71_fpMulTest_in(35 downto 24);
-- expRPreExc_uid72_fpMulTest(BITSELECT,71)@2
expRPreExc_uid72_fpMulTest_in <= expRPreExcExt_uid71_fpMulTest_b(7 downto 0);
expRPreExc_uid72_fpMulTest_b <= expRPreExc_uid72_fpMulTest_in(7 downto 0);
-- expOvf_uid75_fpMulTest(COMPARE,74)@2
expOvf_uid75_fpMulTest_cin <= GND_q;
expOvf_uid75_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 12 => expRPreExcExt_uid71_fpMulTest_b(11)) & expRPreExcExt_uid71_fpMulTest_b) & '0');
expOvf_uid75_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00000" & cstAllOWE_uid10_fpMulTest_q) & expOvf_uid75_fpMulTest_cin(0));
expOvf_uid75_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid75_fpMulTest_a) - SIGNED(expOvf_uid75_fpMulTest_b));
expOvf_uid75_fpMulTest_n(0) <= not (expOvf_uid75_fpMulTest_o(14));
-- invExpXIsMax_uid35_fpMulTest(LOGICAL,34)@2
invExpXIsMax_uid35_fpMulTest_a <= redist3_q;
invExpXIsMax_uid35_fpMulTest_q <= not (invExpXIsMax_uid35_fpMulTest_a);
-- InvExpXIsZero_uid36_fpMulTest(LOGICAL,35)@2
InvExpXIsZero_uid36_fpMulTest_a <= redist4_q;
InvExpXIsZero_uid36_fpMulTest_q <= not (InvExpXIsZero_uid36_fpMulTest_a);
-- excR_y_uid37_fpMulTest(LOGICAL,36)@2
excR_y_uid37_fpMulTest_a <= InvExpXIsZero_uid36_fpMulTest_q;
excR_y_uid37_fpMulTest_b <= invExpXIsMax_uid35_fpMulTest_q;
excR_y_uid37_fpMulTest_q <= excR_y_uid37_fpMulTest_a and excR_y_uid37_fpMulTest_b;
-- invExpXIsMax_uid21_fpMulTest(LOGICAL,20)@2
invExpXIsMax_uid21_fpMulTest_a <= redist6_q;
invExpXIsMax_uid21_fpMulTest_q <= not (invExpXIsMax_uid21_fpMulTest_a);
-- InvExpXIsZero_uid22_fpMulTest(LOGICAL,21)@2
InvExpXIsZero_uid22_fpMulTest_a <= redist7_q;
InvExpXIsZero_uid22_fpMulTest_q <= not (InvExpXIsZero_uid22_fpMulTest_a);
-- excR_x_uid23_fpMulTest(LOGICAL,22)@2
excR_x_uid23_fpMulTest_a <= InvExpXIsZero_uid22_fpMulTest_q;
excR_x_uid23_fpMulTest_b <= invExpXIsMax_uid21_fpMulTest_q;
excR_x_uid23_fpMulTest_q <= excR_x_uid23_fpMulTest_a and excR_x_uid23_fpMulTest_b;
-- ExcROvfAndInReg_uid84_fpMulTest(LOGICAL,83)@2
ExcROvfAndInReg_uid84_fpMulTest_a <= excR_x_uid23_fpMulTest_q;
ExcROvfAndInReg_uid84_fpMulTest_b <= excR_y_uid37_fpMulTest_q;
ExcROvfAndInReg_uid84_fpMulTest_c <= expOvf_uid75_fpMulTest_n;
ExcROvfAndInReg_uid84_fpMulTest_q <= ExcROvfAndInReg_uid84_fpMulTest_a and ExcROvfAndInReg_uid84_fpMulTest_b and ExcROvfAndInReg_uid84_fpMulTest_c;
-- excYRAndExcXI_uid83_fpMulTest(LOGICAL,82)@2
excYRAndExcXI_uid83_fpMulTest_a <= excR_y_uid37_fpMulTest_q;
excYRAndExcXI_uid83_fpMulTest_b <= excI_x_uid19_fpMulTest_q;
excYRAndExcXI_uid83_fpMulTest_q <= excYRAndExcXI_uid83_fpMulTest_a and excYRAndExcXI_uid83_fpMulTest_b;
-- excXRAndExcYI_uid82_fpMulTest(LOGICAL,81)@2
excXRAndExcYI_uid82_fpMulTest_a <= excR_x_uid23_fpMulTest_q;
excXRAndExcYI_uid82_fpMulTest_b <= excI_y_uid33_fpMulTest_q;
excXRAndExcYI_uid82_fpMulTest_q <= excXRAndExcYI_uid82_fpMulTest_a and excXRAndExcYI_uid82_fpMulTest_b;
-- excXIAndExcYI_uid81_fpMulTest(LOGICAL,80)@2
excXIAndExcYI_uid81_fpMulTest_a <= excI_x_uid19_fpMulTest_q;
excXIAndExcYI_uid81_fpMulTest_b <= excI_y_uid33_fpMulTest_q;
excXIAndExcYI_uid81_fpMulTest_q <= excXIAndExcYI_uid81_fpMulTest_a and excXIAndExcYI_uid81_fpMulTest_b;
-- excRInf_uid85_fpMulTest(LOGICAL,84)@2
excRInf_uid85_fpMulTest_a <= excXIAndExcYI_uid81_fpMulTest_q;
excRInf_uid85_fpMulTest_b <= excXRAndExcYI_uid82_fpMulTest_q;
excRInf_uid85_fpMulTest_c <= excYRAndExcXI_uid83_fpMulTest_q;
excRInf_uid85_fpMulTest_d <= ExcROvfAndInReg_uid84_fpMulTest_q;
excRInf_uid85_fpMulTest_q <= excRInf_uid85_fpMulTest_a or excRInf_uid85_fpMulTest_b or excRInf_uid85_fpMulTest_c or excRInf_uid85_fpMulTest_d;
-- expUdf_uid73_fpMulTest(COMPARE,72)@2
expUdf_uid73_fpMulTest_cin <= GND_q;
expUdf_uid73_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "000000000000" & GND_q) & '0');
expUdf_uid73_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 12 => expRPreExcExt_uid71_fpMulTest_b(11)) & expRPreExcExt_uid71_fpMulTest_b) & expUdf_uid73_fpMulTest_cin(0));
expUdf_uid73_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid73_fpMulTest_a) - SIGNED(expUdf_uid73_fpMulTest_b));
expUdf_uid73_fpMulTest_n(0) <= not (expUdf_uid73_fpMulTest_o(14));
-- excZC3_uid79_fpMulTest(LOGICAL,78)@2
excZC3_uid79_fpMulTest_a <= excR_x_uid23_fpMulTest_q;
excZC3_uid79_fpMulTest_b <= excR_y_uid37_fpMulTest_q;
excZC3_uid79_fpMulTest_c <= expUdf_uid73_fpMulTest_n;
excZC3_uid79_fpMulTest_q <= excZC3_uid79_fpMulTest_a and excZC3_uid79_fpMulTest_b and excZC3_uid79_fpMulTest_c;
-- excYZAndExcXR_uid78_fpMulTest(LOGICAL,77)@2
excYZAndExcXR_uid78_fpMulTest_a <= redist4_q;
excYZAndExcXR_uid78_fpMulTest_b <= excR_x_uid23_fpMulTest_q;
excYZAndExcXR_uid78_fpMulTest_q <= excYZAndExcXR_uid78_fpMulTest_a and excYZAndExcXR_uid78_fpMulTest_b;
-- excXZAndExcYR_uid77_fpMulTest(LOGICAL,76)@2
excXZAndExcYR_uid77_fpMulTest_a <= redist7_q;
excXZAndExcYR_uid77_fpMulTest_b <= excR_y_uid37_fpMulTest_q;
excXZAndExcYR_uid77_fpMulTest_q <= excXZAndExcYR_uid77_fpMulTest_a and excXZAndExcYR_uid77_fpMulTest_b;
-- excXZAndExcYZ_uid76_fpMulTest(LOGICAL,75)@2
excXZAndExcYZ_uid76_fpMulTest_a <= redist7_q;
excXZAndExcYZ_uid76_fpMulTest_b <= redist4_q;
excXZAndExcYZ_uid76_fpMulTest_q <= excXZAndExcYZ_uid76_fpMulTest_a and excXZAndExcYZ_uid76_fpMulTest_b;
-- excRZero_uid80_fpMulTest(LOGICAL,79)@2
excRZero_uid80_fpMulTest_a <= excXZAndExcYZ_uid76_fpMulTest_q;
excRZero_uid80_fpMulTest_b <= excXZAndExcYR_uid77_fpMulTest_q;
excRZero_uid80_fpMulTest_c <= excYZAndExcXR_uid78_fpMulTest_q;
excRZero_uid80_fpMulTest_d <= excZC3_uid79_fpMulTest_q;
excRZero_uid80_fpMulTest_q <= excRZero_uid80_fpMulTest_a or excRZero_uid80_fpMulTest_b or excRZero_uid80_fpMulTest_c or excRZero_uid80_fpMulTest_d;
-- concExc_uid90_fpMulTest(BITJOIN,89)@2
concExc_uid90_fpMulTest_q <= excRNaN_uid89_fpMulTest_q & excRInf_uid85_fpMulTest_q & excRZero_uid80_fpMulTest_q;
-- excREnc_uid91_fpMulTest(LOOKUP,90)@2
excREnc_uid91_fpMulTest: PROCESS (concExc_uid90_fpMulTest_q)
BEGIN
-- Begin reserved scope level
CASE (concExc_uid90_fpMulTest_q) IS
WHEN "000" => excREnc_uid91_fpMulTest_q <= "01";
WHEN "001" => excREnc_uid91_fpMulTest_q <= "00";
WHEN "010" => excREnc_uid91_fpMulTest_q <= "10";
WHEN "011" => excREnc_uid91_fpMulTest_q <= "00";
WHEN "100" => excREnc_uid91_fpMulTest_q <= "11";
WHEN "101" => excREnc_uid91_fpMulTest_q <= "00";
WHEN "110" => excREnc_uid91_fpMulTest_q <= "00";
WHEN "111" => excREnc_uid91_fpMulTest_q <= "00";
WHEN OTHERS => -- unreachable
excREnc_uid91_fpMulTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- expRPostExc_uid100_fpMulTest(MUX,99)@2
expRPostExc_uid100_fpMulTest_s <= excREnc_uid91_fpMulTest_q;
expRPostExc_uid100_fpMulTest: PROCESS (expRPostExc_uid100_fpMulTest_s, en, cstAllZWE_uid12_fpMulTest_q, expRPreExc_uid72_fpMulTest_b, cstAllOWE_uid10_fpMulTest_q)
BEGIN
CASE (expRPostExc_uid100_fpMulTest_s) IS
WHEN "00" => expRPostExc_uid100_fpMulTest_q <= cstAllZWE_uid12_fpMulTest_q;
WHEN "01" => expRPostExc_uid100_fpMulTest_q <= expRPreExc_uid72_fpMulTest_b;
WHEN "10" => expRPostExc_uid100_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q;
WHEN "11" => expRPostExc_uid100_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q;
WHEN OTHERS => expRPostExc_uid100_fpMulTest_q <= (others => '0');
END CASE;
END PROCESS;
-- oneFracRPostExc2_uid92_fpMulTest(CONSTANT,91)
oneFracRPostExc2_uid92_fpMulTest_q <= "00000000000000000000001";
-- fracRPreExc_uid70_fpMulTest(BITSELECT,69)@2
fracRPreExc_uid70_fpMulTest_in <= expFracRPostRounding_uid69_fpMulTest_q(23 downto 0);
fracRPreExc_uid70_fpMulTest_b <= fracRPreExc_uid70_fpMulTest_in(23 downto 1);
-- fracRPostExc_uid95_fpMulTest(MUX,94)@2
fracRPostExc_uid95_fpMulTest_s <= excREnc_uid91_fpMulTest_q;
fracRPostExc_uid95_fpMulTest: PROCESS (fracRPostExc_uid95_fpMulTest_s, en, cstZeroWF_uid11_fpMulTest_q, fracRPreExc_uid70_fpMulTest_b, oneFracRPostExc2_uid92_fpMulTest_q)
BEGIN
CASE (fracRPostExc_uid95_fpMulTest_s) IS
WHEN "00" => fracRPostExc_uid95_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q;
WHEN "01" => fracRPostExc_uid95_fpMulTest_q <= fracRPreExc_uid70_fpMulTest_b;
WHEN "10" => fracRPostExc_uid95_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q;
WHEN "11" => fracRPostExc_uid95_fpMulTest_q <= oneFracRPostExc2_uid92_fpMulTest_q;
WHEN OTHERS => fracRPostExc_uid95_fpMulTest_q <= (others => '0');
END CASE;
END PROCESS;
-- R_uid103_fpMulTest(BITJOIN,102)@2
R_uid103_fpMulTest_q <= signRPostExc_uid102_fpMulTest_q & expRPostExc_uid100_fpMulTest_q & fracRPostExc_uid95_fpMulTest_q;
-- xOut(GPOUT,4)@2
q <= R_uid103_fpMulTest_q;
END normal;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Font_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(8-1 downto 0)
);
end Font_exdes;
architecture xilinx of Font_exdes is
component Font is
PORT (
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : Font
port map (
SPO => SPO,
A => A
);
end xilinx;
|
library verilog;
use verilog.vl_types.all;
entity Test_Line is
port(
address : in vl_logic_vector(0 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(7 downto 0)
);
end Test_Line;
|
library verilog;
use verilog.vl_types.all;
entity Test_Line is
port(
address : in vl_logic_vector(0 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(7 downto 0)
);
end Test_Line;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 10:10:04 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_inverter_0_0_1/system_inverter_0_0_sim_netlist.vhdl
-- Design : system_inverter_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_inverter_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_inverter_0_0 : entity is "system_inverter_0_0,inverter,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_inverter_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_inverter_0_0 : entity is "inverter,Vivado 2016.4";
end system_inverter_0_0;
architecture STRUCTURE of system_inverter_0_0 is
begin
x_not_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => x,
O => x_not
);
end STRUCTURE;
|
---------------------------------------------------------------------------
-- Color_Mapper.vhd --
-- Stephen Kempf, David Kesler, Raj Vinjamuri, Sai Koppula --
-- 4-13 --
-- --
-- For use with ECE 385 --
-- University of Illinois ECE Department --
-- --
-- --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Color_Mapper is
Port ( game_status : in std_logic_vector(3 downto 0);
BallX, BallY : in std_logic_vector(10 downto 0);
PaddleX, PaddleY : in std_logic_vector (10 downto 0);
BricksX, BricksY : in std_logic_vector(219 downto 0);
BricksOn : in std_logic_vector(19 downto 0);
DrawX, DrawY : in std_logic_vector(10 downto 0);
Ball_size : in std_logic_vector(10 downto 0);
Paddle_size : in std_logic_vector(10 downto 0);
-- Brick_size : in std_logic_vector(9 downto 0);
Red : out std_logic_vector(9 downto 0);
Green : out std_logic_vector(9 downto 0);
Blue : out std_logic_vector(9 downto 0));
end Color_Mapper;
architecture Behavioral of Color_Mapper is
signal Ball_on, Paddle_on, Brick_on : std_logic;
signal Brick_Width : std_logic_vector(10 downto 0);
signal Brick_Height : std_logic_vector(10 downto 0);
signal BrickX, BrickY : std_logic_vector(10 downto 0);
signal BrickOn : std_logic;
signal start , ender : natural;
--signal temp1, temp2 : std_logic_vector(9 downto 0) := CONV_STD_LOGIC_VECTOR(100, 10); --Step size on the Y axis (modified)
begin
Brick_Width <= CONV_STD_LOGIC_VECTOR(60, 11); -- assigns the value 4 as a 10-digit binary number, ie "0000000100"
Brick_Height <= CONV_STD_LOGIC_VECTOR(20, 11);
-----------------------------------------------------
Ball_on_proc : process (BallX, BallY, DrawX, DrawY, Ball_size)
begin
-- Old Ball: Generated square box by checking if the current pixel is within a square of length
-- 2*Ball_Size, centered at (BallX, BallY). Note that this requires unsigned comparisons, by using
-- IEEE.STD_LOGIC_UNSIGNED.ALL at the top.
-- if ((DrawX >= BallX - Ball_size) AND
-- (DrawX <= BallX + Ball_size) AND
-- (DrawY >= BallY - Ball_size) AND
-- (DrawY <= BallY + Ball_size)) then
-- New Ball: Generates (pixelated) circle by using the standard circle formula. Note that while
-- this single line is quite powerful descriptively, it causes the synthesis tool to use up three
-- of the 12 available multipliers on the chip! It also requires IEEE.STD_LOGIC_SIGNED.ALL for
-- the signed multiplication to operate correctly.
if ((((DrawX - BallX) * (DrawX - BallX)) + ((DrawY - BallY) * (DrawY - BallY))) <= (Ball_size*Ball_size)) then
Ball_on <= '1';
else
Ball_on <= '0';
end if;
end process Ball_on_proc;
-----------------------------------------------------
Paddle_on_proc : process (PaddleX, PaddleY, DrawX, DrawY, Paddle_size)
begin
if ((DrawX >= PaddleX - ("00000000110"*Paddle_size)) AND
(DrawX <= PaddleX + ("00000000110"*Paddle_size)) AND
(DrawY >= PaddleY - Paddle_size) AND
(DrawY <= PaddleY + Paddle_size)) then
Paddle_on <= '1';
else
Paddle_on <= '0';
end if;
end process Paddle_on_proc;
-----------------------------------------------------
-----------------------------------------------------
Brick_on_proc : process (BrickX, BrickY, DrawX, DrawY)
begin
Brick_On <= '0';
--for I in 0 to 19 loop
--start <= I*11+10;
--ender <= I*11;
--case I is
--when 0 =>
--BrickX <= BricksX(10 downto 0);
--BrickY <= BricksY(10 downto 0);
--BrickOn <= BricksOn(0);
--when others =>
--BrickX <= BricksX(219 downto 209);
--BrickY <= BricksY(219 downto 209);
--BrickOn <= BricksOn(19);
--end case;
--BrickX <= BricksX(10 downto 0);
--BrickY <= BricksY(10 downto 0);
--BrickOn <= BricksOn(0);
if (DrawX <= BricksX(10 downto 0) + Brick_Width) AND (DrawX >= BricksX(10 downto 0))
AND (DrawY>= BricksY(10 downto 0)) AND (DrawY<= BricksY(10 downto 0) + Brick_Height)
AND (BricksOn(0) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(21 downto 11) + Brick_Width) AND (DrawX >= BricksX(21 downto 11))
AND (DrawY>= BricksY(21 downto 11)) AND (DrawY<= BricksY(21 downto 11) + Brick_Height)
AND (BricksOn(1) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(32 downto 22) + Brick_Width) AND (DrawX >= BricksX(32 downto 22))
AND (DrawY>= BricksY(32 downto 22)) AND (DrawY<= BricksY(32 downto 22) + Brick_Height)
AND (BricksOn(2) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(43 downto 33) + Brick_Width) AND (DrawX >= BricksX(43 downto 33))
AND (DrawY>= BricksY(43 downto 33)) AND (DrawY<= BricksY(43 downto 33) + Brick_Height)
AND (BricksOn(3) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(54 downto 44) + Brick_Width) AND (DrawX >= BricksX(54 downto 44))
AND (DrawY>= BricksY(54 downto 44)) AND (DrawY<= BricksY(54 downto 44) + Brick_Height)
AND (BricksOn(4) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(65 downto 55) + Brick_Width) AND (DrawX >= BricksX(65 downto 55))
AND (DrawY>= BricksY(65 downto 55)) AND (DrawY<= BricksY(65 downto 55) + Brick_Height)
AND (BricksOn(5) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(76 downto 66) + Brick_Width) AND (DrawX >= BricksX(76 downto 66))
AND (DrawY>= BricksY(76 downto 66)) AND (DrawY<= BricksY(76 downto 66) + Brick_Height)
AND (BricksOn(6) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(87 downto 77) + Brick_Width) AND (DrawX >= BricksX(87 downto 77))
AND (DrawY>= BricksY(87 downto 77)) AND (DrawY<= BricksY(87 downto 77) + Brick_Height)
AND (BricksOn(7) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(98 downto 88) + Brick_Width) AND (DrawX >= BricksX(98 downto 88))
AND (DrawY>= BricksY(98 downto 88)) AND (DrawY<= BricksY(98 downto 88) + Brick_Height)
AND (BricksOn(8) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(109 downto 99) + Brick_Width) AND (DrawX >= BricksX(109 downto 99))
AND (DrawY>= BricksY(109 downto 99)) AND (DrawY<= BricksY(109 downto 99) + Brick_Height)
AND (BricksOn(9) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(120 downto 110) + Brick_Width) AND (DrawX >= BricksX(120 downto 110))
AND (DrawY>= BricksY(120 downto 110)) AND (DrawY<= BricksY(120 downto 110) + Brick_Height)
AND (BricksOn(10) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(131 downto 121) + Brick_Width) AND (DrawX >= BricksX(131 downto 121))
AND (DrawY>= BricksY(131 downto 121)) AND (DrawY<= BricksY(131 downto 121) + Brick_Height)
AND (BricksOn(11) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(142 downto 132) + Brick_Width) AND (DrawX >= BricksX(142 downto 132))
AND (DrawY>= BricksY(142 downto 132)) AND (DrawY<= BricksY(142 downto 132) + Brick_Height)
AND (BricksOn(12) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(153 downto 143) + Brick_Width) AND (DrawX >= BricksX(153 downto 143))
AND (DrawY>= BricksY(153 downto 143)) AND (DrawY<= BricksY(153 downto 143) + Brick_Height)
AND (BricksOn(13) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(164 downto 154) + Brick_Width) AND (DrawX >= BricksX(164 downto 154))
AND (DrawY>= BricksY(164 downto 154)) AND (DrawY<= BricksY(164 downto 154) + Brick_Height)
AND (BricksOn(14) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(175 downto 165) + Brick_Width) AND (DrawX >= BricksX(175 downto 165))
AND (DrawY>= BricksY(175 downto 165)) AND (DrawY<= BricksY(175 downto 165) + Brick_Height)
AND (BricksOn(15) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(186 downto 176) + Brick_Width) AND (DrawX >= BricksX(186 downto 176))
AND (DrawY>= BricksY(186 downto 176)) AND (DrawY<= BricksY(186 downto 176) + Brick_Height)
AND (BricksOn(16) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(197 downto 187) + Brick_Width) AND (DrawX >= BricksX(197 downto 187))
AND (DrawY>= BricksY(197 downto 187)) AND (DrawY<= BricksY(197 downto 187) + Brick_Height)
AND (BricksOn(17) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(208 downto 198) + Brick_Width) AND (DrawX >= BricksX(208 downto 198))
AND (DrawY>= BricksY(208 downto 198)) AND (DrawY<= BricksY(208 downto 198) + Brick_Height)
AND (BricksOn(18) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(219 downto 209) + Brick_Width) AND (DrawX >= BricksX(219 downto 209))
AND (DrawY>= BricksY(219 downto 209)) AND (DrawY<= BricksY(219 downto 209) + Brick_Height)
AND (BricksOn(19) = '1') then
Brick_On <= '1';
end if;
--end loop;
end process Brick_on_proc;
--
--
-----------------------------------------------------
RGB_Display : process (game_status, Ball_on, Paddle_on, Brick_on, DrawX, DrawY)
variable GreenVar, BlueVar : std_logic_vector(22 downto 0);
begin
if (Ball_on = '1') AND
(Paddle_on = '0') then -- turn ball on display --ball
if (game_status(0) = '0') then
Red <= "0101010101";
Green <= "1010101010";
Blue <= "1010101010";
else --change ball to black if lost
Red <= "0000000000";
Green <= "0000000000";
Blue <= "0000000000";
end if;
elsif (Paddle_on = '1') then -- turn paddle on display --paddle
if (game_status(0) = '0') then
Red <= "0000000000";
Green <= "1001100010";
Blue <= "0000000000";
else --change paddle to red if lost
Red <= "1001100010";
Green <= "0000000000";
Blue <= "0000000000";
end if;
elsif (Brick_On = '1') then --turn brick on display --bricks
if (game_status(0) = '0') then
Red <= "1010101010";
Green <= "0101010101";
Blue <= "0000000000";
else --change brick to White if lost
Red <= "1010101010";
Green <= "1010101010";
Blue <= "1010101010";
end if;
else -- turn on gradient background --BG
if (game_status(3) = '1') then
Red <= DrawY(9 downto 0);
Green <= "0111100010";
Blue <= DrawY(9 downto 0);
elsif (game_status(0) = '0') then
Red <= DrawY(9 downto 0);
Green <= DrawY(9 downto 0);
Blue <= DrawY(9 downto 0);
else --change background to if lost
Red <= "0111100010";
Green <= DrawY(9 downto 0);
Blue <= DrawY(9 downto 0);
end if;
end if;
end process RGB_Display;
-----------------------------------------------------
end Behavioral;
------------Previous Code, saved for possible reuse ------------------
-- BrickX <= temp1;
-- BrickY <= temp1;
-- Brick_size <= "0000000100"
--
-- --already lose? put all Bricks back
-- if (game_statusSig = '1') then Brick_statusSig <= '0';
-- end if;
--
-- if ((DrawX >= BrickX - ("0000000100"*Brick_size)) AND
-- (DrawX <= BrickX + ("0000000100"*Brick_size)) AND
-- (DrawY >= BrickY - Brick_size) AND
-- (DrawY <= BrickY + Brick_size)) then
-- Brick_on <= '1';
-- else
-- Brick_on <= '0';
-- end if;
--------------------------------------------------------------------- |
--
-- PhaseGenerator.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org)
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
--
-- modified by t.hara
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.vm2413.all;
entity PhaseGenerator is
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in std_logic_vector( 4 downto 0 );
stage : in std_logic_vector( 1 downto 0 );
rhythm : in std_logic;
pm : in std_logic;
ml : in std_logic_vector(3 downto 0);
blk : in std_logic_vector(2 downto 0);
fnum : in std_logic_vector(8 downto 0);
key : in std_logic;
noise : out std_logic;
pgout : out std_logic_vector( 17 downto 0 )
);
end entity;
architecture RTL of PhaseGenerator is
type ML_TABLE is array (0 to 15) of std_logic_vector(4 downto 0);
constant mltbl : ML_TABLE := (
"00001","00010","00100","00110","01000","01010","01100","01110",
"10000","10010","10100","10100","11000","11000","11110","11110"
);
constant noise14_tbl : std_logic_vector(63 downto 0) :=
"1000100010001000100010001000100100010001000100010001000100010000";
constant noise17_tbl : std_logic_vector(7 downto 0) :=
"00001010";
-- Signals connected to the phase memory.
signal memwr : std_logic;
signal memout, memin : std_logic_vector (17 downto 0);
-- Counter for pitch modulation;
signal pmcount : std_logic_vector(12 downto 0);
begin
process(clk, reset)
variable lastkey : std_logic_vector(18-1 downto 0);
variable dphase : std_logic_vector (17 downto 0);
variable noise14 : std_logic;
variable noise17 : std_logic;
variable pgout_buf : std_logic_vector( 17 downto 0 ); -- ® 9bit, ¬ 9bit
begin
if reset = '1' then
pmcount <= (others=>'0');
memwr <= '0';
lastkey := (others=>'0');
dphase := (others=>'0');
noise14 := '0';
noise17 := '0';
elsif clk'event and clk='1' then if clkena = '1' then
noise <= noise14 xor noise17;
if stage = 0 then
memwr <= '0';
elsif stage = 1 then
-- Wait for memory
elsif stage = 2 then
-- Update pitch LFO counter when slot = 0 and stage = 0 (i.e. increment per 72 clocks)
if slot = 0 then
pmcount <= pmcount + '1';
end if;
-- Delta phase
dphase := (SHL("00000000"&(fnum*mltbl(CONV_INTEGER(ml))),blk)(19 downto 2));
if pm ='1' then
case pmcount(pmcount'high downto pmcount'high-1) is
when "01" =>
dphase := dphase + SHR(dphase,"111");
when "11" =>
dphase := dphase - SHR(dphase,"111");
when others => null;
end case;
end if;
-- Update Phase
if lastkey(conv_integer(slot)) = '0' and key = '1' and (rhythm = '0' or (slot /= "01110" and slot /= "10001")) then
memin <= (others=>'0');
else
memin <= memout + dphase;
end if;
lastkey(conv_integer(slot)) := key;
-- Update noise
if slot = "01110" then
noise14 := noise14_tbl(CONV_INTEGER(memout(15 downto 10)));
elsif slot = "10001" then
noise17 := noise17_tbl(CONV_INTEGER(memout(13 downto 11)));
end if;
pgout_buf := memout;
pgout <= pgout_buf;
memwr <= '1';
elsif stage = 3 then
memwr <= '0';
end if;
end if; end if;
end process;
MEM : entity work.PhaseMemory
port map (
clk,reset,slot,memwr,memout,memin
);
end architecture;
|
-------------------------------------------------------------------------------
--
-- File: tb_TestAD96xx_92xxSPI_Model.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Test bench used to validate the AD96xx_92xxSPI_Model simulation model.
-- Errors encoded by the kErrorType generic are deliberately inserted in subsequent
-- SPI transactions.
-- This test bench will be instantiated as multiple entities in the
-- tb_TestAD96xx_92xxSPI_Model_all to cover all supported error types.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.PkgZmodADC.all;
entity tb_TestAD96xx_92xxSPI_Model is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 0;
-- kErrorType encodes the error introduced by the test bench:
-- 0-No error.
-- 1-Insert sSDIO to sSPI_Clk Setup Time error for Cmd[2] and Data[2] bits of kSclkHigh.
-- 2-Insert CS to sSPI_Clk and data to sSPI_Clk (on Cmd[15]) setup time error of 1ns.
-- 3-Insert sSDIO to sSPI_Clk hold time error of 1ns for command bit 2.
-- 4-Insert sCS to sSPI_Clk hold time error of 1ns; sSPI_Clk pulse width errors
-- and hold time error also inserted on Data[0].
-- 5-Insert pulse width errors (0.5ns) and TestSPI_Clk period errors Cmd[2] and Data[2].
-- 6-Send extra address bit (25 bit transfer).
kErrorType : integer := 1;
--kCmdRdWr selects between read and write operations: '1' -> read; '0' -> write.
kCmdRdWr : std_logic := '0';
-- Command address; Error reporting depends on the kCmdAddr's value!
-- Transition on the error affected bits is necessary!
kCmdAddr : std_logic_vector (12 downto 0) := "0000000000101";
-- Command address; Error reporting depends on the kCmdAddr's value!
kCmdData : std_logic_vector (7 downto 0) := x"AA";
-- The number of data bits for the data phase of the transaction:
-- only 8 data bits currently supported.
kNoDataBits : integer := 8;
-- The number of bits of the command phase of the SPI transaction.
kNoCommandBits : integer := 16
);
end tb_TestAD96xx_92xxSPI_Model;
architecture Behavioral of tb_TestAD96xx_92xxSPI_Model is
signal asRst_n : std_logic := '0';
signal TestSPI_Clk, tSDIO : std_logic := 'X';
signal tCS : std_logic := '1';
signal tCommand : std_logic_vector(15 downto 0);
signal tData : std_logic_vector(7 downto 0);
signal SysClk100 : std_logic := '1';
begin
Clock: process
begin
for i in 0 to 1000 loop
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
end loop;
wait;
end process;
AD96xx_AD92xx_inst: entity work.AD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
InsertError => '0',
sSPI_Clk => TestSPI_Clk,
sSDIO => tSDIO,
sCS => tCS
);
Main: process
begin
-- Assert the reset signal
asRst_n <= '0';
-- Hold the reset condition for 10 clock cycles
-- (one clock cycle is sufficient, however 10 clock cycles makes
-- it easier to visualize the reset condition in simulation).
wait for kSysClkPeriod*10;
asRst_n <= '1';
if (kErrorType = 0) then
if (kCmdRdWr = '1') then
-- Read operation: SPI read register correct sequence.
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for ktS;
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end loop;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= 'Z';
wait for kSclkLow*3;
end loop;
wait for ktH;
tSDIO <= '0';
tCS <= '1';
else
-- Write operation: SPI read register correct sequence.
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for ktS;
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end loop;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i > 0) then
tSDIO <= tData(i-1);
else
tSDIO <= 'Z';
end if;
wait for kSclkLow*3;
end loop;
wait for ktH;
tSDIO <= '0';
tCS <= '1';
end if;
elsif (kErrorType = 1) then
if (kCmdRdWr = '1') then
-- Read operation not currently supported for this error type.
TestSPI_Clk <= '0';
tCS <= '1';
tSDIO <= '0';
else
-- Write operation: Insert tSDIO to TestSPI_Clk Setup Time error for Cmd[2]
-- and Data[2] bits of kSclkHigh.
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for ktS;
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
if (i = 1) then
report "Insert sSDIO to sSPI_Clk setup time error on Cmd[2]" & LF & HT & HT;
tSDIO <= tCommand(i+1);
end if;
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i /= 2) then
tSDIO <= tCommand(i);
end if;
wait for kSclkLow*3;
end loop;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
if (i = 2) then
report "Insert sSDIO to sSPI_Clk setup time error on Data[2]" & LF & HT & HT;
tSDIO <= tData(i);
end if;
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i > 0) then
if (i /= 3) then
tSDIO <= tData(i-1);
end if;
else
tSDIO <= 'Z';
end if;
wait for kSclkLow*3;
end loop;
wait for ktH;
tSDIO <= '0';
tCS <= '1';
end if;
elsif (kErrorType = 2) then
if (kCmdRdWr = '1') then
-- Read operation not currently supported for this error type.
TestSPI_Clk <= '0';
tCS <= '1';
tSDIO <= '0';
else
-- Write operation: Insert tCS to TestSPI_Clk and tSDIO to TestSPI_Clk
-- (on Cmd[15]) setup time error of 1ns.
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for (ktS - 1 ns);
report "Insert sCS and sSDIO (Cmd[15]) to sSPI_Clk setup time error" & LF & HT & HT;
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end loop;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i > 0) then
tSDIO <= tData(i-1);
else
tSDIO <= 'Z';
end if;
wait for kSclkLow*3;
end loop;
wait for ktH;
tSDIO <= '0';
tCS <= '1';
end if;
elsif (kErrorType = 3) then
if (kCmdRdWr = '1') then
-- Read operation not currently supported for this error type.
TestSPI_Clk <= '0';
tCS <= '1';
tSDIO <= '0';
else
-- Write operation: Insert sSDIO to TestSPI_Clk hold time error of 1ns
-- for command bit 2.
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for (ktS);
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
wait for (ktDH - 1 ns);
if (i = 1) then
report "Insert sSDIO (Cmd[2]) to sSPI_Clk hold time error" & LF & HT & HT;
tSDIO <= tCommand(i);
end if;
wait for (kSclkHigh*3 - ktDH + 1ns);
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end loop;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i > 0) then
tSDIO <= tData(i-1);
else
tSDIO <= 'Z';
end if;
wait for kSclkLow*3;
end loop;
wait for ktH;
tSDIO <= '0';
tCS <= '1';
end if;
elsif (kErrorType = 4) then
if (kCmdRdWr = '1') then
-- Read operation not currently supported for this error type.
TestSPI_Clk <= '0';
tCS <= '1';
tSDIO <= '0';
else
-- Write operation: Insert tCS to TestSPI_Clk hold time error of 1ns;
-- TestSPI_Clk pulse width errors and hold time error also inserted on Data[0].
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for (ktS);
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
wait for (kSclkHigh*3);
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end loop;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
if (i = 0) then
wait for ((ktH - 1ns)/2);
report "insert sSPI_Clk pulse width error and sSDIO (Data[0]) to sSPI_Clk hold time error" & LF & HT & HT;
else
wait for kSclkHigh*3;
end if;
TestSPI_Clk <= '0';
if (i > 0) then
tSDIO <= tData(i-1);
else
tSDIO <= 'Z';
end if;
if (i = 0) then
wait for ((ktH - 1ns)/2);
report "insert sCS to sSPI_Clk hold and sSPI_CLK pulse width errors" & LF & HT & HT;
tCS <= '1';
else
wait for kSclkLow*3;
end if;
end loop;
tSDIO <= '0';
tCS <= '1';
end if;
elsif (kErrorType = 5) then
if (kCmdRdWr = '1') then
-- Read operation not currently supported for this error type.
TestSPI_Clk <= '0';
tCS <= '1';
tSDIO <= '0';
else
-- Write operation: insert pulse width errors (0.5ns) and TestSPI_Clk
-- period errors on Cmd[2] and Data[2].
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for ktS;
for i in (kNoCommandBits - 2) downto 0 loop
if (i=1) then
-- Rising edge of address bit 2.
TestSPI_Clk <= '1';
wait for (kSclkHigh - 0.5ns);
report "Insert sSPI_Clk pulse width high error on Cmd[2]" & LF & HT & HT;
TestSPI_Clk <= '0';
-- Place address bit 1 on SDIO.
tSDIO <= tCommand(i);
wait for (kSclkLow - 0.5ns);
report "Insert sSPI_Clk pulse width low and period error on Cmd[2]" & LF & HT & HT;
else
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end if;
end loop;
for i in (kNoDataBits) downto 0 loop
if (i = 2) then
TestSPI_Clk <= '1';
wait for (kSclkHigh - 0.5ns);
report "Insert sSPI_Clk pulse width high error on Data[2]" & LF & HT & HT;
TestSPI_Clk <= '0';
tSDIO <= tData(i-1);
wait for (kSclkLow - 0.5ns);
report "Insert sSPI_Clk pulse width low and period error on Data[2]" & LF & HT & HT;
else
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i > 0) then
tSDIO <= tData(i-1);
else
tSDIO <= 'Z';
end if;
wait for kSclkLow*3;
end if;
end loop;
wait for ktH;
tSDIO <= '0';
tCS <= '1';
end if;
elsif (kErrorType = 6) then
if (kCmdRdWr = '1') then
-- Read operation not currently supported for this error type.
TestSPI_Clk <= '0';
tCS <= '1';
tSDIO <= '0';
else
-- Write operation: send extra command bit (25 bit transfer).
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for ktS;
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end loop;
-- Add extra command bit.
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= tCommand(0);
wait for kSclkLow*3;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i > 0) then
tSDIO <= tData(i-1);
else
tSDIO <= 'Z';
end if;
wait for kSclkLow*3;
end loop;
wait for ktH;
report "Insert Extra bit in transaction" & LF & HT & HT;
tSDIO <= '0';
tCS <= '1';
wait for 100 ns;
end if;
end if;
wait;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulsennAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulsennAltr ;
architecture syn of alt_dspbuilder_sImpulsennAltr is
type States_ImpulseAltr is (sclear, slow, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
signal count : std_logic_vector(ToNatural(nbitnecessary(Impulsedelay)-1) downto 0);
signal countwidth : std_logic_vector(ToNatural(nbitnecessary(Impulsewidth)-1) downto 0);
signal enawidth : std_logic;
begin
rp:process(clock,aclr)
begin
if aclr='1' then
count <= (others=>'0');
countwidth <= (others=>'0');
current_state <= sclear;
elsif clock'event and clock='1' then
if (sclr='1') then
count <= (others=>'0');
countwidth <= (others=>'0');
current_state <= sclear;
elsif (ena='1') then
count <= count+int2ustd(1,nbitnecessary(Impulsedelay));
current_state <= next_state;
if (enawidth='1') then
countwidth <= countwidth+int2ustd(1,nbitnecessary(Impulsewidth));
end if;
end if;
end if;
end process;
cp:process(count, countwidth, current_state, sclr, ena)
begin
case current_state is
when sclear =>
q <= '0';
enawidth <='0';
if (ena='1') and (sclr='0') then
next_state <= slow;
else
next_state <= sclear;
end if;
when slow =>
q <= '0';
enawidth <='0';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(Impulsedelay-1,nbitnecessary(Impulsedelay))) and (ena='1') then
next_state <= shigh;
else
next_state <= slow ;
end if;
when shigh =>
q <= '1';
enawidth <='1';
if (sclr='1') then
next_state <= sclear;
elsif (countwidth=int2ustd(Impulsewidth-1,nbitnecessary(Impulsewidth))) and (ena='1') then
next_state <= slowend ;
else
next_state <= shigh;
end if;
when slowend =>
q <= '0';
enawidth <='0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulsennAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulsennAltr ;
architecture syn of alt_dspbuilder_sImpulsennAltr is
type States_ImpulseAltr is (sclear, slow, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
signal count : std_logic_vector(ToNatural(nbitnecessary(Impulsedelay)-1) downto 0);
signal countwidth : std_logic_vector(ToNatural(nbitnecessary(Impulsewidth)-1) downto 0);
signal enawidth : std_logic;
begin
rp:process(clock,aclr)
begin
if aclr='1' then
count <= (others=>'0');
countwidth <= (others=>'0');
current_state <= sclear;
elsif clock'event and clock='1' then
if (sclr='1') then
count <= (others=>'0');
countwidth <= (others=>'0');
current_state <= sclear;
elsif (ena='1') then
count <= count+int2ustd(1,nbitnecessary(Impulsedelay));
current_state <= next_state;
if (enawidth='1') then
countwidth <= countwidth+int2ustd(1,nbitnecessary(Impulsewidth));
end if;
end if;
end if;
end process;
cp:process(count, countwidth, current_state, sclr, ena)
begin
case current_state is
when sclear =>
q <= '0';
enawidth <='0';
if (ena='1') and (sclr='0') then
next_state <= slow;
else
next_state <= sclear;
end if;
when slow =>
q <= '0';
enawidth <='0';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(Impulsedelay-1,nbitnecessary(Impulsedelay))) and (ena='1') then
next_state <= shigh;
else
next_state <= slow ;
end if;
when shigh =>
q <= '1';
enawidth <='1';
if (sclr='1') then
next_state <= sclear;
elsif (countwidth=int2ustd(Impulsewidth-1,nbitnecessary(Impulsewidth))) and (ena='1') then
next_state <= slowend ;
else
next_state <= shigh;
end if;
when slowend =>
q <= '0';
enawidth <='0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulsennAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulsennAltr ;
architecture syn of alt_dspbuilder_sImpulsennAltr is
type States_ImpulseAltr is (sclear, slow, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
signal count : std_logic_vector(ToNatural(nbitnecessary(Impulsedelay)-1) downto 0);
signal countwidth : std_logic_vector(ToNatural(nbitnecessary(Impulsewidth)-1) downto 0);
signal enawidth : std_logic;
begin
rp:process(clock,aclr)
begin
if aclr='1' then
count <= (others=>'0');
countwidth <= (others=>'0');
current_state <= sclear;
elsif clock'event and clock='1' then
if (sclr='1') then
count <= (others=>'0');
countwidth <= (others=>'0');
current_state <= sclear;
elsif (ena='1') then
count <= count+int2ustd(1,nbitnecessary(Impulsedelay));
current_state <= next_state;
if (enawidth='1') then
countwidth <= countwidth+int2ustd(1,nbitnecessary(Impulsewidth));
end if;
end if;
end if;
end process;
cp:process(count, countwidth, current_state, sclr, ena)
begin
case current_state is
when sclear =>
q <= '0';
enawidth <='0';
if (ena='1') and (sclr='0') then
next_state <= slow;
else
next_state <= sclear;
end if;
when slow =>
q <= '0';
enawidth <='0';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(Impulsedelay-1,nbitnecessary(Impulsedelay))) and (ena='1') then
next_state <= shigh;
else
next_state <= slow ;
end if;
when shigh =>
q <= '1';
enawidth <='1';
if (sclr='1') then
next_state <= sclear;
elsif (countwidth=int2ustd(Impulsewidth-1,nbitnecessary(Impulsewidth))) and (ena='1') then
next_state <= slowend ;
else
next_state <= shigh;
end if;
when slowend =>
q <= '0';
enawidth <='0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulsennAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulsennAltr ;
architecture syn of alt_dspbuilder_sImpulsennAltr is
type States_ImpulseAltr is (sclear, slow, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
signal count : std_logic_vector(ToNatural(nbitnecessary(Impulsedelay)-1) downto 0);
signal countwidth : std_logic_vector(ToNatural(nbitnecessary(Impulsewidth)-1) downto 0);
signal enawidth : std_logic;
begin
rp:process(clock,aclr)
begin
if aclr='1' then
count <= (others=>'0');
countwidth <= (others=>'0');
current_state <= sclear;
elsif clock'event and clock='1' then
if (sclr='1') then
count <= (others=>'0');
countwidth <= (others=>'0');
current_state <= sclear;
elsif (ena='1') then
count <= count+int2ustd(1,nbitnecessary(Impulsedelay));
current_state <= next_state;
if (enawidth='1') then
countwidth <= countwidth+int2ustd(1,nbitnecessary(Impulsewidth));
end if;
end if;
end if;
end process;
cp:process(count, countwidth, current_state, sclr, ena)
begin
case current_state is
when sclear =>
q <= '0';
enawidth <='0';
if (ena='1') and (sclr='0') then
next_state <= slow;
else
next_state <= sclear;
end if;
when slow =>
q <= '0';
enawidth <='0';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(Impulsedelay-1,nbitnecessary(Impulsedelay))) and (ena='1') then
next_state <= shigh;
else
next_state <= slow ;
end if;
when shigh =>
q <= '1';
enawidth <='1';
if (sclr='1') then
next_state <= sclear;
elsif (countwidth=int2ustd(Impulsewidth-1,nbitnecessary(Impulsewidth))) and (ena='1') then
next_state <= slowend ;
else
next_state <= shigh;
end if;
when slowend =>
q <= '0';
enawidth <='0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
|
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