content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
package ftlbase is
constant ZERO_std_ulogic : std_ulogic := '0';
constant UNDEF_std_ulogic : std_ulogic := 'U';
function to_bool(x: std_ulogic) return boolean;
function to_stdulogic(x: boolean) return std_ulogic;
function zero_std_logic_vector(hi: integer; lo: integer) ret... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:53:03 06/10/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/UDP_RX_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versio... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "... |
-------------------------------------------------------------------------------
-- $Id: parity.vhd,v 1.1.2.2 2010/09/06 09:01:24 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- This module is used for dividing master clock
-- frecuency to required base Bauds frecuency.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRateRD is
port(
RST : in std_logic;
CLK : in std_logic;
ENC : in std_logic;
NBau... |
-- This module is used for dividing master clock
-- frecuency to required base Bauds frecuency.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRateRD is
port(
RST : in std_logic;
CLK : in std_logic;
ENC : in std_logic;
NBau... |
-- This module is used for dividing master clock
-- frecuency to required base Bauds frecuency.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRateRD is
port(
RST : in std_logic;
CLK : in std_logic;
ENC : in std_logic;
NBau... |
-- This module is used for dividing master clock
-- frecuency to required base Bauds frecuency.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRateRD is
port(
RST : in std_logic;
CLK : in std_logic;
ENC : in std_logic;
NBau... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_bb
--
-- Generated
-- by: wig
-- on: Wed Nov 30 13:58:36 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $... |
-- Technology and synthesis options
constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
constant CFG_MEMTECH : integer := CFG_RAM_TECH;
constant CFG_PADTECH : integer := CFG_PAD_TECH;
constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
|
-- Technology and synthesis options
constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
constant CFG_MEMTECH : integer := CFG_RAM_TECH;
constant CFG_PADTECH : integer := CFG_PAD_TECH;
constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
|
-- Technology and synthesis options
constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
constant CFG_MEMTECH : integer := CFG_RAM_TECH;
constant CFG_PADTECH : integer := CFG_PAD_TECH;
constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
|
-- Technology and synthesis options
constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
constant CFG_MEMTECH : integer := CFG_RAM_TECH;
constant CFG_PADTECH : integer := CFG_PAD_TECH;
constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
|
-- NEED RESULT: ARCH00700: Expressions, signal and variable names allowed as actual designator in association list passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
----------------... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_3_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Au... |
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : clk_gen_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
... |
library ieee;
use ieee.std_logic_1164.all;
use work.koc_signal_pack.all;
entity koc_signal_axi4_read_cntrl is
generic (
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := ... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: BuzzerMi.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- =================================... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 22:04:40 2017
-- Host : DarkCube running 64-bit major releas... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
CONTEXT c1;
CONTEXT c2;
CONTEXT c2;
|
-- NEED RESULT: Assertion statement in architecture body
-- NEED RESULT: ARCH00263: Block statements, process_statements, signal assignment statements, component instantiation statements, concurrent procedure call statements and generate statements in architecture statement part passed
-- NEED RESULT: *** Check simul... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: tx_add_preamble - Behavioral
--
-- Description: Add the required 16 nibbles of preamble to the data packet.
--
--------------------------------------------------... |
library IEEE;
use IEEE.std_logic_1164.ALL;
use work.constants.all;
entity right_XLEN_barrel_shifter is
port( i : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic_vector(4 downto 0);
o : out std_logic_vector(XLEN -1 downto 0)
);
end right_XLEN_barrel_shifter;
architecture structural of right... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_A_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 07:51:26 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../case.xls
--
-- !!! Do not edit this file! Autogenerated... |
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of In... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
port (
... |
--!
--! Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Tue Jun 06 02:30:20 2017
--Host : GILAMONSTER running 64-bit major release ... |
-------------------------------------------------------------------------------
-- Title : Modulator
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------... |
-------------------------------------------------------------------------------
-- Title : Modulator
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------... |
library verilog;
use verilog.vl_types.all;
entity drive_analog_io is
port(
parallel_in : in vl_logic_vector(63 downto 0);
serial_out : out vl_logic
);
end drive_analog_io;
|
library verilog;
use verilog.vl_types.all;
entity drive_analog_io is
port(
parallel_in : in vl_logic_vector(63 downto 0);
serial_out : out vl_logic
);
end drive_analog_io;
|
library verilog;
use verilog.vl_types.all;
entity drive_analog_io is
port(
parallel_in : in vl_logic_vector(63 downto 0);
serial_out : out vl_logic
);
end drive_analog_io;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity FloatAdder is
port (
fltIn1 : in std_logic_vector(31 downto 0);
fltIn2 : in std_logic_vector(31 downto 0);
fltOut : out std_logic_vector(31 downto 0));
end FloatAdder;
architectur... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
package mem_pkg is
type mem_in is record
alu_out : word;
rf_we : std_logic;
insn_type : insn_type_t;
rd_addr : std_logic_vector(4 downto 0);
end record mem_in;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
package mem_pkg is
type mem_in is record
alu_out : word;
rf_we : std_logic;
insn_type : insn_type_t;
rd_addr : std_logic_vector(4 downto 0);
end record mem_in;
... |
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2
-- Module Version: 5.7
--/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll_16 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 12.288 -fclkop 196.608 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -rst -fb_mode 1
-- S... |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: KeyToFreqROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =========================... |
----------------------------------------------------------------------------------
--
-- Generate a single SID voice
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sid_voice is port (
clk1M : in ... |
----------------------------------------------------------------------------------
-- Company: CPE 233
-- Engineer:
-- -------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functi... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
--------------... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eb_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TxSample is
Port ( Txck : in STD_LOGIC;
Txen : out STD_LOGIC;
Tx0 : o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
use work.testtest_pkg.all; -- Missing
package test2_pkg is
type t_test is protected
procedure test_proc;
end protected;
end package;
package body test2_pkg is
type t_test is protected body
procedure test_proc is
alias a_test_val is test_val.rec_val;
begin
a_test_val := 1;
end ... |
component logo is
port (
a,b,c : in bit_vector(1 downto 0);
x,y : out bit_vector(1 downto 0)
);
end component;
|
component logo is
port (
a,b,c : in bit_vector(1 downto 0);
x,y : out bit_vector(1 downto 0)
);
end component;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versi... |
-- pwm_decoder.vhd
-- Author: Fred
-- Status: Tested and passed
-- Works with 490Hz Arduino PWM
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pwm_decoder is
port (
clock : in std_logic := '0'; -- clock
pwm_in : in std_logic ... |
-- pwm_decoder.vhd
-- Author: Fred
-- Status: Tested and passed
-- Works with 490Hz Arduino PWM
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pwm_decoder is
port (
clock : in std_logic := '0'; -- clock
pwm_in : in std_logic ... |
-- pwm_decoder.vhd
-- Author: Fred
-- Status: Tested and passed
-- Works with 490Hz Arduino PWM
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pwm_decoder is
port (
clock : in std_logic := '0'; -- clock
pwm_in : in std_logic ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:47:55 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
entity hello is
generic (constant l : natural := 8);
port (a : in std_logic_vector (l - 1 downto 0));
end hello;
architecture behav of hello is
signal clk : std_logic;
signal q : std_logic_vector (l - 1 downto 0);
begin
process
begin
clk <= '0';
wait for ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:49 2017
-- Host : KLight-PC running 64-bit major relea... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:49 2017
-- Host : KLight-PC running 64-bit major relea... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--
-- Copyright (C) 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This progr... |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it a... |
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 11:50:14 11/30/2015
-- Design Name:
-- Module Name: Ultrasonic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Descrip... |
library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
package pack_sum_medio is
component eAnd
port(
entrada1_and: in std_logic;
entrada2_and: in std_logic;
salida_and: out std_logic);
end component;
component ... |
library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
package pack_sum_medio is
component eAnd
port(
entrada1_and: in std_logic;
entrada2_and: in std_logic;
salida_and: out std_logic);
end component;
component ... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDET12 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic_vector(11 downto 0);
RISE : out vl_logic_vector(11 downto 0)
);
end F2DSS_ACE_MIS... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDET12 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic_vector(11 downto 0);
RISE : out vl_logic_vector(11 downto 0)
);
end F2DSS_ACE_MIS... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDET12 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic_vector(11 downto 0);
RISE : out vl_logic_vector(11 downto 0)
);
end F2DSS_ACE_MIS... |
package pkg is
procedure say_hello;
end pkg;
package body pkg is
procedure say_hello is
begin
report "Hello";
end say_hello;
end pkg;
|
--
-- Copyright (C) 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This progr... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
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