content stringlengths 1 1.04M ⌀ |
|---|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: Common functions and types
--
-- Authors: Thomas... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: Common functions and types
--
-- Authors: Thomas... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2016
-- Module Name: REGBank
-- Project Name: REGBank
-- Target Devices: Spartan-3E
-- Tool versions: Xili... |
library verilog;
use verilog.vl_types.all;
entity View2_vlg_check_tst is
port(
hex0 : in vl_logic_vector(7 downto 0);
hex1 : in vl_logic_vector(7 downto 0);
Lose : in vl_logic;
Win : in vl_logic;
sampler_rx : i... |
entity test is
type t is range foo'bar;
end;
|
entity repro is
end repro;
architecture behav of repro is
type int_vector is array (natural range <>) of integer;
constant c1 : int_vector (0 to 1) := 12 & 13;
constant c2 : int_vector (0 to 1) := 14 & 15;
constant p : boolean := c1 = c2;
constant p1 : boolean := c1 < c2;
begin
process
begin
case tr... |
entity repro is
end repro;
architecture behav of repro is
type int_vector is array (natural range <>) of integer;
constant c1 : int_vector (0 to 1) := 12 & 13;
constant c2 : int_vector (0 to 1) := 14 & 15;
constant p : boolean := c1 = c2;
constant p1 : boolean := c1 < c2;
begin
process
begin
case tr... |
entity repro is
end repro;
architecture behav of repro is
type int_vector is array (natural range <>) of integer;
constant c1 : int_vector (0 to 1) := 12 & 13;
constant c2 : int_vector (0 to 1) := 14 & 15;
constant p : boolean := c1 = c2;
constant p1 : boolean := c1 < c2;
begin
process
begin
case tr... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:04:02 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end... |
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is begin end block;
BLOCK_LABEL : block (guard_condition) is begin end block;
-- Violations below
BLOCK_LABEL : block is begin end block;
BLOCK_LABEL:block (guard_condition)is begin end block;
end architecture RTL;
|
library verilog;
use verilog.vl_types.all;
entity stripes is
port(
CLOCK_27 : in vl_logic;
TD_CLK27 : in vl_logic;
TD_RESET : out vl_logic;
VGA_R : out vl_logic_vector(9 downto 0);
VGA_G : out vl_logic_vector(9 downto ... |
library verilog;
use verilog.vl_types.all;
entity stripes is
port(
CLOCK_27 : in vl_logic;
TD_CLK27 : in vl_logic;
TD_RESET : out vl_logic;
VGA_R : out vl_logic_vector(9 downto 0);
VGA_G : out vl_logic_vector(9 downto ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
entity rs232 is
generic(
BAUD_RATE : integer := 115200
);
port(
rst : in std_logic;
clk : in std_logic;
rx : in std_logic;
tx... |
library verilog;
use verilog.vl_types.all;
entity generic_cdr is
generic(
reference_clock_frequency: string := "0 ps";
output_clock_frequency: string := "0 ps";
sim_debug_msg : string := "false"
);
port(
extclk : in vl_logic;
ltd : in ... |
library verilog;
use verilog.vl_types.all;
entity generic_cdr is
generic(
reference_clock_frequency: string := "0 ps";
output_clock_frequency: string := "0 ps";
sim_debug_msg : string := "false"
);
port(
extclk : in vl_logic;
ltd : in ... |
library verilog;
use verilog.vl_types.all;
entity generic_cdr is
generic(
reference_clock_frequency: string := "0 ps";
output_clock_frequency: string := "0 ps";
sim_debug_msg : string := "false"
);
port(
extclk : in vl_logic;
ltd : in ... |
library verilog;
use verilog.vl_types.all;
entity generic_cdr is
generic(
reference_clock_frequency: string := "0 ps";
output_clock_frequency: string := "0 ps";
sim_debug_msg : string := "false"
);
port(
extclk : in vl_logic;
ltd : in ... |
library verilog;
use verilog.vl_types.all;
entity generic_cdr is
generic(
reference_clock_frequency: string := "0 ps";
output_clock_frequency: string := "0 ps";
sim_debug_msg : string := "false"
);
port(
extclk : in vl_logic;
ltd : in ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY testP IS
END ENTITY testP;
ARCHITECTURE test of testP IS
TYPE in1_array IS ARRAY( 0 TO 32) OF STD_LOGIC_VECTOR ( 31 DOWNTO 0);
SIGNAL in1_data: in1_array := ( B"000100_00001_00011_00001_00000000000", B"000100_00001_00100_00001_... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_a
--
-- Generated
-- by: wig
-- on: Fri Jul 15 12:55:13 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a.... |
package body foo is
function bar return std_logic is
begin
-- Wait Statement
wait;
wait for 10 ns;
wait until false;
wait on S;
wait until F(S(3)) and (S(l) or S(r));
wait on S(3), S, l, r until F(S(3)) and (S(l) or S(r));
wait on S(3), S, l, r until F(S(3)) and (S(l) or S(r)) for 20 ns;
loop
wait on Clk;
exit whe... |
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:43:50 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- SONAR.VHD (a peripheral module for SCOMP)
-- 2012.06.07
-- This sonar device is based on the summer 2001 project
-- by Clliff Cross, Matt Pinkston, Phap Dinh, and Vu Phan.
-- Interrupt functionality based on the summer 2014 project
-- by Team Twinkies
LIBRARY IEEE;
LIBRARY LPM;
USE IEEE.STD_LOGIC_1164.A... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-------------------------------------------------------------------------------
-- xor18.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xi... |
-------------------------------------------------------------------------------
-- xor18.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xi... |
-------------------------------------------------------------------------------
-- xor18.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xi... |
-------------------------------------------------------------------------------
-- xor18.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xi... |
-------------------------------------------------------------------------------
-- xor18.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xi... |
-------------------------------------------------------------------------------
-- xor18.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xi... |
-------------------------------------------------------------------------------
-- xor18.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xi... |
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] X... |
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] X... |
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] X... |
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] X... |
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] X... |
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] X... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex2_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex2_nov;
architecture behaviour of ex2_nov is
constant s1: std_logic_vector(4 downto 0) := "1111... |
library verilog;
use verilog.vl_types.all;
entity MSS_AHB_F060 is
generic(
ACT_CONFIG : integer := 0;
ACT_FCLK : integer := 0;
ACT_DIE : string := "";
ACT_PKG : string := "";
VECTFILE : string := "test.vec"
);
port(
MSSHAD... |
library verilog;
use verilog.vl_types.all;
entity MSS_AHB_F060 is
generic(
ACT_CONFIG : integer := 0;
ACT_FCLK : integer := 0;
ACT_DIE : string := "";
ACT_PKG : string := "";
VECTFILE : string := "test.vec"
);
port(
MSSHAD... |
library verilog;
use verilog.vl_types.all;
entity MSS_AHB_F060 is
generic(
ACT_CONFIG : integer := 0;
ACT_FCLK : integer := 0;
ACT_DIE : string := "";
ACT_PKG : string := "";
VECTFILE : string := "test.vec"
);
port(
MSSHAD... |
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_never is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- NEED RESULT: ARCH00137.P1: Multi inertial transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00137.P2: Multi inertial transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00137.P3: Multi inertial transactions occurred on signal asg with indexe... |
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Me... |
-- $Id: tb_w11a_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_n4d
-- Description: Configuration for ... |
-- arduinointerface.vhd
--
-- takes 8-bit parallel data and sends frame
-- Frame ends when data value is written with "rxLast" set.
-- connect data to low 4 bits of port
-- connect strb to b4 of port (configured as output)
-- connect RnW to b5 of port (configured as output)
-- to read this peripheral:
-- (assuming s... |
library ieee;
use ieee.std_logic_1164.all;
use work.pkg.all;
entity vhd01 is
port (i1 : std_logic_vector (1 to 1);
o1 : out std_logic_vector (1 to 1));
end vhd01;
architecture behav of vhd01 is
begin
o1 <= i1;
end behav;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ab_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 11:02:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this f... |
entity sub is
generic (
type t; -- OK
INIT : t ); -- OK
end entity;
architecture test of sub is
constant myconst : t := INIT; -- OK
signal mysig : t; -- OK
subtype mysub is t range 1 to 2; -- Error
begin
end architec... |
-------------------------------------------------------------------------------
--! @file cntRtl.vhd
--
--! @brief Terminal Counter
--
--! @details The terminal counter is a synchronous counter configured
--! by several generics.
--
------------------------------------------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.3 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 11:57:09 10/26/2009
-- Design Name:
-- Module Name: EX - Behavioral
-- Project Name: OZ-3
-- Target Devices: Xilinx XC3S500E-4FG320
-- Tool versions:
-... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 11:57:09 10/26/2009
-- Design Name:
-- Module Name: EX - Behavioral
-- Project Name: OZ-3
-- Target Devices: Xilinx XC3S500E-4FG320
-- Tool versions:
-... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_eb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
--... |
----------------------------------------
-- Datapath : IITB - Pipelined - RISC
-- Author : Titto Thomas, Sainath, Anakha
-- Date : 2/4/2015
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LmSmBlock is
port (
clock, reset : in std_logic;
Ir0_8 : in ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity alu8 i... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic);
end component fa1;
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_log... |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic);
end component fa1;
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_log... |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic);
end component fa1;
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_log... |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic);
end component fa1;
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_log... |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic);
end component fa1;
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_log... |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic);
end component fa1;
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_log... |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic);
end component fa1;
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_log... |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic);
end component fa1;
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_log... |
architecture a of b is
begin
-- Wait statements
process is
begin
wait for 1 ns;
block_forever: wait;
wait on x;
wait on x, y, z(1 downto 0);
wait on w(1) for 2 ns;
wait until x = 3;
wait until y = x for 5 ns;
wait on x until x = 2 for 1 ns;
... |
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