content stringlengths 1 1.04M ⌀ |
|---|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity somasub is
port
(
sub : in std_logic;
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
R : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of somasub is
begin
R <= (A - B) w... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:04:07 12/09/2018
-- Design Name:
-- Module Name: top - structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04.03.2016 11:22:26
-- Design Name:
-- Module Name: rem_testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
--##### NOTE:
--##### THIS IS A TEMPLATE. It will be processed by mkbfmsim.py
------------------------------------------------------------------------------
--
-- This vhdl module is a template for creating IP testbenches using the IBM
-- BFM toolkits. It provides a fixed interface to the subsystem testbench.
--
--... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
constant CFG_SPICTRL_SLVREG : integer ... |
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
constant CFG_SPICTRL_SLVREG : integer ... |
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
constant CFG_SPICTRL_SLVREG : integer ... |
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
constant CFG_SPICTRL_SLVREG : integer ... |
----------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or techno... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.all;
entity flip_flop is
port( CK: in std_logic;
RESET: in std_logic;
ENABLE: in std_logic;
D: in std_logic;
Q: out std_logic);
end flip_flop;
architecture BEHAVIORAL of flip_flop is
begin
REGISTER_PROC... |
--
-- Mems testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.MEMs.all;
use FPGALIB.Simul.all;
entity Mems_tb is
end entity Mems_tb;
architecture TestBench o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common.ALL;
entity RAM1_Visitor is
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
DataReady: in std_logic;
WriteData: ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common.ALL;
entity RAM1_Visitor is
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
DataReady: in std_logic;
WriteData: ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm4 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm4;
architecture BEHAVIORAL of dcm... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_counter is
port (
clk_in : in std_logic;
reset : in std_logic;
inc : in std_logic;
bcd : out std_logic_vector(3 downto 0);
clk_out : out std_logic);
end;
architecture behavioral of... |
-------------------------------------------------------------------------------
-- Title : Motor control for DC Motors
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian.greif@rwth-aachen.de>
-- Company : Roboterclub Aachen e... |
-------------------------------------------------------------------------------
-- Title : Motor control for DC Motors
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian.greif@rwth-aachen.de>
-- Company : Roboterclub Aachen e... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: w... |
component unsaved is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
pio_0_external_connection_export : out std_logic_vector(7 downto 0) -- export
);
end component unsa... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.aconvenientpackage.all;
entity sdram_ctrl_de2_tb is
generic(
DATA_WIDTH : Integer := 32;
DQM_WIDTH : Integer := 4;
ROW_WIDTH : Integer := 13;
COLS_WIDTH : Integer := 10;
BANK_WIDTH : Integer := 2;
... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Mon Apr 10 13:17:00 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major... |
library IEEE;
use IEEE.std_logic_1164.all;
entity com5 is
end entity com5;
architecture RTL of com5 is
begin
end architecture RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pixel_processing is
Port ( clk : in STD_LOGIC;
-------------------------------
-- VGA data recovered from HDMI
-------------------------------
in_blank : in std_logic;
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.11.2013 09:58:03
-- Design Name:
-- Module Name: SC0720 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- R... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s208_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(10 downto 0);
output: out std_logic_vector(1 downto 0)
);
end s208_rnd;
architecture behaviour of s208_rnd is
constant s11111111: std_logic_vector(4 downto ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for __COMMON__
--
-- Generated
-- by: lutscher
-- on: Tue Jun 23 10:43:20 2009
-- cmd: /home/lutscher/work/MIX/mix_1.pl a_clk.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Lo... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_typ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package packagegeneric00 is
component toposc00
port(
indivosc: in std_logic_vector ( 3 downto 0 );
oscout: out std_logic;
soscdis: in std_logic;
stmrrst: in std_logic;
ou... |
-- NEED RESULT: ARCH00106.P1: Multi transport transactions occurred on signal asg with slice name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00106: One transport transaction occurred on signal asg with slice name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00106: Old transactions ... |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: rx_fifo.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- =================================... |
library verilog;
use verilog.vl_types.all;
entity core_if is
generic(
CORE_ID : integer := 0
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
oFREE_TLB_FLUSH : out vl_logic;
oIO_IRQ_CONFIG_TABLE_REQ: out vl_logic;
oI... |
----------------------------------------------------------------------------------
-- Company: CPE 233 Productions partnered with Colto Ledstrom
-- Engineer: Various Engineers and Coltron Sundstrom, Nico Ledwith
--
-- Create Date: 20:59:29 02/04/2013
-- Design Name:
-- Module Name: RAT Control Unit
-- Proje... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
entity tbStallGenerator is
end tbStallGenerator;
architecture tb_stall_generator_arch of tbStallGenerator is
constant CWRD_SIZE : integer := C_SYS_CWRD_SIZE;
component StallGenerator i... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.pr_types.all;
USE work.lcd_types.all;
package pattern_constants is
constant PATTERN_SIZE : integer := 16;
constant PATTERN_CLASS_COUNT : integer := 16;
constant PATTERN_TRAINING_COUNT : integer := 16;
constant PATTERN_TRAINING_DATA : std_logic_vector(PATTERN_SIZE * ... |
-- DDRMP controller
constant CFG_DDRMP_EN : integer := CONFIG_DDRMP;
constant CFG_DDRMP_EN2P : integer := CONFIG_DDRMP_EN2P;
constant CFG_DDRMP_NCS : integer := CONFIG_DDRMP_NCS;
constant CFG_DDRMP_NDEV : integer := CONFIG_DDRMP_NDEV;
constant CFG_DDRMP_NBITS : integer := CONFIG_DDRMP_NBITS;... |
-- DDRMP controller
constant CFG_DDRMP_EN : integer := CONFIG_DDRMP;
constant CFG_DDRMP_EN2P : integer := CONFIG_DDRMP_EN2P;
constant CFG_DDRMP_NCS : integer := CONFIG_DDRMP_NCS;
constant CFG_DDRMP_NDEV : integer := CONFIG_DDRMP_NDEV;
constant CFG_DDRMP_NBITS : integer := CONFIG_DDRMP_NBITS;... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 19:26:51 2017
-- Host : GILAMONSTER running 64-bit major rel... |
entity alias7 is
end entity;
architecture test of alias7 is
signal x : bit_vector(7 downto 0);
alias top is x(7);
signal ctr : integer := 0;
begin
process (top) is
begin
if top = '1' then
ctr <= ctr + 1;
end if;
end process;
process is
begin
asser... |
entity alias7 is
end entity;
architecture test of alias7 is
signal x : bit_vector(7 downto 0);
alias top is x(7);
signal ctr : integer := 0;
begin
process (top) is
begin
if top = '1' then
ctr <= ctr + 1;
end if;
end process;
process is
begin
asser... |
entity alias7 is
end entity;
architecture test of alias7 is
signal x : bit_vector(7 downto 0);
alias top is x(7);
signal ctr : integer := 0;
begin
process (top) is
begin
if top = '1' then
ctr <= ctr + 1;
end if;
end process;
process is
begin
asser... |
entity alias7 is
end entity;
architecture test of alias7 is
signal x : bit_vector(7 downto 0);
alias top is x(7);
signal ctr : integer := 0;
begin
process (top) is
begin
if top = '1' then
ctr <= ctr + 1;
end if;
end process;
process is
begin
asser... |
entity alias7 is
end entity;
architecture test of alias7 is
signal x : bit_vector(7 downto 0);
alias top is x(7);
signal ctr : integer := 0;
begin
process (top) is
begin
if top = '1' then
ctr <= ctr + 1;
end if;
end process;
process is
begin
asser... |
use work.pkg.all;
entity tb is
end entity tb;
architecture arch of tb is
begin
process
begin
report integer'image(c_int.get);
wait;
end process;
end arch ;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.tb_package.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
e... |
--------------------------------------------------------------------------------
-- Light8080 simulation test bench.
--------------------------------------------------------------------------------
-- Source for the 8080 program is in asm\@PROGNAME@.asm
------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
entity xor_gate is
generic (
INVERT : boolean
);
port (
a : in std_logic;
b : in std_logic;
q : out std_logic
);
end;
architecture a of xor_gate is
begin
gen: if INVERT generate
q <= not (a xor b);
else generate
q <= a xor b;
end generate;
end;
library iee... |
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Me... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/19/2016 09:18:50 PM
-- Design Name:
-- Module Name: SystemTest - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.snes_lib.all;
entity js_generator is
port (
clk_i : in std_logic;
rst_i : in std_logic;
pause_i : in std_logic;
pc_o : out std_logic_vector(15 downto 0);
js_o : out snes_js_btn_r
);
... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity AdderDemo is
port( SW : in std_logic_vector (7 downto 0);
LEDR : out std_logic_vector(4 downto 0);
KEY : in std_logic);
end AdderDemo;
architecture Shell of AdderDemo is
begin
system_core: entity work.AddSub4(structural2)
port map(a => SW(3 downto... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_out_one_hot_pseudo_with_checkers_top is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_out_one_hot_pseudo_with_checkers_top is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_out_one_hot_pseudo_with_checkers_top is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_MIPS IS
END tb_MIPS;
ARCHITECTURE behavior OF tb_MIPS IS
--Inputs
SIGNAL tb_clk : std_logic := '0';
SIGNAL tb_reset : std_logic := '0';
-- Clock period definitions
CONSTANT clk_period : TIME := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
U1_Test : EN... |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer:
--
-- Create Date: 11:15:42 09/02/2015
-- Design Name:
-- Module Name: SN74LS138 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implmentation of a TTL
-- ... |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | _... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity core is
end core;
architecture BEHAVIOR of core is
component clock is
port(
pulse : out std_logic
);
end component;
component alu is
port(
func : in std_logic_vector(3 downto 0);
busA ... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <suppo... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <suppo... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity pps is
port(
clk : in std_logic;
pps : in std_logic;
pps_count : out std_logic_vector(31 downto 0);
pps_count_stb : out std_logic;
pps_count_ack : in std_logic);
end entity pps;
architecture rtl of pps is
signal count... |
library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library decl... |
library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library decl... |
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
entity muxandcpt is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
i_iters1 : in STD_LOGIC_VECTOR (ITER_RANGE-1... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013, Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gais... |
library ieee;
use ieee.std_logic_textio;
entity tb is
end tb;
|
library ieee;
use ieee.std_logic_textio;
entity tb is
end tb;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:09:46 2017
-- Host : EffulgentTome running 64-bit major r... |
--===========================================================================--
-- --
-- LED Flasher --
-- --
... |
entity const8 is
end entity;
architecture test of const8 is
begin
p1: process is
variable s : string(1 to 12);
begin
s := (1 to 11 => "some string", others => NUL);
wait for 1 ns;
assert s = "some string" & NUL;
s := ("foo", "bar", "baz", others => NUL);
wait f... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity mmio_vga is
port(
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
w... |
----------------------------------------------------------------------------------
-- Company: TU Wien - ECS Group --
-- Engineer: Florian Huemer --
-- ... |
----------------------------------------------------------------------------------
-- Company: TU Wien - ECS Group --
-- Engineer: Florian Huemer --
-- ... |
entity anon01_sub is
port (i : bit_vector (7 downto 0);
o : out bit_vector (7 downto 0));
end anon01_sub;
architecture behav of anon01_sub is
begin
o <= i xor x"a5";
end behav;
entity anon01 is
port (i : bit_vector (6 downto 0);
o : out bit_vector (6 downto 0));
end anon01;
architecture behav o... |
-- This testbench should work unmodified.
library ieee;
use ieee.std_logic_1164.all;
library work;
entity testbench_diviseur is
end entity;
architecture behaviorial of testbench_diviseur is
component diviseur is
port(
ck: in std_logic;
go: in std_logic;
n: in std_logi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
end;
architecture a of ent is
component c is
port (
p : in std_logic_vector(7 downto 0)
);
end component;
begin
inst: component c
port map (
p => x"00"
);
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity divisor is
port(
clock : in std_logic;
zera : in std_logic;
conta : in std_logic;
amostra : out std_logic;
conta4 : out std_logic_vector(1 downto 0);
conta8 : out std_logic_vector(2 downto 0));
end divisor;
architecture structure of di... |
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 17:00:57 11/21/2015
-- Design Name:
-- Module Name: Output_robot - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Descr... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity befunge_alu is
generic(
word_size : integer := 8
);
port(
clk : in std_logic;
reset : in std_logic;
a : in std_logic_vector(word_size-1 downto 0);
b : ... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 31-03-2016
-- Module Name: fitness.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.... |
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_misc.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
--DPU entity
entity DPU is
generic (BitWidth: integer);
port ( Data_in_mem: in std_logic_vector (BitWidth-1 downto 0);
Data_in: in std_logic_vector (Bit... |
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