content stringlengths 1 1.04M ⌀ |
|---|
architecture a of b is
begin
-- Wait statements
process is
begin
wait for 1 ns;
block_forever: wait;
wait on x;
wait on x, y, z(1 downto 0);
wait on w(1) for 2 ns;
wait until x = 3;
wait until y = x for 5 ns;
wait on x until x = 2 for 1 ns;
... |
architecture a of b is
begin
-- Wait statements
process is
begin
wait for 1 ns;
block_forever: wait;
wait on x;
wait on x, y, z(1 downto 0);
wait on w(1) for 2 ns;
wait until x = 3;
wait until y = x for 5 ns;
wait on x until x = 2 for 1 ns;
... |
architecture a of b is
begin
-- Wait statements
process is
begin
wait for 1 ns;
block_forever: wait;
wait on x;
wait on x, y, z(1 downto 0);
wait on w(1) for 2 ns;
wait until x = 3;
wait until y = x for 5 ns;
wait on x until x = 2 for 1 ns;
... |
----------------------------------------------------------------------------------
-- Company: Mike Field <hamster@snap.net.nz>
--
-- Module Name: accumulator - Behavioral
--
-- Description: Accumulate the 'up' and 'down' pulses from a rotary encoder.
--
-------------------------------------------------------------... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std... |
-- file: player/calculate_position.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Calculate current position based on internal register for position and
-- current speed value.
library ieee ;
use ieee.std_logic_1164.all... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: multiplication entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: multiplication entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: multiplication entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity c2n_record is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity c2n_record is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity c2n_record is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp ... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Nov 10 10:29:04 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../genwidth.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
library verilog;
use verilog.vl_types.all;
entity cw3 is
port(
LEDG9 : out vl_logic;
UP : in vl_logic;
clk : in vl_logic;
DOWN : in vl_logic;
bcd0 : out vl_logic_vector(3 downto 0);
bcd1 ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF ... |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF ... |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF ... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integ... |
library verilog;
use verilog.vl_types.all;
entity Projeto2 is
port(
LEDG : out vl_logic_vector(1 downto 1);
SW : in vl_logic_vector(4 downto 1)
);
end Projeto2;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--------------------------------------------------------------------------------
-- Entity: generic_mixer
-- Date:2018-08-02
-- Author: gideon
--
-- Description: Audio mixer
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeri... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
--Date : Sat Apr 15 18:53:53 2017
--Host : work running 64-bit Ubuntu 16.04.2 LTS
--... |
--test bench written by alban bourge @ tima
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_tb is
--fsm state types
type state_t is (Rst,Sig_start,Ack_data,Running,Waitfor,Cp_search,Cp_save,Idle,Rst_uut,Rest_ini0,Rest_ini1,Rest,Stop);
--context descriptor
subtype context_t is std_... |
--test bench written by alban bourge @ tima
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_tb is
--fsm state types
type state_t is (Rst,Sig_start,Ack_data,Running,Waitfor,Cp_search,Cp_save,Idle,Rst_uut,Rest_ini0,Rest_ini1,Rest,Stop);
--context descriptor
subtype context_t is std_... |
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
begin
a <= b;
end block;
-- Violations below
BLOCK_LABEL : block is
begin
a <= b;
end block;
end architecture RTL;
|
--
-- UART receiver
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the Licen... |
--
-- UART receiver
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the Licen... |
--
-- UART receiver
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the Licen... |
-- NEED RESULT: ENT00006: port clause not present in entity header passed
-- NEED RESULT: ENT00006_1: port clause present in entity header passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserve... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : asymmetric_dp_bank_v6.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
-------------------------------------------------------------------------------
--
-- T410 ROM wrapper for lpm_rom.
--
-- $Id: t410_rom-lpm-c.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
---------------------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ecc_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-... |
entity ent is
generic (
config : string := "config0";
bits : bit_vector := "10101" );
end entity;
architecture a of ent is
signal sig : integer;
begin
gen_cfg1 : if config = "config1" generate
bad: sig <= 0;
end generate;
gen_cfg2 : if bits /= "00000" generate
good: sig <= 1;
end gen... |
entity ent is
generic (
config : string := "config0";
bits : bit_vector := "10101" );
end entity;
architecture a of ent is
signal sig : integer;
begin
gen_cfg1 : if config = "config1" generate
bad: sig <= 0;
end generate;
gen_cfg2 : if bits /= "00000" generate
good: sig <= 1;
end gen... |
entity ent is
generic (
config : string := "config0";
bits : bit_vector := "10101" );
end entity;
architecture a of ent is
signal sig : integer;
begin
gen_cfg1 : if config = "config1" generate
bad: sig <= 0;
end generate;
gen_cfg2 : if bits /= "00000" generate
good: sig <= 1;
end gen... |
entity ent is
generic (
config : string := "config0";
bits : bit_vector := "10101" );
end entity;
architecture a of ent is
signal sig : integer;
begin
gen_cfg1 : if config = "config1" generate
bad: sig <= 0;
end generate;
gen_cfg2 : if bits /= "00000" generate
good: sig <= 1;
end gen... |
entity ent is
generic (
config : string := "config0";
bits : bit_vector := "10101" );
end entity;
architecture a of ent is
signal sig : integer;
begin
gen_cfg1 : if config = "config1" generate
bad: sig <= 0;
end generate;
gen_cfg2 : if bits /= "00000" generate
good: sig <= 1;
end gen... |
-- Generation properties:
-- Format : hierarchical
-- Generic mappings : exclude
-- Leaf-level entities : direct binding
-- Regular libraries : use library name
-- View name : include
--
LIBRARY lab7_lib;
CONFIGURATION fetch_struct_config OF fetch IS
FOR struct
FOR ALL ... |
-- Generation properties:
-- Format : hierarchical
-- Generic mappings : exclude
-- Leaf-level entities : direct binding
-- Regular libraries : use library name
-- View name : include
--
LIBRARY lab7_lib;
CONFIGURATION fetch_struct_config OF fetch IS
FOR struct
FOR ALL ... |
when others =>
instrOutput <= X"0000_0000";
end case;
end if;
end process;
end architecture;
|
-- NEED RESULT: ARCH00109.P1: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00109.P2: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00109.P3: Mu... |
--!
--! Copyright (C) 2010 - 2012 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Generic single port RAM with a single read/write port
--! @author Matthias Alles
--! @date 2010/09/28... |
--
-- SineTable.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
--
-- This entity represents a sine wave table which allow to choose one of
-- the normal sine or half sine wave. The table only contains quarter of
-- full wave to reduce hardware re... |
--
-- SineTable.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
--
-- This entity represents a sine wave table which allow to choose one of
-- the normal sine or half sine wave. The table only contains quarter of
-- full wave to reduce hardware re... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-... |
---------------------------------------------------------------------
--
-- File Name: TESTER_pkg.vhd
-- Project: LL FIFO
-- Version: 1.2
-- Date: 2005-06-29
--
-- Company: Xilinx, Inc.
-- Contributors: Wen Ying Wei, Davy Huang
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, ... |
architecture RTL of FIFO is
begin
process
variable var1 : integer := 0;
file file1 : load_file_file open read_mode is load_file_name;
constant con1 : std_logic := '1';
alias alias1 is name;
alias alias1 : subtype_indicator is name;
begin
end process;
-- Violations below... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
--###############################
--# Project Name :
--# File :
--# Project :
--# Engineer :
--# Modification History
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
entity TB_I2CSLAVE_READ is
end TB_I2CSLAVE_READ;
architecture stimulus of TB_I2CSLAVE_READ is
-- COM... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_signed.all; -- never use this library!!!
use ieee.std_logic_misc.all; -- provides or_reduce
use work.core_defs.all;
use work.functions_and_types.all;
entity alu is
port(op1 : in std_logic_vector(data_bits-1 downto 0);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 260/111/136/1
library work;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity iec_processor_io is
generic (
g_mhz : natural := 50);
port (
clock : in std_lo... |
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