content stringlengths 1 1.04M ⌀ |
|---|
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- ... |
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- ... |
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.icap_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity icap is
generic (
g_fpga_type : std_logic_vector(7 downto 0) := X"3A" );
port (
clock : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.icap_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity icap is
generic (
g_fpga_type : std_logic_vector(7 downto 0) := X"3A" );
port (
clock : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.icap_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity icap is
generic (
g_fpga_type : std_logic_vector(7 downto 0) := X"3A" );
port (
clock : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.icap_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity icap is
generic (
g_fpga_type : std_logic_vector(7 downto 0) := X"3A" );
port (
clock : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.icap_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity icap is
generic (
g_fpga_type : std_logic_vector(7 downto 0) := X"3A" );
port (
clock : in std_logic;
... |
entity lut4_test is
end entity;
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
architecture test of lut4_test is
signal i : std_logic_vector(3 downto 0);
signal o : std_logic;
begin
uut: LUT4
generic map (
INIT => X"8001" )
port map (
... |
entity lut4_test is
end entity;
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
architecture test of lut4_test is
signal i : std_logic_vector(3 downto 0);
signal o : std_logic;
begin
uut: LUT4
generic map (
INIT => X"8001" )
port map (
... |
entity lut4_test is
end entity;
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
architecture test of lut4_test is
signal i : std_logic_vector(3 downto 0);
signal o : std_logic;
begin
uut: LUT4
generic map (
INIT => X"8001" )
port map (
... |
entity lut4_test is
end entity;
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
architecture test of lut4_test is
signal i : std_logic_vector(3 downto 0);
signal o : std_logic;
begin
uut: LUT4
generic map (
INIT => X"8001" )
port map (
... |
entity lut4_test is
end entity;
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
architecture test of lut4_test is
signal i : std_logic_vector(3 downto 0);
signal o : std_logic;
begin
uut: LUT4
generic map (
INIT => X"8001" )
port map (
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:56:25 10/19/2014
-- Design Name:
-- Module Name: D:/Documents/Xilinx Projects/multi_cycle_cpu/src/reg_file_tb.vhd
-- Project Name: multi_cycle_cpu
-- Target Device:
-- Tool... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: ... |
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code mu... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:50 2017
-- Host : WK117 running 64-bit major release ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- NEED RESULT: ARCH00683: Allocators with static scalar subtype indication passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------... |
---------------------------------------------------------------------------
--
-- (c) Copyright 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- l... |
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet.... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity keyboard is
port(
CLK : in std_logic;
RESET : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
KEYB_DATA : out std_logic_vector(4 downto 0);
RESET_TICK : ou... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture RTL of FIFO is
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
begin
PROC_1 : process
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- clock_generator_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library clock_generator_0_v4_03_a;
use... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
-- $Id: tb_serport_uart_rx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, eithe... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:08:31 07/07/2016
-- Design Name:
-- Module Name: key2segments - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Re... |
entity array10 is
end entity;
architecture test of array10 is
type int_vec is array (natural range <>) of integer;
type int_vec_ptr is access int_vec;
procedure do_stuff (variable p : inout int_vec_ptr;
variable r : inout integer) is
constant orig : int_vec(1 to p'length) ... |
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLAH16bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CarryIn: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC;
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
SomaResult:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END CLAH16bits;
ARCHITECTURE strc_CLAH16bits of CLAH16bits is
... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
--
-- @file sig_pkg.vhd
-- @date December, 2013
-- @author G. Roggemans <g.roggemans@grog.be>
-- @copyright Copyright (c) GROG [https://grog.be] 2013, All Rights Reserved
--
-- This application is free software: you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public Lice... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity somadornbits is
generic(n: integer := 32);
port(
a, b : in bit_vector(n-1 downto 0);
te : in bit;
s : out bit_vector(n-1 downto 0);
ts : out bit
);
end entity;
architecture estrutura of somadornbits is
signal t: bit_vector(n downto 0);
begin
process(a,b,t,te)
begin
t(0) <= te;
for i in 0 to... |
library verilog;
use verilog.vl_types.all;
entity Controller_vlg_sample_tst is
port(
CLK : in vl_logic;
D7 : in vl_logic;
D711 : in vl_logic;
D2312 : in vl_logic;
Eq : in vl_logic;
Rb ... |
--===========================================================================--
-- --
-- Synthesizable Hardware Breakpoint Trap --
-- --
... |
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:35:46 07/17/2015
-- Design Name:
-- Module Name: C:/Users/rccoder/ALU/Lab3/ctrl_tb.vhd
-- Project Name: Lab3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Tes... |
-- Testbench for Filters H_a1-4(z)
-- Uses a sine sweep as stimuli
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.... |
-- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <n3vu0r@qu1x.org>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 Novem... |
entity 0test is end;
|
library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_0_rsp_demux_001 is
port(
sink_valid : in vl_logic_vector(0 downto 0);
sink_data : in vl_logic_vector(104 downto 0);
sink_channel : in vl_logic_vector(5 downto 0);
sink_startofpacket... |
-- Descp. Generate the table of all the possible pattern
--
-- entity name: g05_possibility_table
--
-- Version 1.0
-- Author: Felix Dube; felix.dube@mail.mcgill.ca & Auguste Lalande; auguste.lalande@mail.mcgill.ca
-- Date: November 2, 2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
us... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_nios2_oci_fifo_wrptr_inc is
port(
ge2_free : in vl_logic;
ge3_free : in vl_logic;
input_tm_cnt : in vl_logic_vector(1 downto 0);
fifo_wrptr_inc : out vl_logic_vector(3 downto 0)
);
e... |
-------------------------------------------------------------------------------
-- axi_vdma_reg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights... |
-------------------------------------------------------------------------------
-- axi_vdma_reg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights... |
-------------------------------------------------------------------------------
-- axi_vdma_reg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights... |
-------------------------------------------------------------------------------
-- axi_vdma_reg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity RF is
Port ( rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
DWR : in STD_LOGIC_VECTOR (31 downto 0);
rs... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gleichmann;
use gleichmann.dac.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity adcdac is
generic (
pindex : integer := 0;
paddr : integer := 0;
... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gleichmann;
use gleichmann.dac.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity adcdac is
generic (
pindex : integer := 0;
paddr : integer := 0;
... |
--------------------------------------------------------------------------------
-- system_xadc_wiz_0_0_family_support.vhd - package
--------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
... |
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
... |
-- multiple1902 <multple1902@gmail.com>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
entity fourstep_tb is
end fourstep_tb;
architecture behav of fourstep_tb is
component fourstep
port (
clk : in std_logic;
step : out std_logic_vector(3 do... |
-------------------------------------------------------------------------------
-- FT2232H Sync FIFO Interface
--
-- This component is designed to interface an FT2232H USB chip with two
-- dual-port FIFOs in first-word-fall-through (zero read latency) mode. The
-- FIFOs are used for buffering and (de)serializing data w... |
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool versions... |
------------------------------------------------------------------------
-- vga_controller_640_60.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- S... |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
end;
architecture a of ent is
function count_ones(vec : std_logic_vector) return natural is
variable temp : natural := 0;
begin
for i in vec'range loop
if vec(i) then
temp := temp + 1;
end if;
... |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
o : out std_logic
);
end;
architecture a of ent is
begin
gen: if false generate
o <= '1';
else generate
o <= '0';
end generate;
end;
|
entity tb_anon01 is
end tb_anon01;
architecture behav of tb_anon01 is
signal i, o : bit_vector(6 downto 0);
begin
dut: entity work.anon01
port map (i, o);
process
begin
i <= b"000_0000";
wait for 1 ns;
assert o = b"010_0101" severity failure;
i <= b"111_1111";
wait for 1 ns;
asser... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 14:40:47 2017
-- Host : EffulgentTome running 64-bit major... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity styr_hot is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(9 downto 0)
);
end styr_hot;
architecture behaviour of styr_hot is
constant st0: std_logic_vector(29 downto 0) := ... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.trfsmparts.all;
use work.trfsmpkg.all;
use work.tb_trfsmpkg.all;
use work.tbfuncs.all;
entity tb_trfsm is
end tb_trfsm;
architecture behavior of tb_trfsm... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mult_pkg is
type mult_state_t is (NOP, DMULSL, DMULSL1, DMULSL2, DMULUL, DMULUL1, DMULUL2, MACL, MACL1, MACL2, MACW, MACW1, MACWS, MACWS1, MULL, MULL1, MULL2, MULSW, MULSW1, MULUW, MULUW1);
type mult_result_op_t is (IDENTITY, SATURATE32, ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity bug7 is
end entity bug7;
architecture x of bug7 is
constant cst : real := 5.5;
signal test : integer;
begin
test <= cst;
end architecture x;
|
entity bug7 is
end entity bug7;
architecture x of bug7 is
constant cst : real := 5.5;
signal test : integer;
begin
test <= cst;
end architecture x;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_splitter_tb is
end entity;
architecture number_splitter_tb_arq of number_splitter_tb is
signal number_in: std_logic_vector(22 downto 0);
signal sign_out: std_logic;
signal exp_out: std_logic_vector(5 downto 0);
signal mant_out: st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_splitter_tb is
end entity;
architecture number_splitter_tb_arq of number_splitter_tb is
signal number_in: std_logic_vector(22 downto 0);
signal sign_out: std_logic;
signal exp_out: std_logic_vector(5 downto 0);
signal mant_out: st... |
-- NEED RESULT: ARCH00479: Choices in an element association of an aggregate may contain several or no choices passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
--------------------... |
entity const1 is
end entity;
architecture test of const1 is
type int_vector is array (integer range <>) of integer;
constant c : int_vector(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable v : int_vector(1 to 2);
variable i : integer;
begin
i := c(3);
assert i = 3... |
entity const1 is
end entity;
architecture test of const1 is
type int_vector is array (integer range <>) of integer;
constant c : int_vector(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable v : int_vector(1 to 2);
variable i : integer;
begin
i := c(3);
assert i = 3... |
entity const1 is
end entity;
architecture test of const1 is
type int_vector is array (integer range <>) of integer;
constant c : int_vector(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable v : int_vector(1 to 2);
variable i : integer;
begin
i := c(3);
assert i = 3... |
entity const1 is
end entity;
architecture test of const1 is
type int_vector is array (integer range <>) of integer;
constant c : int_vector(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable v : int_vector(1 to 2);
variable i : integer;
begin
i := c(3);
assert i = 3... |
entity const1 is
end entity;
architecture test of const1 is
type int_vector is array (integer range <>) of integer;
constant c : int_vector(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable v : int_vector(1 to 2);
variable i : integer;
begin
i := c(3);
assert i = 3... |
-------------------------------------------------------------------------------
--! @file addrDecodeRtl.vhd
--
--! @brief Address Decoder for generating select signal
--
--! @details This address decoder generates a select signal depending on the
--! provided base- and high-addresses by using smaller/greater logic.
--!... |
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