content stringlengths 1 1.04M ⌀ |
|---|
package FIFO_PKG is
procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic);
-- Violations below this line
procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
signal ch : character;
function to_bit (a : in char... |
------------------------------------------------------------------------------
---- ----
---- Text Utils ----
---- ----
----... |
--------------------------------------------------------------------------------
-- Entity: tape_speed_control_tb
-- Date:2016-04-17
-- Author: Gideon
--
-- Description: Testbench
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
PACKAGE PIC_pkg IS
-------------------------------------------------------------------------------
-- Types for the RAM memory
-------------------------------------------------------------------------------
SUBTYPE item_array8_ram IS std_logic_vector (7 downt... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
-------------------------------------------------------------------------------
-- Title : Bus Module for ADC MCP3008
-- Project : Loa
-------------------------------------------------------------------------------
-- Copyright (c) 2012
---------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Bus Module for ADC MCP3008
-- Project : Loa
-------------------------------------------------------------------------------
-- Copyright (c) 2012
---------------------------------------------------------------------------... |
entity ENTITY1 is
generic (
wait_generic : std_logic := '0'
);
port (
wait_port : std_logic := '1'
);
end entity ENTITY1;
architecture ARCH of ENTITY1 is
signal wait_for_something : std_logic;
component ENTITY2 is
generic (
wait_generic : std_logic := '0'
);
port (
wait_p... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 02:59:14 04/10/2009
-- Design Name:
-- Module Name: Comp_7segDecoder - Behavioral
-- Project Name: Seven segment display decoder
-- Target Devices:
-- Tool versi... |
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.alu_types.all;
--
-- Generic n-bit mux with two input vectors and one output vector
--
entity MUX is
generic (
N: integer := NSUMG -- Number of bits
);
port (
A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
SEL: in std_l... |
-- file: clk50m.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer ... |
package vital_timing is
end package;
PACKAGE BODY VITAL_Timing IS
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArray... |
----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer: Prof. Dr. Eng. Rafael Luiz Cancian
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: ... |
-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2010 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- This source file ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Generation properties:
-- Format : flat
-- Generic mappings : exclude
-- Leaf-level entities : direct binding
-- Regular libraries : use work
-- View name : include
--
library work;
configuration r65c02_tc_config of R65C02_TC is
for struct
for all : core
use... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
use work.tl_vector_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity tb_ulpi_host is
end ;
architecture tb of tb_ulpi_host is
signal clock : std_l... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
use work.tl_vector_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity tb_ulpi_host is
end ;
architecture tb of tb_ulpi_host is
signal clock : std_l... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
use work.tl_vector_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity tb_ulpi_host is
end ;
architecture tb of tb_ulpi_host is
signal clock : std_l... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Class: ECE 368 Digital Design
-- Engineer: [Engineer 1]
-- [Engineer 2]
--
-- Create Date: [Date]
-- Module Name: [Module Name]
-- Proj... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:44:37 05/17/2011
-- Design Name:
-- Module Name: spi_loopback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is a simple ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:44:37 05/17/2011
-- Design Name:
-- Module Name: spi_loopback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is a simple ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:44:37 05/17/2011
-- Design Name:
-- Module Name: spi_loopback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is a simple ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:44:37 05/17/2011
-- Design Name:
-- Module Name: spi_loopback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is a simple ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- NEED RESULT: ARCH00483: The expression in an attribute specification may be locally static passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fmc150_pkg.all;
entity fmc150_testbench is
generic(
g_sim : integer := 0
);
port
(
rst : in std_logic;
clk_100Mhz... |
----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: hardware_interface.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEB... |
--
-- \file burst_ram.vhd
--
-- Highly parametrizable local RAM block for hardware threads
--
-- Port A is thread-side, port AX is optional thread-side, port b is osif-side.
-- If configured for two thread-side ports, each port will access one half of
-- the total burst RAM.
--
-- Possible combinations of generics:
--
... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:52:12 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:52:12 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "Core"
-- Project :
-------------------------------------------------------------------------------
-- File : Core_tb.vhd
-- Author : Johann Glaser
-- Company :
-- Created : 2013-12-... |
architecture RTL of FIFO is
begin
process
begin
if (a = '1') then
b <= '0';
end if;
-- Violations below
if (a = '1')then
b <= '0';
end if;
if (a = '1') then
b <= '0';
end if;
end process;
end architecture RTL;
|
--------------------------------------------------------------------------------
-- ion_cpu.vhdl -- MIPS32r2(tm) compatible CPU core
--------------------------------------------------------------------------------
-- project: ION (http://www.opencores.org/project,ion_cpu)
-- author: Jose A. Ruiz (ja_rd@hot... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... |
-------------------------------------------------------------------------------
-- mdm_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library mdm_v2_00_b;
use mdm_v2_00_b.all;
entity ... |
library verilog;
use verilog.vl_types.all;
entity ttn_n_cntr is
port(
clk : in vl_logic;
reset : in vl_logic;
cout : out vl_logic;
modulus : in vl_logic_vector(31 downto 0)
);
end ttn_n_cntr;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_153 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end add_153;
architecture augh of add_153 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_153 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end add_153;
architecture augh of add_153 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_153 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end add_153;
architecture augh of add_153 is
signal carry_inA : std_l... |
------------------------------------------------------------------------------
-- Pull-up and pull-down (on signals and busses)
--
-- Project :
-- File : pull.vhd
-- Author : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/23
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use work.fixed_pkg.all;
entity Fixed_Point_ALU is
port( A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
result : ou... |
architecture RTL of FIFO is
function func1 return integer;
pure function func1 return integer;
impure function func1 return integer;
-- Violations follow
function func1 return integer;
function func1 return integer;
pure function func1 return integer;
pure function func1 return integer;
impu... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Title : Toplevel File of A25 FPGA
-- Project : 1614_CERN_A25
--------------------------------------------------------------------------------
-- File : A25_top.vhd
-- Author : michael.miehling@men.de
-- Org... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity create_opcode is
PORT (
COL_A : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_B : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_D : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_E : IN STD_LOGIC_VECTOR(2 DOWN... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity create_opcode is
PORT (
COL_A : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_B : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_D : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_E : IN STD_LOGIC_VECTOR(2 DOWN... |
-------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of Nios MN design Host part
--
--! @details This is the toplevel of the Nios MN FPGA Host design for the
--! INK DE2-115 Evaluation Board.
--
----------------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.Numeric_std.all;
use work.HammingPack16.all;
use work.PhoenixPackage.all;
entity HAM_DEC is
port
(
data_in : in regflit; -- data input
parity_in : in reghamm; -- parity input
data_out : out regflit; -- dat... |
----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Armin FALTINGER
--
-- Create Date: 10:21:09 12/25/2009
-- Module Name: ErrorBit - RTL
-- Project Name: Uart
-- Description: Indicate possible errors,
-- clearing the error wi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:26:00 2017
-- Host : DarkCube running 64-bit major re... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
port (
clk : in std_logic;
rst : in std_logic;
write : in std_logic;
address_read : in integer;
address_write : in integer;
write_data : in std_logic_vector(11 dow... |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: modulo100Hz.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms... |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: modulo1KHz.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the... |
-------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR for Xilinx
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are... |
-------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR for Xilinx
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity KeyboardMapper is
port (Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
PS2Busy : in STD_LOGIC;
PS2Error : in STD_LOGIC;
DataReady : in STD_LOGIC;
DataByte : in STD_LOGIC_VECTOR... |
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library BananaCore;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
package Instruction is
-- Represents a instruction by name
type InstructionCode... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
--Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.1 (lin64) Build 1846317 Fri Apr 14 18:54:47 MDT 2017
--Date : Mon May 15 23:35:17 2017
--Host : beta running 64-bit Arch Linux
--Command ... |
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-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
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-- pf_dpram_select.vhd
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