content stringlengths 1 1.04M ⌀ |
|---|
entity open_bot is
port (
i : in integer;
o : out integer;
v : out bit_vector(3 downto 0) := X"f" );
end entity;
architecture test of open_bot is
begin
v(1) <= '0';
process (i) is
begin
o <= i + 1;
end process;
end architecture;
----------------------------------... |
entity open_bot is
port (
i : in integer;
o : out integer;
v : out bit_vector(3 downto 0) := X"f" );
end entity;
architecture test of open_bot is
begin
v(1) <= '0';
process (i) is
begin
o <= i + 1;
end process;
end architecture;
----------------------------------... |
entity open_bot is
port (
i : in integer;
o : out integer;
v : out bit_vector(3 downto 0) := X"f" );
end entity;
architecture test of open_bot is
begin
v(1) <= '0';
process (i) is
begin
o <= i + 1;
end process;
end architecture;
----------------------------------... |
entity open_bot is
port (
i : in integer;
o : out integer;
v : out bit_vector(3 downto 0) := X"f" );
end entity;
architecture test of open_bot is
begin
v(1) <= '0';
process (i) is
begin
o <= i + 1;
end process;
end architecture;
----------------------------------... |
entity open_bot is
port (
i : in integer;
o : out integer;
v : out bit_vector(3 downto 0) := X"f" );
end entity;
architecture test of open_bot is
begin
v(1) <= '0';
process (i) is
begin
o <= i + 1;
end process;
end architecture;
----------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.rtl_pack.all;
entity fifo is
generic (
depth_order_g : positive;
data_width_g : positive;
prefill_g : natural := 0);
port (
a_reset_i : in std_ulogic := '0';
a_clock_i : in std_ulogic;
a_full_o : out std_ulogic;
a_write_i : in std_ulogi... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This... |
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Found... |
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Found... |
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Found... |
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Found... |
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Found... |
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Found... |
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Found... |
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Found... |
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Found... |
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Found... |
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Found... |
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Found... |
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Found... |
entity wait3 is
end entity;
architecture test of wait3 is
signal x, y : bit;
begin
proc_a: process is
begin
wait for 1 ns;
x <= '1';
wait for 1 ns;
assert y = '1';
wait;
end process;
proc_b: process is
begin
wait on x;
assert x = '1';
... |
entity wait3 is
end entity;
architecture test of wait3 is
signal x, y : bit;
begin
proc_a: process is
begin
wait for 1 ns;
x <= '1';
wait for 1 ns;
assert y = '1';
wait;
end process;
proc_b: process is
begin
wait on x;
assert x = '1';
... |
entity wait3 is
end entity;
architecture test of wait3 is
signal x, y : bit;
begin
proc_a: process is
begin
wait for 1 ns;
x <= '1';
wait for 1 ns;
assert y = '1';
wait;
end process;
proc_b: process is
begin
wait on x;
assert x = '1';
... |
entity wait3 is
end entity;
architecture test of wait3 is
signal x, y : bit;
begin
proc_a: process is
begin
wait for 1 ns;
x <= '1';
wait for 1 ns;
assert y = '1';
wait;
end process;
proc_b: process is
begin
wait on x;
assert x = '1';
... |
entity wait3 is
end entity;
architecture test of wait3 is
signal x, y : bit;
begin
proc_a: process is
begin
wait for 1 ns;
x <= '1';
wait for 1 ns;
assert y = '1';
wait;
end process;
proc_b: process is
begin
wait on x;
assert x = '1';
... |
-- NEED RESULT: ARCH00574: Can declare entities with same name as entities declared in a use'd pkg passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
--------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity luz_cpu_tb is end;
architecture luz_cpu_tb_arc of luz_cpu_tb is
constant RESET_ADDRESS: word := x"00000000";
signal clk: std_logic := '0';
signal reset_n: std_logic;
sig... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity luz_cpu_tb is end;
architecture luz_cpu_tb_arc of luz_cpu_tb is
constant RESET_ADDRESS: word := x"00000000";
signal clk: std_logic := '0';
signal reset_n: std_logic;
sig... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nfa_forward_buckets_if_async_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk_w : in std_logic;
clk_r : in std_logic;
... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 12;
constant AMPL_WIDTH : integer := 12;
type lut_type is arr... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 12;
constant AMPL_WIDTH : integer := 12;
type lut_type is arr... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Tue Aug 2 21:54:54 2016
--Host : andrewandrepowell2-desktop running 64-bit... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity <<ENTITY_NAME>> is
port (<<IN_P>>: in <<type>>; <<OUT_P>>: out <<type>>);
end <<ENTITY_NAME>>;
architecture <<ARCH_TYPE>> of <<ENTITY_NAME>> is
<<DECL_COMPONENTS>>
<<DECL_SIGNALS>>
begin
-- Comman... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity <<ENTITY_NAME>> is
port (<<IN_P>>: in <<type>>; <<OUT_P>>: out <<type>>);
end <<ENTITY_NAME>>;
architecture <<ARCH_TYPE>> of <<ENTITY_NAME>> is
<<DECL_COMPONENTS>>
<<DECL_SIGNALS>>
begin
-- Comman... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity <<ENTITY_NAME>> is
port (<<IN_P>>: in <<type>>; <<OUT_P>>: out <<type>>);
end <<ENTITY_NAME>>;
architecture <<ARCH_TYPE>> of <<ENTITY_NAME>> is
<<DECL_COMPONENTS>>
<<DECL_SIGNALS>>
begin
-- Comman... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity <<ENTITY_NAME>> is
port (<<IN_P>>: in <<type>>; <<OUT_P>>: out <<type>>);
end <<ENTITY_NAME>>;
architecture <<ARCH_TYPE>> of <<ENTITY_NAME>> is
<<DECL_COMPONENTS>>
<<DECL_SIGNALS>>
begin
-- Comman... |
-------------------------------------------------------------------------------
-- Title : Testbench for serialiser
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
----------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Testbench for serialiser
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
----------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- Title : Testbench for CORDIC module
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_bench.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Creat... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
------------------------------------------------------------------------------
-- matrixmultiplier - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: matrixmultiplier
-- Version: 2.00.a
-- Description: matrix multiplier(VHDL).
-- Date: Wed June 7... |
------------------------------------------------------------------------------
-- matrixmultiplier - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: matrixmultiplier
-- Version: 2.00.a
-- Description: matrix multiplier(VHDL).
-- Date: Wed June 7... |
library verilog;
use verilog.vl_types.all;
entity decode_mmucheck is
port(
iPAGING_ENA : in vl_logic;
iKERNEL_ACCESS : in vl_logic;
iMMU_FLAGS : in vl_logic_vector(13 downto 0);
oIRQ40 : out vl_logic_vector(2 downto 0);
oIRQ41 : out ... |
library ieee;
use ieee.std_logic_1164.all;
entity e1 is
port(
r1: in real;
slv1: in std_logic_vector(7 downto 0);
sl1: in std_logic
);
end;
architecture a of e1 is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
entity e2 is
begin
end;
architecture a of e2 is
constant r2: integer := 10e6;
signal sl... |
library ieee;
use ieee.std_logic_1164.all;
entity e1 is
port(
r1: in real;
slv1: in std_logic_vector(7 downto 0);
sl1: in std_logic
);
end;
architecture a of e1 is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
entity e2 is
begin
end;
architecture a of e2 is
constant r2: integer := 10e6;
signal sl... |
library ieee;
use ieee.std_logic_1164.all;
entity e1 is
port(
r1: in real;
slv1: in std_logic_vector(7 downto 0);
sl1: in std_logic
);
end;
architecture a of e1 is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
entity e2 is
begin
end;
architecture a of e2 is
constant r2: integer := 10e6;
signal sl... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:19:38 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
architecture RTL of FIFO is
attribute coordinate of comp_1:component is (0.0, 17.5);
-- Violations below
attribute coordinate of comp_1:component is (0.0, 17.5);
attribute coordinate of comp_1:component is (0.0, 17.5);
begin
end architecture RTL;
|
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY register_file IS
GENERIC(
register_size: INTEGER := 32 --MIPS register size is 32 bit
);
PORT(
-- ************** Do we need a standard enable input ? *****************
clock: IN STD_... |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
-- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your opt... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (just sws)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/27/2008
--
----------------------------------------------------------
--- EXPECTED RESULT
-- Physical register values changes as follows :
-- 32 => 00000010(h)
-- 33 => 00000020(h)
-- 34 => 00000030(h... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (just sws)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/27/2008
--
----------------------------------------------------------
--- EXPECTED RESULT
-- Physical register values changes as follows :
-- 32 => 00000010(h)
-- 33 => 00000020(h)
-- 34 => 00000030(h... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (just sws)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/27/2008
--
----------------------------------------------------------
--- EXPECTED RESULT
-- Physical register values changes as follows :
-- 32 => 00000010(h)
-- 33 => 00000020(h)
-- 34 => 00000030(h... |
--========================================================================
-- alu.vhd :: PDP-11 16-bit ALU
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use work.my_types.all;
entity ... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:54 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: rx_ll_ufc_datapath_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:54 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: rx_ll_ufc_datapath_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:59:18 06/17/2009
-- Design Name:
-- Module Name: /home/jagron/uark_research/uark_ht_trunk/src/hardware/MyRepository/pcores/plb_cond_vars_v1_00_a/hdl/vhdl//user_logic_tb.vhd
-- Project ... |
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers ... |
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers ... |
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers ... |
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers ... |
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers ... |
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers ... |
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers ... |
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
--------------------------------------------------------------------------------
-- File name: gen_utils.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1996, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
--
-- This program is free software; you can redistr... |
--------------------------------------------------------------------------------
-- File name: gen_utils.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1996, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
--
-- This program is free software; you can redistr... |
--------------------------------------------------------------------------------
-- File name: gen_utils.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1996, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
--
-- This program is free software; you can redistr... |
--------------------------------------------------------------------------------
-- File name: gen_utils.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1996, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
--
-- This program is free software; you can redistr... |
--------------------------------------------------------------------------------
-- File name: gen_utils.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1996, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
--
-- This program is free software; you can redistr... |
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