content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity val1 is
generic(
n:integer:=9
);
port(
NewWord : IN STD_LOGIC_VECTOR(n-1 downto 0); --cadena recien hecha
Clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
GoodWord : OUT STD_LOGIC_VECTOR(n-1 down... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:51:54 10/29/2013
-- Design Name:
-- Module Name: InstructionMemory - Behavioral_InstructionMemory
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:33:48 11/17/2015
-- Design Name:
-- Module Name: Datapath - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:59:22 01/11/2012
-- Design Name:
-- Module Name: F:/repos/cpe-233-test-benches/lab-4-arc/RegisterFileTestBench.vhd
-- Project Name: lab-4-arc
-- Target Device:
-- Tool versions:
-... |
entity tb_dff01 is
end tb_dff01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff01 is
signal clk : std_logic;
signal en1 : std_logic;
signal en2 : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff01
port map (
q => dout,
d => din... |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: BRAM_SYNC_TDP
-- AUTHORS: Jakub Cabal <xcabal05@stud.feec.vutbr.cz>
-- LICENSE: The MIT License, please rea... |
-- Test case from Brian Padalino
--
entity wait22 is end entity ;
architecture arch of wait22 is
procedure generate_clock(signal ena : in boolean ; signal clock : inout bit) is
begin
-- Inspired by UVVM clock_generator procedure
loop
if not ena then
if now /= 0 ps t... |
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
--! Physics Department ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_ent is
-- Interrupt mapping register:
signal iar : unsigned(15 downto 0) := "0000000010010000";
signal ipend : unsigned(3 downto 0) := (others => '0');
signal irq : unsigned(3 downto 0);
si... |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemen... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Assume beginning of LVDS packet occurs at same time as
-- falling edge of I2S_SCLK where WS also falls (or
-- any multiple of exactly 8 bits later than this time).
-- This means that the first packet actually contains the
-- LSB of the la... |
architecture RTL of FIFO is
begin
process
begin
-- These are passing
ret := (
data => (others => '-'),
valid => '0',
sop => '0',
eop => '0',
empty => (others => '0'),
error => (others => '0')
);
-- These are failing
ret := (data => (others => '-'),... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- axi_tpg.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE C... |
-- brdConst_pkg (for Maker Board)
----------------------------------------------------------------------
-- (c) 2019 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
---------------------... |
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- * Redistributions i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clkkey is
port
(
clkkey_port_clk: in std_logic;
clkkey_clk: out std_logic
);
end clkkey;
architecture Behavioral of clkkey is
begin
clkkey_clk <= clkkey_port_clk;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity lfsr_tb is
generic (
LFSR_LENGTH : positive := 8;
DUMP_FILE : string := string'("lfsr_dump.txt"));
end entity;
architecture sim of lfsr_tb is
file dump : text open write_mode is DUMP_FILE;
... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate FOR_LABEL;
IF_LABEL : if a = '1' generate
end generate IF_LABEL;
CASE_LABEL : case data generate
end generate CASE_LABEL;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end generate FOR_LABEL;... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture RTL of FIFO is
begin
process
begin
for_label : for index in 4 to 23 loop
end loop FOR_LABEL;
FOR_LABEL : for index in 4 to 23 loop
end loop FOR_LABEL;
For_label : for index in 4 to 23 loop
end loop FOR_LABEL;
end process;
end;
|
-- file dummy.vhd
package COMPONENTS is
component DUMMY_MODULE
port (I : in bit; O : out bit);
end component;
end package;
entity DUMMY_MODULE is
port (I: in bit; O: out bit);
end entity;
architecture RTL of DUMMY_MODULE is
begin
O <= I;
end architecture;
-- file dummy_top.vhd
library DUMMY;
u... |
-- file dummy.vhd
package COMPONENTS is
component DUMMY_MODULE
port (I : in bit; O : out bit);
end component;
end package;
entity DUMMY_MODULE is
port (I: in bit; O: out bit);
end entity;
architecture RTL of DUMMY_MODULE is
begin
O <= I;
end architecture;
-- file dummy_top.vhd
library DUMMY;
u... |
-- file dummy.vhd
package COMPONENTS is
component DUMMY_MODULE
port (I : in bit; O : out bit);
end component;
end package;
entity DUMMY_MODULE is
port (I: in bit; O: out bit);
end entity;
architecture RTL of DUMMY_MODULE is
begin
O <= I;
end architecture;
-- file dummy_top.vhd
library DUMMY;
u... |
-- file dummy.vhd
package COMPONENTS is
component DUMMY_MODULE
port (I : in bit; O : out bit);
end component;
end package;
entity DUMMY_MODULE is
port (I: in bit; O: out bit);
end entity;
architecture RTL of DUMMY_MODULE is
begin
O <= I;
end architecture;
-- file dummy_top.vhd
library DUMMY;
u... |
-- file dummy.vhd
package COMPONENTS is
component DUMMY_MODULE
port (I : in bit; O : out bit);
end component;
end package;
entity DUMMY_MODULE is
port (I: in bit; O: out bit);
end entity;
architecture RTL of DUMMY_MODULE is
begin
O <= I;
end architecture;
-- file dummy_top.vhd
library DUMMY;
u... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity interpolate is
generic(
interpolation_factor : integer := 8192;
output_width : integer := 24;
width : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width - 1 dow... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity interpolate is
generic(
interpolation_factor : integer := 8192;
output_width : integer := 24;
width : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width - 1 dow... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity interpolate is
generic(
interpolation_factor : integer := 8192;
output_width : integer := 24;
width : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width - 1 dow... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 31-05-2016
-- Module Name: main.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cpld_bridge_tb is
end;
architecture bench of cpld_bridge_tb is
signal cfg_act : std_logic := '0';
signal cfg_clk : std_logic := '0';
signal cfg_err : std_logic := '0';
signal cfg_rdy : std_logic := '0';
signal cfgd : std_logic_vect... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity h264_deblock_filter_core is
port(
clk : in std_logic;
rst : in std_logic;
is_chroma : in std_logic;
boundary_strength : in signed(8 downto 0);
p0 ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity h264_deblock_filter_core is
port(
clk : in std_logic;
rst : in std_logic;
is_chroma : in std_logic;
boundary_strength : in signed(8 downto 0);
p0 ... |
-- File name: bus_test.vhd
-- Created: 2009-02-25
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: block for testing bus stuff
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bus_test is
port (
clk : in std_logic... |
-- megafunction wizard: %LPM_ROM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =================================... |
-------------------------------------------------------------------------------
-- $Id: pf_adder.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_adder - entity/architecture pair
---------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_adder.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_adder - entity/architecture pair
---------------------------------------------------------... |
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- nbits_register.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the... |
entity record2 is
end entity;
architecture test of record2 is
type rec is record
x, y : integer;
end record;
procedure set_to(variable r : inout rec;
constant n : in integer) is
begin
r.x := n;
r.y := r.x;
end procedure;
begin
process is
... |
entity record2 is
end entity;
architecture test of record2 is
type rec is record
x, y : integer;
end record;
procedure set_to(variable r : inout rec;
constant n : in integer) is
begin
r.x := n;
r.y := r.x;
end procedure;
begin
process is
... |
entity record2 is
end entity;
architecture test of record2 is
type rec is record
x, y : integer;
end record;
procedure set_to(variable r : inout rec;
constant n : in integer) is
begin
r.x := n;
r.y := r.x;
end procedure;
begin
process is
... |
entity record2 is
end entity;
architecture test of record2 is
type rec is record
x, y : integer;
end record;
procedure set_to(variable r : inout rec;
constant n : in integer) is
begin
r.x := n;
r.y := r.x;
end procedure;
begin
process is
... |
entity record2 is
end entity;
architecture test of record2 is
type rec is record
x, y : integer;
end record;
procedure set_to(variable r : inout rec;
constant n : in integer) is
begin
r.x := n;
r.y := r.x;
end procedure;
begin
process is
... |
library ieee;
library work;
library altera;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.altera_pll_top_pkg.all;
use altera.altera_syn_attributes.all;
entity hardheat_top is
generic
(
-- Number of bits in time-to-digital converter
TDC_N : positive := 12;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity prime is
port(
-- 32-bit input signal to test.
-- Should be registered in the circuit.
number: in std_logic_vector(31 downto 0);
-- Asynchronous reset when equal to '1'.
reset: in std_logic;... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library verilog;
use verilog.vl_types.all;
entity lab50_vlg_check_tst is
port(
led1 : in vl_logic_vector(7 downto 0);
led2 : in vl_logic_vector(7 downto 0);
lose : in vl_logic;
win : in vl_logic;
sampler_rx : i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:07:57 10/06/2010
-- Design Name:
-- Module Name: Cont0a23 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:07:57 10/06/2010
-- Design Name:
-- Module Name: Cont0a23 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:07:57 10/06/2010
-- Design Name:
-- Module Name: Cont0a23 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:07:57 10/06/2010
-- Design Name:
-- Module Name: Cont0a23 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
var... |
-- NEED RESULT: ARCH00331: Component instantiated with no port or generic clause passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
--------------------------------------------------... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:02:12 09/08/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/Temp/P07_BinaryGray_Converter_Loops/BinaryGray_Converter_tb.vhd
-- Project Name: P07_BinaryGray_Converter_Loops
-- Ta... |
library verilog;
use verilog.vl_types.all;
entity alt_cal is
generic(
number_of_channels: integer := 1;
channel_address_width: integer := 1;
sim_model_mode : string := "TRUE";
lpm_type : string := "alt_cal";
lpm_hint : string := "UNUSED"
);
port(
... |
---------------------------------------------------------------------
-- Divider
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Based on the NRD (Non Restoring Division) algorithm. Takes
-- 36 cycles to calculate quotient (37 for remainder).
---------------------------------------------... |
library verilog;
use verilog.vl_types.all;
entity bus_slave_mux is
port(
s0_cs_n : in vl_logic;
s0_rd_data : in vl_logic_vector(31 downto 0);
s0_rdy_n : in vl_logic;
s1_cs_n : in vl_logic;
s1_rd_data : in vl_logic_vector(31... |
-------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptograp... |
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