content stringlengths 1 1.04M ⌀ |
|---|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- $Id: simlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2,... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ExtIntr_tb is
end ExtIntr_tb;
architecture behavior of ExtIntr_tb is
component ExtIntr
port (
ExtIntrOut_o : out std_logic;
ExtIntrIn_i : in std_logic
);
end component;
signal ExtIntrOut_o : std_logic;
signal Ext... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major relea... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
-------------------------------------------------------------------------------
--axi_vdma_blkmem.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2013 Xilinx, Inc. All rights re... |
-------------------------------------------------------------------------------
--axi_vdma_blkmem.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2013 Xilinx, Inc. All rights re... |
-------------------------------------------------------------------------------
--axi_vdma_blkmem.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2013 Xilinx, Inc. All rights re... |
-------------------------------------------------------------------------------
--axi_vdma_blkmem.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2013 Xilinx, Inc. All rights re... |
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant1.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- =========================... |
entity file10 is
end entity;
architecture test of file10 is
type rec is record
x : integer;
s : string(1 to 5);
end record;
type rec_array is array (natural range <>) of rec;
type rf is file of rec_array;
begin
p1: process is
file f : rf;
variable v : rec_array(1 ... |
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Wishbone DMA Streaming Interface
---------------------------------------------------------------------------------------
-- File : xdma_interface_wb.vhd
-- Author : auto-... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
library ieee;
|
library ieee;
library ieee;
|
library ieee;
library ieee;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- system_sws_8bits_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_gpio_v1_01_b;
use axi_gpio_... |
-------------------------------------------------------------------------------
-- system_sws_8bits_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_gpio_v1_01_b;
use axi_gpio_... |
-------------------------------------------------------------------------------
-- system_sws_8bits_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_gpio_v1_01_b;
use axi_gpio_... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
----------------------------------------------------------------------------------------------
--
-- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006
-- Wed Jun 17 2009 00:53:18
--
-- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdr... |
entity simple is
end;
architecture behav of simple is
begin
process
begin
assert false report "Test is running" severity note;
wait; -- Indefinite
end process;
end behav;
|
entity simple is
end;
architecture behav of simple is
begin
process
begin
assert false report "Test is running" severity note;
wait; -- Indefinite
end process;
end behav;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ENTITY counter IS
GENERIC ( WIDTH : integer := 32);
PORT (CLK : IN std_logic;
RST : IN std_logic;
LOAD : IN std_logic;
DATA : IN unsigned(WIDTH-1 DOWNTO 0);
Q : OUT unsigned(WIDTH-1 DOWNTO 0));
END ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity interleaver_tb is
end interleaver_tb;
architecture tb of interleaver_tb is
constant width : positive := 8;
-- interface signals
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal clk_en : std_... |
-- Copyright (C) 2009 OutputLogic.com
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "A... |
-- Copyright (C) 2009 OutputLogic.com
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "A... |
entity tb1 is
package pkg1 is
constant c : natural := 5;
function f return natural;
end pkg1;
end tb1;
architecture behav of tb1 is
begin
assert pkg1.c = 5 severity failure;
assert pkg1.c /= 5 report "value is correct" severity note;
end behav;
|
entity tb1 is
package pkg1 is
constant c : natural := 5;
function f return natural;
end pkg1;
end tb1;
architecture behav of tb1 is
begin
assert pkg1.c = 5 severity failure;
assert pkg1.c /= 5 report "value is correct" severity note;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Multiplier_tb is
end Multiplier_tb;
-------------------------------------------... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use work.CONSTANTS.all;
use work.ROCACHE_PKG.all;
use work.RWCACHE_PKG.all;
use work.alu_types.all;
use work.cu.all;
entity DLX is
port (
-- Inputs
CLK : in std_logic; -- Cl... |
----------------------------------------------------------------------
---- ----
---- iteration_synth.vhd ----
---- ----
---- This file is part of the turbo... |
----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 19:12:14 05/24/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
entity trigger is
po... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ALU IS
PORT (a: IN std_logic_vector(31 DOWNTO 0);
b: IN std_logic_vector(31 DOWNTO 0);
alucontrol: IN bit_vector(2 DOWNTO 0);
zero: OUT bit;
result: OUT std_logic_vector(31 DOWNTO 0));
END ALU;
ARCH... |
architecture ARCH of ENTITY1 is
begin
-- Passing
LABEL : assert boolean report "Something" severity FAILURE;
LABEL : assert boolean
report "Something" severity FAILURE;
LABEL : assert boolean report "Something"
severity FAILURE;
LABEL : assert boolean
report "Something"
severity FAILURE;... |
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: tb_rl-c.vhd,v 1.1 2005/04/10 18:07:26 arniml Exp $
--
-------------------------------------------------------------------------------
configuration tb_rl_behav_c0 of tb_rl is
for behav
for dut_b :... |
-- $Id: rlinktblib.vhd 389 2011-07-07 21:59:00Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versio... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_eaa_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig... |
-- $Id: fx2_2fifoctl_as.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either v... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential ... |
library verilog;
use verilog.vl_types.all;
entity spm is
port(
clk : in vl_logic;
if_spm_addr : in vl_logic_vector(11 downto 0);
if_spm_as_n : in vl_logic;
if_spm_rw : in vl_logic;
if_spm_wr_data : in vl_logic_vector(31 downto 0)... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
architecture RTL of FIFO is
procedure proc1 is begin end procedure proc1;
PROCEDURE PROC1 IS BEGIN END PROCEDURE PROC1;
function func1 return integer is begin End function func1;
begin
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.HammingPack16.all;
use work.NoCPackage.all;
entity HAM_ENC is
port
(
data_in : in regflit; -- data input
data_out : out reghamm -- data output
);
end HAM_ENC;
architecture HAM_ENC of HAM_ENC is
signal P : Std_logic_vector(5 downto 1); --H... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.HammingPack16.all;
use work.NoCPackage.all;
entity HAM_ENC is
port
(
data_in : in regflit; -- data input
data_out : out reghamm -- data output
);
end HAM_ENC;
architecture HAM_ENC of HAM_ENC is
signal P : Std_logic_vector(5 downto 1); --H... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
-------------------------------------------------------------------------------
-- system_v_tc_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library v_tc_v5_01_a;
use v_tc_v5_01_a.all... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.NoCPackage.all;
use work.TablePackage.all;
entity SwitchControl is
generic(
address : regflit := (others=>'0');
ramInit : memory);
port(
clock : in std_logic;
reset : in std_logic;
h : in regNport;
ack_h ... |
-- ALUNOS:
-- Bruno Luiz da Silva
-- Gustavo Fernades
--
--
-- TÍTULO:
-- Controle de entradas
--
--
-- RESUMO:
-- Bloco que envia a sua entrada para um dos registradores desejados dependendo somente dos argumentos dados
--
--
-- ENTRADAS/SAÍDAS (I/O):
-- (I) a: as chaves SW serão conectadas aqui e posteriormente e... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-------------------------------------------------------------------------------
-- Title : Vivado DDS cos lut for SIRIUS 250M
-- Project :
-------------------------------------------------------------------------------
-- File : dds_cos_lut.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- C... |
architecture ARCH of ENTITY is
begin
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief 8-bits memory block with the generic data size parameter.
--! @details This module absolutely similar to the 'infe... |
use work.mwe_pkg.all;
entity ent is
end;
architecture behav of ent is
function f1 (a, b : boolean) return integer is
begin
return 1;
end f1;
procedure p2 (v : bit_vector (3 downto 0)) is
begin
null;
end p2;
subtype byte is bit_vector (7 downto 0);
procedure p3 (a, b : byte) is
begin
nu... |
--
-- PhaseMemory.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org)
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyrigh... |
entity agg6 is
end entity;
architecture test of agg6 is
type int_vec is array (natural range <>) of integer;
type int_vec4x2 is array (1 to 4) of int_vec(1 to 2);
begin
process is
variable a : int_vec4x2;
variable b : int_vec(1 to 8);
begin
b := (1, 2, 3, 4, 5, 6, 7, 8);
... |
entity agg6 is
end entity;
architecture test of agg6 is
type int_vec is array (natural range <>) of integer;
type int_vec4x2 is array (1 to 4) of int_vec(1 to 2);
begin
process is
variable a : int_vec4x2;
variable b : int_vec(1 to 8);
begin
b := (1, 2, 3, 4, 5, 6, 7, 8);
... |
entity agg6 is
end entity;
architecture test of agg6 is
type int_vec is array (natural range <>) of integer;
type int_vec4x2 is array (1 to 4) of int_vec(1 to 2);
begin
process is
variable a : int_vec4x2;
variable b : int_vec(1 to 8);
begin
b := (1, 2, 3, 4, 5, 6, 7, 8);
... |
entity agg6 is
end entity;
architecture test of agg6 is
type int_vec is array (natural range <>) of integer;
type int_vec4x2 is array (1 to 4) of int_vec(1 to 2);
begin
process is
variable a : int_vec4x2;
variable b : int_vec(1 to 8);
begin
b := (1, 2, 3, 4, 5, 6, 7, 8);
... |
entity agg6 is
end entity;
architecture test of agg6 is
type int_vec is array (natural range <>) of integer;
type int_vec4x2 is array (1 to 4) of int_vec(1 to 2);
begin
process is
variable a : int_vec4x2;
variable b : int_vec(1 to 8);
begin
b := (1, 2, 3, 4, 5, 6, 7, 8);
... |
library ieee;
use ieee.std_logic_1164.all;
entity fsm_4s is
port (clk : std_logic;
rst : std_logic;
d : std_logic;
done : out std_logic);
end fsm_4s;
architecture behav of fsm_4s is
type state_t is (S0_1, S1_0, S2_0, S3_1);
signal s : state_t;
begin
process (clk)
begin
if rising_... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:54 12/01/2014
-- Design Name:
-- Module Name: befunge_processor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Depend... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vector_dff_block is
Generic (
WIDTH : positive := 8
);
Port (
D : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (WIDTH-1 downto 0)
... |
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