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// See LICENSE for license details.
#ifndef _RISCV_CSRS_H
#define _RISCV_CSRS_H
#include "common.h"
#include "encoding.h"
// For reg_t:
#include "decode.h"
// For std::unordered_map
#include <unordered_map>
// For std::shared_ptr
#include <memory>
// For std::optional
#include <optional>
// For access_type:
#include "... | spike/riscv/csrs.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.11 | false | false | 35,517 | -1 |
#ifndef _RISCV_ROCC_H
#define _RISCV_ROCC_H
#include "extension.h"
struct rocc_insn_t
{
unsigned opcode : 7;
unsigned rd : 5;
unsigned xs2 : 1;
unsigned xs1 : 1;
unsigned xd : 1;
unsigned rs1 : 5;
unsigned rs2 : 5;
unsigned funct : 7;
};
union rocc_insn_union_t
{
rocc_insn_t r;
insn_t i;
};
clas... | spike/riscv/rocc.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.203 | false | false | 2,453 | -1 |
// See LICENSE for license details.
#include "config.h"
#include "cfg.h"
#include "mmu.h"
#include "decode.h"
#include "encoding.h"
#include "platform.h"
mem_cfg_t::mem_cfg_t(reg_t base, reg_t size) : base(base), size(size)
{
assert(mem_cfg_t::check_if_supported(base, size));
}
bool mem_cfg_t::check_if_supported(r... | spike/riscv/cfg.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.277 | false | false | 2,115 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_CACHE_SIM_H
#define _RISCV_CACHE_SIM_H
#include "memtracer.h"
#include "common.h"
#include <cstring>
#include <string>
#include <map>
#include <cstdint>
class lfsr_t
{
public:
lfsr_t() : reg(1) {}
lfsr_t(const lfsr_t& lfsr) : reg(lfsr.reg) {}
uint32_t next() ... | spike/riscv/cachesim.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.082 | false | false | 3,280 | -1 |
// See LICENSE for license details.
#include "socketif.h"
#ifdef HAVE_BOOST_ASIO
#include <iostream>
socketif_t::socketif_t()
{
try { // create socket server
using boost::asio::ip::tcp;
io_service_ptr = new boost::asio::io_service;
acceptor_ptr = new tcp::acceptor(*io_service_ptr, tcp::endpoint(tcp::v... | spike/riscv/socketif.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.25 | false | false | 2,495 | -1 |
// See LICENSE for license details.
// For std::any_of
#include <algorithm>
#include "csrs.h"
// For processor_t:
#include "processor.h"
#include "mmu.h"
// For get_field():
#include "decode_macros.h"
// For trap_virtual_instruction and trap_illegal_instruction:
#include "trap.h"
// For require():
#include "insn_macr... | spike/riscv/csrs.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.086 | false | false | 96,429 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_PROCESSOR_H
#define _RISCV_PROCESSOR_H
#include "decode.h"
#include "trap.h"
#include "abstract_device.h"
#include <string>
#include <vector>
#include <unordered_map>
#include <map>
#include <cassert>
#include "debug_rom_defines.h"
#include "entropy_source.h"
#include... | spike/riscv/processor.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.109 | false | false | 12,272 | -1 |
// See LICENSE for license details.
#include "arith.h"
#include "processor.h"
#include "extension.h"
#include "common.h"
#include "config.h"
#include "decode_macros.h"
#include "simif.h"
#include "mmu.h"
#include "disasm.h"
#include "platform.h"
#include "vector_unit.h"
#include "debug_defines.h"
#include <cinttypes>
... | spike/riscv/processor.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.12 | false | false | 28,123 | -1 |
// See LICENSE for license details.
#include "config.h"
#include "dtb_discovery.h"
#include "sim.h"
#include "mmu.h"
#include "dts.h"
#include "remote_bitbang.h"
#include "byteorder.h"
#include "platform.h"
#include "libfdt.h"
#include "socketif.h"
#include <fstream>
#include <map>
#include <iostream>
#include <sstrea... | spike/riscv/sim.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.118 | false | false | 17,527 | -1 |
// See LICENSE for license details.
#include "cachesim.h"
#include "common.h"
#include <cstdlib>
#include <iostream>
#include <iomanip>
cache_sim_t::cache_sim_t(size_t _sets, size_t _ways, size_t _linesz, const char* _name)
: sets(_sets), ways(_ways), linesz(_linesz), name(_name), log(false)
{
init();
}
static voi... | spike/riscv/cachesim.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.056 | false | false | 5,438 | -1 |
#ifndef _RISCV_TRIGGERS_H
#define _RISCV_TRIGGERS_H
#include <vector>
#include <optional>
#include "decode.h"
namespace triggers {
typedef enum {
OPERATION_EXECUTE,
OPERATION_STORE,
OPERATION_LOAD,
} operation_t;
typedef enum
{
ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION,
ACTION_DEBUG_MODE =... | spike/riscv/triggers.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.023 | false | false | 10,102 | -1 |
#ifndef JTAG_DTM_H
#define JTAG_DTM_H
#include <stdint.h>
class debug_module_t;
typedef enum {
TEST_LOGIC_RESET,
RUN_TEST_IDLE,
SELECT_DR_SCAN,
CAPTURE_DR,
SHIFT_DR,
EXIT1_DR,
PAUSE_DR,
EXIT2_DR,
UPDATE_DR,
SELECT_IR_SCAN,
CAPTURE_IR,
SHIFT_IR,
EXIT1_IR,
PAUSE_IR,
EXIT2_IR,
UPDATE_IR
... | spike/riscv/jtag_dtm.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.203 | false | false | 1,503 | -1 |
// these overlap c.ld[sp]/c.sd[sp]
DECLARE_OVERLAP_INSN(c_flw, EXT_ZCF)
DECLARE_OVERLAP_INSN(c_flwsp, EXT_ZCF)
DECLARE_OVERLAP_INSN(c_fsw, EXT_ZCF)
DECLARE_OVERLAP_INSN(c_fswsp, EXT_ZCF)
// these overlap c.fsdsp
DECLARE_OVERLAP_INSN(cm_push, EXT_ZCMP)
DECLARE_OVERLAP_INSN(cm_pop, EXT_ZCMP)
DECLARE_OVERLAP_INSN(cm_popr... | spike/riscv/overlap_list.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.077 | false | false | 3,842 | -1 |
#ifndef _RISCV_ABSTRACT_INTERRUPT_CONTROLLER_H
#define _RISCV_ABSTRACT_INTERRUPT_CONTROLLER_H
#include "decode.h"
#include <cstdint>
#include <cstddef>
class abstract_interrupt_controller_t {
public:
virtual void set_interrupt_level(uint32_t interrupt_id, int level) = 0;
virtual ~abstract_interrupt_controller_t(... | spike/riscv/abstract_interrupt_controller.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.545 | false | false | 336 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_VECTOR_UNIT_H
#define _RISCV_VECTOR_UNIT_H
#include <array>
#include <cstdint>
#include "decode.h"
#include "csrs.h"
class processor_t;
enum VRM{
RNU = 0,
RNE,
RDN,
ROD,
INVALID_RM
};
template<uint64_t N>
struct type_usew_t;
template<>
struct type_usew_... | spike/riscv/vector_unit.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.137 | false | false | 7,698 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_ARITH_H
#define _RISCV_ARITH_H
#include <cassert>
#include <cstdint>
#include <climits>
#include <cstddef>
#include <type_traits>
inline uint64_t mulhu(uint64_t a, uint64_t b)
{
uint64_t t;
uint32_t y1, y2, y3;
uint64_t a0 = (uint32_t)a, a1 = a >> 32;
uint64... | spike/riscv/arith.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.088 | false | false | 5,744 | -1 |
#include <sys/time.h>
#include <sstream>
#include "devices.h"
#include "processor.h"
#include "mmu.h"
#include "term.h"
#include "sim.h"
#include "dts.h"
#define UART_QUEUE_SIZE 64
#define UART_RX 0 /* In: Receive buffer */
#define UART_TX 0 /* Out: Transmit buffer */
#define... | spike/riscv/ns16550.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.235 | false | false | 9,974 | -1 |
#include "devices.h"
#include "mmu.h"
#include <stdexcept>
mmio_device_map_t& mmio_device_map()
{
static mmio_device_map_t device_map;
return device_map;
}
static auto empty_device = rom_device_t(std::vector<char>());
bus_t::bus_t()
: bus_t(&empty_device)
{
}
bus_t::bus_t(abstract_device_t* fallback)
: fall... | spike/riscv/devices.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.072 | false | false | 4,849 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_SIM_H
#define _RISCV_SIM_H
#include "cfg.h"
#include "debug_module.h"
#include "devices.h"
#include "common.h"
#include "log_file.h"
#include "processor.h"
#include "simif.h"
#include <fesvr/htif.h>
#include <vector>
#include <map>
#include <unordered_map>
#include ... | spike/riscv/sim.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.233 | false | false | 7,404 | -1 |
// Helper macros to help implement instructions defined as part of
// the RISC-V Zvkned extension (vector AES single round).
#include "insns/aes_common.h"
#include "zvk_ext_macros.h"
#ifndef RISCV_ZVKNED_EXT_MACROS_H_
#define RISCV_ZVKNED_EXT_MACROS_H_
// vaes*.vs instruction constraints:
// - Zvkned is enabled
// ... | spike/riscv/zvkned_ext_macros.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.301 | false | false | 11,126 | -1 |
// See LICENSE for license details.
#include "imsic.h"
#include "processor.h"
#include "arith.h"
#include "sim.h"
class imsic_csr_t : public masked_csr_t {
public:
imsic_csr_t(processor_t* const proc, const reg_t addr, imsic_file_t *imsic_file, const reg_t mask = -1, const reg_t init = 0) : masked_csr_t(proc, addr,... | spike/riscv/imsic.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.077 | false | false | 7,671 | -1 |
// See LICENSE for license details.
#define DECODE_MACRO_USAGE_LOGGED 1
#include "decode_macros.h"
#include "rocc.h"
#include "trap.h"
#include <cstdlib>
#define customX(n) \
static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \
{ \
rocc_t* rocc = static_cast<rocc_t*>(p->get_extension()); \
rocc_insn... | spike/riscv/rocc.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.163 | false | false | 1,214 | -1 |
// See LICENSE for license details.
#include "config.h"
#include "mmu.h"
#include "arith.h"
#include "memif.h"
#include "simif.h"
#include "processor.h"
#include "decode_macros.h"
#include "platform.h"
#include "triggers.h"
#include <cassert>
static reg_t compute_reservation_set_mask(const processor_t *proc) {
reg... | spike/riscv/mmu.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.072 | false | false | 31,109 | -1 |
#ifndef _RISCV_BULKNORMDOT_H
#define _RISCV_BULKNORMDOT_H
#include <cstdint>
#include <vector>
#include "softfloat.h"
struct bulk_norm_out_t {
uint32_t out;
uint8_t flags;
};
template<typename T>
static int int_log2(T n)
{
int res = 0;
while (n >>= 1)
res++;
return res;
}
template<typename T>
static T... | spike/riscv/bulknormdot.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.182 | false | false | 11,797 | -1 |
// Helper macros to help implement instructions defined as part of
// the RISC-V Zvknh[ab] extensions (vector SHA-256/SHA-512 cryptography).
#include "zvk_ext_macros.h"
#ifndef RISCV_ZVKNH_EXT_MACROS_H_
#define RISCV_ZVKNH_EXT_MACROS_H_
// Constraints common to all vsha* instructions, across all VSEW:
// - VSEW is ... | spike/riscv/zvknh_ext_macros.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.624 | false | false | 5,329 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_ZICFISS_H
#define _RISCV_ZICFISS_H
#define xSSE() \
((STATE.prv != PRV_M) && get_field(STATE.menvcfg->read(), MENVCFG_SSE) && \
p->extension_enabled('S') && \
((STATE.v && get_field(STATE.henvcfg->read(), HENVCFG_SSE)) || !STATE.v) && \
(((STATE.prv == PRV_U)... | spike/riscv/zicfiss.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.269 | false | false | 1,103 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_DEBUG_MODULE_H
#define _RISCV_DEBUG_MODULE_H
#include <array>
#include <vector>
#include "abstract_device.h"
class simif_t;
class bus_t;
class processor_t;
struct debug_module_config_t {
// Size of program_buffer in 32-bit words, as exposed to the rest of the
/... | spike/riscv/debug_module.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.174 | false | false | 7,074 | -1 |
#include "decode.h"
#include "common.h"
#include <unordered_map>
#include <vector>
#include <string>
#include <cstdio>
struct opcode {
insn_bits_t match;
insn_bits_t mask;
std::string name;
};
static bool overlaps(const opcode& a, const opcode& b)
{
return (a.mask & b.mask & (a.match ^ b.match)) == 0;
}
int ... | spike/riscv/check-opcode-overlap.t.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.265 | false | false | 2,159 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_ISA_PARSER_H
#define _RISCV_ISA_PARSER_H
#include "decode.h"
#include <bitset>
#include <string>
#include <set>
typedef enum {
// 65('A') ~ 90('Z') is reserved for standard isa in misa
EXT_ZFH = 'Z' + 1,
EXT_ZFHMIN,
EXT_ZBA,
EXT_ZBB,
EXT_ZBC,
EXT_ZBS,
... | spike/riscv/isa_parser.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.049 | false | false | 3,481 | -1 |
// See LICENSE for license details.
#ifndef _MEMTRACER_H
#define _MEMTRACER_H
#include <cstdint>
#include <cstring>
#include <vector>
enum access_type {
LOAD,
STORE,
FETCH,
};
class memtracer_t
{
public:
memtracer_t() {}
virtual ~memtracer_t() {}
virtual bool interested_in_range(uint64_t begin, uint64... | spike/riscv/memtracer.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.143 | false | false | 1,245 | -1 |
// See LICENSE file for license details.
#ifndef DEBUG_ROM_DEFINES_H
#define DEBUG_ROM_DEFINES_H
// These are implementation-specific addresses in the Debug Module
#define DEBUG_ROM_HALTED 0x100
#define DEBUG_ROM_GOING 0x104
#define DEBUG_ROM_RESUMING 0x108
#define DEBUG_ROM_EXCEPTION 0x10C
// Saved hart sta... | spike/riscv/debug_rom_defines.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 1 | false | false | 849 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_DECODE_MACROS_H
#define _RISCV_DECODE_MACROS_H
#include "config.h"
#include "decode.h"
#include "encoding.h"
#include "common.h"
#include "softfloat_types.h"
#include "specialize.h"
// helpful macros, etc
#define MMU (*p->get_mmu())
#define STATE (*p->get_state())
#... | spike/riscv/decode_macros.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.518 | false | false | 14,036 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_SOCKETIF_H
#define _RISCV_SOCKETIF_H
#include "config.h"
#ifdef HAVE_BOOST_ASIO
#include <boost/algorithm/string.hpp>
#include <boost/regex.hpp>
#include <boost/asio.hpp>
class socketif_t
{
public:
socketif_t();
~socketif_t();
std::string rin(std::ostream &... | spike/riscv/socketif.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.458 | false | false | 667 | -1 |
#ifndef RISCV_ZVZIP_MACROS_H_
#define RISCV_ZVZIP_MACROS_H_
#define require_zvzip \
do { \
require_vector(true); \
require_extension(EXT_ZVZIP); \
} while (0)
#define ZVZIP_EXTRACT_V(x, VS2_IDX) \
type_sew_t<x>::type UNUSED &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \
vd = P.VU.elt<type_sew... | spike/riscv/zvzip_ext_macros.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.143 | false | false | 3,493 | -1 |
#ifndef _RISCV_P_EXT_MACROS_H_
#define _RISCV_P_EXT_MACROS_H_
// rd temp
#define WRITE_P_RD() \
rd_tmp = set_field(rd_tmp, make_mask64((i * sizeof(p_rd) * 8), sizeof(p_rd) * 8), p_rd);
// Field
#define P_FIELD(R, INDEX, SIZE) \
(type_sew_t<SIZE>::type)get_field(R, make_mask64(((INDEX) * SIZE), SIZE))
#define P_U... | spike/riscv/p_ext_macros.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.207 | false | false | 23,300 | -1 |
#include "processor.h"
#include "debug_defines.h"
void state_t::add_csr(reg_t addr, const csr_t_p& csr)
{
csrmap[addr] = csr;
}
#define add_const_ext_csr(ext, addr, csr) do { auto csr__ = (csr); if (proc->extension_enabled_const(ext)) { add_csr(addr, csr__); } } while (0)
#define add_ext_csr(ext, addr, csr) do { au... | spike/riscv/csr_init.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.042 | false | false | 37,164 | -1 |
#include <algorithm>
#include <array>
#include <cassert>
#include <iterator>
#include <limits>
#include "decode.h"
#include "simif.h"
#include "devices.h"
#include "debug_module.h"
#include "debug_defines.h"
#include "opcodes.h"
#include "mmu.h"
#include "debug_rom/debug_rom.h"
#include "debug_rom_defines.h"
#if 0
#... | spike/riscv/debug_module.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.052 | false | false | 44,030 | -1 |
// See LICENSE for license details.
#include "config.h"
#include "dts.h"
#include "libfdt.h"
#include "platform.h"
#include <cassert>
#include <iostream>
#include <sstream>
#include <csignal>
#include <unistd.h>
#include <sys/wait.h>
#include <sys/types.h>
std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz... | spike/riscv/dts.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.076 | false | false | 13,150 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_SIMIF_H
#define _RISCV_SIMIF_H
#include <map>
#include "decode.h"
#include "cfg.h"
class processor_t;
class mmu_t;
// this is the interface to the simulator used by the processors and memory
class simif_t
{
public:
// should return NULL for MMIO addresses
virtu... | spike/riscv/simif.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.367 | false | false | 1,254 | -1 |
// Helper macros and functions to help implement instructions defined as part of
// the RISC-V Zvksed extension (vectorized SM4).
#include "insns/sm4_common.h"
#include "zvk_ext_macros.h"
#ifndef RISCV_ZVKSED_MACROS_H_
#define RISCV_ZVKSED_MACROS_H_
// Constraints common to all vsm4* instructions:
// - Zvksed is en... | spike/riscv/zvksed_ext_macros.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.623 | false | false | 2,287 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_V_EXT_MACROS_H
#define _RISCV_V_EXT_MACROS_H
#include "vector_unit.h"
#include "fp_arith.h"
#include "zvbdot.h"
#include <functional>
//
// vector: masking skip helper
//
#define VI_LOOP_ELEMENT_SKIP(BODY) \
if (insn.v_vm() == 0) { \
BODY; \
if (!P.VU.mask... | spike/riscv/v_ext_macros.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.117 | false | false | 66,571 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_DISASM_H
#define _RISCV_DISASM_H
#include "common.h"
#include "decode.h"
#include "isa_parser.h"
#include <string>
#include <sstream>
#include <algorithm>
#include <vector>
extern const char* xpr_name[NXPR];
extern const char* fpr_name[NFPR];
extern const char* vr_n... | spike/riscv/disasm.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.121 | false | false | 2,478 | -1 |
#ifndef _RISCV_DTB_DISCOVERY_H
#define _RISCV_DTB_DISCOVERY_H
#include "sim.h"
#include <vector>
#include <string>
class bus_t;
class abstract_mem_t;
namespace dtb_discovery {
void discover_devices_from_dtb(const void* fdt,
std::vector<device_factory_sargs_t>& factories);
void discov... | spike/riscv/dtb_discovery.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.462 | false | false | 476 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_COPROCESSOR_H
#define _RISCV_COPROCESSOR_H
#include "processor.h"
#include "disasm.h"
#include <vector>
#include <functional>
class extension_t
{
public:
virtual std::vector<insn_desc_t> get_instructions(const processor_t &proc) = 0;
virtual std::vector<disasm_... | spike/riscv/extension.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.31 | false | false | 1,135 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_TRAP_H
#define _RISCV_TRAP_H
#include "decode.h"
#include "encoding.h"
#include <string>
struct state_t;
class trap_debug_mode
{
/* Used to enter debug mode, which isn't quite a normal trap. */
};
class trap_t
{
public:
trap_t(reg_t which) : which(which) {}
... | spike/riscv/trap.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.12 | false | false | 4,128 | -1 |
// See LICENSE for license details.
#include "extension.h"
#include "trap.h"
void extension_t::illegal_instruction([[maybe_unused]] processor_t &proc)
{
throw trap_illegal_instruction(0);
}
void extension_t::raise_interrupt([[maybe_unused]] processor_t &proc)
{
proc.take_interrupt((reg_t)1 << IRQ_COP); // must n... | spike/riscv/extension.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.231 | false | false | 492 | -1 |
#include "encoding.h"
#include <cassert>
#include <cstdint>
#include <limits>
enum Reg : std::uint32_t {
ZERO = 0,
T0 = 5,
S0 = 8,
S1 = 9,
};
// Bit count of the words we splice fields into, not a field width itself.
constexpr unsigned u32_bits = std::numeric_limits<std::uint32_t>::digits;
enum class ... | spike/riscv/opcodes.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.295 | false | false | 8,393 | -1 |
// See LICENSE for license details.
#include "insn_template.h"
#include "insn_macros.h"
#define DECODE_MACRO_USAGE_LOGGED 0
#define PROLOGUE \
reg_t npc = sext_xlen(pc + insn_length(OPCODE)); \
if (!p->extension_enabled(EXT_ZCA)) assume(insn_length(OPCODE) % 4 == 0)
#define EPILOGUE \
trace_opcode(p, OPCODE, ... | spike/riscv/insn_template.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.463 | false | false | 1,805 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_MMU_H
#define _RISCV_MMU_H
#include "bloom_filter.h"
#include "decode.h"
#include "trap.h"
#include "common.h"
#include "simif.h"
#include "processor.h"
#include "memtracer.h"
#include "../fesvr/byteorder.h"
#include "triggers.h"
#include "cfg.h"
#include <algorithm... | spike/riscv/mmu.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.114 | false | false | 21,772 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_DECODE_H
#define _RISCV_DECODE_H
#include "../softfloat/softfloat_types.h"
#include <algorithm>
#include <array>
#include <cstdint>
#include <cstring>
#include <strings.h>
#include <cinttypes>
#include <type_traits>
typedef int64_t sreg_t;
typedef uint64_t reg_t;
ty... | spike/riscv/decode.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.218 | false | false | 7,813 | -1 |
// See LICENSE for license details.
#include "config.h"
#include "processor.h"
#include "mmu.h"
#include "disasm.h"
#include "decode_macros.h"
#include <cassert>
static void commit_log_reset(processor_t* p)
{
p->get_state()->log_reg_write.clear();
p->get_state()->log_mem_read.clear();
p->get_state()->log_mem_wr... | spike/riscv/execute.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.086 | false | false | 10,510 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_PLATFORM_H
#define _RISCV_PLATFORM_H
#define DEFAULT_KERNEL_BOOTARGS "console=ttyS0 earlycon"
#define DEFAULT_RSTVEC 0x00001000
#define DEFAULT_ISA "rv64imafdc_zicntr_zihpm"
#define DEFAULT_PRIV "MSU"
#define CLINT_BASE 0x02000000
#define CLIN... | spike/riscv/platform.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 1 | false | false | 1,147 | -1 |
// See LICENSE for license details.
#include "config.h"
#include "sim.h"
#include "decode.h"
#include "decode_macros.h"
#include "disasm.h"
#include "mmu.h"
#include "vector_unit.h"
#include "socketif.h"
#include <sys/mman.h>
#include <termios.h>
#include <map>
#include <iostream>
#include <iomanip>
#include <climits>... | spike/riscv/interactive.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.084 | false | false | 26,300 | -1 |
#include "dtb_discovery.h"
#include "libfdt.h"
#include "dts.h"
#include <iostream>
#include <sstream>
#include <cstdlib>
namespace {
std::vector<std::string> split_csv(const std::string& str) {
std::vector<std::string> result;
std::stringstream ss(str);
std::string item;
while (std::getline(ss, ite... | spike/riscv/dtb_discovery.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.103 | false | false | 4,476 | -1 |
package vexriscv.demo
import vexriscv.plugin._
import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
import spinal.core._
/**
* Created by spinalvm on 15.06.17.
*/
object GenSmallestNoCsr extends App{
def cpu() = new VexRiscv(
config = VexRiscvConfig(
plugins = List(
// new PcManagerSimplePlugin(
//... | vexriscv/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.115 | false | false | 1,785 | -1 |
package vexriscv.demo
import spinal.core._
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
import vexriscv.plugin._
import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
/**
* Both iBusTc and dBusTc assume
* - 1 cycle read latency
* - read_data stay on the port until the next access
* - writes should on... | vexriscv/src/main/scala/vexriscv/demo/GenFullWithTcm.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.073 | false | false | 2,937 | -1 |
package vexriscv.ip
import vexriscv._
import spinal.core._
import spinal.lib._
import spinal.lib.bus.amba4.axi.{Axi4Config, Axi4Shared}
import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
import spinal.lib.bus.bmb.{Bmb, BmbAccessParameter, BmbCmd, BmbInvalidationParameter, BmbParameter, BmbSourceParameter}
import ... | vexriscv/src/main/scala/vexriscv/ip/DataCache.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.03 | false | false | 45,175 | -1 |
package vexriscv.demo
import spinal.core._
import spinal.lib.cpu.riscv.debug.DebugTransportModuleParameter
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
import vexriscv.plugin._
import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
/**
* This an example of VexRiscv configuration which can run the officia... | vexriscv/src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.244 | false | false | 3,874 | -1 |
/**
* Thanks Efinix for funding the official RISC-V debug implementation on VexRiscv !
*/
package vexriscv.plugin
import spinal.core._
import spinal.lib._
import spinal.lib.com.jtag._
import spinal.lib.cpu.riscv.debug._
import vexriscv._
class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
... | vexriscv/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.064 | false | false | 3,636 | -1 |
package vexriscv.plugin
import vexriscv.{plugin, _}
import vexriscv.ip._
import spinal.core._
import spinal.lib._
import scala.collection.mutable.ArrayBuffer
//class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConfig : Any = null) extends Plugin[VexRiscv] {
// var iBus : InstructionCacheM... | vexriscv/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.038 | false | false | 11,082 | -1 |
package vexriscv.demo
import vexriscv.plugin._
import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
import spinal.core._
/**
* Created by spinalvm on 15.06.17.
*/
object GenMicroNoCsr extends App{
def cpu() = new VexRiscv(
config = VexRiscvConfig(
withMemoryStage = false,
withWriteBackStage = false,... | vexriscv/src/main/scala/vexriscv/demo/GenMicroNoCsr.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.051 | false | false | 1,715 | -1 |
package vexriscv.test
import java.awt.event.{MouseEvent, MouseListener}
import java.awt.{Color, Dimension, Graphics}
import javax.swing.JPanel
abstract class JLedArray(ledCount : Int,ledDiameter : Int = 20, blackThickness : Int = 2) extends JPanel{
def getValue() : BigInt
override def paintComponent(g : Graphics... | vexriscv/src/main/scala/vexriscv/test/Swing.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0 | false | false | 2,018 | -1 |
/*
* Copyright (c) 2020 Samuel Lindemer <samuel.lindemer@ri.se>
*
* SPDX-License-Identifier: MIT
*/
package vexriscv.plugin
import vexriscv.{VexRiscv, _}
import spinal.core._
import spinal.lib._
import scala.collection.mutable.ArrayBuffer
/* Each 32-bit pmpcfg# register contains four 8-bit configuration sections... | vexriscv/src/main/scala/vexriscv/plugin/PmpPlugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.387 | false | false | 9,787 | -1 |
package vexriscv
import spinal.core._
object Riscv{
def misaToInt(values : String) = values.toLowerCase.map(e => 1 << (e-'a')).reduce(_ | _)
def funct7Range = 31 downto 25
def rdRange = 11 downto 7
def funct3Range = 14 downto 12
def rs1Range = 19 downto 15
def rs2Range = 24 downto 20
def rs3Range = 31... | vexriscv/src/main/scala/vexriscv/Riscv.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.009 | false | false | 12,498 | -1 |
package vexriscv.demo
import vexriscv.plugin._
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
import spinal.core._
object GenSecure extends App {
def cpu() = new VexRiscv(
config = VexRiscvConfig(
plugins = List(
new IBusCachedPlugin... | vexriscv/src/main/scala/vexriscv/demo/GenSecure.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0 | false | false | 2,520 | -1 |
package vexriscv
import vexriscv.plugin._
import spinal.core._
import spinal.lib._
import scala.collection.mutable
import scala.collection.mutable.ArrayBuffer
trait PipelineThing[T]
trait Pipeline {
type T <: Pipeline
val plugins = ArrayBuffer[Plugin[T]]()
var stages = ArrayBuffer[Stage]()
var unremovableSt... | vexriscv/src/main/scala/vexriscv/Pipeline.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.046 | false | false | 6,381 | -1 |
package vexriscv.plugin
import spinal.core._
import spinal.lib._
object RvcDecompressor{
def main(args: Array[String]): Unit = {
SpinalVerilog(new Component{
out(Delay((apply(Delay(in Bits(16 bits),2), false, false)),2))
}.setDefinitionName("Decompressor"))
}
def apply(i : Bits, rvf : Boolean, r... | vexriscv/src/main/scala/vexriscv/plugin/Misc.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.127 | false | false | 8,341 | -1 |
package vexriscv.plugin
import spinal.core._
import spinal.lib._
import vexriscv.{VexRiscv, _}
object MulDivIterativePlugin{
object IS_MUL extends Stageable(Bool)
object IS_DIV extends Stageable(Bool)
object IS_REM extends Stageable(Bool)
object IS_RS1_SIGNED extends Stageable(Bool)
object IS_RS2_SIGNED ext... | vexriscv/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.031 | false | false | 8,469 | -1 |
package vexriscv.demo
import spinal.core._
import spinal.lib._
import spinal.lib.bus.amba4.axi.Axi4ReadOnly
import spinal.lib.bus.avalon.AvalonMM
import spinal.lib.com.jtag.Jtag
import spinal.lib.eda.altera.{InterruptReceiverTag, QSysify, ResetEmitterTag}
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
im... | vexriscv/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.132 | false | false | 6,834 | -1 |
package vexriscv.demo
import spinal.core._
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
import vexriscv.plugin._
import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
/**
* Created by spinalvm on 15.06.17.
*/
object GenNoCacheNoMmuMaxPerf extends App{
def cpu() = new VexRiscv(
config = VexRiscvCo... | vexriscv/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.046 | false | false | 2,092 | -1 |
package vexriscv.demo.smp
import spinal.core
import spinal.core._
import spinal.core.sim.{onSimEnd, simSuccess}
import spinal.lib._
import spinal.lib.bus.bmb.sim.BmbMemoryAgent
import spinal.lib.bus.bmb._
import spinal.lib.bus.misc.{DefaultMapping, SizeMapping}
import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig,... | vexriscv/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.502 | false | false | 31,541 | -1 |
package vexriscv.plugin
import spinal.core._
import vexriscv.{VexRiscv, _}
class DummyFencePlugin extends Plugin[VexRiscv]{
override def setup(pipeline: VexRiscv): Unit = {
import Riscv._
import pipeline.config._
val decoderService = pipeline.service(classOf[DecoderService])
decoderService.add(FEN... | vexriscv/src/main/scala/vexriscv/plugin/DummyFencePlugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.059 | false | false | 491 | -1 |
package vexriscv.plugin
import vexriscv._
import spinal.core._
import spinal.lib._
class HazardPessimisticPlugin() extends Plugin[VexRiscv] {
import Riscv._
override def setup(pipeline: VexRiscv): Unit = {
import pipeline.config._
val decoderService = pipeline.service(classOf[DecoderService])
decode... | vexriscv/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0 | false | false | 781 | -1 |
package vexriscv.ip
import vexriscv._
import spinal.core._
import spinal.lib._
import spinal.lib.bus.amba4.axi.{Axi4Config, Axi4ReadOnly}
import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
import spinal.lib.bus.bmb.{Bmb, BmbAccessParameter, BmbParameter, BmbSourceParameter}
import spinal.lib.bus.wishbone.{Address... | vexriscv/src/main/scala/vexriscv/ip/InstructionCache.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.002 | false | false | 17,152 | -1 |
package vexriscv.plugin
import vexriscv.{Pipeline, Stage}
import spinal.core.{Area, Nameable}
/**
* Created by PIC32F_USER on 03/03/2017.
*/
trait Plugin[T <: Pipeline] extends Nameable{
var pipeline : T = null.asInstanceOf[T]
setName(this.getClass.getSimpleName.replace("$",""))
// Used to setup things with ... | vexriscv/src/main/scala/vexriscv/plugin/Plugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.25 | false | false | 763 | -1 |
package vexriscv.ip.fpu
import spinal.core._
import spinal.lib._
object Fpu{
object Function{
val MUL = 0
val ADD = 1
}
}
case class FpuFloatDecoded() extends Bundle{
val isNan = Bool()
val isNormal = Bool()
val isSubnormal = Bool()
val isZero = Bool()
val isInfinity = Bool()
val isQuiet ... | vexriscv/src/main/scala/vexriscv/ip/fpu/Interface.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0 | false | false | 5,361 | -1 |
package vexriscv.plugin
import vexriscv._
import spinal.core._
object IntAluPlugin{
object AluBitwiseCtrlEnum extends SpinalEnum(binarySequential){
val XOR, OR, AND = newElement()
}
object AluCtrlEnum extends SpinalEnum(binarySequential){
val ADD_SUB, SLT_SLTU, BITWISE = newElement()
}
object ALU_BI... | vexriscv/src/main/scala/vexriscv/plugin/IntAluPlugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.012 | false | false | 4,161 | -1 |
package vexriscv.demo
import spinal.core._
import vexriscv.plugin._
import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
/**
* Created by spinalvm on 15.06.17.
*/
object GenCustomSimdAdd extends App{
def cpu() = new VexRiscv(
config = VexRiscvConfig(
plugins = List(
new SimdAddPlugin,
new ... | vexriscv/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.054 | false | false | 1,566 | -1 |
package vexriscv.plugin
import spinal.core._
import spinal.lib._
import vexriscv.{DecoderService, Stageable, VexRiscv}
/**
* The AesPlugin allow to reduce the instruction count of each AES round by providing the following instruction :
* 1) aes_enc_round(rs1, rs2, sel). rd = rs1 ^ quad_mul(sel, sbox(byte_sel... | vexriscv/src/main/scala/vexriscv/plugin/AesPlugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.204 | false | false | 14,832 | -1 |
package vexriscv.demo
import spinal.core._
import vexriscv.plugin.Plugin
import vexriscv.{Stageable, DecoderService, VexRiscv}
//This plugin example will add a new instruction named SIMD_ADD which do the following :
//
//RD : Regfile Destination, RS : Regfile Source
//RD( 7 downto 0) = RS1( 7 downto 0) + RS2( 7 dow... | vexriscv/src/main/scala/vexriscv/demo/CustomInstruction.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.381 | false | false | 3,114 | -1 |
package vexriscv.demo
import vexriscv.plugin._
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
import spinal.core._
/**
* Created by spinalvm on 15.06.17.
*/
object GenFull extends App{
def config = VexRiscvConfig(
plugins = List(
new IBusC... | vexriscv/src/main/scala/vexriscv/demo/GenFull.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.034 | false | false | 2,510 | -1 |
package vexriscv.demo.smp
import spinal.core._
import spinal.core.fiber._
import spinal.lib.bus.bmb._
import spinal.lib.bus.misc.{AddressMapping, DefaultMapping, SizeMapping}
import spinal.lib.bus.wishbone.{WishboneConfig, WishboneToBmbGenerator}
import spinal.lib.generator.GeneratorComponent
import spinal.lib.sim.Spa... | vexriscv/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.108 | false | false | 13,021 | -1 |
package vexriscv.plugin
import vexriscv.{VexRiscv, _}
import spinal.core._
import spinal.lib._
import scala.collection.mutable.ArrayBuffer
case class StaticMemoryTranslatorPort(bus : MemoryTranslatorBus, priority : Int)
class StaticMemoryTranslatorPlugin(ioRange : UInt => Bool) extends Plugin[VexRiscv] with MemoryTr... | vexriscv/src/main/scala/vexriscv/plugin/StaticMemoryTranslatorPlugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0 | false | false | 1,371 | -1 |
package vexriscv
import java.util
import spinal.core._
import spinal.lib._
import scala.beans.BeanProperty
trait JumpService{
def createJumpInterface(stage : Stage, priority : Int = 0) : Flow[UInt] //High priority win
}
trait IBusFetcher{
def haltIt() : Unit
def incoming() : Bool
def pcValid(stage : Stage)... | vexriscv/src/main/scala/vexriscv/Services.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0 | false | false | 3,445 | -1 |
package vexriscv.demo
import spinal.core.SpinalVerilog
import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusSimplePlugin, DecoderSimplePlugin, DivPlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusSimplePlugin, IntAluPlugin, LightShifterPlugin, ... | vexriscv/src/main/scala/vexriscv/demo/GenTwoThreeStage.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0 | false | false | 2,343 | -1 |
package vexriscv.plugin
import vexriscv.{VexRiscv, _}
import spinal.core._
// DivPlugin was by the past a standalone plugin, but now it use the MulDivIterativePlugin implementation
class DivPlugin extends MulDivIterativePlugin(genMul = false, genDiv = true, mulUnrollFactor = 1, divUnrollFactor = 1)
//import spinal.l... | vexriscv/src/main/scala/vexriscv/plugin/DivPlugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.944 | false | false | 2,518 | -1 |
package vexriscv.plugin
import spinal.core._
import spinal.core.internals.{BoolLiteral, Literal}
import spinal.lib._
import spinal.lib.fsm._
import vexriscv._
import vexriscv.Riscv._
import vexriscv.ip.fpu._
import scala.collection.mutable.ArrayBuffer
class FpuAcessPort(val p : FpuParameter) extends Bundle{
val st... | vexriscv/src/main/scala/vexriscv/plugin/FpuPlugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.011 | false | false | 15,204 | -1 |
package vexriscv.plugin
import vexriscv._
import spinal.core._
import spinal.lib._
import vexriscv.Riscv.IMM
import StreamVexPimper._
import scala.collection.mutable.ArrayBuffer
//TODO val killLastStage = jump.pcLoad.valid || decode.arbitration.isRemoved
// DBUSSimple check memory halt execute optimization
abstract... | vexriscv/src/main/scala/vexriscv/plugin/Fetcher.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.047 | false | false | 28,212 | -1 |
package vexriscv.plugin
import vexriscv.{DecoderService, ExceptionCause, ExceptionService, Stage, Stageable, VexRiscv}
import spinal.core._
import spinal.lib._
import spinal.lib.bus.bmb.WeakConnector
import spinal.lib.bus.misc.{AddressMapping, DefaultMapping}
import vexriscv.Riscv.IMM
case class CfuPluginParameter(
... | vexriscv/src/main/scala/vexriscv/plugin/CfuPlugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.058 | false | false | 13,546 | -1 |
package vexriscv.demo
import spinal.core._
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin}
import vexriscv.plugin.{BranchPlugin, CsrAccess, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlug... | vexriscv/src/main/scala/vexriscv/demo/OpenRoad.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.02 | false | false | 3,361 | -1 |
package vexriscv.ip.fpu
import spinal.core._
import spinal.lib._
import spinal.lib.eda.bench.{Bench, Rtl, XilinxStdTargets}
import spinal.lib.math.UnsignedDivider
import scala.collection.mutable.ArrayBuffer
object FpuDivSqrtIterationState extends SpinalEnum{
val IDLE, YY, XYY, Y2_XYY, DIV, _15_XYY2, Y_15_XYY2, Y_1... | vexriscv/src/main/scala/vexriscv/ip/fpu/FpuCore.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.067 | false | false | 70,893 | -1 |
package vexriscv.demo
import vexriscv.plugin._
import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
import spinal.core._
import vexriscv.ip.InstructionCacheConfig
/**
* Created by spinalvm on 15.06.17.
*/
object GenSmallAndProductiveICache extends App{
def cpu() = new VexRiscv(
config = VexRiscvConfig(
pl... | vexriscv/src/main/scala/vexriscv/demo/GenSmallAndProductiveICache.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.044 | false | false | 1,960 | -1 |
package vexriscv.demo
import vexriscv.plugin._
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
import spinal.core._
/**
* Created by spinalvm on 15.06.17.
*/
object GenFullNoMmuNoCacheSimpleMul extends App{
def cpu() = new VexRiscv(
config = VexR... | vexriscv/src/main/scala/vexriscv/demo/GenFullNoMmuNoCacheSimpleMul.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.05 | false | false | 1,800 | -1 |
package vexriscv.plugin
import vexriscv._
import spinal.core._
import spinal.lib.KeepAttribute
class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false, decodeAddSub : Boolean = false) extends Plugin[VexRiscv]{
object SRC2_FORCE_ZERO extends Stageable(Bool)
override def setup(pipel... | vexriscv/src/main/scala/vexriscv/plugin/SrcPlugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.062 | false | false | 2,879 | -1 |
package vexriscv.demo
import vexriscv.plugin._
import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
import spinal.core._
/**
* GenWithMstatush
*
* Demonstrates how to include the MstatushPlugin in a VexRiscv configuration.
*
* This configuration is based on GenSmallest but includes the MstatushPlugin
* to impleme... | vexriscv/src/main/scala/vexriscv/demo/GenWithMstatush.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.239 | false | false | 2,170 | -1 |
package vexriscv.demo
import vexriscv.plugin._
import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
import spinal.core._
/**
* Created by spinalvm on 15.06.17.
*/
object GenSmallest extends App{
def cpu() = new VexRiscv(
config = VexRiscvConfig(
plugins = List(
new IBusSimplePlugin(
rese... | vexriscv/src/main/scala/vexriscv/demo/GenSmallest.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.054 | false | false | 1,583 | -1 |
package vexriscv.demo
import spinal.core._
import vexriscv.plugin._
import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
/**
* Created by spinalvm on 15.06.17.
*/
object GenCustomInterrupt extends App{
def cpu() = new VexRiscv(
config = VexRiscvConfig(
plugins = List(
new CsrPlugin(
CsrP... | vexriscv/src/main/scala/vexriscv/demo/GenCustomInterrupt.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.043 | false | false | 1,903 | -1 |
package vexriscv.demo
import spinal.core._
import spinal.lib._
import spinal.lib.com.jtag.Jtag
import spinal.lib.cpu.riscv.debug.DebugTransportModuleParameter
import spinal.lib.eda.bench._
import spinal.lib.eda.icestorm.IcestormStdTargets
import spinal.lib.eda.xilinx.VivadoFlow
import spinal.lib.io.InOutWrapper
import... | vexriscv/src/main/scala/vexriscv/demo/SynthesisBench.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.088 | false | false | 17,895 | -1 |
package vexriscv
import spinal.core._
import spinal.lib._
import scala.collection.mutable
import scala.collection.mutable.ArrayBuffer
class Stageable[T <: Data](_dataType : => T) extends HardType[T](_dataType) with Nameable{
def dataType = apply()
setWeakName(this.getClass.getSimpleName.replace("$",""))
}
clas... | vexriscv/src/main/scala/vexriscv/Stage.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.016 | false | false | 4,303 | -1 |
package vexriscv.plugin
import vexriscv._
import vexriscv.VexRiscv
import spinal.core._
class MulSimplePlugin extends Plugin[VexRiscv]{
object MUL_OPA extends Stageable(SInt(33 bits))
object MUL_OPB extends Stageable(SInt(33 bits))
object MUL extends Stageable(Bits(64 bits))
object IS_MUL extends Stageab... | vexriscv/src/main/scala/vexriscv/plugin/MulSimplePlugin.scala | arch_code | vexriscv | vexriscv/src/main | MIT | MIT | baf7dc82f855eddaf5b0a20a6802c526f127e38a | other | false | 0.026 | false | false | 2,579 | -1 |
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