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// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.system
import org.chipsalliance.cde.config.Config
import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket.{WithNBigCores, WithNMedCores, WithNSmallCores, WithRV32, WithFP16, WithHype... | rocket-chip/src/main/scala/system/Configs.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.023 | false | false | 4,111 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.regmapper
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.Pow2ClockDivider
object LFSR16Seed
{
def apply(seed: Int): UInt =
{
... | rocket-chip/src/main/scala/regmapper/Test.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.013 | false | false | 8,234 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.log2Ceil
import scala.reflect.ClassTag
/* MuxLiteral creates a lookup table from a key to a list of values.
* Unlike MuxLookup, the table keys must be exclusive literals.
*/
object MuxLiteral
{
def a... | rocket-chip/src/main/scala/util/MuxLiteral.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.157 | false | false | 2,211 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.resources.SimpleDevice
import freechips.rocketchip.tilelink.{TLArbiter, TL... | rocket-chip/src/main/scala/devices/tilelink/Error.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.108 | false | false | 2,640 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.DecoupledIO
import freechips.rocketchip.tile.{TraceBundle}
import freechips.rocketchip.rocket.{TracedInstruction}
import freechips.rocketchip.trace.{TraceCoreInterface, TraceItype}
/** A trait supplying ... | rocket-chip/src/main/scala/util/Blockable.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.052 | false | false | 2,871 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import ... | rocket-chip/src/main/scala/tilelink/Xbar.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.045 | false | false | 16,887 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.TransferSizes
import freechips.rocketchip.tilelink.{TLClientNode, T... | rocket-chip/src/main/scala/devices/debug/DMI.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.304 | false | false | 4,095 | -1 |
// See LICENSE.jtag for license details.
package freechips.rocketchip.jtag
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.property
object JtagState {
sealed abstract class State(val id: Int) {
def U: UInt = id.U(State.width.W)
}
objec... | rocket-chip/src/main/scala/jtag/JtagStateMachine.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.087 | false | false | 5,514 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
object Gather {
// Compress all the valid data to the lowest indices
def apply[T <: Data](data: Seq[ValidIO[T]]): Vec[T] = apply(data, DensePrefixSum)
def apply[T <: Data](data: Seq[ValidIO[T]], ... | rocket-chip/src/main/scala/util/ScatterGather.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.031 | false | false | 4,006 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, R... | rocket-chip/src/main/scala/devices/tilelink/BootROM.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.081 | false | false | 4,655 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
/** A queue that delays elements by a certain cycle count.
*
* @param gen queue element type
* @param entries queue size
*
* @param enq enqueue
* @param d... | rocket-chip/src/main/scala/util/DelayQueue.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.435 | false | false | 3,210 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.unittest
import chisel3._
import org.chipsalliance.cde.config.Parameters
class TestHarness(implicit val p: Parameters) extends Module {
val io = IO(new Bundle { val success = Output(Bool()) })
io.success := Module(new UnitTestSuite).io.finis... | rocket-chip/src/main/scala/unittest/TestHarness.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.125 | false | false | 326 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
// q is the probability to delay a request
class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModu... | rocket-chip/src/main/scala/tilelink/Delayer.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.025 | false | false | 3,439 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.language.implicitConversions
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def un... | rocket-chip/src/main/scala/util/package.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.095 | false | false | 10,933 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.groundtest
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.system.SimAXIMem
class TestHarness(implicit p: Parameters) extends Module {
val io = IO(new Bundle ... | rocket-chip/src/main/scala/groundtest/TestHarness.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.077 | false | false | 494 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.ahb
import chisel3.experimental.SourceInfo
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.BaseNode
import freechips.rocketchip.resources.{Resource, Device, ResourceAddress, Re... | rocket-chip/src/main/scala/amba/ahb/Parameters.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.052 | false | false | 4,489 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{Mux1H, Queue, IrrevocableIO, log2Ceil, UIntToOH}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketch... | rocket-chip/src/main/scala/amba/axi4/Fragmenter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.241 | false | false | 9,920 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.ro... | rocket-chip/src/main/scala/rocket/PMA.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.122 | false | false | 1,660 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortPar... | rocket-chip/src/main/scala/tilelink/Edges.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.047 | false | false | 31,816 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.prci.{ClockCrossingType, NoCrossing, SynchronousCrossing}
import freechips.rocketchip.tilelink.{TLBusWrapper, TLBusWrapperTopo... | rocket-chip/src/main/scala/subsystem/BusTopology.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.231 | false | false | 6,419 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.AMBAProt
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, I... | rocket-chip/src/main/scala/tilelink/Broadcast.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.08 | false | false | 22,281 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronizatio... | rocket-chip/src/main/scala/util/SynchronizerReg.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.161 | false | false | 8,289 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rock... | rocket-chip/src/main/scala/devices/tilelink/MasterMux.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.034 | false | false | 5,516 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3.util.log2Ceil
object AddressDecoder
{
type Port = Seq[AddressSet]
type Ports = Seq[Port]
type Partition = Ports
type Partitions = Seq[Partition]
val addressOrder = Ordering.ordered[AddressSet]
import Orderin... | rocket-chip/src/main/scala/diplomacy/AddressDecoder.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.2 | false | false | 5,901 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
):... | rocket-chip/src/main/scala/util/DescribedSRAM.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.091 | false | false | 545 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up}
import org.chipsalliance.cde.config.Parameters
import freechi... | rocket-chip/src/main/scala/rocket/CSR.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.018 | false | false | 66,954 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.jtag._
import freechips.rocketchip.util.property
case class JtagDTMConfig (
idcodeVersion : Int, // chosen by manu... | rocket-chip/src/main/scala/devices/debug/DebugTransport.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.221 | false | false | 9,754 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, IdRange, TransferSizes}
import freechips.rocketchip.util.Repeater
imp... | rocket-chip/src/main/scala/tilelink/HintHandler.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.105 | false | false | 6,706 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.apb
import chisel3._
import chisel3.util.{Cat, log2Ceil, RegEnable}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.diplomacy.{AddressSet... | rocket-chip/src/main/scala/amba/apb/SRAM.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.019 | false | false | 2,186 | -1 |
// See LICENSE.SiFive for license details.
// !!! HACK TO WORK-AROUND MISSING CHISEL FEATURE
// !!! We need to be inside the chisel3 package to access Builder
package chisel3.shim
import chisel3._
import scala.collection.immutable.SeqMap
class ClonePorts protected[shim](elts: Data*) extends Record
{
val elements... | rocket-chip/src/main/scala/diplomacy/CloneModule.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.273 | false | false | 431 | -1 |
// See LICENSE.SiFive for license details.
// If you know two clocks are related with a N:1 or 1:N relationship, you
// can cross the clock domains with lower latency than an AsyncQueue.
// This clock crossing behaves almost identically to a TLBuffer(2):
// - It adds one cycle latency to each clock domain.
// - Al... | rocket-chip/src/main/scala/tilelink/RationalCrossing.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.056 | false | false | 7,193 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionTyp... | rocket-chip/src/main/scala/tilelink/SRAM.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.165 | false | false | 16,757 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.IdRange
import freechips.rocketchip.util.leftOR
import freechips.rocket... | rocket-chip/src/main/scala/tilelink/SourceShrinker.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.061 | false | false | 3,386 | -1 |
package freechips.rocketchip.prci
import chisel3._
import chisel3.util._
import chisel3.experimental.DoubleParam
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
class ClockSourceIO extends Bundle {
val power = Input(Bool())
val gate = Input(Bool())
val clk = Output(Clock()... | rocket-chip/src/main/scala/prci/TestClockSource.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.038 | false | false | 2,766 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.prci.{HasClockDomainCrossing, HasResetDomainCrossing}
package object interrupts
{
type IntInwardNode = InwardNodeHan... | rocket-chip/src/main/scala/interrupts/package.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.037 | false | false | 1,912 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.ahb
import chisel3._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
class AHBLite()(implicit p: Parameters) extends LazyModule {
val node = AHBMasterAdapterNode(
... | rocket-chip/src/main/scala/amba/ahb/AHBLite.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.028 | false | false | 1,201 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.resources
import chisel3.util.log2Ceil
import scala.collection.immutable.{ListMap, SortedMap}
import scala.collection.mutable.HashMap
import freechips.rocketchip.diplomacy.{AddressSet, AddressRange}
import org.chipsalliance.diplomacy.lazymodule.... | rocket-chip/src/main/scala/resources/Resources.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.159 | false | false | 18,199 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.axi4.{AXI4InwardNode, AXI4OutwardNode}
import freechips.rocketchip.prci.{ClockCrossingType, HasClockDomainCrossing}
... | rocket-chip/src/main/scala/subsystem/CrossingWrapper.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.148 | false | false | 3,755 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.prci.ClockGroupNode
import freechips.rocketchip.tilelink.TLBusWrapper
import freechips.rocketchip.util.{Location, Locatio... | rocket-chip/src/main/scala/subsystem/Attachable.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.383 | false | false | 2,796 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.tilelink.{BuiltInDevices, HasBuiltInDeviceParams, BuiltInErrorDeviceParams, BuiltInZeroDeviceParams}
import freec... | rocket-chip/src/main/scala/subsystem/MemoryBus.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.062 | false | false | 2,236 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.trace
import chisel3._
import chisel3.util._
import scala.math.min
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
case class TraceEncoderParams(
enco... | rocket-chip/src/main/scala/trace/TraceEncoder.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.111 | false | false | 1,122 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.trace
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import fre... | rocket-chip/src/main/scala/trace/TraceEncoderController.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.027 | false | false | 2,604 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import chisel3._
import chisel3.util._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.resources.DTSTimebase
import freechips.rocketchip.devices.tilelink.{CLINTAttachKey, CanHavePeripheryCLINT}
trait HasRT... | rocket-chip/src/main/scala/subsystem/RTC.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.16 | false | false | 1,123 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.experimental.{noPrefix, IntParam}
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.apb.{APBBundle, APBBund... | rocket-chip/src/main/scala/devices/debug/Periphery.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.056 | false | false | 13,465 | -1 |
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.BitPat
import chisel3.util.experimental.decode._
object DecodeLogic
{
// TODO This should be a method on BitPat
private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width
// Pa... | rocket-chip/src/main/scala/rocket/Decode.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.146 | false | false | 2,762 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{IdRange, RegionType, TransferSizes}
import freechips.rocketchip.tilelin... | rocket-chip/src/main/scala/tilelink/CacheCork.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.182 | false | false | 8,372 | -1 |
package freechips.rocketchip.subsystem
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.debug.TLDebugModule
import org.chipsalliance.diplomacy.{DisableMonitors, FlipRendering}
import freechips.rocketchip.i... | rocket-chip/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.3 | false | false | 4,699 | -1 |
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
abstract class Decoding
{
def uncorrected: UInt
def corrected: UInt
def correctable: Bool
def uncorrectable: Bool // If true, correctable should be ignored
d... | rocket-chip/src/main/scala/util/ECC.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.141 | false | false | 8,326 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.ahb
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Parameters, Field}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.nodes.{SimpleNodeImp, RenderedEdge, OutwardNo... | rocket-chip/src/main/scala/amba/ahb/Nodes.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.083 | false | false | 5,050 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{Cat, isPow2, log2Ceil, ReadyValidIO,
log2Up, OHToUInt, Queue, QueueIO, UIntToOH}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyMod... | rocket-chip/src/main/scala/amba/axi4/Deinterleaver.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.194 | false | false | 5,836 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util.property
import chisel3._
import chisel3.experimental.SourceInfo
import chisel3.util.{ReadyValidIO}
sealed abstract class PropertyType(name: String) {
override def toString: String = name
}
object PropertyType {
object Assert extends P... | rocket-chip/src/main/scala/util/Property.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.19 | false | false | 5,167 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.debug.TLDebugModule
import org.chipsalliance.... | rocket-chip/src/main/scala/subsystem/HasTiles.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.291 | false | false | 16,252 | -1 |
package freechips.rocketchip.subsystem
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.debug.TLDebugModule
import freechips.rocketchip.diplomacy.{BufferParams}
import freechips.rocketchip.interrupts.IntXb... | rocket-chip/src/main/scala/subsystem/HierarchicalElement.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.333 | false | false | 3,987 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axis
import chisel3._
import chisel3.util.{Cat, log2Ceil, Mux1H}
import org.chipsalliance.cde.config.{Config, Parameters}
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.tilelink.{TLXba... | rocket-chip/src/main/scala/amba/axis/Xbar.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.151 | false | false | 5,244 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import org.chipsalliance.diplomacy.lazymodule.{LazyScope, LazyModule}
import freechips.rocketchip.diplomacy.{BufferParams}
import freechips.rocketchip.util.{RationalDirection, FastToSlow, AsyncQueueParams, CreditedDelay}
trait CrossingType
... | rocket-chip/src/main/scala/prci/ClockCrossingType.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.062 | false | false | 1,662 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.ahb
import chisel3._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp, SimpleLazyModule}
import freechips.rocketchip.devices.tilelink.TLTestRAM
import freechips.rocket... | rocket-chip/src/main/scala/amba/ahb/Test.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.011 | false | false | 3,844 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.resources
import org.chipsalliance.cde.config.Field
import sys.process._
import java.io.{ByteArrayInputStream, ByteArrayOutputStream}
import freechips.rocketchip.diplomacy.{AddressRange}
case object DTSModel extends Field[String]
case object ... | rocket-chip/src/main/scala/resources/DeviceTree.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.024 | false | false | 6,083 | -1 |
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
class LatencyPipe[T <: Data](typ: T, latency: Int) extends Module {
val io = IO(new Bundle {
val in = Flipped(Decoupled(typ))
val out = Decoupled(typ)
})
def doN[T](n: Int, func: T => ... | rocket-chip/src/main/scala/util/LatencyPipe.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.05 | false | false | 685 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.apb
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Parameters, Field}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.nodes.{SimpleNodeImp,RenderedEdge, InwardNode... | rocket-chip/src/main/scala/amba/apb/Nodes.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.031 | false | false | 2,224 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.resources.{SimpleDevice}
/** Adds a /dev/null slave that does not raise ready for any in... | rocket-chip/src/main/scala/devices/tilelink/Deadlock.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.208 | false | false | 1,011 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDi... | rocket-chip/src/main/scala/tilelink/Nodes.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.027 | false | false | 11,332 | -1 |
// See LICENSE for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.ResetCatchAndSync
/**
* Synchronizes the reset of a diplomatic clock-reset pair to its ac... | rocket-chip/src/main/scala/prci/ResetSynchronizer.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.175 | false | false | 1,471 | -1 |
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
case class RocketCoreVectorParams(
build: Parameters => RocketVectorUnit,
vLen:... | rocket-chip/src/main/scala/rocket/VectorUnit.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0 | false | false | 3,055 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util.{log2Ceil, log2Up}
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.bundlebridge._
import freechips.rocketchip.resources.{PropertyMap, Prope... | rocket-chip/src/main/scala/tile/BaseTile.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.201 | false | false | 17,475 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3.Data
import chisel3.experimental.{SourceInfo, SourceLine}
import org.chipsalliance.cde.config.Parameters
import scala.language.implicitConversions
/** Rocketchip Specific Diplomacy code. All other Diplomacy core functionality has... | rocket-chip/src/main/scala/diplomacy/package.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.037 | false | false | 23,487 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.ro... | rocket-chip/src/main/scala/rocket/TLB.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.341 | false | false | 32,719 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{Queue, IrrevocableIO}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.diplomacy.BufferParams
... | rocket-chip/src/main/scala/amba/axi4/Buffer.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.086 | false | false | 2,665 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.tilelink.{BuiltInErrorDeviceParams, BuiltInZeroDeviceParams, BuiltInDevices, HasBuiltInDeviceParams}
import freec... | rocket-chip/src/main/scala/subsystem/FrontBus.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.033 | false | false | 1,317 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.unittest
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.util._
trait UnitTestIO {
val finished = Output(Bool())
val start = Input(Bool())
}
trait HasUnitTestIO {
val io: UnitTestIO... | rocket-chip/src/main/scala/unittest/UnitTest.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.024 | false | false | 1,557 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.log2Ceil
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String... | rocket-chip/src/main/scala/rocket/Events.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.041 | false | false | 2,946 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.ahb
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.nodes.{MixedAdapterNode}
import org.chipsalliance.diplomacy.lazymodule.... | rocket-chip/src/main/scala/amba/ahb/ToTL.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.109 | false | false | 7,982 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.trace
import chisel3._
// Definitions for Trace core Interface defined in RISC-V Processor Trace Specification V1.0
object TraceItype extends ChiselEnum {
val ITNothing = Value(0.U)
val ITExcept... | rocket-chip/src/main/scala/trace/TraceCoreInterface.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.07 | false | false | 1,401 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.apb
import chisel3._
object APBParameters
{
// These are all fixed by the AHB standard:
val protBits = 3
def PROT_PRIVILEGED = 1.U(protBits.W)
def PROT_NONSECURE = 2.U(protBits.W)
def PROT_INSTRUCTION = 4.U(protBits.W)
def P... | rocket-chip/src/main/scala/amba/apb/Protocol.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.167 | false | false | 352 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionType}
import freechips.rocketchip.resources.{... | rocket-chip/src/main/scala/devices/tilelink/Zero.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.125 | false | false | 1,396 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}
import freechips.rocketchip.util._
import ALU._
class MultiplierReq(dataBits: ... | rocket-chip/src/main/scala/rocket/Multiplier.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.016 | false | false | 8,285 | -1 |
package freechips.rocketchip.trace
import chisel3._
import chisel3.util._
import chisel3.experimental.StringParam
class TraceSinkMonitor(name: String) extends BlackBox(
Map(
"FILE_NAME" -> StringParam(s"${name}")
)
) with HasBlackBoxResource {
val io = IO(new Bundle {
val clk = Input(Clock())
val re... | rocket-chip/src/main/scala/trace/TraceSinkMonitor.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0 | false | false | 456 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
import freechips.rocketchip.resources.{SimpleDevice}
import free... | rocket-chip/src/main/scala/devices/tilelink/DevNull.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.088 | false | false | 2,666 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
// This file was originally written by Matthew Naylor, University of
// Cambridge, based on code already present in the groundtest repo.
//
// This software was partly developed by the University of Cambridge
// Computer Laboratory... | rocket-chip/src/main/scala/groundtest/TraceGen.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.378 | false | false | 19,927 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.BlockDuringReset
/** BlockDuringReset ensures that no interrupt is raised while reset is raised. */
class IntBlock... | rocket-chip/src/main/scala/interrupts/BlockDuringReset.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.087 | false | false | 951 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.am... | rocket-chip/src/main/scala/tilelink/ToAXI4.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.111 | false | false | 13,663 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.trace
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import fre... | rocket-chip/src/main/scala/trace/TraceSinkArbiter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.065 | false | false | 1,302 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import org.chipsalliance.cde.config.Parameters
case class CustomCSR(id: Int, mask: BigInt, init: Option[BigInt])
object CustomCSR {
def constant(id: Int, value: BigInt): CustomCSR = CustomCSR(id, BigInt(0), Some(value))... | rocket-chip/src/main/scala/tile/CustomCSRs.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.098 | false | false | 2,341 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.amba.AMBAProt
import freechips.rocketchip.diplomacy.{BufferParams}
import freechips.rocketchi... | rocket-chip/src/main/scala/rocket/DCache.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.063 | false | false | 62,358 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{Cat, Queue, UIntToOH, log2Ceil, OHToUInt, Mux1H, IrrevocableIO}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import fre... | rocket-chip/src/main/scala/amba/axi4/Xbar.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.125 | false | false | 15,146 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure ... | rocket-chip/src/main/scala/interrupts/Crossing.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.009 | false | false | 4,147 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.system // TODO this should really be in a testharness package
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.AMBACorrupt
import freechips.rocketchip.amba.a... | rocket-chip/src/main/scala/system/SimAXIMem.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.188 | false | false | 2,199 | -1 |
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module {
val io = IO(new QueueIO(data, entries))
require(entries > 1)
val do_flow = Wire(Bool())
val do_enq = io.enq.fir... | rocket-chip/src/main/scala/util/HellaQueue.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.083 | false | false | 2,021 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{Cat, log2Up, log2Ceil, UIntToOH, Queue}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.nodes.{MixedAdapterNode, Inward... | rocket-chip/src/main/scala/amba/axi4/ToTL.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.083 | false | false | 9,800 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.apb
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.nodes.{MixedAdapterNode}
import org.chipsalliance.diplomacy.lazymodule.... | rocket-chip/src/main/scala/amba/apb/ToTL.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.139 | false | false | 4,999 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
class TLJbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Paramete... | rocket-chip/src/main/scala/tilelink/Jbar.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.029 | false | false | 2,788 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder}
import freechips.rocketchip.tilelink.TLManagerParameters
case class TLBPermissions(
homogeneous: Bool,... | rocket-chip/src/main/scala/rocket/TLBPermissions.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.051 | false | false | 5,536 | -1 |
package freechips.rocketchip.trace
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.prci._
import freechips.rocketchip.subsystem._
abstract class LazyTraceSink()(impl... | rocket-chip/src/main/scala/trace/TraceSink.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0 | false | false | 582 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.ahb
import chisel3._
import freechips.rocketchip.util._
// Signal directions are from the master's point-of-view
class AHBSlaveBundle(val params: AHBBundleParameters) extends Bundle
{
// Control signals from the arbiter to slave
val hma... | rocket-chip/src/main/scala/amba/ahb/Bundles.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.209 | false | false | 2,926 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tilelink._
import freechips.rocketchip.ut... | rocket-chip/src/main/scala/rocket/NBDcache.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.049 | false | false | 42,070 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.Cat
/** A 16-bit psuedo-random generator based on a linear conguential
* generator (LCG). The state is stored in an unitialised register.
* When using th... | rocket-chip/src/main/scala/util/LCG.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.224 | false | false | 1,422 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.apb
import chisel3._
case class APBMonitorArgs(edge: APBEdgeParameters)
abstract class APBMonitorBase(args: APBMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new APBBundle(args.edge.bundle))
})
def legaliz... | rocket-chip/src/main/scala/amba/apb/Monitor.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.083 | false | false | 424 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.experimental._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rock... | rocket-chip/src/main/scala/devices/tilelink/Plic.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.086 | false | false | 15,419 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.RegionType
import fr... | rocket-chip/src/main/scala/tilelink/FIFOFixer.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.109 | false | false | 6,642 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.prci.{
AsynchronousCrossing, CrossingType, ClockCrossingType, NoCrossing,
RationalCrossing, CreditedCrossing, Synchron... | rocket-chip/src/main/scala/tilelink/CrossingHelper.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.014 | false | false | 3,642 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
// Produces 0-width value when counting to 1
class ZCounter(val n: Int) {
val value = RegInit(0.U(log2Ceil(n).W))
def inc(): Bool = {
if (n == 1) tr... | rocket-chip/src/main/scala/util/Counters.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.066 | false | false | 1,946 | -1 |
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