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// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes.NodeHandle
import freechips.rocke... | rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.043 | false | false | 5,499 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// in... | rocket-chip/src/main/scala/tilelink/WidthWidget.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.09 | false | false | 10,161 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.groundtest
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.tile.CoreModule
import freechips.rocketchip.uti... | rocket-chip/src/main/scala/groundtest/DummyPTW.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.043 | false | false | 1,823 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba
import org.chipsalliance.diplomacy.nodes.{InwardNodeHandle, OutwardNodeHandle, SimpleNodeHandle}
package object ahb
{
type AHBSlaveOutwardNode = OutwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBSlav... | rocket-chip/src/main/scala/amba/ahb/package.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.083 | false | false | 972 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.experimental.IntParam
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.rock... | rocket-chip/src/main/scala/tile/LazyRoCC.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.043 | false | false | 14,070 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import scala.collection.immutable.ListMap
// All Clock parameters specify only the PLL values required at power-on
// Dynamic control of the PLL from softw... | rocket-chip/src/main/scala/prci/ClockParameters.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.091 | false | false | 2,367 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.apb
import chisel3._
import freechips.rocketchip.util._
// Signal directions are from the master's point-of-view
class APBBundle(val params: APBBundleParameters) extends Bundle
{
// Flow control signals from the master
val psel = O... | rocket-chip/src/main/scala/amba/apb/Bundles.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.154 | false | false | 930 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{HasBlackBoxResource, HasBlackBoxPath}
import org.chipsalliance.cde.config.{Field, Parameters}
import java.nio.file.{Files, Paths}
case object ClockGateImpl extends Field[() => ClockGate](() => new EICG... | rocket-chip/src/main/scala/util/ClockGate.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.045 | false | false | 1,394 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
/** This adapter takes an input reset and stretches it.
*
* If the reset wa... | rocket-chip/src/main/scala/prci/ResetStretcher.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.161 | false | false | 1,112 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.tilelink.{BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams, BuiltInDevices}
import freec... | rocket-chip/src/main/scala/subsystem/PeripheryBus.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.015 | false | false | 3,084 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle}
import freechips.rocketchip.prci.{AsynchronousCrossing}
import freech... | rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.022 | false | false | 6,325 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
class AXI4Filter(
Sfilter: AXI4SlaveParamete... | rocket-chip/src/main/scala/amba/axi4/Filter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.033 | false | false | 2,646 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, StretchedResetCrossing, CrossingType, ClockCrossingType, NoCrossing, Asynchron... | rocket-chip/src/main/scala/interrupts/CrossingHelper.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.014 | false | false | 4,199 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.EnableMonitors
import freechips.rocketchip.forma... | rocket-chip/src/main/scala/tilelink/Monitor.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.025 | false | false | 50,322 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{Cat, log2Ceil}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.amba.AMBACorrupt
import freechi... | rocket-chip/src/main/scala/amba/axi4/SRAM.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.115 | false | false | 5,024 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axis
import chisel3.experimental.SourceInfo
import chisel3.util.{isPow2, log2Ceil}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.BaseNode
import freechips.rocketchip.diplomacy.{TransferSizes, IdRang... | rocket-chip/src/main/scala/amba/axis/Parameters.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.003 | false | false | 9,464 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is re... | rocket-chip/src/main/scala/util/AsyncQueue.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.193 | false | false | 10,059 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Valid,Decoupled,Queue,log2Up,OHToUInt,UIntToOH,PriorityEncoderOH,Arbiter,RegEnable,Cat}
import org.chipsalliance.cde.config.Parameters
import freechips.roc... | rocket-chip/src/main/scala/rocket/SimpleHellaCacheIF.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.283 | false | false | 5,453 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{DecoupledIO, Mux1H, OHToUInt, PriorityEncoder, PriorityEncoderOH}
class ReorderQueueWrite[T <: Data](dType: T, tagWidth: Int) extends Bundle {
val data = d... | rocket-chip/src/main/scala/util/ReorderQueue.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.033 | false | false | 2,448 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
abstract class LookupByHartIdImpl {
def apply[T <: Data](f: TileParams => Option[T], hartId: UInt): T
}
case class HartsWontDeduplicate(t: TileParams) extends LookupByHartIdImpl {
def apply[T <: D... | rocket-chip/src/main/scala/tile/LookupByHartId.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.071 | false | false | 640 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
case class BankBinderNode(mask: BigInt)(implic... | rocket-chip/src/main/scala/tilelink/BankBinder.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.029 | false | false | 3,478 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Decoupled,log2Ceil,Cat,UIntToOH,Fill}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class Instruction(implicit val p: Parameters)... | rocket-chip/src/main/scala/rocket/IBuf.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.018 | false | false | 5,651 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
class TLFilter(
mfilter: TLFilter.ManagerFilter = T... | rocket-chip/src/main/scala/tilelink/Filter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.104 | false | false | 6,925 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
/** Useful for stubbing out parts of an interrupt interface where certain devices might be missing */
class NullIntSource(num: Int... | rocket-chip/src/main/scala/interrupts/NullIntSource.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.08 | false | false | 1,100 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util.log2Up
import org.chipsalliance.cde.config.Parameters
trait L1CacheParams {
def nSets: Int
def nWays: Int
def rowBits: Int
def nTLBSets: Int
def nTLBWays: Int
... | rocket-chip/src/main/scala/tile/L1Cache.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.026 | false | false | 1,432 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3.experimental.SourceInfo
import chisel3.util.{isPow2, log2Up}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.BaseNode
import freechips.rocketchip.diplomacy.{AddressSet, RegionTyp... | rocket-chip/src/main/scala/amba/axi4/Parameters.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.083 | false | false | 8,898 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.tile
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.tilelink.{BasicBusBlockerParams, BasicBusBlocker}
impor... | rocket-chip/src/main/scala/tile/RocketTile.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.088 | false | false | 13,636 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
// Moves the AddressSets of slave devices around
// Combine with TLFilter to remov... | rocket-chip/src/main/scala/tilelink/Map.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.073 | false | false | 1,617 | -1 |
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
/** A generalized locking RR arbiter that addresses the limitations of the
* version in the Chisel standard library */
abstract class HellaLockingArbi... | rocket-chip/src/main/scala/util/Arbiters.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.076 | false | false | 4,159 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, n... | rocket-chip/src/main/scala/util/ShiftReg.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.239 | false | false | 2,726 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.ahb
import chisel3._
case class AHBSlaveMonitorArgs(edge: AHBEdgeParameters)
abstract class AHBSlaveMonitorBase(args: AHBSlaveMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new AHBSlaveBundle(args.edge.bundle))... | rocket-chip/src/main/scala/amba/ahb/Monitor.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.048 | false | false | 804 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, IdRange}
/* A ProbePicker is used to unify multiple cache ... | rocket-chip/src/main/scala/tilelink/ProbePicker.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.078 | false | false | 2,754 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.util.{log2Ceil, log2Floor}
trait PrefixSum {
// out[0] = summands[0]
// out[1] = summands[0] + summands[1]
// out[2] = summands[0] + summands[1] + summands[2]
// ...
// where + is your associative operator (reflexiv... | rocket-chip/src/main/scala/util/PrefixSum.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.079 | false | false | 4,664 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.apb
import chisel3._
import chisel3.util.{Decoupled, log2Up, log2Ceil}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.nodes.SinkNode
import freechips.rocketchip... | rocket-chip/src/main/scala/amba/apb/RegisterRouter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.14 | false | false | 2,648 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import chisel3._
import chisel3.util._
abstract class LookupByClusterIdImpl {
def apply[T <: Data](f: BaseClusterParams => Option[T], clusterId: UInt): T
}
case class ClustersWontDeduplicate(t: BaseClusterParams) extends LookupByClu... | rocket-chip/src/main/scala/subsystem/LookupByClusterId.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.071 | false | false | 710 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.apb.APBRegisterNode
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.regmapper.RegFi... | rocket-chip/src/main/scala/devices/debug/APB.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.043 | false | false | 874 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import chisel3._
import freechips.rocketchip.util.RecordMap
class ClockBundle(val params: ClockBundleParameters = ClockBundleParameters()) extends Bundle
{
val clock = Output(Clock())
val reset = Output(Reset())
}
class ClockGroupBundl... | rocket-chip/src/main/scala/prci/ClockBundles.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.067 | false | false | 499 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.regmapper
import scala.util.matching.Regex
// This information is not used internally by the regmap(...) function.
// However, the author of a RegField may be the best person to provide this
// information which is likely to be needed by downstr... | rocket-chip/src/main/scala/regmapper/RegFieldDesc.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.433 | false | false | 6,339 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
/** Takes in data on one decoupled interface and broadcasts it
* to N decoupled output interfaces.
*/
class Broadcaster[T <: Data](typ: T, n: Int) exten... | rocket-chip/src/main/scala/util/Broadcaster.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.125 | false | false | 1,181 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.subsystem
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.debug.{DebugModuleKey, DefaultDebugModulePar... | rocket-chip/src/main/scala/subsystem/Configs.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.104 | false | false | 15,885 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.regmapper
import chisel3._
import chisel3.experimental.SourceInfo
import chisel3.util._
import freechips.rocketchip.diplomacy.AddressDecoder
import freechips.rocketchip.util.{BundleFieldBase, BundleMap, MuxSeq, ReduceOthers, property}
// A bus... | rocket-chip/src/main/scala/regmapper/RegMapper.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.169 | false | false | 9,756 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.tilelink.BuiltInDevices
import freechips.rocketchip.diplomacy.AddressSet
import freechips.... | rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.045 | false | false | 4,204 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.prci.{HasResetDomainCrossing, HasClockDomainCrossing}
package object tilelink
{
type TLInwardNode = InwardNodeHandle[TLMasterPortParam... | rocket-chip/src/main/scala/tilelink/package.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.037 | false | false | 1,793 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.resources
import chisel3._
import chisel3.util.log2Ceil
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{DescribedSRAM, Code}
import freechips.rocketchip.diplomacy.Ad... | rocket-chip/src/main/scala/resources/SRAM.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.304 | false | false | 2,067 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.di... | rocket-chip/src/main/scala/rocket/Frontend.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.036 | false | false | 17,255 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug.systembusaccess
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.{AMBAProt, AMBAProtField}
import freechips.rocketchip.de... | rocket-chip/src/main/scala/devices/debug/SBA.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.044 | false | false | 21,153 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange,... | rocket-chip/src/main/scala/tilelink/Fragmenter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.317 | false | false | 19,181 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3.util._
object CustomInstructions {
def MNRET = BitPat("b01110000001000000000000001110011")
def CEASE = BitPat("b00110000010100000000000001110011")
... | rocket-chip/src/main/scala/rocket/CustomInstructions.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.038 | false | false | 2,533 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.resources.Resource
import freechips.rocketchip.regmapper._
/** Mix this trait into a RegisterRouter to be able to attach its interrupt sou... | rocket-chip/src/main/scala/interrupts/RegisterRouter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.267 | false | false | 889 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.system
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util.DontTouch
/** Example Top with periphery devices and ports, and a Rocke... | rocket-chip/src/main/scala/system/ExampleRocketSystem.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.174 | false | false | 1,087 | -1 |
// See LICENSE.jtag for license details.
package freechips.rocketchip.jtag
import chisel3._
import chisel3.reflect.DataMirror
import chisel3.internal.firrtl.KnownWidth
import chisel3.util.{Cat, Valid}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.property
/** Base JTAG shifter IO, ... | rocket-chip/src/main/scala/jtag/JtagShifter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.2 | false | false | 7,041 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
object ElaborationArtefacts {
var files: Seq[(String, () => String)] = Nil
def add(extension: String, contents: => String): Unit = {
files = (extension, () => contents) +: files
}
def contains(extension: String): Boolean = {
... | rocket-chip/src/main/scala/util/GeneratorUtils.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.091 | false | false | 385 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.bundlebridge.BundleBridgeNexus.fillN
import freech... | rocket-chip/src/main/scala/prci/BundleBridgeBlockDuringReset.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.029 | false | false | 1,272 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.system
import org.chipsalliance.cde.config.Config
import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket.{WithNBigCores, WithNMedCores, WithNSmallCores, WithRV32, WithFP16, WithHype... | rocket-chip/src/main/scala/system/Litex.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.011 | false | false | 4,595 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.{CoreBundle, HasCoreParameters}
import freechips.rocketchip.util._
class BPControl(implicit p: Parameters) extends ... | rocket-chip/src/main/scala/rocket/Breakpoint.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.01 | false | false | 4,366 | -1 |
// See LICENSE.jtag for license details.
package freechips.rocketchip.jtag
import chisel3._
import chisel3.util._
/** Bundle representing a tristate pin.
*/
class Tristate extends Bundle {
val data = Bool()
val driven = Bool() // active high, pin is hi-Z when driven is low
}
/** A module that counts transiti... | rocket-chip/src/main/scala/jtag/Utils.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.17 | false | false | 1,400 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental.{IntParam, StringParam}
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring... | rocket-chip/src/main/scala/util/PlusArg.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.336 | false | false | 5,342 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axis
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.nodes.{SimpleNodeImp, SourceNode, SinkNode, NexusNode, AdapterNode, Out... | rocket-chip/src/main/scala/amba/axis/Nodes.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.034 | false | false | 2,205 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.regmapper
case class RegFieldDescSer(
byteOffset: String,
bitOffset: Int,
bitWidth: Int,
name: String,
resetValue: BigInt,
accessType: String,
wrType: String,
rdAction: String,
desc: String,
group: String,
groupDesc: String... | rocket-chip/src/main/scala/regmapper/Annotation.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.042 | false | false | 566 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.resources.{Device, DeviceSnippet, Description, ResourceBinding, ResourceInt}
import freechips.rock... | rocket-chip/src/main/scala/tile/Interrupts.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.109 | false | false | 4,620 | -1 |
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRaw... | rocket-chip/src/main/scala/prci/ClockDomain.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.056 | false | false | 1,930 | -1 |
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.unittest.UnitTest
class MultiWidthFifo(inW: Int, outW: Int, n: Int) extends Module {
val io = IO(new Bundle {
val in = Flipped(Decoupled(Bits(inW.W)))
val out = ... | rocket-chip/src/main/scala/util/MultiWidthFifo.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.008 | false | false | 4,614 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import scala.collection.immutable.ListMap
import chisel3.experimental.requireIsChiselType
import chisel3.reflect.DataMirror.internal.chiselTypeClone
final class RecordMap[T <: Data] (eltMap: ListMap[String, T])
extends ... | rocket-chip/src/main/scala/util/RecordMap.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.091 | false | false | 921 | -1 |
// See LICENSE for license details.
package freechips.rocketchip.prci
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{AsyncResetReg, ResetCatchAndSync}
class ResetWrangler(debounceNs: Double = 100000)(impli... | rocket-chip/src/main/scala/prci/ResetWrangler.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.079 | false | false | 1,626 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
object IntImp extends SimpleNodeImp[IntSourcePortParameters... | rocket-chip/src/main/scala/interrupts/Nodes.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.012 | false | false | 5,009 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import freechips.rocketchip.devices.debug.HasPeripheryDebug
import freechips.rocketchip.devices.tilelink.{CanHavePeripheryCLINT, CanHavePeripheryPLIC}
import freechips.rocketchip.prci.{ResetCrossin... | rocket-chip/src/main/scala/subsystem/RocketSubsystem.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.022 | false | false | 2,073 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.{NodeHandle}
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.diplomacy.{Ad... | rocket-chip/src/main/scala/amba/axi4/AsyncCrossing.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.158 | false | false | 4,812 | -1 |
// See LICENSE.jtag for license details
package freechips.rocketchip
import scala.language.implicitConversions
package object jtag {
/** An implicit conversion to allow the instruction map for the TAP generator to be specified as
* an Int instead of BigInt. Scala doesn't seem to want to automatically apply the... | rocket-chip/src/main/scala/jtag/package.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.583 | false | false | 576 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.resources.{SimpleDevice}
import freechips.rock... | rocket-chip/src/main/scala/devices/tilelink/ClockBlocker.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.114 | false | false | 1,900 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also ha... | rocket-chip/src/main/scala/util/AsyncResetReg.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.322 | false | false | 3,196 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.regmapper
import scala.language.implicitConversions
import chisel3._
import chisel3.util.{DecoupledIO, ReadyValidIO}
import org.json4s.JsonDSL._
import org.json4s.JsonAST.JValue
import freechips.rocketchip.util.{SimpleRegIO}
case class RegRea... | rocket-chip/src/main/scala/regmapper/RegField.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.219 | false | false | 9,316 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{Decoupled, Queue, log2Ceil, log2Up}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.nodes.{SinkNode}
import freechips.... | rocket-chip/src/main/scala/amba/axi4/RegisterRouter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.112 | false | false | 4,198 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.resour... | rocket-chip/src/main/scala/prci/ClockNodes.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.023 | false | false | 4,462 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
class IntXbar()(implicit p: Parameters) extends LazyModule
{
val intnode = new IntNexusNode(
sinkFn = { _ => IntSinkPortParameters(Seq... | rocket-chip/src/main/scala/interrupts/Xbar.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.019 | false | false | 1,992 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
/** Given a list of (frequency, value) pairs, return a random value
* according to the frequency distribution. The sum of the
* frequencies in the dist... | rocket-chip/src/main/scala/util/Frequency.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.353 | false | false | 1,145 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3.{dontTouch, _}
import chisel3.util._
import chisel3.util.random.LFSR
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diploma... | rocket-chip/src/main/scala/rocket/ICache.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.456 | false | false | 40,787 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.regmapper.{RRTest0, RRTest1}
import freechips.rocketchip.unittest.{UnitTest, UnitTestModule}
class TLRR... | rocket-chip/src/main/scala/tilelink/RegisterRouterTest.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.024 | false | false | 1,782 | -1 |
#include "common.h"
#include "devices.h"
rom_device_t::rom_device_t(std::vector<char> data)
: data(std::move(data))
{
}
bool rom_device_t::load(reg_t addr, size_t len, uint8_t* bytes)
{
if (addr + len > data.size())
return false;
memcpy(bytes, &data[addr], len);
return true;
}
bool rom_device_t::store(re... | spike/riscv/rom.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.118 | false | false | 405 | -1 |
// See LICENSE for license details.
#include "devices.h"
#include "processor.h"
#include "arith.h"
#include "sim.h"
#include "dts.h"
#include <cassert>
#define DOMAINCFG 0x0
#define SOURCECFG_BASE 0x4
#define MMSIADDRCFG 0x1bc0
#define MMSIADDRCFGH 0x1bc4
#define SMSIADDRCFG 0x1bc8
#define SMSIADDRCF... | spike/riscv/aplic.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.157 | false | false | 9,457 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_BLOOM_FILTER_H
#define _RISCV_BLOOM_FILTER_H
#include <bitset>
#include <cstdint>
struct simple_hash1 {
uint64_t operator()(uint64_t x) const
{
x = (x ^ (x >> 33)) * 0xff51afd7ed558ccd;
x = (x ^ (x >> 33)) * 0xc4ceb9fe1a85ec53;
return x ^ (x >> 33);
... | spike/riscv/bloom_filter.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.115 | false | false | 1,202 | -1 |
// See LICENSE for license details.
#include "decode_macros.h"
#include "arith.h"
#include "fp_arith.h"
#include "mmu.h"
#include "softfloat.h"
#include "internals.h"
#include "specialize.h"
#include "tracer.h"
#include "p_ext_macros.h"
#include "v_ext_macros.h"
#include "debug_defines.h"
#include <cassert>
| spike/riscv/insn_template.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 1 | false | false | 310 | -1 |
#include <sys/time.h>
#include <sstream>
#include "devices.h"
#include "processor.h"
#include "simif.h"
#include "sim.h"
#include "dts.h"
clint_t::clint_t(const simif_t* sim, uint64_t freq_hz, bool real_time)
: sim(sim), freq_hz(freq_hz), real_time(real_time), mtime(0)
{
struct timeval base;
gettimeofday(&base,... | spike/riscv/clint.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.171 | false | false | 4,677 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_DTS_H
#define _RISCV_DTS_H
#include "devices.h"
#include "processor.h"
#include <string>
std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz,
const cfg_t* cfg,
std::vector<std::pair<reg_t, abstract_mem_t*>> mems,
... | spike/riscv/dts.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.219 | false | false | 1,781 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_ENTROPY_SOURCE_H
#define _RISCV_ENTROPY_SOURCE_H
#include <fstream>
#include <iostream>
#include "common.h"
//
// Used to model the cryptography extension entropy source.
// See Section 4 of the Scalar Cryptography Extension specificaiton.
class entropy_source {
p... | spike/riscv/entropy_source.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.519 | false | false | 2,940 | -1 |
// Helper macros to help implement instructions defined as part of
// the RISC-V Zvk extension (vector cryptography).
// Note that a good deal of code here would be cleaner/simpler
// if exposed as C++ functions (including templated ones), however
// this is not possible in the contexts where those headers are
// incl... | spike/riscv/zvk_ext_macros.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.61 | false | false | 42,913 | -1 |
#ifndef _RISCV_ZVBDOT_H
#define _RISCV_ZVBDOT_H
#include "bulknormdot.h"
#include <vector>
#include <algorithm>
static inline float32_t f32_add_odd(float32_t a, float32_t b)
{
auto rm = softfloat_roundingMode;
auto flags = softfloat_exceptionFlags;
softfloat_roundingMode = softfloat_round_odd;
softfloat_exce... | spike/riscv/zvbdot.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.136 | false | false | 1,812 | -1 |
#ifndef _RISCV_DEVICES_H
#define _RISCV_DEVICES_H
#include "decode.h"
#include "abstract_device.h"
#include "abstract_interrupt_controller.h"
#include "platform.h"
#include <map>
#include <queue>
#include <vector>
#include <utility>
#include <cassert>
class processor_t;
class simif_t;
class bus_t : public abstract_d... | spike/riscv/devices.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.075 | false | false | 8,019 | -1 |
#ifndef REMOTE_BITBANG_H
#define REMOTE_BITBANG_H
#include <stdint.h>
#include "jtag_dtm.h"
class remote_bitbang_t
{
public:
// Create a new server, listening for connections from localhost on the given
// port.
remote_bitbang_t(uint16_t port, jtag_dtm_t *tap);
// Do a bit of work.
void tick();
// Chec... | spike/riscv/remote_bitbang.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.379 | false | false | 780 | -1 |
#include <sys/time.h>
#include <sstream>
#include "devices.h"
#include "processor.h"
#include "simif.h"
#include "sim.h"
#include "dts.h"
#define PLIC_MAX_CONTEXTS 15872
/*
* The PLIC consists of memory-mapped control registers, with a memory map
* as follows:
*
* base + 0x000000: Reserved (interrupt source 0 doe... | spike/riscv/plic.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.234 | false | false | 11,863 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_LOGFILE_H
#define _RISCV_LOGFILE_H
#include <cstdio>
#include <memory>
#include <sstream>
#include <stdexcept>
// Header-only class wrapping a log file. When constructed with an
// actual path, it opens the named file for writing. When constructed
// with the null pa... | spike/riscv/log_file.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.355 | false | false | 858 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_IMSIC_H
#define _RISCV_IMSIC_H
#include <memory>
#include <map>
#include <unordered_map>
#include "csrs.h"
#include "abstract_device.h"
#define IMSIC_FILE_LEVEL_NUM 2
// EIP/EIE0 to 63 but internally there are only 32 64b registers
#define IMSIC_NUM_EI_REGS 32
#defin... | spike/riscv/imsic.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.313 | false | false | 2,211 | -1 |
#include "arith.h"
#include "debug_defines.h"
#include "processor.h"
#include "triggers.h"
#define ASIDMAX(SXLEN) (SXLEN == 32 ? 9 : 16)
#define SATP_ASID(SXLEN) (SXLEN == 32 ? SATP32_ASID : SATP64_ASID)
#define VMIDMAX(HSXLEN) (HSXLEN == 32 ? 7 : 14)
#define HGATP_VMID(HSXLEN) (HSXLEN == 32 ? HGATP32_VMID : HGATP64_V... | spike/riscv/triggers.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.068 | false | false | 26,839 | -1 |
// Helper macros and functions to help implement instructions defined as part of
// the RISC-V Zvksh extension (vectorized SM3).
#include "zvk_ext_macros.h"
#ifndef RISCV_INSNS_ZVKSH_COMMON_H_
#define RISCV_INSNS_ZVKSH_COMMON_H_
// Constraints common to all vsm3* instructions:
// - Zvksh is enabled
// - VSEW == 32... | spike/riscv/zvksh_ext_macros.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.769 | false | false | 1,659 | -1 |
#include <arpa/inet.h>
#include <cerrno>
#include <fcntl.h>
#include <poll.h>
#include <cstdlib>
#include <cstring>
#include <unistd.h>
#ifndef AF_INET
#include <sys/socket.h>
#endif
#ifndef INADDR_ANY
#include <netinet/in.h>
#endif
#include <algorithm>
#include <cassert>
#include <cstdio>
#include "remote_bitbang.h... | spike/riscv/remote_bitbang.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.146 | false | false | 5,119 | -1 |
// See LICENSE for license details
#include "config.h"
#include "vector_unit.h"
#include "processor.h"
#include "arith.h"
void vectorUnit_t::vectorUnit_t::reset()
{
free(reg_file);
VLEN = get_vlen();
ELEN = get_elen();
reg_file = malloc(NVPR * vlenb);
memset(reg_file, 0, NVPR * vlenb);
auto state = p->ge... | spike/riscv/vector_unit.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.047 | false | false | 5,133 | -1 |
#include <cstdio>
#include "decode.h"
#include "jtag_dtm.h"
#include "debug_module.h"
#include "debug_defines.h"
#if 0
# define D(x) x
#else
# define D(x)
#endif
enum {
IR_IDCODE=1,
IR_DTMCONTROL=0x10,
IR_DBUS=0x11,
IR_BYPASS=0x1f
};
#define DTMCONTROL_VERSION 0xf
#define DTMCONTROL_ABITS (0x3... | spike/riscv/jtag_dtm.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.246 | false | false | 5,471 | -1 |
// See LICENSE for license details.
#include "extension.h"
#include <string>
#include <map>
#include <dlfcn.h>
static std::map<std::string, std::function<extension_t*()>>& extensions()
{
static std::map<std::string, std::function<extension_t*()>> v;
return v;
}
void register_extension(const char* name, std::func... | spike/riscv/extensions.cc | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | cpp | false | 0.154 | false | false | 1,241 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_CFG_H
#define _RISCV_CFG_H
#include <optional>
#include <vector>
#include "decode.h"
#include <cassert>
#include <map>
class abstract_sim_if_t;
typedef enum {
endianness_little,
endianness_big
} endianness_t;
template <typename T>
class cfg_arg_t {
public:
cfg... | spike/riscv/cfg.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.12 | false | false | 2,055 | -1 |
// See LICENSE for license details.
#ifndef _RISCV_COMMON_H
#define _RISCV_COMMON_H
#ifdef __GNUC__
# define likely(x) __builtin_expect(x, 1)
# define unlikely(x) __builtin_expect(x, 0)
# define NOINLINE __attribute__ ((noinline))
# define NORETURN __attribute__ ((noreturn))
# define ALWAYS_INLINE __attribute__ ((a... | spike/riscv/common.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 1 | false | false | 766 | -1 |
#ifndef _RISCV_ABSTRACT_DEVICE_H
#define _RISCV_ABSTRACT_DEVICE_H
#include "decode.h"
#include "common.h"
#include <cstdint>
#include <cstddef>
#include <string>
#include <map>
#include <stdexcept>
#include <vector>
class sim_t;
class abstract_device_t {
public:
virtual bool load(reg_t addr, size_t len, uint8_t* ... | spike/riscv/abstract_device.h | arch_code | spike | spike | BSD-3-Clause | BSD-3-Clause | 4c6a9bc79dab80616932949707e7c0471d8e9e54 | c | false | 0.34 | false | false | 2,284 | -1 |
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