author int64 658 755k | date stringlengths 19 19 | timezone int64 -46,800 43.2k | hash stringlengths 40 40 | message stringlengths 5 490 | mods list | language stringclasses 20 values | license stringclasses 3 values | repo stringlengths 5 68 | original_message stringlengths 12 491 |
|---|---|---|---|---|---|---|---|---|---|
136,418 | 16.07.2018 09:32:50 | 25,200 | 9b7ce9c9dbdb5eb858757dc61a55bb98749019b0 | cheza: Enable MKBP keyboard protocol
This is used for passing button information from EC to AP.
BRANCH=None
TEST=make buildall -j | [
{
"change_type": "MODIFY",
"old_path": "board/cheza/board.h",
"new_path": "board/cheza/board.h",
"diff": "#define CONFIG_HOST_COMMAND_STATUS\n#define CONFIG_HOSTCMD_SECTION_SORTED /* Host commands are sorted. */\n#define CONFIG_MKBP_EVENT\n+#define CONFIG_KEYBOARD_PROTOCOL_MKBP\n#define CONFIG_BOARD... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cheza: Enable MKBP keyboard protocol
This is used for passing button information from EC to AP.
BRANCH=None
BUG=b:74395451
TEST=make buildall -j
Change-Id: I8a4ee99fb699f484dcc71fe4c0c6a7fd05a94ffb
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1138731
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org> |
136,228 | 17.07.2018 10:53:52 | 25,200 | 2fbcc97df9d88701d09ed1d2fcd17f729f4d840f | yorp: Deprecate yorp v0 support
This change gets rid of yorp v0 support from EC codebase.
BRANCH=None
TEST=Boots to OS.
Commit-Ready: Furquan Shaikh
Tested-by: Furquan Shaikh | [
{
"change_type": "MODIFY",
"old_path": "board/yorp/board.c",
"new_path": "board/yorp/board.c",
"diff": "#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)\n#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)\n+#define CPRINTS(format, args...) cprints(CC... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | yorp: Deprecate yorp v0 support
This change gets rid of yorp v0 support from EC codebase.
BUG=b:111545725
BRANCH=None
TEST=Boots to OS.
Change-Id: I1db238ce673a576b913e92874d0f1de730c04b05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1140742
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org> |
136,282 | 26.06.2018 09:15:11 | -28,800 | 97df79fcb02f046c12768497946a7eb8d6b4cffe | careena: enable keyboard factory scanning
This patch is referring to CL:332322.
BRANCH=none
TEST=Short keyboard pins and make sure "ectool kbfactorytest" works. | [
{
"change_type": "MODIFY",
"old_path": "board/careena/board.c",
"new_path": "board/careena/board.c",
"diff": "@@ -239,3 +239,21 @@ void board_reset_pd_mcu(void)\nmsleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);\nboard_set_tcpc_power_mode(USB_PD_PORT_ANX74XX, 1);\n}\n+\n+#ifdef CONFIG_KEYBOARD_FACTORY_TEST\n+/*... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | careena: enable keyboard factory scanning
This patch is referring to CL:332322.
BUG=none
BRANCH=none
TEST=Short keyboard pins and make sure "ectool kbfactorytest" works.
Change-Id: Ic943753c8cec8dde79842de48e5d21ff4dc01c00
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/1114400
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org> |
136,405 | 18.07.2018 09:53:25 | 25,200 | d2e7d0421d0bef3d7d76c873937a5d95c7858193 | Nami: Remove ALS from all projects
ALS has been removed from all variants
BRANCH=none
TEST=make BOARD=nami
Commit-Ready: Daisuke Nojiri
Tested-by: Daisuke Nojiri | [
{
"change_type": "MODIFY",
"old_path": "board/nami/board.c",
"new_path": "board/nami/board.c",
"diff": "#include \"driver/accelgyro_bmi160.h\"\n#include \"driver/accel_bma2x2.h\"\n#include \"driver/accel_kionix.h\"\n-#include \"driver/als_opt3001.h\"\n#include \"driver/baro_bmp280.h\"\n#include \"dr... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Nami: Remove ALS from all projects
ALS has been removed from all variants
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:111597256
BRANCH=none
TEST=make BOARD=nami
Change-Id: If85545f79cc2f076c366ffeebdd96d3ccf31ed9c
Reviewed-on: https://chromium-review.googlesource.com/1142192
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vincent Wang <vwang@chromium.org> |
136,197 | 19.07.2018 16:00:01 | -28,800 | 1e1dea7c3af29801bf853c60a960dd07b4920f3b | kukui/scarlet: Remove CONFIG_MPU
CONFIG_MPU does not make sense anyway on STM32F0 with Cortex-M0
core.
BRANCH=none
TEST=make buildall -j | [
{
"change_type": "MODIFY",
"old_path": "board/kukui/board.h",
"new_path": "board/kukui/board.h",
"diff": "#define CONFIG_UART_CONSOLE 1\n#define CONFIG_UART_RX_DMA\n-/* Region sizes are no longer a power of 2 so we can't enable MPU */\n-#undef CONFIG_MPU\n-\n/* Bootblock */\n#ifdef SECTION_IS_RO\n#d... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | kukui/scarlet: Remove CONFIG_MPU
CONFIG_MPU does not make sense anyway on STM32F0 with Cortex-M0
core.
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I6e338cbbf783babd4e2c9dbe0a3188a086b54807
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1143108
Reviewed-by: Yilun Lin <yllin@chromium.org> |
136,396 | 20.07.2018 17:14:20 | 25,200 | 64f5571960f212bc2085c308d52da1336f6d72a8 | cr50: prepare to release 0.4.9
BRANCH=cr50, cr50-mp
TEST=none | [
{
"change_type": "MODIFY",
"old_path": "util/signer/ec_RW-manifest-dev.json",
"new_path": "util/signer/ec_RW-manifest-dev.json",
"diff": "\"timestamp\": 0,\n\"epoch\": 0, // FWR diversification contributor, 32 bits.\n\"major\": 4, // FW2_HIK_CHAIN counter.\n- \"minor\": 8, // Mostly harmless version... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cr50: prepare to release 0.4.9
BRANCH=cr50, cr50-mp
BUG=none
TEST=none
Change-Id: Ied65e2169a209eaea5d313d6e8461b0f6f219ba2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1145897
Reviewed-by: Mary Ruthven <mruthven@chromium.org> |
136,197 | 22.07.2018 09:44:37 | -28,800 | d12b65708437b586ad8d84dd637d1bae9dfb1549 | kukui: Remap DMA channel 6/7 to SPI2
BRANCH=none
TEST=Flash kukui, see that UART and eMMC emulation work. | [
{
"change_type": "MODIFY",
"old_path": "board/kukui/board.c",
"new_path": "board/kukui/board.c",
"diff": "@@ -241,11 +241,13 @@ void board_config_pre_init(void)\n{\nSTM32_RCC_AHBENR |= STM32_RCC_HB_DMA1;\n/*\n- * Remap USART1:\n+ * Remap USART1 and SPI2 DMA:\n*\n* Ch4: USART1_TX / Ch5: USART1_RX (10... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | kukui: Remap DMA channel 6/7 to SPI2
BRANCH=none
BUG=b:80159522
BUG=b:110907438
TEST=Flash kukui, see that UART and eMMC emulation work.
Change-Id: I2ffc26d4fd19becb2675b86ede64112e6b571de2
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1146129
Reviewed-by: Yilun Lin <yllin@chromium.org> |
136,197 | 23.07.2018 07:52:07 | -28,800 | fb4b73d341948f46597c7a7ca83a194a755c23b6 | power/mt8183: Fix PMIC_EN_ODL polarity, watchdog signal
Watchdog signal should on high by default (and only pulsed to
shut down the PMIC).
Also, PMIC_EN_ODL is active-low, fix polarity.
BRANCH=none
TEST=make BOARD=kukui -j => Boot to FW | [
{
"change_type": "MODIFY",
"old_path": "board/kukui/gpio.inc",
"new_path": "board/kukui/gpio.inc",
"diff": "@@ -51,7 +51,7 @@ GPIO(PP3300_S3_EN, PIN(A, 8), GPIO_OUT_LOW)\n/* Reset pins */\nGPIO(AP_SYS_RST_L, PIN(C, 11), GPIO_ODR_LOW)\n-GPIO(PMIC_WATCHDOG_L, PIN(C, 3), GPIO_OUT_LOW)\n+GPIO(PMIC_WATCH... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | power/mt8183: Fix PMIC_EN_ODL polarity, watchdog signal
Watchdog signal should on high by default (and only pulsed to
shut down the PMIC).
Also, PMIC_EN_ODL is active-low, fix polarity.
BRANCH=none
BUG=b:109850749
TEST=make BOARD=kukui -j => Boot to FW
Change-Id: I3f69bfd75c02ae958785153593d4494c02f39172
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1146132
Reviewed-by: Yilun Lin <yllin@chromium.org> |
136,197 | 23.07.2018 07:48:21 | -28,800 | 83fc351b086a560b21f538828d0eb9fc6d491780 | kukui: Use MODULE_SPI_FLASH for eMMC emulation pins
Will make it possible to unconfigure eMMC emulation pins after the
AP has booted.
BRANCH=None
TEST=make BOARD=kukui BOOTBLOCK=bootblock.bin -j => boot | [
{
"change_type": "MODIFY",
"old_path": "board/kukui/emmc.c",
"new_path": "board/kukui/emmc.c",
"diff": "@@ -187,7 +187,7 @@ static void emmc_init_spi(void)\n#error \"Please define EMMC_SPI_PORT in board.h.\"\n#endif\nclock_wait_bus_cycles(BUS_APB, 1);\n- gpio_config_module(MODULE_SPI, 1);\n+ gpio_co... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | kukui: Use MODULE_SPI_FLASH for eMMC emulation pins
Will make it possible to unconfigure eMMC emulation pins after the
AP has booted.
BRANCH=None
BUG=b:110907438
TEST=make BOARD=kukui BOOTBLOCK=bootblock.bin -j => boot
Change-Id: I1289da42472bbbc176f8a29fc2ffcf7f15b9ab18
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1146133
Reviewed-by: Yilun Lin <yllin@chromium.org> |
136,197 | 23.07.2018 08:18:58 | -28,800 | 5dac338a8c35cf11835db08b36e3f189b2217824 | Cr50: Fix _plat__StartupCallback()
In C, one needs to explicitly say that a function takes no
parameters (we use -Werror=strict-prototypes so this throws
an error).
BRANCH=none
TEST=make BOARD=cr50 -j | [
{
"change_type": "MODIFY",
"old_path": "board/cr50/tpm2/platform.c",
"new_path": "board/cr50/tpm2/platform.c",
"diff": "@@ -63,7 +63,7 @@ void _plat__GetFwVersion(uint32_t *firmwareV1, uint32_t *firmwareV2)\n*firmwareV2 = strtoi(ver_str, NULL, 16);\n}\n-void _plat__StartupCallback()\n+void _plat__St... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Cr50: Fix _plat__StartupCallback()
In C, one needs to explicitly say that a function takes no
parameters (we use -Werror=strict-prototypes so this throws
an error).
BRANCH=none
BUG=chromium:863572
TEST=make BOARD=cr50 -j
Change-Id: I30205df30b794e505030b56691a09e103c434910
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1146131
Reviewed-by: Allen Webb <allenwebb@google.com> |
136,208 | 23.07.2018 14:02:56 | -28,800 | 8ff9198bb10722481139a2e540d76789f8404d36 | charger/mt6370: Support set LDO voltage function.
TEST=flash kukui and manually test on kukui p0.
BRANCH=None
Commit-Ready: Yilun Lin
Tested-by: Yilun Lin | [
{
"change_type": "MODIFY",
"old_path": "driver/charger/rt946x.c",
"new_path": "driver/charger/rt946x.c",
"diff": "@@ -983,6 +983,30 @@ int rt946x_enable_charge_termination(int en)\n}\n#ifdef CONFIG_CHARGER_MT6370\n+/* MT6370 LDO */\n+\n+int mt6370_set_ldo_voltage(int mv)\n+{\n+ int rv;\n+ int vout_v... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | charger/mt6370: Support set LDO voltage function.
TEST=flash kukui and manually test on kukui p0.
BUG=b:80160408
BRANCH=None
Change-Id: I2be4bda585babd0afe6e64837904898d46115e54
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1146418
Commit-Ready: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,256 | 24.07.2018 13:15:33 | 21,600 | 88b8e085862c8ebc68ac62e08f49d0b6e41f13f9 | bip: correct ADC scaling factors
We need to scale the thermistor reading to the exact voltage so it will
lookup correctly in the thermistor table.
BRANCH=none
TEST=temps on EC console makes sense | [
{
"change_type": "MODIFY",
"old_path": "board/bip/board.c",
"new_path": "board/bip/board.c",
"diff": "@@ -47,13 +47,23 @@ static void ppc_interrupt(enum gpio_signal signal)\n/* ADC channels */\nconst struct adc_t adc_channels[] = {\n/* Vbus C0 sensing (10x voltage divider). PPVAR_USB_C0_VBUS */\n- [... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | bip: correct ADC scaling factors
We need to scale the thermistor reading to the exact voltage so it will
lookup correctly in the thermistor table.
BRANCH=none
BUG=b:79932676
TEST=temps on EC console makes sense
Change-Id: Id142fb0a8f588af033d39888c6c7832b2117195d
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1148809
Reviewed-by: Justin TerAvest <teravest@chromium.org> |
136,197 | 24.07.2018 14:11:20 | -28,800 | efac3d3266c6ddcca411d46e24f2d12a593d6670 | kukui: Disable eMMC power supply on boot
Allows reworked boards to boot using eMMC emulation, without
manual steps.
BRANCH=none
TEST=Flash and boot kukui
Commit-Ready: ChromeOS CL Exonerator Bot | [
{
"change_type": "MODIFY",
"old_path": "board/kukui/emmc.c",
"new_path": "board/kukui/emmc.c",
"diff": "@@ -216,6 +216,9 @@ void emmc_task(void *u)\n/* Are we currently transmitting data? */\nint tx = 0;\n+ /* TODO(b:111773571): Remove this once we fix eMMC power supply. */\n+ mt6370_set_ldo_voltage... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | kukui: Disable eMMC power supply on boot
Allows reworked boards to boot using eMMC emulation, without
manual steps.
BRANCH=none
BUG=b:111773571
TEST=Flash and boot kukui
Change-Id: I0a28bcd5a047f708996ee6ac214968e269e17ffe
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1149426
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Yilun Lin <yllin@chromium.org> |
136,405 | 19.07.2018 16:04:37 | 25,200 | 1241107ff7de1e18f80cd83d93a6cb1dc09134a3 | power: Add power_get_state API
This patch adds power_get_state API, which returns the low-level power
chipset state.
BRANCH=none
TEST=make buildall
Commit-Ready: Daisuke Nojiri
Tested-by: Daisuke Nojiri | [
{
"change_type": "MODIFY",
"old_path": "include/power.h",
"new_path": "include/power.h",
"diff": "@@ -138,6 +138,13 @@ int power_wait_signals_timeout(uint32_t want, int timeout);\n*/\nvoid power_set_state(enum power_state new_state);\n+/**\n+ * Set the low-level chipset power state.\n+ *\n+ * @retur... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | power: Add power_get_state API
This patch adds power_get_state API, which returns the low-level power
chipset state.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I104fdf9623f64416d8c27d583cd434920808afdb
Reviewed-on: https://chromium-review.googlesource.com/1144447
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
136,418 | 29.05.2018 15:04:42 | 25,200 | bc4f8b6f4cf0120413561df7e6733b0299e027d0 | cheza: Change GPIO for the rev-1 board
Reflect the chanages on the rev-1 board.
BRANCH=none
TEST=Verified on the rev-1 board, power-on and off, USB boot to kernel. | [
{
"change_type": "MODIFY",
"old_path": "board/cheza/gpio.inc",
"new_path": "board/cheza/gpio.inc",
"diff": "@@ -20,11 +20,7 @@ GPIO_INT(USB_C0_CABLE_DET, PIN(3, 7), GPIO_INT_RISING, anx74xx_cable_det_int\nGPIO_INT(ACCEL_GYRO_INT_L, PIN(D, 3), GPIO_INT_RISING | GPIO_SEL_1P8V, bmi160_interrupt) /* Acc... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cheza: Change GPIO for the rev-1 board
Reflect the chanages on the rev-1 board.
BRANCH=none
BUG=b:79548010
TEST=Verified on the rev-1 board, power-on and off, USB boot to kernel.
Change-Id: I933ff8dc171954dd6c44e0031016b300f15aa24e
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1080995
Reviewed-by: Alexandru M Stan <amstan@chromium.org> |
136,418 | 29.05.2018 15:27:09 | 25,200 | d0d4c9ae0e92b3ae08608c216e090859dd61ac3b | cheza: Enable PWM for display backlight
BRANCH=none
TEST=On the rev-1 board, connects as a panel, the display works. | [
{
"change_type": "MODIFY",
"old_path": "board/cheza/board.c",
"new_path": "board/cheza/board.c",
"diff": "#include \"pi3usb9281.h\"\n#include \"power.h\"\n#include \"power_button.h\"\n+#include \"pwm.h\"\n+#include \"pwm_chip.h\"\n#include \"system.h\"\n#include \"shi_chip.h\"\n#include \"switch.h\"... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cheza: Enable PWM for display backlight
BRANCH=none
BUG=b:79548010, b:78599945
TEST=On the rev-1 board, connects as a panel, the display works.
Change-Id: If5a85e0a173bc51d63b32d92cf734ac40e57cbfc
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1080997
Reviewed-by: Alexandru M Stan <amstan@chromium.org> |
136,418 | 29.05.2018 15:31:43 | 25,200 | 5e42c41ed2ac5d9dec952680117825214e4db783 | cheza: Remove the switchcap hack
Don't need it as the switchcap has been OTP'ed.
BRANCH=none
TEST=On the rev-1 board, power-on and power-off work. | [
{
"change_type": "MODIFY",
"old_path": "board/cheza/board.c",
"new_path": "board/cheza/board.c",
"diff": "@@ -120,16 +120,6 @@ static void ppc_interrupt(enum gpio_signal signal)\nsn5s330_interrupt(port);\n}\n-void board_set_switchcap(int enable)\n-{\n- /*\n- * Disable SwitchCap auto-boot and make EN... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cheza: Remove the switchcap hack
Don't need it as the switchcap has been OTP'ed.
BRANCH=none
BUG=b:77957956
TEST=On the rev-1 board, power-on and power-off work.
Change-Id: I318e658b34d2ebdd8cd169bc5690aa1edd669008
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1080998
Reviewed-by: Alexandru M Stan <amstan@chromium.org> |
136,250 | 26.07.2018 20:49:34 | 25,200 | aae40533b1a390994f4a112d7d46e2595747d784 | servo_micro: increase stack size
This resolves occasional stack overflows.
BRANCH=none
TEST=No longer getting stack overflows. | [
{
"change_type": "MODIFY",
"old_path": "board/servo_micro/ec.tasklist",
"new_path": "board/servo_micro/ec.tasklist",
"diff": "*/\n#define CONFIG_TASK_LIST \\\nTASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \\\n- TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)\n+ TASK_ALWAYS(CON... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | servo_micro: increase stack size
This resolves occasional stack overflows.
BRANCH=none
BUG=b:79684405
TEST=No longer getting stack overflows.
Change-Id: Ib9188b4e4e0c5c87f34c87f490ae8bc26e34e041
Signed-off-by: Matthew Blecker <matthewb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1152564
Reviewed-by: Nick Sanders <nsanders@chromium.org> |
136,256 | 26.07.2018 15:49:41 | 21,600 | 0d7abde47bfb30098f0b6060f9585d5aa24b9821 | octopus: remove unused usb_pd_policy files
We haven't used them yet, so we are removing them.
BRANCH=none
TEST=everything still builds. | [
{
"change_type": "MODIFY",
"old_path": "board/bip/build.mk",
"new_path": "board/bip/build.mk",
"diff": "@@ -13,4 +13,3 @@ BASEBOARD:=octopus\nboard-y=board.o led.o\nboard-$(CONFIG_BATTERY_SMART)+=battery.o\n\\ No newline at end of file\n-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o\n\\ No new... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | octopus: remove unused usb_pd_policy files
We haven't used them yet, so we are removing them.
BRANCH=none
BUG=b:78638238
TEST=everything still builds.
Change-Id: I21aaf060073f3daa6f18a8202c0b7ba98ce9b018
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1152363
Reviewed-by: Justin TerAvest <teravest@chromium.org> |
136,305 | 26.07.2018 10:13:19 | 21,600 | 72573a70d309dfa480708018c481d9da13415d8d | meep: create initial EC image
This image is based on yorp proto 2 from ToT and the most recent meep
schematics
BRANCH=none
TEST=builds | [
{
"change_type": "ADD",
"old_path": null,
"new_path": "board/meep/battery.c",
"diff": "+/* Copyright 2018 The Chromium OS Authors. All rights reserved.\n+ * Use of this source code is governed by a BSD-style license that can be\n+ * found in the LICENSE file.\n+ *\n+ * Battery pack vendor provided c... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | meep: create initial EC image
This image is based on yorp proto 2 from ToT and the most recent meep
schematics
BRANCH=none
BUG=b:111543000
TEST=builds
Change-Id: I42df536b26266da377efbda0db98af1ef269380b
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1151545
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org> |
136,420 | 26.07.2018 12:06:37 | -7,200 | e072f821cd2a14f5e87b6634098601e0d921de99 | util/iteflash: Fix resource leak
Found-by: Coverity Scan
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "util/iteflash.c",
"new_path": "util/iteflash.c",
"diff": "@@ -1134,6 +1134,7 @@ int write_flash2(struct ftdi_context *ftdi, const char *filename,\nif (res <= 0) {\nfprintf(stderr, \"Cannot read %s\\n\", filename);\nfree(buffer);\n+ fclose(hnd);\nreturn -EIO;\n... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | util/iteflash: Fix resource leak
Change-Id: I68008a1ed0d33c5b8c99f7b3d4d8275970c6b04b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #187193
Reviewed-on: https://chromium-review.googlesource.com/1151117
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> |
136,420 | 26.07.2018 12:14:20 | -7,200 | 6282b239e77b6d8d607274ec57732a6291a725c6 | util/uut: Fix resource leak
Found-by: Coverity Scan
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "util/uut/l_com_port.c",
"new_path": "util/uut/l_com_port.c",
"diff": "@@ -237,6 +237,7 @@ int com_port_open(const char *com_port_dev_name,\n\"com_port_open() Error %d, Failed on com_config_uart() %s, \"\n\"%s\\n\",\nerrno, com_port_dev_name, strerror(errno));\... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | util/uut: Fix resource leak
Change-Id: I07b9a0eff390be97b3ee8adbc47dcc28bffa5ff9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #187043
Reviewed-on: https://chromium-review.googlesource.com/1151119
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> |
136,420 | 26.07.2018 12:17:03 | -7,200 | 168897eb1d07b8cdeee74fa2a3bf73f7147121ae | util/cbi-util: Fix resource leaks
Found-by: Coverity Scan
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "util/cbi-util.c",
"new_path": "util/cbi-util.c",
"diff": "@@ -322,6 +322,7 @@ static int cmd_create(int argc, char **argv)\nfprintf(stderr, \"Unable to write CBI image to %s\\n\", filename);\nreturn rv;\n}\n+ free(cbi);\nfprintf(stderr, \"CBI image is created ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | util/cbi-util: Fix resource leaks
Change-Id: I1bac7756df713be66011c75df7e04b0ed342b96d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #187040, #187042
Reviewed-on: https://chromium-review.googlesource.com/1151120
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> |
136,420 | 26.07.2018 12:18:41 | -7,200 | d21c0a90c374b88e09f173de42ed9a388f84f169 | util/cbi-util: Check pointer before using it
Found-by: Coverity Scan
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "util/cbi-util.c",
"new_path": "util/cbi-util.c",
"diff": "@@ -333,11 +333,13 @@ static void print_integer(const uint8_t *buf, enum cbi_data_tag tag)\n{\nuint32_t v;\nstruct cbi_data *d = cbi_find_tag(buf, tag);\n- const char *name = d->tag < CBI_TAG_COUNT ? fi... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | util/cbi-util: Check pointer before using it
Change-Id: If11de8883b001f16d7e8f859a416fbdc5ea0391a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #187038
Reviewed-on: https://chromium-review.googlesource.com/1151121
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> |
136,420 | 26.07.2018 12:20:53 | -7,200 | 358464dd972e34208903313b5391960afd065c7d | util/ectool_keyscan: Fix resource leak
Found-by: Coverity Scan
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "util/ectool_keyscan.c",
"new_path": "util/ectool_keyscan.c",
"diff": "@@ -106,6 +106,7 @@ static int keyscan_read_fdt_matrix(struct keyscan_info *keyscan,\nmatrix->col >= KEYBOARD_COLS) {\nfprintf(stderr, \"Matrix pos out of range (%d,%d)\\n\",\nmatrix->row, m... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | util/ectool_keyscan: Fix resource leak
Change-Id: I6b24df29ce3e04500947868239f7b941c659ffbb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #58169
Reviewed-on: https://chromium-review.googlesource.com/1151123
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> |
136,420 | 26.07.2018 12:22:27 | -7,200 | eed612d047e7ce652bb77f4bd9b7d8c0446ca586 | util/ecst.c: Fix resource leak
Found-by: Coverity Scan
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "util/ecst.c",
"new_path": "util/ecst.c",
"diff": "@@ -984,8 +984,10 @@ int copy_file_to_file(char *dst_file_name,\n/* Open the source file for read. */\nsrc_file = fopen(src_file_name, \"rb\");\n- if (src_file == NULL)\n+ if (src_file == NULL) {\n+ fclose(dst_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | util/ecst.c: Fix resource leak
Change-Id: I3397dcaf90c8141efee170183a6e54e8430924f9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #58168
Reviewed-on: https://chromium-review.googlesource.com/1151124
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> |
136,420 | 26.07.2018 12:23:48 | -7,200 | 99b25eca1e3481e2960a9a084503e5a9211dcc7b | util/stm32mon: Fix resource leak
Found-by: Coverity Scan
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "util/stm32mon.c",
"new_path": "util/stm32mon.c",
"diff": "@@ -871,6 +871,7 @@ int write_flash(int fd, struct stm32_def *chip, const char *filename,\nif (res <= 0) {\nfprintf(stderr, \"Cannot read %s\\n\", filename);\nfree(buffer);\n+ fclose(hnd);\nreturn -EIO;... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | util/stm32mon: Fix resource leak
Change-Id: I81941a440ae0abda226795855b67c2c9b12f6686
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #58166
Reviewed-on: https://chromium-review.googlesource.com/1151125
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> |
136,259 | 03.07.2018 17:14:25 | 25,200 | fa96abba710e10638d783e1c753c3dc523b0226c | DragonEgg: Add support for Type C port 0, charging, and battery
BRANCH=none
TEST=make buildall
Commit-Ready: Jett Rink
Tested-by: Scott Collyer | [
{
"change_type": "MODIFY",
"old_path": "baseboard/dragonegg/baseboard.c",
"new_path": "baseboard/dragonegg/baseboard.c",
"diff": "*/\n/* DragonEgg family-specific configuration */\n+#include \"charge_manager.h\"\n+#include \"charge_state_v2.h\"\n#include \"chipset.h\"\n#include \"console.h\"\n+#incl... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | DragonEgg: Add support for Type C port 0, charging, and battery
BRANCH=none
BUG=b:111281797
TEST=make buildall
Change-Id: I2f4342f2c9ddfb4a6b2debbf94c1b0589227b58c
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1135928
Commit-Ready: Jett Rink <jettrink@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org> |
136,306 | 24.07.2018 18:53:20 | -28,800 | c7670aeaa3c67890a3a001795a6f7127656df264 | stats_manager: add title banner pretty-printing
If a title is supplied it now gets printed centralized on top of the
summary when calling SummaryToString.
BRANCH=None
TEST=unit tests are passing | [
{
"change_type": "MODIFY",
"old_path": "extra/usb_power/stats_manager.py",
"new_path": "extra/usb_power/stats_manager.py",
"diff": "@@ -35,7 +35,7 @@ class StatsManager(object):\nExample usage:\n- >>> stats = StatsManager()\n+ >>> stats = StatsManager(title='Title Banner')\n>>> stats.AddSample(TIME_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | stats_manager: add title banner pretty-printing
If a title is supplied it now gets printed centralized on top of the
summary when calling SummaryToString.
BRANCH=None
BUG=chromium:760267
TEST=unit tests are passing
Change-Id: I7c59896ebac82d2ee7b632fd18350b9b4fff2c24
Signed-off-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1140030
Reviewed-by: Mengqi Guo <mqg@chromium.org> |
136,420 | 01.08.2018 13:17:13 | -7,200 | 3f6fc95c0c55ad8d562c79022cd68823d15a5c93 | chip/mec1322: properly compare timestamps
(uint32_t)(uint32_t - uint32_t) >= 0 is always true.
Found-by: Coverity Scan
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "chip/mec1322/lfw/ec_lfw.c",
"new_path": "chip/mec1322/lfw/ec_lfw.c",
"diff": "@@ -126,7 +126,7 @@ int timestamp_expired(timestamp_t deadline, const timestamp_t *now)\nnow = &now_val;\n}\n- return ((uint32_t)(now->le.lo - deadline.le.lo) >= 0);\n+ return now->l... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | chip/mec1322: properly compare timestamps
(uint32_t)(uint32_t - uint32_t) >= 0 is always true.
Change-Id: I95343379ed76e6ea338e95600006867a1835943a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #142090
Reviewed-on: https://chromium-review.googlesource.com/1158413
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> |
136,420 | 01.08.2018 13:52:28 | -7,200 | 120dc54711a07d6f8e6b597af2bcd04ede3872ae | common/spi_flash: don't mix up unsigned and signed types
Found-by: Coverity Scan
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "common/spi_flash.c",
"new_path": "common/spi_flash.c",
"diff": "@@ -65,7 +65,7 @@ static int spi_flash_write_enable(void)\n/**\n* Returns the contents of SPI flash status register 1\n- * @return register contents or -1 on error\n+ * @return register contents o... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | common/spi_flash: don't mix up unsigned and signed types
Change-Id: Ib06fd16ddbe6455b0f194ee4b6c6f1c1bc8f3adc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #142081, #142083
Reviewed-on: https://chromium-review.googlesource.com/1158505
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> |
136,420 | 01.08.2018 14:01:28 | -7,200 | 3724d39d198cbf706d26f41af1d434afb1b66754 | common/ec_ec_comm_slave: initialize seq
Found-by: Coverity Scan
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "common/ec_ec_comm_slave.c",
"new_path": "common/ec_ec_comm_slave.c",
"diff": "@@ -212,7 +212,7 @@ void ec_ec_comm_slave_task(void *u)\n* aligned on a 32-bit boundary.\n*/\nuint8_t __aligned(4) params[COMMAND_BUFFER_PARAMS_SIZE];\n- unsigned int len, seq, hascr... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | common/ec_ec_comm_slave: initialize seq
Change-Id: Ibf196528fa8e16ec9bcd51151d0397f38c302d08
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #182319
Reviewed-on: https://chromium-review.googlesource.com/1158564
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> |
136,427 | 01.08.2018 18:29:40 | 21,600 | 1a0e7d1371ea2aea694e6ffc91c08dd94927bdd3 | grunt: Remove support for board version 0
We no longer need to support both version 0 and 2.
BRANCH=none
TEST=build | [
{
"change_type": "MODIFY",
"old_path": "board/grunt/board.c",
"new_path": "board/grunt/board.c",
"diff": "#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)\n#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)\n-/*\n- * These GPIOs change pins depending on bo... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | grunt: Remove support for board version 0
We no longer need to support both version 0 and 2.
BUG=b:74538637
BRANCH=none
TEST=build
Change-Id: I37eb7adfd2e9e1f50cb30f489c593bfd00b220d9
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1159722
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org> |
136,427 | 01.08.2018 18:34:08 | 21,600 | cbcf963069165059b1b61a2268a3dbd9cdffd872 | aleena,liara: Update GPIO, battery, and LED.
Change battery to 3S1P.
Change LED to match grunt.
Add keyboard backlight.
Pick up SYS_RESET_L change.
BRANCH=none
TEST=build | [
{
"change_type": "MODIFY",
"old_path": "board/aleena/battery.c",
"new_path": "board/aleena/battery.c",
"diff": "* address, mask, and disconnect value need to be provided.\n*/\nconst struct board_batt_params board_battery_info[] = {\n- /* DynaPack Coslight Battery Information */\n- [BATTERY_DANAPACK_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | aleena,liara: Update GPIO, battery, and LED.
Change battery to 3S1P.
Change LED to match grunt.
Add keyboard backlight.
Pick up SYS_RESET_L change.
BUG=b:111606874,b:111607004
BRANCH=none
TEST=build
Change-Id: I914880010964b25cfc18fb8d5a5018d019d7ba6b
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1159723
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> |
136,256 | 03.08.2018 07:50:01 | 21,600 | 7ceca8cd1e661359cff4cfbdaf6b05ef7171b060 | cleanup: removing \n in CPRINTS
CPRINTS already appends a \n, so we currently have 2
BRANCH=none
TEST=none | [
{
"change_type": "MODIFY",
"old_path": "driver/tcpm/anx7447.c",
"new_path": "driver/tcpm/anx7447.c",
"diff": "@@ -489,7 +489,7 @@ static int anx7447_mux_set(int port, mux_state_t mux_state)\ncc_direction = mux_state & MUX_POLARITY_INVERTED;\nmux_type = mux_state & TYPEC_MUX_DOCK;\n- CPRINTS(\"mux_st... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cleanup: removing \n in CPRINTS
CPRINTS already appends a \n, so we currently have 2
BRANCH=none
BUG=none
TEST=none
Change-Id: Ib782a1b760c771af5ac200c18e0fe84ad7f0aaa1
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1162073 |
136,236 | 03.08.2018 17:34:03 | -28,800 | 572045e5974ab34515ca509fa94bfe0fae5d7d01 | Octopus: Add new battery configuration for Bobba
bobba new battery: AP13J7K of SIMPLO
BRANCH=master
TEST=recognize new battery AP13J7K okay, ship mode test okay, DSG FET
status test okay | [
{
"change_type": "MODIFY",
"old_path": "board/bobba/battery.c",
"new_path": "board/bobba/battery.c",
"diff": "@@ -145,6 +145,36 @@ const struct board_batt_params board_battery_info[] = {\n.discharging_max_c = 60,\n},\n},\n+\n+ /* Simplo AP13J7K Battery Information */\n+ [BATTERY_SMP_AP13J7K] = {\n+ ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Octopus: Add new battery configuration for Bobba
bobba new battery: AP13J7K of SIMPLO
BUG=b:110096478
BRANCH=master
TEST=recognize new battery AP13J7K okay, ship mode test okay, DSG FET
status test okay
Change-Id: Ibfcd9af05492593d99e8d0d433dbc9f59cfeee79
Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1162081
Reviewed-by: Jett Rink <jettrink@chromium.org> |
136,418 | 02.08.2018 12:30:10 | 25,200 | 40906ac081d894eb160164c87366b3f3de974d01 | cheza: Fix triggering PPC interrupt
Cheza only has PPC on port-0. Passing only 0 to the interrupt handler.
BRANCH=none
TEST=Plug a charger to port-0; it charges. | [
{
"change_type": "MODIFY",
"old_path": "board/cheza/board.c",
"new_path": "board/cheza/board.c",
"diff": "@@ -115,9 +115,8 @@ static void anx74xx_cable_det_interrupt(enum gpio_signal signal)\nstatic void ppc_interrupt(enum gpio_signal signal)\n{\n- int port = (signal == GPIO_USB_C0_SWCTL_INT_ODL) ? ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cheza: Fix triggering PPC interrupt
Cheza only has PPC on port-0. Passing only 0 to the interrupt handler.
BRANCH=none
BUG=b:74395451
TEST=Plug a charger to port-0; it charges.
Change-Id: I2d8e33ade5e34cf6da901582fdb08181115cbc28
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1161214
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> |
136,305 | 02.08.2018 09:37:26 | 21,600 | 9a5a7f3692a3e6627ecbce83b799f175cd75b4b9 | meep: confirm thermistor parts
Confirmed that meep is using thermistors with the same b-constants as
yorp, so removing the TODO to overwrite the yorp values
BRANCH=None
TEST=builds | [
{
"change_type": "MODIFY",
"old_path": "board/meep/board.c",
"new_path": "board/meep/board.c",
"diff": "@@ -92,7 +92,6 @@ const struct temp_sensor_t temp_sensors[] = {\n.read = charge_get_battery_temp,\n.idx = 0,\n.action_delay_sec = 1},\n- /* TODO(b/111920102): confirm thermistor parts */\n[TEMP_SE... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | meep: confirm thermistor parts
Confirmed that meep is using thermistors with the same b-constants as
yorp, so removing the TODO to overwrite the yorp values
BRANCH=None
BUG=b:111920102
TEST=builds
Change-Id: Iccf7ba59b0c137b33d7544807d82d6e814a2e259
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1160867
Reviewed-by: Jett Rink <jettrink@chromium.org> |
136,420 | 16.07.2018 17:00:18 | -7,200 | 30b09cea62d5dab06301223020140788dbe6e4de | cortex-m/vecttable: -Wattribute-alias is supported starting GCC8
BRANCH=none
TEST=no more build error with gcc6
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "core/cortex-m/vecttable.c",
"new_path": "core/cortex-m/vecttable.c",
"diff": "@@ -42,7 +42,7 @@ extern void stack_end(void); /* not technically correct, it's just a pointer */\nextern void reset(void);\n#pragma GCC diagnostic push\n-#if __GNUC__ >= 6\n+#if __G... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cortex-m/vecttable: -Wattribute-alias is supported starting GCC8
BUG=none
BRANCH=none
TEST=no more build error with gcc6
Change-Id: Ia575effe884a4816f106666dea815b48c636a858
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1138318
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org> |
136,204 | 06.08.2018 14:18:55 | -28,800 | 7c47fcc96889866ee143e01b56f78b3732657a7f | i2c: add i2c_lock before and after calling i2c_xfer
According to the include/i2c.h, we need to call i2c_lock
before and after calling i2c_xfer. This patch adds the lock
to protect the i2c data transmission.
BRANCH=master
TEST=make buildall -j | [
{
"change_type": "MODIFY",
"old_path": "board/sweetberry/board.c",
"new_path": "board/sweetberry/board.c",
"diff": "@@ -121,6 +121,8 @@ static void board_init(void)\nuint8_t tmp;\n/* i2c 0 has a tendancy to get wedged. TODO(nsanders): why? */\n+ i2c_lock(0, 1);\ni2c_xfer(0, 0, NULL, 0, &tmp, 1, I2C_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | i2c: add i2c_lock before and after calling i2c_xfer
According to the include/i2c.h, we need to call i2c_lock
before and after calling i2c_xfer. This patch adds the lock
to protect the i2c data transmission.
BUG=none
BRANCH=master
TEST=make buildall -j
Change-Id: If125333902105c35ca332c154bbb8012c363d1bf
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1163543
Reviewed-by: Nick Sanders <nsanders@chromium.org> |
136,256 | 25.07.2018 09:13:19 | 21,600 | aba9f5e09f7fb1f18a297fb5552404706a642351 | yorp: update sensor rail lifetime
The Base sensor power is off in S5. Update the mask so we re-initialize
the sensor upon S3 entry.
BRANCH=none
TEST=verified on phaser via CL:1148179, which has same power topology | [
{
"change_type": "MODIFY",
"old_path": "board/yorp/board.c",
"new_path": "board/yorp/board.c",
"diff": "@@ -150,7 +150,7 @@ struct motion_sensor_t motion_sensors[] = {\n[BASE_ACCEL] = {\n.name = \"Base Accel\",\n- .active_mask = SENSOR_ACTIVE_S0_S3_S5,\n+ .active_mask = SENSOR_ACTIVE_S0_S3,\n.chip =... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | yorp: update sensor rail lifetime
The Base sensor power is off in S5. Update the mask so we re-initialize
the sensor upon S3 entry.
BRANCH=none
BUG=b:111727977
TEST=verified on phaser via CL:1148179, which has same power topology
Change-Id: I67e37a92df876657c6ce7044a19070116da41129
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1150206
Reviewed-by: Justin TerAvest <teravest@chromium.org> |
136,321 | 10.08.2018 11:47:50 | 25,200 | e76700b03d84acde223f4bcdf79db764e7ed1039 | sweetberry: format README, clarify details
Changing powerlog.README.md(orginally board.README) format to md.
Adding details, making clarifications.
BRANCH=None
TEST=None | [
{
"change_type": "MODIFY",
"old_path": "extra/usb_power/powerlog.README.md",
"new_path": "extra/usb_power/powerlog.README.md",
"diff": "-Sweetberry USB power monitoring\n+# Sweetberry USB power monitoring\nThis tool allows high speed monitoring of power rails via a special USB\n-endpoint. Currently ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | sweetberry: format README, clarify details
Changing powerlog.README.md(orginally board.README) format to md.
Adding details, making clarifications.
BRANCH=None
BUG=b:111318462
TEST=None
Change-Id: Ic617d3da9518708560501be2786031dbd432ffe4
Signed-off-by: Mengqi Guo <mqg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1171503
Reviewed-by: Nick Sanders <nsanders@chromium.org> |
136,208 | 10.08.2018 10:05:29 | -28,800 | 3ab06b6ff1a5656511be76ff52920582682ba6ae | charger/mt6370: Enables CONFIG_USB_PD_VBUS_MEASURE_CHARGER
mt6370 supports this function, so let's enable it by default.
TEST=make BOARD=kukui flash_ec -j
BRANCH=None
Commit-Ready: Yilun Lin
Tested-by: Yilun Lin | [
{
"change_type": "MODIFY",
"old_path": "include/config.h",
"new_path": "include/config.h",
"diff": "*/\n#if defined(CONFIG_CHARGER_BD9995X) || \\\ndefined(CONFIG_CHARGER_RT9466) || \\\n- defined(CONFIG_CHARGER_RT9467)\n+ defined(CONFIG_CHARGER_RT9467) || \\\n+ defined(CONFIG_CHARGER_MT6370)\n#define... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | charger/mt6370: Enables CONFIG_USB_PD_VBUS_MEASURE_CHARGER
mt6370 supports this function, so let's enable it by default.
TEST=make BOARD=kukui flash_ec -j
BUG=b:80160408
BRANCH=None
Change-Id: Ife2ca18e43ab0c913979e235d266ced987d4af77
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1170445
Commit-Ready: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org> |
136,414 | 26.06.2018 19:57:13 | -28,800 | a1e04f74c47d003bddd1802ab50b3ac74c2ea875 | cr50: Add support for virtual NV indexes.
This is to allow reading of board ID and serial number
through NV indexes.
CQ-DEPEND=CL:1114675
BRANCH=none
TEST=NV_Read of virtual indices using trunks_send --raw, b:110971075 | [
{
"change_type": "MODIFY",
"old_path": "board/cr50/build.mk",
"new_path": "board/cr50/build.mk",
"diff": "@@ -55,6 +55,7 @@ board-y += tpm2/stubs.o\nboard-y += tpm2/tpm_mode.o\nboard-y += tpm2/tpm_state.o\nboard-y += tpm2/trng.o\n+board-y += tpm2/virtual_nvmem.o\nboard-y += tpm_nvmem_read.o\nboard-y... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cr50: Add support for virtual NV indexes.
This is to allow reading of board ID and serial number
through NV indexes.
CQ-DEPEND=CL:1114675
BRANCH=none
BUG=b:110971075, chromium:846114
TEST=NV_Read of virtual indices using trunks_send --raw, b:110971075 #3
Change-Id: Iaf7256ea50e36021b61c92f8606d1a62af37df2d
Signed-off-by: Louis Collard <louiscollard@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1114674
Reviewed-by: Andrey Pronin <apronin@chromium.org> |
136,420 | 06.08.2018 14:28:47 | -7,200 | 5012ca7804c594c763cc36ee93db1e90c118eac8 | util/ecst: Also report copy failure on writes
Found-by: Coverity Scan
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "util/ecst.c",
"new_path": "util/ecst.c",
"diff": "@@ -1004,10 +1004,16 @@ int copy_file_to_file(char *dst_file_name,\n/* If byte reading pass than write it to the destination, */\n/* else exit from the reading loop. */\n- if (result)\n+ if (result) {\n/* Read ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | util/ecst: Also report copy failure on writes
Change-Id: Ie01daa75b22fd1efca1c72d34c42c18abea53c2e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #58172
Reviewed-on: https://chromium-review.googlesource.com/1163610
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com> |
136,256 | 27.07.2018 15:14:21 | 21,600 | 5b417bf12ec07042bb79341b5aeb69320041f1bb | ps8751: add low power mode for PS8751 when only MUX
Enter lower power mode for PS8751 when acting as mux only.
BRANCH=none
TEST=PS8751 as MUX on C1 Bip goes into low power mode after disconnect. | [
{
"change_type": "MODIFY",
"old_path": "driver/tcpm/tcpci.c",
"new_path": "driver/tcpm/tcpci.c",
"diff": "@@ -540,6 +540,28 @@ int tcpci_get_chip_info(int port, int renew,\nreturn EC_SUCCESS;\n}\n+/*\n+ * Dissociate from the TCPC.\n+ */\n+\n+int tcpci_tcpm_release(int port)\n+{\n+ int error;\n+\n+ e... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | ps8751: add low power mode for PS8751 when only MUX
Enter lower power mode for PS8751 when acting as mux only.
BRANCH=none
BUG=b:111664205,b:111876407,b:10937880
TEST=PS8751 as MUX on C1 Bip goes into low power mode after disconnect.
Change-Id: Ifac3b76556069e1e5f6acae550d8076c29d5f1cd
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1153835
Reviewed-by: Furquan Shaikh <furquan@chromium.org> |
136,407 | 14.08.2018 22:46:06 | 25,200 | 8dd602a7505176b120c9bee267aee3dcb950559d | nocturne: Change RCAM_VSYNC to rising edge.
BRANCH=None
TEST=`make -j BOARD=nocturne`
Commit-Ready: Aseda Aboagye
Tested-by: Aseda Aboagye | [
{
"change_type": "MODIFY",
"old_path": "board/nocturne/gpio.inc",
"new_path": "board/nocturne/gpio.inc",
"diff": "@@ -33,7 +33,7 @@ GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_\nGPIO_INT(ACCELGYRO3_INT_L, PIN(4, 1), GPIO_INT_FALLING, bmi160_interrupt)\nGPIO_INT(BASE_USB_FAU... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | nocturne: Change RCAM_VSYNC to rising edge.
BUG=b:111282744
BRANCH=None
TEST=`make -j BOARD=nocturne`
Change-Id: I2588291e4daf336ad9365bc21faef0761386c989
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1175542
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org> |
136,420 | 26.07.2018 12:30:45 | -7,200 | 84d2e6824b8eaa68dc0d0920822a5c6489005683 | util/ecst: Fail on partial reads
Found-by: Coverity Scan
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "util/ecst.c",
"new_path": "util/ecst.c",
"diff": "@@ -1872,9 +1872,9 @@ int calc_header_crc_bin(unsigned int *p_cksum)\n/* Go thru the BIN File and calculate the Checksum */\nfseek(g_hfd_pointer, 0x00000000, SEEK_SET);\nif (fread(g_header_array,\n- 1,\nHEADER_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | util/ecst: Fail on partial reads
Change-Id: Iadc031195773f7f1eac6642de6995659eab42707
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #58140, #58142, #58143
Reviewed-on: https://chromium-review.googlesource.com/1151187
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com> |
136,404 | 08.08.2018 12:35:37 | -28,800 | 7ef6291e33c31388652e66ebf0f96ec6d836d528 | keyboard: Change scan code magic values to enum.
The key codes are now always scan code set 2 so we can create a list of
scan codes and use them easily.
TEST=make buildall -j; boots properly
BRANCH=None | [
{
"change_type": "MODIFY",
"old_path": "common/keyboard_8042.c",
"new_path": "common/keyboard_8042.c",
"diff": "@@ -776,30 +776,33 @@ static void i8042_handle_from_host(void)\nstatic void keyboard_special(uint16_t k)\n{\nstatic uint8_t s;\n- static const uint16_t a[] = {0xe075, 0xe075, 0xe072, 0xe07... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | keyboard: Change scan code magic values to enum.
The key codes are now always scan code set 2 so we can create a list of
scan codes and use them easily.
BUG=None
TEST=make buildall -j; boots properly
BRANCH=None
Change-Id: I1fdd7ab81bc13c97c4139afc19d71f5898e22f96
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1166743 |
136,282 | 16.08.2018 11:32:51 | -28,800 | b244deb45b4051a8166824abdccf8cb40b8e2e75 | meep: Add batteries configuration
meep plan to use batteries the same as careena.
BRANCH=none
TEST=make buildall -j
Commit-Ready: ChromeOS CL Exonerator Bot | [
{
"change_type": "MODIFY",
"old_path": "board/meep/battery.c",
"new_path": "board/meep/battery.c",
"diff": "* address, mask, and disconnect value need to be provided.\n*/\nconst struct board_batt_params board_battery_info[] = {\n- /* TODO(b/111838980): fill in after receiving datasheets */\n+ /* Dyn... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | meep: Add batteries configuration
meep plan to use batteries the same as careena.
BUG=b:111838980
BRANCH=none
TEST=make buildall -j
Change-Id: I29955dfaecefd16a48b6b14a48c3f06de97e11c0
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/1177096
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Jett Rink <jettrink@chromium.org> |
136,418 | 17.08.2018 09:27:55 | 25,200 | 2741f9db6f8d893b8dc8f0542e12563f35a9eda7 | cheza: Don't need to set the switchcap register on init
The switchcap register should be OTP'ed.
BRANCH=none
TEST=On the rev-2 board, power cycle the board, check the switchcap
register having a proper value. | [
{
"change_type": "MODIFY",
"old_path": "board/cheza/board.c",
"new_path": "board/cheza/board.c",
"diff": "#include \"driver/tcpm/tcpci.h\"\n#include \"gpio.h\"\n#include \"hooks.h\"\n-#include \"i2c.h\"\n#include \"lid_switch.h\"\n#include \"pi3usb9281.h\"\n#include \"power.h\"\n@@ -52,9 +51,6 @@ st... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cheza: Don't need to set the switchcap register on init
The switchcap register should be OTP'ed.
BRANCH=none
BUG=b:77957956
TEST=On the rev-2 board, power cycle the board, check the switchcap
register having a proper value.
Change-Id: I558301772404618a1d189a567ea61e743f403e84
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1179975
Reviewed-by: Stephen Boyd <swboyd@chromium.org> |
136,332 | 17.08.2018 15:12:35 | -28,800 | 2127ff7e90508d74a975dfe2ec7663d44821a02a | kukui: PMIC_WATCHDOG_L should follow status of PMIC_WATCHDOG_L
BRANCH=none
TEST=make flash_ec BOARD=kukui -j
TEST=waveform in b:112741115
Commit-Ready: Nicolas Boichat
Tested-by: Nicolas Boichat | [
{
"change_type": "MODIFY",
"old_path": "board/kukui/gpio.inc",
"new_path": "board/kukui/gpio.inc",
"diff": "@@ -28,7 +28,7 @@ GPIO_INT(PMIC_EC_RESETB, PIN(B, 7), GPIO_INT_BOTH | GPIO_PULL_DOWN,\npower_signal_interrupt)\nGPIO_INT(WARM_RESET_REQ, PIN(A, 3), GPIO_INT_RISING | GPIO_PULL_DOWN,\nwarm_rese... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | kukui: PMIC_WATCHDOG_L should follow status of PMIC_WATCHDOG_L
BUG=b:112741115
BRANCH=none
TEST=make flash_ec BOARD=kukui -j
TEST=waveform in b:112741115
Change-Id: I53798356714289276a5fdaed9f6190a247a1db7d
Signed-off-by: Ayo Wu <ayowu@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1179494
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,208 | 17.08.2018 15:18:12 | -28,800 | 0b2179c3179a31fde8678e9700477da2365c63ff | gpio.wrap: add *_R[OW] macros for easier pin configuration.
TEST=make BOARD=kukui -j
BRANCH=None
Commit-Ready: Yilun Lin
Tested-by: Yilun Lin | [
{
"change_type": "MODIFY",
"old_path": "include/gpio.wrap",
"new_path": "include/gpio.wrap",
"diff": "#define UNIMPLEMENTED(name)\n#endif\n+/*\n+ * RO/RW pin macro.\n+ *\n+ * Some boards may have very different pin configurations between RO and RW, and\n+ * also may vary from revisions to revisions.... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | gpio.wrap: add *_R[OW] macros for easier pin configuration.
TEST=make BOARD=kukui -j
BUG=b:80159522
BRANCH=None
Change-Id: Iea32d39923d88baaacc2973dd71615b1bacfada3
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1182702
Commit-Ready: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,337 | 17.08.2018 11:00:18 | 25,200 | af908bfce225415c01d56b3f57cfc399d8485d3e | common: add BASE_CHANGE hook
Add a hook to act when a detachable device is connected/disconnected
from a base.
BRANCH=nocturne
TEST=Test with evtest that an event is sent to the AP. | [
{
"change_type": "MODIFY",
"old_path": "common/hooks.c",
"new_path": "common/hooks.c",
"diff": "@@ -45,6 +45,7 @@ static const struct hook_ptrs hook_list[] = {\n{__hooks_ac_change, __hooks_ac_change_end},\n{__hooks_lid_change, __hooks_lid_change_end},\n{__hooks_tablet_mode_change, __hooks_tablet_mod... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | common: add BASE_CHANGE hook
Add a hook to act when a detachable device is connected/disconnected
from a base.
BUG=b:73133611
BRANCH=nocturne
TEST=Test with evtest that an event is sent to the AP.
Change-Id: I21103fff88f19a197124095ee229eebb178dcf3d
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1180538
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,429 | 17.08.2018 11:31:39 | 25,200 | 625acc6b7c7455b0f7c6ad49f467737ce64b37eb | Move fuzzing tests into a fuzz subfolder.
BRANCH=none
CQ-DEPEND=CL:*664115
TEST=make -j buildall && make -j buildfuzztests | [
{
"change_type": "MODIFY",
"old_path": "Makefile",
"new_path": "Makefile",
"diff": "@@ -91,13 +91,14 @@ UC_PROJECT:=$(call uppercase,$(PROJECT))\n# Transform the configuration into make variables. This must be done after\n# the board/baseboard/project/chip/core variables are defined, since some of\n... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Move fuzzing tests into a fuzz subfolder.
BRANCH=none
CQ-DEPEND=CL:*664115
BUG=chromium:876582
TEST=make -j buildall && make -j buildfuzztests
Change-Id: Iade5e5138f495e6b3b99ec16f1a467861ade5537
Signed-off-by: Allen Webb <allenwebb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1180179
Reviewed-by: Mattias Nissler <mnissler@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,274 | 23.08.2018 19:01:19 | 25,200 | b79cd75882007448db3cb9467fc11b6b4f726283 | servo_v4: clear bbram PD state on reboot
Preserved bbram state causes failure to reinit on reboot.
Clear on board init.
BRANCH=None
TEST=PD reinits on reboot.
Commit-Ready: ChromeOS CL Exonerator Bot | [
{
"change_type": "MODIFY",
"old_path": "board/servo_v4/board.c",
"new_path": "board/servo_v4/board.c",
"diff": "#include \"queue_policies.h\"\n#include \"registers.h\"\n#include \"spi.h\"\n+#include \"system.h\"\n#include \"task.h\"\n#include \"timer.h\"\n#include \"update_fw.h\"\n#include \"gpio_li... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | servo_v4: clear bbram PD state on reboot
Preserved bbram state causes failure to reinit on reboot.
Clear on board init.
BRANCH=None
BUG=b:111573811
TEST=PD reinits on reboot.
Change-Id: Ifdf98b5793cb99e2900ac5dc53263a86317b6b07
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1187883
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> |
136,274 | 21.08.2018 15:08:20 | 25,200 | 538f722d8cb63e581ce1756868ee249caafc4ee8 | servo_micro: Fix DMA mappings
UART3 and 4 had DMA collisions. Remove DMA from UART4.
BRANCH=servo-9040
TEST=reboot EC, no crashy | [
{
"change_type": "MODIFY",
"old_path": "board/servo_micro/board.c",
"new_path": "board/servo_micro/board.c",
"diff": "#include \"gpio_list.h\"\n+void board_config_pre_init(void)\n+{\n+ /* enable SYSCFG clock */\n+ STM32_RCC_APB2ENR |= STM32_RCC_SYSCFGEN;\n+\n+ /*\n+ * the DMA mapping is :\n+ * Chan ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | servo_micro: Fix DMA mappings
UART3 and 4 had DMA collisions. Remove DMA from UART4.
BRANCH=servo-9040
BUG=b:112701646,chromium:865478
TEST=reboot EC, no crashy
Change-Id: Ic44b363dafe938d6420b350eb1c5ab796da81f3c
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1188514
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,197 | 28.08.2018 10:00:48 | -28,800 | 2e4cd7bef7ef671d49ea7bb3ae55e9df970d8e25 | kukui: Change FORCE_RESET to ODL
Also, FORCE_RESET is open-drain, active-low. Also, set the default
to high.
BRANCH=none
TEST=boot rev1 to coreboot | [
{
"change_type": "MODIFY",
"old_path": "board/kukui/gpio.inc",
"new_path": "board/kukui/gpio.inc",
"diff": "@@ -74,7 +74,7 @@ GPIO(PP3300_S3_EN, PIN(D, 2), GPIO_OUT_LOW)\nGPIO(AP_SYS_RST_L, PIN(C, 11), GPIO_OUT_LOW)\nGPIO(PMIC_WATCHDOG_L, PIN(C, 3), GPIO_OUT_LOW)\nGPIO(PMIC_EN_ODL, PIN(C, 10), GPIO_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | kukui: Change FORCE_RESET to ODL
Also, FORCE_RESET is open-drain, active-low. Also, set the default
to high.
BRANCH=none
BUG=b:112616655
TEST=boot rev1 to coreboot
Change-Id: I33bd4a97831313f7bc5c3f0044c5b44d88932060
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1192722
Reviewed-by: Yilun Lin <yllin@chromium.org> |
136,396 | 28.08.2018 11:49:40 | 25,200 | 05f0b25f93600338e82109ec1f89fa6b0c59a0d7 | Prepare to release version 0.4.10
BRANCH=cr50
TEST=none | [
{
"change_type": "MODIFY",
"old_path": "util/signer/ec_RW-manifest-dev.json",
"new_path": "util/signer/ec_RW-manifest-dev.json",
"diff": "\"timestamp\": 0,\n\"epoch\": 0, // FWR diversification contributor, 32 bits.\n\"major\": 4, // FW2_HIK_CHAIN counter.\n- \"minor\": 9, // Mostly harmless version... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Prepare to release version 0.4.10
BRANCH=cr50
BUG=none
TEST=none
Change-Id: I397dc1fe7d0382db995880a6963621ab1e4c0b38
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194346
Reviewed-by: Mary Ruthven <mruthven@chromium.org> |
136,256 | 28.08.2018 09:34:29 | 21,600 | 475f67828ff64d5398616a3998f70178b96e2864 | build: print out remaining RAM space
Some boards are pretty tight on RAM space. Print out remain RAM bytes
for each board along with the tightest 3 boards during buildall.
BRANCH=none
TEST=buildall now outputs the tightest boards on RAM. | [
{
"change_type": "MODIFY",
"old_path": "Makefile.rules",
"new_path": "Makefile.rules",
"diff": "@@ -160,9 +160,15 @@ buildall: build_boards\n$(MAKE) runtests\n@touch .tests-passed\n@echo \"$@ completed successfully!\"\n- @echo \"Tightest boards' RW images, bytes left:\"\n- @grep . build/*/RW/space_l... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | build: print out remaining RAM space
Some boards are pretty tight on RAM space. Print out remain RAM bytes
for each board along with the tightest 3 boards during buildall.
BRANCH=none
BUG=none
TEST=buildall now outputs the tightest boards on RAM.
Change-Id: I819e554400e88937bb937f2ca51daf737588a9a5
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194342
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> |
136,204 | 03.08.2018 18:56:55 | -28,800 | 1808ad059f7504f28c84b584d0e7a5affbbaaef3 | Rammus: enable cbi for EEPROM
Rammus uses EEPROM to store the device info like sku id, board version.
This patch adds the cbi config for rammus.
BRANCH=master
TEST=ectool cbi set/get | [
{
"change_type": "MODIFY",
"old_path": "board/rammus/board.h",
"new_path": "board/rammus/board.h",
"diff": "#define CONFIG_ADC\n#define CONFIG_BACKLIGHT_LID\n#define CONFIG_BOARD_FORCE_RESET_PIN\n+#define CONFIG_CRC8\n+#define CONFIG_CROS_BOARD_INFO\n#define CONFIG_DPTF\n#define CONFIG_DPTF_DEVICE_O... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Rammus: enable cbi for EEPROM
Rammus uses EEPROM to store the device info like sku id, board version.
This patch adds the cbi config for rammus.
BUG=b:111815817
BRANCH=master
TEST=ectool cbi set/get
Change-Id: I776de02b66b8545a2998635a974933fadd1e4d7a
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194547
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> |
136,396 | 29.08.2018 14:28:54 | 25,200 | dfb04c7b51b2c467736932a24d811a2e3e43b6d2 | signer: modify publishing instructions
With the updates in the release process the location for saving a new
signed image has changed, let's update instructions printed by the
signer script.
BRANCH=none
TEST=none | [
{
"change_type": "MODIFY",
"old_path": "util/signer/create_released_image.sh",
"new_path": "util/signer/create_released_image.sh",
"diff": "@@ -224,8 +224,9 @@ tarball=\"${dest_dir}.tbz2\"\ntar jcf \"${tarball}\" \"${dest_dir}\"\nrm -rf \"${dest_dir}\"\n-bcs_path=\"gs://chromeos-localmirror/distfile... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | signer: modify publishing instructions
With the updates in the release process the location for saving a new
signed image has changed, let's update instructions printed by the
signer script.
BRANCH=none
BUG=none
TEST=none
Change-Id: I70901256f79bae2a4c20f59c00a51c5cc9309df7
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194618
Reviewed-by: Mary Ruthven <mruthven@chromium.org> |
136,401 | 17.08.2018 15:11:08 | 21,600 | 7a377aff01e61a324bfa6a39087808f1b12e7dc9 | docs: Document low-battery compatibility config.
HOWTO set up an EC board such that plugging it in and turning it on Just
Works.
BRANCH=none
TEST=load docs in a markdown viewer for formatting. | [
{
"change_type": "MODIFY",
"old_path": "common/charge_state_v2.c",
"new_path": "common/charge_state_v2.c",
"diff": "@@ -2308,7 +2308,7 @@ static int charge_command_charge_state(struct host_cmd_handler_args *args)\nval = curr.chg.option;\nbreak;\ncase CS_PARAM_LIMIT_POWER:\n-#ifdef CONFIG_CHARGER_LIM... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | docs: Document low-battery compatibility config.
HOWTO set up an EC board such that plugging it in and turning it on Just
Works.
BUG=none
BRANCH=none
TEST=load docs in a markdown viewer for formatting.
Change-Id: Ib1b31fe0a3c26ac7aad95d362f89afc25f57bf99
Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1180403 |
136,306 | 23.08.2018 17:48:21 | -28,800 | a127ae219416e6352aafaf2498299715047852e1 | flash_ec: leverage new ftdii2c_cmd interface for ite flash
This adopts the change to the ftdii2c controls
CQ-DEPEND=CL:1156425
BRANCH=None
TEST=None
Tested-by: Matthew Blecker | [
{
"change_type": "MODIFY",
"old_path": "util/flash_ec",
"new_path": "util/flash_ec",
"diff": "@@ -487,9 +487,9 @@ cleanup() {\nif [ \"${CHIP}\" == \"it83xx\" ] ; then\ninfo \"Reinitialize ftdi_i2c interface\"\n- dut_control --ftdii2c init\n- dut_control --ftdii2c open\n- dut_control --ftdii2c setclo... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | flash_ec: leverage new ftdii2c_cmd interface for ite flash
This adopts the change to the ftdii2c controls
CQ-DEPEND=CL:1156425
BRANCH=None
BUG=chromium:869335
TEST=None
Change-Id: Ic5c5dbf0404db354834e1148e527353667ec25f9
Signed-off-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1186385
Tested-by: Matthew Blecker <matthewb@chromium.org>
Reviewed-by: Matthew Blecker <matthewb@chromium.org> |
136,282 | 22.08.2018 13:21:15 | -28,800 | d219d5cef0f429ff01753159b11355d02fe194f9 | meep: add VBUS voltage adc sensing
This patch add to detect VBUS voltage, we are using 10x voltage
divider.
BRANCH=none
TEST=make sure "ectool usbpdpower" can detect VBUS voltage. | [
{
"change_type": "MODIFY",
"old_path": "board/meep/board.c",
"new_path": "board/meep/board.c",
"diff": "#include \"charge_manager.h\"\n#include \"charge_state.h\"\n#include \"common.h\"\n+#include \"console.h\"\n#include \"cros_board_info.h\"\n#include \"driver/accel_kionix.h\"\n#include \"driver/ac... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | meep: add VBUS voltage adc sensing
This patch add to detect VBUS voltage, we are using 10x voltage
divider.
BUG=b:113193009
BRANCH=none
TEST=make sure "ectool usbpdpower" can detect VBUS voltage.
Change-Id: Ie96465ce1a28dde3381a2105afff14b1d41c89dd
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/1184587
Reviewed-by: Jett Rink <jettrink@chromium.org> |
136,256 | 28.08.2018 08:03:41 | 21,600 | 7e2620939074ae2ef8af5a3a3df007105f564d2c | cleanup: remove tcpc* extern function declarations
We do not want to use extern when possible, so move the function
declaration section in the tcpm stub c files to an appropriate header file.
BRANCH=none
TEST=zinger compiler (along with everything else) | [
{
"change_type": "MODIFY",
"old_path": "driver/tcpm/stub.c",
"new_path": "driver/tcpm/stub.c",
"diff": "#include \"tcpci.h\"\n#include \"tcpm.h\"\n#include \"usb_pd.h\"\n+#include \"usb_pd_tcpc.h\"\n#include \"usb_pd_tcpm.h\"\n-extern int tcpc_alert_status(int port, int *alert);\n-extern int tcpc_al... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cleanup: remove tcpc* extern function declarations
We do not want to use extern when possible, so move the function
declaration section in the tcpm stub c files to an appropriate header file.
BRANCH=none
BUG=none
TEST=zinger compiler (along with everything else)
Change-Id: If867661840d138e0c912669e401469a152fa3d9b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194083
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> |
136,197 | 06.08.2018 09:46:04 | -28,800 | 845734de27bc705b263a2090ccd662964b6671cd | whiskers: Drive DETECT_PATH_DISABLE_L low, pull-up on BACKLIGHT_EN
BRANCH=nocturne
TEST=make BOARD=whiskers -j
TEST=Without external pull-up, backlight still works
TEST=Check power consumption lower than without patch | [
{
"change_type": "MODIFY",
"old_path": "board/hammer/gpio.inc",
"new_path": "board/hammer/gpio.inc",
"diff": "@@ -76,8 +76,9 @@ GPIO(CHARGER_I2C_SDA, PIN(B, 11), GPIO_INPUT)\nGPIO(SWITCH_STATUS, PIN(A, 15), GPIO_INPUT)\nGPIO(EN_OTG, PIN(B, 5), GPIO_INPUT)\n#elif defined(BOARD_WHISKERS)\n-GPIO(DETECT... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | whiskers: Drive DETECT_PATH_DISABLE_L low, pull-up on BACKLIGHT_EN
BRANCH=nocturne
BUG=b:111191396
BUG=b:109853051
TEST=make BOARD=whiskers -j
TEST=Without external pull-up, backlight still works
TEST=Check power consumption lower than without patch
Change-Id: I4be8726672936ccbc45b262d94085de320c35e54
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1163234
Reviewed-by: Wei-Han Chen <stimim@chromium.org> |
136,256 | 04.09.2018 13:57:52 | 21,600 | 23b3b88f821105125bc7fb1d0607e0d474fa4d1a | bip: add tablet mode for consistency
Hardware has supported tablet mode for a while, add firmware support for
tablet mode.
BRANCH=none
TEST=on bip, can use magnet to enter tablet mode. | [
{
"change_type": "MODIFY",
"old_path": "board/bip/board.c",
"new_path": "board/bip/board.c",
"diff": "#include \"switch.h\"\n#include \"system.h\"\n#include \"tcpci.h\"\n+#include \"tablet_mode.h\"\n#include \"temp_sensor.h\"\n#include \"thermistor.h\"\n#include \"uart.h\"\n"
},
{
"change_ty... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | bip: add tablet mode for consistency
Hardware has supported tablet mode for a while, add firmware support for
tablet mode.
BRANCH=none
BUG=none
TEST=on bip, can use magnet to enter tablet mode.
Change-Id: I97202f1638732c9dcae641d3cf834a8d08b4a134
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1204698
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org> |
136,256 | 04.09.2018 14:08:02 | 21,600 | d6fc2d450496df392e99fc6ce2605fec0e9cfead | octopus: consolidate identical defines
All of the octopus board define the table mode option the same, so move
them into baseboard.
BRANCH=none
TEST=fleex still works | [
{
"change_type": "MODIFY",
"old_path": "baseboard/octopus/baseboard.h",
"new_path": "baseboard/octopus/baseboard.h",
"diff": "#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2\n#define CONFIG_PWM_KBLIGHT\n+/*******************************************************************************\n+ * Sensor Config\... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | octopus: consolidate identical defines
All of the octopus board define the table mode option the same, so move
them into baseboard.
BRANCH=none
BUG=none
TEST=fleex still works
Change-Id: Ibed874a609a2e5947d7aee39f915dc3046a0cc19
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1204700
Reviewed-by: Furquan Shaikh <furquan@chromium.org> |
136,219 | 22.08.2018 09:43:17 | 21,600 | e192f71aed932b88f3c42df4653a430a2e8ba10e | chip/npcx: Tidy up comments for init_hw_timer()
The comments suggest that this function only operates with ITIM16 timers
but it seems to support ITIM32 as well. Also it allows selecting the clock
source. Update the comments, hopefully making them correct.
BRANCH=none
TEST= make buildall -j50 | [
{
"change_type": "MODIFY",
"old_path": "chip/npcx/hwtimer.c",
"new_path": "chip/npcx/hwtimer.c",
"diff": "@@ -46,7 +46,7 @@ static volatile uint32_t cur_cnt_us_dbg;\n/* Internal functions */\nvoid init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source)\n{\n- /* Use internal 32K clock/APB2 for IT... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | chip/npcx: Tidy up comments for init_hw_timer()
The comments suggest that this function only operates with ITIM16 timers
but it seems to support ITIM32 as well. Also it allows selecting the clock
source. Update the comments, hopefully making them correct.
BUG=chromium:876737
BRANCH=none
TEST= make buildall -j50
Change-Id: Ic4ec2457cde2de55d51371f781d49bae80365989
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1185225 |
136,219 | 22.08.2018 09:43:17 | 21,600 | 4c1841b9f30a733c3bcb5fc5ed9b9bf3d7d61c19 | hwtimer: Tidy up and clarify some hw_clock comments
From what I can tell the counter has to tick over at the rate of 1MHz.
Update the comments to make that clear.
BRANCH=none
TEST= make buildall -j50 | [
{
"change_type": "MODIFY",
"old_path": "include/hwtimer.h",
"new_path": "include/hwtimer.h",
"diff": "/**\n* Programs when the next timer should fire an interrupt.\n- * deadline: timestamp of the event.\n+ *\n+ * The deadline is ahead of the current counter (which may of course wrap) by\n+ * the num... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | hwtimer: Tidy up and clarify some hw_clock comments
From what I can tell the counter has to tick over at the rate of 1MHz.
Update the comments to make that clear.
BUG=chromium:876737
BRANCH=none
TEST= make buildall -j50
Change-Id: Ib04731c10a68c544973b810cf70ce9ffba556b89
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1185230 |
136,340 | 31.08.2018 13:01:08 | 25,200 | 837c7609f290d4694c3912aaeb4562fbf4b59b8e | driver: lsm6dsm: Allow roundup to work below 13Hz
Recalculate ODR properly after rounding up the requested rate.
TEST=Check ODR is set properly
BRANCH=none | [
{
"change_type": "MODIFY",
"old_path": "driver/accelgyro_lsm6dsm.c",
"new_path": "driver/accelgyro_lsm6dsm.c",
"diff": "@@ -444,7 +444,7 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)\nif (rnd && (normalized_rate < rate)) {\nreg_val++;\n- normalized_rate *= 2;\n+ nor... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | driver: lsm6dsm: Allow roundup to work below 13Hz
Recalculate ODR properly after rounding up the requested rate.
BUG=b:112179405
TEST=Check ODR is set properly
BRANCH=none
Change-Id: I3f5abd5a1720f21d666cd3029000c2cec257c6f1
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1200067
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> |
136,414 | 24.08.2018 12:02:19 | -28,800 | 4173a851603b2e00b241150092292b5a29ba3be2 | cr50: Make SN data available through vNVRAM.
Defines a new virtual NV index, 0x13fff01 for SN data stored in INFO1.
TEST=tested locally on soraka
BRANCH=none | [
{
"change_type": "MODIFY",
"old_path": "board/cr50/tpm2/virtual_nvmem.c",
"new_path": "board/cr50/tpm2/virtual_nvmem.c",
"diff": "#include \"board_id.h\"\n#include \"console.h\"\n#include \"link_defs.h\"\n+#include \"sn_bits.h\"\n/*\n* Functions to allow access to non-NVRam data through NVRam Indexe... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cr50: Make SN data available through vNVRAM.
Defines a new virtual NV index, 0x13fff01 for SN data stored in INFO1.
BUG=b:111195266
TEST=tested locally on soraka
BRANCH=none
Change-Id: I7a057938a14effe9a5bd93b06a3450aa823d9ff5
Signed-off-by: Louis Collard <louiscollard@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1187860
Reviewed-by: Andrey Pronin <apronin@chromium.org> |
136,401 | 04.09.2018 13:54:21 | 21,600 | 0a61685bef7501b5028c8a3b5e4d7abfe05791e2 | Liara: Add supported batteries
These are two of the three batteries for Liara. Retain the Grunt
reference design battery for testing purposes only.
TEST=buildall
BRANCH=none | [
{
"change_type": "MODIFY",
"old_path": "board/liara/battery.c",
"new_path": "board/liara/battery.c",
"diff": "* address, mask, and disconnect value need to be provided.\n*/\nconst struct board_batt_params board_battery_info[] = {\n- /* Panasonic AP15O5L Battery Information */\n+ /*\n+ * Panasonic AP... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Liara: Add supported batteries
These are two of the three batteries for Liara. Retain the Grunt
reference design battery for testing purposes only.
BUG=b:113823864
TEST=buildall
BRANCH=none
Change-Id: Ibfdfa08298ec142504b24477746ebb87aebc913c
Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1204696
Reviewed-by: Jett Rink <jettrink@chromium.org> |
136,256 | 17.08.2018 13:34:05 | 21,600 | 7fdbe282d79bcb23f9507b3a128998e44285b451 | tcpm: add higher priority tasks to handle TCPC int
See go/usb-pd-slow-response-time for more information
BRANCH=none
TEST=CL stack on fleex and bobba consistently meet PD timing spec
Also tested that PD firmare upgrade still works (uses PD suspend) on
phaser. | [
{
"change_type": "MODIFY",
"old_path": "common/usb_pd_protocol.c",
"new_path": "common/usb_pd_protocol.c",
"diff": "@@ -2353,6 +2353,55 @@ static int pd_restart_tcpc(int port)\n}\n#endif\n+#ifdef HAS_TASK_PD_INT_C0\n+/* Events for pd_interrupt_handler_task */\n+#define PD_PROCESS_INTERRUPT (1<<0)\n+... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | tcpm: add higher priority tasks to handle TCPC int
See go/usb-pd-slow-response-time for more information
BRANCH=none
BUG=b:112088135
TEST=CL stack on fleex and bobba consistently meet PD timing spec
Also tested that PD firmare upgrade still works (uses PD suspend) on
phaser.
Change-Id: If789e79dcb9b69bc7ab5cb729189ca7b651b3a46
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1185728 |
136,256 | 17.08.2018 13:34:43 | 21,600 | 7fafaf999ff6d3b3565278a77fdba0a9ee1e26fe | octopus: use higher priority TCPC interrupt tasks
See go/usb-pd-slow-response-time for more information
BRANCH=none
TEST=CL stack on fleex and bobba consistently meet PD timing spec | [
{
"change_type": "MODIFY",
"old_path": "baseboard/octopus/baseboard.h",
"new_path": "baseboard/octopus/baseboard.h",
"diff": "#ifndef __ASSEMBLER__\n+#include \"gpio_signal.h\"\n+\nenum power_signal {\n#ifdef CONFIG_POWER_S0IX\nX86_SLP_S0_N, /* PCH -> SLP_S0_L */\n@@ -276,6 +278,10 @@ void board_res... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | octopus: use higher priority TCPC interrupt tasks
See go/usb-pd-slow-response-time for more information
BRANCH=none
BUG=b:112088135
TEST=CL stack on fleex and bobba consistently meet PD timing spec
Change-Id: I9eabf8de8d866f5a0af7d1daba5ab585b418d26c
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1185729
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org> |
136,414 | 28.08.2018 18:46:54 | -28,800 | a9a397fa62c4c946c96511356a5e6b6017af932f | cr50: Move Virtual NVRAM indexes into header file.
This is so that they can be referenced outside of the cr50
codebase.
TEST=build
BRANCH=none | [
{
"change_type": "MODIFY",
"old_path": "board/cr50/tpm2/virtual_nvmem.c",
"new_path": "board/cr50/tpm2/virtual_nvmem.c",
"diff": "#include \"console.h\"\n#include \"link_defs.h\"\n#include \"sn_bits.h\"\n+#include \"virtual_nvmem.h\"\n/*\n* Functions to allow access to non-NVRam data through NVRam I... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cr50: Move Virtual NVRAM indexes into header file.
This is so that they can be referenced outside of the cr50
codebase.
BUG=b:110971075
TEST=build
BRANCH=none
Change-Id: Id0754d2b1c9817aeb3db4d4d01ee9fbce8ca2a10
Signed-off-by: Louis Collard <louiscollard@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1193563
Reviewed-by: Andrey Pronin <apronin@chromium.org> |
136,274 | 07.09.2018 11:00:04 | 25,200 | a426c81612527354a14f45c9a43d9bd1f7fa8d0e | servo_updater: more informative error on fail
'Can't detect updater version' is replaced with an error
specifying the failed regex string.
BRANCH=None
TEST=None | [
{
"change_type": "MODIFY",
"old_path": "extra/usb_updater/servo_updater.py",
"new_path": "extra/usb_updater/servo_updater.py",
"diff": "@@ -137,7 +137,8 @@ def do_updater_version(vidpid, iface, serialno):\nreturn 2\nelse:\nreturn 6\n- return 0\n+ raise ServoUpdaterException(\n+ \"Can't determine upd... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | servo_updater: more informative error on fail
'Can't detect updater version' is replaced with an error
specifying the failed regex string.
BRANCH=None
BUG=None
TEST=None
Change-Id: Ia3a52ee27e31d0b4aab0d8f04d5cf5f346498c37
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1213556
Reviewed-by: Mary Ruthven <mruthven@chromium.org> |
136,256 | 04.09.2018 10:19:25 | 21,600 | f48bb683973e10a008eaf0d327ea15d0062bfc1e | octopus: disable tablet mode switch for clamshells
BRANCH=none
TEST=verified that free magnet cannot put a clamshell SKU into tablet mode | [
{
"change_type": "MODIFY",
"old_path": "board/bobba/board.c",
"new_path": "board/bobba/board.c",
"diff": "#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)\n#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)\n+static uint8_t sku_id;\n+\nstatic void pp... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | octopus: disable tablet mode switch for clamshells
BRANCH=none
BUG=b:113837268
TEST=verified that free magnet cannot put a clamshell SKU into tablet mode
Change-Id: I5d69ede2da04cb5d067b6ae5a483323054b584ab
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1204452 |
136,418 | 10.09.2018 04:34:14 | 25,200 | ab54765cf1c71d1f1a91ab08d68521b29d8fec76 | cheza: Config the SPI flash size to 1MB
The NPCX7M7WB has 1MB internal SPI flash. Config it correctly.
BRANCH=none
TEST=Checked the EC image size is 1MB. Ran flashrom to flash EC.
Tested-by: Philip Chen | [
{
"change_type": "MODIFY",
"old_path": "board/cheza/board.h",
"new_path": "board/cheza/board.h",
"diff": "#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */\n/* Internal SPI flash on NPCX7 */\n-#define CONFIG_FLASH_SIZE (512 * 1024) /* It's really 1MB. */\n+#define CONFIG_FLASH_SIZE (1024 *... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cheza: Config the SPI flash size to 1MB
The NPCX7M7WB has 1MB internal SPI flash. Config it correctly.
BRANCH=none
BUG=b:114686845
TEST=Checked the EC image size is 1MB. Ran flashrom to flash EC.
Change-Id: Ie0ed27f72019790cfeb283349ae28fd05dc9693a
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1215882
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org> |
136,230 | 10.09.2018 23:33:53 | 25,200 | a7666732094a81ffc322f52d8b29b0018e0367fb | cheza: Enable RTC EC/host command
BRANCH=none
TEST='rtc' command in ec console and 'ectool rtcget' in ap console
Commit-Ready: ChromeOS CL Exonerator Bot
Tested-by: Philip Chen | [
{
"change_type": "MODIFY",
"old_path": "board/cheza/board.h",
"new_path": "board/cheza/board.h",
"diff": "#define CONFIG_USBC_VCONN\n#define CONFIG_USBC_VCONN_SWAP\n+/* RTC */\n+#define CONFIG_CMD_RTC\n+#define CONFIG_HOSTCMD_RTC\n+\n/* Sensors */\n#define CONFIG_ACCELGYRO_BMI160\n#define CONFIG_ACC... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cheza: Enable RTC EC/host command
BUG=b:115281114
BRANCH=none
TEST='rtc' command in ec console and 'ectool rtcget' in ap console
Change-Id: Id659b873fa24696cc2b883832f85e0d3202158ad
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1218583
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com> |
136,197 | 12.09.2018 14:25:31 | 25,200 | 2c760cf30b95715791eb43701b3d5536558b3a8d | flash: Add CONFIG_FLASH_READOUT_PROTECTION config option
Instead of tying together CONFIG_WP_ALWAYS and RDP protection,
separate the options.
BRANCH=nocturne
TEST=make buildall -j | [
{
"change_type": "MODIFY",
"old_path": "board/coffeecake/board.h",
"new_path": "board/coffeecake/board.h",
"diff": "/* No Write-protect GPIO, force the write-protection */\n#define CONFIG_WP_ALWAYS\n+#define CONFIG_FLASH_READOUT_PROTECTION\n#ifndef __ASSEMBLER__\n"
},
{
"change_type": "MODIF... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | flash: Add CONFIG_FLASH_READOUT_PROTECTION config option
Instead of tying together CONFIG_WP_ALWAYS and RDP protection,
separate the options.
BRANCH=nocturne
BUG=b:111330723
TEST=make buildall -j
Change-Id: I905b573a900ef4dd0431666c525c951582143e09
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1222093
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,305 | 11.09.2018 15:52:03 | 21,600 | ca25c78f48ed3fb6b52945afa9b5d83136f07c08 | Ampton: create initial EC image
This image is based on bip from current ToT and the most recent ampton
schematics. Bugs have been created and put into TODO statements for
the future work needed on this EC image.
BRANCH=None
TEST=builds | [
{
"change_type": "ADD",
"old_path": null,
"new_path": "board/ampton/battery.c",
"diff": "+/* Copyright 2018 The Chromium OS Authors. All rights reserved.\n+ * Use of this source code is governed by a BSD-style license that can be\n+ * found in the LICENSE file.\n+ *\n+ * Battery pack vendor provided... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Ampton: create initial EC image
This image is based on bip from current ToT and the most recent ampton
schematics. Bugs have been created and put into TODO statements for
the future work needed on this EC image.
BRANCH=None
BUG=b:111498206
TEST=builds
Change-Id: Idff972b9ce5231524dd4865a87953ebcd5310c62
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1225350
Reviewed-by: Justin TerAvest <teravest@chromium.org> |
136,427 | 27.08.2018 19:01:32 | 21,600 | 40c522b2dbfd3392f708fd58e3de9e6bc66d07a4 | pd: Cleanup lpm_debounce_deadlines and tasks_waiting_on_reset
Move lpm_debounce_deadlines and tasks_waiting_on_reset into
struct pd_protocol.
BRANCH=none
TEST=PD and TCPC low power still work on Grunt | [
{
"change_type": "MODIFY",
"old_path": "common/usb_pd_protocol.c",
"new_path": "common/usb_pd_protocol.c",
"diff": "@@ -186,6 +186,13 @@ static struct pd_protocol {\nuint64_t try_src_marker;\n#endif\n+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER\n+ /* Time to enter low power mode */\n+ uint64_t low_power_tim... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | pd: Cleanup lpm_debounce_deadlines and tasks_waiting_on_reset
Move lpm_debounce_deadlines and tasks_waiting_on_reset into
struct pd_protocol.
BRANCH=none
BUG=b:111663127
TEST=PD and TCPC low power still work on Grunt
Change-Id: Ied7777175f0b9a8efbda42ecbc4b9147d5564649
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194350
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org> |
136,427 | 27.08.2018 20:03:58 | 21,600 | e3b4438f26ba24d3bb97345da8717225436bbe0a | pd: Change tcpm_set_drp_toggle() to tcpm_enable_drp_toggle()
Change tcpm_set_drp_toggle() to tcpm_enable_drp_toggle(), since enable=0
was unused.
BRANCH=none
TEST=PD and TCPC low power still work on Grunt | [
{
"change_type": "MODIFY",
"old_path": "common/usb_pd_protocol.c",
"new_path": "common/usb_pd_protocol.c",
"diff": "@@ -3831,7 +3831,7 @@ void pd_task(void *u)\npd_set_power_role(port, PD_ROLE_SOURCE);\ntimeout = 2*MSEC;\n} else {\n- tcpm_set_drp_toggle(port, 1);\n+ tcpm_enable_drp_toggle(port);\npd... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | pd: Change tcpm_set_drp_toggle() to tcpm_enable_drp_toggle()
Change tcpm_set_drp_toggle() to tcpm_enable_drp_toggle(), since enable=0
was unused.
BRANCH=none
BUG=b:111663127
TEST=PD and TCPC low power still work on Grunt
Change-Id: I760a067b11984a579261deac856419d46400497b
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194353
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org> |
136,237 | 18.09.2018 15:59:06 | -28,800 | 178d079bb63431078e25c56bb4472fa77b534d5e | Bobba: Support new SKU ID
SKU ID of Bobba360, Sparky360: 9, 10, 11, 12, 25, 26
BRANCH=none
TEST=compile pass
Tested-by: Ryan Zhang | [
{
"change_type": "MODIFY",
"old_path": "board/bobba/board.c",
"new_path": "board/bobba/board.c",
"diff": "@@ -203,8 +203,9 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);\nstatic int board_is_convertible(void)\n{\n- /* SKU ID of Bobba360, Sparky360, & unprovisioned: 9, 25, 26, 255 ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Bobba: Support new SKU ID
SKU ID of Bobba360, Sparky360: 9, 10, 11, 12, 25, 26
BUG=b:112442777
BRANCH=none
TEST=compile pass
Change-Id: Idd85c48a1dc7bc663d91fc3b909a86e699aad622
Signed-off-by: Tino Liu <tino.liu@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1229474
Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Reviewed-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org> |
136,412 | 19.09.2018 18:41:06 | 25,200 | 6e410ccca37239c12b9c5317c8a112e6fba2b0a2 | fpsensor: add a version to the template format
The first 2 bytes of the metadata structure contain the version of the
format of that structure.
BRANCH=nocturne
TEST=enroll/logout/unlock | [
{
"change_type": "MODIFY",
"old_path": "common/fpsensor.c",
"new_path": "common/fpsensor.c",
"diff": "#define FP_MAX_FINGER_COUNT 0\n#endif\n#define SBP_ENC_KEY_LEN 16\n+#define FP_TEMPLATE_FORMAT_VERSION 1\n#define FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE \\\n(FP_ALGORITHM_TEMPLATE_SIZE + \\\nsizeof(st... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | fpsensor: add a version to the template format
The first 2 bytes of the metadata structure contain the version of the
format of that structure.
BRANCH=nocturne
BUG=b:73337313
TEST=enroll/logout/unlock
Change-Id: I1838791603df11fdefb373105617f83eec116f89
Signed-off-by: Nicolas Norvez <norvez@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1235413
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,282 | 20.09.2018 10:58:04 | -28,800 | fac4b5b8552b9c3dbf20eb96fc67b137878aaedc | grunt: Disable ec_feature kbbacklit by SKUID for barla
Disable kbbacklit support for barla.
BRANCH=grunt
TEST=make buildall -j. | [
{
"change_type": "MODIFY",
"old_path": "baseboard/grunt/baseboard.c",
"new_path": "baseboard/grunt/baseboard.c",
"diff": "@@ -516,7 +516,8 @@ uint32_t board_override_feature_flags0(uint32_t flags0)\n* check if the current device is one of them and return\n* the default value - with backlight here.\n... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | grunt: Disable ec_feature kbbacklit by SKUID for barla
Disable kbbacklit support for barla.
BUG=b:115882609
BRANCH=grunt
TEST=make buildall -j.
Change-Id: I966938bad94e1c63757a55df750fdbca862b671e
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/1235475
Reviewed-by: Edward Hill <ecgh@chromium.org> |
136,412 | 21.09.2018 10:37:04 | 25,200 | 5c70df5b3aea27f8d8dc2698b98b0147f366cc1e | aes-gcm: set tag size to 16 bytes in perf test
Use a 16-byte tag instead of 12 bytes.
BRANCH=nocturne
TEST=make BOARD=nocturne_fp test-aes -j
TEST=make run-aes | [
{
"change_type": "MODIFY",
"old_path": "test/aes.c",
"new_path": "test/aes.c",
"diff": "@@ -362,7 +362,7 @@ static void test_aes_gcm_speed(void)\n0x00, 0x00, 0x00, 0x00,\n};\nconst int nonce_size = sizeof(nonce);\n- uint8_t tag[12] = {0};\n+ uint8_t tag[16] = {0};\nconst int tag_size = sizeof(tag);\... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | aes-gcm: set tag size to 16 bytes in perf test
Use a 16-byte tag instead of 12 bytes.
BRANCH=nocturne
BUG=b:111160949
TEST=make BOARD=nocturne_fp test-aes -j
TEST=make run-aes
Change-Id: I9d1d28ec2049590b407eb9ea64d412c29d46b20b
Signed-off-by: Nicolas Norvez <norvez@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1239237
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,412 | 18.09.2018 20:11:32 | 25,200 | fca03b5d61dd2673a6ebcc0aefcbae717d2dd812 | fpsensor: safer argument checking
Ensure that size/offset parameters passed from the AP can't overflow the
buffer, and that their sum doesn't either. Clearer parameter checking.
BRANCH=nocturne
TEST=enroll/match | [
{
"change_type": "MODIFY",
"old_path": "common/fpsensor.c",
"new_path": "common/fpsensor.c",
"diff": "@@ -539,27 +539,44 @@ static int aes_gcm_decrypt(const uint8_t *key, int key_size, uint8_t *plaintext,\nreturn EC_RES_SUCCESS;\n}\n+static int validate_fp_buffer_offset(const uint32_t buffer_size,\n... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | fpsensor: safer argument checking
Ensure that size/offset parameters passed from the AP can't overflow the
buffer, and that their sum doesn't either. Clearer parameter checking.
BUG=b:73337313
BUG=b:116065496
BRANCH=nocturne
TEST=enroll/match
Change-Id: I73600c7d5874329c9a5f19b1bf88603e97d02c7d
Signed-off-by: Nicolas Norvez <norvez@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1234750
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,396 | 20.09.2018 19:10:34 | 25,200 | 673fbe0d71316d3f1a11467bc7995c18e3a91878 | servo_updater: account for versions starting with v2
With resent base tag update the hardcoded version number pattern
in servo_updater.py needs to be adjusted.
BRANCH=none
TEST=TBD | [
{
"change_type": "MODIFY",
"old_path": "extra/usb_updater/servo_updater.py",
"new_path": "extra/usb_updater/servo_updater.py",
"diff": "@@ -128,11 +128,14 @@ def do_updater_version(vidpid, iface, serialno):\n\"\"\"\nvers = do_version(vidpid, iface, serialno)\n- m = re.search('_v1.1.(\\d\\d\\d\\d)', ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | servo_updater: account for versions starting with v2
With resent base tag update the hardcoded version number pattern
in servo_updater.py needs to be adjusted.
BRANCH=none
BUG=b:112475211
TEST=TBD
Change-Id: If3b18f563ff48eb98db95864d8f2298ead04495d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1237714
Reviewed-by: Nick Sanders <nsanders@chromium.org> |
136,208 | 13.09.2018 14:41:51 | -28,800 | 56d600bb39433f804db4cc45e2b32fd6523b2316 | math_util: Support fixed-point sqrtf fp_sqrtf.
TEST=make buildall -j
BRANCH=None
Commit-Ready: ChromeOS CL Exonerator Bot
Tested-by: Yilun Lin | [
{
"change_type": "MODIFY",
"old_path": "common/math_util.c",
"new_path": "common/math_util.c",
"diff": "@@ -86,10 +86,16 @@ static inline int int_sqrtf(fp_inter_t x)\n{\nreturn sqrtf(x);\n}\n+\n+/* If the platform support FPU, just return sqrtf. */\n+fp_t fp_sqrtf(fp_t x)\n+{\n+ return sqrtf(x);\n+}... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | math_util: Support fixed-point sqrtf fp_sqrtf.
TEST=make buildall -j
BUG=b:113364863
BRANCH=None
Change-Id: I63ee741a08e39cf6f234a2131137144c46ae0bbd
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1235476
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,285 | 10.09.2018 13:42:17 | 25,200 | c7b2b4ab2a4b8d4ba95be6ea5c4bd2bc65a9fd0f | Refactor ADC clock enable for STM32F0/F3
Refactor ADC clock enable code to use clock_module_enable()
BRANCH=master
TEST=Build and run on discovery-stm32f072
Commit-Ready: ChromeOS CL Exonerator Bot | [
{
"change_type": "MODIFY",
"old_path": "chip/stm32/adc-stm32f0.c",
"new_path": "chip/stm32/adc-stm32f0.c",
"diff": "@@ -304,7 +304,7 @@ static void adc_init(void)\nreturn;\n/* Enable ADC clock */\n- STM32_RCC_APB2ENR |= (1 << 9);\n+ clock_enable_module(MODULE_ADC, 1);\n/* check HSI14 in RCC ? ON by ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Refactor ADC clock enable for STM32F0/F3
Refactor ADC clock enable code to use clock_module_enable()
BUG=none
BRANCH=master
TEST=Build and run on discovery-stm32f072
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Change-Id: Id3e8852fd5dd2fe47351dd9b9f84b0be9fb82dda
Reviewed-on: https://chromium-review.googlesource.com/1217602
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Nick Sanders <nsanders@chromium.org> |
136,256 | 26.09.2018 10:12:07 | 21,600 | 47cfe9cfe62427d24babddd1f8e9dae88b1cb7d8 | ps8751: set 0x39 as min version if vbus detect
We know that the PS8751 TCPC needs to have firmware version 0x39 or
higher to support properly detecting Vbus presence.
BRANCH=none
TEST=min version for ps8751 is reported correctly | [
{
"change_type": "MODIFY",
"old_path": "driver/tcpm/ps8xxx.c",
"new_path": "driver/tcpm/ps8xxx.c",
"diff": "@@ -152,6 +152,15 @@ static int ps8xxx_get_chip_info(int port, int renew,\n(*chip_info)->fw_version_number = val;\n+#if defined(CONFIG_USB_PD_TCPM_PS8751) && \\\n+ defined(CONFIG_USB_PD_VBUS_D... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | ps8751: set 0x39 as min version if vbus detect
We know that the PS8751 TCPC needs to have firmware version 0x39 or
higher to support properly detecting Vbus presence.
BRANCH=none
BUG=b:116068318
TEST=min version for ps8751 is reported correctly
Change-Id: I83c7587c5b9792659ecb876039e6c460f242d432
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1246265
Reviewed-by: Justin TerAvest <teravest@chromium.org> |
136,401 | 28.09.2018 13:11:26 | 21,600 | c06af8d8c2326a3ebc096dfaa4a2640c1ded1333 | i2c: Elide vestigial comment
TEST=buildall
BRANCH=none | [
{
"change_type": "MODIFY",
"old_path": "common/i2c_master.c",
"new_path": "common/i2c_master.c",
"diff": "@@ -352,9 +352,7 @@ int i2c_write_block(int port, int slave_addr, int offset, const uint8_t *data,\n/*\n* Split into two transactions to avoid the stack space consumption of\n- * appending the d... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | i2c: Elide vestigial comment
TEST=buildall
BRANCH=none
BUG=none
Change-Id: Ifd211a9e37cbb0f2a613a5a5573a7ee8b9315604
Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1252327
Reviewed-by: Edward Hill <ecgh@chromium.org> |
136,239 | 01.10.2018 15:04:53 | 25,200 | 3b4fc2b09524444b6d892c90d6c5d3150c94686a | fpsensor: Clear reset bit only after reset completes
BRANCH=nocturne
TEST=Build, check that boot works. | [
{
"change_type": "MODIFY",
"old_path": "common/fpsensor.c",
"new_path": "common/fpsensor.c",
"diff": "@@ -296,9 +296,9 @@ void fp_task(void)\nif (mode & FP_MODE_ANY_WAIT_IRQ) {\ngpio_enable_interrupt(GPIO_FPS_INT);\n} else if (mode & FP_MODE_RESET_SENSOR) {\n- sensor_mode &= ~FP_MODE_RESET_SENSOR;\n... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | fpsensor: Clear reset bit only after reset completes
BUG=b:110805729
BRANCH=nocturne
TEST=Build, check that boot works.
Change-Id: If54978429431149f5aabcc9b2e531f5a80432c60
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1256054
Reviewed-by: Nicolas Norvez <norvez@chromium.org> |
136,427 | 02.10.2018 13:05:32 | 21,600 | 99d9bd68c45045ec3004ca420c462bab32addfeb | grunt: Remove no longer needed GPIO_EN_PP5000
The BQ24392 driver was renamed to MAX14637 (CL:1250031) and no
longer requires GPIO_EN_PP5000 to be defined (CL:1250032), so
this can be removed from grunt-family gpio.inc.
BRANCH=grunt
TEST=make -j buildall | [
{
"change_type": "MODIFY",
"old_path": "board/aleena/gpio.inc",
"new_path": "board/aleena/gpio.inc",
"diff": "@@ -41,9 +41,6 @@ GPIO(APU_ALERT_L, PIN(A, 2), GPIO_INPUT) /* Alert to SOC */\nGPIO(3AXIS_INT_L, PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V) /* 3 Axis Accel */\nGPIO(KB_BL_EN, PIN(F, 2), GPIO_OUT... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | grunt: Remove no longer needed GPIO_EN_PP5000
The BQ24392 driver was renamed to MAX14637 (CL:1250031) and no
longer requires GPIO_EN_PP5000 to be defined (CL:1250032), so
this can be removed from grunt-family gpio.inc.
BUG=none
BRANCH=grunt
TEST=make -j buildall
Change-Id: I186ece073e544760d487489f874659226c820bd8
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1257644
Reviewed-by: Scott Collyer <scollyer@chromium.org> |
136,418 | 01.10.2018 15:08:49 | 25,200 | 89e438e5061f11fa3e2e9e2b7b3cf4df088d0a82 | cheza: Enable host commands flashspiinfo and uptimeinfo
Enable ectool to get:
* SPI flash info;
* uptime and reset info (for bringup, will be disabled on release).
BRANCH=none
TEST=ectool flashspiinfo
TEST=ectool uptimeinfo | [
{
"change_type": "MODIFY",
"old_path": "board/cheza/board.h",
"new_path": "board/cheza/board.h",
"diff": "#define CONFIG_BRINGUP\n#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */\n#define CONFIG_USB_PD_DEBUG_LEVEL 3\n+#define CONFIG_CMD_AP_RESET_LOG\n/*\n* By default, enable all consol... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cheza: Enable host commands flashspiinfo and uptimeinfo
Enable ectool to get:
* SPI flash info;
* uptime and reset info (for bringup, will be disabled on release).
BRANCH=none
BUG=b:116841576
TEST=ectool flashspiinfo
TEST=ectool uptimeinfo
Change-Id: I8975cfb0c9f53b03a13c2b5be4632c8f656e5a92
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1257652
Reviewed-by: Philip Chen <philipchen@chromium.org> |
136,340 | 01.10.2018 14:41:45 | 25,200 | ae23d068b8830fc613bec9ad95d55a9d8f9ebb4d | FIXUP: sensor: Add flag for tight timestamping
Add description for tight timestamp in ectool inventory.
BRANCH=none
TEST=ectool does not print "Unknown feature" anymore. | [
{
"change_type": "MODIFY",
"old_path": "util/ectool.c",
"new_path": "util/ectool.c",
"diff": "@@ -637,6 +637,8 @@ static const char * const ec_feature_names[] = {\n[EC_FEATURE_HOST_EVENT64] = \"64-bit host events\",\n[EC_FEATURE_EXEC_IN_RAM] = \"Execute code in RAM\",\n[EC_FEATURE_CEC] = \"Consumer ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | FIXUP: sensor: Add flag for tight timestamping
Add description for tight timestamp in ectool inventory.
BUG=b:111079027,b:109786990
BRANCH=none
TEST=ectool does not print "Unknown feature" anymore.
Change-Id: Id51beb3c9bbd80be6c651b68960c61c9f0708cda
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1256049
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Enrico Granata <egranata@chromium.org> |
136,418 | 27.08.2018 16:03:28 | 25,200 | 3e1ab15b1daf39c9ba49423733c06da8ce5340ff | cheza: Change GPIO for the rev-3 board
Reflect the changes on the rev-3 board.
Move port-1 LED pins to PWM, remove DA9313 GPIO1 and EC_SELF_RST.
Empty KSO pins.
BRANCH=none
TEST=Verified the GPIO functions on a r3 board. | [
{
"change_type": "MODIFY",
"old_path": "board/cheza/gpio.inc",
"new_path": "board/cheza/gpio.inc",
"diff": "@@ -23,7 +23,7 @@ GPIO_INT(ACCEL_GYRO_INT_L, PIN(D, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi1\nGPIO_INT(AC_PRESENT, PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt) /* ACOK_OD */\nGPIO_INT(POWER... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cheza: Change GPIO for the rev-3 board
Reflect the changes on the rev-3 board.
Move port-1 LED pins to PWM, remove DA9313 GPIO1 and EC_SELF_RST.
Empty KSO pins.
BRANCH=none
BUG=b:112080059, b:111519662, b:111391913
TEST=Verified the GPIO functions on a r3 board.
Change-Id: Ieeed097a3f1d5892c9360125d0234ca7d977b154
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1194344 |
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