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/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module bt656cap_ctlif #(
parameter csr_addr = 4'h0,
parameter fml_depth = 27
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output reg irq,
output reg [1:0] field_filter,
input in_frame,
output reg [fml_depth-1-5:0] fml_adr_base,
input start_of_frame,
input next_burst,
output reg last_burst,
inout sda,
output reg sdc
);
/* I2C */
reg sda_1;
reg sda_2;
reg sda_oe;
reg sda_o;
always @(posedge sys_clk) begin
sda_1 <= sda;
sda_2 <= sda_1;
end
assign sda = (sda_oe & ~sda_o) ? 1'b0 : 1'bz;
/* CSR IF */
wire csr_selected = csr_a[13:10] == csr_addr;
reg [14:0] max_bursts;
reg [14:0] done_bursts;
always @(posedge sys_clk) begin
if(sys_rst) begin
csr_do <= 32'd0;
field_filter <= 2'd0;
fml_adr_base <= {fml_depth-5{1'b0}};
max_bursts <= 15'd12960;
sda_oe <= 1'b0;
sda_o <= 1'b0;
sdc <= 1'b0;
end else begin
csr_do <= 32'd0;
if(csr_selected) begin
if(csr_we) begin
case(csr_a[2:0])
3'd0: begin
sda_o <= csr_di[1];
sda_oe <= csr_di[2];
sdc <= csr_di[3];
end
3'd1: field_filter <= csr_di[1:0];
3'd2: fml_adr_base <= csr_di[fml_depth-1:5];
3'd3: max_bursts <= csr_di[14:0];
endcase
end
case(csr_a[2:0])
3'd0: csr_do <= {sdc, sda_oe, sda_o, sda_2};
3'd1: csr_do <= {in_frame, field_filter};
3'd2: csr_do <= {fml_adr_base, 5'd0};
3'd3: csr_do <= max_bursts;
3'd4: csr_do <= done_bursts;
endcase
end
end
end
reg in_frame_r;
always @(posedge sys_clk) begin
if(sys_rst) begin
in_frame_r <= 1'b0;
irq <= 1'b0;
end else begin
in_frame_r <= in_frame;
irq <= in_frame_r & ~in_frame;
end
end
reg [14:0] burst_counter;
always @(posedge sys_clk) begin
if(sys_rst) begin
last_burst <= 1'b0;
burst_counter <= 15'd0;
end else begin
if(start_of_frame) begin
last_burst <= 1'b0;
burst_counter <= 15'd0;
done_bursts <= burst_counter;
end
if(next_burst) begin
burst_counter <= burst_counter + 15'd1;
last_burst <= (burst_counter + 15'd1) == max_bursts;
end
end
end
endmodule
|
// $Id: aeMB_core.v,v 1.9 2007/11/23 14:06:41 sybreon Exp $
//
// AEMB 32'bit RISC MICROPROCESSOR CORE
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <>
//
// This file is part of AEMB.
//
// AEMB is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// AEMB is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
// Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// HISTORY
// $Log: aeMB_core.v,v $
// Revision 1.9 2007/11/23 14:06:41 sybreon
// Old version deprecated.
//
// Revision 1.8 2007/10/22 19:12:59 sybreon
// Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.
//
// Revision 1.7 2007/05/30 18:44:30 sybreon
// Added interrupt support.
//
// Revision 1.6 2007/05/17 09:08:21 sybreon
// Removed asynchronous reset signal.
//
// Revision 1.5 2007/04/27 00:23:55 sybreon
// Added code documentation.
// Improved size & speed of rtl/verilog/aeMB_aslu.v
//
// Revision 1.4 2007/04/25 22:15:04 sybreon
// Added support for 8-bit and 16-bit data types.
//
// Revision 1.3 2007/04/11 04:30:43 sybreon
// Added pipeline stalling from incomplete bus cycles.
// Separated sync and async portions of code.
//
// Revision 1.2 2007/04/04 06:13:23 sybreon
// Removed unused signals
//
// Revision 1.1 2007/03/09 17:52:17 sybreon
// initial import
//
module aeMB_core (/*AUTOARG*/
// Outputs
iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
// Inputs
sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i,
fsl_ack_i, dwb_dat_i, dwb_ack_i
);
// Instruction WB address space
parameter ISIZ = 32;
// Data WB address space
parameter DSIZ = 32;
// Multiplier
parameter MUL = 1;
// Barrel Shifter
parameter BSF = 1;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [DSIZ-1:2] dwb_adr_o; // From edk32 of aeMB_edk32.v
output [31:0] dwb_dat_o; // From edk32 of aeMB_edk32.v
output [3:0] dwb_sel_o; // From edk32 of aeMB_edk32.v
output dwb_stb_o; // From edk32 of aeMB_edk32.v
output dwb_wre_o; // From edk32 of aeMB_edk32.v
output [6:2] fsl_adr_o; // From edk32 of aeMB_edk32.v
output [31:0] fsl_dat_o; // From edk32 of aeMB_edk32.v
output fsl_stb_o; // From edk32 of aeMB_edk32.v
output [1:0] fsl_tag_o; // From edk32 of aeMB_edk32.v
output fsl_wre_o; // From edk32 of aeMB_edk32.v
output [ISIZ-1:2] iwb_adr_o; // From edk32 of aeMB_edk32.v
output iwb_stb_o; // From edk32 of aeMB_edk32.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input dwb_ack_i; // To edk32 of aeMB_edk32.v
input [31:0] dwb_dat_i; // To edk32 of aeMB_edk32.v
input fsl_ack_i; // To edk32 of aeMB_edk32.v
input [31:0] fsl_dat_i; // To edk32 of aeMB_edk32.v
input iwb_ack_i; // To edk32 of aeMB_edk32.v
input [31:0] iwb_dat_i; // To edk32 of aeMB_edk32.v
input sys_clk_i; // To edk32 of aeMB_edk32.v
input sys_int_i; // To edk32 of aeMB_edk32.v
input sys_rst_i; // To edk32 of aeMB_edk32.v
// End of automatics
/*AUTOWIRE*/
// INSTANTIATIONS /////////////////////////////////////////////////////////////////
/*
aeMB_edk32 AUTO_TEMPLATE (
.dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
.iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
);
*/
aeMB_edk32 #(ISIZ, DSIZ, MUL, BSF)
edk32 (/*AUTOINST*/
// Outputs
.dwb_adr_o (dwb_adr_o[DSIZ-1:2]), // Templated
.dwb_dat_o (dwb_dat_o[31:0]),
.dwb_sel_o (dwb_sel_o[3:0]),
.dwb_stb_o (dwb_stb_o),
.dwb_wre_o (dwb_wre_o),
.fsl_adr_o (fsl_adr_o[6:2]),
.fsl_dat_o (fsl_dat_o[31:0]),
.fsl_stb_o (fsl_stb_o),
.fsl_tag_o (fsl_tag_o[1:0]),
.fsl_wre_o (fsl_wre_o),
.iwb_adr_o (iwb_adr_o[ISIZ-1:2]), // Templated
.iwb_stb_o (iwb_stb_o),
// Inputs
.dwb_ack_i (dwb_ack_i),
.dwb_dat_i (dwb_dat_i[31:0]),
.fsl_ack_i (fsl_ack_i),
.fsl_dat_i (fsl_dat_i[31:0]),
.iwb_ack_i (iwb_ack_i),
.iwb_dat_i (iwb_dat_i[31:0]),
.sys_int_i (sys_int_i),
.sys_clk_i (sys_clk_i),
.sys_rst_i (sys_rst_i));
endmodule // aeMB_core
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTN_1_V
`define SKY130_FD_SC_LS__DLRTN_1_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTN_1_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module start_for_CvtColomb6_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module start_for_CvtColomb6 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_CvtColomb6_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_start_for_CvtColomb6_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mult30_9.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mult30_9 (
clock,
dataa,
datab,
result);
input clock;
input [29:0] dataa;
input [8:0] datab;
output [38:0] result;
wire [38:0] sub_wire0;
wire [38:0] result = sub_wire0[38:0];
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.clock (clock),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 30,
lpm_mult_component.lpm_widthb = 9,
lpm_mult_component.lpm_widthp = 39;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "30"
// Retrieval info: PRIVATE: WidthB NUMERIC "9"
// Retrieval info: PRIVATE: WidthP NUMERIC "39"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "30"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "39"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: dataa 0 0 30 0 INPUT NODEFVAL dataa[29..0]
// Retrieval info: USED_PORT: datab 0 0 9 0 INPUT NODEFVAL datab[8..0]
// Retrieval info: USED_PORT: result 0 0 39 0 OUTPUT NODEFVAL result[38..0]
// Retrieval info: CONNECT: @dataa 0 0 30 0 dataa 0 0 30 0
// Retrieval info: CONNECT: result 0 0 39 0 @result 0 0 39 0
// Retrieval info: CONNECT: @datab 0 0 9 0 datab 0 0 9 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9_wave*.jpg FALSE
// Retrieval info: LIB_FILE: lpm
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2016-2020 NUDT, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//Vendor: NUDT
//Version: 0.1
//Filename: user_mux.v
//Target Device: Altera
//Dscription:
// 1)receive up cpu and lookup hit pkt stream
// 2)judge these 2 stream ,mux them to 1 single stream
// 3)
//
// pkt type:
// pkt_site 2bit : 2'b01 pkt head / 2'b11 pkt body / 2'b10 pkt tail
// invalid 4bit : the invalid byte sum of every payload cycle
// payload 128bit : pkt payload
//
//
//Author :
//Revision List:
// rn1: date: modifier: description:
// rn2: date: modifier: description:
//
module user_mux(
input clk,
input rst_n,
//lookup pkt waiting for transmit
input disp2usermux_data_wr,
input [133:0] disp2usermux_data,
input disp2usermux_valid_wr,
input disp2usermux_valid,
output usermux2disp_alf,
//up cpu pkt waiting for transmit
input up2usermux_data_wr,
input [133:0] up2usermux_data,
input up2usermux_valid_wr,
input up2usermux_valid,
output usermux2up_alf,
//transmit to down port
output reg usermux2down_data_wr,
output reg [133:0] usermux2down_data,
output reg usermux2down_valid_wr,
output usermux2down_valid,
input down2usermux_alf
);
//***************************************************
// Intermediate variable Declaration
//***************************************************
//all wire/reg/parameter variable
//should be declare below here
reg up_dfifo_rd;
wire [133:0] up_dfifo_rdata;
wire [7:0] up_dfifo_usedw;
reg up_vfifo_rd;
wire up_vfifo_rdata;
wire up_vfifo_empty;
reg disp_dfifo_rd;
wire [133:0] disp_dfifo_rdata;
wire [7:0] disp_dfifo_usedw;
reg disp_vfifo_rd;
wire disp_vfifo_rdata;
wire disp_vfifo_empty;
reg last_select;//which direction last pkt select
// 0:send up cpu's pkt 1: send dispute's pkt
reg grant_bit;//current pkt direction selecct
reg has_pkt;
reg [1:0] usermux_state;
//***************************************************
// Stream Judge
//***************************************************
always @ * begin
case({disp_vfifo_empty,up_vfifo_empty})
2'b00: begin has_pkt = 1'b1; grant_bit = ~last_select; end//both direction have pkt,so select different with last
2'b01: begin has_pkt = 1'b1; grant_bit = 1'b1; end//just dispcute have pkt need to sending
2'b10: begin has_pkt = 1'b1; grant_bit = 1'b0; end//just up cpu have pkt need to sending
2'b11: begin has_pkt = 1'b0; grant_bit = last_select; end//both no pkt,hold last select
endcase
end
//***************************************************
// Stream Judge
//***************************************************
assign usermux2disp_alf = disp_dfifo_usedw[7];
assign usermux2up_alf = up_dfifo_usedw[7];
assign usermux2down_valid = usermux2down_valid_wr;
localparam IDLE_S = 2'd0,
SEND_EXE_S = 2'd1,
SEND_UP_S = 2'd2;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
last_select <= 1'b0;
usermux2down_data_wr <= 1'b0;
usermux2down_valid_wr <= 1'b0;
up_dfifo_rd <= 1'b0;
up_vfifo_rd <= 1'b0;
disp_dfifo_rd <= 1'b0;
disp_vfifo_rd <= 1'b0;
usermux_state <= IDLE_S;
end
else begin
case(usermux_state)
IDLE_S: begin
usermux2down_data_wr <= 1'b0;
usermux2down_valid_wr <= 1'b0;
if((down2usermux_alf == 1'b0) && (has_pkt == 1'b1)) begin
//there is at least a pkt ,& next module can receive a pkt
last_select <= grant_bit;
if(grant_bit == 1'b0) begin//send up cpu's pkt
up_dfifo_rd <= 1'b1;
up_vfifo_rd <= 1'b1;
disp_dfifo_rd <= 1'b0;
disp_vfifo_rd <= 1'b0;
usermux_state <= SEND_UP_S;
end
else begin
up_dfifo_rd <= 1'b0;
up_vfifo_rd <= 1'b0;
disp_dfifo_rd <= 1'b1;
disp_vfifo_rd <= 1'b1;
usermux_state <= SEND_EXE_S;
end
end
else begin
up_dfifo_rd <= 1'b0;
up_vfifo_rd <= 1'b0;
disp_dfifo_rd <= 1'b0;
disp_vfifo_rd <= 1'b0;
usermux_state <= IDLE_S;
end
end
SEND_UP_S:begin
up_vfifo_rd <= 1'b0;
usermux2down_data_wr <= 1'b1;
usermux2down_data <= up_dfifo_rdata;
if(up_dfifo_rdata[133:132] == 2'b10)begin//end of pkt
up_dfifo_rd <= 1'b0;
usermux2down_valid_wr <= 1'b1;
usermux_state <= IDLE_S;
end
else begin
up_dfifo_rd <= 1'b1;
usermux2down_valid_wr <= 1'b0;
usermux_state <= SEND_UP_S;
end
end
SEND_EXE_S:begin
disp_vfifo_rd <= 1'b0;
usermux2down_data_wr <= 1'b1;
usermux2down_data <= disp_dfifo_rdata;
if(disp_dfifo_rdata[133:132] == 2'b10)begin//end of pkt
disp_dfifo_rd <= 1'b0;
usermux2down_valid_wr <= 1'b1;
usermux_state <= IDLE_S;
end
else begin
disp_dfifo_rd <= 1'b1;
usermux2down_valid_wr <= 1'b0;
usermux_state <= SEND_EXE_S;
end
end
default: begin
last_select <= 1'b0;
usermux2down_data_wr <= 1'b0;
usermux2down_valid_wr <= 1'b0;
up_dfifo_rd <= 1'b0;
up_vfifo_rd <= 1'b0;
disp_dfifo_rd <= 1'b0;
disp_vfifo_rd <= 1'b0;
usermux_state <= IDLE_S;
end
endcase
end
end
//***************************************************
// Other IP Instance
//***************************************************
//likely fifo/ram/async block....
//should be instantiated below here
fifo_256_134 up_dfifo(
.aclr(~rst_n),
.clock(clk),
.wrreq(up2usermux_data_wr),
.data(up2usermux_data),
.rdreq(up_dfifo_rd),
.q(up_dfifo_rdata),
.usedw(up_dfifo_usedw)
);
fifo_64_1 up_vfifo(
.aclr(~rst_n),
.clock(clk),
.wrreq(up2usermux_valid_wr),
.data(up2usermux_valid),
.rdreq(up_vfifo_rd),
.q(up_vfifo_rdata),
.empty(up_vfifo_empty)
);
fifo_256_134 disp_dfifo(
.aclr(~rst_n),
.clock(clk),
.wrreq(disp2usermux_data_wr),
.data(disp2usermux_data),
.rdreq(disp_dfifo_rd),
.q(disp_dfifo_rdata),
.usedw(disp_dfifo_usedw)
);
fifo_64_1 disp_vfifo(
.aclr(~rst_n),
.clock(clk),
.wrreq(disp2usermux_valid_wr),
.data(disp2usermux_valid),
.rdreq(disp_vfifo_rd),
.q(disp_vfifo_rdata),
.empty(disp_vfifo_empty)
);
endmodule
/**********************************
Initial Inst
user_mux user_mux(
.clk(clk),
.rst_n(rst_n),
//lookup pkt waiting for transmit
.disp2usermux_data_wr(disp2usermux_data_wr),
.disp2usermux_data(disp2usermux_data),
.disp2usermux_valid_wr(disp2usermux_valid_wr),
.disp2usermux_valid(disp2usermux_valid),
.usermux2disp_alf(usermux2disp_alf),
//up cpu pkt waiting for transmit
.up2usermux_data_wr(um2npe_data_wr),
.up2usermux_data(um2npe_data),
.up2usermux_valid_wr(um2npe_valid_wr),
.up2usermux_valid(um2npe_valid),
.usermux2up_alf(npe2um_alf),
//transmit to down port
.usermux2down_data_wr(um2cdp_data_wr),
.usermux2down_data(um2cdp_data),
.usermux2down_valid_wr(um2cdp_valid_wr),
.usermux2down_valid(um2cdp_valid),
.down2usermux_alf(cdp2um_alf)
);
**********************************/
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; int cnt = 0, val; for (int k = 0; k < n; k++) { cin >> val; cnt += val; } if (n == 1 && val == 1) cout << YES ; else if (cnt == n - 1 && n != 1) cout << YES ; else cout << NO ; return 0; }
|
//
// bsg_fifo_1r1w_pseudo_large
//
// MBT 3/11/15
//
// This fifo looks like a 1R1W fifo but actually is implemented
// with a 1RW FIFO for the bulk of its storage, and has a
// small 1R1W FIFO to help decouple reads and writes that may
// conflict. This FIFO is useful for cases where reads and writes
// each individually have a duty cycle of 50% or less.
//
// In 180 nm, the area of a 128x70 1R1W is about 1.75 the equivalent 1RW.
// The 2-element little fifo is about 0.25 the above 1RW. So the net
// savings is 1.25 versus 1.75; but that assumes the 1R1W has no overhead
// when in reality, it would probably have a 2-el fifo as well (e.g. 2.00).
// So this module does actually save area.
//
// For example, an element is written into the
// FIFO every other cycle, and an element is read from the FIFO
// every other cycle.
//
// _______________________________
// \ __________ \__|\ ____________
// \___/ 1RW FIFO \___| |__/ 1R1W FIFO \______
// \___big____/ | | \___little___/
// |/
//
// Data is inserted directly into the little fifo until
// that fifo is full. Then it is stored in
// the 1 port ram. When data is not enqued into the big fifo,
// and there is sufficient gauranteed space in the little fifo
// then data is transferred from the big fifo to the little fifo.
//
// Although both bsg_fifo_1r1w_pseudo_large and bsg_fifo_1r1w_large
// use 1RW rams, the pseudo fifo will be more area efficient for
// smaller FIFO sizes, because 1) it does not read as much data at a time
// and thus does not require as many sense amps (see your RAM compiler)
// and 2) the little FIFO is smaller than the associated "little fifo"
// serial-to-parallel registers of the 1r1w_large.
//
// * Enque Guarantees:
//
// In order to maintain the appearance of the 1R1W FIFO, this
// FIFO will always accept up to els_p data elements without saying
// that it is full. (These elements can be sent back-to-back, but this
// may starve out the little FIFO since it will not be able to
// access the 1RW FIFO.)
//
// * Deque non-guarantees and guarantees:
//
// As long as the duty cycle is <= 50 percent in any window of the input data stream
// that is twice the size of the parameter max_conflict_run_p, the FIFO will report
// that data is available when there is data available. If the user violates this
// parameter, the FIFO may be busy receiving data and potentially could report not
// having data when there is in fact data inside the FIFO.
//
// As long as you check the v_o signal, you will not lose data; but you may have periods
// where are unable to read because writes are occupying the bandwidth.
//
// On the other hand, if you have code that counts how many elements went into the FIFO,
// and then expects to deque that number of elements without checking the v_o bit, that
// code could fail.)
//
// (Another example: if the incoming data comes in bursts of N words, followed by
// a pause of at least N cycles, and the receiver reads data at most one word
// every other two cycles; then the FIFO will never report empty if it has data.)
//
// Parameters:
//
// max_conflict_run_p (N):
//
// First, the maximum # of sequential writes, N, that the FIFO can sustain before dropping
// below an average throughput of 1/2 because of structural hazards on the 1RW ram.
// This conflict run property is useful, for example, if we know that traffic comes in bursts
// of consecutive packets.
// Second, how many elements must be queued up before the FIFO starts
// using the large 1RW FIFO, which will likely consume a lot more power,
// after how many elements the effective throughput of the FIFO drops to 1/2.
// early_yumi_p: this parameter says whether the yumi signal comes in earlier
// which allows us to reduce latency between deque and the next element
// being transferred from the internal ram to the output, which in turns
// reduces how many FIFO elements are required by the setting of max_conflict_run_p
// Without early_yumi, this latency is
// 2+n cycles (yumi->BF deq->LF enq) where n is the number BF enques. early yumi
// changes this to (yumi/BF deq -> LF enq) or 1+n cycles.
// early_yumi_p can be used if the yumi signal is known early, and reduces the
// required little fifo size by 1 element to 1+n.
// [ Assertion to be formally proved: the FIFO size required for a conflict run size of n is 2+n.
// (yumi->BF deq->LF enq)+conflicts. So, your basic small FIFO should be at least 3 elements for
// enque patterns that do every-other cycle with an unknown relationship to the output, which
// is also every other cycle. The early yumi flag changes this parameter to
// (yumi/BF deq -> LF enq) +conflicts = 1+n = 2 elements ]
//
// (early_yumi_p allows the fifo to support 1/2 rate inputs and outputs with conflict runs of 1
// and only a twofer.)
// TODO: make max_conflict_run_p a parameter (and correspondingly parameterize little FIFO size
// and update control logic)
// add assertions that detect violation of the max conflict run
//
`include "bsg_defines.v"
module bsg_fifo_1r1w_pseudo_large #(parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
// Future extensions: need to add max_conflict_run_p;
// currently it is "1" and only if early_yumi_p = 1.
// to implement this, we need to parameterize the fifo
// to be of size (max_conflict_run_p+2-early_yumi_p)
// if yumi is on critical path; you can change this to 0.
// but to maintain performance, we would need to
// implement the max_conflict_run_p parameter.
, parameter early_yumi_p = 1
, parameter verbose_p = 0
)
(input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
, output ready_o
, output v_o
, output [width_p-1:0] data_o
, input yumi_i
);
wire big_full_lo, big_empty_lo;
wire [width_p-1:0] big_data_lo;
logic big_enq, big_deq, big_deq_r;
wire little_ready_lo, little_will_have_space;
logic little_valid, big_valid;
if (early_yumi_p)
assign little_will_have_space = little_ready_lo | yumi_i;
else
assign little_will_have_space = little_ready_lo;
// whether we dequed something on the last cycle
always_ff @(posedge clk_i)
if (reset_i)
big_deq_r <= 1'b0;
else
big_deq_r <= big_deq;
// if the big fifo is not full, then we can take more data
wire ready_o_int = ~big_full_lo;
assign ready_o = ready_o_int;
// ***** DEBUG ******
// for debugging; whether we are bypassing the big fifo
// synopsys translate_off
wire bypass_mode = v_i & ~ big_enq;
// sum up all of the storage in this fifo
wire [31:0] num_elements_debug = big1p.num_elements_debug + big_deq_r + little2p.num_elements_debug;
logic big_enq_r;
always_ff @(posedge clk_i)
if (reset_i)
big_enq_r <= 0;
else
big_enq_r <= big_enq_r | big_enq;
always_ff @(negedge clk_i)
if (verbose_p & (reset_i === 0) & (~big_enq_r & big_enq))
$display("## %L: overflowing into big fifo for the first time (%m)");
// synopsys translate_on
//
// ***** END DEBUG ******
always_comb
begin
// if we fetch an element last cycle, we need to enque
// it into the little fifo
if (big_deq_r)
begin
// we dequed last cycle, so there must be room
// in both big and little fifos
little_valid = 1'b1;
big_enq = v_i;
// if there is data in big fifo
// and we are not enqueing to the big fifo
// and the little fifo is empty
// we can grab another word
// we do not test for the yumi signal here
// because an empty little fifo cannot have a yumi.
big_deq = (~big_empty_lo & ~big_enq & ~v_o);
end
else
begin
// clean through bypass mode; skip
// big fifo and go to little fifo
if (big_empty_lo)
begin
little_valid = v_i & little_will_have_space;
big_enq = v_i & ~little_will_have_space;
big_deq = 1'b0; // big FIFO is empty, can't deque
end
else
// there is data in the big fifo
// but we did not fetch from it
// last cycle.
// we cannot enque anything into
// the little fifo this cycle.
begin
little_valid = 1'b0;
big_enq = v_i & ~big_full_lo;
big_deq = ~big_enq & little_will_have_space;
end
end // else: !if(big_deq_r)
big_valid = big_enq | big_deq;
end
// if we dequed from the big queue last cycle
// then we enque it into the little fifo
wire [width_p-1:0] little_data = big_deq_r ? big_data_lo : data_i;
bsg_fifo_1rw_large #(.width_p(width_p)
,.els_p(els_p)
,.verbose_p(verbose_p)
) big1p
(.clk_i (clk_i )
,.reset_i (reset_i )
,.data_i (data_i )
,.v_i (big_valid)
,.enq_not_deq_i(big_enq)
,.full_o (big_full_lo )
,.empty_o (big_empty_lo)
,.data_o (big_data_lo )
);
bsg_two_fifo #(.width_p(width_p)
,. verbose_p(verbose_p)
,. allow_enq_deq_on_full_p(early_yumi_p)) little2p
(.clk_i (clk_i)
,.reset_i(reset_i)
,.ready_o(little_ready_lo)
,.data_i (little_data)
,.v_i (little_valid)
,.v_o (v_o)
,.data_o (data_o)
,.yumi_i (yumi_i)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_pseudo_large)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__AND4BB_BEHAVIORAL_PP_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4BB_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; vector<vector<int>> tree; int res = 0; int dfs(int node, int parent) { int left = 2; for (int child : tree[node]) { if (child == parent) { continue; } int x = dfs(child, node); if (x == 1 && left > 0) { ++res; --left; } } return left > 0; } int main() { int n, x, y; cin >> n >> x >> y; vector<int> degs(n, 0); tree.resize(n); for (int i = 0; i < n - 1; ++i) { int a, b; cin >> a >> b; --a; --b; tree[a].push_back(b); tree[b].push_back(a); ++degs[a]; ++degs[b]; } if (x < y) { dfs(0, -1); cout << res * (long long)x + (n - res - 1) * (long long)y << n ; } else { if (*max_element(degs.begin(), degs.end()) == n - 1) { cout << (long long)(n - 2) * y + x << n ; } else { cout << (long long)(n - 1) * y << n ; } } return 0; }
|
#include <bits/stdc++.h> const long long mod = 1e9 + 7; using namespace std; const long long N = 102; const long long M = 1e4 + 2; long long dp[N][M], c[N][N], cnt[N]; signed main() { long long n, i, j, k, l, ans = 0, type = 0; cin >> n; dp[0][0] = 1; c[0][0] = 1; for (i = 1; i <= n; i++) { cin >> j; if (!cnt[j]) { type++; } cnt[j]++; for (l = i; l >= 1; l--) { for (k = 10000; k >= j; k--) { dp[l][k] += dp[l - 1][k - j]; if (dp[l][k] > mod) { dp[l][k] -= mod; } } } } if (type <= 2) { cout << n; return 0; } for (i = 1; i <= 100; i++) { for (j = 0; j <= i; j++) { c[j][i] = c[j][i - 1]; if (j) { c[j][i] += c[j - 1][i - 1]; } c[j][i] %= mod; } } for (i = 1; i <= 100; i++) { for (j = 1; j <= cnt[i]; j++) { if (c[j][cnt[i]] == dp[j][i * j]) { ans = max(ans, j); } } } cout << ans; }
|
// nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int cnt, dfn[800005], ed[800005], tot, head[800005], tr[800005 * 4], sum[800005 * 4], fuckljx, n, m, vis[800005], de[800005]; char c[800005]; vector<char> mp[800005]; struct edge { int to, next; } data[800005 * 2]; struct hh { long long x, a, b, val; } edge[800005 * 2]; bool operator<(hh A, hh B) { return A.x < B.x; } void add_edge(int x, int y) { if (!x || !y) return; de[y]++; data[++tot].next = head[x]; data[tot].to = y; head[x] = tot; } int id(int x, int y) { if (x < 1 || x > n || y < 1 || y > m) return 0; return (x - 1) * m + y; } void dfs(int x, int f) { vis[x] = 1; dfn[x] = ++cnt; for (int i = head[x]; i; i = data[i].next) { int t = data[i].to; if (t == f) continue; dfs(t, x); } ed[x] = cnt; } void add(int x, int l, int r, int s, int t, int val) { if (l > t || r < s) return; if (s <= l && r <= t) { if (val == 1) { sum[x]++; tr[x] = (r - l + 1); } else { sum[x]--; if (!sum[x]) tr[x] = tr[x * 2] + tr[x * 2 + 1]; } return; } int mid = (l + r) / 2; add(x * 2, l, mid, s, t, val); add(x * 2 + 1, mid + 1, r, s, t, val); if (!sum[x]) tr[x] = tr[x * 2] + tr[x * 2 + 1]; else tr[x] = (r - l + 1); } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) { scanf( %s , c + 1); for (int j = 1; j <= m; j++) { if (c[j] == U ) add_edge(id(i - 1, j), id(i + 1, j)); if (c[j] == D ) add_edge(id(i + 1, j), id(i - 1, j)); if (c[j] == L ) add_edge(id(i, j - 1), id(i, j + 1)); if (c[j] == R ) add_edge(id(i, j + 1), id(i, j - 1)); mp[i].push_back(c[j]); } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (((i + j) & 1) && !de[id(i, j)]) dfs(id(i, j), 0); } } cnt = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (!((i + j) & 1) && !de[id(i, j)]) dfs(id(i, j), 0); } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (mp[i][j - 1] == U ) { if ((i + j) & 1) { edge[++fuckljx] = (hh){dfn[id(i, j)], dfn[(id(i + 1, j))], ed[(id(i + 1, j))], 1}; edge[++fuckljx] = (hh){ed[id(i, j)] + 1, dfn[(id(i + 1, j))], ed[(id(i + 1, j))], -1}; } else { edge[++fuckljx] = (hh){dfn[id(i + 1, j)], dfn[(id(i, j))], ed[(id(i, j))], 1}; edge[++fuckljx] = (hh){ed[id(i + 1, j)] + 1, dfn[(id(i, j))], ed[(id(i, j))], -1}; } } if (mp[i][j - 1] == L ) { if ((i + j) & 1) { edge[++fuckljx] = (hh){dfn[id(i, j)], dfn[(id(i, j + 1))], ed[(id(i, j + 1))], 1}; edge[++fuckljx] = (hh){ed[id(i, j)] + 1, dfn[(id(i, j + 1))], ed[(id(i, j + 1))], -1}; } else { edge[++fuckljx] = (hh){dfn[id(i, j + 1)], dfn[(id(i, j))], ed[(id(i, j))], 1}; edge[++fuckljx] = (hh){ed[id(i, j + 1)] + 1, dfn[(id(i, j))], ed[(id(i, j))], -1}; } } } } sort(edge + 1, edge + 1 + fuckljx); long long last = 0, ans = 0; for (int i = 1; i <= fuckljx; i++) { ans += (long long)tr[1] * (edge[i].x - last); last = edge[i].x; add(1, 1, cnt + 3, edge[i].a, edge[i].b, edge[i].val); } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, x1, x2, s = 0, x, y1 = 0, y2 = 0, sm = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> x; for (int i = 0; i < x; i++) cout << 7 << ; cout << endl; } return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_deccdp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// This module has the following functionality :-
// 1. Perform the ECC correction on the 155 bit data readd out from
// the L2 array and convert it into the 128 bit corrected data
// 2. Mux 64 bit out of the 128 bit corrected data for the following
// 2 operations :-
// a. Partial Store.
// b. L2 Data Scrub.
// 3. Mux 39 bit out of the 155 bit uncorrected data for the following
// 3 operations :-
// a. Diagnostic accesses to l2data
// b. TAP reads to DRAM addresses.
// c. BIST accesses to l2data.
// Change ( 4/7/2003)
// Changed the input dword_sel_c8 to dword_sel_c7
// Keep the pin in the same place. Setup of
// dword_sel_c7 should be between 50-70ps.
// Added a 1 bit flop for dword_sel_c7.
module sctag_deccdp(/*AUTOARG*/
// Outputs
retdp_data_c8, deccdp_arbdp_data_c8, retdp_diag_data_c7,
lda_syndrome_c9, check0_c7, check1_c7, check2_c7, check3_c7,
parity0_c7, parity1_c7, parity2_c7, parity3_c7, so,
// Inputs
sel_higher_word_c7, sel_higher_dword_c7, dword_sel_c7,
retdp_data_c7, retdp_ecc_c7, rclk, si, se
);
output [127:0] retdp_data_c8; // data to oqdp
output [63:0] deccdp_arbdp_data_c8; // data to arbdatadp
output [38:0] retdp_diag_data_c7 ; // diagnostic data
output [27:0] lda_syndrome_c9; // to csr block
// from and to decc_ctl
input sel_higher_word_c7;
input sel_higher_dword_c7;
input dword_sel_c7;
output [5:0] check0_c7 ;
output [5:0] check1_c7 ;
output [5:0] check2_c7 ;
output [5:0] check3_c7 ;
output parity0_c7;
output parity1_c7;
output parity2_c7;
output parity3_c7;
input [127:0] retdp_data_c7;
input [27:0] retdp_ecc_c7;
input rclk;
input si, se;
output so;
wire [127:0] corr_data_c7;
wire [38:0] data_word0_c7;
wire [38:0] data_word1_c7;
wire [38:0] data_word2_c7;
wire [38:0] data_word3_c7;
wire [38:0] left_diag_out_c7;
wire [38:0] rgt_diag_out_c7;
wire [127:0] retdp_data_c8; // data to oqdp
wire [27:0] error_synd_c7;
wire [27:0] error_synd_c8;
wire dword_sel_c8;
zzecc_sctag_ecc39 bit117_155
(.dout(corr_data_c7[127:96]),
.cflag(check3_c7[5:0]),
.pflag(parity3_c7),
.parity(retdp_ecc_c7[27:21]),
.din(retdp_data_c7[127:96])
) ;
// msb to the left
dff_s #(32) ff_data_rtn_c8_127_96 // arrange this flop in 4 rows.
(.q (retdp_data_c8[127:96]), // interleave the bits
.din (corr_data_c7[127:96]), // For example, 96,100,104 .. belong to the same row
.clk (rclk),
.se(se), .si (), .so ()
) ;
zzecc_sctag_ecc39 bit78_116
(.dout(corr_data_c7[95:64]),
.cflag(check2_c7[5:0]),
.pflag(parity2_c7),
.parity(retdp_ecc_c7[20:14]),
.din(retdp_data_c7[95:64])
) ;
// msb to the left
dff_s #(32) ff_data_rtn_c8_95_64 // arrange this flop in 4 rows.
(.q (retdp_data_c8[95:64]), // interleave the bits
.din (corr_data_c7[95:64]), // For example, 64,68,8 .. belong to the same row
.clk (rclk),
.se(se), .si (), .so ()
) ;
zzecc_sctag_ecc39 bit39_77
(.dout(corr_data_c7[63:32]),
.cflag(check1_c7[5:0]),
.pflag(parity1_c7),
.parity(retdp_ecc_c7[13:7]),
.din(retdp_data_c7[63:32])
) ;
// msb to the left
dff_s #(32) ff_data_rtn_c8_63_32 // arrange this flop in 4 rows.
(.q (retdp_data_c8[63:32]), // interleave the bits
.din (corr_data_c7[63:32]), // For example, 32,36,40 .. belong to the same row
.clk (rclk),
.se(se), .si (), .so ()
) ;
zzecc_sctag_ecc39 bit0_38
(.dout (corr_data_c7[31:0]),
.cflag (check0_c7[5:0]),
.pflag (parity0_c7),
.parity (retdp_ecc_c7[6:0]),
.din (retdp_data_c7[31:0])
) ;
// msb to the left
dff_s #(32) ff_data_rtn_c8_31_0 // arrange this flop in 4 rows.
(.q (retdp_data_c8[31:0]), // interleave the bits
.din (corr_data_c7[31:0]), // For example, 32,36,40 .. belong to the same row
.clk (rclk),
.se(se), .si (), .so ()
) ;
//////////////////////////
// SYNDROME to csr_ctl.
//////////////////////////
assign error_synd_c7 = {parity3_c7,check3_c7[5:0],
parity2_c7,check2_c7[5:0],
parity1_c7,check1_c7[5:0],
parity0_c7,check0_c7[5:0]} ;
dff_s #(28) ff_error_synd_c8
(.q (error_synd_c8[27:0]),
.din (error_synd_c7[27:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(28) ff_lda_syndrome_c9
(.q (lda_syndrome_c9[27:0]),
.din (error_synd_c8[27:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_dword_sel_c8
(.q (dword_sel_c8),
.din (dword_sel_c7),
.clk (rclk),
.se(se), .si (), .so ()
) ;
mux2ds #(64) ret_mux
(.dout (deccdp_arbdp_data_c8[63:0]),
.in0 (retdp_data_c8[127:64]), .sel0 (~dword_sel_c8),
.in1 (retdp_data_c8[63:0]), .sel1 (dword_sel_c8)
) ;
assign data_word1_c7 = {retdp_data_c7[95:64], retdp_ecc_c7[20:14]} ;
assign data_word0_c7 = {retdp_data_c7[127:96],retdp_ecc_c7[27:21]} ;
mux2ds #(39) mux_left_diag_out
(.dout (left_diag_out_c7[38:0]),
.in0 (data_word0_c7[38:0]), .sel0 (~sel_higher_word_c7),
.in1 (data_word1_c7[38:0]), .sel1 (sel_higher_word_c7)
) ;
assign data_word3_c7 = {retdp_data_c7[31:0], retdp_ecc_c7[6:0]} ;
assign data_word2_c7 = {retdp_data_c7[63:32], retdp_ecc_c7[13:7]} ;
mux2ds #(39) mux_rgt_diag_out
(.dout (rgt_diag_out_c7[38:0]),
.in0 (data_word2_c7[38:0]), .sel0 (~sel_higher_word_c7),
.in1 (data_word3_c7[38:0]), .sel1 (sel_higher_word_c7)
) ;
mux2ds #(39) mux_diag_out
(.dout (retdp_diag_data_c7[38:0]),
.in0 (left_diag_out_c7[38:0]), .sel0 (~sel_higher_dword_c7),
.in1 (rgt_diag_out_c7[38:0]), .sel1 (sel_higher_dword_c7)
) ;
endmodule
|
// file: clk_wiz.v
//
// -----------------------------------------------------------------------------
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1 250.000 0.000 50.0 91.364 85.928
// CLK_OUT2 1000.000 0.000 50.0 70.716 85.928
//
//----------------------------------------------------------------------------
// Input Clock Input Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// primary 200.000 0.010
`timescale 1ps/1ps
module clk_wiz_v2_1
(// Clock in ports
input CLK_IN1_P,
input CLK_IN1_N,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFGDS clkin1_buf
(.O (clkin1),
.I (CLK_IN1_P),
.IB (CLK_IN1_N));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCM_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (5.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (8.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (10),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (5),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (5.000),
.CLKIN2_PERIOD (5.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
BUFG clkout3_buf
(.O (CLK_OUT3),
.I (clkout2));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3_2_V
`define SKY130_FD_SC_HD__NOR3_2_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3_2 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3_2_V
|
#include <bits/stdc++.h> int main() { unsigned long long int n, sum = 0, sum1 = 0, i, MAX = 0, temp; scanf( %llu , &n); int a[n]; for (i = 0; i < n; ++i) { scanf( %llu , &a[i]); } for (i = 0; i < n; ++i) { sum = sum + a[i]; } for (i = 0; i < n; ++i) { if (a[i] > MAX) { MAX = a[i]; } } for (i = 0; i < n; ++i) { if (a[i] == MAX) { break; } } temp = a[n - 1]; a[n - 1] = MAX; a[i] = temp; if (sum % 2 != 0) { printf( NO ); } else { for (i = 0; i < n - 1; ++i) { sum1 = sum1 + a[i]; } if (sum1 >= a[n - 1]) { printf( YES ); } else { printf( NO ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int nr, N, K, ap[100009], last_N; pair<int, int> ans[10]; struct line { int a, b, c, init; }; vector<line> v; struct point { long long a, b, c, d; bool operator==(const point &other) const { return (1LL * a * other.b == 1LL * b * other.a && 1LL * c * other.d == 1LL * d * other.c); } bool operator<(const point &other) const { if (1LL * a * other.b == 1LL * b * other.a) return (1LL * c * other.d < 1LL * d * other.c); return (1LL * a * other.b < 1LL * b * other.a); } }; bool OnLine(point p, line l) { return ((long long)1LL * l.a * p.a * p.d + 1LL * l.b * p.b * p.c + 1LL * l.c * p.b * p.d == 0LL); } bool Exist_Intersection(line p, line q) { return (1LL * p.a * q.b != 1LL * p.b * q.a); } point Intersect(line p, line q) { point ans; ans.c = (long long)1LL * q.c * p.a - 1LL * q.a * p.c; ans.d = (long long)1LL * p.b * q.a - 1LL * q.b * p.a; ans.a = (long long)1LL * q.c * p.b - 1LL * q.b * p.c; ans.b = (long long)1LL * p.a * q.b - 1LL * q.a * p.b; return ans; } void Push(int i, int j) { ans[++nr] = make_pair(i, j); } void Pop() { nr--; } bool back(int pos, int K, vector<line> v) { if (pos == v.size()) return 1; if (K < 0) return 0; if (ap[pos]) return back(pos + 1, K, v); point I; for (int i = pos + 1; i < N; i++) { if (ap[i]) continue; if (Exist_Intersection(v[i], v[pos]) == 0) continue; I = Intersect(v[i], v[pos]); for (int j = pos; j < N; j++) if (OnLine(I, v[j])) ap[j]++; Push(v[pos].init, v[i].init); if (back(pos + 1, K - 1, v) == 1) return 1; Pop(); for (int j = pos; j < N; j++) if (OnLine(I, v[j])) ap[j]--; } Push(v[pos].init, -1), ap[pos]++; if (back(pos + 1, K - 1, v) == 1) return 1; Pop(), ap[pos]--; return 0; } bool solve(int K, vector<line> v) { int N = v.size(); if (K >= N) { for (int i = 0; i < N; i++) Push(v[i].init, -1); return 1; } if (K < 0) return 0; if (N <= K * K) { if (back(0, K, v)) return 1; return 0; } int M = K * K + 1, needed = K + 1; set<point> inters; for (int i = 0; i < M; i++) for (int j = i + 1; j < M; j++) { if (Exist_Intersection(v[i], v[j]) == 0) continue; point curr = Intersect(v[i], v[j]); if (inters.count(curr)) continue; inters.insert(curr); int nr = 0; for (int p = i; p < M; p++) if (OnLine(curr, v[p])) nr++; if (nr >= needed) { vector<line> apel; for (int p = 0; p < N; p++) if (!OnLine(curr, v[p])) apel.push_back(v[p]); Push(v[i].init, v[j].init); if (solve(K - 1, apel)) return 1; Pop(); return 0; } } return 0; } int main() { scanf( %d %d , &N, &K); for (int i = 1; i <= N; i++) { line curr; scanf( %d %d %d , &curr.a, &curr.b, &curr.c), curr.init = i; v.push_back(curr); } if (solve(K, v)) { printf( YES n ); printf( %d n , nr); for (int i = 1; i <= nr; i++) printf( %d %d n , ans[i].first, ans[i].second); return 0; } printf( NO n ); return 0; }
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////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mpram_xor.v: Multiported-RAM based on XOR implementation //
// //
// Author: Ameer M. Abdelhadi (, ) //
// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module mpram_xor
#( parameter MEMD = 16, // memory depth
parameter DATAW = 32, // data width
parameter nRPORTS = 2 , // number of reading ports
parameter nWPORTS = 2 , // number of writing ports
parameter WAW = 1 , // allow Write-After-Write (need to bypass feedback ram)
parameter RAW = 1 , // new data for Read-after-Write (need to bypass output ram)
parameter RDW = 0 , // new data for Read-During-Write
parameter IFILE = "" // initialization file, optional
)( input clk , // clock
input [nWPORTS-1:0 ] WEnb , // write enable for each writing port
input [`log2(MEMD)*nWPORTS-1:0] WAddr, // write addresses - packed from nWPORTS write ports
input [DATAW *nWPORTS-1:0] WData, // write data - packed from nWPORTS read ports
input [`log2(MEMD)*nRPORTS-1:0] RAddr, // read addresses - packed from nRPORTS read ports
output reg [DATAW *nRPORTS-1:0] RData); // read data - packed from nRPORTS read ports
localparam ADDRW = `log2(MEMD); // address width
// Register write addresses, data and enables
reg [ADDRW*nWPORTS-1:0] WAddr_r; // registered write addresses - packed from nWPORTS write ports
reg [DATAW*nWPORTS-1:0] WData_r; // registered write data - packed from nWPORTS read ports
reg [ nWPORTS-1:0] WEnb_r ; // registered write enable for each writing port
always @(posedge clk) begin
WAddr_r <= WAddr;
WData_r <= WData;
WEnb_r <= WEnb ;
end
// unpacked/pack addresses/data
reg [ADDRW -1:0] WAddr2D [nWPORTS-1:0] ; // write addresses / 2D
reg [ADDRW -1:0] WAddr2D_r [nWPORTS-1:0] ; // registered write addresses / 2D
reg [DATAW -1:0] WData2D [nWPORTS-1:0] ; // write data / 2D
reg [DATAW -1:0] WData2D_r [nWPORTS-1:0] ; // registered write data / 2D
wire [DATAW* nRPORTS -1:0] RDataOut2D [nWPORTS-1:0] ; // read data out / 2D
reg [DATAW -1:0] RDataOut3D [nWPORTS-1:0][nRPORTS-1:0]; // read data out / 3D
reg [ADDRW*(nWPORTS-1)-1:0] RAddrFB2D [nWPORTS-1:0] ; // read address fb / 2D
reg [ADDRW -1:0] RAddrFB3D [nWPORTS-1:0][nWPORTS-2:0]; // read address fb / 3D
wire [DATAW*(nWPORTS-1)-1:0] RDataFB2D [nWPORTS-1:0] ; // read data fb / 2D
reg [DATAW -1:0] RDataFB3D [nWPORTS-1:0][nWPORTS-2:0]; // read data fb / 3D
reg [DATAW -1:0] WDataFB2D [nWPORTS-1:0] ; // write data / 2D
reg [DATAW -1:0] RData2D [nRPORTS-1:0] ; // read data / 2D
`ARRINIT;
always @* begin
`ARR1D2D(nWPORTS, ADDRW,WAddr ,WAddr2D );
`ARR1D2D(nWPORTS, ADDRW,WAddr_r ,WAddr2D_r );
`ARR1D2D(nWPORTS, DATAW,WData ,WData2D );
`ARR1D2D(nWPORTS, DATAW,WData_r ,WData2D_r );
`ARR2D1D(nRPORTS, DATAW,RData2D ,RData );
`ARR2D3D(nWPORTS,nRPORTS ,DATAW,RDataOut2D,RDataOut3D);
`ARR3D2D(nWPORTS,nWPORTS-1,ADDRW,RAddrFB3D ,RAddrFB2D );
`ARR2D3D(nWPORTS,nWPORTS-1,DATAW,RDataFB2D ,RDataFB3D );
end
// generate and instantiate mulriread RAM blocks
genvar wpi;
generate
for (wpi=0 ; wpi<nWPORTS ; wpi=wpi+1) begin: RPORTwpi
// feedback multiread ram instantiation
mrram #( .MEMD (MEMD ), // memory depth
.DATAW (DATAW ), // data width
.nRPORTS(nWPORTS-1 ), // number of reading ports
.BYPASS (WAW || RDW || RAW ), // bypass? 0:none; 1:single-stage; 2:two-stages
.IZERO ((wpi>0)&&(IFILE!="")), // binary / Initial RAM with zeros (has priority over IFILE)
.IFILE (IFILE )) // initialization file, optional
mrram_fdb ( .clk (clk ), // clock - in
.WEnb (WEnb_r[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D_r[wpi] ), // write address (1 port) - in : [`log2(MEMD) -1:0]
.WData (WDataFB2D[wpi] ), // write data (1 port) - in : [DATAW -1:0]
.RAddr (RAddrFB2D[wpi] ), // read addresses - packed from nRPORTS read ports - in : [`log2(MEMD)*nRPORTS-1:0]
.RData (RDataFB2D[wpi] )); // read data - packed from nRPORTS read ports - out: [DATAW *nRPORTS-1:0]
// output multiread ram instantiation
mrram #( .MEMD (MEMD ), // memory depth
.DATAW (DATAW ), // data width
.nRPORTS(nRPORTS ), // number of reading ports
.BYPASS (RDW ? 2 : RAW ), // bypass? 0:none; 1:single-stage; 2:two-stages
.IZERO ((wpi>0)&&(IFILE!="")), // binary / Initial RAM with zeros (has priority over IFILE)
.IFILE (IFILE )) // initialization file, optional
mrram_out ( .clk (clk ), // clock - in
.WEnb (WEnb_r[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D_r[wpi] ), // write address (1 port) - in : [`log2(MEMD) -1:0]
.WData (WDataFB2D[wpi] ), // write data (1 port) - in : [DATAW -1:0]
.RAddr (RAddr ), // read addresses - packed from nRPORTS read ports - in : [`log2(MEMD)*nRPORTS-1:0]
.RData (RDataOut2D[wpi] )); // read data - packed from nRPORTS read ports - out: [DATAW *nRPORTS-1:0]
end
endgenerate
// combinatorial logic for output and feedback functions
integer i,j,k;
always @* begin
// generate output read functions
for(i=0;i<nRPORTS;i=i+1) begin
RData2D[i] = RDataOut3D[0][i];
for(j=1;j<nWPORTS;j=j+1) RData2D[i] = RData2D[i] ^ RDataOut3D[j][i];
end
// generate feedback functions
for(i=0;i<nWPORTS;i=i+1) WDataFB2D[i] = WData2D_r[i];
for(i=0;i<nWPORTS;i=i+1) begin
k = 0;
for(j=0;j<nWPORTS-1;j=j+1) begin
k=k+(j==i);
RAddrFB3D[i][j] = WAddr2D[k];
WDataFB2D[k] = WDataFB2D[k] ^ RDataFB3D[i][j];
k=k+1;
end
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; const int mod = 20010905; const int inf = 0x3f3f3f3f; const long long linf = 0x3f3f3f3f3f3f3f3f; long long lowbit(long long x) { return x & (-x); } long long qpow(long long a, long long b, long long c) { long long res = 1; a %= mod; while (b) { if (b & 1) res = (res * a) % c; a = (a * a) % c; b >>= 1; } return res % c; } long long qmul(long long a, long long b, long long c) { long long res = 0; while (b) { if (b & 1) res = (res + a) % c; a = (a + a) % c; b >>= 1; } return res % c; } struct Bit { long long Bit[maxn], N; void addBit(long long x, long long v) { x = N - x + 1; while (x <= N) Bit[x] = max(Bit[x], v), x += lowbit(x); } long long qBit(long long x) { x = N - x + 1; long long res = -linf; while (x) res = max(res, Bit[x]), x -= lowbit(x); return res; } }; char s[maxn]; vector<int> e[maxn]; int pre[maxn], sz[maxn]; int fin(int x) { return pre[x] == x ? x : pre[x] = fin(pre[x]); } int n, k; void add(int x, int y) { x = fin(x), y = fin(y); if (x == y) return; pre[x] = y; sz[y] += sz[x]; } int calc(int x) { int y = fin(x + k); x = fin(x); return min(sz[x], sz[y]); } int main() { scanf( %d%d , &n, &k); scanf( %s , s + 1); for (int i = 1; i <= k; i++) { int kk, x; scanf( %d , &kk); while (kk--) { scanf( %d , &x); e[x].push_back(i); } } sz[0] = inf; for (int i = 1; i <= 2 * k; i++) pre[i] = i, sz[i] = (i <= k); long long ans = 0; for (int i = 1; i <= n; i++) { if (e[i].size()) { if (s[i] == 1 ) { if (e[i].size() == 1) { ans -= calc(e[i][0]); add(e[i][0], 0); ans += calc(e[i][0]); } else { int x = e[i][0], y = e[i][1]; if (fin(x) != fin(y)) { ans -= calc(x) + calc(y); add(x, y), add(x + k, y + k); ans += calc(x); } } } else { if (e[i].size() == 1) { ans -= calc(e[i][0]); add(e[i][0] + k, 0); ans += calc(e[i][0]); } else { int x = e[i][0], y = e[i][1]; if (fin(x) != fin(y + k)) { ans -= calc(x) + calc(y); add(x, y + k), add(x + k, y); ans += calc(x); } } } } cout << ans << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long inf = 1000000000ll; const long long inf64 = inf * inf; const long long base = inf + 7; const double pi = acos(-1.0); long long Abs(long long x) { return (x >= 0 ? x : -x); } int n; string s; int par[62 * 62], size[62 * 62], in[62 * 62], out[62 * 62]; vector<int> ans, g[62 * 62]; vector<bool> used; int _get(char c) { if (c >= 0 && c <= 9 ) return (c - 0 ); else if (c >= a && c <= z ) return (c - a + 10); else return (c - A + 36); } int get(string a) { int x, y; x = _get(a[0]); y = _get(a[1]); return x * 62 + y; } int find(int x) { return (par[x] == x ? x : par[x] = find(par[x])); } void un(int a, int b) { int pa = find(a); int pb = find(b); if (size[pa] == size[pb]) par[pa] = pb, size[pb]++; else { if (size[pa] > size[pb]) swap(pa, pb); par[pa] = pb; } } char chr(int x) { if (x < 10) return char(x + 0 ); else if (x < 36) return char(x + a - 10); else return char(x + A - 36); } void dfs(int v) { while (!g[v].empty()) { int x = g[v].back(); g[v].pop_back(); dfs(x); } ans.push_back(v); } bool solve() { for (int i(0); i < 62 * 62; i++) size[i] = 1, par[i] = i; cin >> n; used.assign(62 * 62, 0); int Q = -1; for (int i(0); i < n; i++) { int x, y; cin >> s; x = get(s.substr(0, 2)); if (Q == -1) Q = x; y = get(s.substr(1, 2)); used[x] = used[y] = 1; g[x].push_back(y); in[y]++; out[x]++; un(x, y); } bool f = 0; for (int i(0); i < 62 * 62; i++) { if (!used[i]) continue; if (par[i] != i) continue; if (f) { puts( NO ); return true; ; } else f = 1; } int x1, x2; x1 = x2 = -1; for (int i(0); i < 62 * 62; i++) { if (in[i] == out[i]) continue; if (in[i] - out[i] == 1) { if (x1 != -1) { puts( NO ); return true; ; } x1 = i; } else if (in[i] - out[i] == -1) { if (x2 != -1) { puts( NO ); return true; ; } x2 = i; } else { puts( NO ); return true; ; } } if (x1 == -1 && x2 != -1 || x1 != -1 && x2 == -1) { puts( NO ); return true; ; } used.assign(62 * 62, 0); dfs(x2 != -1 ? x2 : Q); reverse((ans).begin(), (ans).end()); puts( YES ); int x, y; x = ans[0] / 62; cout << chr(x); for (int i(0); i < (int)ans.size(); i++) { x = ans[i] % 62; cout << chr(x); } return true; } int main() { solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int Win = 3, Loop = 2, Lose = 1; int n, dp[7001][3], ne[3], a[7001][3], k[3], sum[7001][3]; bool b[7001][3]; inline int max(int x, int y) { return x > y ? x : y; } void dfs(int x, int y) { if (b[x][y]) return; b[x][y] = 1; int t = ne[y]; for (int i = 1; i <= k[t]; i++) { int xt = x - a[i][t]; if (xt <= 0) xt += n; if (xt == 1) continue; dp[xt][t] = max(dp[xt][t], 4 - dp[x][y]); if (++sum[xt][t] == k[t] || dp[xt][t] == Win) dfs(xt, t); } } int main() { scanf( %d , &n); scanf( %d , &k[1]); for (int i = 1; i <= k[1]; i++) scanf( %d , &a[i][1]); scanf( %d , &k[2]); for (int i = 1; i <= k[2]; i++) scanf( %d , &a[i][2]); dp[1][1] = dp[1][2] = Lose; ne[1] = 2; ne[2] = 1; dfs(1, 1); dfs(1, 2); for (int j = 1; j <= 2; j++) { for (int i = 2; i <= n; i++) { if (!b[i][j]) dp[i][j] = Loop; printf(dp[i][j] == Win ? Win : dp[i][j] == Loop ? Loop : Lose ); } printf( n ); } }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLRTP_PP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTP_PP_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; int main() { int sum = 0; bool ne = 0; for (int i = 0; i < 5; i++) { int x; cin >> x; sum += x; } if (sum % 5 != 0 or sum == 0) { cout << -1 ; } else cout << sum / 5; return 0; }
|
/*
main function:
1)allocate cpuid for pkt by the key
2)round robin mode & port bind mode in this module
modify:
1)add in_fpgaac_cpuid_cs, module can work when this signal is valid 0:bit:round robin 1:port bind
tips: all fifo are showahead mode
*/
`timescale 1 ps / 1 ps
module DISPATHER_CPUID(
input clk,
input reset,
input in_fpgaac_cpuid_cs,
input [5:0] in_fpgaac_channel_num,
input [31:0] cpuid_valid,
input [4:0] in_input_key,
input in_input_ctl,
output reg out_input_ack,
output reg out_input_valid,
output reg [4:0] out_input_cpuid
);
reg current_cpuid_valid;
reg [4:0] cpuid_reg;
reg [2:0] current_state;
parameter idle_s = 3'd0,
match_s = 3'd1,
judge_s = 3'd2,
wait_s = 3'd3;
always@(posedge clk or negedge reset) begin
if(!reset) begin
out_input_ack<=1'b0;
out_input_valid<=1'b0;
out_input_cpuid<=5'd0;
cpuid_reg<=5'd0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin//wait for the req signal(in_input_ctl) from Input module
out_input_ack<=1'b0;
out_input_valid<=1'b0;
current_cpuid_valid<=1'b0;
if(in_input_ctl==1'b0) begin//Input module have not req for cpuid
current_state <= idle_s;
end
else begin//
if(in_fpgaac_cpuid_cs==1'b0) begin//round robin mode
out_input_cpuid<=cpuid_reg;
end
else begin//port bind mode
out_input_cpuid<=in_input_key;
end
current_state <= match_s;
end
end
match_s: begin
case(out_input_cpuid)
5'd0: current_cpuid_valid <= cpuid_valid[0];
5'd1: current_cpuid_valid <= cpuid_valid[1];
5'd2: current_cpuid_valid <= cpuid_valid[2];
5'd3: current_cpuid_valid <= cpuid_valid[3];
5'd4: current_cpuid_valid <= cpuid_valid[4];
5'd5: current_cpuid_valid <= cpuid_valid[5];
5'd6: current_cpuid_valid <= cpuid_valid[6];
5'd7: current_cpuid_valid <= cpuid_valid[7];
5'd8: current_cpuid_valid <= cpuid_valid[8];
5'd9: current_cpuid_valid <= cpuid_valid[9];
5'd10: current_cpuid_valid <= cpuid_valid[10];
5'd11: current_cpuid_valid <= cpuid_valid[11];
5'd12: current_cpuid_valid <= cpuid_valid[12];
5'd13: current_cpuid_valid <= cpuid_valid[13];
5'd14: current_cpuid_valid <= cpuid_valid[14];
5'd15: current_cpuid_valid <= cpuid_valid[15];
5'd16: current_cpuid_valid <= cpuid_valid[16];
5'd17: current_cpuid_valid <= cpuid_valid[17];
5'd18: current_cpuid_valid <= cpuid_valid[18];
5'd19: current_cpuid_valid <= cpuid_valid[19];
5'd20: current_cpuid_valid <= cpuid_valid[20];
5'd21: current_cpuid_valid <= cpuid_valid[21];
5'd22: current_cpuid_valid <= cpuid_valid[22];
5'd23: current_cpuid_valid <= cpuid_valid[23];
5'd24: current_cpuid_valid <= cpuid_valid[24];
5'd25: current_cpuid_valid <= cpuid_valid[25];
5'd26: current_cpuid_valid <= cpuid_valid[26];
5'd27: current_cpuid_valid <= cpuid_valid[27];
5'd28: current_cpuid_valid <= cpuid_valid[28];
5'd29: current_cpuid_valid <= cpuid_valid[29];
5'd30: current_cpuid_valid <= cpuid_valid[30];
5'd31: current_cpuid_valid <= cpuid_valid[31];
endcase
current_state <= judge_s;
end
judge_s: begin
if(in_fpgaac_cpuid_cs==1'b0) begin//round robin mode
if(cpuid_reg<in_fpgaac_channel_num-6'd1) begin//cpuid start from 0,and the num guide by software start from 1
cpuid_reg<=cpuid_reg+5'd1;//round robin mode
end
else begin//cpuid can't > the num guide by software
cpuid_reg<=5'd0;
end
if(current_cpuid_valid==1'b0) begin
out_input_ack<=1'b0;
out_input_valid<=1'b0;
current_state <= idle_s;
end
else begin
out_input_ack<=1'b1;//cpuid is valid,Input module can get it
out_input_valid<=1'b1;
current_state <= wait_s;
end
end
else begin//port bind mode
out_input_ack<=1'b1;//cpuid is valid,Input module can get it
if(current_cpuid_valid==1'b0) begin
out_input_valid<=1'b0;
end
else begin
out_input_valid<=1'b1;
end
current_state <= wait_s;
end
end
wait_s: begin//wait for req signal invalid after allocated cpuid
if(in_input_ctl==1'b1) begin
out_input_ack<=1'b1;
current_state <= wait_s;
end
else begin
out_input_ack<=1'b0;//cpuid is invalid
current_state <= idle_s;
end
end
default: begin
out_input_ack<=1'b0;
out_input_cpuid<=5'b0;
cpuid_reg<=5'b0;
current_state <= idle_s;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; int cnt[maxn][26]; int dif[26]; int getAns() { int cc = 0; for (int i = 0; i < 26; ++i) if (dif[i]) { ++cc; } return cc; } int main() { string s; cin >> s; int len = s.length(); for (int i = 1; i <= len; ++i) { for (int k = 0; k < 26; ++k) cnt[i][k] = cnt[i - 1][k]; ++cnt[i][s[i - 1] - a ]; } int q; cin >> q; while (q--) { int l, r; cin >> l >> r; --l; for (int i = 0; i < 26; ++i) dif[i] = cnt[r][i] - cnt[l][i]; int tot = getAns(); if (tot == 1) { if (r - l == 1) cout << YES << endl; else cout << NO << endl; } else if (tot == 2) { if (s[l] != s[r - 1]) cout << YES << endl; else cout << NO << endl; } else { cout << YES << endl; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int a, b, c, d, i, j, n, flag = 0; cin >> a >> b >> c >> d; n = max(max(a, b), max(c, d)); flag = 1; for (i = 0; i <= n; i++) { for (j = 0; j <= n; j++) { if (b + i * a == d + j * c) { cout << b + i * a << endl; flag = 0; break; } } if (!flag) break; } if (flag) cout << -1 << endl; return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_axi_basic_rx.v
// Version : 3.0
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [KEEP_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
pcie_7x_0_core_top_axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
pcie_7x_0_core_top_axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
// A Data Channel
`include "globalVariable.v"
module dataChannel (clk, reset, inPort, counterGolden, injectGrant,winningFlitPortTag, winningFlitValid, inRouterFlitLocal,inner_wire_in1, inner_wire_in2,swap1, swap2, inner_wire_out1, inner_wire_out2,outPort);
input clk, reset;
input [`CHANNEL_SIZE-1:0] inPort;
input [`COORDINATE_SIZE+`PKTID_SIZE-1:0] counterGolden;
input [`PORT_TAG_SIZE-1:0] winningFlitPortTag;
input winningFlitValid, injectGrant, swap1, swap2;
input [`IN_ROUTER_SIZE-1:0] inRouterFlitLocal;
input [`IN_ROUTER_SIZE-1:0] inner_wire_in1, inner_wire_in2;
output [`IN_ROUTER_SIZE-1:0] inner_wire_out1, inner_wire_out2;
output reg [`CHANNEL_SIZE-1:0] outPort;
reg [`CHANNEL_SIZE-1:0] inputLatch;
always @ (posedge clk or negedge reset) begin
if (~reset) begin
inputLatch<= 0;
end
else begin
inputLatch <= inPort;
end
end
wire [`COORDINATE_SIZE-1:0] CURRENT_POSITION = {`CURRENT_POSITION_X,`CURRENT_POSITION_Y};
wire [`IN_ROUTER_SIZE-1:0] inRouterFlit;
routerComputation RC (
.flit (inputLatch),
.CURRENT_POSITION (CURRENT_POSITION),
.counterGolden (counterGolden),
.PORT_INDEX (3'd0), // use East port as an example
.inRouterFlit (inRouterFlit)
);
wire valid;
ejectKill ejectKill(
.portIndex (inRouterFlit[`PORT_TAG]),
.winnerPort (winningFlitPortTag),
.validIn (inRouterFlit[`VALID]),
.winnerValid (winningFlitValid),
.validOut (valid) // check if there is any racing
);
wire [`IN_ROUTER_SIZE-1:0] inj2PipelineLatch;
reg [`IN_ROUTER_SIZE-1:0] pipelineLatch;
mux2to1InRouter Inject (
.aIn ({valid,inRouterFlit[`IN_ROUTER_SIZE-2:0]}),
.bIn (inRouterFlitLocal),
.sel (injectGrant),
.dataOut (inj2PipelineLatch)
);
always @ (posedge clk or negedge reset) begin
if (~reset) begin
pipelineLatch <= 0;
end
else begin
pipelineLatch <= inj2PipelineLatch;
end
end
wire [`IN_ROUTER_SIZE-1:0] straightFlit [1:0];
wire [`IN_ROUTER_SIZE-1:0] interStageFlit;
wire [`IN_ROUTER_SIZE-1:0] w_outPort;
demux1to2InRouter demux0(
.dataIn (pipelineLatch),
.sel (swap1),
.aOut (straightFlit[0]),
.bOut (inner_wire_out1)
);
mux2to1InRouter mux0(
.aIn (straightFlit[0]),
.bIn (inner_wire_in1),
.sel (swap1),
.dataOut (interStageFlit)
);
demux1to2InRouter demux1(
.dataIn (interStageFlit),
.sel (swap2),
.aOut (straightFlit[1]),
.bOut (inner_wire_out2)
);
mux2to1InRouter mux1(
.aIn (straightFlit[1]),
.bIn (inner_wire_in2),
.sel (swap2),
.dataOut (w_outPort)
);
always @ (posedge clk or negedge reset) begin
if (~reset) begin
outPort <= 0;
end
else begin
outPort <= w_outPort[`CHANNEL_SIZE-1:0];
end
end
endmodule
|
#include <bits/stdc++.h> int main() { long n, a, b; scanf( %ld %ld %ld , &n, &a, &b); std::vector<long> v(n, 1); long current(1), sum(1); for (long p = 1; p < n; p++) { if (b > 0) { current = sum + 1; --b; } else if ((p > 1) && (a > 0)) { ++current, --a; } v[p] = current; sum += current; } if ((a > 0) || (b > 0)) { puts( -1 ); } else { for (long p = 0; p < n; p++) { printf( %ld , v[p]); }; puts( ); } return 0; }
|
#include <bits/stdc++.h> int main() { char a[100010]; scanf( %s , a); long long i = 0, x = 1; while (a[i] != 0 ) { if (a[i] == 0 ) { a[i] = 2 ; x = 0; break; } i++; } if (x) { a[0] = 2 ; } i = 0; while (a[i] != 0 ) { if (a[i] != 2 ) printf( %c , a[i]); i++; } printf( n ); return (0); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLCLKP_PP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLCLKP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long n, ans = 1; long long C(long long m, long long n) { long long p = 1; for (long long i = 1; i <= n; i++) p *= i; for (long long i = 1; i <= m; i++) p /= i; for (long long i = 1; i <= n - m; i++) p /= i; return p; } signed main() { cin >> n; for (long long i = 1; i <= n / 2 - 1; i++) ans *= i; ans *= ans; ans *= C(n / 2, n); ans /= 2; cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const long long INFLL = 1e18 + 1; const int MAX = 200001; const long long MOD = 1000000007; const int SZ = 300100; const double PI = 3.14159265358979323846264338327; long long inq(long long k, long long q, long long mod) { if (q == 0) return 1; long long l = inq(k, q / 2, mod); if (q % 2 == 0) return l * l % mod; else return l * l % mod * k % mod; } long long gcd(long long a, long long b) { if (a < b) swap(a, b); if (b == 0) return a; return gcd(b, a % b); } long long cubr(long long a) { long long l = -1, r = 1e6 + 2; while (l < r - 1) { long long mid = (l + r) / 2; if (mid * mid * mid > a) r = mid; else l = mid; } return l; } long long max(long long a, long long b) { if (a > b) return a; return b; } long long min(long long a, long long b) { return -1 * max(-a, -b); } long long possible(long long q) { if (q == INF) return -1; return q; } bool correct(int x, int xx) { if (x < 0) return 0; if (x >= xx) return 0; return 1; } long long dsumm(long long x, long long k) { long long y = 1; long long z = 0; for (int i = 0; y < 1e18; i++) { z += x / y % k; y *= k; } return z; } long long dcount(long long x) { long long y = 1; long long z = 0; int c[100]; for (int i = 0; i < 10; i++) c[i] = 0; for (int i = 0; x > 0; i++) { if (c[x / y % 10] == 0) z++; c[x / y % 10] = 1; x /= 10; } return z; } long long lg10(long long x) { if (10000 <= x && x < 100000) return 5; if (x == 0) return 0; return lg10(x / 10) + 1; } long long g(long long x, long long mod) { if (x == 0) return 0; return x / mod + g(x / mod, mod); } bool is_digit(char c) { return ( 0 <= c && c <= 9 ); } string s; string t; long long prefAS[500000]; long long prefAT[500000]; long long suffA1[500000]; long long suffA2[500000]; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> s; cin >> t; for (long long(i) = 0; (i) != (s.size()); i++) { if (s[i] == C ) s[i] = B ; if (i > 0) prefAS[i] = prefAS[i - 1]; prefAS[i] += (s[i] == A ); } for (long long(i) = 0; (i) != (t.size()); i++) { if (t[i] == C ) t[i] = B ; if (i > 0) prefAT[i] = prefAT[i - 1]; prefAT[i] += (t[i] == A ); } long long aa = 0; for (long long(i) = 0; (i) != (s.size()); i++) { if (s[i] == A ) aa++; else aa = 0; suffA1[i] = aa; } aa = 0; for (long long(i) = 0; (i) != (t.size()); i++) { if (t[i] == A ) aa++; else aa = 0; suffA2[i] = aa; } long long q; cin >> q; while (q--) { long long l1, r1, l2, r2; cin >> l1 >> r1 >> l2 >> r2; l1--; r1--; l2--; r2--; long long cntA1 = prefAS[r1] - (l1 > 0 ? prefAS[l1 - 1] : 0); long long cntA2 = prefAT[r2] - (l2 > 0 ? prefAT[l2 - 1] : 0); long long cntB1 = r1 - l1 + 1 - cntA1; long long cntB2 = r2 - l2 + 1 - cntA2; long long suffA1q = min(suffA1[r1], r1 - l1 + 1); long long suffA2q = min(suffA2[r2], r2 - l2 + 1); if (suffA1q % 3 != suffA2q % 3 || (suffA1q == r1 - l1 + 1 && suffA2q != r2 - l2 + 1)) { suffA1q--; cntB1 += 2; } if (cntB1 % 2 != cntB2 % 2 || cntB1 > cntB2 || suffA1q < suffA2q) { cout << 0; } else { cout << 1; } } }
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int a, long long int n, long long int m); long long int power(long long int a, long long int n, long long int m) { if (n == 0) return 1; long long int x = power(a, n / 2, m); if (n % 2 != 0) return (((a * x) % m) * (x) % m) % m; else return (x * x) % m; } double PI = 3.14159265357; int32_t main() { long long int n, i, j, x, y, m, k, t, sum, count, cnt, b, c, d, j1, z, a, temp; ios::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); cin >> t; while (t--) { cin >> n; long long int arr[n]; long long int e = 0, o = 0; for (i = 0; i < n; i++) { cin >> arr[i]; if (arr[i] % 2 == 0) e++; else o++; } if (e - o != (n) % 2) { cout << -1 n ; continue; } cnt = 0; for (i = 0; i < n; i++) if (arr[i] % 2 != i % 2) cnt++; cout << cnt / 2 << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD1_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD1_PP_BLACKBOX_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv5sd1 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD1_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int NO_OF_ALPHABETS = 26; vector<int> degree(NO_OF_ALPHABETS, 0); vector<int> graph[NO_OF_ALPHABETS]; vector<int> component_no(NO_OF_ALPHABETS, 0); void dfs(int v, int parent_v, int c) { component_no[v] = c; for (int i = 0; i < graph[v].size(); i++) { int child_v = graph[v][i]; if (child_v == parent_v || component_no[child_v] == c) { continue; } dfs(child_v, v, c); } } void solve() { string password; cin >> password; const int NO_OF_ALPHABETS = 26; vector<vector<int> > adjacency(NO_OF_ALPHABETS, vector<int>(NO_OF_ALPHABETS, false)); for (int alpha = 0; alpha < NO_OF_ALPHABETS; alpha++) { degree[alpha] = 0; graph[alpha].clear(); component_no[alpha] = 0; } for (int i = 1; i < password.size(); i++) { if (adjacency[password[i] - a ][password[i - 1] - a ] == false) { adjacency[password[i] - a ][password[i - 1] - a ] = true; adjacency[password[i - 1] - a ][password[i] - a ] = true; graph[password[i] - a ].push_back(password[i - 1] - a ); graph[password[i - 1] - a ].push_back(password[i] - a ); degree[password[i] - a ]++; degree[password[i - 1] - a ]++; } } vector<int> degree_2; for (int alpha = 0; alpha < NO_OF_ALPHABETS; alpha++) { if (degree[alpha] > 2) { cout << NO n ; return; } if (degree[alpha] == 2) { degree_2.push_back(alpha); } } int component = 1; for (int alpha = 0; alpha < NO_OF_ALPHABETS; alpha++) { if (component_no[alpha] == 0) { dfs(alpha, -1, component++); } } string keyboard; vector<int> components; vector<int> used(NO_OF_ALPHABETS, false); for (int c = 1; c < component; c++) { vector<int> this_component; for (int alpha = 0; alpha < NO_OF_ALPHABETS; alpha++) { if (component_no[alpha] == c) { this_component.push_back(alpha); } } if (this_component.size() == 1) { keyboard += (char)( a + this_component[0]); used[this_component[0]] = true; continue; } int border_1 = -1, border_2 = -1; for (int i = 0; i < this_component.size(); i++) { if (degree[this_component[i]] == 1) { if (border_1 == -1) border_1 = this_component[i]; else border_2 = this_component[i]; } } if (border_1 == -1 || border_2 == -1) { cout << NO n ; return; } keyboard += (char)( a + border_1); used[border_1] = true; while (keyboard.back() - a != border_2) { for (int i = 0; i < graph[keyboard.back() - a ].size(); i++) { if (!used[graph[keyboard.back() - a ][i]]) { int next = graph[keyboard.back() - a ][i]; keyboard += (char)( a + next); used[next] = true; break; } } } } cout << YES n ; cout << keyboard << n ; return; } int main() { int no_of_test_cases; cin >> no_of_test_cases; while (no_of_test_cases--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[1000006], s[1000006]; int main() { ios_base::sync_with_stdio(false); long long n, i, j, k; string st; cin >> st; long long ln = st.size(); stack<long long> stk; for (i = 0; i < ln; i++) { if (st[i] == ( ) { stk.push(i); } else { if (stk.empty()) { s[i] = -1; } if (!stk.empty()) { long long idx = stk.top(); stk.pop(); if (idx > 0 && st[idx - 1] == ) && s[idx - 1] >= 0) s[i] = s[idx - 1]; else s[i] = idx; long long xx = i - s[i] + 1; a[xx]++; } } } for (i = 1000005; i >= 0; i--) { if (a[i] > 0) { cout << i << << a[i] << endl; return 0; } } cout << 0 << << 1 << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__XNOR2_PP_BLACKBOX_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR2_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int i, n; string st; vector<string> v; map<string, int> mp; cin >> n; for (i = 0; i < n; i++) { cin >> st; if (mp[st] == 0) { v.push_back(st); } mp[st]++; } if (v.size() == 1) cout << v[0] << n ; else { if (mp[v[0]] > mp[v[1]]) cout << v[0]; else cout << v[1] << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_PP_SYMBOL_V
`define SKY130_FD_SC_LP__AND4_PP_SYMBOL_V
/**
* and4: 4-input AND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> bool Max(T1& a, T2 b) { return a < b ? a = b, 1 : 0; } template <typename T1, typename T2> bool Min(T1& a, T2 b) { return a > b ? a = b, 1 : 0; } const int N = 1000001; bool prime[N]; vector<long long> pri; vector<pair<long long, long long> > nv, sv; long long n, m, s; long long ans; void rec(long long i, long long prod) { if (i == sv.size()) { ans++; return; } auto cur = sv[i]; for (int j = 0; j < (cur.second + 1); ++j) { rec(i + 1, prod); if ((prod *= cur.first) > n) break; } } long long pow(long long a, long long p) { long long ret = 1; while (p) { if (p & 1) ret *= a; a *= a; p >>= 1; } return ret; } void solve() { long long v; n = 1; for (int i = 0; i < (3); ++i) { cin >> v; n *= v; } m = 1; for (int i = 0; i < (3); ++i) { cin >> v; m *= v; } s = 2; for (int i = 0; i < (3); ++i) { cin >> v; s *= v; } long long ts = s, tn = n; nv.clear(); sv.clear(); for (auto& e : pri) { if (e * e > ts) break; long long cnt = 0; while (ts % e == 0) { cnt++; ts /= e; } if (cnt) sv.emplace_back(e, cnt); } if (ts > 1) sv.emplace_back(ts, 1); for (auto& e : pri) { if (e * e > tn) break; long long cnt = 0; while (tn % e == 0) { cnt++; tn /= e; } if (cnt) nv.emplace_back(e, cnt); } if (tn > 1) nv.emplace_back(tn, 1); ans = 0; rec(0, 1); sv.emplace_back(N, 1); vector<long long> tmp; long long i = 0; for (auto& e : nv) { while (sv[i].first < e.first) i++; if (sv[i].first > e.first) { tmp.emplace_back(e.first); } else { if (sv[i].second < e.second) tmp.emplace_back(pow(e.first, sv[i].second + 1)); i++; } } long long sz = tmp.size(); for (int sub = 0; sub < (1 << sz); ++sub) { long long t = 1; bool add = 1; for (int i = 0; i < (sz); ++i) if ((sub >> i) & 1) { t *= tmp[i]; add ^= 1; } if (add) ans += m / t; else ans -= m / t; } cout << ans << n ; } void init() { for (int i = 2; i <= (N - 1); ++i) if (!prime[i]) { pri.emplace_back(i); for (long long j = (long long)i * i; j < N; j += i) prime[j] = 1; } } int main(void) { ios::sync_with_stdio(false); cin.tie(0); cout.setf(ios::fixed); cout.precision(20); init(); int TC = 1; cin >> TC; for (int TI = 1; TI <= (TC); ++TI) { solve(); } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:58:49 03/06/2017
// Design Name: FULL_ADDER
// Module Name: D:/Projects/XilinxISE/HW1/Homework1/testFULL_ADDER.v
// Project Name: Homework1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: FULL_ADDER
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testFULL_ADDER;
// Inputs
reg A;
reg B;
reg Ci;
// Outputs
wire S;
wire Co;
// Instantiate the DESIGN Under Test (DUT)
FULL_ADDER dut (
.A(A),
.B(B),
.Ci(Ci),
.S(S),
.Co(Co)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
Ci = 0;
#30;
A = 0;
B = 0;
Ci = 1;
#30;
A = 0;
B = 1;
Ci = 0;
#30;
A = 0;
B = 1;
Ci = 1;
#30;
A = 1;
B = 0;
Ci = 0;
#30;
A = 1;
B = 0;
Ci = 1;
#30;
A = 1;
B =1;
Ci = 0;
#30;
A = 1;
B = 1;
Ci = 1;
// Add stimulus here
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_data_pipeline
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The TX Data pipeline module takes arbitrarily 32-bit aligned data
// from the WR_TX_DATA interface and shifts the data so that it is 0-bit
// aligned. This data is presented on a set of N fifos, where N =
// (C_DATA_WIDTH/32). Each fifo provides it's own VALID signal and is
// controlled by a READY signal. Each fifo also provides an independent DATA bus
// and additional END_FLAG signal which inidicates that the dword provided in this
// fifo is the last dword in the current payload. The START_FLAG signal indicates
// that the dword at index N = 0 is the start of a new packet.
//
// The TX Data Pipeline is built from two modules: tx_data_shift.v and
// tx_data_fifo.v. See these modules for more information.
//
// Author: Dustin Richmond (@darichmond)
//----------------------------------------------------------------------------
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_data_pipeline
#(parameter C_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_MAX_PAYLOAD_DWORDS = 256,
parameter C_DEPTH_PACKETS = 10,
parameter C_VENDOR = "ALTERA")
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: WR TX DATA
input WR_TX_DATA_VALID,
input [C_DATA_WIDTH-1:0] WR_TX_DATA,
input WR_TX_DATA_START_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_START_OFFSET,
input WR_TX_DATA_END_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_OFFSET,
output WR_TX_DATA_READY,
// Interface: TX DATA FIFOS
input [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_READY,
output [C_DATA_WIDTH-1:0] RD_TX_DATA,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_END_FLAGS,
output RD_TX_DATA_START_FLAG,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_VALID,
output RD_TX_DATA_PACKET_VALID);
`include "functions.vh"
wire wRdTxDataValid;
wire wRdTxDataReady;
wire wRdTxDataStartFlag;
wire [C_DATA_WIDTH-1:0] wRdTxData;
wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataEndFlags;
wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataWordValid;
/*AUTOWIRE*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
tx_data_shift
#(.C_PIPELINE_OUTPUT (0),
/*AUTOINSTPARAM*/
// Parameters
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_VENDOR (C_VENDOR))
tx_shift_inst
(// Outputs
.RD_TX_DATA (wRdTxData),
.RD_TX_DATA_VALID (wRdTxDataValid),
.RD_TX_DATA_START_FLAG (wRdTxDataStartFlag),
.RD_TX_DATA_WORD_VALID (wRdTxDataWordValid),
.RD_TX_DATA_END_FLAGS (wRdTxDataEndFlags),
// Inputs
.RD_TX_DATA_READY (wRdTxDataReady),
/*AUTOINST*/
// Outputs
.WR_TX_DATA_READY (WR_TX_DATA_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_TX_DATA_VALID (WR_TX_DATA_VALID),
.WR_TX_DATA (WR_TX_DATA[C_DATA_WIDTH-1:0]),
.WR_TX_DATA_START_FLAG (WR_TX_DATA_START_FLAG),
.WR_TX_DATA_START_OFFSET (WR_TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_END_FLAG (WR_TX_DATA_END_FLAG),
.WR_TX_DATA_END_OFFSET (WR_TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]));
// TX Data Fifo
tx_data_fifo
#(// Parameters
.C_PIPELINE_INPUT (1),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
txdf_inst
(// Outputs
.WR_TX_DATA_READY (wRdTxDataReady),
.RD_TX_DATA (RD_TX_DATA[C_DATA_WIDTH-1:0]),
.RD_TX_DATA_START_FLAG (RD_TX_DATA_START_FLAG),
.RD_TX_DATA_WORD_VALID (RD_TX_DATA_WORD_VALID[(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_END_FLAGS (RD_TX_DATA_END_FLAGS[(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_PACKET_VALID (RD_TX_DATA_PACKET_VALID),
// Inputs
.WR_TX_DATA (wRdTxData),
.WR_TX_DATA_VALID (wRdTxDataValid),
.WR_TX_DATA_START_FLAG (wRdTxDataStartFlag),
.WR_TX_DATA_WORD_VALID (wRdTxDataWordValid),
.WR_TX_DATA_END_FLAGS (wRdTxDataEndFlags),
.RD_TX_DATA_WORD_READY (RD_TX_DATA_WORD_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/")
// End:
|
#include <bits/stdc++.h> using namespace std; map<pair<string, string>, int> m, m1; vector<pair<string, string> > ans; int main() { string s1, s2; int n, t, i, d, j; scanf( %d%d , &n, &d); for (i = 1; i <= n; i++) { cin >> s1 >> s2 >> t; for (j = 0; j < ans.size(); j++) if ((ans[j].first == s1 && ans[j].second == s2) || (ans[j].first == s2 && ans[j].second == s1)) break; if (j != int(ans.size())) continue; t++; if ((m[make_pair(s2, s1)] != 0 && t - m[make_pair(s2, s1)] <= d && t - m[make_pair(s2, s1)] > 0) || (m1[make_pair(s2, s1)] != 0 && t - m1[make_pair(s2, s1)] <= d && t - m1[make_pair(s2, s1)] > 0)) ans.push_back(make_pair(s1, s2)); if (m[make_pair(s1, s2)] != t) m1[make_pair(s1, s2)] = m[make_pair(s1, s2)]; m[make_pair(s1, s2)] = t; } printf( %d , int(ans.size())); for (i = 0; i < ans.size(); i++) cout << endl << ans[i].first << << ans[i].second; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:26:11 07/23/2010
// Design Name:
// Module Name: dac_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module dac(
input clkin,
input sysclk,
input we,
input[10:0] pgm_address,
input[7:0] pgm_data,
input[7:0] volume,
input vol_latch,
input [2:0] vol_select,
input [8:0] dac_address_ext,
input play,
input reset,
input palmode,
output sdout,
output mclk_out,
output lrck_out,
output sclk_out,
output DAC_STATUS
);
`define DAC
`ifndef DAC
assign sdout = 0;
assign mclk_out = 0;
assign lrck_out = 0;
assign DAC_STATUS = 0;
`else
reg[8:0] dac_address_r;
reg[8:0] dac_address_r_sync;
wire[8:0] dac_address = dac_address_r_sync;
wire[31:0] dac_data;
assign DAC_STATUS = dac_address_r[8];
reg[10:0] vol_reg;
reg[10:0] vol_target_reg;
reg[1:0] vol_latch_reg;
reg vol_valid;
reg[2:0] sysclk_sreg;
wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01);
always @(posedge clkin) begin
sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
end
`ifdef MK2
`ifndef DEBUG
dac_buf snes_dac_buf (
.clka(clkin),
.wea(~we), // Bus [0 : 0]
.addra(pgm_address), // Bus [10 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
`endif
`endif
`ifdef MK3
dac_buf snes_dac_buf (
.clock(clkin),
.wren(~we), // Bus [0 : 0]
.wraddress(pgm_address), // Bus [10 : 0]
.data(pgm_data), // Bus [7 : 0]
.rdaddress(dac_address), // Bus [8 : 0]
.q(dac_data)); // Bus [31 : 0]
`endif
reg [10:0] cnt;
reg [15:0] smpcnt;
reg [1:0] samples;
reg [15:0] smpshift;
wire mclk = cnt[2]; // mclk = clk/8
wire lrck = cnt[8]; // lrck = mclk/64
wire sclk = cnt[3]; // sclk = lrck*32
reg [2:0] mclk_sreg;
reg [2:0] lrck_sreg;
reg [1:0] sclk_sreg;
assign mclk_out = ~mclk_sreg[2];
assign lrck_out = lrck_sreg[2];
assign sclk_out = sclk_sreg[1];
wire lrck_rising = ({lrck_sreg[0],lrck} == 2'b01);
wire lrck_falling = ({lrck_sreg[0],lrck} == 2'b10);
wire sclk_rising = ({sclk_sreg[0],sclk} == 2'b01);
wire sclk_falling = ({sclk_sreg[0],sclk} == 2'b10);
wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
reg sdout_reg;
assign sdout = sdout_reg;
reg play_r;
initial begin
cnt = 9'h100;
smpcnt = 16'b0;
lrck_sreg = 2'b00;
sclk_sreg = 2'b00;
mclk_sreg = 2'b00;
dac_address_r = 9'b0;
vol_valid = 1'b0;
vol_latch_reg = 1'b0;
vol_reg = 9'h000;
vol_target_reg = 9'h000;
samples <= 2'b00;
end
/*
21477272.727272... / 37500 * 1232 = 44100 * 16
21281370 / 709379 * 23520 = 44100 * 16
*/
reg [19:0] phaseacc = 0;
wire [14:0] phasemul = (palmode ? 23520 : 1232);
wire [19:0] phasediv = (palmode ? 709379 : 37500);
reg [3:0] subcount = 0;
reg int_strobe = 0, comb_strobe = 0;
always @(posedge clkin) begin
int_strobe <= 0;
comb_strobe <= 0;
if(reset) begin
dac_address_r <= dac_address_ext;
phaseacc <= 0;
subcount <= 0;
end else if(sysclk_rising) begin
if(phaseacc >= phasediv) begin
phaseacc <= phaseacc - phasediv + phasemul;
subcount <= subcount + 1;
int_strobe <= 1;
if (subcount == 0) begin
comb_strobe <= 1;
dac_address_r <= dac_address_r + play_r;
end
end else begin
phaseacc <= phaseacc + phasemul;
end
end
end
parameter ST0_IDLE = 10'b1000000000;
parameter ST1_COMB1 = 10'b0000000001;
parameter ST2_COMB2 = 10'b0000000010;
parameter ST3_COMB3 = 10'b0000000100;
parameter ST4_INT1 = 10'b0000010000;
parameter ST5_INT2 = 10'b0000100000;
parameter ST6_INT3 = 10'b0001000000;
reg [63:0] ci[2:0], co[2:0], io[2:0];
reg [9:0] cicstate = 10'h200;
wire [63:0] bufi = {{16{dac_data[31]}}, dac_data[31:16], {16{dac_data[15]}}, dac_data[15:0]};
always @(posedge clkin) begin
if(reset) begin
cicstate <= ST0_IDLE;
{ci[2], ci[1], ci[0]} <= 192'h0;
{co[2], co[1], co[0]} <= 192'h0;
{io[2], io[1], io[0]} <= 192'h0;
end else if(int_strobe) begin
if(comb_strobe) cicstate <= ST1_COMB1;
else cicstate <= ST4_INT1;
end else begin
case(cicstate)
/****** COMB STAGES ******/
ST1_COMB1: begin
cicstate <= ST2_COMB2;
ci[0] <= bufi;
co[0][63:32] <= bufi[63:32] - ci[0][63:32];
co[0][31:0] <= bufi[31:0] - ci[0][31:0];
end
ST2_COMB2: begin
cicstate <= ST3_COMB3;
ci[1] <= co[0];
co[1][63:32] <= co[0][63:32] - ci[1][63:32];
co[1][31:0] <= co[0][31:0] - ci[1][31:0];
end
ST3_COMB3: begin
cicstate <= ST4_INT1;
ci[2] <= co[1];
co[2][63:32] <= co[1][63:32] - ci[2][63:32];
co[2][31:0] <= co[1][31:0] - ci[2][31:0];
end
/****** INTEGRATOR STAGES ******/
ST4_INT1: begin
io[0][63:32] <= co[2][63:32] + io[0][63:32];
io[0][31:0] <= co[2][31:0] + io[0][31:0];
cicstate <= ST5_INT2;
end
ST5_INT2: begin
io[1][63:32] <= io[0][63:32] + io[1][63:32];
io[1][31:0] <= io[0][31:0] + io[1][31:0];
cicstate <= ST6_INT3;
end
ST6_INT3: begin
io[2][63:32] <= io[1][63:32] + io[2][63:32];
io[2][31:0] <= io[1][31:0] + io[2][31:0];
cicstate <= ST0_IDLE;
end
default: begin
cicstate <= ST0_IDLE;
end
endcase
end
end
always @(posedge clkin) begin
cnt <= cnt + 1;
mclk_sreg <= {mclk_sreg[1:0], mclk};
lrck_sreg <= {lrck_sreg[1:0], lrck};
sclk_sreg <= {sclk_sreg[0], sclk};
vol_latch_reg <= {vol_latch_reg[0], vol_latch};
play_r <= play;
end
wire [9:0] vol_orig = volume + volume[7];
wire [9:0] vol_3db = volume + volume[7:1] + volume[7];
wire [9:0] vol_6db = {1'b0, volume, volume[7]} + volume[7];
wire [9:0] vol_9db = {1'b0, volume, 1'b0} + volume + volume[7:6];
wire [9:0] vol_12db = {volume, volume[7:6]};
reg [9:0] vol_scaled;
always @* begin
case(vol_select)
3'b000: vol_scaled = vol_orig;
3'b001: vol_scaled = vol_3db;
3'b010: vol_scaled = vol_6db;
3'b011: vol_scaled = vol_9db;
3'b100: vol_scaled = vol_12db;
default: vol_scaled = vol_orig;
endcase
end
always @(posedge clkin) begin
vol_target_reg <= vol_scaled;
end
always @(posedge clkin) begin
if (lrck_rising) begin
dac_address_r_sync <= dac_address_r;
end
end
// ramp volume only on sample boundaries
always @(posedge clkin) begin
if (lrck_rising) begin
if(vol_reg > vol_target_reg)
vol_reg <= vol_reg - 1;
else if(vol_reg < vol_target_reg)
vol_reg <= vol_reg + 1;
end
end
wire signed [15:0] dac_data_ch = lrck ? io[2][59:44] : io[2][27:12];
wire signed [25:0] vol_sample;
wire signed [15:0] vol_sample_sat;
assign vol_sample = dac_data_ch * $signed({1'b0, vol_reg});
assign vol_sample_sat = ((vol_sample[25:23] == 3'b000 || vol_sample[25:23] == 3'b111) ? vol_sample[23:8]
: vol_sample[25] ? 16'sh8000
: 16'sh7fff);
always @(posedge clkin) begin
if (sclk_falling) begin
smpcnt <= smpcnt + 1;
sdout_reg <= smpshift[15];
if (lrck_rising | lrck_falling) begin
smpshift <= vol_sample_sat;
end else begin
smpshift <= {smpshift[14:0], 1'b0};
end
end
end
`endif
endmodule
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#include <bits/stdc++.h> const int maxn(505); char ans[maxn]; int main() { int n; scanf( %d , &n); int nr(1), nc(1); ans[(n - 1) * 2] = 0 ; for (int i(0); i < n - 1; ++i) { printf( ? %d %d %d %d n , nr, nc + 1, n, n); fflush(stdout); char tmp[5]; scanf( %s , tmp); if (!strcmp(tmp, BAD )) { return 0; } else if (!strcmp(tmp, YES )) { ++nc; ans[i] = R ; } else if (!strcmp(tmp, NO )) { ++nr; ans[i] = D ; } else { printf( F**K n ); return 0; } } nr = nc = n; for (int i((n - 1) * 2 - 1); i >= n - 1; --i) { printf( ? 1 1 %d %d n , nr - 1, nc); fflush(stdout); char tmp[5]; scanf( %s , tmp); if (!strcmp(tmp, BAD )) { printf( F**K n ); return 0; } else if (!strcmp(tmp, YES )) { --nr; ans[i] = D ; } else if (!strcmp(tmp, NO )) { --nc; ans[i] = R ; } else { printf( F**K n ); return 0; } } printf( ! %s n , ans); fflush(stdout); return 0; }
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#include <bits/stdc++.h> using namespace std; int N, T, L, R, X, H; unordered_map<int, int> siz; unordered_map<int, pair<int, int> > par; pair<int, int> find(int now) { if (par.count(now)) { pair<int, int> a, b; a = par[now]; b = find(a.first); return {b.first, a.second ^ b.second}; } return {now, 0}; } int getsize(int now) { if (!siz.count(now)) { siz[now] = 1; } return siz[now]; } void merge(int x, int y, int z) { pair<int, int> a, b; a = find(x); b = find(y); if (a.first == b.first) { return; } if (getsize(a.first) > getsize(b.first)) { par[b.first] = {a.first, z ^ a.second ^ b.second}; siz[a.first] += siz[b.first]; } else { par[a.first] = {b.first, z ^ a.second ^ b.second}; siz[b.first] += siz[a.first]; } return; } int ans(int x, int y) { pair<int, int> a, b; a = find(x); b = find(y); if (a.first != b.first) { return -1; } return a.second ^ b.second; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> N; for (int i = 0; i < N; i++) { cin >> T >> L >> R; L ^= H; R ^= H; if (L > R) { swap(L, R); } if (T == 1) { cin >> X; X ^= H; merge(L - 1, R, X); } else { H = ans(L - 1, R); cout << H << n ; if (H == -1) { H = 1; } } } return 0; }
|
/*
8 bit up-down counter.
Based on code from Mojo tutorial
https://embeddedmicro.com/tutorials/mojo/pulse-width-modulation
/\ /\
/ \ / \
/ \ / \
/ \/ \
the CRT_LEN determines the period of the resulting counter
26 results in ~1s period.
*/
module counter #(parameter CTR_LEN = 27) (
input wire clk,
input wire rst,
output reg [7:0] value
);
//flip flop registers
reg[CTR_LEN-1:0] ctr_d, ctr_q;
//We are creating a count-up/count-down timer here with a
// triangular shape.
//The MSB determines the direction (up or down)
//The 8 next highest bits form out output value
//The remaining bits are not used (they are needed to get the timing
// right though, otherwise the counter would be too fast)
//There is a little trick if inverting the value to get
// it to count down instead of up when the MSB == 1
always @(ctr_q) begin
ctr_d = ctr_q + 1'b1;
if (ctr_q[CTR_LEN-1] == 1)
value = ~ctr_q[CTR_LEN-2:CTR_LEN-9];
else
value = ctr_q[CTR_LEN-2:CTR_LEN-9];
end
//standard positive edge of clk triggered always block
//reset sets the coutner to zero
//otherwise it sets the output (ctr_q) to the input (crt_d)
always @(posedge clk) begin
if (rst == 1) begin
ctr_q <= 'b0;
end else begin
ctr_q <= ctr_d;
end
end
endmodule
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#include <bits/stdc++.h> const int INF = 1e9 + 1; const int MOD = 1e9 + 7; using namespace std; void solve() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i += 1) cin >> a[i]; ; sort(a.begin(), a.end()); vector<int> ans; for (int i = 0; i < n; i += 1) { for (int j = 0; j < 31; j += 1) { int pv = a[i] - (1 << j); int nx = a[i] + (1 << j); bool pv_find = binary_search(a.begin(), a.end(), pv); bool nx_find = binary_search(a.begin(), a.end(), nx); if (pv_find && nx_find) { ans = {pv, a[i], nx}; break; } else if (pv_find) ans = {pv, a[i]}; else if (nx_find) ans = {a[i], nx}; } if ((int)ans.size() == 3) break; } if (ans.empty()) ans.push_back(a[0]); cout << (int)ans.size() << n ; for (int i = 0; i < (int)ans.size(); i += 1) cout << ans[i] << ; ; cout << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct nodo { int v, c, i, d; nodo() {} nodo(int V, int C, int I, int D) { v = V, c = C, i = I, d = D; } }; int ans[200055], I[200055]; int n, m; void solve(vector<vector<nodo> > v) { int d[m + 5]; memset(d, -1, sizeof(d)); queue<int> Q; Q.push(0); while (!Q.empty()) { int u = Q.front(); Q.pop(); for (int i = 0; i < v[u].size(); i++) { int id = v[u][i].i; if (d[id] == -1) { d[id] = v[u][i].d; int go = v[u][i].v; I[go] -= v[u][i].c; if (go != n - 1 && I[go] == 0) { Q.push(go); } } } } for (int i = 0; i < m; i++) ans[i] = d[i]; } int main() { scanf( %d%d , &n, &m); vector<vector<nodo> > v(n + 5); int a, b, c; for (int i = 0; i < m; i++) { scanf( %d%d%d , &a, &b, &c); a--; b--; v[a].push_back(nodo(b, c, i, 0)); v[b].push_back(nodo(a, c, i, 1)); I[a] += c; I[b] += c; } for (int i = 0; i < n; i++) I[i] /= 2; solve(v); for (int i = 0; i < m; i++) printf( %d n , ans[i]); }
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#include <bits/stdc++.h> using namespace std; bool compare(pair<double, int> p1, pair<double, int> p2) { return p1.first > p2.first; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, t1, t2, k; cin >> n >> t1 >> t2 >> k; vector<pair<double, int>> participants(n); int a, b; for (size_t i = 0; i < n; i++) { cin >> a >> b; participants[i] = make_pair(max(a * t1 * (100 - k) / 100.0 + b * t2, b * t1 * (100 - k) / 100.0 + a * t2), i + 1); } stable_sort(participants.begin(), participants.end(), compare); for (size_t i = 0; i < n; i++) cout << participants[i].second << << fixed << setprecision(2) << participants[i].first << endl; }
|
//======================================================================
//
// sha256.v
// --------
// Top level wrapper for the SHA-256 hash function providing
// a simple memory like interface with 32 bit data access.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, 201, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module sha256(
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam CTRL_MODE_BIT = 2;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam ADDR_BLOCK0 = 8'h10;
localparam ADDR_BLOCK15 = 8'h1f;
localparam ADDR_DIGEST0 = 8'h20;
localparam ADDR_DIGEST7 = 8'h27;
localparam CORE_NAME0 = 32'h73686132; // "sha2"
localparam CORE_NAME1 = 32'h2d323536; // "-256"
localparam CORE_VERSION = 32'h312e3830; // "1.80"
localparam MODE_SHA_224 = 1'h0;
localparam MODE_SHA_256 = 1'h1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg mode_reg;
reg mode_new;
reg mode_we;
reg ready_reg;
reg [31 : 0] block_reg [0 : 15];
reg block_we;
reg [255 : 0] digest_reg;
reg digest_valid_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire core_ready;
wire [511 : 0] core_block;
wire [255 : 0] core_digest;
wire core_digest_valid;
reg [31 : 0] tmp_read_data;
reg tmp_error;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
block_reg[04], block_reg[05], block_reg[06], block_reg[07],
block_reg[08], block_reg[09], block_reg[10], block_reg[11],
block_reg[12], block_reg[13], block_reg[14], block_reg[15]};
assign read_data = tmp_read_data;
assign error = tmp_error;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
sha256_core core(
.clk(clk),
.reset_n(reset_n),
.init(init_reg),
.next(next_reg),
.mode(mode_reg),
.block(core_block),
.ready(core_ready),
.digest(core_digest),
.digest_valid(core_digest_valid)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 16 ; i = i + 1)
block_reg[i] <= 32'h0;
init_reg <= 0;
next_reg <= 0;
ready_reg <= 0;
mode_reg <= MODE_SHA_256;
digest_reg <= 256'h0;
digest_valid_reg <= 0;
end
else
begin
ready_reg <= core_ready;
digest_valid_reg <= core_digest_valid;
init_reg <= init_new;
next_reg <= next_new;
if (mode_we)
mode_reg <= mode_new;
if (core_digest_valid)
digest_reg <= core_digest;
if (block_we)
block_reg[address[3 : 0]] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
// api_logic
//
// Implementation of the api logic. If cs is enabled will either
// try to write to or read from the internal registers.
//----------------------------------------------------------------
always @*
begin : api_logic
init_new = 0;
next_new = 0;
mode_new = 0;
mode_we = 0;
block_we = 0;
tmp_read_data = 32'h0;
tmp_error = 0;
if (cs)
begin
if (we)
begin
if (address == ADDR_CTRL)
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
mode_new = write_data[CTRL_MODE_BIT];
mode_we = 1;
end
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
block_we = 1;
end // if (we)
else
begin
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
tmp_read_data = block_reg[address[3 : 0]];
if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST7))
tmp_read_data = digest_reg[(7 - (address - ADDR_DIGEST0)) * 32 +: 32];
case (address)
// Read operations.
ADDR_NAME0:
tmp_read_data = CORE_NAME0;
ADDR_NAME1:
tmp_read_data = CORE_NAME1;
ADDR_VERSION:
tmp_read_data = CORE_VERSION;
ADDR_CTRL:
tmp_read_data = {29'h0, mode_reg, next_reg, init_reg};
ADDR_STATUS:
tmp_read_data = {30'h0, digest_valid_reg, ready_reg};
default:
begin
end
endcase // case (address)
end
end
end // addr_decoder
endmodule // sha256
//======================================================================
// EOF sha256.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; struct STree { vector<int> st; int n; STree(int n) : st(4 * n + 5, 0), n(n) {} void upd(int k, int s, int e, int p, int v) { if (s + 1 == e) { st[k] = v; return; } int m = (s + e) / 2; if (p < m) upd(2 * k, s, m, p, v); else upd(2 * k + 1, m, e, p, v); st[k] = (st[2 * k] | st[2 * k + 1]); } int query(int k, int s, int e, int pos, int v) { if (e - 1 < pos) return -1; if (s >= pos) { if (!(st[k] & v)) return -1; if (s + 1 == e) return s; } int m = (s + e) / 2; int ans = query(2 * k, s, m, pos, v); if (ans == -1) ans = query(2 * k + 1, m, e, pos, v); return ans; } void upd(int p, int v) { upd(1, 0, n, p, v); } int query(int a, int b) { return query(1, 0, n, a, b); } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { string s; int n, k; cin >> n >> k >> s; vector<int> a(n); int ne = n / 2 - k; for (int i = 0, ThxDem = 2 * (k - 1); i < ThxDem; ++i) a[i] = i % 2; for (int i = 2 * (k - 1), ThxDem = n; i < ThxDem; ++i) a[i] = i - 2 * (k - 1) > ne; STree st(n); for (int i = 0, ThxDem = n; i < ThxDem; ++i) st.upd(i, 1 << (s[i] == ) )); cout << n << n ; for (int i = 0, ThxDem = n; i < ThxDem; ++i) { int wh = st.query(i, 1 << a[i]); swap(s[i], s[wh]); st.upd(i, 1 << (s[i] == ) )); st.upd(wh, 1 << (s[wh] == ) )); cout << i + 1 << << wh + 1 << n ; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << 0 0 << endl; string left; cin >> left; int l = 0, r = 1e9; for (int i = 1; i < n; i++) { int mid = (l + r) / 2; cout << mid << 1 << endl; string s; cin >> s; if (s == left) { l = mid; } else { r = mid; } } cout << l << 2 << r << 0 << endl; return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.2
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fir_hw_smpl_V_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 18;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./fir_hw_smpl_V_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module fir_hw_smpl_V(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd18;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
fir_hw_smpl_V_ram fir_hw_smpl_V_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long b) { long long result = 1; while (b > 0) { if (b % 2 == 1) { result *= a; } a *= a; b /= 2; } return result; } long long gcd(long long x, long long y) { long long r; while (y != 0 && (r = x % y) != 0) { x = y; y = r; } return y == 0 ? x : y; } long long countSetBits(long long x) { long long Count = 0; while (x > 0) { if (x & 1) Count++; x = x >> 1; } return Count; } bool isPerfectSquare(long long n) { long long sr = sqrt(n); if (sr * sr == n) return true; else return false; } long long mod(long long x, long long M) { return ((x % M + M) % M); } long long add(long long a, long long b, long long M) { return mod(mod(a, M) + mod(b, M), M); } long long mul(long long a, long long b, long long M) { return mod(mod(a, M) * mod(b, M), M); } long long powerM(long long a, long long b, long long M) { long long res = 1; while (b) { if (b % 2 == 1) { res = mul(a, res, M); } a = mul(a, a, M); b /= 2; } return res; } long long modInverse(long long n, long long M) { return powerM(n, M - 2, M); } long long nCrM(long long n, long long r, long long M) { if (n < r) return 0; if (r == 0) return 1; vector<long long> fact(n + 1); fact[0] = 1; for (long long i = 1; i <= n; i++) { fact[i] = mul(fact[i - 1], i, M); } return mul(mul(fact[n], modInverse(fact[r], M), M), modInverse(fact[n - r], M), M); } long long n; vector<pair<long long, long long>> vv; map<pair<long long, long long>, long long> vis; long long ans = 0; void dfs(pair<long long, long long> p) { vis[p] = 1; for (long long i = 0; i < n; i++) { if (vis[vv[i]] == 0) { if (vv[i].first == p.first || vv[i].second == p.second) { dfs(vv[i]); } } } } void solve() { cin >> n; for (long long i = 0; i < n; i++) { long long x1, y1; cin >> x1 >> y1; vv.push_back({x1, y1}); } for (long long i = 0; i < n; i++) { if (vis[vv[i]] == 0) { dfs(vv[i]); ans++; } } cout << ans - 1 << n ; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; double dot(complex<double> a, complex<double> b) { return real(conj(a) * b); } double calcspeed(complex<double> p1, complex<double> p2, complex<double> w, double vmax) { complex<double> r = p2 - p1; double k = dot(r, w) + sqrt(pow(dot(r, w), 2) - norm(r) * (norm(w) - vmax * vmax)); k /= abs(r); return k; } double calc(complex<double> p1, complex<double> p2, complex<double> w, double vmax) { double speed = calcspeed(p1, p2, w, vmax); return abs(p2 - p1) / speed; } int main() { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; double vmax, t; cin >> vmax >> t; int vx, vy, wx, wy; cin >> vx >> vy >> wx >> wy; if (x1 == x2 && y1 == y2) { cout << 0 << endl; return 0; } complex<double> r(x2, y2), v(vx, vy), w(wx, wy); double ret = calc(complex<double>(x1, y1), complex<double>(x2, y2), v, vmax); if (ret < t) { printf( %.20f n , ret); return 0; } r -= complex<double>(x1, y1); v /= r; w /= r; vmax /= abs(r); r /= r; const double pi = acos(-1); double low = -pi + 1e-6; double high = pi - 1e-6; double f = 0; for (int i = (0); i < (200); i++) { double mid1 = (low * 2 + high) / 3; double mid2 = (low + high * 2) / 3; complex<double> target1 = polar(200.0, mid1); complex<double> target2 = polar(200.0, mid2); complex<double> speed1 = calcspeed(complex<double>(0, 0), target1, v, vmax); complex<double> speed2 = calcspeed(complex<double>(0, 0), target2, v, vmax); complex<double> point1 = speed1 * target1 / abs(target1) * t; complex<double> point2 = speed2 * target2 / abs(target2) * t; double f1 = calc(point1, r, w, vmax); double f2 = calc(point2, r, w, vmax); if (f1 > f2) { low = mid1; f = f1; } else { high = mid2; f = f2; } } printf( %.20f n , f + t); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD2_SYMBOL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD2_SYMBOL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv5sd2 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD2_SYMBOL_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_switches (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; constexpr int inf = 1e9 + 7; constexpr long long md = 1e6; void solve(int testi) { int n; cin >> n; if (n == 0) { cout << 1 << n ; ; return; } vector<int> digits = {6, 8, 4, 2}; cout << digits[n % digits.size()] << n ; ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); long long testn = 1; for (long long testi = 1; testi <= testn; testi++) { solve(testi); } }
|
//////////////////////////////////////////////////////////////////
////
////
//// CRCAHB CORE BLOCK
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// crcahb IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Julio Cesar
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module crc_ip
(
//OUTPUTS
output [31:0] HRDATA,
output HREADYOUT,
output HRESP,
//INPUTS
input [31:0] HWDATA,
input [31:0] HADDR,
input [ 2:0] HSIZE,
input [ 1:0] HTRANS,
input HWRITE,
input HSElx,
input HREADY,
input HRESETn,
input HCLK
);
//Internal Signals
wire [31:0] crc_poly_out;
wire [31:0] crc_out;
wire [31:0] crc_init_out;
wire [ 7:0] crc_idr_out;
wire buffer_full;
wire read_wait;
wire [31:0] bus_wr;
wire [ 1:0] crc_poly_size;
wire [ 1:0] bus_size;
wire [ 1:0] rev_in_type;
wire rev_out_type;
wire crc_init_en;
wire crc_idr_en;
wire crc_poly_en;
wire buffer_write_en;
wire reset_chain;
//Instanciation of Host Interface
host_interface HOST_INTERFACE
(
.HRDATA ( HRDATA ),
.HREADYOUT ( HREADYOUT ),
.HRESP ( HRESP ),
.bus_wr ( bus_wr ),
.crc_poly_size ( crc_poly_size ),
.bus_size ( bus_size ),
.rev_in_type ( rev_in_type ),
.rev_out_type ( rev_out_type ),
.crc_init_en ( crc_init_en ),
.crc_idr_en ( crc_idr_en ),
.crc_poly_en ( crc_poly_en ),
.buffer_write_en ( buffer_write_en ),
.reset_chain ( reset_chain ),
.reset_pending ( reset_pending ),
.HWDATA ( HWDATA ),
.HADDR ( HADDR ),
.HSIZE ( HSIZE ),
.HTRANS ( HTRANS ),
.HWRITE ( HWRITE ),
.HSElx ( HSElx ),
.HREADY ( HREADY ),
.HRESETn ( HRESETn ),
.HCLK ( HCLK ),
.crc_poly_out ( crc_poly_out ),
.crc_out ( crc_out ),
.crc_init_out ( crc_init_out ),
.crc_idr_out ( crc_idr_out ),
.buffer_full ( buffer_full ),
.read_wait ( read_wait )
);
//Instantiation of crc_unit
crc_unit CRC_UNIT
(
.crc_poly_out ( crc_poly_out ),
.crc_out ( crc_out ),
.crc_init_out ( crc_init_out ),
.crc_idr_out ( crc_idr_out ),
.buffer_full ( buffer_full ),
.read_wait ( read_wait ),
.bus_wr ( bus_wr ),
.crc_poly_size ( crc_poly_size ),
.bus_size ( bus_size ),
.rev_in_type ( rev_in_type ),
.rev_out_type ( rev_out_type ),
.crc_init_en ( crc_init_en ),
.crc_idr_en ( crc_idr_en ),
.crc_poly_en ( crc_poly_en ),
.buffer_write_en ( buffer_write_en ),
.reset_chain ( reset_chain ),
.reset_pending ( reset_pending ),
.clk ( HCLK ),
.rst_n ( HRESETn )
);
endmodule
|
/*------------------------------------------------------------------------------
Purpose
Placement test environment with CPU core.
------------------------------------------------------------------------------*/
`include "tenv_test/tenv_test.v"
`include "tenv_link.v"
`include "tenv_4ssram_wishbone.v"
module testbench;
/*------------------------------------------------------------------------------
Test environment
------------------------------------------------------------------------------*/
initial
begin
tenv_test.start;
$finish;
end
tenv_test tenv_test();
tenv_link tenv_link();
//EXCEPTION HANDLER PROGRAM
tenv_4ssram_wishbone #(.WADDR(13), .WDATA(8))
tenv_pexc ();
//MAIN PROGRAM
tenv_4ssram_wishbone #(.WADDR(13), .WDATA(8))
tenv_pmain ();
//DATA MEMORY
tenv_4ssram_wishbone #(.WADDR(6), .WDATA(8))
tenv_dmem ();
/*------------------------------------------------------------------------------
DUT
------------------------------------------------------------------------------*/
mips_cpucore
cpucore();
endmodule
|
`timescale 1ns / 1ps
module WhacAMole(BCD1, BCD0, mole_position, random, mallet_position, timesup, PRESS_VALID, reset, clk_1us);
input PRESS_VALID, reset, clk_1us;
input [3:0] random;
input [3:0] mallet_position;
input timesup;
output [3:0] BCD1, BCD0;
output [4:0] mole_position;
reg [4:0] mole_position;
wire [4:0] next_mole;
reg [3:0] BCD0, BCD1;
wire [3:0] next_BCD0, next_BCD1;
reg[19:0] counter500000, next_counter500000; //500000 * 1us = 0.5s
reg [1:0] state, next_state;
reg generatenewmole, next_generatenewmole;
wire hit;
parameter status0 = 2'h0;
parameter status1 = 2'h1;
parameter status2 = 2'h2;
always @(posedge clk_1us or negedge reset)begin
if(!reset)begin
mole_position <= 5'd0;
state <= 2'd0;
BCD0 <= 4'd0;
BCD1 <= 4'd0;
counter500000 <= 20'd0;
generatenewmole <= 0;
end else begin
mole_position <= next_mole;
state <= next_state;
BCD0 <= next_BCD0;
BCD1 <= next_BCD1;
counter500000 <= next_counter500000;
generatenewmole <= next_generatenewmole;
end
end
always @(*) begin
case (state)
status0: begin
if(hit) begin
next_state = status2;
next_counter500000 = 20'd0;
end else if(counter500000==20'd500000) begin
next_state = status1;
next_counter500000 = 20'd0;
end else begin
next_state = state;
next_counter500000 = counter500000 + 20'd1;
end
next_generatenewmole = 0;
end
status1: begin
if(hit) begin
next_state = status2;
next_counter500000 = 20'd0;
end else if(counter500000==20'd500000) begin
next_state = status2;
next_counter500000 = 20'd0;
end else begin
next_state = state;
next_counter500000 = counter500000 + 20'd1;
end
next_generatenewmole = 0;
end
// disappear and generate next new mole (hit or 1s after appear)
status2: begin
if(counter500000==20'd500000) begin
next_state = status0;
next_counter500000 = 20'd0;
next_generatenewmole = 1;
end else begin
next_state = state;
next_counter500000 = counter500000 + 20'd1;
next_generatenewmole = 0;
end
end
default: begin
next_state = 2'd0;
next_counter500000 = 20'd0;
next_generatenewmole = 1;
end
endcase
end
// judge the hit and update the scores
assign next_BCD0 = (hit==4'd1) ? ( (BCD0==4'd9) ? 4'd0 : (BCD0+4'd1) ) : BCD0;
assign next_BCD1 = (hit==4'd1) ? ( (BCD0==4'd9) ? (BCD1+4'd1) : BCD1 ) : BCD1;
assign hit = ((mallet_position == mole_position[3:0])&&(!timesup)&&(PRESS_VALID)) ? 1'd1 : 1'd0;
//one bit for "no mole to show" ( 5'b10000 = 16'd0 = none -> refer MoleDecoder.v )
assign next_mole = (hit) ? 5'b10000 : ((state==status2) ? 5'b10000 : ((generatenewmole && !timesup) ? random : mole_position));
endmodule
|
#include <bits/stdc++.h> const int inf = 0xfffffff; const long long INF = 1ll << 61; using namespace std; int n, s, k; int aa[100 + 55][100 + 55]; int ans; void init() { memset(aa, 0, sizeof(aa)); } bool input() { while (scanf( %d %d %d , &n, &s, &k) == 3) { for (int i = 0; i < n; i++) for (int j = 0; j < s; j++) scanf( %d , &aa[i][j]); return false; } return true; } void cal() { ans = 11; if (n < s) { for (int i = 0; i < s; i++) for (int j = i + 1; j < s; j++) swap(aa[i][j], aa[j][i]); swap(n, s); } if (n <= k) { for (int i = 0; i < (1 << s); i++) { int sum = 0; for (int j = 0; j < n; j++) { int now = 0; for (int l = 0; l < s; l++) { if (i & (1 << l)) { if (!aa[j][l]) now++; } else { if (aa[j][l]) now++; } } sum += min(now, s - now); } ans = min(ans, sum); } } else { for (int i = 0; i < n; i++) { int sum = 0; for (int j = 0; j < n; j++) { int now = 0; for (int l = 0; l < s; l++) { if (aa[i][l] != aa[j][l]) now++; } sum += min(now, s - now); } ans = min(ans, sum); } } } void output() { if (ans <= k) cout << ans << endl; else puts( -1 ); } int main() { while (true) { init(); if (input()) return 0; cal(); output(); } }
|
`timescale 1 ns / 1 ps
module sample_generator_v1_0_S_AXIS #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// AXI4Stream sink: Data Width
parameter integer C_S_AXIS_TDATA_WIDTH = 32
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// AXI4Stream sink: Clock
input wire S_AXIS_ACLK,
// AXI4Stream sink: Reset
input wire S_AXIS_ARESETN,
// Ready to accept data in
output wire S_AXIS_TREADY,
// Data in
input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
// Byte qualifier
input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
// Indicates boundary of last packet
input wire S_AXIS_TLAST,
// Data is in valid
input wire S_AXIS_TVALID
);
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction
// Total number of input data.
localparam NUMBER_OF_INPUT_WORDS = 8;
// bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
// Define the states of state machine
// The control state machine oversees the writing of input streaming data to the FIFO,
// and outputs the streaming data from the FIFO
parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
WRITE_FIFO = 1'b1; // In this state FIFO is written with the
// input stream data S_AXIS_TDATA
wire axis_tready;
// State variable
reg mst_exec_state;
// FIFO implementation signals
genvar byte_index;
// FIFO write enable
wire fifo_wren;
// FIFO full flag
reg fifo_full_flag;
// FIFO write pointer
reg [bit_num-1:0] write_pointer;
// sink has accepted all the streaming data and stored in FIFO
reg writes_done;
// I/O Connections assignments
assign S_AXIS_TREADY = axis_tready;
// Control state machine implementation
always @(posedge S_AXIS_ACLK)
begin
if (!S_AXIS_ARESETN)
// Synchronous reset (active low)
begin
mst_exec_state <= IDLE;
end
else
case (mst_exec_state)
IDLE:
// The sink starts accepting tdata when
// there tvalid is asserted to mark the
// presence of valid streaming data
if (S_AXIS_TVALID)
begin
mst_exec_state <= WRITE_FIFO;
end
else
begin
mst_exec_state <= IDLE;
end
WRITE_FIFO:
// When the sink has accepted all the streaming input data,
// the interface swiches functionality to a streaming master
if (writes_done)
begin
mst_exec_state <= IDLE;
end
else
begin
// The sink accepts and stores tdata
// into FIFO
mst_exec_state <= WRITE_FIFO;
end
endcase
end
// AXI Streaming Sink
//
// The example design sink is always ready to accept the S_AXIS_TDATA until
// the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
always@(posedge S_AXIS_ACLK)
begin
if(!S_AXIS_ARESETN)
begin
write_pointer <= 0;
writes_done <= 1'b0;
end
else
if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
begin
if (fifo_wren)
begin
// write pointer is incremented after every write to the FIFO
// when FIFO write signal is enabled.
write_pointer <= write_pointer + 1;
writes_done <= 1'b0;
end
if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
begin
// reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
// has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
writes_done <= 1'b1;
end
end
end
// FIFO write enable generation
assign fifo_wren = S_AXIS_TVALID && axis_tready;
// FIFO Implementation
generate
for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
begin:FIFO_GEN
reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
// Streaming input data is stored in FIFO
always @( posedge S_AXIS_ACLK )
begin
if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
begin
stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
end
end
end
endgenerate
// Add user logic here
// User logic ends
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100000 + 10; struct TreeNode { int L, R; pair<double, double> val; } tree[maxn << 2]; int a[maxn], b[maxn], n, q; void pushUp(int root) { tree[root].val.first = tree[root << 1].val.first * tree[root << 1 | 1].val.first; tree[root].val.second = tree[root << 1].val.second + tree[root << 1].val.first * tree[root << 1 | 1].val.second; } void build(int L, int R, int root) { tree[root].L = L; tree[root].R = R; if (L == R) { return; } int mid = (L + R) >> 1; build(L, mid, root << 1); build(mid + 1, R, root << 1 | 1); } void update(int pos, pair<double, double> val, int root) { int L = tree[root].L, R = tree[root].R; if (L == R) { tree[root].val = val; return; } int mid = (L + R) >> 1; if (pos <= mid) { update(pos, val, root << 1); } else { update(pos, val, root << 1 | 1); } pushUp(root); } pair<double, double> query(int ql, int qr, int root) { int L = tree[root].L, R = tree[root].R; if (L >= ql && R <= qr) return tree[root].val; int mid = (L + R) >> 1; pair<double, double> a = make_pair(1.0, 0.0), b = make_pair(1.0, 0.0), c; if (ql <= mid) { a = query(ql, qr, root << 1); } if (qr > mid) { b = query(ql, qr, root << 1 | 1); } c.first = a.first * b.first; c.second = a.second + a.first * b.second; return c; } int main() { cin >> n >> q; build(1, n, 1); for (int i = 1; i <= n; i++) { double x, y; cin >> x >> y; double p = x / y; update(i, make_pair((1 - p) / p, (1 - p) / p), 1); } while (q--) { int type; cin >> type; if (type == 1) { int i, x, y; scanf( %d%d%d , &i, &x, &y); double p = double(x) / y; update(i, make_pair((1.0 - p) / p, (1.0 - p) / p), 1); } else { int l, r; scanf( %d%d , &l, &r); pair<double, double> t = query(l, r, 1); double p = t.second; if (p < 1e20) printf( %.6lf n , 1.0 / (1 + p)); else cout << 0.0000000 << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<pair<string, long long> > Name(1010); long long n; vector<vector<pair<string, long long> > > a(1010); map<string, long long> already; map<string, long long>::iterator ii; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; long long i, j; for (i = 1; i <= n; i++) { string w; long long version; cin >> w >> version; if (i == 1) { already[w] = version; } Name[i] = make_pair(w, version); long long m; cin >> m; for (j = 0; j < m; j++) { cin >> w >> version; a[i].push_back(make_pair(w, version)); } } vector<pair<string, long long> > q; map<string, long long> pretendent; q.push_back(Name[1]); while (q.size() > 0) { long long qs = 0, qf = q.size(); vector<pair<string, long long> > temp; temp.clear(); pretendent.clear(); while (qs < qf) { long long cur; for (i = 1; i <= n; i++) { if (Name[i].first == q[qs].first && Name[i].second == q[qs].second) cur = i; } for (i = 0; i < a[cur].size(); i++) { string task = a[cur][i].first; long long version = a[cur][i].second; if (already[task] == 0) pretendent[task] = max(pretendent[task], version); } qs++; } q.clear(); for (ii = pretendent.begin(); ii != pretendent.end(); ii++) { string task = ii->first; long long version = ii->second; already[task] = version; q.push_back(make_pair(task, version)); } } if (already[Name[1].first] == Name[1].second) already.erase(Name[1].first); cout << already.size() << endl; for (ii = already.begin(); ii != already.end(); ii++) { cout << ii->first << << ii->second << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, a, b; cin >> n >> a >> b; long long ma, mi; ma = max(a, b); mi = min(a, b); long long seated = 0; for (long long i = (long long)(0); i < (long long)(n); i++) { char t; cin >> t; while (t == . and i < n) { if (ma != 0) { ma--; seated++; } a = ma; ma = mi; mi = a; i++; if (i < n) cin >> t; } a = ma; ma = max(mi, ma); mi = min(mi, a); } cout << seated << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
wire buf0_out_Q ;
wire not1_out_qn;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int oriArr[2000001] = {0}; int arr[2000001]; int main() { int oriCnt; cin >> oriCnt; int maxOri = 0; for (int i = 0; i < oriCnt; i++) { int tmp; cin >> tmp; oriArr[tmp] = 1; if (maxOri < tmp) maxOri = tmp; } arr[0] = 0; int cnt = 0; for (int i = 1; i <= maxOri; i++) { if (oriArr[i] == 0) { arr[i] = arr[i - 1]; } else { arr[i] = i; cnt++; } } if (cnt == 1) { cout << 0 << endl; return 0; } int max = 0; for (int i = maxOri - 1; i >= 0; i--) { if (arr[i] < max) break; if (oriArr[i] == 0) continue; for (int j = 2; arr[i] * (j - 1) <= maxOri; j++) { int tmp = j * arr[i] - 1; if (tmp > maxOri) tmp = maxOri; if (arr[tmp] % arr[i] > max) max = arr[tmp] % arr[i]; } } cout << max << endl; return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_bram_7vx_8k.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_bram_7vx_8k.v //
// Description : Implements 8 KB Dual Ported Memory //
// - Output Regs are always enabled //
// - if INTERFACE_SPEED = 500 MHz -> 4xRAMB36E1 in TDP mode //
// - if INTERFACE_SPEED = 250 MHz -> 2xRAMB36E1 in SDP mode //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_8k.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_bram_7vx_8k #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [8:0] waddr0_i, // write address
input [8:0] waddr1_i, // write address
input [127:0] wdata_i, // write data
input [15:0] wdip_i, // write parity
input [3:0] wen_i, // write enable
input [8:0] raddr0_i, // write address
input [8:0] raddr1_i, // write address
output [127:0] rdata_o, // read data
output [15:0] rdop_o, // read parity
input [3:0] ren_i // read enable
);
genvar i;
wire [3:0] wen = {wen_i[3], wen_i[2], wen_i[1], wen_i[0]};
wire [3:0] ren = {ren_i[3], ren_i[2], ren_i[1], ren_i[0]};
wire [35:0] waddr = {waddr1_i, waddr1_i, waddr0_i, waddr0_i};
wire [35:0] raddr = {raddr1_i, raddr1_i, raddr0_i, raddr0_i};
generate
for (i = 0; i < 4; i = i + 1) begin : RAMB18E1
RAMB18E1 #(
.SIM_DEVICE ("7SERIES"),
.DOA_REG ( 1 ),
.DOB_REG ( 1 ),
.SRVAL_A ( 36'h00000 ),
.INIT_FILE ( "NONE" ),
.RAM_MODE ( "SDP" ),
.READ_WIDTH_A ( 36 ),
.READ_WIDTH_B ( 0 ),
.RSTREG_PRIORITY_A ( "REGCE" ),
.RSTREG_PRIORITY_B ( "REGCE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.INIT_A ( 36'h00000 ),
.INIT_B ( 36'h00000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.WRITE_WIDTH_A ( 0 ),
.WRITE_WIDTH_B ( 36 ),
.SRVAL_B ( 36'h00000 ))
u_fifo (
.CLKARDCLK(clk_i),
.CLKBWRCLK(clk_i),
.ENARDEN(ren[i]),
.ENBWREN(1'b1),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0 ),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.ADDRARDADDR({raddr[(9*i)+8:(9*i)+0], 5'b0}),
.ADDRBWRADDR({waddr[(9*i)+8:(9*i)+0], 5'b0}),
.DIADI(wdata_i[(2*16*i)+15:(2*16*i)+0]),
.DIBDI(wdata_i[(2*16*i)+31:(2*16*i)+16]),
.DIPADIP(wdip_i[(2*2*i)+1:(2*2*i)+0]),
.DIPBDIP(wdip_i[(2*2*i)+3:(2*2*i)+2]),
.DOADO(rdata_o[(2*16*i)+15:(2*16*i)+0]),
.DOBDO(rdata_o[(2*16*i)+31:(2*16*i)+16]),
.DOPADOP(rdop_o[(2*2*i)+1:(2*2*i)+0]),
.DOPBDOP(rdop_o[(2*2*i)+3:(2*2*i)+2]),
.WEA({2'b00}),
.WEBWE({4{wen[i]}})
);
end
endgenerate
endmodule // pcie_bram_7vx_8k
|
module axis_shifter_v2 #
(
parameter integer C_PIXEL_WIDTH = 8,
parameter integer C_IMG_WBITS = 12,
parameter integer C_IMG_HBITS = 12
)
(
input wire clk,
input wire resetn,
input wire fsync,
input wire lsync,
input wire [C_IMG_WBITS-1 : 0] col_idx,
input wire [C_IMG_WBITS-1 : 0] col_idx_next,
input wire col_update,
input wire [C_IMG_HBITS-1 : 0] row_idx,
///input wire [C_IMG_HBITS-1 : 0] row_idx_next,
input wire row_update,
input wire [C_IMG_WBITS-1 : 0] s_win_left,
input wire [C_IMG_HBITS-1 : 0] s_win_top,
input wire [C_IMG_WBITS-1 : 0] s_win_width,
input wire [C_IMG_HBITS-1 : 0] s_win_height,
output wire s_need,
output reg s_eol,
output wire s_sof
);
reg col_need;
reg row_need;
always @ (posedge clk) begin
if (resetn == 1'b0 || lsync)
col_need <= 0;
else if (col_update) begin
if (col_idx == s_win_left + s_win_width)
col_need <= 0;
else if (col_idx == s_win_left)
col_need <= 1;
else
col_need <= col_need;
end
else
col_need <= col_need;
end
always @ (posedge clk) begin
if (resetn == 1'b0 || fsync)
row_need <= 0;
else if (row_update) begin
if (row_idx == s_win_top + s_win_height)
row_need <= 0;
else if (row_idx == s_win_top)
row_need <= 1;
else
row_need <= row_need;
end
else
row_need <= row_need;
end
assign s_need = (col_need && row_need);
reg first_line;
always @ (posedge clk) begin
if (resetn == 1'b0)
first_line <= 0;
else if (row_update)
first_line <= (row_idx == s_win_top);
else
first_line <= first_line;
end
reg first_pixel;
always @ (posedge clk) begin
if (resetn == 1'b0)
first_pixel <= 0;
else if (col_update)
first_pixel <= (col_idx == s_win_left);
else
first_pixel <= first_pixel;
end
assign s_sof = first_line && first_pixel;
always @ (posedge clk) begin
if (resetn == 1'b0)
s_eol <= 0;
else if (col_update)
s_eol <= (col_idx_next == s_win_left + s_win_width);
else
s_eol <= s_eol;
end
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_length_adjust
*/
module test_axis_frame_length_adjust_8;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg status_ready = 0;
reg [15:0] length_min = 0;
reg [15:0] length_max = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire status_valid;
wire status_frame_pad;
wire status_frame_truncate;
wire [15:0] status_frame_length;
wire [15:0] status_frame_original_length;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready,
status_ready,
length_min,
length_max
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
status_valid,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length
);
// dump file
$dumpfile("test_axis_frame_length_adjust_8.lxt");
$dumpvars(0, test_axis_frame_length_adjust_8);
end
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_valid(status_valid),
.status_ready(status_ready),
.status_frame_pad(status_frame_pad),
.status_frame_truncate(status_frame_truncate),
.status_frame_length(status_frame_length),
.status_frame_original_length(status_frame_original_length),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
endmodule
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Thu Mar 20 14:12:08 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/lab_2/part_4/ip/clk_video/clk_video_funcsim.v
// Design : clk_video
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_video,clk_wiz_v5_1,{component_name=clk_video,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_video
(clk_100MHz,
clk_193MHz,
locked);
input clk_100MHz;
output clk_193MHz;
output locked;
wire clk_100MHz;
wire clk_193MHz;
wire locked;
clk_videoclk_video_clk_wiz U0
(.clk_100MHz(clk_100MHz),
.clk_193MHz(clk_193MHz),
.locked(locked));
endmodule
module clk_videoclk_video_clk_wiz
(clk_100MHz,
clk_193MHz,
locked);
input clk_100MHz;
output clk_193MHz;
output locked;
wire \<const0> ;
wire \<const1> ;
wire clk_100MHz;
wire clk_100MHz_clk_video;
wire clk_193MHz;
wire clk_193MHz_clk_video;
wire clkfbout_buf_clk_video;
wire clkfbout_clk_video;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_video),
.O(clkfbout_buf_clk_video));
(* box_type = "PRIMITIVE" *)
BUFG clkin1_bufg
(.I(clk_100MHz),
.O(clk_100MHz_clk_video));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_193MHz_clk_video),
.O(clk_193MHz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(45.875000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(4.750000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("BUF_IN"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_video),
.CLKFBOUT(clkfbout_clk_video),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_100MHz_clk_video),
.CLKIN2(\<const0> ),
.CLKINSEL(\<const1> ),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_193MHz_clk_video),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.DCLK(\<const0> ),
.DEN(\<const0> ),
.DI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(\<const0> ),
.LOCKED(locked),
.PSCLK(\<const0> ),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(\<const0> ),
.PSINCDEC(\<const0> ),
.PWRDWN(\<const0> ),
.RST(\<const0> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
module f16ToRecF16 (input [15:0] in, output [16:0] out);
fNToRecFN#(5, 11) fNToRecFN(in, out);
endmodule
module f32ToRecF32 (input [31:0] in, output [32:0] out);
fNToRecFN#(8, 24) fNToRecFN(in, out);
endmodule
module f64ToRecF64 (input [63:0] in, output [64:0] out);
fNToRecFN#(11, 53) fNToRecFN(in, out);
endmodule
module f128ToRecF128 (input [127:0] in, output [128:0] out);
fNToRecFN#(15, 113) fNToRecFN(in, out);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 8e5 + 5; struct trie { int a[26]; vector<int> val[2]; } a[N]; int vis[N][2]; char ch[800005]; int cnt, n; void insert(char ch[], int op, int k) { int u = 0; int len = strlen(ch + 1); a[u].val[op].push_back(k); for (int i = 1; i <= len; i++) { if (!a[u].a[ch[i] - a ]) a[u].a[ch[i] - a ] = ++cnt; u = a[u].a[ch[i] - a ]; a[u].val[op].push_back(k); } } int dfs(int k, int dep) { int ans = 0; for (int i = 0; i < 26; i++) if (a[k].a[i]) ans += dfs(a[k].a[i], dep + 1); vector<int> t[2]; for (int i = 0; i <= 1; i++) for (int j = 0; j < a[k].val[i].size(); j++) if (!vis[a[k].val[i][j]][i]) t[i].push_back(a[k].val[i][j]); int tmp = min(t[0].size(), t[1].size()); ans += tmp * dep; for (int i = 0; i < tmp; i++) { vis[t[0][i]][0] = t[1][i]; vis[t[1][i]][1] = t[0][i]; } return ans; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s , ch + 1); insert(ch, 0, i); } for (int i = 1; i <= n; i++) { scanf( %s , ch + 1); insert(ch, 1, i); } printf( %d n , dfs(0, 0)); for (int i = 1; i <= n; i++) printf( %d %d n , i, vis[i][0]); return 0; }
|
#include <bits/stdc++.h> using namespace std; map<int, int> uf; map<int, vector<int> > contents; map<int, int> val; void make(int a) { if (uf.find(a) == uf.end()) { uf[a] = a; contents[a].push_back(a); val[a] = 0; } } int main() { cin.sync_with_stdio(0); cin.tie(0); int q; cin >> q; int last = 0; for (int i = 0; i < q; i++) { int t; cin >> t; if (t == 1) { int l, r, x; cin >> l >> r >> x; l ^= last; r ^= last; x ^= last; if (l > r) swap(l, r); r++; make(l); make(r); if (uf[l] == uf[r]) continue; int v = val[l] ^ val[r] ^ x; l = uf[l]; r = uf[r]; if (contents[l].size() > contents[r].size()) { swap(l, r); } for (int a : contents[l]) { uf[a] = r; val[a] ^= v; contents[r].push_back(a); } contents.erase(l); } else { int l, r; cin >> l >> r; l ^= last; r ^= last; if (l > r) swap(l, r); r++; make(l); make(r); if (uf[l] != uf[r]) { cout << -1 << n ; last = 1; } else { cout << (val[l] ^ val[r]) << n ; last = val[l] ^ val[r]; } } } }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always if ( constant) statement ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
begin
value1 = 0;
# 5 ;
if(value1 != 4'd4)
$display("FAILED - always 3.1.5A always if ( constant) statement \n");
else
$display("PASSED");
$finish;
end
always if( 1'b1) begin
# 1;
value1 = value1 + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int Length[1001], n, x, a[1001], Concern, Pos, Ppl; vector<int> Queues, adj[1001], Ans; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n >> x; for (int i = 1; i <= n; ++i) { cin >> a[i]; if (a[i]) adj[a[i]].push_back(i); } for (int i = 1; i <= n; ++i) { if (a[i] == 0) { Ppl = i; int len = 0; while (Ppl) { ++len; if (Ppl == x) Concern = i, Pos = len; if (adj[Ppl].size()) Ppl = adj[Ppl][0]; else Ppl = 0; } if (Concern != i) Queues.push_back(len); } } for (int i = Queues.size() - 1; i >= 0; --i) { vector<int> Add; for (int j = 0; j < Ans.size(); ++j) { if (!Length[Ans[j] + Queues[i]]) Add.push_back(Ans[j] + Queues[i]), Length[Ans[j] + Queues[i]] = 1; } for (int j = 0; j < Add.size(); ++j) Ans.push_back(Add[j]); if (!Length[Queues[i]]) Ans.push_back(Queues[i]), Length[Queues[i]] = 1; } cout << Pos << n ; sort(Ans.begin(), Ans.end()); for (int i = 0; i < Ans.size(); ++i) cout << Pos + Ans[i] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n; cin >> n; int a[n], b[n]; for (int i = 0; i < n; i++) cin >> a[i]; string s; cin >> s; vector<pair<long long, pair<long long, long long>>> c(n); for (int i = 0; i < n; i++) { c[i].second.first = a[i]; c[i].second.second = i; c[i].first = (s[i] - 0 ); } sort(c.begin(), c.end()); long long cnt = 1; for (int i = 0; i < n; i++) { b[c[i].second.second] = cnt; cnt++; } for (int i = 0; i < n; i++) { cout << b[i] << ; } cout << endl; } }
|
// ====================================================================
// Bashkiria-2M FPGA REPLICA
//
// Copyright (C) 2010 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Bashkiria-2M home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: k580ww55.v
//
// Parallel interface k580ww55 design file of Bashkiria-2M replica.
//
// Warning: This realization is not fully operational.
module k580ww55(
input clk, input reset, input[1:0] addr, input we_n,
input[7:0] idata, output reg[7:0] odata,
input[7:0] ipa, output reg[7:0] opa,
input[7:0] ipb, output reg[7:0] opb,
input[7:0] ipc, output reg[7:0] opc);
//reg[6:0] mode;
always begin
case (addr)
2'b00: odata = ipa;
2'b01: odata = ipb;
2'b10: odata = ipc;
2'b11: odata = 8'h00;
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
//mode <= 7'b0011011;
{opa,opb,opc} <= {8'hFF,8'hFF,8'hFF};
end else
if (~we_n) begin
if (addr==2'b00) opa <= idata;
if (addr==2'b01) opb <= idata;
if (addr==2'b10) opc <= idata;
//if (addr==2'b11 && idata[7]) mode <= idata[6:0];
if (addr==2'b11 && ~idata[7]) opc[idata[3:1]] <= idata[0];
end
end
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cyclone4gx_pmem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cyclone4gx_pmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [11:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV GX",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0]
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, const U &b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, const U &b) { if (a < b) a = b; } template <class T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T1, class T2> inline void gn(T1 &x1, T2 &x2) { gn(x1), gn(x2); } template <class T1, class T2, class T3> inline void gn(T1 &x1, T2 &x2, T3 &x3) { gn(x1, x2), gn(x3); } template <class T> inline void print(T first) { if (first < 0) { putchar( - ); return print(-first); } if (first < 10) { putchar( 0 + first); return; } print(first / 10); putchar(first % 10 + 0 ); } template <class T> inline void println(T first) { print(first); putchar( n ); } template <class T> inline void printsp(T first) { print(first); putchar( ); } template <class T1, class T2> inline void print(T1 x1, T2 x2) { printsp(x1), println(x2); } template <class T1, class T2, class T3> inline void print(T1 x1, T2 x2, T3 x3) { printsp(x1), printsp(x2), println(x3); } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = (long long)a * a % m) if (b & 1) ans = (long long)ans * a % m; return ans; } int a[3010], arr[3010], n, nn; long long dp[3010][3010]; int main() { gn(n); for (int i = 1; i <= n; i++) { gn(a[i]); a[i] -= i; arr[i] = a[i]; } sort(arr + 1, arr + n + 1); nn = unique(arr + 1, arr + n + 1) - arr - 1; for (int i = 1; i <= n; i++) { dp[i][0] = 0x3f3f3f3f3f3f3f3fLL; for (int j = 1; j <= nn; j++) { dp[i][j] = abs(a[i] - arr[j]); dp[i][j] += dp[i - 1][j]; smin(dp[i][j], dp[i][j - 1]); } } print(dp[n][nn]); }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; void printV(vector<int> &S) { for (int s : S) { cout << s; } cout << endl; } void solve() { int x; cin >> x; string T; cin >> T; vector<int> S; for (int i = 0; i < (int)T.size(); i++) { S.push_back(T[i] - 0 ); } int l = 0; while (x > (int)S.size()) { int end = (int)S.size(); for (int rp = 0; rp < S[l] - 1; rp++) { for (int i = l + 1; i < end; i++) { S.push_back(S[i]); } } l++; } long long len = (long long)S.size() - l - 1; for (int i = l; i < x; i++) { len *= S[i]; len--; len %= MOD; } cout << (len + x + 1 + MOD) % MOD << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t; cin >> t; for (int i = 0; i < t; i++) solve(); }
|
#include <bits/stdc++.h> using namespace std; int n, tx, ty; vector<pair<int, int> > ar; int vis[100010]; bool check(int first, int second, int x1, int y1, int x2, int y2) { if ((1LL * x2 - 1LL * x1) * 1LL * (1LL * second - 1LL * y1) == (1LL * y2 - 1LL * y1) * 1LL * (1LL * first - 1LL * x1)) return true; return false; } int main(int argc, char const *argv[]) { scanf( %d , &n); ar.clear(); for (int i = 0; i < n; i++) { scanf( %d%d , &tx, &ty); ar.push_back({tx, ty}); } if (n == 1) { cout << YES n ; } else if (n == 2) { cout << YES n ; } else { memset(vis, 0, sizeof(vis)); for (int i = 0; i < n; i++) { if (check(ar[i].first, ar[i].second, ar[0].first, ar[0].second, ar[1].first, ar[1].second)) { vis[i] = 1; } } int x1, y1, x2, y2, flag = 0, hold1, hold2; for (int j = 0; j < n; j++) { if (!vis[j]) { flag++; x1 = ar[j].first; y1 = ar[j].second; vis[j] = 1; hold1 = j; break; } } for (int j = 0; j < n; j++) { if (!vis[j]) { flag++; x2 = ar[j].first; y2 = ar[j].second; int fgh = 1; if (check(ar[0].first, ar[0].second, x1, y1, x2, y2) || check(ar[1].first, ar[1].second, x1, y1, x2, y2)) { fgh = 0; hold2 = j; continue; } if (fgh) { vis[j] = 1; hold2 = j; } break; } } vis[hold2] = 1; if (flag == 0 || flag == 1) { cout << YES n ; } else { for (int i = 0; i < n; i++) { if (check(ar[i].first, ar[i].second, x1, y1, x2, y2)) { vis[i] = 1; } } flag = 0; for (int i = 0; i < n; i++) { if (!vis[i]) { flag = 1; } } if (!flag) cout << YES n ; else { memset(vis, 0, sizeof(vis)); for (int i = 0; i < n; i++) { if (check(ar[i].first, ar[i].second, ar[0].first, ar[0].second, x1, y1)) vis[i] = 1; else if (check(ar[i].first, ar[i].second, ar[1].first, ar[1].second, x2, y2)) vis[i] = 1; } flag = 0; for (int i = 0; i < n; i++) { if (!vis[i]) { flag = 1; } } if (!flag) { cout << YES n ; } else { memset(vis, 0, sizeof(vis)); for (int i = 0; i < n; i++) { if (check(ar[i].first, ar[i].second, ar[0].first, ar[0].second, x2, y2)) vis[i] = 1; else if (check(ar[i].first, ar[i].second, ar[1].first, ar[1].second, x1, y1)) vis[i] = 1; } flag = 0; for (int i = 0; i < n; i++) { if (!vis[i]) { flag = 1; } } if (flag) cout << NO n ; else cout << YES n ; } } } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__XNOR2_BEHAVIORAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_BEHAVIORAL_PP_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream multiplexer
*/
module axis_mux #
(
// Number of AXI stream inputs
parameter S_COUNT = 4,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep,
input wire [S_COUNT-1:0] s_axis_tvalid,
output wire [S_COUNT-1:0] s_axis_tready,
input wire [S_COUNT-1:0] s_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Control
*/
input wire enable,
input wire [$clog2(S_COUNT)-1:0] select
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg [CL_S_COUNT-1:0] select_reg = 2'd0, select_next;
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg [ID_WIDTH-1:0] m_axis_tid_int;
reg [DEST_WIDTH-1:0] m_axis_tdest_int;
reg [USER_WIDTH-1:0] m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_axis_tdata[select_reg*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_axis_tkeep[select_reg*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_axis_tvalid[select_reg];
wire current_s_tready = s_axis_tready[select_reg];
wire current_s_tlast = s_axis_tlast[select_reg];
wire [ID_WIDTH-1:0] current_s_tid = s_axis_tid[select_reg*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_axis_tdest[select_reg*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_axis_tuser[select_reg*USER_WIDTH +: USER_WIDTH];
always @* begin
select_next = select_reg;
frame_next = frame_reg;
s_axis_tready_next = 0;
if (current_s_tvalid & current_s_tready) begin
// end of frame detection
if (current_s_tlast) begin
frame_next = 1'b0;
end
end
if (!frame_reg && enable && (s_axis_tvalid & (1 << select))) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
end
// generate ready signal on selected port
s_axis_tready_next = (m_axis_tready_int_early && frame_next) << select_next;
// pass through selected packet data
m_axis_tdata_int = current_s_tdata;
m_axis_tkeep_int = current_s_tkeep;
m_axis_tvalid_int = current_s_tvalid && current_s_tready && frame_reg;
m_axis_tlast_int = current_s_tlast;
m_axis_tid_int = current_s_tid;
m_axis_tdest_int = current_s_tdest;
m_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 1'b0;
s_axis_tready_reg <= 0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
s_axis_tready_reg <= s_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tid_reg <= m_axis_tid_int;
m_axis_tdest_reg <= m_axis_tdest_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tid_reg <= m_axis_tid_int;
temp_m_axis_tdest_reg <= m_axis_tdest_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int nb; scanf( %d , &nb); int arr[nb]; for (int i = 0; i < nb; i++) scanf( %d , arr + i); sort(arr, arr + nb); int occ[3] = {0}; for (int i = 0; i < nb; i++) { for (int j = 0; j < 3; j++) if (arr[i] == arr[j]) occ[j]++; } if ((occ[0] == 1 && occ[1] == 1) || (occ[0] == 2)) { printf( %d , occ[2]); return 0; } if (occ[0] == 1 && occ[1] >= 2) { long long res = (occ[1] * (long long)(occ[1] - 1)) / 2; printf( %lld , res); return 0; } long long res = (occ[0] * (long long)(occ[0] - 1) * (occ[0] - 2)) / 6; printf( %lld , res); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2B_BLACKBOX_V
`define SKY130_FD_SC_LP__OR2B_BLACKBOX_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or2b (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2B_BLACKBOX_V
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module uarttx(
input rst,
input clk,
input tx_start,
input [7 : 0] tx_byte,
output tx, output tx_ready);
localparam STATE_IDLE = 0;
localparam STATE_START_BYTE = 1;
localparam STATE_BYTE_1 = 2;
localparam STATE_BYTE_2 = 3;
localparam STATE_BYTE_3 = 4;
localparam STATE_BYTE_4 = 5;
localparam STATE_BYTE_5 = 6;
localparam STATE_BYTE_6 = 7;
localparam STATE_BYTE_7 = 8;
localparam STATE_BYTE_8 = 9;
localparam STATE_STOP_BYTE1 = 10;
localparam STATE_STOP_BYTE2 = 11;
localparam STATE_FINISH = 12;
localparam STATE_WIDTH = $clog2(STATE_FINISH);
parameter CLK_SPEED = 12000000; //Hz
`ifdef IVERILOG
parameter BAUD_RATE = CLK_SPEED / 4; //Divide clock by 4 for simulation
`else
parameter BAUD_RATE = 19200;
`endif
localparam BAUD_COUNT = CLK_SPEED / BAUD_RATE;
localparam BAUD_REG_SIZE = $clog2(BAUD_COUNT);
reg [BAUD_REG_SIZE-1 : 0] baud_counter;
reg [STATE_WIDTH-1 : 0] tx_state;
reg tx_val;
reg [7 : 0] value;
assign tx_ready = (tx_state != STATE_IDLE) || (tx_start) ? 0 : 1;
assign tx = (tx_state == STATE_IDLE) ? 1 : tx_val;
always @(posedge clk) begin
if (rst) begin
tx_state <= 0;
tx_val <= 0;
baud_counter <= 0;
value <= 0;
end else begin
if (baud_counter == BAUD_COUNT) begin
baud_counter <= 0;
end else if (tx_state != STATE_IDLE) begin
baud_counter <= baud_counter + 1;
end
case (tx_state)
STATE_IDLE: begin
if (tx_start) begin
tx_state <= STATE_START_BYTE;
tx_val <= 1;
value <= tx_byte;
end
end
STATE_START_BYTE: begin
if (baud_counter == 0) begin
tx_val <= 0;
tx_state <= STATE_BYTE_1;
end
end
STATE_BYTE_1: begin
if (baud_counter == 0) begin
tx_val <= value[0];
tx_state <= STATE_BYTE_2;
end
end
STATE_BYTE_2: begin
if (baud_counter == 0) begin
tx_val <= value[1];
tx_state <= STATE_BYTE_3;
end
end
STATE_BYTE_3: begin
if (baud_counter == 0) begin
tx_val <= value[2];
tx_state <= STATE_BYTE_4;
end
end
STATE_BYTE_4: begin
if (baud_counter == 0) begin
tx_val <= value[3];
tx_state <= STATE_BYTE_5;
end
end
STATE_BYTE_5: begin
if (baud_counter == 0) begin
tx_val <= value[4];
tx_state <= STATE_BYTE_6;
end
end
STATE_BYTE_6: begin
if (baud_counter == 0) begin
tx_val <= value[5];
tx_state <= STATE_BYTE_7;
end
end
STATE_BYTE_7: begin
if (baud_counter == 0) begin
tx_val <= value[6];
tx_state <= STATE_BYTE_8;
end
end
STATE_BYTE_8: begin
if (baud_counter == 0) begin
tx_val <= value[7];
tx_state <= STATE_STOP_BYTE1;
end
end
STATE_STOP_BYTE1: begin
if (baud_counter == 0) begin
tx_val <= 1;
tx_state <= STATE_STOP_BYTE2;
end
end
STATE_STOP_BYTE2: begin
if (baud_counter == 0) begin
tx_val <= 1;
tx_state <= STATE_FINISH;
end
end
STATE_FINISH : begin
tx_state <= STATE_IDLE;
end
default: begin
tx_state <= STATE_IDLE;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, i, a, counter = 0, ar[100000]; map<char, int> mp; mp[ 6 ] = 1, mp[ 7 ] = 2, mp[ 8 ] = 3, mp[ 9 ] = 4, mp[ T ] = 5; mp[ J ] = 6, mp[ Q ] = 7, mp[ K ] = 8, mp[ A ] = 9; string str1, str2; char trump; cin >> trump; cin >> str1 >> str2; if (str1[1] == trump && str1[1] != str2[1]) cout << YES << endl; else if (str1[1] == str2[1] && mp[str1[0]] > mp[str2[0]]) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> const int MAX_N = (int)5e5 + 4, MAX_M = (int)1e7 + 4; const double eps = 1e-6; const int mod = (int)1e9 + 7; using namespace std; int n; int a[MAX_N]; bool pr[MAX_M]; int lp[MAX_M], mu[MAX_M]; inline void sieve() { for (int i = 2; i < MAX_M; i++) { if (pr[i]) continue; lp[i] = i; if (1ll * i * i < MAX_M) for (int j = i * i; j < MAX_M; j += i) if (!pr[j]) pr[j] = 1, lp[j] = i; } mu[1] = 1; for (int i = 2; i < MAX_M; i++) { if (i == lp[i]) mu[i] = -1; else if (!mu[i / lp[i]] || lp[i] == lp[i / lp[i]]) mu[i] = 0; else mu[i] = (-1) * mu[i / lp[i]]; } } vector<int> add; vector<pair<int, int> > first; void rec(int v, int id, int now, vector<int> &add) { if (v == int((first).size())) { add.push_back(now); return; } rec(v + 1, id, now, add); for (int i = 1; i <= first[v].second; i++) { now *= first[v].first; rec(v + 1, id, now, add); } } inline void fact(int id, int x) { first.clear(); while (x > 1) { if (first.empty() || first.back().first != lp[x]) first.push_back(make_pair(lp[x], 1)); else first.back().second++; x /= lp[x]; } add.clear(); rec(0, id, 1, add); } int cnt[MAX_M], all; unordered_set<int> q; int ans; int two[MAX_N]; inline int calc(int id) { fact(id, a[id]); int nw = all; for (auto i : add) { nw = (nw - mu[i] * two[cnt[i] - 1]) % mod; if (nw < 0) nw += mod; } nw = two[n - 1] - 1 - nw; if (nw < 0) nw += mod; for (auto i : add) { if (i == 1) continue; nw = (nw + mu[i] * (two[cnt[i] - 1] - 1)) % mod; if (nw < 0) nw += mod; } return nw; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sieve(); for (int i = 1; i <= n; i++) { fact(i, a[i]); for (auto j : add) cnt[j]++, q.insert(j); } two[0] = 1; for (int i = 1; i <= n; i++) two[i] = 2ll * two[i - 1] % mod; for (auto i : q) { all = (all + mu[i] * (two[cnt[i]] - 1)) % mod; if (all < 0) all += mod; } for (int i = 1; i <= n; i++) ans = (ans + calc(i)) % mod; printf( %d n , ans); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module SP_block(
input [47:0] Din,
output [31:0] P_S
);
wire [31:0] S_B;
S_combined S_combined_instance(
Din,
S_B);
S_permutation S_permutation_instance(
S_B,
P_S
);
endmodule
|
#include <bits/stdc++.h> using namespace std; static long long mod = 998244353; long long pow(long long x, long long y) { x = x % mod; int res = 1; while (y > 0) { if (y & 1) { res = (res * x) % mod; } y = y >> 1; x = (x * x) % mod; } return res; } long long modInverse(long long n, long long mod) { return pow(n, mod - 2); } long long nCrmodFermat(long long n, long long r) { if (r == 0) return 1; long long fact[n + 1]; fact[0] = 1; for (long long i = 1; i <= n; i++) { fact[i] = ((fact[i - 1] % mod) * (i % mod)) % mod; } return (fact[n] * modInverse(fact[r], mod) % mod * modInverse(fact[n - r], mod) % mod) % mod; } int main() { long long n; cin >> n; vector<long long> v(2 * n); long long sum = 0; for (int i = 0; i < 2 * n; i++) { cin >> v[i]; } sort(v.begin(), v.end()); int i = 0; int j = (2 * n) - 1; while (i < n && j >= n) { sum = (sum + abs(v[i] - v[j])) % mod; i++; j--; } cout << ((sum % mod) * (nCrmodFermat((2 * n), n) % mod)) % mod << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const signed long long int INF = 1e9; int main() { int n; cin >> n; vector<signed long long int> a(n); for (int i(0); i < n; i++) { scanf( %lld , &a[i]); } int s, f; scanf( %d %d , &s, &f); vector<signed long long int> d(n + 1); d[0] = a[0]; for (int i(1); i < n; i++) { d[i] = d[i - 1] + a[i]; } signed long long int ans = 0; signed long long int tp = INF; for (int i(0); i < n; i++) { int l = (i + s - 1 + n) % n; int r = (i + f - 2 + n) % n; signed long long int tmp = 0; if (l <= r) { tmp += d[r]; if (l - 1 >= 0) tmp -= d[l - 1]; } else { tmp += d[r]; tmp += d[n - 1]; if (l - 1 >= 0) tmp -= d[l - 1]; } if (ans <= tmp) { signed long long int ti; if (i == 0) ti = 1; else ti = n - 1 - i + 2; if (ans == tmp) { tp = min(tp, ti); } else { ans = tmp; tp = ti; } } } cout << tp; return 0; }
|
#include <bits/stdc++.h> using namespace std; namespace IO { template <typename t> inline void read(t& x) { x = 0; bool f = 1; char ch; for (ch = getchar(); ch < 0 || 9 < ch; ch = getchar()) if (ch == - ) f ^= 1; for (; 0 <= ch && ch <= 9 ; ch = getchar()) x = (x << 3) + (x << 1) + (ch ^ 48); x = f ? x : -x; } } // namespace IO const int MAXN = 50 + 10; const int CHAR_RANGE = 26 + 10; int n, len[2], f[MAXN][MAXN]; bool can[2][MAXN][MAXN][CHAR_RANGE]; char str[2][MAXN], tmp[10]; vector<int> trans[CHAR_RANGE], rtrans[CHAR_RANGE * CHAR_RANGE + 100]; void calc(int _) { for (int i = (1), iend = (len[_]); i <= iend; ++i) can[_][i][i][str[_][i] - a ] = true; for (int l = (2), lend = (len[_]); l <= lend; ++l) { for (int i = (1), iend = (len[_] - l + 1); i <= iend; ++i) { int j = i + l - 1; for (int k = (i), kend = (j - 1); k <= kend; ++k) for (int ch1 = (0), ch1end = (25); ch1 <= ch1end; ++ch1) if (can[_][i][k][ch1]) for (int ch2 = (0), ch2end = (25); ch2 <= ch2end; ++ch2) { if (can[_][k + 1][j][ch2]) { for (int x : rtrans[26 * ch1 + ch2]) can[_][i][j][x] = true; } } } } } int main() { scanf( %s , str[0] + 1), scanf( %s , str[1] + 1); len[0] = strlen(str[0] + 1), len[1] = strlen(str[1] + 1); IO::read(n); for (int i = (1), iend = (n); i <= iend; ++i) { scanf( %s , tmp + 1); rtrans[26 * (tmp[4] - a ) + tmp[5] - a ].push_back(tmp[1] - a ); } memset(f, -1, sizeof f); f[0][0] = 0; calc(0), calc(1); for (int i = (1), iend = (len[0]); i <= iend; ++i) for (int j = (1), jend = (len[1]); j <= jend; ++j) { f[i][j] = 1e9; for (int i2 = (0), i2end = (i - 1); i2 <= i2end; ++i2) for (int j2 = (0), j2end = (j - 1); j2 <= j2end; ++j2) if (f[i2][j2] != -1) for (int ch1 = (0), ch1end = (25); ch1 <= ch1end; ++ch1) { if (can[0][i2 + 1][i][ch1] && can[1][j2 + 1][j][ch1]) { f[i][j] = min(f[i2][j2] + 1, f[i][j]); } } if (f[i][j] == 1e9) f[i][j] = -1; } printf( %d n , f[len[0]][len[1]]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; int t; cin >> t; while (t--) { int n; cin >> n; long long move = 0; for (int i = 1; i <= n / 2; ++i) { move += i * 1ll * i; } cout << move * 8 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e3 + 13; const int INF = 1e6 + 7; int t[MAXN][MAXN]; int tab[MAXN * MAXN]; bool odw[MAXN * MAXN]; int wyn[MAXN * MAXN]; bool prze[MAXN * MAXN]; int xx[4] = {0, 0, -1, 1}; int yy[4] = {-1, 1, 0, 0}; vector<int> v[MAXN * MAXN]; int check(int x) { int spr = 0; odw[x] = true; prze[x] = true; for (auto it : v[x]) { if (odw[it] && prze[it]) spr = 1; else if (!odw[it]) spr = max(spr, check(it)); } prze[x] = false; return spr; } int DFS(int x, int gl) { odw[x] = true; for (auto it : v[x]) { if (odw[it]) wyn[x] = max(wyn[x], wyn[it]); else wyn[x] = max(wyn[x], DFS(it, gl + 1)); } wyn[x]++; return wyn[x]; } int main() { int n, m; int mx = 0; char c; scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { scanf( ); for (int j = 1; j <= m; j++) { scanf( %c , &c); if (c == I ) t[i][j] = 1; if (c == M ) t[i][j] = 2; if (c == A ) t[i][j] = 3; tab[(i - 1) * m + j] = t[i][j]; } t[i][0] = t[i][m + 1] = 5; } for (int i = 1; i <= m; i++) t[0][i] = t[n + 1][i] = 5; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { for (int l = 0; l < 4; l++) { if (t[i + xx[l]][j + yy[l]] == (t[i][j] + 1) % 4) v[(i - 1) * m + j].push_back((i + xx[l] - 1) * m + j + yy[l]); } } } for (int i = 1; i <= n * m; i++) { if (!odw[i] && tab[i] == 0) { if (check(i) == 1) { printf( Poor Inna! ); return 0; } } } for (int i = 1; i <= n * m; i++) odw[i] = false; for (int i = 1; i <= n * m; i++) { if (!odw[i] && tab[i] == 0) mx = max(mx, DFS(i, 1) / 4); } if (mx == 0) printf( Poor Dima! ); else printf( %d , mx); return 0; }
|
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