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#include <bits/stdc++.h> using namespace std; const int mod = (int)1e9 + 7; const int N_ = (int)2e6 + 2; long long n; char a[N_], b[N_]; double res; long long T; int main() { scanf( %lld , &n); scanf( %s , a + 1); scanf( %s , b + 1); for (char cur = A ; cur <= Z ; cur++) { long long S = 0; for (int i = 1; i <= n; i++) { if (a[i] == cur) S += i; if (b[i] == cur) res += S * (n - i + 1); } S = 0; for (int i = 0; i <= n; i++) { if (a[i] == cur) res += S * (n - i + 1); if (b[i] == cur) S += i; } } for (int i = 1; i <= n; i++) T += (n - i + 1) * (n - i + 1); printf( %.9lf , res / T); return 0; }
|
// MBT 11/9/2014
// DWP 5/9/2020
//
// 1 read-port, 1 write-port ram with a onehot address scheme
//
// reads are asynchronous
//
`include "bsg_defines.v"
module bsg_mem_1r1w_one_hot #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter safe_els_lp=`BSG_MAX(els_p,1)
)
(input w_clk_i
// Currently unused
, input w_reset_i
// one or zero-hot
, input [safe_els_lp-1:0] w_v_i
, input [width_p-1:0] w_data_i
// one or zero-hot
, input [safe_els_lp-1:0] r_v_i
, output logic [width_p-1:0] r_data_o
);
logic [safe_els_lp-1:0][width_p-1:0] data_r;
wire unused0 = w_reset_i;
for (genvar i = 0; i < els_p; i++)
begin : mem_array
bsg_dff_en
#(.width_p(width_p))
mem_reg
(.clk_i(w_clk_i)
,.en_i(w_v_i[i])
,.data_i(w_data_i)
,.data_o(data_r[i])
);
end
bsg_mux_one_hot
#(.width_p(width_p)
,.els_p(safe_els_lp)
)
one_hot_sel
(.data_i(data_r)
,.sel_one_hot_i(r_v_i)
,.data_o(r_data_o)
);
//synopsys translate_off
initial
begin
if (width_p*els_p >= 64)
$display("## %L: instantiating width_p=%d, els_p=%d (%m)"
,width_p,els_p);
end
always_ff @(negedge w_clk_i)
begin
assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || $countones(w_v_i) <= 1)
else $error("Invalid write address %b to %m is not onehot (w_reset_i=%b)\n", w_v_i, w_reset_i);
assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || $countones(r_v_i) <= 1)
else $error("Invalid read address %b to %m is not onehot (w_reset_i=%b)\n", r_v_i, w_reset_i);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_one_hot)
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/14.0/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n); vector<int> b(n); string aans = string(n / 2, 1 ) + string((n + 1) / 2, 0 ); string bans = string(n / 2, 1 ) + string((n + 1) / 2, 0 ); for (int i = 0; i < n; i++) { cin >> a[i]; cin >> b[i]; } if (n % 2) { if (a[n / 2] < b[n / 2]) aans[n / 2] = 1 ; else bans[n / 2] = 1 ; } int bpoint = 0; int apoint = 0; for (int i = 0; i < n; i++) { if (a[apoint] < b[bpoint]) { aans[apoint] = 1 ; apoint++; } else { bans[bpoint] = 1 ; bpoint++; } } cout << aans << n << bans; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2005; struct Point { long long x, y; Point() {} Point(long long x, long long y) : x(x), y(y) {} bool operator<(const Point& rhs) const { if (y != rhs.y) return y < rhs.y; else return x < rhs.x; } }; Point operator-(Point a, Point b) { return Point(a.x - b.x, a.y - b.y); } Point operator*(Point v, long long mul) { return Point(v.x * mul, v.y * mul); } long long cross(Point a, Point b) { return a.x * b.y - a.y * b.x; } int n; Point p[MAXN]; inline long long C(long long x) { return x * (x - 1) / 2; } long long calc(Point o, vector<pair<Point, int> >& v) { sort(v.begin(), v.end(), [&o](const pair<Point, int>& a, const pair<Point, int>& b) -> bool { return cross(a.first - o, b.first - o) < 0; }); long long cnt[2] = {0}, ret = 0; for (auto& i : v) cnt[i.second]++; for (auto& i : v) { cnt[i.second]--; ret += C(cnt[0]) * C(cnt[1]); cnt[i.second ^ 1]++; } return ret; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lld%lld , &p[i].x, &p[i].y); long long ans = 0; for (int i = 0; i < n; i++) { vector<pair<Point, int> > v; for (int j = 0; j < n; j++) if (j != i) { if (p[i] < p[j]) v.emplace_back(p[j], 1); else v.emplace_back(p[i] * 2 - p[j], 0); } ans += calc(p[i], v); } ans /= 2; printf( %lld n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A32OI_PP_BLACKBOX_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> struct node { node() { zuo = you = he = 0; } int zuo, you, he; } a[1000002]; char s[1000002]; int sum(int l, int r) { int ans = 0, you = 0; while (r >= l) { while (r && r - l + 1 >= (r & -r)) { ans += a[r].he; if (a[r].zuo >= you) { ans += you; you = 0; } else { ans += a[r].zuo; you -= a[r].zuo; } you += a[r].you; r -= r & -r; } if (r >= l) { if (s[r] == ( ) { if (you) { ++ans; --you; } } else ++you; --r; } } return ans; } int main() { scanf( %s , s + 1); int n = strlen(s + 1), x; for (int i = 1; i <= n; ++i) { x = i; if (s[x] == ( ) { while (x <= n) { ++a[x].zuo; x += x & -x; } } else { while (x <= n) { if (a[x].zuo) { --a[x].zuo; ++a[x].he; } else ++a[x].you; x += x & -x; } } } int m, l, r; scanf( %d , &m); while (m--) { scanf( %d%d , &l, &r); printf( %d n , sum(l, r) << 1); } return 0; }
|
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Output Buffer
// /___/ /\ Filename : OBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/22/06 - CR#226003 - Added integer, real parameter type
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
`timescale 1 ps / 1 ps
`celldefine
module OBUF (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
parameter SLEW = "SLOW";
output O;
input I;
tri0 GTS = glbl.GTS;
bufif0 B1 (O, I, GTS);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on OBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/*
* In The Name Of God
* ========================================
* [] File Name : set.v
*
* [] Creation Date : 04-03-2015
*
* [] Last Modified : Tue, Mar 31, 2015 11:00:04 PM
*
* [] Created By : Parham Alvani ()
* =======================================
*/
module set (enable, word, comp,
write, rst, tag_in, data_in, valid_in,
hit, dirty_out, tag_out,
data_out, valid_out, ack);
/* set number of block in a set */
parameter N = 4;
input enable;
input rst;
input [0:1] word;
input comp;
input write;
input rst;
input [0:4] tag_in;
input [0:15] data_in;
input valid_in;
output reg hit;
output reg dirty_out;
output reg [0:4] tag_out;
output reg [0:15] data_out;
output reg valid_out;
output reg ack;
reg [0:4] tag;
reg valid = 1'b0;
reg dirty = 1'b0;
reg [0:15] word_in [0:N - 1];
reg word_en [0:N - 1];
reg word_wr [0:N - 1];
wire [0:15] word_out [0:N - 1];
wire word_ack [0:N - 1];
generate
genvar i;
for (i = 0; i < N; i = i + 1) begin
block blk_ins(word_en[i], word_wr[i], 1'b0, word_in[i], word_out[i], word_ack[i]);
end
endgenerate
always @ (enable) begin
ack = 1'b0;
if (enable) begin
/* Reset */
if (rst) begin
valid = 1'b0;
ack = 1'b1;
end
/* Compare Read */
if (comp && !write) begin
if (tag == tag_in) begin
/* HIT */
hit = 1'b1;
valid_out = valid;
dirty_out = dirty;
tag_out = tag;
word_en[word] = 1'b1;
/* waiting for block ack */
wait (word_ack[word]) begin
data_out = word_out[word];
end
ack = 1'b1;
end else begin
/* MISS */
hit = 1'b0;
valid_out = valid;
dirty_out = dirty;
ack = 1'b1;
end
end
/* Compare Write */
if (comp && write) begin
if (tag == tag_in && valid) begin
/* HIT -- Valid */
dirty = 1'b1;
dirty_out = 1'b0;
hit = 1'b1;
word_en[word] = 1'b1;
word_wr[word] = 1'b1;
word_in[word] = data_in;
/* waiting for block ack */
wait (word_ack[word]) begin
end
ack = 1'b1;
end else begin
/* MISS -- Valid */
valid_out = valid;
dirty_out = dirty;
ack = 1'b1;
end
end
/* Access Read */
if (!comp && !write) begin
dirty_out = dirty;
valid_out = valid;
tag_out = tag;
ack = 1'b1;
end
/* Access Write */
if (!comp && write) begin
tag <= tag_in;
valid <= valid_in;
dirty <= 1'b0;
word_in[word] <= data_in;
word_wr[word] <= 1'b1;
word_en[word] <= 1'b1;
/* waiting for block ack */
wait (word_ack[word]) begin
ack = 1'b1;
end
end
end else begin
word_en[word] = 1'b0;
word_wr[word] = 1'b0;
hit = 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100010], ar[100010]; int main() { int n, track = -100002, i; cin >> n; for (i = 1; i <= n; i++) { cin >> a[i]; ar[a[i]] = ar[a[i] - 1] + 1; track = max(ar[a[i]], track); } cout << n - track << endl; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ad
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ad.v,v 1.6 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_ad.v,v $
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ad
//
// No user `defines in this module
module ent_ad
//
// Generated Module inst_ad
//
(
port_ad_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ad_2;
// Generated Wires:
wire port_ad_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ad
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB4TO1_BLACKBOX_V
`define SKY130_FD_SC_HDLL__MUXB4TO1_BLACKBOX_V
/**
* muxb4to1: Buffered 4-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__muxb4to1 (
Z,
D,
S
);
output Z;
input [3:0] D;
input [3:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB4TO1_BLACKBOX_V
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_mux_2
*/
module test_wb_mux_2;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs0_dat_i = 0;
reg wbs0_ack_i = 0;
reg wbs0_err_i = 0;
reg wbs0_rty_i = 0;
reg [ADDR_WIDTH-1:0] wbs0_addr = 0;
reg [ADDR_WIDTH-1:0] wbs0_addr_msk = 0;
reg [DATA_WIDTH-1:0] wbs1_dat_i = 0;
reg wbs1_ack_i = 0;
reg wbs1_err_i = 0;
reg wbs1_rty_i = 0;
reg [ADDR_WIDTH-1:0] wbs1_addr = 0;
reg [ADDR_WIDTH-1:0] wbs1_addr_msk = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs0_adr_o;
wire [DATA_WIDTH-1:0] wbs0_dat_o;
wire wbs0_we_o;
wire [SELECT_WIDTH-1:0] wbs0_sel_o;
wire wbs0_stb_o;
wire wbs0_cyc_o;
wire [ADDR_WIDTH-1:0] wbs1_adr_o;
wire [DATA_WIDTH-1:0] wbs1_dat_o;
wire wbs1_we_o;
wire [SELECT_WIDTH-1:0] wbs1_sel_o;
wire wbs1_stb_o;
wire wbs1_cyc_o;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
wbm_adr_i,
wbm_dat_i,
wbm_we_i,
wbm_sel_i,
wbm_stb_i,
wbm_cyc_i,
wbs0_dat_i,
wbs0_ack_i,
wbs0_err_i,
wbs0_rty_i,
wbs0_addr,
wbs0_addr_msk,
wbs1_dat_i,
wbs1_ack_i,
wbs1_err_i,
wbs1_rty_i,
wbs1_addr,
wbs1_addr_msk);
$to_myhdl(wbm_dat_o,
wbm_ack_o,
wbm_err_o,
wbm_rty_o,
wbs0_adr_o,
wbs0_dat_o,
wbs0_we_o,
wbs0_sel_o,
wbs0_stb_o,
wbs0_cyc_o,
wbs1_adr_o,
wbs1_dat_o,
wbs1_we_o,
wbs1_sel_o,
wbs1_stb_o,
wbs1_cyc_o);
// dump file
$dumpfile("test_wb_mux_2.lxt");
$dumpvars(0, test_wb_mux_2);
end
wb_mux_2 #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs0_adr_o(wbs0_adr_o),
.wbs0_dat_i(wbs0_dat_i),
.wbs0_dat_o(wbs0_dat_o),
.wbs0_we_o(wbs0_we_o),
.wbs0_sel_o(wbs0_sel_o),
.wbs0_stb_o(wbs0_stb_o),
.wbs0_ack_i(wbs0_ack_i),
.wbs0_err_i(wbs0_err_i),
.wbs0_rty_i(wbs0_rty_i),
.wbs0_cyc_o(wbs0_cyc_o),
.wbs0_addr(wbs0_addr),
.wbs0_addr_msk(wbs0_addr_msk),
.wbs1_adr_o(wbs1_adr_o),
.wbs1_dat_i(wbs1_dat_i),
.wbs1_dat_o(wbs1_dat_o),
.wbs1_we_o(wbs1_we_o),
.wbs1_sel_o(wbs1_sel_o),
.wbs1_stb_o(wbs1_stb_o),
.wbs1_ack_i(wbs1_ack_i),
.wbs1_err_i(wbs1_err_i),
.wbs1_rty_i(wbs1_rty_i),
.wbs1_cyc_o(wbs1_cyc_o),
.wbs1_addr(wbs1_addr),
.wbs1_addr_msk(wbs1_addr_msk)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_BEHAVIORAL_V
`define SKY130_FD_SC_LP__ISO0N_BEHAVIORAL_V
/**
* iso0n: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__iso0n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Module supplies
supply1 VPWR ;
supply0 KAGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
and and0 (X , A, SLEEP_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; char a[100100]; char b[100100]; int na, nb; int main() { cin >> a >> b; na = 0; nb = 0; for (int i = 0; a[i]; i++) if (a[i] == 1 ) na++; for (int i = 0; b[i]; i++) if (b[i] == 1 ) nb++; if (na % 2) na++; if (na >= nb) { cout << YES << endl; } else { cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 3e5 + 10; const long long MAXE = 3e5 + 10; const long long INF = 2e18 + 3; long long n, m, k, ec; long long from[2 * MAXE], to[2 * MAXE], prv[2 * MAXE], w[2 * MAXE], head[MAXN], sec[2 * MAXE]; long long comp[MAXN], d[MAXN], ss[MAXN]; bool portal[MAXN], mark[MAXN]; set<pair<long long, long long>> st; long long ans = 0; void add_edge(long long u, long long v, long long c) { from[ec] = u, to[ec] = v, w[ec] = c, prv[ec] = head[u]; head[u] = ec++; } long long get_min() { pair<long long, long long> fr = *st.begin(); st.erase(st.begin()); return fr.second; } void update(long long v) { mark[v] = 1; for (long long e = head[v]; e != -1; e = prv[e]) { long long u = to[e], c = w[e]; if (!mark[u] && d[u] > w[e] + d[v]) { st.erase({d[u], u}); d[u] = d[v] + w[e]; st.insert({d[u], u}); ss[u] = ss[v]; } } } void dijk() { fill(d, d + MAXN, INF); memset(ss, -1, sizeof(ss)); for (long long i = 0; i < n; i++) if (portal[i]) mark[i] = 1, d[i] = 0, ss[i] = i; for (long long i = 0; i < n; i++) if (portal[i]) update(i); while (st.size()) update(get_min()); } bool cmp(long long e1, long long e2) { if (w[e1] != w[e2]) return w[e1] < w[e2]; return e1 < e2; } long long get_comp(long long v) { if (comp[v] == v) return v; return comp[v] = get_comp(comp[v]); } void merge(long long e) { if (get_comp(ss[to[e]]) == get_comp(ss[from[e]])) return; ans += w[e]; comp[get_comp(ss[to[e]])] = get_comp(ss[from[e]]); } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m; memset(head, -1, sizeof(head)); while (m--) { long long a, b, c; cin >> a >> b >> c; a--, b--; add_edge(a, b, c); add_edge(b, a, c); } cin >> k; while (k--) { long long temp; cin >> temp, temp--, portal[temp] = 1; } dijk(); ans = d[0]; iota(comp, comp + n, 0); iota(sec, sec + ec, 0); for (int i = 0; i < ec; i++) w[i] += d[from[i]] + d[to[i]]; sort(sec, sec + ec, cmp); for (long long e = 0; e < ec; e++) merge(sec[e]); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; set<int> se; struct zzz { int v, id; } zz[1000005]; bool cmp(const zzz &i, const zzz &j) { return i.v > j.v; } int N, M, K; char S[1000005], T[1000005], s[1000005]; int z[1000005], p[2][1000005]; void w(int td) { for (int i = 0; i < M; i++) s[i] = T[i]; s[M] = ; for (int i = 0; i < N; i++) s[M + 1 + i] = S[i]; int L = 0, R = 0, n = N + M + 1; for (int i = 1; i < n; i++) { if (i > R) { L = R = i; while (R < n && s[R - L] == s[R]) R++; z[i] = R - L; R--; } else { int k = i - L; if (z[k] < R - i + 1) z[i] = z[k]; else { L = i; while (R < n && s[R - L] == s[R]) R++; z[i] = R - L; R--; } } } for (int i = 0; i < N; i++) zz[i].v = z[M + 1 + i], zz[i].id = i; sort(zz, zz + N, cmp); int i = -1; se.clear(); for (int x = M; x >= 0; x--) { while (i + 1 < N && zz[i + 1].v >= x) { i++; se.insert(zz[i].id); } if (se.lower_bound(K - x) == se.end()) p[td][x] = 1000000000; else p[td][x] = *se.lower_bound(K - x); } } int main() { scanf( %d%d%d , &N, &M, &K); scanf( %s%s , S, T); w(0); for (int i = 1; i <= N; i++) if (z[M + i] == M) { puts( Yes ); if (i + K + K - 1 <= N) printf( %d %d , i, i + K); else printf( %d %d , N - K - K + 1, N - K + 1); return 0; } reverse(S, S + N); reverse(T, T + M); w(1); for (int i = 1; i < M; i++) if (i <= K && M - i <= K && p[0][i] + i <= N - p[1][M - i] - (M - i)) { puts( Yes ); printf( %d %d , p[0][i] + i - K + 1, N - p[1][M - i] - (M - i) + 1); return 0; } puts( No ); }
|
#include <bits/stdc++.h> using namespace std; int treeNo[111111]; vector<vector<int> > BIT; vector<pair<int, int> > E[111111]; int in[111111]; int base[111111]; int P[111111], depth[111111]; void update(int x, int val, int id) { for (; x < BIT[id].size(); x += (x & -x)) BIT[id][x] += val; } int read(int x, int id) { int sum = 0; for (; x; x -= (x & -x)) sum += BIT[id][x]; return sum; } void dfs(int first, int par, int d, int id) { P[first] = par; depth[first] = d; BIT[id].push_back(0); treeNo[first] = id; for (int i = 0; i < E[first].size(); i++) { int u = E[first][i].first; if (u == par) continue; dfs(u, first, d + 1, id); base[E[first][i].second] = u; } } int main() { int N; cin >> N; int u, first; for (int i = 1; i < N; i++) { cin >> u >> first; E[u].push_back({first, i}); E[first].push_back({u, i}); in[u]++; in[first]++; } int root = 0; for (int i = 1; i <= N; i++) if (in[i] > 2) root = i; if (root == 0) for (int i = 1; i <= N; i++) if (in[i] == 1) root = i; BIT.resize(E[root].size()); for (int i = 0; i < E[root].size(); i++) { BIT[i].push_back(0); dfs(E[root][i].first, root, 1, i); base[E[root][i].second] = E[root][i].first; } int Q, t; cin >> Q; while (Q--) { scanf( %d %d , &t, &first); if (t == 3) { scanf( %d , &u); if (u == root or first == root) { if (u == root) swap(u, first); int sum = read(depth[u], treeNo[u]); if (sum == 0) printf( %d n , depth[u]); else printf( -1 n ); } else if (treeNo[u] == treeNo[first]) { if (depth[u] == depth[first]) printf( 0 n ); else { if (depth[first] < depth[u]) swap(u, first); int sum = read(depth[first], treeNo[first]) - read(depth[u], treeNo[first]); if (sum == 0) printf( %d n , depth[first] - depth[u]); else printf( -1 n ); } } else { int sum = read(depth[u], treeNo[u]) + read(depth[first], treeNo[first]); if (sum == 0) printf( %d n , depth[first] + depth[u]); else printf( -1 n ); } } else if (t == 2) { int b = base[first]; update(depth[b], 1, treeNo[b]); } else if (t == 1) { int b = base[first]; update(depth[b], -1, treeNo[b]); } } }
|
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-9; const int inf = (1 << 30) - 1; const long long inf64 = ((long long)1 << 62) - 1; const long double pi = 3.1415926535897932384626433832795; template <class T> T sqr(T x) { return x * x; } template <class T> T abs(T x) { return x < 0 ? -x : x; } const int nmax = 15000; int n, k; int a[nmax], pos[nmax]; int main() { cin >> n >> k; for (int i = 0; i < (int)(n); i++) { a[i] = 1; pos[i] = i + 1; } a[n - 1] = 0; pos[n - 1] = n - 1; for (int i = 0; i < (int)(k); i++) { for (int j = 0; j < (int)(n); j++) { while (a[j] + a[pos[j]] > n - j - 1) pos[j]++; printf( %d , pos[j] + 1); a[j] += a[pos[j]]; } puts( ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int size = 400007; const long long modulo = 1000000007; const int INF = 2e9; const double EPS = 1e-8; const double PI = acos(-1.0); int d[2][size]; char board[2][size]; int compo[size]; int l[size], r[size]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; cin.ignore(); gets(board[0]); gets(board[1]); for (int i = 0; i < 2; i++) for (int j = 0; j < size; j++) d[i][j] = 2e9; int j = 0, com = -1; vector<bool> start(n, false); while (j < n) { while (j < n && board[0][j] == X && board[1][j] == X ) ++j; if (j < n) { start[j] = true; ++com; compo[j] = com; } d[0][j] = (board[0][j] == X ? 2e9 : 0); d[0][j + n] = (board[1][j] == X ? 2e9 : 1); d[1][j] = (board[0][j] == X ? 2e9 : 1); d[1][j + n] = (board[1][j] == X ? 2e9 : 0); int col = j + 1; while (col < n) { bool ok = false; for (int st = 0; st < 2; st++) for (int cell = col; cell < 2 * n; cell += n) if (board[cell / n][col] != X && d[st][cell] > d[st][cell - 1] + 1) { ok = true; d[st][cell] = d[st][cell - 1] + 1; } for (int st = 0; st < 2; st++) for (int cell = col; cell < 2 * n; cell += n) if (board[cell / n][col] != X && d[st][cell] > d[st][(cell + n) % (2 * n)] + 1) { d[st][cell] = d[st][(cell + n) % (2 * n)] + 1; } if (ok) { compo[col] = com; ++col; } else { break; } } j = col; } if (board[0][0] == . && board[1][0] == . ) l[0] = -1; else l[0] = 0; for (int i = 1; i < n; i++) { if (board[0][i] == . && board[1][i] == . ) l[i] = l[i - 1]; else l[i] = i; } if (board[0][n - 1] == . && board[1][n - 1] == . ) r[n - 1] = n; else r[n - 1] = n - 1; for (int i = n - 2; i >= 0; i--) { if (board[0][i] == . && board[1][i] == . ) r[i] = r[i + 1]; else r[i] = i; } while (m--) { int a, b; cin >> a >> b; if (a > b) swap(a, b); if (a + n == b) cout << 1 << endl; else { --a; --b; int a_row = a / n, a_col = a % n, b_row = b / n, b_col = b % n; if (a_col > b_col) { swap(a_row, b_row); swap(a_col, b_col); swap(a, b); } if (compo[a_col] != compo[b_col]) { cout << -1 << endl; continue; } int ans = min(d[0][b], d[1][b]); if (l[a_col] == a_col) ans -= min(d[0][a], d[1][a]); else if (start[a_col]) ans = d[a_row][b]; else { if (r[a_col] > b_col) ans = b_col - a_col + (a_row != b_row); else { int right_exit = (board[0][r[a_col]] == . ? 0 : 1); ans = min(d[0][b] - d[0][a], d[1][b] - d[1][a]); int pref = (d[0][b] - d[0][a] < d[1][b] - d[1][a] ? 0 : 1); int lind = l[a_col]; int left_exit = -1; if (lind < 0 || start[lind + 1]) left_exit = pref; else if (board[0][lind] == . ) left_exit = 0; else left_exit = 1; if (right_exit != a_row && left_exit != a_row) ans += 2; } } cout << ans << n ; } } return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_r_efa.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//****************************************************************
//
// Module: bw_r_efa
//
// Description: RTL model for EFA (EFuse Array)
//
//****************************************************************
`include "sys.h"
module bw_r_efa (
vpp,
pi_efa_prog_en,
sbc_efa_read_en,
sbc_efa_word_addr,
sbc_efa_bit_addr,
sbc_efa_margin0_rd,
sbc_efa_margin1_rd,
efa_sbc_data,
pwr_ok,
por_n,
sbc_efa_sup_det_rd,
sbc_efa_power_down,
so,
si,
se,
vddo,
clk
);
input vpp; // VPP input from I/O
output [31:0] efa_sbc_data; // Data from e-fuse array to SBC
input pi_efa_prog_en; // e-fuse array program enable
input sbc_efa_read_en; // e-fuse array read enable
input [5:0] sbc_efa_word_addr; // e-fuse array word addr
input [4:0] sbc_efa_bit_addr; // e-fuse array bit addr
input sbc_efa_margin0_rd; // e-fuse array margin0 read
input sbc_efa_margin1_rd; // e-fuse array margin1 read
input pwr_ok; // power_ok reset
input por_n; // por_n reset
input sbc_efa_sup_det_rd; // e-fuse array supply detect read
input sbc_efa_power_down; // e-fuse power down signal from SBC
output so; // Scan ports
input si;
input se;
input vddo;
input clk; // cpu clk
/*--------------------------------------------------------------------------*/
//** Parameters and define **//
parameter MAXFILENAME=200;
//parameter EFA_READ_LAT = 5670 ; // 7 system cycles (150Mhz) - 1/4(sys clk); about 45ns
// 840 ticks = 1 system cycle
parameter EFA_READ_LAT = 45000 ; // about 45ns (timescale is 1 ps)
/* The access time has been specified to be 45ns for a worst case read */
//** Wire and Reg declarations **//
reg [MAXFILENAME*8-1:0] efuse_data_filename;
reg [31:0] efuse_array[0:63],efuse_row,efa_read_data; //EFUSE ARRAY
integer file_get_status,i;
reg [31:0] fpInVec;
wire [31:0] efa_sbc_data;
wire l1clk;
wire lvl_det_l; // level detect ok
wire vddc_ok_l; // vddc ok
wire vddo_ok_l; // vddo ok
wire vpp_ok_l; // vpp ok
reg efuse_rd_progress;
reg efuse_enable_write_check;
/*--------------------------------------------------------------------------*/
// Process data file
// synopsys translate_off
initial
begin
efuse_enable_write_check = 1;
// Get Efuse data file from plusarg.
if ($value$plusargs("efuse_data_file=%s", efuse_data_filename))
begin
// Read Efuse data file if present
$display("INFO: efuse data file is being read--filename=%0s",
efuse_data_filename);
$readmemh(efuse_data_filename, efuse_array);
$display("INFO: completed reading efuse data file");
end
else
begin
//if file not present, initialize efuse_array with default value
$display("INFO: Using default efuse data for the efuse array");
for (i=0;i<=63;i=i+1) begin
efuse_array[i] = 32'b0;
end
end
end
// Process power down signal
assign l1clk = clk & ~sbc_efa_power_down;
// Scan logic not in RTL
assign so = se ? si : 1'bx;
//assign supply detect signals to valid values (circuit cannot be impl in model)
assign vddc_ok_l = 1'b0;
assign vddo_ok_l = 1'b0;
assign vpp_ok_l = 1'b0;
assign lvl_det_l = 1'b0;
always @(posedge l1clk) begin
// Write operation , one bit at a time
if ((pi_efa_prog_en === 1'b1) && (pwr_ok === 1'b1) && (por_n === 1'b1)) begin
efuse_row = efuse_array[sbc_efa_word_addr];
efuse_row[sbc_efa_bit_addr] = 1'b1;
efuse_array[sbc_efa_word_addr] <= efuse_row;
end
end
// efa_read_data is from the VPP_CORE which is reset to 0 in ckt when read is de-asserted
// However in RTL it is reset to X because I want to simulate the wait time where
// efa_read_data is indeed X till the latency period
// margin reads are not modelled in the RTL
always @(posedge l1clk) begin
// Read operation , 32 bits at a time
if ((sbc_efa_read_en) & ~efuse_rd_progress) begin
// About 45ns
efa_read_data[31:0] <= #EFA_READ_LAT efuse_array[sbc_efa_word_addr];
efuse_rd_progress = 1'b1;
end
if (~(sbc_efa_read_en)) begin
efuse_rd_progress = 1'b0;
end
if (~efuse_rd_progress) begin
efa_read_data[31:0] <= 32'bx;
end
end
// synopsys translate_on
// In ckt, when sbc_efa_read_en is low, output remains the same.
assign efa_sbc_data[31:0] = por_n ? ((pwr_ok & sbc_efa_read_en) ? (sbc_efa_sup_det_rd ?
{28'bx,~lvl_det_l,~vddc_ok_l,~vddo_ok_l,~vpp_ok_l}
: efa_read_data[31:0] ) : efa_sbc_data[31:0]) : 32'b0;
endmodule
|
`define ADDER_WIDTH 005
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
// $Id: whr_la_routing_logic.v 1922 2010-04-15 03:47:49Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// lookahead routing logic for wormhole router
module whr_la_routing_logic
(clk, reset, router_address, route_op, route_info, la_route_info);
`include "c_functions.v"
`include "c_constants.v"
// number of routers in each dimension
parameter num_routers_per_dim = 4;
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// number of dimensions in network
parameter num_dimensions = 2;
// width required to select individual router in network
localparam router_addr_width = num_dimensions * dim_addr_width;
// number of nodes per router (a.k.a. consentration factor)
parameter num_nodes_per_router = 1;
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// width of global addresses
localparam addr_width = router_addr_width + node_addr_width;
// connectivity within each dimension
parameter connectivity = `CONNECTIVITY_LINE;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// width required for lookahead routing information
localparam la_route_info_width = port_idx_width;
// select routing function type
parameter routing_type = `ROUTING_TYPE_DOR;
// select order of dimension traversal
parameter dim_order = `DIM_ORDER_ASCENDING;
// total number of bits required for storing routing information
localparam route_info_width = addr_width;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// current router's address
input [0:router_addr_width-1] router_address;
// port on which the packet will leave the current router
input [0:num_ports-1] route_op;
// routing data
input [0:route_info_width-1] route_info;
// lookahead routing information for next router
output [0:la_route_info_width-1] la_route_info;
wire [0:la_route_info_width-1] la_route_info;
// address of destination router
wire [0:router_addr_width-1] dest_router_address;
assign dest_router_address = route_info[0:router_addr_width-1];
// address of the downstream router
wire [0:router_addr_width-1] next_router_address;
wire [0:num_dimensions-1] dim_addr_match;
wire [0:num_ports-1] next_route_op;
generate
case(routing_type)
`ROUTING_TYPE_DOR:
begin
genvar dim;
for(dim = 0; dim < num_dimensions; dim = dim + 1)
begin:dims
wire [0:dim_addr_width-1] dest_dim_addr;
assign dest_dim_addr
= dest_router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1];
wire [0:dim_addr_width-1] curr_dim_addr;
assign curr_dim_addr
= router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1];
wire [0:dim_addr_width-1] next_dim_addr;
assign dim_addr_match[dim] = (next_dim_addr == dest_dim_addr);
wire dim_sel;
case(dim_order)
`DIM_ORDER_ASCENDING:
begin
if(dim == 0)
assign dim_sel = ~dim_addr_match[dim];
else
assign dim_sel = &dim_addr_match[0:dim-1] &
~dim_addr_match[dim];
end
`DIM_ORDER_DESCENDING:
begin
if(dim == (num_dimensions - 1))
assign dim_sel = ~dim_addr_match[dim];
else
assign dim_sel = ~dim_addr_match[dim] &
dim_addr_match[(dim+1):
(num_dimensions-1)];
end
endcase
wire [0:num_neighbors_per_dim-1] port_dec;
assign next_router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1]
= next_dim_addr;
case(connectivity)
`CONNECTIVITY_LINE, `CONNECTIVITY_RING:
begin
wire route_down;
assign route_down
= route_op[dim*num_neighbors_per_dim];
wire route_up;
assign route_up
= route_op[dim*num_neighbors_per_dim+1];
// Assemble a delta value for the address segment
// corresponding to the current dimension; the delta
// can have the values -1 (i.e., all ones in two's
// complement), 0 or 1
wire [0:dim_addr_width-1] addr_delta;
if(dim_addr_width > 1)
assign addr_delta[0:dim_addr_width-2]
= {(dim_addr_width-1){route_down}};
assign addr_delta[dim_addr_width-1]
= route_down | route_up;
assign next_dim_addr = curr_dim_addr + addr_delta;
case(connectivity)
`CONNECTIVITY_LINE:
begin
assign port_dec
= {dest_dim_addr < next_dim_addr,
dest_dim_addr > next_dim_addr};
end
`CONNECTIVITY_RING:
begin
// FIXME: add implementation here!
// synopsys translate_off
initial
begin
$display({"ERROR: The lookahead routing ",
"logic module %m does not yet ",
"support ring connectivity ",
"within each dimension."});
$stop;
end
// synopsys translate_on
end
endcase
end
`CONNECTIVITY_FULL:
begin
wire route_dest;
assign route_dest
= |route_op[dim*num_neighbors_per_dim:
(dim+1)*num_neighbors_per_dim-1];
assign next_dim_addr
= route_dest ? dest_dim_addr : curr_dim_addr;
wire [0:num_routers_per_dim-1] dest_dim_addr_dec;
c_decoder
#(.num_ports(num_routers_per_dim))
dest_dim_addr_dec_dec
(.data_in(dest_dim_addr),
.data_out(dest_dim_addr_dec));
wire [0:(2*num_routers_per_dim-1)-1]
dest_dim_addr_dec_repl;
assign dest_dim_addr_dec_repl
= {dest_dim_addr_dec,
dest_dim_addr_dec[0:(num_routers_per_dim-1)-1]};
assign port_dec
= dest_dim_addr_dec_repl[(next_dim_addr+1) +:
num_neighbors_per_dim];
end
endcase
assign next_route_op[dim*num_neighbors_per_dim:
(dim+1)*num_neighbors_per_dim-1]
= port_dec & {num_neighbors_per_dim{dim_sel}};
end
end
endcase
wire eject;
assign eject = &dim_addr_match;
if(num_nodes_per_router > 1)
begin
wire [0:node_addr_width-1] dest_node_address;
assign dest_node_address
= route_info[route_info_width-node_addr_width:route_info_width-1];
wire [0:num_nodes_per_router-1] node_sel;
c_decoder
#(.num_ports(num_nodes_per_router))
node_sel_dec
(.data_in(dest_node_address),
.data_out(node_sel));
assign next_route_op[num_ports-num_nodes_per_router:num_ports-1]
= node_sel & {num_nodes_per_router{eject}};
end
else
assign next_route_op[num_ports-1] = eject;
endgenerate
wire [0:port_idx_width-1] next_route_port;
c_encoder
#(.num_ports(num_ports))
next_route_port_enc
(.data_in(next_route_op),
.data_out(next_route_port));
assign la_route_info[0:port_idx_width-1] = next_route_port;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_pipe_misc_v6.v
// Version : 2.4
//--
//-- Description: Misc PIPE module for Virtex6 PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_pipe_misc_v6 #
(
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
input wire pipe_tx_rcvr_det_i ,
input wire pipe_tx_reset_i ,
input wire pipe_tx_rate_i ,
input wire pipe_tx_deemph_i ,
input wire [2:0] pipe_tx_margin_i ,
input wire pipe_tx_swing_i ,
output wire pipe_tx_rcvr_det_o ,
output wire pipe_tx_reset_o ,
output wire pipe_tx_rate_o ,
output wire pipe_tx_deemph_o ,
output wire [2:0] pipe_tx_margin_o ,
output wire pipe_tx_swing_o ,
input wire pipe_clk ,
input wire rst_n
);
//******************************************************************//
// Reality check. //
//******************************************************************//
localparam TCQ = 1; // clock to out delay model
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
end else if (PIPE_PIPELINE_STAGES == 1) begin
always @(posedge pipe_clk) begin
if (rst_n) begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
end else begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
end else if (PIPE_PIPELINE_STAGES == 2) begin
always @(posedge pipe_clk) begin
if (rst_n) begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
pipe_tx_rcvr_det_qq <= #TCQ 0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 0;
pipe_tx_swing_qq <= #TCQ 0;
end else begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; char a[105][3]; int main() { scanf( %s%d , a[0], &n); for (int i = 1; i <= n; ++i) { scanf( %s , a[i]); if (a[i][0] == a[0][0] && a[i][1] == a[0][1]) { printf( YES n ); return 0; } } for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) if ((a[i][1] == a[0][0] && a[j][0] == a[0][1])) { printf( YES n ); return 0; } printf( NO n ); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; long long n, x, y, nr; long long cx, cy; int ans[2000002]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> x >> y; int xx = 0; while (xx <= x + y) { long long pa = (cx + 1) * y; long long pb = (cy + 1) * x; if (pa == pb) ++cx, ++cy, xx += 2; else if (pa < pb) ans[xx] = 1, ++cx, ++xx; else ans[xx] = 2, ++cy, ++xx; } for (int i = 1; i <= n; ++i) { cin >> nr; --nr; nr %= (x + y); if (ans[nr] == 1) cout << Vanya << n ; if (ans[nr] == 2) cout << Vova << n ; if (ans[nr] == 0) cout << Both << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND_PP_SYMBOL_V
`define SKY130_FD_SC_LS__TAPVGND_PP_SYMBOL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 3; int n, m, dp[N], vis[2][N]; vector<int> adj[2][N]; vector<pair<int, int>> e; void dfs(int u, int dir) { vis[dir][u] = 1; for (int v : adj[dir][u]) if (!vis[dir][v]) dfs(v, dir); } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m; for (int i = 0, u, v; i < m; i++) { cin >> u >> v; adj[0][u].push_back(v); adj[1][v].push_back(u); e.push_back({u, v}); } dfs(1, 0), dfs(n, 1); for (int i = 0; i < n - 1; i++) for (auto [u, v] : e) if (vis[0][u] & vis[1][v]) { dp[u] = min(dp[u], dp[v] + 2); dp[v] = min(dp[v], dp[u] - 1); } for (auto [u, v] : e) if (vis[0][u] & vis[1][v] & (dp[u] > dp[v] + 2 || dp[v] > dp[u] - 1)) return cout << No << endl, 0; cout << Yes << endl; for (auto [u, v] : e) cout << (vis[0][u] & vis[1][v] ? dp[u] - dp[v] : 1) << endl; }
|
#include <bits/stdc++.h> using namespace std; const int n = 100002; char h[n], h1[n]; int a[n]; bool check(int e, int r, int v1, int c1) { int c, v, c2, v2; while (e < r) { for (c = 0; c < 10; c++) for (v = 0; v < 10; v++) if (c + v == v1 + h[r]) { if ((c == 0) && (e == 0)) continue; goto st; } if ((h[r] == 9) && (v1 == 10)) { c = 9; v = 0; goto st; } return 0; st: h[r - 1] -= (c + v) / 10; if (h[r - 1] < 0) { for (c2 = r - 2; (c2 >= 0) && (h[c2 + 1] < 0); c2--) { h[c2 + 1] += 10; h[c2]--; } if (c2 < e - 1) return 0; } a[e] = c; a[r] = v; c += v; v = v1 + h[e] - c; if ((v != 0) && (v != 1)) return 0; v1 = v * 10; c1 = c / 10; if (e == r - 1) { if (v == 1) return 0; return 1; } e++; r--; } if (e > r) { if ((v1 + c1 == 11) || (v1 + c1 == 0)) return 1; return 0; } for (c = 0; c < 10; c++) if (c + c == v1 + h[e]) break; if (c == 10) return 0; a[e] = c; return 1; } int main() { int q, w, e, r, t; scanf( %s , h1); q = strlen(h1); for (w = 0; w < q; w++) h1[w] -= 48; for (w = 0; w < q; w++) h[w] = h1[w]; if (check(0, q - 1, 0, 0)) { for (w = 0; w < q; w++) printf( %d , a[w]); return 0; } for (w = 0; w < q; w++) h[w] = h1[w]; if ((h[0] == 1) && (check(1, q - 1, 10, 0))) { for (w = 1; w < q; w++) printf( %d , a[w]); return 0; } printf( 0 ); return 0; }
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module tx_fct_counter(
input pclk_tx,
input send_null_tx,
input enable_tx,
input gotfct_tx,
input char_sent,
output reg [5:0] fct_counter_p
);
reg [2:0] state_fct_receive/* synthesis dont_replicate */;
reg [2:0] next_state_fct_receive/* synthesis dont_replicate */;
reg [2:0] state_fct_p/* synthesis dont_replicate */;
reg [2:0] next_state_fct_p/* synthesis dont_replicate */;
reg [5:0] fct_counter_receive;
reg clear_reg;
reg internal_reset;
reg get_got_fct;
always@(posedge gotfct_tx or negedge internal_reset)
begin
if(!internal_reset)
begin
get_got_fct <= 1'b0;
end
else if(send_null_tx)
begin
get_got_fct <= 1'b1;
end
end
always@(*)
begin
next_state_fct_receive = state_fct_receive;
case(state_fct_receive)
3'd0:
begin
if(get_got_fct)
begin
next_state_fct_receive = 3'd1;
end
else if(clear_reg)
begin
next_state_fct_receive = 3'd3;
end
else
next_state_fct_receive = 3'd0;
end
3'd1:
begin
next_state_fct_receive = 3'd2;
end
3'd2:
begin
if(get_got_fct)
begin
next_state_fct_receive = 3'd2;
end
else
begin
next_state_fct_receive = 3'd0;
end
end
3'd3:
begin
next_state_fct_receive = 3'd4;
end
3'd4:
begin
if(clear_reg)
begin
next_state_fct_receive = 3'd4;
end
else
begin
next_state_fct_receive = 3'd0;
end
end
default:
begin
next_state_fct_receive = 3'd0;
end
endcase
end
always@(posedge pclk_tx or negedge enable_tx)
begin
if(!enable_tx)
begin
fct_counter_receive<= 6'd0;
state_fct_receive <= 3'd0;
internal_reset <= 1'b0;
end
else if(send_null_tx)
begin
state_fct_receive <= next_state_fct_receive;
case(state_fct_receive)
3'd0:
begin
fct_counter_receive <= fct_counter_receive;
internal_reset <= 1'b1;
end
3'd1:
begin
fct_counter_receive <= fct_counter_receive + 6'd8;
internal_reset <= 1'b0;
end
3'd2:
begin
fct_counter_receive <= fct_counter_receive;
internal_reset <= 1'b0;
end
3'd3:
begin
fct_counter_receive <= fct_counter_receive;
internal_reset <= 1'b0;
end
3'd4:
begin
internal_reset <= 1'b1;
fct_counter_receive <= 6'd0;
end
default:
begin
fct_counter_receive <= fct_counter_receive;
end
endcase
end
end
always@(*)
begin
next_state_fct_p = state_fct_p;
case(state_fct_p)
3'd0:
begin
if(fct_counter_receive == 6'd56)
begin
next_state_fct_p = 3'd1;
end
else
next_state_fct_p = 3'd0;
end
3'd1:
begin
next_state_fct_p = 3'd2;
end
3'd2:
begin
if(fct_counter_receive == 6'd0)
next_state_fct_p = 3'd3;
else
next_state_fct_p = 3'd2;
end
3'd3:
begin
if(char_sent)
next_state_fct_p = 3'd4;
else
next_state_fct_p = 3'd3;
end
3'd4:
begin
if(!char_sent)
next_state_fct_p = 3'd5;
else
next_state_fct_p = 3'd4;
end
3'd5:
begin
if(fct_counter_p == 6'd0)
next_state_fct_p = 3'd0;
else if(fct_counter_p > 6'd0)
next_state_fct_p = 3'd3;
else
next_state_fct_p = 3'd5;
end
default:
begin
next_state_fct_p = 3'd0;
end
endcase
end
always@(posedge pclk_tx or negedge enable_tx)
begin
if(!enable_tx)
begin
fct_counter_p<= 6'd0;
state_fct_p <= 3'd0;
clear_reg <= 1'b0;
end
else if(send_null_tx)
begin
state_fct_p <= next_state_fct_p;
case(state_fct_p)
3'd0:
begin
clear_reg <= 1'b0;
fct_counter_p <= fct_counter_p;
end
3'd1:
begin
fct_counter_p <= fct_counter_receive;
clear_reg <= 1'b0;
end
3'd2:
begin
if(fct_counter_receive == 6'd0)
clear_reg <= 1'b0;
else
clear_reg <= 1'b1;
fct_counter_p <= fct_counter_p;
end
3'd3:
begin
clear_reg <= 1'b0;
if(char_sent)
begin
if(fct_counter_p == 6'd0)
fct_counter_p <= fct_counter_p;
else
fct_counter_p <= fct_counter_p - 6'd1;
end
else
fct_counter_p <= fct_counter_p;
end
3'd4:
begin
clear_reg <= 1'b0;
fct_counter_p <= fct_counter_p;
end
3'd5:
begin
clear_reg <= 1'b0;
fct_counter_p <= fct_counter_p;
end
default:
begin
fct_counter_p <= fct_counter_p;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, k; cin >> n >> k; vector<int> table(n), d = {119, 18, 93, 91, 58, 107, 111, 82, 127, 123}; for (int i = 0; i < n; ++i) { string tmp; cin >> tmp; reverse(tmp.begin(), tmp.end()); for (int j = 0; j < 7; ++j) { if (tmp[j] == 1 ) { table[i] += (1 << j); } } } vector<vector<int>> dp(n + 1, vector<int>(k + 1, -1)); vector<vector<int>> par(n + 1, vector<int>(k + 1, -1)); dp[n][0] = 0; for (int i = n - 1; i >= 0; --i) { for (int j = 0; j <= k; ++j) { for (int k = 9; k >= 0; --k) { int cnt = __builtin_popcount(d[k] ^ table[i]); if (j >= cnt && (d[k] | table[i]) == d[k] && dp[i + 1][j - cnt] != -1) { dp[i][j] = k; par[i][j] = j - cnt; break; } } } } if (dp[0][k] == -1) { cout << -1 << n ; } else { int i = 0, j = k; while (i < n && j >= 0) { cout << dp[i][j]; j = par[i][j]; ++i; } cout << n ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; int p[maxn], w[maxn]; vector<pair<pair<int, int>, int>> a; int find(int x) { if (p[x] == x) return x; else { int ret = find(p[x]); w[x] ^= w[p[x]]; return p[x] = ret; } } int main() { int l, r, n; cin >> n; for (int i = 0; i < n; i++) { cin >> l >> r; a.push_back(make_pair(make_pair(l, 0), i)); a.push_back(make_pair(make_pair(r, 1), i)); } sort(a.begin(), a.end()); for (int i = 0; i < n; i++) p[i] = i; for (int i = 0; i < a.size(); i += 2) if (a[i].second != a[i + 1].second) { int ret = a[i].first.second == a[i + 1].first.second; int u = a[i].second, v = a[i + 1].second; if (find(u) == find(v)) { if (w[u] ^ w[v] ^ ret) { cout << -1 << endl; return 0; } } else { w[p[v]] = ret ^ w[v]; p[p[v]] = u; } } for (int i = 0; i < n; i++) { find(i); cout << w[i] << ; } cout << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211AI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O211AI_FUNCTIONAL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o211ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
// Local signals
wire C1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211AI_FUNCTIONAL_V
|
//======================================================================
//
// shr32.v
// -------
// 32bit right shift with carry in / carry out.
//
//
// Author: Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module shr32(
input wire [31 : 0] a,
input wire carry_in,
output wire [31 : 0] adiv2,
output wire carry_out
);
assign adiv2 = {carry_in, a[31 : 1]};
assign carry_out = a[0];
endmodule // shr32
//======================================================================
// EOF shr32.v
//======================================================================
|
// ====================================================================
// MAH PONK
//
// Copyright (C) 2007, Viacheslav Slavinsky
// This design and core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
// An open table tennis game for VGA displays.
//
// Author: Viacheslav Slavinsky, http://sensi.org/~svo
//
// Design File: analinput.v
// Analog input module.
// Implements SPI and alternatingly queries 2 channels of ADxxxx.
//
// Pins description:
// clk input clock, same as used for SPI SCK
// pay output paddle A y-coordinate
// pby output paddle B y-coordinate
// miso input MISO
// mosi output MOSI
// cs output ADC CS
// sck output SCK
module analinput(clk, pay, pby, miso, mosi, cs, sck);
parameter PADDLESIZE = 0;
parameter SCREENHEIGHT = 0;
input clk;
output reg[9:0] pay;
output reg[9:0] pby;
input miso;
output reg mosi;
output reg cs;
output sck;
parameter state0 = 0, state1 = 1, state2 = 2, state3 = 3;
reg [1:0] state;
reg [4:0] sckcount;
reg [11:0] datain;
reg ab;
assign sck = clk;
always @(posedge sck) begin
case(state)
state0:
begin
ab <= 1;
state <= state1;
end
state1:
begin
ab <= !ab;
cs <= 0;
mosi <= !ab;
sckcount <= 15;
state <= state2;
end
state2:
begin
if (sckcount != 0)
sckcount <= sckcount - 1'b1;
else
state <= state3;
end
state3:
begin
cs <= 1;
mosi <= 0;
if (ab == 0) begin
pay <= paddlelimiter(datain[11:3]);
end else begin
pby <= paddlelimiter(datain[11:3]);
end
state <= state1;
end
default:
state <= state0;
endcase
end
always @(negedge sck) begin
if (state == state2)
datain <= (datain << 1) | miso;
else if (state == state1)
datain <= 0;
end
//
// Limit paddle position to stay within screen coordinates
//
function [9:0] paddlelimiter;
input [9:0] py;
begin
if (py < PADDLESIZE/2)
paddlelimiter = PADDLESIZE/2;
else
if (py > SCREENHEIGHT-96/2)
paddlelimiter = SCREENHEIGHT-PADDLESIZE/2;
else
paddlelimiter = py;
end
endfunction
endmodule
// $Id: analinput.v,v 1.6 2007/08/27 22:14:46 svo Exp $
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } sort(arr, arr + n); cout << (arr[n - 1] - arr[0] + 1) - n << n ; }
|
#include <bits/stdc++.h> using namespace std; const int N = 500005; int n, k; char a[N], b[N]; int main() { scanf( %d%d%s%s , &n, &k, a, b); long long cur = 1, ans = 0; if (k == 1) { cout << n << endl; return 0; } for (int i = 0; i < n; i++) { cur *= 2; if (a[i] != a ) --cur; if (b[i] != b ) --cur; cur = min(cur, k * 1ll); ans += cur; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int t; cin >> t; while (t--) { long long int n, k, i, c = 1, p; cin >> n >> k; long long int a[n]; set<long long int> s; for (i = 0; i < n; i++) { cin >> a[i]; s.insert(a[i]); } if (s.size() <= k) { cout << 1; } else { if (k == 1) cout << -1; else { p = s.size(); p -= k; if (p % (k - 1) != 0) c++; c += p / (k - 1); cout << c; } } cout << n ; } return 0; }
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2011 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(*i $Id: Decidable.v 13323 2010-07-24 15:57:30Z herbelin $ i*)
(** Properties of decidable propositions *)
Definition decidable (P:Prop) := P \/ ~ P.
Theorem dec_not_not : forall P:Prop, decidable P -> (~ P -> False) -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_True : decidable True.
Proof.
unfold decidable; auto.
Qed.
Theorem dec_False : decidable False.
Proof.
unfold decidable, not; auto.
Qed.
Theorem dec_or :
forall A B:Prop, decidable A -> decidable B -> decidable (A \/ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_and :
forall A B:Prop, decidable A -> decidable B -> decidable (A /\ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_not : forall A:Prop, decidable A -> decidable (~ A).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_imp :
forall A B:Prop, decidable A -> decidable B -> decidable (A -> B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_iff :
forall A B:Prop, decidable A -> decidable B -> decidable (A<->B).
Proof.
unfold decidable; tauto.
Qed.
Theorem not_not : forall P:Prop, decidable P -> ~ ~ P -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_or : forall A B:Prop, ~ (A \/ B) -> ~ A /\ ~ B.
Proof.
tauto.
Qed.
Theorem not_and : forall A B:Prop, decidable A -> ~ (A /\ B) -> ~ A \/ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_imp : forall A B:Prop, decidable A -> ~ (A -> B) -> A /\ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem imp_simp : forall A B:Prop, decidable A -> (A -> B) -> ~ A \/ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_iff :
forall A B:Prop, decidable A -> decidable B ->
~ (A <-> B) -> (A /\ ~ B) \/ (~ A /\ B).
Proof.
unfold decidable; tauto.
Qed.
(** Results formulated with iff, used in FSetDecide.
Negation are expanded since it is unclear whether setoid rewrite
will always perform conversion. *)
(** We begin with lemmas that, when read from left to right,
can be understood as ways to eliminate uses of [not]. *)
Theorem not_true_iff : (True -> False) <-> False.
Proof.
tauto.
Qed.
Theorem not_false_iff : (False -> False) <-> True.
Proof.
tauto.
Qed.
Theorem not_not_iff : forall A:Prop, decidable A ->
(((A -> False) -> False) <-> A).
Proof.
unfold decidable; tauto.
Qed.
Theorem contrapositive : forall A B:Prop, decidable A ->
(((A -> False) -> (B -> False)) <-> (B -> A)).
Proof.
unfold decidable; tauto.
Qed.
Lemma or_not_l_iff_1 : forall A B: Prop, decidable A ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_l_iff_2 : forall A B: Prop, decidable B ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_1 : forall A B: Prop, decidable A ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_2 : forall A B: Prop, decidable B ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma imp_not_l : forall A B: Prop, decidable A ->
(((A -> False) -> B) <-> (A \/ B)).
Proof.
unfold decidable. tauto.
Qed.
(** Moving Negations Around:
We have four lemmas that, when read from left to right,
describe how to push negations toward the leaves of a
proposition and, when read from right to left, describe
how to pull negations toward the top of a proposition. *)
Theorem not_or_iff : forall A B:Prop,
(A \/ B -> False) <-> (A -> False) /\ (B -> False).
Proof.
tauto.
Qed.
Lemma not_and_iff : forall A B:Prop,
(A /\ B -> False) <-> (A -> B -> False).
Proof.
tauto.
Qed.
Lemma not_imp_iff : forall A B:Prop, decidable A ->
(((A -> B) -> False) <-> A /\ (B -> False)).
Proof.
unfold decidable. tauto.
Qed.
Lemma not_imp_rev_iff : forall A B : Prop, decidable A ->
(((A -> B) -> False) <-> (B -> False) /\ A).
Proof.
unfold decidable. tauto.
Qed.
(** With the following hint database, we can leverage [auto] to check
decidability of propositions. *)
Hint Resolve dec_True dec_False dec_or dec_and dec_imp dec_not dec_iff
: decidable_prop.
(** [solve_decidable using lib] will solve goals about the
decidability of a proposition, assisted by an auxiliary
database of lemmas. The database is intended to contain
lemmas stating the decidability of base propositions,
(e.g., the decidability of equality on a particular
inductive type). *)
Tactic Notation "solve_decidable" "using" ident(db) :=
match goal with
| |- decidable _ =>
solve [ auto 100 with decidable_prop db ]
end.
Tactic Notation "solve_decidable" :=
solve_decidable using core.
|
#include <bits/stdc++.h> using namespace std; int main() { int l; float p, q, t, res; cin >> l >> p >> q; t = l / (p + q); res = p * t; printf( %.4f , res); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e3 + 5; const int inf = 0x3f3f3f3f; const long long mod = 1e9 + 7; const double eps = 1e-6; vector<int> g[maxn]; vector<int> tree[maxn]; int deep[maxn], son[maxn]; int cnt, mx; void dfs(int x, int y) { int sz = g[x].size(); deep[x] = 0; son[x] = -1; for (int i = 0; i < sz; ++i) { int to = g[x][i]; if (to == y) { continue; } tree[x].push_back(to); dfs(to, x); if (son[x] == -1 || deep[son[x]] < deep[to]) { son[x] = son[to]; } } if (son[x] == -1) { son[x] = x; } else { deep[x] = deep[son[x]] + 1; } } struct node { int id, w; bool operator<(const node& rhs) const { return w > rhs.w; } } nd[maxn]; int solve(int x) { int sz = tree[x].size(); for (int i = 0; i < sz; ++i) { nd[i] = {tree[x][i], deep[tree[x][i]]}; } sort(nd, nd + sz); int hf = sz / 2; for (int i = 0; i < hf; ++i) { int a = nd[i * 2].id, b = nd[i * 2 + 1].id; ++cnt; printf( ? %d %d n , son[a], son[b]); fflush(stdout); int c; scanf( %d , &c); if (c != x) { return solve(c); } if (cnt >= mx) break; } if ((sz & 1) == 1 && cnt < mx) { ++cnt; printf( ? %d %d n , x, son[nd[sz - 1].id]); fflush(stdout); int c; scanf( %d , &c); if (c != x) { return solve(c); } } return x; } int main() { int n; scanf( %d , &n); cnt = 0, mx = n / 2; for (int i = 1; i < n; ++i) { int u, v; scanf( %d%d , &u, &v); g[u].push_back(v); g[v].push_back(u); } dfs(1, -1); printf( ! %d n , solve(1)); fflush(stdout); return 0; }
|
`timescale 1 ps / 1 ps
module song_ip_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output speaker,
output ampSD,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
song_ip_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) song_ip_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready),
.speaker(speaker), //our stuff
.ampSD(ampSD) // our stuff
);
// Add user logic here
// User logic ends
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int bt[50 + 10]; map<int, int> MAP; int main() { long long int a, b, c, d, e, f, m, n, p, q, x, y, z, w, k; vector<long long int> v[2525], temp; cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> x; bt[i] = x; temp.push_back(x); } sort(temp.begin(), temp.end(), greater<long long int>()); for (int i = 0; i < temp.size(); i++) { v[i + 1].push_back(temp[i]); } if (n >= k) { for (int i = 1; i <= k; i++) { cout << 1 << << bt[i] << endl; } } else { long long int start = 2; long long int end = n; long long int mul = 1; long long int cnt = 1; int p = 0; long long int get = n + 1; while (get - 1 < k) { for (int i = start; i <= end; i++) { v[get] = v[i]; v[get].insert(v[get].end(), v[mul].begin(), v[mul].end()); get++; } start = end + 2; end = get - 1; mul++; } for (int i = 1; i <= k; i++) { cout << v[i].size() << ; long long int lmt = v[i].size(); cout << v[i][0]; for (int j = 1; j < lmt; j++) { cout << << v[i][j]; } cout << endl; } } return (0); }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_idelay8(
input [7:0] i,
output [7:0] o,
input clk,
input rst,
input ce,
input inc
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d0 (
.I(i[0]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[0])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d1 (
.I(i[1]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[1])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d2 (
.I(i[2]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[2])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d3 (
.I(i[3]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[3])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d4 (
.I(i[4]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[4])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d5 (
.I(i[5]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[5])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d6 (
.I(i[6]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[6])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d7 (
.I(i[7]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[7])
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111A_SYMBOL_V
`define SKY130_FD_SC_HD__O2111A_SYMBOL_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2111a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111A_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31O_2_V
`define SKY130_FD_SC_LP__A31O_2_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31O_2_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ram.v
//
// *Module Description:
// Scalable RAM model
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module ram_16x1k_sp (
clka,
ena,
wea,
addra,
dina,
douta
);
input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
//============
// RAM
//============
ram_sp #(.ADDR_MSB(9), .MEM_SIZE(2048)) ram_sp_inst (
// OUTPUTs
.ram_dout ( douta), // RAM data output
// INPUTs
.ram_addr ( addra), // RAM address
.ram_cen (~ena), // RAM chip enable (low active)
.ram_clk ( clka), // RAM clock
.ram_din ( dina), // RAM data input
.ram_wen (~wea) // RAM write enable (low active)
);
endmodule // ram_16x1k_sp
|
#include <bits/stdc++.h> using namespace std; const int N = 10005; int a[N], sorted[N], n, m, sum[20][N], tree[20][N]; inline void build(int deep, int l, int r) { int i, mid = (l + r) >> 1, lm = mid - l + 1, lp = l, rp = mid + 1; for (i = l; i <= mid; i++) if (sorted[i] > sorted[mid]) lm--; for (i = l; i <= r; i++) { if (i == l) sum[deep][i] = 0; else sum[deep][i] = sum[deep][i - 1]; if (tree[deep][i] == sorted[mid]) { if (lm) { lm--; sum[deep][i]++; tree[deep + 1][lp++] = tree[deep][i]; } else tree[deep + 1][rp++] = tree[deep][i]; } else if (tree[deep][i] > sorted[mid]) { sum[deep][i]++; tree[deep + 1][lp++] = tree[deep][i]; } else tree[deep + 1][rp++] = tree[deep][i]; } if (l != r) { build(deep + 1, l, mid); build(deep + 1, mid + 1, r); } } int ask(int deep, int l, int r, int ql, int qr, int k) { int s, ss, mid = (l + r) >> 1; if (l == r) return tree[deep][l]; if (l == ql) { s = 0; ss = sum[deep][qr]; } else { s = sum[deep][ql - 1]; ss = sum[deep][qr] - s; } if (k <= ss) return ask(deep + 1, l, mid, l + s, l + s + ss - 1, k); else return ask(deep + 1, mid + 1, r, mid - l + 1 + ql - s, mid - l + 1 + qr - s - ss, k - ss); } inline bool cmp(int a, int b) { return a > b; } inline int read() { int x = 0; char ch = getchar(); bool positive = 1; for (; !isdigit(ch); ch = getchar()) if (ch == - ) positive = 0; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return positive ? x : -x; } inline void write(int a) { if (a >= 10) write(a / 10); putchar( 0 + a % 10); } int main() { n = read(); m = read(); for (int i = 1; i <= n; i++) a[i] = tree[0][i] = sorted[i] = read(); sort(sorted + 1, sorted + 1 + n, cmp); build(0, 1, n); while (m--) { int s1 = read(), s2 = read(), s3 = read(); if (ask(0, 1, n, s1, s2, s2 - s3 + 1) == a[s3]) puts( Yes ); else puts( No ); } }
|
#include <bits/stdc++.h> using namespace std; bool diverse(string x) { sort(x.begin(), x.end()); for (int i = 1; i < x.size(); i++) if (x[i] - x[i - 1] != 1) return 0; return 1; } int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(0); int n; cin >> n; cin.ignore(256, n ); vector<string> in(n); for (int i = 0; i < n; i++) getline(cin, in[i], n ); for (int i = 0; i < n; i++) { if (diverse(in[i]) || in[i].size() == 1) cout << Yes << endl; else cout << No << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A22O_FUNCTIONAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22O_FUNCTIONAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_tagl_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// This module is instanced twice, one for
// each half of what used to be tagdp.
// Pin positions. ( DP size is
`include "iop.h"
`include "sctag.h"
module sctag_tagl_dp( /*AUTOARG*/
// Outputs
so, parity_c2, tag_triad0_c3, tag_triad1_c3,
// Inputs
way0_tag_c2, way1_tag_c2, way2_tag_c2, way3_tag_c2, way4_tag_c2,
way5_tag_c2, rclk, si, se, triad0_muxsel_c3, triad1_muxsel_c3
);
input [`TAG_WIDTH-1:0] way0_tag_c2; // tag rd
input [`TAG_WIDTH-1:0] way1_tag_c2;// tag rd
input [`TAG_WIDTH-1:0] way2_tag_c2;// tag rd
input [`TAG_WIDTH-1:0] way3_tag_c2;// tag rd
input [`TAG_WIDTH-1:0] way4_tag_c2;// tag rd
input [`TAG_WIDTH-1:0] way5_tag_c2;// tag rd
input rclk;
input si,se;
output so;
output [5:0] parity_c2;
output [`TAG_WIDTH-1:0] tag_triad0_c3;
output [`TAG_WIDTH-1:0] tag_triad1_c3;
input [2:0] triad0_muxsel_c3;
input [2:0] triad1_muxsel_c3;
// All tag bits are staged into C3
wire [`TAG_WIDTH-1:0] way0_tag_c3;
wire [`TAG_WIDTH-1:0] way1_tag_c3;
wire [`TAG_WIDTH-1:0] way2_tag_c3;
wire [`TAG_WIDTH-1:0] way3_tag_c3;
wire [`TAG_WIDTH-1:0] way4_tag_c3;
wire [`TAG_WIDTH-1:0] way5_tag_c3;
// This data path is 32 bits wide/
zzpar32 p0_way0 ( .z(parity_c2[0]), .d({4'b0,way0_tag_c2[`TAG_WIDTH-1:0]}));
dff_s #(`TAG_WIDTH) ff_tag_way0_c3 (.din(way0_tag_c2[`TAG_WIDTH-1:0]), .clk(rclk),
.q(way0_tag_c3[`TAG_WIDTH-1:0]), .se(se), .si(), .so());
zzpar32 p0_way1 ( .z(parity_c2[1]), .d({4'b0,way1_tag_c2[`TAG_WIDTH-1:0]}));
dff_s #(`TAG_WIDTH) ff_tag_way1_c3 (.din(way1_tag_c2[`TAG_WIDTH-1:0]), .clk(rclk),
.q(way1_tag_c3[`TAG_WIDTH-1:0]), .se(se), .si(), .so());
zzpar32 p0_way2 ( .z(parity_c2[2]), .d({4'b0,way2_tag_c2[`TAG_WIDTH-1:0]}));
dff_s #(`TAG_WIDTH) ff_tag_way2_c3 (.din(way2_tag_c2[`TAG_WIDTH-1:0]), .clk(rclk),
.q(way2_tag_c3[`TAG_WIDTH-1:0]), .se(se), .si(), .so());
mux3ds #(`TAG_WIDTH) mux_tag_triad0 (.dout (tag_triad0_c3[`TAG_WIDTH-1:0]),
.in0(way0_tag_c3[`TAG_WIDTH-1:0]),
.in1(way1_tag_c3[`TAG_WIDTH-1:0]),
.in2(way2_tag_c3[`TAG_WIDTH-1:0]),
.sel0(triad0_muxsel_c3[0]),
.sel1(triad0_muxsel_c3[1]),
.sel2(triad0_muxsel_c3[2]));
mux3ds #(`TAG_WIDTH) mux_tag_triad1 (.dout (tag_triad1_c3[`TAG_WIDTH-1:0]),
.in0(way3_tag_c3[`TAG_WIDTH-1:0]),
.in1(way4_tag_c3[`TAG_WIDTH-1:0]),
.in2(way5_tag_c3[`TAG_WIDTH-1:0]),
.sel0(triad1_muxsel_c3[0]),
.sel1(triad1_muxsel_c3[1]),
.sel2(triad1_muxsel_c3[2]));
zzpar32 p0_way3 ( .z(parity_c2[3]), .d({4'b0,way3_tag_c2[`TAG_WIDTH-1:0]}));
dff_s #(`TAG_WIDTH) ff_tag_way3_c3 (.din(way3_tag_c2[`TAG_WIDTH-1:0]), .clk(rclk),
.q(way3_tag_c3[`TAG_WIDTH-1:0]), .se(se), .si(), .so());
zzpar32 p0_way4 ( .z(parity_c2[4]), .d({4'b0,way4_tag_c2[`TAG_WIDTH-1:0]}));
dff_s #(`TAG_WIDTH) ff_tag_way4_c3 (.din(way4_tag_c2[`TAG_WIDTH-1:0]), .clk(rclk),
.q(way4_tag_c3[`TAG_WIDTH-1:0]), .se(se), .si(), .so());
zzpar32 p0_way5 ( .z(parity_c2[5]), .d({4'b0,way5_tag_c2[`TAG_WIDTH-1:0]}));
dff_s #(`TAG_WIDTH) ff_tag_way5_c3 (.din(way5_tag_c2[`TAG_WIDTH-1:0]), .clk(rclk),
.q(way5_tag_c3[`TAG_WIDTH-1:0]), .se(se), .si(), .so());
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int an[333333]; int bit[333333]; void upd(int x, int v) { for (int i = x; i <= n; i += (i & -i)) { bit[i] += v; } } int get(int x) { int an = 0; for (int i = x; i > 0; i -= (i & -i)) an += bit[i]; return an; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) upd(i, 1); while (m--) { int from, to, win; scanf( %d%d%d , &from, &to, &win); int add = get(to); int dec = get(from - 1); while (add > dec) { int ll = from, rr = to; while (ll <= rr) { int mid = (ll + rr) / 2; if (get(mid) == dec) ll = mid + 1; else rr = mid - 1; } an[ll] = win; upd(ll, -1); --add; } an[win] = 0; upd(win, 1); } for (int i = 1; i <= n; ++i) printf( %d , an[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s1; string s2; while (cin >> s1 >> s2) { int n = s1.length(), m = s2.length(); int dp[n + 1][m + 1]; for (int i = 0; i < n + 1; i++) dp[i][0] = i; for (int i = 0; i < m + 1; i++) dp[0][i] = i; for (int i = 1; i < n + 1; i++) { for (int j = 1; j < m + 1; j++) { if (s1[i - 1] == s2[j - 1]) dp[i][j] = dp[i - 1][j - 1]; else dp[i][j] = min(min(dp[i - 1][j], dp[i][j - 1]), dp[i - 1][j - 1]) + 1; } } cout << dp[n][m] << endl; int i = n, j = m; while (i >= 0 && j >= 0) { if (dp[i][j - 1] == dp[i][j] - 1) { cout << INSERT + to_string(i + 1) + + s2[j - 1] << endl; j--; } else if (dp[i - 1][j] == dp[i][j] - 1) { cout << DELETE + to_string(i) << endl; i--; } else if (dp[i - 1][j - 1] == dp[i][j] - 1 && s1[i - 1] != s2[j - 1]) { cout << REPLACE + to_string(i) + + s2[j - 1] << endl; i--, j--; } else i--, j--; } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hd__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22O_2_V
`define SKY130_FD_SC_LS__A22O_2_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a22o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a22o_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22O_2_V
|
#include <bits/stdc++.h> using namespace std; template <class T, class U> void ckmin(T &a, U b) { if (a > b) a = b; } template <class T, class U> void ckmax(T &a, U b) { if (a < b) a = b; } int N, M; bitset<1013> grid[1013]; int dn[1013][1013], rt[1013][1013]; int upd[1013][1013]; int x = -1, y = -1; int ans = 998244353; void check(int sx, int sy) { for (auto i = (0); i < (N + 1); i++) { for (auto j = (0); j < (M + 1); j++) { upd[i][j] = 0; } } int cx = x, cy = y; while (true) { upd[cx][cy]++; upd[cx + sx][cy]--; upd[cx][cy + sy]--; upd[cx + sx][cy + sy]++; if (grid[cx + sx][cy]) { cx++; continue; } if (grid[cx][cy + sy]) { cy++; continue; } break; } for (auto i = (0); i < (N); i++) { for (auto j = (0); j < (M); j++) { if (i) upd[i][j] += upd[i - 1][j]; if (j) upd[i][j] += upd[i][j - 1]; if (i && j) upd[i][j] -= upd[i - 1][j - 1]; if (upd[i][j] && !grid[i][j]) return; if (!upd[i][j] && grid[i][j]) return; } } ckmin(ans, sx * sy); } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> N >> M; for (auto i = (0); i < (N); i++) { string temps; cin >> temps; for (auto j = (0); j < (M); j++) { grid[i][j] = (temps[j] == X ); } } for (auto i = (N)-1; i >= (0); i--) { for (auto j = (M)-1; j >= (0); j--) { if (grid[i][j]) { x = i; y = j; } } } for (auto i = (0); i < (N); i++) { for (auto j = (0); j < (y); j++) { if (grid[i][j]) { cout << -1 n ; return 0; } } } for (auto i = (0); i < (N); i++) { for (auto j = (M)-1; j >= (0); j--) { rt[i][j] = (grid[i][j] ? 1 + rt[i][j + 1] : 0); } } for (auto i = (0); i < (M); i++) { for (auto j = (N)-1; j >= (0); j--) { dn[j][i] = (grid[j][i] ? 1 + dn[j + 1][i] : 0); } } int dy = rt[x][y], dx = dn[x][y]; for (auto i = (x); i < (x + dx); i++) { for (auto j = (y); j < (y + dy); j++) { if (!grid[i][j]) { cout << -1 n ; return 0; } } } check(dx, dy); check(dx, 1); check(1, dy); for (auto i = (0); i < (dy); i++) { if (grid[x + dx][y + i]) { check(dx, dy - i); break; } } for (auto i = (0); i < (dx); i++) { if (grid[x + i][y + dy]) { check(dx - i, dy); break; } } if (ans == 998244353) { cout << -1 n ; return 0; } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; void ga(int N, int *A) { for (int i(0); i < N; i++) scanf( %d , A + i); } unordered_map<int, int> dp; int N, S[(4000)]; int dyn(int a, int b, int K, bool x) { if (b - a + 1 < K) return 0; if (b - a + 1 == K) return (S[b] - (a ? S[a - 1] : 0)); if (dp.count( (a + (4000) * b + (4000) * (4000) * K + x * (4000) * (4000) * 100))) return dp[(a + (4000) * b + (4000) * (4000) * K + x * (4000) * (4000) * 100)]; if (!x) return dp[(a + (4000) * b + (4000) * (4000) * K + x * (4000) * (4000) * 100)] = max(-dyn(a + K, b, K, 1) + (S[a + K - 1] - (a ? S[a - 1] : 0)), -dyn(a + K + 1, b, K + 1, 1) + (S[a + K] - (a ? S[a - 1] : 0))); return dp[(a + (4000) * b + (4000) * (4000) * K + x * (4000) * (4000) * 100)] = max(-dyn(a, b - K, K, 0) + (S[b] - (b - K + 1 ? S[b - K + 1 - 1] : 0)), -dyn(a, b - K - 1, K + 1, 0) + (S[b] - (b - K ? S[b - K - 1] : 0))); } int main(void) { dp.max_load_factor(.4); scanf( %d , &N), ga(N, S); for (int k(1); k < N; k++) S[k] += S[k - 1]; printf( %d n , dyn(0, N - 1, 1, 0)); return 0; }
|
#include <bits/stdc++.h> using namespace std; double dp[200]; int next1[200]; int cnt(int i, int j) { if ((11 - i) % 2 == 1) { return (10 - i) * 10 + j; } else { return (10 - i) * 10 + (11 - j); } } int main() { for (int i = (1); i < (11); i++) { for (int j = (1); j < (11); j++) { int x; cin >> x; int now = cnt(i, j); int net = cnt(i - x, j); next1[now] = net; } } for (int i = (0); i < (6); i++) dp[99 - i] = 6; for (int i = 93; i >= 1; i--) { dp[i] = 1; for (int j = (1); j < (7); j++) { dp[i] += min(dp[i + j], dp[next1[i + j]]) / 6; } } printf( %.10lf , dp[1]); return 0; }
|
#include <bits/stdc++.h> int main() { int mem, arr[5001], i, tri = 0; scanf( %d , &mem); for (i = 1; i <= mem; i++) { scanf( %d , &arr[i]); } for (i = 1; i <= mem; i++) { if (i == arr[arr[arr[i]]]) { tri = 1; } } if (tri == 1) { printf( YES n ); } else { printf( NO n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_2_V
`define SKY130_FD_SC_LP__A21O_2_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21o_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21o_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_2_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; int main() { int n; cin >> n; string s; cin >> s; queue<int> D, R; for (int i = 0; i < n; i++) { if (s[i] == D ) D.push(i); if (s[i] == R ) R.push(i); } while (D.size() && R.size()) { if (D.front() < R.front()) { R.pop(); D.push(D.front() + n); D.pop(); } else { D.pop(); R.push(R.front() + n); R.pop(); } } cout << (D.size() ? D : R ) << endl; return 0; }
|
`timescale 1ns / 1ps
module uart_test(
input clk,
input rst,
input [7:0] sw,
input rx,
input write,
input read,
input speed_up,
input speed_down,
output tx,
output rdy,
output full,
output [7:0]seg,
output [3:0] an
);
reg [3:0] baud;
wire up, down, reset;
wire up_pulse, down_pulse;
wire write_pulse, read_pulse;
always @ (posedge clk) begin
if(reset == 1'b1) begin
baud <= 4'h5;
end
else if(up_pulse == 1'b1) begin
if (baud < 4'h9) begin
baud <= baud + 1'b1;
end
else begin
baud <= baud;
end
end
else if(down_pulse == 1'b1) begin
if(baud > 4'h0) begin
baud <= baud - 1'b1;
end
else begin
baud <= baud;
end
end
else begin
baud <= baud;
end
end
high_to_pulse htp_up(
.CLK(clk),
.IN(up),
.OUT(up_pulse)
);
high_to_pulse htp_down(
.CLK(clk),
.IN(down),
.OUT(down_pulse)
);
high_to_pulse htp_write(
.CLK(clk),
.IN(write),
.OUT(write_pulse)
);
high_to_pulse htp_read(
.CLK(clk),
.IN(read),
.OUT(read_pulse)
);
uart_ctrl uart(
.CLK(clk),
.RST(reset),
.EN(1'b1),
.BAUD(baud),
.TXEN(1'b1),
.RXEN(1'b1),
.TX(tx),
.RX(rx),
.WRITE(write_pulse),
.WRDATA(sw),
.ISFULL(full),
.READ(read_pulse),
.RDDATA(seg),
.DATARDY(rdy)
);
debounce debounce_speed_up(
.CLK(clk),
.IN(speed_up),
.OUT(up)
);
debounce debounce_speed_down(
.CLK(clk),
.IN(speed_down),
.OUT(down)
);
debounce debounce_reset(
.CLK(clk),
.IN(rst),
.OUT(reset)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return (b == 0 ? a : gcd(b, a % b)); } long long lcm(long long a, long long b) { return (a * (b / gcd(a, b))); } long long POWER(long long x, long long y, long long m) { if (y == 0) return 1; if (y % 2 == 0) { long long temp = POWER(x, y / 2, m); temp *= temp; temp %= m; return temp; } long long temp = POWER(x, y - 1, m); temp *= x; temp %= m; return temp; } long long POWER(long long x, long long y) { if (y == 0) return 1; if (y % 2 == 0) { long long temp = POWER(x, y / 2); temp *= temp; return temp; } long long temp = POWER(x, y - 1); temp *= x; return temp; } long long a[100010]; int main() { ifstream fin( ali ); long long n, k; cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; long long id = 0; for (long long i = 1; i <= n; i++) { if ((i * (i + 1)) / 2 >= k) { id = i; break; } } if ((id * (id + 1) / 2) == k) { cout << a[id] << n ; return 0; } id--; id = (id * (id + 1)) / 2; for (int i = 1; i <= n; i++) { id++; if (id == k) { cout << a[i] << n ; return 0; } } main(); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) { int sum, limit; cin >> sum >> limit; vector<pair<int, int>> v; for (int i = 1; i <= limit; i++) { v.push_back({1 << __builtin_ctz(i), i}); } sort(v.rbegin(), v.rend()); vector<int> a; int i = 0; while (sum) { if (i == v.size()) break; if (sum >= v[i].first) { a.push_back(v[i].second); sum -= v[i].first; } i++; } if (sum != 0) cout << -1 n ; else { cout << a.size() << n ; for (auto i : a) { cout << i << ; } cout << n ; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB8TO1_TB_V
`define SKY130_FD_SC_HDLL__MUXB8TO1_TB_V
/**
* muxb8to1: Buffered 8-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__muxb8to1.v"
module top();
// Inputs are registered
reg D;
reg S;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
S = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 S = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 S = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 S = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 S = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 S = 1'bx;
#600 D = 1'bx;
end
sky130_fd_sc_hdll__muxb8to1 dut (.D(D), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB8TO1_TB_V
|
`timescale 1ns / 1ns
module eth_grx
(input c,
input [3:0] phy_rxd,
input phy_rxc,
input phy_rxdv,
output [7:0] d,
output dv,
output erx); // end of RX
wire [7:0] int_d;
wire int_dv;
wire int_er;
altddio_in #(.width(5)) phy_rx_ddr
(.inclock(~phy_rxc),
.datain({phy_rxdv, phy_rxd}),
.dataout_h({int_er, int_d[7:4]}),
.dataout_l({int_dv, int_d[3:0]}),
.aclr(1'b0), .aset(1'b0), .inclocken(1'b1), .sset(1'b0), .sclr(1'b0));
///////////////////////////////////////////////////////////////////////////
// this fifo takes us from the phy GRX clock domain to the on-chip 125 mhz
wire [4:0] xclk_fifo_rdusedw;
wire [7:0] xclk_fifo_q;
wire draining;
r draining_r
(.c(c), .en(|xclk_fifo_rdusedw[4:2]), .rst(xclk_fifo_rdusedw == 5'h2),
.d(1'b1), .q(draining));
dcfifo #(.lpm_width(8),
.lpm_numwords(32),
.lpm_widthu(5),
.lpm_showahead("ON"),
.use_eab("ON"),
.intended_device_family("CYCLONE V")) xclk_fifo
(.wrclk(~phy_rxc), .rdclk(c),
.wrreq(int_dv), .rdreq(draining),
.data(int_d), .q(xclk_fifo_q),
.rdusedw(xclk_fifo_rdusedw),
.aclr(1'b0));
// synchronize to on-chip clk_125 domain
// todo: this doesn't always work, depending on how the PHY phase-locked
// to the 25mhz clock. need to do a FIFO here.
/*
wire [29:0] rx_sync;
r #(30) rx_sync_r
(.c(clk), .rst(1'b0), .en(1'b1),
.d({rx_sync[19:0], int_dv, int_er, int_d}),
.q(rx_sync));
wire raw_dv = rx_sync[29];
assign d = rx_sync[27:20];
*/
wire eth_dv = draining; //|xclk_fifo_rdusedw;
assign d = xclk_fifo_q;
localparam SW = 3, CW = 3;
localparam ST_IDLE = 3'd0;
localparam ST_PREAMBLE = 3'd1;
localparam ST_PAYLOAD = 3'd2;
localparam ST_STOP = 3'd3;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
always @* begin
case (state)
ST_IDLE:
if (eth_dv && d == 8'h55) ctrl = { ST_PREAMBLE, 3'b000 };
else ctrl = { ST_IDLE , 3'b000 };
ST_PREAMBLE:
if (eth_dv && d == 8'h55) ctrl = { ST_PREAMBLE, 3'b000 };
else if (eth_dv && d == 8'hd5) ctrl = { ST_PAYLOAD , 3'b000 };
else ctrl = { ST_IDLE , 3'b000 };
ST_PAYLOAD:
if (eth_dv) ctrl = { ST_PAYLOAD , 3'b001 };
else ctrl = { ST_STOP , 3'b010 };
ST_STOP: ctrl = { ST_IDLE , 3'b000 }; // fcs ?
default: ctrl = { ST_IDLE , 3'b000 };
endcase
end
assign dv = ctrl[0];
assign erx = ctrl[1];
endmodule
|
`include "defs.v"
// Bundling CPU and ICache together
module toycpu(
input clk, // clock
input rst, // reset
// Memory bus
input [31:0] bus_data_in, // bus data in
input bus_data_in_ready, // bus data ready
input bus_data_ack, // acknowledge write op
output bus_data_wr, // request data write
output bus_data_rd, // request data read
output [31:0] bus_data_address, // output data address
output [31:0] bus_data_out, // data to be written
// CPU signals
input irq, // IRQ requested
input [3:0] irqn, // IRQ number
output irq_ack, // Interrupt acknowledged and processed
output irq_busy, // Busy doing current interrupt (maintain your fifo outside!)
output [31:0] debug_reg_out,
input [3:0] debug_reg_num,
input debug,
input step,
output step_ack,
input stall
);
wire [31:0] ic_addr;
wire [31:0] ic_data_out;
wire [31:0] ic_bus_data_address;
wire [31:0] ic_data_in;
wire [31:0] data_in;
wire [31:0] data_out;
wire [31:0] data_address;
wire ic_rq;
wire ic_data_out_valid;
wire data_ack;
wire data_wr;
wire data_rd;
wire data_in_ready;
wire ic_data_in_ready;
wire ic_data_rd;
toycpu_core core1(.clk(clk),
.rst(rst),
.ic_addr(ic_addr),
.ic_rq(ic_rq),
.ic_data_out(ic_data_out),
.ic_data_out_valid(ic_data_out_valid),
.data_in(data_in),
.data_in_ready(data_in_ready),
.data_ack(data_ack),
.data_wr(data_wr),
.data_rd(data_rd),
.data_address(data_address),
.data_out(data_out),
.irq(irq),
.irqn(irqn),
.irq_ack(irq_ack),
.irq_busy(irq_busy),
.debug_reg_out(debug_reg_out),
.debug_reg_num(debug_reg_num),
.debug(debug),
.step(step),
.step_ack(step_ack),
.stall(stall)
);
toy_icache cache1 (.clk(clk),
.reset(rst),
.ic_addr(ic_addr),
.ic_rq(ic_rq),
.ic_data_out_valid(ic_data_out_valid),
.ic_data_out(ic_data_out),
.data_in(ic_data_in),
.data_in_ready(ic_data_in_ready),
.data_rd(ic_data_rd),
.data_address(ic_bus_data_address));
wire grant_ic;
wire grant_lsu;
reg ic_rq_cnt;
reg lsu_rq_cnt;
wire gnt2;
wire gnt3;
arbiter arb1 (.clk(clk),
.rst(!rst),
.req0(ic_rq_cnt),
.req1(lsu_rq_cnt),
.req2(0),
.req3(0),
.gnt0(grant_ic),
.gnt1(grant_lsu),
.gnt2(gnt2),
.gnt3(gnt3)
);
always @(posedge clk)
if(!rst) begin
ic_rq_cnt <= 0;
lsu_rq_cnt <= 0;
end else begin
if (ic_data_rd) ic_rq_cnt <= 1;
else if (grant_ic && !bus_data_in_ready) ic_rq_cnt <= 0;
if (data_rd|data_wr) lsu_rq_cnt <= 1;
else if (grant_lsu && !bus_data_in_ready && !bus_data_ack)
lsu_rq_cnt <= 0;
end
assign ic_data_in_ready = grant_ic?bus_data_in_ready:0;
assign data_in_ready = grant_lsu?bus_data_in_ready:0;
assign ic_data_in = grant_ic?bus_data_in:0;
assign data_in = grant_lsu?bus_data_in:0;
// Memory bus combinational logic
assign bus_data_address = grant_ic?ic_bus_data_address:data_address;
assign bus_data_wr = grant_lsu?data_wr:0;
assign bus_data_rd = grant_ic?ic_data_rd:grant_lsu?data_rd:0;
assign bus_data_out = grant_lsu?data_out:0;
assign data_ack = grant_lsu?bus_data_ack:0;
endmodule // toycpu
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CONB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__CONB_BEHAVIORAL_PP_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_p/sky130_fd_sc_ms__udp_pwrgood_pp_p.v"
`include "../../models/udp_pwrgood_pp_g/sky130_fd_sc_ms__udp_pwrgood_pp_g.v"
`celldefine
module sky130_fd_sc_ms__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_ms__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_ms__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CONB_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
module regfile(
input wire wclk, rclk,
input wire[3:0] address,
input wire[23:0] data_in,
output wire[23:0] data_out);
wire[15:0] Yi;
wire[15:0] clk;
assign clk[15:0] = {16{wclk}} & Yi;
wire[23:0] regQ0, regQ1, regQ2, regQ3, regQ4,
regQ5, regQ6, regQ7, regQ8, regQ9, regQ10,
regQ11, regQ12, regQ13, regQ14, regQ15;
decoder_4_16 m0(address, wclk, Yi);
mux_16_1 m1(rclk, address, regQ0, regQ1, regQ2, regQ3, regQ4,
regQ5, regQ6, regQ7, regQ8, regQ9, regQ10,
regQ11, regQ12, regQ13, regQ14, regQ15, data_out);
register24 r0(clk[0], data_in, regQ0),
r1(clk[1], data_in, regQ1),
r2(clk[2], data_in, regQ2),
r3(clk[3], data_in, regQ3),
r4(clk[4], data_in, regQ4),
r5(clk[5], data_in, regQ5),
r6(clk[6], data_in, regQ6),
r7(clk[7], data_in, regQ7),
r8(clk[8], data_in, regQ8),
r9(clk[9], data_in, regQ9),
r10(clk[10], data_in, regQ10),
r11(clk[11], data_in, regQ11),
r12(clk[12], data_in, regQ12),
r13(clk[13], data_in, regQ13),
r14(clk[14], data_in, regQ14),
r15(clk[15], data_in, regQ15);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Exam { int s, d, c, id; bool operator<(const Exam &e1) const { return d < e1.d; } }; const int N = 105; int n, m, to[N]; Exam e[N]; int main() { cin >> n >> m; for (int i = 1; i <= m; i++) { cin >> e[i].s >> e[i].d >> e[i].c; e[i].id = i; to[e[i].d] = m + 1; } sort(e + 1, e + m + 1); for (int i = 1; i <= m; i++) { int cnt = 0; for (int j = e[i].s; j < e[i].d; j++) { if (to[j] == 0) { to[j] = e[i].id; if (++cnt == e[i].c) break; } } if (cnt < e[i].c) { cout << -1 << endl; return 0; } } for (int i = 1; i <= n; i++) cout << to[i] << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; const int D = 10000010; const int MAXW = N + 1000; const int mod = 1e9 + 7; int n, m; int pw2[MAXW + 10]; struct edge { int to, nx, w; } ee[N * 2]; int eq[N], en = 1; int dn, flag; int l[D], r[D], hs[D]; int ans[N], root[N], pred[N]; bool done[N]; int sv[N], svt; bool cmp(int u, int v) { if (!l[u] && !r[u]) return hs[u] <= hs[v]; else return hs[r[u]] == hs[r[v]] ? cmp(l[u], l[v]) : cmp(r[u], r[v]); } struct compare { bool operator()(const pair<int, int>& u, const pair<int, int>& v) { if (hs[u.first] == hs[v.first]) return u > v; else return !cmp(u.first, v.first); } }; priority_queue<pair<int, int>, vector<pair<int, int> >, compare> Q; void update(int d, int lt, int rt) { int md = (lt + rt) >> 1; hs[d] = (1LL * hs[r[d]] * pw2[md - lt + 1] + hs[l[d]]) % mod; } int add(int d, int lt, int rt) { int nd = ++dn, md = (lt + rt) >> 1; if (lt == rt) hs[nd] = 1; else { if ((hs[l[d]] + 1) % mod != pw2[md - lt + 1]) { l[nd] = add(l[d], lt, md); r[nd] = r[d]; } else { l[nd] = 0; r[nd] = add(r[d], md + 1, rt); } update(nd, lt, rt); } return nd; } int add(int d, int lt, int rt, int w) { int nd = ++dn, md = (lt + rt) >> 1; if (lt == rt) { if (hs[d]) return 0; else { flag = 1; return hs[nd] = 1, nd; } } if (w <= md) { l[nd] = add(l[d], lt, md, w); if (flag) { r[nd] = r[d]; } else { if ((hs[r[d]] + 1) % mod == pw2[rt - md]) r[nd] = 0; else { flag = 1; r[nd] = add(r[d], md + 1, rt); } } } else { l[nd] = l[d]; r[nd] = add(r[d], md + 1, rt, w); } update(nd, lt, rt); return nd; } void link(int u, int v, int w) { ee[++en] = (edge){v, eq[u], w}, eq[u] = en; } int main() { scanf( %d %d , &n, &m); for (int i = 0; i <= MAXW; ++i) { pw2[i] = !i ? 1 : (pw2[i - 1] * 2) % mod; } for (int i = 1; i <= m; ++i) { int u, v, w; scanf( %d %d %d , &u, &v, &w); link(u, v, w); link(v, u, w); } int s, t; scanf( %d %d , &s, &t); for (int i = 1; i <= n; ++i) { if (i != s) { flag = 0; root[i] = add(root[i], 0, MAXW, MAXW); } Q.push(make_pair(root[i], i)); } while (!Q.empty()) { int u = Q.top().second; Q.pop(); if (done[u]) continue; done[u] = 1; for (int j = eq[u], v; v = ee[j].to, j; j = ee[j].nx) if (!done[v]) { flag = 0; int nt = add(root[u], 0, MAXW, ee[j].w); if (cmp(nt, root[v])) { root[v] = nt; pred[v] = u; ans[v] = (ans[u] + pw2[ee[j].w]) % mod; flag = 0; int nt = add(root[u], 0, MAXW, ee[j].w); Q.push(make_pair(root[v], v)); } } } if (s == t || pred[t]) { printf( %d n , ans[t]); svt = 0; for (int o = t; o; o = pred[o]) sv[++svt] = o; printf( %d n , svt); for (int i = svt; i >= 1; --i) printf( %d , sv[i]); putchar( n ); } else { printf( -1 n ); } }
|
#include <bits/stdc++.h> using namespace std; int main(void) { int t; cin >> t; while (t--) { long long n, g, b; cin >> n >> g >> b; long long t = (n + 1) / 2; long long r = t / g * (g + b); if (t % g == 0) { r -= b; } else { r += t % g; } cout << max(r, n) << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int n, flag = 0; cin >> n; long long int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < (n - 1); i++) { if (a[i] > a[i + 1]) { flag = 0; } else { flag = 1; break; } } if (flag == 0) { cout << NO << endl; } else { cout << YES << endl; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a; scanf( %d%d , &n, &m); if (n == 1) a = 1; else if (m == 1) a = 2; else if (m == n) a = n - 1; else if (m - 1 < n - m) a = m + 1; else a = m - 1; printf( %d , a); return 0; }
|
module peripherals (
input clk,
input nrst,
output reg[31:0] data_out,
input wire[31:0] data_in,
input wire[5:0] addr,
input cs,
input oe,
input[3:0] wstrb,
// PORTA
inout[7:0] porta,
// PORTB
inout[7:0] portb,
// SDCARD
input sdcard_sck,
input sdcard_mosi,
output sdcard_miso,
// UART related
input rxd,
output wire txd,
// TIMER0
output timer0_comp_irq
);
wire [7:0] porta_pinx;
reg [7:0] porta_portx;
reg [7:0] porta_ddrx;
wire [7:0] portb_pinx;
reg [7:0] portb_portx;
reg [7:0] portb_ddrx;
reg [10:0] ser_out = ~0;
reg [8:0] ser_in = ~0;
reg [15:0] ser_tx_cnt = 0;
reg [15:0] ser_rx_cnt = 0;
reg [7:0] ser_rx_data;
reg [15:0] ser_brr;
reg ser_rxc;
reg ser_fe;
reg ser_dor;
reg rxd_s;
assign txd = ser_out[0];
reg ocie0, ocf0;
reg [23:0] tcnt0, ocr0;
assign timer0_comp_irq = ocie0 && ocf0;
tri_buf tri_buf_porta_inst[7:0](.out(porta_portx), .in(porta_pinx),
.en(porta_ddrx), .pin(porta));
tri_buf tri_buf_portb_inst[7:0](
.out ({portb_portx[7:3],
{sdcard_mosi, sdcard_sck},
portb_portx[0]}),
.in (portb_pinx),
.en ({portb_ddrx[7:4], 1'b0, portb_ddrx[2:0]}),
.pin (portb));
assign sdcard_miso = portb_pinx[3];
always @(posedge clk)
if (~nrst) begin
porta_portx <= 8'h00;
porta_ddrx <= 8'h00;
portb_portx <= 8'h00;
portb_ddrx <= 8'h00;
ser_out <= ~0;
ser_in <= ~0;
ser_tx_cnt <= 0;
ser_rx_cnt <= 0;
ser_brr <= 0;
ser_rx_data <= 8'h00;
ser_rxc <= 1'b0;
ser_fe <= 1'b0;
ser_dor <= 1'b0;
rxd_s <= 1'b1;
ocie0 <= 1'b0;
ocf0 <= 1'b0;
tcnt0 <= 0;
ocr0 <= 0;
end else begin
if (ser_tx_cnt == 0) begin
ser_out <= {1'b1,ser_out[10:1]};
ser_tx_cnt <= ser_brr;
end else
ser_tx_cnt <= ser_tx_cnt - 1;
if (ser_rx_cnt == 0) begin
ser_rx_cnt <= ser_brr;
if (!ser_in[0]) begin
ser_rx_data <= ser_in[8:1];
ser_fe <= ~rxd_s;
ser_dor <= ser_rxc;
ser_rxc <= 1'b1;
ser_in <= ~0;
end else
ser_in <= { rxd_s, ser_in[8:1] };
end else if (&ser_in && rxd_s) // if (ser_rx_cnt == 0)
ser_rx_cnt <= ser_brr >> 1;
else
ser_rx_cnt <= ser_rx_cnt - 1;
rxd_s <= rxd;
if(cs && oe && addr == 6'h08) begin
/* UDR0 is read, clear RXC0, FE0, and DOR0 */
ser_rxc <= 1'b0;
ser_fe <= 1'b0;
ser_dor <= 1'b0;
end
if (tcnt0 == ocr0) begin
tcnt0 <= 0;
ocf0 <= 1'b1;
end else
tcnt0 <= tcnt0 + 1;
if(cs && wstrb[0])
case(addr)
6'h00: porta_portx <= data_in[7:0];
6'h02: porta_ddrx <= data_in[7:0];
6'h04: portb_portx <= data_in[7:0];
6'h06: portb_ddrx <= data_in[7:0];
6'h08: ser_out <= {1'b1, data_in[7:0], 1'b0, 1'b1};
6'h0a: ser_brr[7:0] <= data_in[7:0];
6'h0c: tcnt0[7:0] <= data_in[7:0];
6'h0d: ocr0[7:0] <= data_in[7:0];
6'h0e: if (data_in[0]) ocf0 <= 1'b0;
6'h0f: ocie0 <= data_in[0];
endcase; // case (addr)
if(cs && wstrb[1])
case(addr)
6'h0a: ser_brr[15:8] <= data_in[15:8];
6'h0c: tcnt0[15:8] <= data_in[15:8];
6'h0d: ocr0[15:8] <= data_in[15:8];
endcase; // case (addr)
if(cs && wstrb[2])
case(addr)
6'h0c: tcnt0[23:16] <= data_in[23:16];
6'h0d: ocr0[23:16] <= data_in[23:16];
endcase; // case (addr)
end // else: !if(~nrst)
always @(*) begin
data_out = 32'h00000000;
if (nrst && cs && oe)
case(addr)
6'h00: data_out[7:0] = porta_portx;
6'h01: data_out[7:0] = porta_pinx;
6'h02: data_out[7:0] = porta_ddrx;
6'h04: data_out[7:0] = portb_portx;
6'h05: data_out[7:0] = portb_pinx;
6'h06: data_out[7:0] = portb_ddrx;
6'h08: data_out[7:0] = ser_rx_data;
6'h09: data_out[7:0] = {ser_rxc, &ser_out, &ser_out, ser_fe, ser_dor, 3'b000};
6'h0a: data_out[15:0] = ser_brr;
6'h0c: data_out[23:0] = tcnt0;
6'h0d: data_out[23:0] = ocr0;
6'h0e: data_out[0] = ocf0;
6'h0f: data_out[0] = ocie0;
endcase // case (addr)
end
endmodule // peripherals
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Wishbone Single-Port Synchronous RAM ////
//// Memory Model ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
//// ////
//// Description ////
//// This Wishbone controller connects to the wrapper of ////
//// the single-port synchronous memory interface. ////
//// Besides universal memory due to onchip_ram it provides a ////
//// generic way to set the depth of the memory. ////
//// ////
//// To Do: ////
//// ////
//// Author(s): ////
//// - Raul Fajardo, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revision History
//
//
// Revision 1.0 2009/08/18 15:15:00 fajardo
// Created interface and tested
//
`include "timescale.v"
module minsoc_memory_model (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o
);
//
// Parameters
//
parameter adr_width = 2;
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Internal regs and wires
//
wire we;
wire [3:0] be_i;
wire [31:0] wb_dat_o;
reg ack_we;
reg ack_re;
//
// Aliases and simple assignments
//
assign wb_ack_o = ack_re | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
//
// Write acknowledge
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_we <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
ack_we <= #1 1'b1;
else
ack_we <= #1 1'b0;
end
//
// read acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_re <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
ack_re <= #1 1'b1;
else
ack_re <= #1 1'b0;
end
minsoc_onchip_ram #
(
.aw(adr_width)
)
block_ram_0 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[adr_width+1:2]),
.di(wb_dat_i[7:0]),
.doq(wb_dat_o[7:0]),
.we(we),
.oe(1'b1),
.ce(be_i[0]));
minsoc_onchip_ram #
(
.aw(adr_width)
)
block_ram_1 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[adr_width+1:2]),
.di(wb_dat_i[15:8]),
.doq(wb_dat_o[15:8]),
.we(we),
.oe(1'b1),
.ce(be_i[1]));
minsoc_onchip_ram #
(
.aw(adr_width)
)
block_ram_2 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[adr_width+1:2]),
.di(wb_dat_i[23:16]),
.doq(wb_dat_o[23:16]),
.we(we),
.oe(1'b1),
.ce(be_i[2]));
minsoc_onchip_ram #
(
.aw(adr_width)
)
block_ram_3 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[adr_width+1:2]),
.di(wb_dat_i[31:24]),
.doq(wb_dat_o[31:24]),
.we(we),
.oe(1'b1),
.ce(be_i[3]));
endmodule
|
#include <bits/stdc++.h> using namespace std; inline bool equal(double _x, double _y) { return _x > _y - 1e-9 && _x < _y + 1e-9; } char s[300]; int mx, cnt, sum, ans; bool OK(char c) { if (c >= a && c <= z || c >= A && c <= Z ) return 1; return 0; } int main() { int n; scanf( %d , &n); scanf( %s , s); for (int l = 0, r = 0; l < n; l = r) { if (s[l] == ( ) { while (s[r] != ) ) r++; for (int i = l + 1; i < r; i++) { if (OK(s[i]) && !OK(s[i - 1])) { cnt++; } } for (int i = l + 1; i < r; i++) s[i] = _ ; } r++; } for (int i = 0; i < n; i++) { if (OK(s[i])) sum++; else sum = 0; ans = max(ans, sum); } printf( %d %d n , ans, cnt); }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module softusb_ram #(
parameter pmem_width = 12,
parameter dmem_width = 13,
parameter initprog = ""
) (
input sys_clk,
input sys_rst,
input usb_clk,
input usb_rst,
input [31:0] wb_adr_i,
output [31:0] wb_dat_o,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
input wb_we_i,
input pmem_ce,
input [pmem_width-1:0] pmem_a,
output [15:0] pmem_d,
input dmem_we,
input [dmem_width-1:0] dmem_a,
input [7:0] dmem_di,
output reg [7:0] dmem_do
);
always @(posedge sys_clk) begin
if(sys_rst)
wb_ack_o <= 1'b0;
else begin
if(wb_stb_i & wb_cyc_i & ~wb_ack_o)
wb_ack_o <= 1'b1;
else
wb_ack_o <= 1'b0;
end
end
wire [31:0] wb_dat_o_prog;
softusb_dpram #(
.depth(pmem_width),
.width(16),
.initfile(initprog)
) program (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[pmem_width+1:2]),
.we(wb_stb_i & wb_cyc_i & ~wb_adr_i[17] & wb_we_i & ~wb_ack_o),
.di(wb_dat_i[15:0]),
.do(wb_dat_o_prog[15:0]),
.ce2(pmem_ce),
.a2(pmem_a),
.we2(1'b0),
.di2(16'hxxxx),
.do2(pmem_d)
);
assign wb_dat_o_prog[31:16] = 16'd0;
wire [7:0] dmem_do0;
wire [7:0] dmem_do1;
wire [7:0] dmem_do2;
wire [7:0] dmem_do3;
wire [31:0] wb_dat_o_data;
softusb_dpram #(
.depth(dmem_width-2),
.width(8)
) dataram0 (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[dmem_width-1:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[0] & ~wb_ack_o),
.di(wb_dat_i[7:0]),
.do(wb_dat_o_data[7:0]),
.ce2(1'b1),
.a2(dmem_a[dmem_width-1:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd3)),
.di2(dmem_di),
.do2(dmem_do0)
);
softusb_dpram #(
.depth(dmem_width-2),
.width(8)
) dataram1 (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[dmem_width-1:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[1] & ~wb_ack_o),
.di(wb_dat_i[15:8]),
.do(wb_dat_o_data[15:8]),
.ce2(1'b1),
.a2(dmem_a[dmem_width-1:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd2)),
.di2(dmem_di),
.do2(dmem_do1)
);
softusb_dpram #(
.depth(dmem_width-2),
.width(8)
) dataram2 (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[dmem_width-1:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[2] & ~wb_ack_o),
.di(wb_dat_i[23:16]),
.do(wb_dat_o_data[23:16]),
.ce2(1'b1),
.a2(dmem_a[dmem_width-1:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd1)),
.di2(dmem_di),
.do2(dmem_do2)
);
softusb_dpram #(
.depth(dmem_width-2),
.width(8)
) dataram3 (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[dmem_width-1:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[3] & ~wb_ack_o),
.di(wb_dat_i[31:24]),
.do(wb_dat_o_data[31:24]),
.ce2(1'b1),
.a2(dmem_a[dmem_width-1:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd0)),
.di2(dmem_di),
.do2(dmem_do3)
);
reg [1:0] dmem_a01;
always @(posedge usb_clk) dmem_a01 <= dmem_a[1:0];
always @(*) begin
case(dmem_a01)
2'd0: dmem_do = dmem_do3;
2'd1: dmem_do = dmem_do2;
2'd2: dmem_do = dmem_do1;
2'd3: dmem_do = dmem_do0;
endcase
end
reg datasel;
always @(posedge sys_clk) datasel <= wb_adr_i[17];
assign wb_dat_o = datasel ? wb_dat_o_data : wb_dat_o_prog;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MX = 300003; int h[4][4]; bool res[4][MX]; int len; int calc(int i) { if (h[0][i] <= h[0][1]) { int x = h[0][1] - h[0][i]; if ((h[1][i] < x) || (h[1][i] - x) % 2) return -1; int k = (h[1][i] - x) / 2; if (k > h[0][i]) return -1; return h[0][i] - k; } else { int x = h[0][i] - h[0][1]; if (h[1][i] < x || (h[1][i] - x) % 2) return -1; int k = (h[1][i] - x) / 2; if (k > h[0][1]) return -1; return h[0][1] - k; } } bool solve() { for (int j = 0; j < h[0][1]; ++j) res[1][j] = 1; int a = calc(2); int c = calc(3); if (a == -1 || c == -1) return false; int b = h[0][2] - a; int d = h[0][3] - c; int x1, y1; if (a >= c) { x1 = a - c; y1 = a; h[2][3] -= a - c; for (int i = 0; i < a; ++i) res[2][i] = 1; for (int i = a - c; i < a; ++i) res[3][i] = 1; } else { x1 = c - a; y1 = c; h[2][3] -= c - a; for (int i = c - a; i < c; ++i) res[2][i] = 1; for (int i = 0; i < c; ++i) res[3][i] = 1; } int x2, y2; if (b >= d) { x2 = h[0][1] + b - d; y2 = h[0][1] + b; h[2][3] -= b - d; for (int i = h[0][1]; i < h[0][1] + b; ++i) res[2][i] = 1; for (int i = h[0][1] + b - d; i < h[0][1] + b; ++i) res[3][i] = 1; } else { x2 = h[0][1] + d - b; y2 = h[0][1] + d; h[2][3] -= d - b; for (int i = h[0][1] + d - b; i < h[0][1] + d; ++i) res[2][i] = 1; for (int i = h[0][1]; i < h[0][1] + d; ++i) res[3][i] = 1; } if (h[2][3] < 0 || h[2][3] % 2) return false; int py = y1; while (y1 < h[0][1] && x1 < py && h[2][3] > 0) { swap(res[2][x1], res[2][y1]); ++x1; ++y1; h[2][3] -= 2; } len = y2; py = y2; while (x2 < py && h[2][3] > 0) { swap(res[2][x2], res[2][y2]); ++x2; ++y2; ++len; h[2][3] -= 2; } return h[2][3] == 0; } int main() { for (int i = 0; i < 4; ++i) for (int j = i + 1; j < 4; ++j) scanf( %d , h[i] + j); if (solve()) { printf( %d n , len); for (int i = 0; i < 4; ++i) { for (int j = 0; j < len; ++j) printf( %c , a + res[i][j]); printf( n ); } } else puts( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; char str[100005]; int main() { cin.getline(str, 100005); int y = 0; int l = strlen(str); int has = 0; for (int i = 0; i < l; i++) { if (y == 1 && str[i] != ) { cout << str[i]; continue; } if (str[i] == ) { if (y == 0) { y = 1; if (has) { cout << > << endl; has = 0; } cout << < ; } else if (y == 1) { cout << > << endl; y = 0; } continue; } if (str[i] == ) { if (has) { cout << > << endl; has = 0; } continue; } if (has) cout << str[i]; else { has = 1; cout << < << str[i]; } } if (str[l - 1] != && str[l - 1] != ) cout << > << endl; return 0; }
|
/*
* Linear mode graphics for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* VGA FML support
* Copyright (C) 2013 Charley Picker <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_linear_fml (
input clk,
input rst,
input enable,
// CSR slave interface for reading
output [17:1] fml_adr_o,
input [15:0] fml_dat_i,
output fml_stb_o,
input [9:0] h_count,
input [9:0] v_count,
input horiz_sync_i,
input video_on_h_i,
output video_on_h_o,
output [7:0] color,
output horiz_sync_o
);
// Registers
reg [ 9:0] row_addr;
reg [ 6:0] col_addr;
reg [14:1] word_offset;
reg [ 1:0] plane_addr;
reg [ 1:0] plane_addr0;
reg [ 7:0] color_l;
reg [ 15:0] fml1_dat;
reg [ 15:0] fml2_dat;
reg [ 15:0] fml3_dat;
reg [ 15:0] fml4_dat;
reg [ 15:0] fml5_dat;
reg [ 15:0] fml6_dat;
reg [ 15:0] fml7_dat;
reg [4:0] video_on_h;
reg [4:0] horiz_sync;
reg [18:0] pipe;
// Continous assignments
assign fml_adr_o = { 1'b0, word_offset, plane_addr };
assign fml_stb_o = pipe[1];
assign color = pipe[4] ? fml_dat_i[7:0] : color_l;
assign video_on_h_o = video_on_h[4];
assign horiz_sync_o = horiz_sync[4];
// Behaviour
// FML 8x16 pipeline count
always @(posedge clk)
if (rst)
begin
pipe <= 18'b0;
end
else
if (enable)
begin
pipe <= { pipe[17:0], (h_count[3:0]==4'h0) };
end
// Load FML 8x16 burst
always @(posedge clk)
if (enable)
begin
fml1_dat <= pipe[5] ? fml_dat_i[15:0] : fml1_dat;
fml2_dat <= pipe[6] ? fml_dat_i[15:0] : fml2_dat;
fml3_dat <= pipe[7] ? fml_dat_i[15:0] : fml3_dat;
fml4_dat <= pipe[8] ? fml_dat_i[15:0] : fml4_dat;
fml5_dat <= pipe[9] ? fml_dat_i[15:0] : fml5_dat;
fml6_dat <= pipe[10] ? fml_dat_i[15:0] : fml6_dat;
fml7_dat <= pipe[11] ? fml_dat_i[15:0] : fml7_dat;
end
// video_on_h
always @(posedge clk)
if (rst)
begin
video_on_h <= 5'b0;
end
else
if (enable)
begin
video_on_h <= { video_on_h[3:0], video_on_h_i };
end
// horiz_sync
always @(posedge clk)
if (rst)
begin
horiz_sync <= 5'b0;
end
else
if (enable)
begin
horiz_sync <= { horiz_sync[3:0], horiz_sync_i };
end
// Address generation
always @(posedge clk)
if (rst)
begin
row_addr <= 10'h0;
col_addr <= 7'h0;
plane_addr0 <= 2'b00;
word_offset <= 14'h0;
plane_addr <= 2'b00;
end
else
if (enable)
begin
// Loading new row_addr and col_addr when h_count[3:0]==4'h0
// v_count * 5 * 32
row_addr <= { v_count[8:1], 2'b00 } + v_count[8:1];
col_addr <= h_count[9:3];
plane_addr0 <= h_count[2:1];
word_offset <= { row_addr + col_addr[6:4], col_addr[3:0] };
plane_addr <= plane_addr0;
end
// color_l
always @(posedge clk)
if (rst)
begin
color_l <= 8'h0;
end
else
if (enable)
begin
if (pipe[4])
color_l <= fml_dat_i[7:0];
else
if (pipe[5])
color_l <= fml_dat_i[7:0];
else
if (pipe[7])
color_l <= fml2_dat[7:0];
else
if (pipe[9])
color_l <= fml3_dat[7:0];
else
if (pipe[11])
color_l <= fml4_dat[7:0];
else
if (pipe[13])
color_l <= fml5_dat[7:0];
else
if (pipe[15])
color_l <= fml6_dat[7:0];
else
if (pipe[17])
color_l <= fml7_dat[7:0];
end
endmodule
|
`include "defines.v"
module brouter
#(parameter addr = 4'b0101)
(
input `control_w port0_ci,
input `control_w port1_ci,
input `control_w port2_ci,
input `control_w port3_ci,
input `control_w port4_ci,
input `data_w port0_di,
input `data_w port1_di,
input `data_w port2_di,
input `data_w port3_di,
input `data_w port4_di,
input clk,
input rst,
output `control_w port0_co,
output `control_w port1_co,
output `control_w port2_co,
output `control_w port3_co,
output `control_w port4_co,
output `data_w port0_do,
output `data_w port1_do,
output `data_w port2_do,
output `data_w port3_do,
output `data_w port4_do,
output port4_ready);
// Config
wire `addrx_w addrx, max_addrx;
wire `addry_w addry, max_addry;
assign addrx = addr[`addrx_f]; // This nodes x address
assign addry = addr[`addry_f]; // This nodes y address
assign max_addrx = `addrx_max;
assign max_addry = `addry_max;
// Input wires for reset
wire `control_w port0_cin, port1_cin, port2_cin, port3_cin, port4_cin;
assign port0_cin = (rst) ? `control_n'd0 : port0_ci;
assign port1_cin = (rst) ? `control_n'd0 : port1_ci;
assign port2_cin = (rst) ? `control_n'd0 : port2_ci;
assign port3_cin = (rst) ? `control_n'd0 : port3_ci;
assign port4_cin = (rst) ? `control_n'd0 : port4_ci;
// Resource Ready Wires
wire all_valid;
wire resource_go0, resource_go1, resource_go2, resource_go3;
// Cross Stage Wires
reg `control_w port0_c1, port1_c1, port2_c1, port3_c1, port4_c1;
reg `data_w port0_d1, port1_d1, port2_d1, port3_d1, port4_d1;
wire `control_w port0_c2, port1_c2, port2_c2, port3_c2, port4_c2;
reg `data_w port0_d2, port1_d2, port2_d2, port3_d2, port4_d2;
// Routing Matrices
wire `rmatrix_w rmatrix0, rmatrix1, rmatrix2, rmatrix3, rmatrix4;
reg `rmatrix_w rmatrix0_r, rmatrix1_r, rmatrix2_r, rmatrix3_r, rmatrix4_r;
// Final Route
wire `routecfg_w route_config;
/************* STAGE 1 *************/
// Route Computation
RouteCompute rc0(.control_in(port0_cin),
.addrx(addrx),
.addry(addry),
.addrx_max(max_addrx),
.addry_max(max_addry),
.clk(clk),
.rst(rst),
.resource_go(resource_go0),
.rmatrix(rmatrix0));
RouteCompute rc1(.control_in(port1_cin),
.addrx(addrx),
.addry(addry),
.addrx_max(max_addrx),
.addry_max(max_addry),
.clk(clk),
.rst(rst),
.resource_go(resource_go1),
.rmatrix(rmatrix1));
RouteCompute rc2(.control_in(port2_cin),
.addrx(addrx),
.addry(addry),
.addrx_max(max_addrx),
.addry_max(max_addry),
.clk(clk),
.rst(rst),
.resource_go(resource_go2),
.rmatrix(rmatrix2));
RouteCompute rc3(.control_in(port3_cin),
.addrx(addrx),
.addry(addry),
.addrx_max(max_addrx),
.addry_max(max_addry),
.clk(clk),
.rst(rst),
.resource_go(resource_go3),
.rmatrix(rmatrix3));
RouteCompute rc4(.control_in(port4_cin),
.addrx(addrx),
.addry(addry),
.addrx_max(max_addrx),
.addry_max(max_addry),
.clk(clk),
.rst(rst),
.resource_go(),
.rmatrix(rmatrix4));
// Registers for the data/control for the first stage
always @ (posedge clk) begin
port0_c1 <= port0_cin;
port1_c1 <= port1_cin;
port2_c1 <= port2_cin;
port3_c1 <= port3_cin;
port4_c1 <= port4_cin;
port0_d1 <= port0_di;
port1_d1 <= port1_di;
port2_d1 <= port2_di;
port3_d1 <= port3_di;
port4_d1 <= port4_di;
$display("RC in: %04x %04x %04x %04x", port0_cin, port1_cin, port2_cin, port3_cin);
$display("RC out: %04x %04x %04x %04x", rmatrix0, rmatrix1, rmatrix2, rmatrix3);
rmatrix0_r <= rmatrix0;
rmatrix1_r <= rmatrix1;
rmatrix2_r <= rmatrix2;
rmatrix3_r <= rmatrix3;
rmatrix4_r <= rmatrix4;
end
// Let the resource know stuff is incoming
assign all_valid = port0_cin[`valid_f] &
port1_cin[`valid_f] &
port2_cin[`valid_f] &
port3_cin[`valid_f];
assign port4_ready = ~(all_valid) |
resource_go0 |
resource_go1 |
resource_go2 |
resource_go3;
/******** Stage 2 ********/
arbitor arb(.rmatrix0(rmatrix0_r),
.rmatrix1(rmatrix1_r),
.rmatrix2(rmatrix2_r),
.rmatrix3(rmatrix3_r),
.rmatrix4(rmatrix4_r),
.control0_in(port0_c1),
.control1_in(port1_c1),
.control2_in(port2_c1),
.control3_in(port3_c1),
.control4_in(port4_c1),
.clk(clk),
.rst(rst),
.control0_out(port0_c2),
.control1_out(port1_c2),
.control2_out(port2_c2),
.control3_out(port3_c2),
.control4_out(port4_c2),
.route_config(route_config));
// Registers for data/control for stage 2
always @ (posedge clk) begin
port0_d2 <= port0_d1;
port1_d2 <= port1_d1;
port2_d2 <= port2_d1;
port3_d2 <= port3_d1;
port4_d2 <= port4_d1;
$display("ARB out: %04x %04x %04x %04x (route %x)", port0_c2, port1_c2, port2_c2, port3_c2, route_config);
end
/*********** Stage 3 **********/
crossbar xbar(.control0_in(port0_c2),
.control1_in(port1_c2),
.control2_in(port2_c2),
.control3_in(port3_c2),
.control4_in(port4_c2),
.data0_in(port0_d2),
.data1_in(port1_d2),
.data2_in(port2_d2),
.data3_in(port3_d2),
.data4_in(port4_d2),
.route_config(route_config),
.clk(clk),
.rst(rst),
.control0_out(port0_co),
.control1_out(port1_co),
.control2_out(port2_co),
.control3_out(port3_co),
.control4_out(port4_co),
.data0_out(port0_do),
.data1_out(port1_do),
.data2_out(port2_do),
.data3_out(port3_do),
.data4_out(port4_do));
endmodule
|
#include <bits/stdc++.h> using namespace std; const signed long long llf = (signed long long)(~0ull >> 1); const signed int inf = (signed)(~0u >> 1); template <typename T> T __abs(T x) { return (x < 0) ? (-x) : (x); } template <typename T> void pfill(T* pst, const T* ped, T val) { for (; pst != ped; *(pst++) = val) ; } template <typename T> void pcopy(T* pst, const T* ped, T* pv) { for (; pst != ped; *(pst++) = *(pv++)) ; } typedef class Edge { public: int ed, nx, cap, f; Edge() {} Edge(int ed, int nx, int cap, int f) : ed(ed), nx(nx), cap(cap), f(f) {} } Edge; typedef class MapManager { public: int* h; vector<Edge> es; MapManager() {} MapManager(int n) { h = new int[(n + 1)]; pfill(h, h + n + 1, -1); } void addEdge(int u, int v, int cap, int f) { es.push_back(Edge(v, h[u], cap, f)); h[u] = (signed)es.size() - 1; } void addArc(int u, int v, int cap) { addEdge(u, v, cap, 0); addEdge(v, u, cap, cap); } Edge& operator[](int p) { return es[p]; } void clear() { delete[] h; es.clear(); } } MapManager; const int N = 605; int n, m, K; int s = 0, t; int mxcap; int deg[N]; MapManager g; inline void init() { scanf( %d%d%d , &n, &m, &K); pfill(deg, deg + n + 1, 0); g = MapManager(n + m + 1); for (int i = 1, u, v; i <= m; i++) { scanf( %d%d , &u, &v); deg[u]++, deg[v]++; g.addArc(0, i, 1); g.addArc(i, u + m, 1); g.addArc(i, v + m, 1); } t = n + m + 1, mxcap = 0; for (int i = 1; i <= n; i++) if (deg[i] > K) g.addArc(i + m, t, (deg[i] - K) << 1), mxcap += deg[i] - K; mxcap <<= 1; } int cur[N << 1], _div[N << 1]; int dfs(int p, int mf) { if (p == t || !mf) return mf; int f, flow = 0; for (int &i = cur[p], e; ~i; i = g[i].nx) { e = g[i].ed; if (g[i].f < g[i].cap && _div[e] == _div[p] + 1 && (f = dfs(e, min(mf, g[i].cap - g[i].f))) > 0) { g[i].f += f; g[i ^ 1].f -= f; mf -= f; flow += f; if (!mf) break; } } return flow; } queue<int> que; bool bfs() { pfill(_div, _div + t + 1, -1); _div[s] = 0; que.push(s); while (!que.empty()) { int e = que.front(); que.pop(); for (int i = g.h[e], eu; ~i; i = g[i].nx) { eu = g[i].ed; if (g[i].cap == g[i].f) continue; if (~_div[eu]) continue; _div[eu] = _div[e] + 1; que.push(eu); } } return _div[t] != -1; } int dinic() { int rt = 0; while (bfs()) { pcopy(cur, cur + t + 1, g.h); rt += dfs(s, inf); } return rt; } int lab[N]; vector<int> mat[N]; inline void solve() { int flow = dinic(), used = 0; if (flow != mxcap) { for (int i = 1; i <= m; i++) printf( 0 ); putchar( n ); return; } for (int i = 1; i <= n; i++) mat[i].clear(); for (int i = 1; i <= m; i++) for (int j = g.h[i]; ~j; j = g[j].nx) if (g[j].cap == g[j].f && g[j].ed > m) { mat[g[j].ed - m].push_back(i); break; } pfill(lab + 1, lab + m + 1, 0); for (int i = 1, a, b; i <= n; i++) while (!mat[i].empty()) { a = mat[i].back(); mat[i].pop_back(); b = mat[i].back(); mat[i].pop_back(); lab[a] = lab[b] = ++used; } for (int i = 1; i <= m; i++) { if (!lab[i]) lab[i] = ++used; printf( %d , lab[i]); } putchar( n ); } inline void clear() { g.clear(); } int T; int main() { scanf( %d , &T); while (T--) { init(); solve(); clear(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2AI_BLACKBOX_V
`define SKY130_FD_SC_HD__O2BB2AI_BLACKBOX_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2AI_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_r_rf16x128d.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
// 16 X 128 R1 W1 RF macro with decoded wordlines.
// REad/Write ports can be accessed in PH1 only.
////////////////////////////////////////////////////////////////////////
module bw_r_rf16x128d(/*AUTOARG*/
// Outputs
dout, so,
// Inputs
din, rd_wl, wr_wl, read_en, wr_en, rst_tri_en, rclk, se, si,
reset_l, sehold
);
input [127:0] din; // data input
input [15:0] rd_wl; // read addr
input [15:0] wr_wl; // write addr
input read_en;
input wr_en; // used in conjunction with
// word_wen and byte_wen
input rst_tri_en ; // gates off writes during SCAN.
input rclk;
input se, si ;
input reset_l;
input sehold; // hold scan in data.
output [127:0] dout;
output so;
reg [127:0] dout;
// memory array
reg [127:0] inq_ary [15:0];
// internal variable
integer i;
reg [127:0] temp, data_in;
reg [3:0] rdptr_d1, wrptr_d1;
wire [160:0] scan_out;
reg [127:0] wrdata_d1 ;
reg ren_d1;
reg wr_en_d1;
reg [15:0] rd_wl_d1, wr_wl_d1;
reg rst_tri_en_d1;
always @(posedge rclk ) begin
wrdata_d1 <= ( sehold)? wrdata_d1 : din;
wr_en_d1 <= ( sehold)? wr_en_d1 : wr_en ;
wr_wl_d1 <= (sehold) ? wr_wl_d1 : wr_wl ;
ren_d1 <= (sehold)? ren_d1 : read_en;
rd_wl_d1 <= (sehold) ? rd_wl_d1 : rd_wl ;
rst_tri_en_d1 <= rst_tri_en ; // not a real flop ( only used as a trigger ). Works only for accesses made in PH1
end
//////////////////////////////////////////////////////////////////////
// Read Operation
//////////////////////////////////////////////////////////////////////
always @(/*AUTOSENSE*/ /*memory or*/ rd_wl_d1 or ren_d1 or reset_l
or rst_tri_en_d1 or wr_en_d1 or wr_wl_d1)
begin
if (reset_l)
begin
// ---- \/ added the rst_tri_en qual on 11/11 \/------
if (ren_d1)
begin
case(rd_wl_d1 & {16{~rst_tri_en}})
16'b0000_0000_0000_0000: ; // do nothing.
16'b0000_0000_0000_0001: rdptr_d1 = 4'b0000;
16'b0000_0000_0000_0010: rdptr_d1 = 4'b0001;
16'b0000_0000_0000_0100: rdptr_d1 = 4'b0010;
16'b0000_0000_0000_1000: rdptr_d1 = 4'b0011;
16'b0000_0000_0001_0000: rdptr_d1 = 4'b0100;
16'b0000_0000_0010_0000: rdptr_d1 = 4'b0101;
16'b0000_0000_0100_0000: rdptr_d1 = 4'b0110;
16'b0000_0000_1000_0000: rdptr_d1 = 4'b0111;
16'b0000_0001_0000_0000: rdptr_d1 = 4'b1000;
16'b0000_0010_0000_0000: rdptr_d1 = 4'b1001;
16'b0000_0100_0000_0000: rdptr_d1 = 4'b1010;
16'b0000_1000_0000_0000: rdptr_d1 = 4'b1011;
16'b0001_0000_0000_0000: rdptr_d1 = 4'b1100;
16'b0010_0000_0000_0000: rdptr_d1 = 4'b1101;
16'b0100_0000_0000_0000: rdptr_d1 = 4'b1110;
16'b1000_0000_0000_0000: rdptr_d1 = 4'b1111;
default: rdptr_d1 = 4'bx ;
endcase
`ifdef INNO_MUXEX
`else
// Checking for Xs on the rd pointer input when read is enabled
if(rdptr_d1 == 4'bx) begin
`ifdef MODELSIM
$display("rf_error"," read pointer error %h ", rdptr_d1[3:0]);
`else
$error("rf_error"," read pointer error %h ", rdptr_d1[3:0]);
`endif
end
`endif
if(rst_tri_en_d1) begin // special case
dout[127:0] = 128'hFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF ;
end
// RW -conflict case and the case where all wlines are zero
else if ((( wr_en_d1 & ~rst_tri_en ) && (rd_wl_d1 == wr_wl_d1))||
((rd_wl_d1 & {16{~rst_tri_en}}) == 16'b0 )) begin
dout[127:0] = 128'bx ;
end
else dout = inq_ary[rdptr_d1];
end // of if rd_en
end // if reset_l
else dout = 128'b0 ;
end // always @ (...
//////////////////////////////////////////////////////////////////////
// Write Operation
//////////////////////////////////////////////////////////////////////
always @ (/*AUTOSENSE*/reset_l or rst_tri_en_d1 or wr_en_d1
or wr_wl_d1 or wrdata_d1)
begin
if ( reset_l) begin
`ifdef INNO_MUXEX
if(wr_en_d1==1'bx) begin
// do nothing
end
`else
if(wr_en_d1==1'bx) begin
`ifdef MODELSIM
$display("rf_error"," write enable error %b ", wr_en_d1);
`else
$error("rf_error"," write enable error %b ", wr_en_d1);
`endif
end
`endif
else if(wr_en_d1 & ~rst_tri_en ) begin
case(wr_wl_d1)
16'b0000_0000_0000_0000: ; // do nothing.
16'b0000_0000_0000_0001: wrptr_d1 = 4'b0000;
16'b0000_0000_0000_0010: wrptr_d1 = 4'b0001;
16'b0000_0000_0000_0100: wrptr_d1 = 4'b0010;
16'b0000_0000_0000_1000: wrptr_d1 = 4'b0011;
16'b0000_0000_0001_0000: wrptr_d1 = 4'b0100;
16'b0000_0000_0010_0000: wrptr_d1 = 4'b0101;
16'b0000_0000_0100_0000: wrptr_d1 = 4'b0110;
16'b0000_0000_1000_0000: wrptr_d1 = 4'b0111;
16'b0000_0001_0000_0000: wrptr_d1 = 4'b1000;
16'b0000_0010_0000_0000: wrptr_d1 = 4'b1001;
16'b0000_0100_0000_0000: wrptr_d1 = 4'b1010;
16'b0000_1000_0000_0000: wrptr_d1 = 4'b1011;
16'b0001_0000_0000_0000: wrptr_d1 = 4'b1100;
16'b0010_0000_0000_0000: wrptr_d1 = 4'b1101;
16'b0100_0000_0000_0000: wrptr_d1 = 4'b1110;
16'b1000_0000_0000_0000: wrptr_d1 = 4'b1111;
default: wrptr_d1= 4'bx ;
endcase
`ifdef INNO_MUXEX
if(wr_wl_d1!=16'b0)
inq_ary[wrptr_d1] = wrdata_d1 ;
`else
if(wrptr_d1 == 4'bx) begin
`ifdef MODELSIM
$display("rf_error"," write pointer error %h ", wrptr_d1[3:0]);
`else
$error("rf_error"," write pointer error %h ", wrptr_d1[3:0]);
`endif
end
else begin
if(wr_wl_d1!=16'b0)
inq_ary[wrptr_d1] = wrdata_d1 ;
end
`endif
end
else begin
// do nothing
end
end // of if reset_l
end // always @ (...
endmodule // rf_16x128d
|
module ghrd_10as066n2_avlmm_pr_freeze_bridge_0 (
input wire clock, // clock.clk
input wire freeze_conduit_freeze, // freeze_conduit.freeze
output wire freeze_conduit_illegal_request, // .illegal_request
input wire reset_n, // reset_n.reset_n
output wire slv_bridge_to_pr_read, // slv_bridge_to_pr.read
input wire slv_bridge_to_pr_waitrequest, // .waitrequest
output wire slv_bridge_to_pr_write, // .write
output wire [9:0] slv_bridge_to_pr_address, // .address
output wire [3:0] slv_bridge_to_pr_byteenable, // .byteenable
output wire [31:0] slv_bridge_to_pr_writedata, // .writedata
input wire [31:0] slv_bridge_to_pr_readdata, // .readdata
output wire [2:0] slv_bridge_to_pr_burstcount, // .burstcount
input wire slv_bridge_to_pr_readdatavalid, // .readdatavalid
output wire slv_bridge_to_pr_beginbursttransfer, // .beginbursttransfer
output wire slv_bridge_to_pr_debugaccess, // .debugaccess
input wire [1:0] slv_bridge_to_pr_response, // .response
output wire slv_bridge_to_pr_lock, // .lock
input wire slv_bridge_to_pr_writeresponsevalid, // .writeresponsevalid
input wire slv_bridge_to_sr_read, // slv_bridge_to_sr.read
output wire slv_bridge_to_sr_waitrequest, // .waitrequest
input wire slv_bridge_to_sr_write, // .write
input wire [9:0] slv_bridge_to_sr_address, // .address
input wire [3:0] slv_bridge_to_sr_byteenable, // .byteenable
input wire [31:0] slv_bridge_to_sr_writedata, // .writedata
output wire [31:0] slv_bridge_to_sr_readdata, // .readdata
input wire [2:0] slv_bridge_to_sr_burstcount, // .burstcount
output wire slv_bridge_to_sr_readdatavalid, // .readdatavalid
input wire slv_bridge_to_sr_beginbursttransfer, // .beginbursttransfer
input wire slv_bridge_to_sr_debugaccess, // .debugaccess
output wire [1:0] slv_bridge_to_sr_response, // .response
input wire slv_bridge_to_sr_lock, // .lock
output wire slv_bridge_to_sr_writeresponsevalid // .writeresponsevalid
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; long long INF = 1e7; double EPS = 1e-12; double tick() { static clock_t oldt; clock_t newt = clock(); double diff = 1.0 * (newt - oldt) / CLOCKS_PER_SEC; oldt = newt; return diff; } long long int powP(long long int a, long long int b) { if (b == 0) return 1 % mod; long long int k; k = powP(a, b / 2); k = k * k % mod; if (b % 2 == 0) return k; else return a * k % mod; } bool bitSet(long long int n, long long int i) { if ((n & (1LL << i)) != 0) return true; else return false; } long long int findGcd(long long int a, long long int b) { if (a == 0) return b; else return findGcd(b % a, a); } long long int A[700005], B[700005], C[700005]; int main() { long long int T, i, n, m, p, j, l, e, r, b, c, k, q, a, d, w, x, y, v, z, t, curr, prev, sum, ans, pos, val, countA, secondMin, indicator; scanf( %lld , &n); stack<int> S; ans = 0; S.push(0); B[0] = INT_MAX; for (long long int i = (1); i <= (n); ++i) { scanf( %lld , &A[i]); B[i] = 1; while (!S.empty() && A[i] > A[S.top()]) { B[i] = max(B[i], B[S.top()] + 1); S.pop(); } if (B[i] < INT_MAX) ans = max(ans, B[i]); S.push(i); } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, p, num, mi = 1000000, ma = 0, ans = 1; cin >> n >> p; vector<long long> v, res; for (long long i = 0; i < n; i++) { cin >> num; v.push_back(num); mi = min(mi, num); ma = max(ma, num); } sort(v.begin(), v.end()); for (long long i = mi; i <= ma; i++) { ans = 1; for (long long j = 0; j < n; j++) { auto it = upper_bound(v.begin(), v.end(), i + j); it--; ans *= (distance(v.begin(), it) + 1 - j); ans = ans % p; } if (ans) { if (ans % p != 0) res.push_back(i); } } cout << res.size() << endl; for (long long i = 0; i < res.size(); i++) cout << res[i] << ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLSTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SRDLSTP_BEHAVIORAL_V
/**
* srdlstp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_psa_pp_pkg_sn/sky130_fd_sc_lp__udp_dlatch_psa_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srdlstp (
Q ,
SET_B ,
D ,
GATE ,
SLEEP_B
);
// Module ports
output Q ;
input SET_B ;
input D ;
input GATE ;
input SLEEP_B;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire reset_delayed;
wire SET_B_delayed;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$PSa_pp$PKG$sN dlatch0 (buf_Q , D_delayed, GATE_delayed, SET_B_delayed, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( SLEEP_B === 1'b1 );
assign cond0 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B === 1'b1 ) );
bufif1 bufif10 (Q , buf_Q, VPWR );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLSTP_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_4_V
`define SKY130_FD_SC_LP__O2BB2A_4_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2a_4 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2a_4 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int arr[100000 + 1]; int n, a; set<int> s; cin >> n; vector<bool> vst(n, false); for (int i = 0; i < n; ++i) { cin >> a; arr[i] = a; s.insert(a); } int k = 1; if (n != 1) for (int i = 0; i < n; ++i) { int j = arr[i]; if (!vst[j] && j <= n) { vst[j] = 1; cout << j << ; } else { while (s.count(k) || vst[k]) { k++; } vst[k] = true; cout << k << ; k++; } } else cout << 1 ; }
|
`include "../include/tune.v"
module resetter(
clk,
rst_in_n,
rst_out_n );
parameter RST_CNT_SIZE = 4;
input clk;
input rst_in_n; // input of external asynchronous reset
output rst_out_n; // output of end-synchronized reset (beginning is asynchronous to clock)
reg rst_out_n;
reg [RST_CNT_SIZE:0] rst_cnt; // one bit more for counter stopping
reg rst1_n,rst2_n;
`ifdef SIMULATE
initial
begin
rst_cnt = 0;
rst1_n = 1'b0;
rst2_n = 1'b0;
rst_out_n = 1'b0;
end
`endif
always @(posedge clk, negedge rst_in_n)
if( !rst_in_n ) // external asynchronous reset
begin
rst_cnt <= 0;
rst1_n <= 1'b0;
rst2_n <= 1'b0;
rst_out_n <= 1'b0; // this zeroing also happens after FPGA configuration, so also power-up reset happens
end
else // clocking
begin
rst1_n <= 1'b1;
rst2_n <= rst1_n;
if( rst2_n && !rst_cnt[RST_CNT_SIZE] )
begin
rst_cnt <= rst_cnt + 1;
end
if( rst_cnt[RST_CNT_SIZE] )
begin
rst_out_n <= 1'b1;
end
end
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SoC_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N (
Q ,
D ,
GATE ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; struct node { int a[2][2]; node() { a[0][0] = a[0][1] = a[1][0] = a[1][1] = 0; } int *operator[](const size_t &s) { return a[s]; } }; node segTree[400008], L[400008]; node id, M, zero; int a[100002]; int lazy[400008]; inline node operator+(node &a, node &b) { node res; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) res[i][j] = (a[i][j] + b[i][j]) % 1000000007; return res; } inline node operator*(node &a, node &b) { node res; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) for (int k = 0; k < 2; k++) res[i][j] = (res[i][j] + (1ll * a[i][k] * b[k][j]) % 1000000007) % 1000000007; return res; } inline node matPower(int n) { node res = id; node m = M; while (n > 0) { if (n & 1) res = res * m; m = m * m; n >>= 1; } return res; } inline void buildTree(int v, int s, int e) { L[v] = id; lazy[v] = 0; if (s == e) { segTree[v] = matPower(a[s]); return; } int m = (s + e) / 2; buildTree(2 * v, s, m); buildTree(2 * v + 1, m + 1, e); segTree[v] = segTree[2 * v] + segTree[2 * v + 1]; } inline void propogate(int v, int l, int r) { if (lazy[v] > 0) { segTree[v] = segTree[v] * L[v]; if (l != r) { lazy[2 * v] = lazy[2 * v + 1] = 1; L[2 * v] = L[2 * v] * L[v]; L[2 * v + 1] = L[2 * v + 1] * L[v]; } lazy[v] = 0; L[v] = id; } return; } inline void update(int v, int tl, int tr, int l, int r, node x) { propogate(v, tl, tr); if (l > r) return; if (tl == l && tr == r) { lazy[v] = 1; L[v] = x; propogate(v, tl, tr); return; } int tm = (tl + tr) / 2; update(2 * v, tl, tm, l, min(tm, r), x); update(2 * v + 1, tm + 1, tr, max(l, tm + 1), r, x); segTree[v] = segTree[2 * v] + segTree[2 * v + 1]; } inline node query(int v, int tl, int tr, int l, int r) { propogate(v, tl, tr); if (l > r) return zero; if (tl == l && tr == r) return segTree[v]; int tm = (tl + tr) / 2; node left = query(2 * v, tl, tm, l, min(tm, r)); node right = query(2 * v + 1, tm + 1, tr, max(l, tm + 1), r); return (left + right); } int main() { id[0][0] = id[1][1] = 1; M[0][0] = M[0][1] = M[1][0] = 1; ios::sync_with_stdio(false); int n, m, q, l, r, x; cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; buildTree(1, 0, n - 1); while (m--) { cin >> q; if (q == 1) { cin >> l >> r >> x; node val = matPower(x); update(1, 0, n - 1, l - 1, r - 1, val); } else { cin >> l >> r; cout << query(1, 0, n - 1, l - 1, r - 1)[0][1] << endl; } } return 0; }
|
`include "./logic_macro.sim.v"
`include "./c_frag_modes.sim.v"
`include "./q_frag_modes.sim.v"
`include "./f_frag.sim.v"
(* FASM_FEATURES="LOGIC.LOGIC.Ipwr_gates.J_pwr_st" *)
(* MODES="MACRO;FRAGS" *)
module LOGIC (QST, QDS, TBS, TAB, TSL, TA1, TA2, TB1, TB2, BAB, BSL, BA1, BA2, BB1, BB2, QDI, QEN, QCK, QRT, F1, F2, FS, TZ, CZ, QZ, FZ, FAKE_CONST);
input wire QST;
input wire QDS;
input wire TBS;
input wire TAB;
input wire TSL;
input wire TA1;
input wire TA2;
input wire TB1;
input wire TB2;
input wire BAB;
input wire BSL;
input wire BA1;
input wire BA2;
input wire BB1;
input wire BB2;
input wire QDI;
input wire QEN;
input wire QCK;
input wire QRT;
input wire F1;
input wire F2;
input wire FS;
output wire TZ;
output wire CZ;
output wire QZ;
output wire FZ;
// This is a synthetic pin that can be connected to the global const
// network bypassing the switchbox.
input wire FAKE_CONST;
parameter MODE = "MACRO";
// LOGIC macro
generate if (MODE == "MACRO") begin
(* FASM_PREFIX="LOGIC.LOGIC" *)
LOGIC_MACRO logic_macro (
.TBS(TBS),
.TAB(TAB),
.TSL(TSL),
.TA1(TA1),
.TA2(TA2),
.TB1(TB1),
.TB2(TB2),
.BAB(BAB),
.BSL(BSL),
.BA1(BA1),
.BA2(BA2),
.BB1(BB1),
.BB2(BB2),
.TZ (TZ),
.CZ (CZ),
.QCK(QCK),
.QST(QST),
.QRT(QRT),
.QEN(QEN),
.QDI(QDI),
.QDS(QDS),
.QZ (QZ),
.F1 (F1),
.F2 (F2),
.FS (FS),
.FZ (FZ)
);
// LOGIC split into fragments
end else if (MODE == "FRAGS") begin
// The C-Frag (with modes)
(* FASM_PREFIX="LOGIC.LOGIC" *)
C_FRAG_MODES c_frag_modes (
.TBS(TBS),
.TAB(TAB),
.TSL(TSL),
.TA1(TA1),
.TA2(TA2),
.TB1(TB1),
.TB2(TB2),
.BAB(BAB),
.BSL(BSL),
.BA1(BA1),
.BA2(BA2),
.BB1(BB1),
.BB2(BB2),
.TZ (TZ),
.CZ (CZ)
);
// The Q-Frag (with modes)
(* FASM_PREFIX="LOGIC.LOGIC" *)
Q_FRAG_MODES q_frag_modes (
.QCK(QCK),
.QST(QST),
.QRT(QRT),
.QEN(QEN),
.QDI(QDI),
.QDS(QDS),
.CZI(CZ),
.QZ (QZ),
.FAKE_CONST (FAKE_CONST)
);
// The F-Frag
F_FRAG f_frag (
.F1 (F1),
.F2 (F2),
.FS (FS),
.FZ (FZ)
);
end endgenerate
endmodule
|
/*
Copyright (C) {2014} {Ganesh Ajjanagadde} <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
///////////////////////////////////////////////////////////////////////////////////////////////////
// move_cursor: This module implements a simple UI for manually adjusting the
// projector correction via pressing the arrow keys, and selecting which
// corner of the quadrilateral the user is manipulating via switch[1:0] positions.
// 00 -> point 1, 01 -> point 2, 10 -> point 3, 11 -> point 4
// All the adjustments can only happen when the override is pressed.
// Inputs are xi_raw, yi_raw (obtained from accelerometer lut)
// Outputs are xi, yi and display_x, display_y (for hex display).
// The intention is to run this on a slow clk, even vsync could be a little
// too fast
///////////////////////////////////////////////////////////////////////////////////////////////////
module move_cursor(input clk,
input up,
input down,
input left,
input right,
input override,
input[1:0] switch,
input[9:0] x1_raw,
input[8:0] y1_raw,
input[9:0] x2_raw,
input[8:0] y2_raw,
input[9:0] x3_raw,
input[8:0] y3_raw,
input[9:0] x4_raw,
input[8:0] y4_raw,
output reg[9:0] x1,
output reg[8:0] y1,
output reg[9:0] x2,
output reg[8:0] y2,
output reg[9:0] x3,
output reg[8:0] y3,
output reg[9:0] x4,
output reg[8:0] y4,
output reg[9:0] display_x,
output reg[8:0] display_y);
parameter OVERRIDE = 1'b0;
parameter XSPEED = 1'd1;
parameter YSPEED = 1'd1;
// 640 x 480 screen
parameter SCR_WIDTH = 10'd639;
parameter SCR_HEIGHT = 9'd479;
reg cur_state = ~OVERRIDE;
always @(posedge clk) begin
case (switch)
2'b00: begin
display_x <= x1;
display_y <= y1;
end
2'b01: begin
display_x <= x2;
display_y <= y2;
end
2'b10: begin
display_x <= x3;
display_y <= y3;
end
2'b11: begin
display_x <= x4;
display_y <= y4;
end
endcase
end
always @(posedge clk) begin
if (override && !(cur_state == OVERRIDE)) begin
cur_state <= OVERRIDE;
x1 <= x1_raw;
y1 <= y1_raw;
x2 <= x2_raw;
y2 <= y2_raw;
x3 <= x3_raw;
y3 <= y3_raw;
x4 <= x4_raw;
y4 <= y4_raw;
end
else if (override) begin
case (switch)
2'b00: begin
if (down) begin
y1 <= (y1 <= SCR_HEIGHT-YSPEED) ? (y1 + YSPEED) : y1;
end
else if (up) begin
y1 <= (y1 >= YSPEED) ? (y1 - YSPEED) : y1;
end
else if (left) begin
x1 <= (x1 >= XSPEED) ? (x1 - XSPEED) : x1;
end
else if (right) begin
x1 <= (x1 <= SCR_WIDTH-XSPEED) ? (x1 + XSPEED) : x1;
end
end
2'b01: begin
if (down) begin
y2 <= (y2 <= SCR_HEIGHT-YSPEED) ? (y2 + YSPEED) : y2;
end
else if (up) begin
y2 <= (y2 >= YSPEED) ? (y2 - YSPEED) : y2;
end
else if (left) begin
x2 <= (x2 >= XSPEED) ? (x2 - XSPEED) : x2;
end
else if (right) begin
x2 <= (x2 <= SCR_WIDTH-XSPEED) ? (x2 + XSPEED) : x2;
end
end
2'b10: begin
if (down) begin
y3 <= (y3 <= SCR_HEIGHT-YSPEED) ? (y3 + YSPEED) : y3;
end
else if (up) begin
y3 <= (y3 >= YSPEED) ? (y3 - YSPEED) : y3;
end
else if (left) begin
x3 <= (x3 >= XSPEED) ? (x3 - XSPEED) : x3;
end
else if (right) begin
x3 <= (x3 <= SCR_WIDTH-XSPEED) ? (x3 + XSPEED) : x3;
end
end
2'b11: begin
if (down) begin
y4 <= (y4 <= SCR_HEIGHT-YSPEED) ? (y4 + YSPEED) : y4;
end
else if (up) begin
y4 <= (y4 >= YSPEED) ? (y4 - YSPEED) : y4;
end
else if (left) begin
x4 <= (x4 >= XSPEED) ? (x4 - XSPEED) : x4;
end
else if (right) begin
x4 <= (x4 <= SCR_WIDTH-XSPEED) ? (x4 + XSPEED) : x4;
end
end
endcase
end
else begin
x1 <= x1_raw;
y1 <= y1_raw;
x2 <= x2_raw;
y2 <= y2_raw;
x3 <= x3_raw;
y3 <= y3_raw;
x4 <= x4_raw;
y4 <= y4_raw;
cur_state <= ~OVERRIDE;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[5010], n, s = 0, i; int main() { cin >> n >> i; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); for (i = 0; i < n; i++) s += a[i] != a[(i + n / 2) % n]; cout << s << endl; for (i = 0; i < n; i++) cout << a[i] << << a[(i + n / 2) % n] << endl; }
|
module etx_fifo(/*AUTOARG*/
// Outputs
txrd_wait, txwr_wait, txrr_wait, etx_cfg_access, etx_cfg_packet,
txrd_fifo_access, txrd_fifo_packet, txrr_fifo_access,
txrr_fifo_packet, txwr_fifo_access, txwr_fifo_packet,
// Inputs
etx_reset, sys_reset, sys_clk, tx_lclk_div4, txrd_access,
txrd_packet, txwr_access, txwr_packet, txrr_access, txrr_packet,
etx_cfg_wait, txrd_fifo_wait, txrr_fifo_wait, txwr_fifo_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h000;
//Clocks,reset,config
input etx_reset;
input sys_reset;
input sys_clk;
input tx_lclk_div4; // slow speed parallel clock
//Read Request Channel Input
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Write Channel Input
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Read Response Channel Input
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
//Configuration Interface (for ERX)
output etx_cfg_access;
output [PW-1:0] etx_cfg_packet;
input etx_cfg_wait;
output txrd_fifo_access;
output [PW-1:0] txrd_fifo_packet;
input txrd_fifo_wait;
output txrr_fifo_access;
output [PW-1:0] txrr_fifo_packet;
input txrr_fifo_wait;
output txwr_fifo_access;
output [PW-1:0] txwr_fifo_packet;
input txwr_fifo_wait;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
/************************************************************/
/*FIFOs */
/************************************************************/
//TODO: Minimize depth and width
/*fifo_cdc AUTO_TEMPLATE (
// Outputs
.access_out (@"(substring vl-cell-name 0 4)"_fifo_access),
.packet_out (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
.wait_out (@"(substring vl-cell-name 0 4)"_wait),
.wait_in (@"(substring vl-cell-name 0 4)"_fifo_wait),
.clk_out (tx_lclk_div4),
.clk_in (sys_clk),
.access_in (@"(substring vl-cell-name 0 4)"_access),
.rd_en (@"(substring vl-cell-name 0 4)"_fifo_read),
.reset_in (sys_reset),
.reset_out (etx_reset),
.packet_in (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
);
*/
//Write fifo (from slave)
fifo_cdc #(.DW(104), .DEPTH(32)) txwr_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txwr_wait), // Templated
.access_out (txwr_fifo_access), // Templated
.packet_out (txwr_fifo_packet[PW-1:0]), // Templated
// Inputs
.clk_in (sys_clk), // Templated
.reset_in (sys_reset), // Templated
.access_in (txwr_access), // Templated
.packet_in (txwr_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.reset_out (etx_reset), // Templated
.wait_in (txwr_fifo_wait)); // Templated
//Read request fifo (from slave)
fifo_cdc #(.DW(104), .DEPTH(32)) txrd_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txrd_wait), // Templated
.access_out (txrd_fifo_access), // Templated
.packet_out (txrd_fifo_packet[PW-1:0]), // Templated
// Inputs
.clk_in (sys_clk), // Templated
.reset_in (sys_reset), // Templated
.access_in (txrd_access), // Templated
.packet_in (txrd_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.reset_out (etx_reset), // Templated
.wait_in (txrd_fifo_wait)); // Templated
//Read response fifo (from master)
fifo_cdc #(.DW(104), .DEPTH(32)) txrr_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txrr_wait), // Templated
.access_out (txrr_fifo_access), // Templated
.packet_out (txrr_fifo_packet[PW-1:0]), // Templated
// Inputs
.clk_in (sys_clk), // Templated
.reset_in (sys_reset), // Templated
.access_in (txrr_access), // Templated
.packet_in (txrr_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.reset_out (etx_reset), // Templated
.wait_in (txrr_fifo_wait)); // Templated
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../edma/hdl/")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
// memoria dual port - single clk que permite escrita e leitura
// simultaneas em portas distintas
module regs(
clk, // clk
en_write, // write enable
data_write, // dados in
addr_write, // endereco
addr_read1, // endereco
addr_read2, // endereco
data_read1, // saida
data_read2
);
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// declaracao de entrada / saida
input clk, en_write;
input signed [DATA_WIDTH-1:0] data_write;
input [REG_ADDR_WIDTH-1:0] addr_write, addr_read1, addr_read2;
output [DATA_WIDTH-1:0] data_read1, data_read2;
// declaracao da memoria RAM
reg [DATA_WIDTH-1:0] ram [0:(1<<REG_ADDR_WIDTH)-1];
// Port A - write only
always @ (posedge clk) begin
if (en_write) begin
ram[addr_write] <= data_write;
end
end
// data read
assign data_read1 = (addr_write == addr_read1 && en_write ? data_write : ram[addr_read1]);
assign data_read2 = (addr_write == addr_read2 && en_write ? data_write : ram[addr_read2]);
// inicialize os registradores 0 e 1
initial begin
ram[0] <= 0;
ram[1] <= 1;
end
endmodule
|
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