text stringlengths 59 71.4k |
|---|
module arm9_soft(
input coe_M1_RSTN, coe_M1_CLK,
output rso_MRST_reset,
output cso_MCLK_clk,
output [31:0] avm_M1_writedata,
input [31:0] avm_M1_readdata,
output [29:0] avm_M1_address,
output [3:0] avm_M1_byteenable,
output avm_M1_write,
output avm_M1_read,
output avm_M1_begintransfer,
input avm_M1_readdatavalid,
input avm_M1_waitrequest,
input [9:0] inr_EVENTS_irq
);
assign rso_MRST_reset = ~coe_M1_RSTN;
assign cso_H1CLK_clk = coe_M1_CLK; //66.66 MHz
wire [31:0] rom_address;
assign avm_M1_address = rom_address[29:0];
arm9_compatiable_code arm9(
.clk(cso_H1CLK_clk),
.rst(rso_MRST_reset),
.cpu_en(1'b1),
.cpu_restart(1'b0),
.fiq(1'b0),
.irq(&inr_EVENTS_irq),
.rom_abort(1'b0),
.rom_data(avm_M1_readdata),
.rom_addr(rom_address),
.rom_en(avm_M1_read),
.ram_abort(1'b0),
.ram_rdata(),
.ram_addr(),
.ram_cen(),
.ram_flag(),
.ram_wdata(),
.ram_wen()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRBP_1_V
`define SKY130_FD_SC_HS__DFRBP_1_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog wrapper for dfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfrbp_1 (
RESET_B,
CLK ,
D ,
Q ,
Q_N ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfrbp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfrbp_1 (
RESET_B,
CLK ,
D ,
Q ,
Q_N
);
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfrbp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRBP_1_V
|
#include <bits/stdc++.h> using namespace std; int a[100005], n, k; bool cmp(int x, int y) { return x % 10 > y % 10; } int main() { cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n, cmp); for (int i = 0; i < n; i++) { if (a[i] % 10 == 0 || k < 10 - a[i] % 10) break; k -= 10 - a[i] % 10; a[i] += 10 - a[i] % 10; } for (int i = 0; i < n; i++) { if (k < 10) break; int cpy = a[i]; a[i] = min(100, a[i] + k - k % 10); k -= (a[i] - cpy); } int ans = 0; for (int i = 0; i < n; i++) ans += a[i] / 10; cout << ans; } |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_timer_ecc_fault_itr (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg d1_data_in;
reg d2_data_in;
wire data_in;
reg edge_capture;
wire edge_capture_wr_strobe;
wire edge_detect;
wire irq;
reg irq_mask;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask) |
({1 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture <= 0;
else if (edge_detect)
edge_capture <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in & ~d2_data_in;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_2_V
`define SKY130_FD_SC_LP__O211AI_2_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211ai_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221A_TB_V
`define SKY130_FD_SC_HD__O221A_TB_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o221a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__o221a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221A_TB_V
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:36777216 ) template <class T> void chmax(T& l, const T r) { l = max(l, r); } template <class T> void chmin(T& l, const T r) { l = min(l, r); } void reader(int& x) { int k, m = 0; x = 0; for (;;) { (k) = getchar_unlocked(); if (k == - ) { m = 1; break; } if ( 0 <= k && k <= 9 ) { x = k - 0 ; break; } } for (;;) { (k) = getchar_unlocked(); if (k < 0 || k > 9 ) break; x = x * 10 + k - 0 ; } if (m) x = -x; } void reader(long long& x) { int k, m = 0; x = 0; for (;;) { (k) = getchar_unlocked(); if (k == - ) { m = 1; break; } if ( 0 <= k && k <= 9 ) { x = k - 0 ; break; } } for (;;) { (k) = getchar_unlocked(); if (k < 0 || k > 9 ) break; x = x * 10 + k - 0 ; } if (m) x = -x; } int reader(char c[]) { int i, s = 0; for (;;) { (i) = getchar_unlocked(); if (i != && i != n && i != r && i != t && i != EOF) break; } c[s++] = i; for (;;) { (i) = getchar_unlocked(); if (i == || i == n || i == r || i == t || i == EOF) break; c[s++] = i; } c[s] = 0 ; return s; } template <class T, class S> void reader(T& x, S& y) { reader(x); reader(y); } template <class T, class S, class U> void reader(T& x, S& y, U& z) { reader(x); reader(y); reader(z); } template <class T, class S, class U, class V> void reader(T& x, S& y, U& z, V& w) { reader(x); reader(y); reader(z); reader(w); } void writer(int x, char c) { int s = 0, m = 0; char f[10]; if (x < 0) m = 1, x = -x; while (x) f[s++] = x % 10, x /= 10; if (!s) f[s++] = 0; if (m) putchar_unlocked( - ); while (s--) putchar_unlocked(f[s] + 0 ); putchar_unlocked(c); } void writer(long long x, char c) { int s = 0, m = 0; char f[20]; if (x < 0) m = 1, x = -x; while (x) f[s++] = x % 10, x /= 10; if (!s) f[s++] = 0; if (m) putchar_unlocked( - ); while (s--) putchar_unlocked(f[s] + 0 ); putchar_unlocked(c); } void writer(const char c[]) { int i; for (i = 0; c[i] != 0 ; i++) putchar_unlocked(c[i]); } void writer(const char x[], char c) { int i; for (i = 0; x[i] != 0 ; i++) putchar_unlocked(x[i]); putchar_unlocked(c); } template <class T> void writerLn(T x) { writer(x, n ); } template <class T, class S> void writerLn(T x, S y) { writer(x, ); writer(y, n ); } template <class T, class S, class U> void writerLn(T x, S y, U z) { writer(x, ); writer(y, ); writer(z, n ); } template <class T> void writerArr(T x[], int n) { if (!n) { putchar_unlocked( n ); return; } for (int i = 0; i < (n - 1); i++) writer(x[i], ); writer(x[n - 1], n ); } template <class T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } template <class T> T extgcd(T a, T b, T& x, T& y) { for (T u = y = 1, v = x = 0; a;) { T q = b / a; swap(x -= q * u, u); swap(y -= q * v, v); swap(b -= q * a, a); } return b; } template <class T> T mod_inv(T a, T m) { T x, y; extgcd(a, m, x, y); return (m + x % m) % m; } template <class T> T CRT(T r1, T m1, T r2, T m2) { T a1, a2; extgcd(m1, m2, a1, a2); T ret = (m1 * a1 * r2 + m2 * a2 * r1) % (m1 * m2); return ret < 0 ? ret + m1 * m2 : ret; } int memo[100][100]; int _k; int dfs(int a, int b, int k) { if (memo[a][b] != -1) return memo[a][b]; if (k == 0) { if (_k % 2 == 0) return b % 2 == 1; else return b % 2 == 0; } int val = 0; if (a != 0) val = max(val, dfs(a - 1, b, k - 1) ^ 1); if (b != 0) val = max(val, dfs(a, b - 1, k - 1) ^ 1); return memo[a][b] = val; } int solve_dfs(int e, int o, int m) { memset(memo, -1, sizeof(memo)); _k = m; int ans = dfs(e, o, m); return ans; } int solve(int e, int o, int m) { if (m == 0) return o % 2; if (o == 0) return 0; if (e + o + 1 == m) return 0; if (m > o * 2) return 0; if (m < e * 2) return m % 2; else return (m + o + e) % 2; } void test() { for (int e = 0; e < (10); e++) { for (int o = 0; o < (10); o++) { printf( %d %d : , e, o); for (int k = 0; k < (e + o + 1); k++) { int x = solve_dfs(e, o, k); printf( %d , x); int y = solve(e, o, k); if (x != y) { cout << ? ; } } puts( ); } } } int main() { int n, m; cin >> n >> m; int e = 0, o = 0; for (int i = 0; i < (n); i++) { int x; reader(x); if (x % 2 == 0) e++; else o++; } m = n - m; int ans = solve(e, o, m); if (ans) puts( Stannis ); else puts( Daenerys ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXBP_SYMBOL_V
`define SKY130_FD_SC_MS__EDFXBP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXBP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, m; void update(int *c, int x, int v) { while (x <= m) { c[x] += v; x += x & -x; } } long long sum(int *c, int x) { long long ret = 0; while (x > 0) { ret += c[x]; x -= x & -x; } return ret; } long long calc(int *c, int L, int R) { return sum(c, R) - sum(c, L - 1); } int c[3060 + 3060][3060], L[3060][3060], R[3060][3060], Ld[3060][3060]; char s[3060][3060]; vector<pair<int, int> > g[3060]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) scanf( %s , s[i] + 1); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) { if (s[i][j] == . ) L[i][j] = 0; else L[i][j] = L[i][j - 1] + 1; } for (int i = n; i > 0; --i) for (int j = m; j > 0; --j) { if (s[i][j] == . ) R[i][j] = 0; else R[i][j] = R[i][j + 1] + 1; if (s[i][j] == . ) Ld[i][j] = 0; else Ld[i][j] = Ld[i + 1][j - 1] + 1; } for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) g[j + R[i][j] - 1].push_back(make_pair(i, j)); long long ans = 0; for (int j = m; j > 0; --j) { for (int i = 0; i < g[j].size(); ++i) { int x = g[j][i].first; int y = g[j][i].second; update(c[x + y], y, 1); } for (int i = 1; i <= n; ++i) { int mi = min(L[i][j], Ld[i][j]); if (!mi) continue; ans += calc(c[i + j], j - mi + 1, j); } } cout << ans << endl; return 0; } |
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 32-bit"
// VERSION "Version 11.1 Build 173 11/01/2011 SJ Full Version"
// CREATED "Wed Oct 12 19:43:24 2016"
module div_23(
clk,
div23
);
input wire clk;
output wire div23;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
assign div23 = SYNTHESIZED_WIRE_11;
assign SYNTHESIZED_WIRE_12 = 0;
assign SYNTHESIZED_WIRE_14 = 0;
\7490 b2v_inst(
.SET9A(SYNTHESIZED_WIRE_11),
.CLRA(SYNTHESIZED_WIRE_12),
.SET9B(SYNTHESIZED_WIRE_13),
.CLKB(SYNTHESIZED_WIRE_3),
.CLKA(clk),
.CLRB(SYNTHESIZED_WIRE_12),
.QD(SYNTHESIZED_WIRE_9),
.QA(SYNTHESIZED_WIRE_3),
.QB(SYNTHESIZED_WIRE_13)
);
\7490 b2v_inst2(
.SET9A(SYNTHESIZED_WIRE_13),
.CLRA(SYNTHESIZED_WIRE_14),
.SET9B(SYNTHESIZED_WIRE_11),
.CLKB(SYNTHESIZED_WIRE_8),
.CLKA(SYNTHESIZED_WIRE_9),
.CLRB(SYNTHESIZED_WIRE_14),
.QA(SYNTHESIZED_WIRE_8),
.QB(SYNTHESIZED_WIRE_11)
);
endmodule
|
/*
Module: nes_controller
Description: Fetches nes controller buttons
and returns them as an array of 8 stored in buttons.
A FSM is implemented to fetch data,
also taking into account the correct
clock speed by scaling down the clock
slow enough for the controller to read
the pulses.
Author: Sergio M, Randy T, Omar T, Hector D, Kevin M
Date: 8/9/14 (Rev2)
*/
module nes_controller(
LATCH, // GPIO[x]
DATA, // GPIO[x]
PULSE, // GPIO[x]
CLOCK, // eg. CLOCK_50 (50MHz)
BUTTONS // Array of buttons
);
//=======================================================
// PORT declarations
//=======================================================
input DATA;
input CLOCK;
output LATCH;
output PULSE;
output [7:0] BUTTONS;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg [7:0] buttons; // Holds the buttons to be pressed
reg latch; // nes latch pin
reg pulse; // nes pulse pin
reg nes_clock; // Oscillates slower for nes
reg [17:0] prescaler; // For scaling down clock rate
// FSM
reg [5:0] states; // Keeps track of current state
//=======================================================
// Constant Variables
//=======================================================
//Constant variables named accordingly to the states
//18 states total
//1 Init state
parameter NES_Init = 1;
//Latch
//3 states for the Latch (A button)
parameter Latch_ON_1 = 2;
parameter Latch_ON_2 = 3;
parameter Latch_OFF = 4;
//Pulses
//14 states for the pulses (B, Select, Start, Up, Down, Left, Right)
parameter ButtonB_ON = 5;
parameter ButtonB_OFF = 6;
parameter ButtonSelect_ON = 7;
parameter ButtonSelect_OFF = 8;
parameter ButtonStart_ON = 9;
parameter ButtonStart_OFF = 10;
parameter ButtonUp_ON = 11;
parameter ButtonUp_OFF = 12;
parameter ButtonDown_ON = 13;
parameter ButtonDown_OFF = 14;
parameter ButtonLeft_ON = 15;
parameter ButtonLeft_OFF = 16;
parameter ButtonRight_ON = 17;
parameter ButtonRight_OFF = 18;
// For slowing down the clock by a certain factor
// TODO: Still need to check for optimal timing
parameter To_Tick = 12'h0A2;
//=======================================================
// Structural coding
//=======================================================
assign LATCH = latch;
assign PULSE = pulse;
assign BUTTONS = buttons;
//Initialize variables
initial begin
prescaler <= 0;
nes_clock <= 0;
latch <= 0;
pulse <= 0;
states <= NES_Init;
end
// Prescales CLOCK_50 to appropriate Hz for controller
always @ (posedge CLOCK)
begin
// Slow down the clock by a certain factor
// Still need to check for optimal timing
if(prescaler < To_Tick)
prescaler <= prescaler + 1;
else
prescaler <= 0;
// Once prescaler reached count, oscillate clk
if(prescaler == 0)
begin
nes_clock <= ~nes_clock;
end
end
/*
* Runs whenever nes_clock ticks which would be counted by the prescaler loop above.
* Summary: State machine first latches on (1) for one full pulse period. After another tick,
latch turns off (0) sending a bit stored in DATA, 1 for A not pressed, 0 for pressed (Active low).
Adjusted the bits so that 1 meant the button would be pressed for simplicity.
After checking latch (A button), the pulse would oscillate on and off.
After every off, take in DATA to see if each button is pressed or not
Order of checks:(B, Select, Start, Up, Down, Left, Right)
Each button excluding A, has 2 states (On and Off).
* Output: 8 bit register buttons stored with all the buttons
buttons[0] = A
buttons[1] = B
buttons[2] = Select
buttons[3] = Start
buttons[4] = Up
buttons[5] = Down
buttons[6] = Left
buttons[7] = Right
Example: b10010100 - Right, Up, and Select are pressed.
*/
always @ (posedge nes_clock)
begin
//Transitions
case(states)
NES_Init :
states <= Latch_ON_1;
//Latch starts
//Latch stays on for 2 states as it needs to keep the latch on for twice as longer than one pulse
//Diagram shown on the notes
Latch_ON_1 :
states <= Latch_ON_2;
Latch_ON_2 :
states <= Latch_OFF;
Latch_OFF :
states <= ButtonB_ON;
//Pulses
ButtonB_ON :
states <= ButtonB_OFF;
ButtonB_OFF :
states <= ButtonSelect_ON;
ButtonSelect_ON :
states <= ButtonSelect_OFF;
ButtonSelect_OFF :
states <= ButtonStart_ON;
ButtonStart_ON :
states <= ButtonStart_OFF;
ButtonStart_OFF :
states <= ButtonUp_ON;
ButtonUp_ON :
states <= ButtonUp_OFF;
ButtonUp_OFF :
states <= ButtonDown_ON;
ButtonDown_ON :
states <= ButtonDown_OFF;
ButtonDown_OFF :
states <= ButtonLeft_ON;
ButtonLeft_ON :
states <= ButtonLeft_OFF;
ButtonLeft_OFF :
states <= ButtonRight_ON;
ButtonRight_ON :
states <= ButtonRight_OFF;
ButtonRight_OFF :
states <= Latch_ON_1;
endcase
//Actions
case(states)
NES_Init : begin
latch <= 0;
pulse <= 0;
end
//Latch starts
//Latch stays on for 2 states (two ticks), then off for 1 state (1 tick)
//After going off, read in the Data for the A button, invert Data because
//it is active low, meaning 1 would be button pressed.
Latch_ON_1 : begin
latch <= 1;
pulse <= 0;
end
Latch_ON_2 : begin
latch <= 1;
pulse <= 0;
end
Latch_OFF : begin
latch <= 0;
pulse <= 0;
buttons[0] <= ~DATA;
end
//Pulses start
//On states have pulse as 1, off states has pulse as 0. After it pulses 0, read data in.
ButtonB_ON :
pulse <= 1;
ButtonB_OFF : begin
pulse <= 0;
buttons[1] <= ~DATA;
end
ButtonSelect_ON :
pulse <= 1;
ButtonSelect_OFF : begin
pulse <= 0;
buttons[2] <= ~DATA;
end
ButtonStart_ON :
pulse <= 1;
ButtonStart_OFF : begin
pulse <= 0;
buttons[3] <= ~DATA;
end
ButtonUp_ON :
pulse <= 1;
ButtonUp_OFF : begin
pulse <= 0;
buttons[4] <= ~DATA;
end
ButtonDown_ON :
pulse <= 1;
ButtonDown_OFF : begin
pulse <= 0;
buttons[5] <= ~DATA;
end
ButtonLeft_ON :
pulse <= 1;
ButtonLeft_OFF : begin
pulse <= 0;
buttons[6] <= ~DATA;
end
ButtonRight_ON :
pulse <= 1;
ButtonRight_OFF : begin
pulse <= 0;
buttons[7] <= ~DATA;
end
endcase
end
endmodule // END nes_controller
|
`timescale 1ns / 1ps
module Sine_Cosine_CORDIC_tb;
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
parameter W=32, W_Exp = 8, W_Sgf = 23, S_Exp = 9;
//declaration of signals
//Input Signals
reg clk; // Reloj del sistema.
reg rst; // Señal de reset del sistema.
reg beg_fsm_cordic; // Señal de inicio de la maquina de estados del módulo CORDIC.
reg ack_cordic; // Señal de acknowledge proveniente de otro módulo que indica que ha recibido el resultado del modulo CORDIC.
reg operation; // Señal que indica si se realiza la operacion seno(1'b1) o coseno(1'b0).
reg [W-1:0] data_in; // Dato de entrada, contiene el angulo que se desea calcular en radianes.
reg [1:0] shift_region_flag; // Señal que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
//Output Signals
wire ready_cordic; // Señal de salida que indica que se ha completado el calculo del seno/coseno.
wire [W-1:0] data_output; // Bus de datos con el valor final del angulo calculado.
wire overflow_flag; // Bandera de overflow de la operacion.
wire underflow_flag; // Bandera de underflow de la operacion.
//integer i;
Sine_Cosine_CORDIC #(.W(W),.W_Exp(W_Exp),.W_Sgf(W_Sgf),.S_Exp(S_Exp)) Sine_Cosine_CORDIC_dut //Single Precision */ # (parameter W = 64, W_Exp = 11, W_Sgf = 52, S_Exp = 12) //-- Double Precision */
(
//Input Signals
.clk(clk), // Reloj del sistema.
.rst(rst), // Señal de reset del sistema.
.beg_fsm_cordic(beg_fsm_cordic), // Señal de inicio de la maquina de estados del módulo CORDIC.
.ack_cordic(ack_cordic), // Señal de acknowledge proveniente de otro módulo que indica que ha recibido el resultado del modulo CORDIC.
.operation(operation), // Señal que indica si se realiza la operacion seno(1'b1) o coseno(1'b0).
.data_in(data_in), // Dato de entrada, contiene el angulo que se desea calcular en radianes.
.shift_region_flag(shift_region_flag), // Señal que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
//Output Signals
.ready_cordic(ready_cordic), // Señal de salida que indica que se ha completado el calculo del seno/coseno.
.data_output(data_output), // Bus de datos con el valor final del angulo calculado.
.overflow_flag(overflow_flag), // Bandera de overflow de la operacion.
.underflow_flag(underflow_flag) // Bandera de underflow de la operacion.
);
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//Generation of the clock
initial
begin
clk = 1;
forever #5 clk = ~clk;
end
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
initial
begin
//inicializacion de señales
rst = 1;
beg_fsm_cordic = 0;
ack_cordic = 0;
operation = 0;
data_in = 32'h00000000;
shift_region_flag = 2'b00;
#100
rst = 0;
data_in = 32'h3f91361e;
shift_region_flag = 2'b00;
#5
beg_fsm_cordic = 1;
#10
beg_fsm_cordic = 0;
end
integer f,i;
initial
begin
f=$fopen("Primera_prueba_1_dato.txt","w");
$timeformat(-9,1,"ns",12);
for(i=0; i<2;i=i+1)
begin
@(ready_cordic)
$fwrite(f,"%t %h\n", $realtime, data_output);
end
$fclose(f);
end
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
module nysa_host_interface (
input clk,
input rst
//output reg [7:0] o_reg_example
//input [7:0] i_reg_example
);
//local parameters
localparam PARAM1 = 32'h00000000;
//registes/wires
//submodules
//asynchronous logic
//synchronous logic
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5010; inline int read() { int s = 0, w = 1; register char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = (s << 3) + (s << 1) + (ch ^ 48), ch = getchar(); return s * w; } int n, m, K; int a[N], b[N], c[N], dp[N][N]; struct Node { int x, w; } g[N]; inline bool cp(Node x, Node y) { return x.w < y.w; } signed main() { n = read(), m = read(), K = read(); for (register int i = 1; i <= n; i++) a[i] = read(), b[i] = read(), c[i] = read(), g[i].x = g[i].w = i; for (register int i = 1; i <= m; i++) { int u, v; u = read(), v = read(); g[v].w = max(g[v].w, u); } sort(g + 1, g + 1 + n, cp); int now = 1; while (!g[now].w) now++; memset(dp, -0x3f, sizeof(dp)); for (register int i = 0; i <= K; i++) dp[0][i] = 0; int qwq = K; for (register int i = 1; i <= n; i++) { if (qwq < a[i]) { puts( -1 ); return 0; } qwq += b[i]; for (register int j = a[i]; j <= 5000 - b[i]; j++) dp[i][j + b[i]] = max(dp[i][j + b[i]], dp[i - 1][j]); while (now <= n && g[now].w == i) { for (register int j = 1; j <= 5000; j++) dp[i][j - 1] = max(dp[i][j - 1], dp[i][j] + c[g[now].x]); now++; } } int res = 0; for (register int i = 0; i <= 5000; i++) res = max(res, dp[n][i]); printf( %d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; string a[33]; int z[33][33]; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cerr.tie(nullptr); cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { z[i + 1][j + 1] = z[i + 1][j] + z[i][j + 1] - z[i][j] + (a[i][j] == 1 ); } int sol = 0; for (int p = 0; p < n; p++) for (int q = 0; q < m; q++) for (int r = p + 1; r <= n; r++) for (int s = q + 1; s <= m; s++) { int c = 0; c += z[p][q]; c += z[r][s]; c -= z[p][s]; c -= z[r][q]; if (c == 0) { sol = max(sol, r - p + s - q); } } cout << 2 * sol << n ; } |
#include <bits/stdc++.h> using namespace std; struct unionfind_t { vector<int> parent, rank; unionfind_t(int n) : parent(n), rank(n, 0) { iota(parent.begin(), parent.end(), 0); } int find(int v) { if (parent[v] == v) return v; return parent[v] = find(parent[v]); } int join(int a, int b) { a = find(a), b = find(b); if (a == b) return a; if (rank[a] > rank[b]) swap(a, b); parent[a] = b; if (rank[a] == rank[b]) ++rank[b]; return b; } }; int main() { int n, m; scanf( %d %d , &n, &m); struct edge_t { int a, b, value; }; vector<edge_t> edges(m); for (int i = 0; i < m; ++i) { scanf( %d %d %d , &edges[i].a, &edges[i].b, &edges[i].value); --edges[i].a, --edges[i].b; } unionfind_t uf(n); vector<int> node_count(n, 1); vector<int> edge_count(n, 0); sort(edges.rbegin(), edges.rend(), [](const edge_t &a, const edge_t &b) { return a.value < b.value; }); int result = 0; for (const edge_t &ed : edges) { int a = uf.find(ed.a), b = uf.find(ed.b); bool should_add; if (a == b) { should_add = (edge_count[a] + 1 <= node_count[a]); } else { should_add = (edge_count[a] + 1 + edge_count[b] <= node_count[a] + node_count[b]); } if (should_add) { int id; if (a != b) { id = uf.join(a, b); edge_count[id] = edge_count[a] + edge_count[b]; node_count[id] = node_count[a] + node_count[b]; } else { id = a; } ++edge_count[id]; result += ed.value; } } printf( %d n , result); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, x, m, y; int main() { int i, j, k, flag; long long ans; int l1, l2, r1, r2, l, r; int cnt; while (scanf( %d%d%d%d , &n, &x, &m, &y) != EOF) { if (x > y) { k = x; x = y; y = k; } ans = 1; flag = 0; for (i = 1; i <= n; i++) { k = ans; if (i + x == y) { r1 = y - x + i; r = min(r1, m); cnt = 0; if (r1 <= r) { cnt++; } ans += 2 * (r - cnt) + cnt; flag = 1; } else if (i + x > y) { l1 = i + x - y; r1 = y - x + i; if (m < l1) { ans++; continue; } r = min(r1, m); cnt = 1; if (r1 <= r) { cnt++; } ans += (r - l1 + 1 - cnt) * 2 + cnt; flag = 1; } else { l1 = y - x - i; r1 = y - x + i; if (m < l1) { ans++; continue; } cnt = 1; r = min(r1, m); if (r1 <= r) { cnt++; } ans += 2 * (r - l1 + 1 - cnt) + cnt; flag = 1; } } for (i = 1; i <= m; i++) { if (i + x == y) { continue; } else if (i + x > y) { l1 = i + x - y; r1 = y - x + i; if (n < l1) { ans++; } } else { l1 = y - x - i; r1 = y - x + i; if (n < l1) { ans++; continue; } } } if (flag) ans++; cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; bool b1[N]; int Z, num[N], in[N], dp[N][20], dep[N], freq[2][N], f[N]; long long fans[N]; vector<int> g[N], v; map<int, int> mp; struct qq { int in, l, r, c; qq(int a, int b, int e, int d) { in = a, l = b, r = e, c = d; } bool operator<(const qq& s) const { if (l / Z != s.l / Z) return l / Z < s.l / Z; return r / Z < s.r / Z; } }; vector<qq> q; void dfs(int u, int p, int d) { dep[u] = d; dp[u][0] = p; in[u] = v.size(); v.push_back(u); for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (v != p) dfs(v, u, d + 1); } v.push_back(u); } int lca(int a, int b) { if (dep[a] < dep[b]) swap(a, b); int x = dep[a] - dep[b]; for (int i = 0; i < 20; i++) { if ((1 << i) & x) a = dp[a][i]; } if (a == b) return a; for (int i = 19; i >= 0; i--) { if (dp[a][i] != dp[b][i]) { a = dp[a][i], b = dp[b][i]; } } return dp[a][0]; } long long ans; int l = 0, r = -1; void add(int in, int d) { int x = v[in]; f[x] += d; if (d == 1 && f[x] == 2) d = -1; else if (d == -1 && f[x] == 1) d = 1; ans += d * freq[!b1[x]][num[x]]; freq[b1[x]][num[x]] += d; } void fix(int L, int R) { while (l < L) { add(l, -1); l++; } while (l > L) { l--; add(l, 1); } while (r < R) { r++; add(r, 1); } while (r > R) { add(r, -1); r--; } } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , b1 + i); } for (int i = 1; i <= n; i++) { scanf( %d , num + i); if (mp.find(num[i]) == mp.end()) mp[num[i]] = mp.size(); num[i] = mp[num[i]]; } for (int i = 1, a, b; i < n; i++) { scanf( %d%d , &a, &b); g[a].push_back(b), g[b].push_back(a); } dfs(1, -1, 0); Z = sqrt(v.size() + 0.0) + 1; for (int k = 1; k < 20; k++) { for (int i = 1; i <= n; i++) { if (dp[i][k - 1] == -1) dp[i][k] = -1; else dp[i][k] = dp[dp[i][k - 1]][k - 1]; } } int m; scanf( %d , &m); for (int i = 0, a, b, c; i < m; i++) { scanf( %d%d , &a, &b); c = lca(a, b); bool f = (c != a) & (c != b); q.push_back(qq(i, min(in[a], in[b]) + f, max(in[a], in[b]), c * f)); } sort(q.begin(), q.end()); for (int i = 0; i < m; i++) { fix(q[i].l, q[i].r); if (q[i].c) add(in[q[i].c], 1); fans[q[i].in] = ans; if (q[i].c) add(in[q[i].c], -1); } for (int i = 0; i < m; i++) { printf( %I64d n , fans[i]); } } |
#include <bits/stdc++.h> using namespace std; long long modpow(long long a, long long n, long long temp) { long long res = 1, y = a; while (n > 0) { if (n & 1) res = (res * y) % temp; y = (y * y) % temp; n /= 2; } return res % temp; } long long ison(long long mask, long long pos) { return (mask & (1 << pos)); } long long cbit(long long n) { long long k = 0; while (n) n &= (n - 1), k++; return k; } long long nbit(long long n) { long long k = 0; while (n) n /= 2, k++; return k; } long long mod = 1e9 + 7; int sgn(long long x) { return x < 0 ? -1 : !!x; } long long c[200005]; long long d[200005]; long long bit[500005], n, bit2[500005]; void upd(long long ind, long long val) { if (ind == 0) return; while (ind <= n) { bit[ind] += val; ind += (ind & -ind); } } long long qu(long long ind) { long long k = 0; while (ind > 0) { k += bit[ind]; ind -= (ind & -ind); } return k; } void upd2(long long ind, long long val) { if (ind == 0) return; while (ind <= n) { bit2[ind] += val; ind += (ind & -ind); } } long long qu2(long long ind) { long long k = 0; while (ind > 0) { k += bit2[ind]; ind -= (ind & -ind); } return k; } long long xo(long long i) { if ((i & 3) == 0) return i; if ((i & 3) == 1) return 1; if ((i & 3) == 2) return i + 1; return 0; } int main() { long long k, a, b, l, r, t, i, q; cin >> n >> k >> a >> b >> q; while (q--) { cin >> t; if (t == 1) { long long d1, d2; cin >> d1 >> d2; long long x1 = min(b, c[d1] + d2); long long x2 = min(a, d[d1] + d2); upd(d1, x1 - c[d1]); upd2(d1, x2 - d[d1]); c[d1] = x1; d[d1] = x2; } else { long long r1; cin >> r1; long long ans = 0; ans += qu(r1 - 1); ans += (qu2(n) - qu2(r1 + k - 1)); cout << ans << endl; } } } |
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: cx4_mul.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cx4_mul (
clock,
dataa,
datab,
result);
input clock;
input [23:0] dataa;
input [23:0] datab;
output [47:0] result;
wire [47:0] sub_wire0;
wire [47:0] result = sub_wire0[47:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_pipeline = 2,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 24,
lpm_mult_component.lpm_widthb = 24,
lpm_mult_component.lpm_widthp = 48;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "2"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "24"
// Retrieval info: PRIVATE: WidthB NUMERIC "24"
// Retrieval info: PRIVATE: WidthP NUMERIC "48"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "24"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "24"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "48"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 24 0 INPUT NODEFVAL "dataa[23..0]"
// Retrieval info: USED_PORT: datab 0 0 24 0 INPUT NODEFVAL "datab[23..0]"
// Retrieval info: USED_PORT: result 0 0 48 0 OUTPUT NODEFVAL "result[47..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 24 0 dataa 0 0 24 0
// Retrieval info: CONNECT: @datab 0 0 24 0 datab 0 0 24 0
// Retrieval info: CONNECT: result 0 0 48 0 @result 0 0 48 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_mul.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_mul.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_mul.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_mul.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_mul_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_mul_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; set<int> s; for (int i = 0, x; i < n; i++) { cin >> x; s.insert(((x + i) % n + n) % n); } puts(s.size() == n ? YES : NO ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A32O_BEHAVIORAL_PP_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a32o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long numC[200011]; long long numQ[200011]; long long numBC[200011]; long long numBQ[200011]; long long numQC[200011]; long long numQQ[200011]; long long triple(int n) { if (n < 0) return 0; if (n == 1) return 3; if (n == 0) return 1; long long temp = triple(n / 2); long long res = (temp * temp) % 1000000007; if (n % 2 == 0) return res; else return (res * 3) % 1000000007; } int main() { int n; string str; cin >> n >> str; int qNum = 0; for (int i = 0; i < n; i++) if (str[i] == ? ) qNum++; for (int i = n - 1; i >= 0; i--) { if (str[i] == c ) numC[i] = numC[i + 1] + 1; else numC[i] = numC[i + 1]; } for (int i = n - 1; i >= 0; i--) { if (str[i] == ? ) numQ[i] = numQ[i + 1] + 1; else numQ[i] = numQ[i + 1]; } for (int i = n - 1; i >= 0; i--) { if (str[i] == b ) numBC[i] = numBC[i + 1] + numC[i + 1]; else numBC[i] = numBC[i + 1]; numBC[i] %= 1000000007; } for (int i = n - 1; i >= 0; i--) { if (str[i] == b ) numBQ[i] = numBQ[i + 1] + numQ[i + 1]; else numBQ[i] = numBQ[i + 1]; numBQ[i] %= 1000000007; } for (int i = n - 1; i >= 0; i--) { if (str[i] == ? ) numQC[i] = numQC[i + 1] + numC[i + 1]; else numQC[i] = numQC[i + 1]; numQC[i] %= 1000000007; } for (int i = n - 1; i >= 0; i--) { if (str[i] == ? ) numQQ[i] = numQQ[i + 1] + numQ[i + 1]; else numQQ[i] = numQQ[i + 1]; numQQ[i] %= 1000000007; } long long t1 = 0; for (int i = n - 1; i >= 0; i--) if (str[i] == a ) t1 += numBC[i + 1]; t1 %= 1000000007; long long t2 = 0; for (int i = n - 1; i >= 0; i--) if (str[i] == a ) t2 += numQC[i + 1]; for (int i = n - 1; i >= 0; i--) if (str[i] == a ) t2 += numBQ[i + 1]; for (int i = n - 1; i >= 0; i--) if (str[i] == ? ) t2 += numBC[i + 1]; t2 %= 1000000007; long long t3 = 0; for (int i = n - 1; i >= 0; i--) if (str[i] == a ) t3 += numQQ[i + 1]; for (int i = n - 1; i >= 0; i--) if (str[i] == ? ) t3 += numBQ[i + 1]; for (int i = n - 1; i >= 0; i--) if (str[i] == ? ) t3 += numQC[i + 1]; t3 %= 1000000007; long long t4 = 0; for (int i = n - 1; i >= 0; i--) if (str[i] == ? ) t4 += numQQ[i + 1]; t4 %= 1000000007; long long ans = (t1 * triple(qNum)) % 1000000007 + (t2 * triple(qNum - 1)) % 1000000007 + (t3 * triple(qNum - 2)) % 1000000007 + (t4 * triple(qNum - 3)) % 1000000007; cout << ans % 1000000007; } |
#include <bits/stdc++.h> using namespace std; const int INF = numeric_limits<int>::max(); int n; vector<int> d, a; int get_longest(int l) { vector<int> d; while (l > a.size()) for (int i = 0; i < n; ++i) a.push_back(a[i]); d.assign(l + 10, INF); d[0] = -INF; for (int i = 0; i < l; ++i) { int j = int(upper_bound(d.begin(), d.end(), a[i]) - d.begin()); if (d[j - 1] <= a[i] && a[i] < d[j]) d[j] = a[i]; } for (int i = 1; i <= l; ++i) if (d[i] == INF) return i - 1; return l; } int main() { int t; int longest_same = 1; vector<int> b; scanf( %d %d , &n, &t); a.assign(n, 0); for (int i = 0; i < n; ++i) scanf( %d , &a[i]); b.assign(a.begin(), a.end()); sort(b.begin(), b.end()); map<int, int> new_val; int longest = 1; for (int i = 0; i < n; ++i) { if (i > 0 && b[i] == b[i - 1]) ++longest; else { if (longest > longest_same) longest_same = longest; longest = 1; } if (i == 0 || b[i] != b[i - 1]) new_val[b[i]] = i; } if (longest > longest_same) longest_same = longest; for (int i = 0; i < n; ++i) { } longest = get_longest(n); int next_longest, prev_longest; int d = INF; int k = 1; while (d > longest_same && k < t) { ++k; next_longest = get_longest(k * n); d = next_longest - longest; prev_longest = longest; longest = next_longest; } if (d <= longest_same) { longest = prev_longest + (t - k + 1) * longest_same; } printf( %d n , longest); return 0; } |
#include <bits/stdc++.h> using namespace std; int Count(int ar[], int m, int n) { int count = 0, i; for (i = 0; i < n; i++) { if (ar[i] == m) { count++; } } return count; } void change(int br[], int ar[], int n, int clr, int d, int m) { int count = 0, i; for (i = 0; i < n; i++) { if (ar[i] == m) { count++; br[i] = ceil(float(count) / d) + clr; ar[i] = -1; } } } int main() { int n, i, cnt = 0; cin >> n; int ar[n], br[n]; for (i = 0; i < n; i++) { br[i] = 0; } for (i = 0; i < n; i++) { cin >> ar[i]; if (ar[i] == 0) { cnt++; } } if (cnt == n) { cout << Possible n ; for (i = 0; i < n; i++) { cout << 1 << ; } return 0; } if (cnt != 0) { cout << Impossible ; return 0; } int m, count, clr = 0; m = *max_element(ar, ar + n); while (m != -1) { m = *max_element(ar, ar + n); count = Count(ar, m, n); if ((n - count) > m) { cout << Impossible ; return 0; } if (m == n - count) { change(br, ar, n, clr, count, m); clr++; } else { int bp = m - (n - count); if (bp % (count - bp) == 0) { change(br, ar, n, clr, count - bp, m); clr += count / (count - bp); } else { cout << Impossible ; return 0; } } m = *max_element(ar, ar + n); } cout << Possible n ; for (i = 0; i < n; i++) { cout << br[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 105; int S[N], E[N], T[N], C[N]; int t[N], W[N]; int main() { int n, m; scanf( %d %d , &n, &m); int i; for (i = 1; i <= n; i++) { t[i] = 1006; W[i] = -1; } for (i = 1; i <= m; i++) { scanf( %d %d %d %d , &S[i], &E[i], &T[i], &C[i]); for (int j = S[i]; j <= E[i]; j++) { if (T[i] < t[j]) { t[j] = T[i]; W[j] = i; } } } int sum = 0; for (i = 1; i <= n; i++) { if (W[i] != -1) { sum += C[W[i]]; } } printf( %d n , sum); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 66666; const int M = 55; const int sM = 105; const int inf = 1e9 + 7; const double pi = acos(-1); inline int read() { int x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) x = x * 10 + (ch ^ 48), ch = getchar(); return x * f; } int lim, pp[N]; struct CP { double x, y; CP(double xx = 0, double yy = 0) { x = xx, y = yy; } }; CP operator+(CP aa, CP bb) { return CP(aa.x + bb.x, aa.y + bb.y); } CP operator-(CP aa, CP bb) { return CP(aa.x - bb.x, aa.y - bb.y); } CP operator*(CP aa, CP bb) { return CP(aa.x * bb.x - aa.y * bb.y, aa.x * bb.y + aa.y * bb.x); } void FFT(CP *f, int flag) { for (int i = (0), iE = (lim - 1); i <= iE; i++) if (i < pp[i]) swap(f[i], f[pp[i]]); for (int i = 2; i <= lim; i <<= 1) { CP ch(cos(2 * pi / i), flag * sin(2 * pi / i)); for (int l = (i >> 1), j = 0; j < lim; j += i) { CP now(1, 0); for (int k = j; k < j + l; k++) { CP pa = f[k], pb = now * f[k + l]; f[k] = pa + pb, f[k + l] = pa - pb, now = now * ch; } } } if (flag == -1) for (int i = (0), iE = (lim - 1); i <= iE; i++) f[i].x /= lim, f[i].y /= lim; } CP A[N], B[N]; int n, m, t, x, dis[N]; int fu[N], fv[N], fval[N]; double ans[M][N], p[sM][N], calc[sM][N]; void Solve(int l, int mid, int r) { for (int d = (1), dE = (m); d <= dE; d++) { int tota = -1, totb = 0; B[0] = CP(0, 0); for (int i = (l), iE = (mid); i <= iE; i++) A[++tota] = CP(ans[fv[d]][i], 0); for (int i = (1), iE = (min(r - l + 1, t)); i <= iE; i++) B[++totb] = CP(p[d][i], 0); for (lim = 1; lim <= tota + totb; lim <<= 1) ; for (int i = (0), iE = (lim - 1); i <= iE; i++) pp[i] = ((pp[i >> 1] >> 1) | ((i & 1) * (lim >> 1))); for (int i = (tota + 1), iE = (lim - 1); i <= iE; i++) A[i] = CP(0, 0); for (int i = (totb + 1), iE = (lim - 1); i <= iE; i++) B[i] = CP(0, 0); FFT(A, 1), FFT(B, 1); for (int i = (0), iE = (lim - 1); i <= iE; i++) A[i] = A[i] * B[i]; FFT(A, -1); for (int i = (1), iE = (r - mid); i <= iE; i++) calc[d][i + mid] += A[i + tota].x; } } void Divide(int l, int r) { if (l == r) { for (int j = (1), jE = (m); j <= jE; j++) ans[fu[j]][l] = min(ans[fu[j]][l], calc[j][l] + fval[j]); return; } int mid = (l + r) / 2; Divide(l, mid); Solve(l, mid, r); Divide(mid + 1, r); } int main() { n = read(), m = read(), t = read(), x = read(); dis[n] = 0; for (int i = (1), iE = (n - 1); i <= iE; i++) dis[i] = inf; for (int i = (1), iE = (n - 1); i <= iE; i++) for (int j = (t), jE = (t * 2); j <= jE; j++) ans[i][j] = inf; for (int i = (1), iE = (m); i <= iE; i++) { fu[i] = read(), fv[i] = read(), fval[i] = read(); for (int j = (1), jE = (t); j <= jE; j++) p[i][j] = 1. * read() / 100000; } for (int i = (1), iE = (n); i <= iE; i++) for (int j = (1), jE = (m); j <= jE; j++) dis[fu[j]] = min(dis[fu[j]], dis[fv[j]] + fval[j]); for (int i = (1), iE = (n); i <= iE; i++) for (int j = (0), jE = (t - 1); j <= jE; j++) ans[i][j] = dis[i] + x; Solve(0, t - 1, t * 2); Divide(t, t * 2); printf( %.10lf n , ans[1][2 * t]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { long long a, b, x, y; cin >> a >> b >> x >> y; long long distX = x - a, distY = y - b; cout << distX * distY + 1 << n ; } } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void umin(T &a, T b) { a = min(a, b); } template <class T> inline void umax(T &a, T b) { a = max(a, b); } const int INF = 0x3f3f3f3f; long long mod = 1e9 + 7; const int N = 100005; char s[N]; struct Trie { static const int maxnode = 100005; static const int sigma_size = 26; int ch[maxnode][sigma_size]; int val[maxnode]; int p[maxnode]; int d[maxnode], ms[maxnode]; priority_queue<int> q[maxnode]; int sz; void clear() { sz = 1; memset(ch[0], 0, sizeof(ch[0])); } int idx(char c) { return c - a ; } void insert(const char *s, int v) { int u = 0, n = strlen(s); for (int i = 0; i < n; i++) { int c = idx(s[i]); if (!ch[u][c]) { memset(ch[sz], 0, sizeof(ch[sz])); val[sz] = 0; ch[u][c] = sz++; d[ch[u][c]] = d[u] + 1; } p[ch[u][c]] = u; u = ch[u][c]; } val[u] = v; } void dfs(int u) { for (int i = 0; i < 26; i++) { int v = ch[u][i]; if (v) { dfs(v); while (!q[v].empty()) { q[u].push(q[v].top()); q[v].pop(); } } } if (u == 0) return; if (val[u] == 0) { q[u].pop(); q[u].push(d[u]); } else { q[u].push(d[u]); } } int solve() { dfs(0); int ans = 0; while (!q[0].empty()) { ans += q[0].top(); q[0].pop(); } return ans; } } wc; int main() { int n; scanf( %d , &n); wc.clear(); for (int i = 0; i < n; i++) { scanf( %s , s); wc.insert(s, 1); } printf( %d n , wc.solve()); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBP_1_V
`define SKY130_FD_SC_MS__DLRBP_1_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBP_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 100; const int M = 1e9 + 100; long long a[N]; int main() { int n, m; long long x, y; while (~scanf( %d %d , &n, &m)) { x = -M; y = M; for (int i = 0; i < n; i++) { scanf( %lld , &a[i]); x = max(a[i], x); y = min(a[i], y); } if (m == 1) printf( %lld n , y); else if (m >= 3) printf( %lld n , x); else printf( %lld n , max(a[0], a[n - 1])); } return 0; } |
#include <bits/stdc++.h> using namespace std; string getbiner(long long n) { string ret = ; while (n) { if (n % 2) ret += 1 ; else ret += 0 ; n /= 2; } return ret; } long long getnum(string s) { long long ret = 0; long long now = 1; cout << t << ( s ) << = << (s) << n ; for (long long(i) = (0); (i) < (s.length()); (i)++) { ret += ((s[i] - 0 ) * now); now *= 2; } return ret; } int main() { ios::sync_with_stdio(NULL); cin.tie(NULL); cout.tie(NULL); long long n, m; cin >> n >> m; if (n < m) { cout << 0 << n ; return 0; } if ((n - m) % 2) { cout << 0 << n ; return 0; } long long k = (n - m) / 2; string a = getbiner(m); string b = getbiner(k); long long mx = max(a.length(), b.length()); long long diffa = mx - a.length(); long long diffb = mx - b.length(); for (long long(i) = (0); (i) < (diffa); (i)++) a += 0 ; for (long long(i) = (0); (i) < (diffb); (i)++) b += 0 ; reverse(a.begin(), a.end()); reverse(b.begin(), b.end()); long long counter = 0; int flag = 0; for (long long(i) = (0); (i) < (a.length()); (i)++) { if (a[i] == 1 && b[i] == 0 ) { counter++; } else if (a[i] == 1 && b[i] == 1 ) { flag = 1; } } if (flag) { cout << 0 << n ; return 0; } long long ans = pow(2, counter); if (n == m) ans -= 2; cout << ans << n ; } |
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// A pulse based clock domain synchronization scheme.
// When a sEN is asserted, a pulse is eventually sent to dPulse in the
// destination clock domain.
// Close and Multiple asserts of sEN may not be seen at the destination side.
// Reset signal is not needed since it a pulse-based, rather than
// level-based protocol
// Delay is 2 dCLK cycle.
// dPulse is not registered.
module SyncPulse(
sCLK,
sRST,
dCLK,
sEN,
dPulse
);
// source clock ports
input sCLK ;
input sRST ;
input sEN ;
// destination clock ports
input dCLK ;
output dPulse ;
// Flops to hold data
reg sSyncReg;
reg dSyncReg1, dSyncReg2;
reg dSyncPulse;
assign dPulse = dSyncReg2 != dSyncPulse ;
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
sSyncReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
else
begin
if ( sEN )
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY ! sSyncReg ;
end
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
always @(posedge dCLK or `BSV_RESET_EDGE sRST )
begin
if (sRST == `BSV_RESET_VALUE)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
dSyncPulse <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sSyncReg ;// domain crossing
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
dSyncPulse <= `BSV_ASSIGNMENT_DELAY dSyncReg2 ;
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
sSyncReg = 1'b0 ;
dSyncReg1 = 1'b0 ;
dSyncReg2 = 1'b0 ;
dSyncPulse = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // PulseSync
|
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* $Id: sqrt32synth.v,v 1.2 2007/08/30 01:25:29 stevewilliams Exp $"
*/
/*
* This module approximates the square root of an unsigned 32bit
* number. The algorithm works by doing a bit-wise binary search.
* Starting from the most significant bit, the accumulated value
* tries to put a 1 in the bit position. If that makes the square
* too big for the input, the bit is left zero, otherwise it is set
* in the result. This continues for each bit, decreasing in
* significance, until all the bits are calculated or all the
* remaining bits are zero.
*
* Since the result is an integer, this function really calculates
* value of the expression:
*
* x = floor(sqrt(y))
*
* where sqrt(y) is the exact square root of y and floor(N) is the
* largest integer <= N.
*
* For 32bit numbers, this will never run more then 16 iterations,
* which amounts to 16 clocks.
*/
module sqrt
(input clk,
output wire rdy,
input reset,
input [31:0] x,
output reg [15:0] acc);
//32
parameter ss=5; localparam w=1<<ss; //need to change in 2 places 1/2
// acc holds the accumulated result, and acc2 is the accumulated
// square of the accumulated result.
//reg [w/2-1:0] acc;
reg [w-1:0] acc2;
// Keep track of which bit I'm working on.
reg [ss-1:0] bitl;
wire [w/2-1:0] bit = 1 << bitl;
wire [w-1:0] bit2 = 1 << (bitl << 1);
// The output is ready when the bitl counter underflows.
assign rdy = bitl[ss-1];
// guess holds the potential next values for acc, and guess2 holds
// the square of that guess. The guess2 calculation is a little bit
// subtle. The idea is that:
//
// guess2 = (acc + bit) * (acc + bit)
// = (acc * acc) + 2*acc*bit + bit*bit
// = acc2 + 2*acc*bit + bit2
// = acc2 + 2 * (acc<<bitl) + bit
//
// This works out using shifts because bit and bit2 are known to
// have only a single bit in them.
wire [w/2-1:0] guess = acc | bit;
wire [w-1:0] guess2 = acc2 + bit2 + ((acc << bitl) << 1);
(* ivl_synthesis_on *)
always @(posedge clk or posedge reset)
if (reset) begin
acc = 0;
acc2 = 0;
bitl = w/2-1;
end else begin
if (guess2 <= x) begin
acc <= guess;
acc2 <= guess2;
end
bitl <= bitl - 1;
end
endmodule // sqrt
module testBench;
parameter ss=5; parameter w=1<<ss; //need to change in 2 places 2/2
//parameter Amax= ;
parameter Amax= 10001; //quick test
reg [w-1:0] A;
reg clk, reset;
wire [(w/2)-1:0] Z;
wire done;
sqrt dut (.clk(clk), .rdy(done), .reset(reset), .x(A), .acc(Z));
(* ivl_synthesis_off *)
always #5 clk = !clk;
task reset_dut ;
begin
reset = 1;
@(posedge clk);
#1 reset = 0;
@(negedge clk);
end
endtask
task run_dut ;
begin
while (done==0)
begin
@(posedge clk);
end
end
endtask
integer idx, a, z, errCnt;
(* ivl_synthesis_off *)
initial
begin
reset = 0;
clk = 0;
$display ("ss=%d, width=%d, Amax=%d", ss, w, Amax);
errCnt = 0;
A = 4;
reset_dut;
run_dut;
$display("test=0 x=%d, y=%d", A, Z);
A = Amax/10;
reset_dut;
run_dut;
$display("test=0 x=%d, y=%d", A, Z);
A = Amax-1;
reset_dut;
run_dut;
$display("test=0 x=%d, y=%d", A, Z);
for (idx = 1 ; idx < Amax; idx = 2*idx) begin
A = idx;
reset_dut;
run_dut;
$display("%d: x=%d, y=%d", idx, A, Z);
a = A;
z = Z;
if (a < (z *z)) begin
$display("test=%d x=%d, y=%d ERROR:y is too big", idx, A, Z);
$display("FAILED");
$finish;
end
if (z<65535) // at this number y*y overflows, so cannot test this way
begin
if (a >= ((z + 1)*(z + 1)))
begin
$display("test=%d x=%d, y=%d ERROR: y is too small", idx, A, Z);
$display("FAILED");
$finish;
end
end
else
begin
$display ("Could not verify above number");
end
end
$display ("Running tests Amax=%d random input numbers", Amax);
for (idx = 0 ; idx < Amax; idx = 1+ idx) begin
A = $random;
// A = A - ((A / Amax) * Amax); //this is needed only if <32 bit
//A = idx; //sequential -- comment out to get random tests
if (A < 1<<(w-1)) begin
reset_dut;
run_dut;
//$display("%d: x=%d, y=%d", idx, A, Z);
a = A;
z = Z;
if (a < (z *z)) begin
$display("test=%d x=%d, y=%d ERROR:y is too big", idx, A, Z);
$display("FAILED");
$finish;
end
if (z<65535) // at this number y*y overflows, so cannot test this way
begin
if (a >= ((z + 1)*(z + 1)))
begin
$display("test=%d x=%d, y=%d ERROR: y is too small", idx, A, Z);
$display("FAILED");
$finish;
end
end
else
begin
$display ("Could not verify above number");
end
//$display("%d: x=%d, y=%d", idx, A, Z);
if (idx%1000 == 0) $display("Finished %d tests", idx);
end // if (A < Amax) begin
end
$display ("PASSED");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, i; long long a[2019]; int b[2100], ok[2100]; const int MAXN = 2000; long long C[MAXN + 1][MAXN + 1]; void init() { int i, j; for (i = 0; i <= MAXN; ++i) { C[0][i] = 0; C[i][0] = 1; } for (i = 1; i <= MAXN; ++i) { for (j = 1; j <= MAXN; ++j) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % 1000000007; } } int main() { init(); int T, j; a[1] = 0; a[2] = 1; for (i = 3; i <= 2001; i++) a[i] = (i - 1) * ((a[i - 1] + a[i - 2])) % 1000000007; cin >> n; int p = 0; int flag = 1; for (i = 1; i <= n; i++) { int x; cin >> x; if (x != -1) { p++; ok[i] = 1; } if (x != -1) b[x] = 1; } if (n == 2) { cout << 1 << endl; return 0; } long long ans = 1; for (i = 2; i <= n - p; i++) ans = ans * i % 1000000007; long long t = 0, r = n - p; for (i = 1; i <= n; i++) if (ok[i] == 0 && b[i] == 0) t++; int f = 1; for (i = 1; i <= t; i++) { long long tmp = C[t][i] % 1000000007; for (j = 2; j <= n - p - i; j++) tmp = tmp * j % 1000000007; ans -= f * tmp % 1000000007; ans %= 1000000007; ans += 1000000007; ans %= 1000000007; f = -f; } cout << ans << endl; } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module timestamp_core
#(
parameter ABUSWIDTH = 16,
parameter IDENTIFIER = 4'b0001
)(
input wire CLK,
input wire DI,
input wire EXT_ENABLE,
input wire [63:0] EXT_TIMESTAMP,
output wire [63:0] TIMESTAMP_OUT,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD
);
localparam VERSION = 2;
//output format:
//31-28: ID, 27-24: 0x1, 23-0: 23-0th bit of timestamp data
//31-28: ID, 27-24: 0x2, 23-0: 47-24th bit of timestamp data
//31-28: ID, 27-24: 0x3, 23-16: 0x00, 15-0: 63-48th bit timestamp data
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg CONF_EN, CONF_EXT_ENABLE; //TODO add enable/disable by software
reg CONF_EXT_TIMESTAMP;
reg [7:0] LOST_DATA_CNT;
always @(posedge BUS_CLK) begin
if(RST) begin
CONF_EN <= 0;
CONF_EXT_TIMESTAMP <=0;
CONF_EXT_ENABLE <= 0;
end
else if(BUS_WR) begin
if(BUS_ADD == 2)
CONF_EN <= BUS_DATA_IN[0];
CONF_EXT_TIMESTAMP <=BUS_DATA_IN[1];
CONF_EXT_ENABLE <=BUS_DATA_IN[2];
end
end
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {6'b0,CONF_EXT_TIMESTAMP, CONF_EN};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= LOST_DATA_CNT;
else
BUS_DATA_OUT <= 8'b0;
end
end
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire EN_SYNC;
assign EN_SYNC= CONF_EN | ( EXT_ENABLE & CONF_EXT_ENABLE);
reg [7:0] sync_cnt;
always@(posedge BUS_CLK) begin
if(RST)
sync_cnt <= 120;
else if(sync_cnt != 100)
sync_cnt <= sync_cnt +1;
end
wire RST_LONG;
assign RST_LONG = sync_cnt[7];
reg [1:0] DI_FF;
wire DI_SYNC;
always@(posedge CLK) begin
if(RST_SYNC)
DI_FF <=2'b0;
else
DI_FF <= {DI_FF[0],DI};
end
assign DI_SYNC = ~DI_FF[1] & DI_FF[0];
reg [63:0] curr_timestamp;
always@(posedge CLK) begin
if(RST_SYNC)
curr_timestamp <= 0;
else
curr_timestamp <= curr_timestamp + 1;
end
reg [63:0] timestamp_out;
reg [1:0] cdc_fifo_write_reg;
reg [3:0] bit_cnt;
always@(posedge CLK) begin //TODO better fo separate cdc_fifo_write_reg?
if(RST_SYNC | ~EN_SYNC) begin
timestamp_out <= 0;
cdc_fifo_write_reg<=0;
end
else if(DI_SYNC & cdc_fifo_write_reg==0) begin
if (CONF_EXT_TIMESTAMP)
timestamp_out <= EXT_TIMESTAMP;
else
timestamp_out <= curr_timestamp;
cdc_fifo_write_reg<=1;
end
else if (cdc_fifo_write_reg==1)
cdc_fifo_write_reg<=2;
else
cdc_fifo_write_reg<=0;
end
assign TIMESTAMP_OUT=timestamp_out;
wire [63:0] cdc_data_in;
assign cdc_data_in = timestamp_out;
wire cdc_fifo_write;
assign cdc_fifo_write = cdc_fifo_write_reg[1];
wire fifo_full,fifo_write,cdc_fifo_empty;
wire wfull;
always@(posedge CLK) begin
if(RST_SYNC)
LOST_DATA_CNT <= 0;
else if (wfull && cdc_fifo_write && LOST_DATA_CNT != -1)
LOST_DATA_CNT <= LOST_DATA_CNT +1;
end
wire [63:0] cdc_data_out;
wire cdc_fifo_read;
cdc_syncfifo
#(.DSIZE(64), .ASIZE(8))
cdc_syncfifo_i
(
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(cdc_data_in),
.winc(cdc_fifo_write), .wclk(CLK), .wrst(RST_LONG),
.rinc(cdc_fifo_read), .rclk(BUS_CLK), .rrst(RST_LONG)
);
reg [1:0] byte2_cnt, byte2_cnt_prev;
always@(posedge BUS_CLK)
byte2_cnt_prev <= byte2_cnt;
assign cdc_fifo_read = (byte2_cnt_prev==0 & byte2_cnt!=0);
assign fifo_write = byte2_cnt_prev != 0;
always@(posedge BUS_CLK)
if(RST)
byte2_cnt <= 0;
else if(!cdc_fifo_empty && !fifo_full && byte2_cnt == 0 )
byte2_cnt <= 3;
else if (!fifo_full & byte2_cnt != 0)
byte2_cnt <= byte2_cnt - 1;
reg [63:0] data_buf;
always@(posedge BUS_CLK)
if(cdc_fifo_read)
data_buf <= cdc_data_out;
wire [31:0] fifo_write_data_byte [3:0];
assign fifo_write_data_byte[0]={IDENTIFIER,4'b0001,data_buf[23:0]};
assign fifo_write_data_byte[1]={IDENTIFIER,4'b0010,data_buf[47:24]};
assign fifo_write_data_byte[2]={IDENTIFIER,4'b0011,8'b0,data_buf[63:48]};
wire [31:0] fifo_data_in;
assign fifo_data_in = fifo_write_data_byte[byte2_cnt];
gerneric_fifo #(.DATA_SIZE(32), .DEPTH(1024)) fifo_i
( .clk(BUS_CLK), .reset(RST_LONG | BUS_RST),
.write(fifo_write),
.read(FIFO_READ),
.data_in(fifo_data_in),
.full(fifo_full),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA[31:0]), .size()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 15; const int K = 500; int a[N][N]; const int INF = 1e9 + 7; int calc(int x, int y, int h, int w) { int cnt = 0; for (int i = x; i < x + h; i++) { for (int j = y; j < y + w; j++) { cnt += a[i][j]; } } return cnt; } int main() { int r, c; int n, k; cin >> r >> c >> n >> k; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; x--; y--; a[x][y] = 1; } int ans = 0; for (int d = 1; d <= r; d++) { for (int w = 1; w <= c; w++) { for (int i = 0; i + d - 1 < r; i++) { for (int j = 0; j + w - 1 < c; j++) { if (calc(i, j, d, w) >= k) ans++; } } } } cout << ans; } |
#include <bits/stdc++.h> using namespace std; typedef long long ll; typedef long double ld; typedef string str; #define pb push_back #define ppp pop_back #define pii pair<int,int> #define fi first #define se second #define stie std::tie #define vec vector #define forn(i, l, r) for (int i=l; i<=r; i++) #define forb(i, r, l) for (int i=r; i>=l; i--) #define emp empty #define beg begin #define ins insert #define cle clear #define era erase #define que queue #define pque priority_queue #define mset multiset #define deq deque #define sta stack #define con const #define rsz resize #define ass assign #define lowb lower_bound #define uppb upper_bound template<class T> void mini(T& a, T b) { a = min(a, b); } template<class T> void maxi(T& a, T b) { a = max(a, b); } template<class T1, class T2> ostream& operator<<(ostream &out, pair<T1, T2> a) { return out << a.first << << a.second; } template<class T> ostream& operator<<(ostream& out, vector<T> a) { for (auto& i : a) out << i << ; return out; } template<class T> ostream& operator<<(ostream& out, set<T> a) { for (auto& i : a) out << i << ; return out; } template<class T> ostream& operator<<(ostream& out, multiset<T> a) { for (auto& i : a) out << i << ; return out; } template<class T1, class T2> ostream& operator<<(ostream& out, map<T1, T2> a) { for (auto& i : a) out << i << n ; return out; } template<class T1, class T2> ostream& operator<<(ostream& out, unordered_map<T1, T2> a) { for (auto& i : a) out << i << n ; return out; } template<class T> ostream& operator<<(ostream& out, queue<T> a) { while (!a.empty()) { out << a.front() << ; a.pop(); } return out; } template<class T> ostream& operator<<(ostream& out, deque<T> a) { while (!a.empty()) { out << a.front() << ; a.pop_front(); } return out; } template<class T> ostream& operator<<(ostream& out, priority_queue<T> a) { while (!a.empty()) { out << a.top() << n ; a.pop(); } return out; } template<class T> void out(T a) { cout << a << endl; } template<class T1, class T2> void out(T1 a, T2 b) { cout << a << << b << endl; } template<class T1, class T2, class T3> void out(T1 a, T2 b, T3 c) { cout << a << << b << << c << endl; } template<class T1, class T2, class T3, class T4> void out(T1 a, T2 b, T3 c, T4 d) { cout << a << << b << << c << << d << endl; } template<class T> void out(vector<vector<T>> a) { for (vector<T> i : a) out(i); } template<class T> void out_(T a[], int l, int r) { for (int i = l; i <= r; i++) cout << a[i] << ; cout << endl; } void out() { cout << OK << endl; } template<class T> void sort(vector<T>& a) { sort(a.begin(), a.end()); } template<class T> void uniq(vector<T>& a) { sort(a); a.erase(unique(a.begin(), a.end()), a.end()); } template<class T> vector<T> set_int(vector<T> a, vector<T> b) { sort(a); sort(b); vector<T> res; set_intersection(a.begin(), a.end(), b.begin(), b.end(), back_inserter(res)); return res; } clock_t start_time; void start_timer() { start_time = clock(); } double get_time() { return (double)(clock() - start_time) / CLOCKS_PER_SEC; } #if __SIZEOF_INT128__ >= 16 typedef __int128 LL; istream& operator>>(istream& in, __int128& a) { int64_t b; cin >> b; a = b; return in; } ostream& operator<<(ostream& out, const __int128 a) { unsigned __int128 b = a < 0 ? -a : a; char buf[128]; char* c = end(buf); do { --c; *c = 0123456789 [b % 10]; b /= 10; } while (b); if (a < 0) { --c; *c = - ; } int len = end(buf) - c; out.rdbuf()->sputn(c, len); return out; } #endif vec<str> lets = { . , . . , .. , .. . , . . , ... , .... , . .. , .. , ... , . . , . . . , .. . , .. .. , . .. , ... . , ..... , . ... , .. . , .... , . .. , . . .. , ... . , .. .. , .. ... , . ... }; void Solve() { int T; cin >> T; while (T--) { vec<int> a(5); forn(i, 0, 4) cin >> a[i]; int res = -1; forn(i, 0, 25) { vec<int> cur(5); forn(j, 0, 5) { if (lets[i][j] == . ) { cur[j / 2]++; cur[3 + j % 2]++; } } if (cur == a) { res = i; break; } } cout << char( a + res); } cout << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); #ifdef LOCAL freopen( input.txt , r , stdin); #endif start_timer(); Solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; struct Edge { int to, nxt; } e[N << 1]; int h[N], idx, a[N]; void Ins(int a, int b) { e[++idx].to = b; e[idx].nxt = h[a]; h[a] = idx; } long long dis[N], siz[N]; void dfs(int u, int fa) { siz[u] = a[u]; for (int i = h[u]; i; i = e[i].nxt) { int v = e[i].to; if (v == fa) continue; dfs(v, u); siz[u] += siz[v]; dis[1] += siz[v]; } } long long sum; void dfs1(int u, int fa) { for (int i = h[u]; i; i = e[i].nxt) { int v = e[i].to; if (v == fa) continue; dis[v] = dis[u] + sum - 2ll * siz[v]; dfs1(v, u); } } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]), sum += a[i]; for (int i = 2; i <= n; i++) { int x, y; scanf( %d%d , &x, &y); Ins(x, y); Ins(y, x); } dfs(1, 0); dfs1(1, 0); long long res = 0; for (int i = 1; i <= n; i++) res = max(res, dis[i]); printf( %lld n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; int id[200005], sz[200005]; vector<pair<int, int> > edges; int n, m, s1, s2, l1, l2; bool bad(int x) { return x == s1 || x == s2; } bool cmp(pair<int, int> p1, pair<int, int> p2) { bool b1 = bad(p1.first) || bad(p1.second); bool b2 = bad(p2.first) || bad(p2.second); if (b1 ^ b2) return b1 ? false : true; return p1 < p2; } int root(int x) { if (x == id[x]) return x; return id[x] = root(id[x]); } vector<pair<int, int> > ans; bool merge(int x, int y) { int xx = x, yy = y; x = root(x); y = root(y); if (x == y) return false; if (sz[x] < sz[y]) swap(x, y); id[y] = x; sz[x] += sz[y]; ans.push_back(make_pair(xx, yy)); return true; } int ok1[200005], ok2[200005]; int main() { ios::sync_with_stdio(false); scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) id[i] = i, sz[i] = 1, ok1[i] = ok2[i] = -1; for (int i = 0; i < m; i++) { int u, v; scanf( %d%d , &u, &v); edges.push_back(make_pair(u - 1, v - 1)); } scanf( %d%d%d%d , &s1, &s2, &l1, &l2); --s1; --s2; sort(edges.begin(), edges.end(), cmp); int ind = 0; while (ind < int(edges.size())) if (bad(edges[ind].first) || bad(edges[ind].second)) break; else merge(edges[ind].first, edges[ind].second), ind++; for (int i = ind; i < int(edges.size()); i++) { if (edges[i].first == s1) ok1[root(edges[i].second)] = edges[i].second; if (edges[i].second == s1) ok1[root(edges[i].first)] = edges[i].first; if (edges[i].first == s2) ok2[root(edges[i].second)] = edges[i].second; ; if (edges[i].second == s2) ok2[root(edges[i].first)] = edges[i].first; } int a = 0, b = 0, c = 0; for (int i = 0; i < n; i++) if (root(i) == i && i != s1 && i != s2) { if (ok1[i] != -1 && ok2[i] != -1) c++; else if (ok1[i] != -1) a++; else if (ok2[i] != -1) b++; else { puts( No ); return 0; } } if (a >= l1 || b >= l2) { puts( No ); return 0; } l1 -= a; l2 -= b; if (c + 1 > l1 + l2) { puts( No ); return 0; } for (int i = 0; i < n; i++) if (root(i) == i && i != s1 && i != s2) { if (ok1[i] != -1 && ok2[i] != -1) continue; else if (ok1[i] != -1) merge(s1, ok1[i]); else if (ok2[i] != -1) merge(s2, ok2[i]); else { puts( No ); return 0; } } int lst = -1; for (int i = 0; i < n; i++) if (root(i) == i && i != s1 && i != s2) { if (ok1[i] != -1 && ok2[i] != -1) { if (l1 > 1) merge(s1, ok1[i]), l1--, lst = 1; else merge(s2, ok2[i]), l2--, lst = 2; } } if (ok2[s1] != -1 && l1 >= 1 && l2 >= 1) merge(s1, s2); else if (lst == -1) { puts( No ); return 0; } else { for (int i = n - 1; i >= 0; i--) if (ok1[i] != -1 && ok2[i] != -1) { if (lst == 2 && l1 > 0) merge(s1, ok1[i]), l1--; else if (lst == 1 && l2 > 0) merge(s2, ok2[i]), l2--; else { puts( No ); return 0; } break; } } puts( Yes ); for (int i = 0; i < int(ans.size()); i++) printf( %d %d n , ans[i].first + 1, ans[i].second + 1); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__NOR4BB_BEHAVIORAL_PP_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4bb (
VPWR,
VGND,
Y ,
A ,
B ,
C_N ,
D_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
// Local signals
wire DN nor0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4BB_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> const int md = 1e9 + 7; const long long hs = 199; const long double eps = 1e-9, pi = acos(-1); using namespace std; struct node { int val, x, y; node(int _v = -1, int _x = -1, int _y = -1) { val = _v, x = _x, y = _y; } }; struct query { int t, x, y; query(int _t = 0, int _x = 0, int _y = 0) : t(_t), x(_x), y(_y){}; }; struct segtree { int n; vector<node> tree; segtree(int size) { n = size; tree.resize(2 * n, -1); } void fix(int x) { tree[x].val = max(tree[2 * x + 1].val, tree[2 * x + 2].val); } void insert(int i, node a) { i += n - 1; tree[i] = a; for (i = (i - 1) / 2; i; i = (i - 1) / 2) fix(i); fix(0); } void erase(int i) { i += n - 1; tree[i] = node(); for (i = (i - 1) / 2; i; i = (i - 1) / 2) fix(i); fix(0); } int query(int l, int r) { int rtn = -2e9; for (l += n - 1, r += n - 1; l < r; l = (l - 1) / 2, r = (r - 1) / 2) { if (!(l & 1)) rtn = max(rtn, tree[l++].val); if (r & 1) rtn = max(rtn, tree[r--].val); } if (l == r) rtn = max(rtn, tree[l].val); return rtn; } pair<int, int> bs(int st, int x) { int lo = st, hi = n - 1, mid; while (lo < hi) { mid = lo + (hi - lo) / 2; if (query(st, mid) > x) hi = mid; else lo = mid + 1; } if (query(st, lo) <= x) return {-1, -1}; return {tree[lo + n - 1].x, tree[lo + n - 1].y}; } }; string temp; int n, p1, p2; map<pair<int, int>, int> m; vector<query> q; vector<int> stfrom; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; q.resize(n); for (int i = 0; i < n; i++) { cin >> temp >> p1 >> p2; if (temp[0] == a ) q[i] = query(0, p1, p2); else if (temp[0] == r ) q[i] = query(1, p1, p2); else q[i] = query(2, p1, p2); if (q[i].t != 2) m[{p1, p2}] = -1; } if (m.size() == 0) { while (n--) cout << -1 << n ; return 0; } int x = 0; for (auto i = m.begin(); i != m.end(); i++, x++) i->second = x; stfrom.resize(m.size()); (stfrom)[(stfrom).size() - (1)] = -1; if (m.size() > 1) { auto it1 = m.rbegin(), it2 = it1; it2++; x = stfrom.size() - 2; for (; it2 != m.rend(); it1++, it2++, x--) { if (it2->first.first == it1->first.first) stfrom[x] = stfrom[x + 1]; else stfrom[x] = x + 1; } } segtree seg = segtree(m.size()); for (auto &i : q) { if (i.t == 0) seg.insert(m[{i.x, i.y}], node(i.y, i.x, i.y)); else if (i.t == 1) seg.erase(m[{i.x, i.y}]); else { auto it = m.upper_bound({i.x, i.y}); if (it == m.end()) printf( -1 n ); else { int at; if (it->first.first > i.x) at = it->second; else at = stfrom[it->second]; if (at == -1) printf( -1 n ); else { pair<int, int> rtn = seg.bs(at, i.y); if (rtn.first == -1) printf( -1 n ); else printf( %d %d n , rtn.first, rtn.second); } } } } } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2012.2
// Copyright (C) 2012 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module types_float_double_grp_fu_93_ACMP_dmul_3_io(
clk,
reset,
io_ce,
io_rdy,
io_a,
io_b,
io_result);
input clk;
input reset;
input io_ce;
output io_rdy;
input[64 - 1:0] io_a;
input[64 - 1:0] io_b;
output[64 - 1:0] io_result;
//floating_point_v5_0 m(
multiplier64fp m(
.clk(clk),
.ce(io_ce),
.rdy(io_rdy),
.a(io_a),
.b(io_b),
.result(io_result));
endmodule
//module floating_point_v5_0(
module multiplier64fp(
clk,
ce,
rdy,
a,
b,
result);
input clk;
input ce;
output rdy;
input[64 - 1:0] a;
input[64 - 1:0] b;
output[64 - 1:0] result;
//ACMP_dmul #(
//.ID( ID ),
//.NUM_STAGE( 18 ),
//.din0_WIDTH( din0_WIDTH ),
//.din1_WIDTH( din1_WIDTH ),
//.dout_WIDTH( dout_WIDTH ))
//ACMP_dmul_U(
// .clk( clk ),
// .reset( reset ),
// .ce( ce ),
// .din0( din0 ),
// .din1( din1 ),
// .dout( dout ));
//assign io_dout = io_din0 + io_din1;
endmodule
|
`include "defines.v"
module brouter
#(parameter addr = 4'b0101)
(
input `control_w port0_ci,
input `control_w port1_ci,
input `control_w port2_ci,
input `control_w port3_ci,
input `control_w port4_ci,
input `data_w port0_di,
input `data_w port1_di,
input `data_w port2_di,
input `data_w port3_di,
input `data_w port4_di,
input clk,
input rst,
output `control_w port0_co,
output `control_w port1_co,
output `control_w port2_co,
output `control_w port3_co,
output `control_w port4_co,
output `data_w port0_do,
output `data_w port1_do,
output `data_w port2_do,
output `data_w port3_do,
output `data_w port4_do,
output port4_ready);
// Config
wire `addrx_w addrx, max_addrx;
wire `addry_w addry, max_addry;
assign addrx = addr[`addrx_f]; // This nodes x address
assign addry = addr[`addry_f]; // This nodes y address
assign max_addrx = `addrx_max;
assign max_addry = `addry_max;
// Input wires for reset
wire `control_w port0_cin, port1_cin, port2_cin, port3_cin, port4_cin;
assign port0_cin = (rst) ? `control_n'd0 : port0_ci;
assign port1_cin = (rst) ? `control_n'd0 : port1_ci;
assign port2_cin = (rst) ? `control_n'd0 : port2_ci;
assign port3_cin = (rst) ? `control_n'd0 : port3_ci;
assign port4_cin = (rst) ? `control_n'd0 : port4_ci;
// Resource Ready Wires
wire all_valid;
wire resource_go0, resource_go1, resource_go2, resource_go3;
// Cross Stage Wires
wire `control_w port0_c1, port1_c1, port2_c1, port3_c1, port4_c1;
wire `data_w port0_d1, port1_d1, port2_d1, port3_d1, port4_d1;
wire `control_w port0_c2, port1_c2, port2_c2, port3_c2, port4_c2;
wire `data_w port0_d2, port1_d2, port2_d2, port3_d2, port4_d2;
// Routing Matrices
wire `rmatrix_w rmatrix0, rmatrix1, rmatrix2, rmatrix3, rmatrix4;
// Final Route
wire `routecfg_w route_config;
/************* STAGE 1 *************/
reg `control_w port0_r, port1_r, port2_r, port3_r, port4_r;
always @(posedge clk) begin
port0_r <= port0_cin;
port1_r <= port1_cin;
port2_r <= port2_cin;
port3_r <= port3_cin;
port4_r <= port4_cin;
end
// Route Computation
RouteCompute rc0(.control_in(port0_r),
.addrx(addrx),
.addry(addry),
.addrx_max(max_addrx),
.addry_max(max_addry),
.clk(clk),
.resource_go(resource_go0),
.rmatrix(rmatrix0));
RouteCompute rc1(.control_in(port1_r),
.addrx(addrx),
.addry(addry),
.addrx_max(max_addrx),
.addry_max(max_addry),
.clk(clk),
.resource_go(resource_go1),
.rmatrix(rmatrix1));
RouteCompute rc2(.control_in(port2_r),
.addrx(addrx),
.addry(addry),
.addrx_max(max_addrx),
.addry_max(max_addry),
.clk(clk),
.resource_go(resource_go2),
.rmatrix(rmatrix2));
RouteCompute rc3(.control_in(port3_r),
.addrx(addrx),
.addry(addry),
.addrx_max(max_addrx),
.addry_max(max_addry),
.clk(clk),
.resource_go(resource_go3),
.rmatrix(rmatrix3));
RouteCompute rc4(.control_in(port4_r),
.addrx(addrx),
.addry(addry),
.addrx_max(max_addrx),
.addry_max(max_addry),
.clk(clk),
.resource_go(),
.rmatrix(rmatrix4));
age_incr age_s1 (.control0_in(port0_r),
.control1_in(port1_r),
.control2_in(port2_r),
.control3_in(port3_r),
.control4_in(port4_r),
.control4_ready(port4_ready),
.clk(clk),
.control0_out(port0_c1),
.control1_out(port1_c1),
.control2_out(port2_c1),
.control3_out(port3_c1),
.control4_out(port4_c1));
//always @(*) $display("RC out: %x %x %x %x (rmat %x %x %x %x)", port0_c1, port1_c1, port2_c1, port3_c1, rmatrix0, rmatrix1, rmatrix2, rmatrix3);
assign all_valid = port0_cin[`valid_f] &
port1_cin[`valid_f] &
port2_cin[`valid_f] &
port3_cin[`valid_f];
assign port4_ready = ~(all_valid) |
resource_go0 |
resource_go1 |
resource_go2 |
resource_go3;
data_buf data_s0(.data0_in(port0_di),
.data1_in(port1_di),
.data2_in(port2_di),
.data3_in(port3_di),
.data4_in(port4_di),
.clk(clk),
.data0_out(port0_d1),
.data1_out(port1_d1),
.data2_out(port2_d1),
.data3_out(port3_d1),
.data4_out(port4_d1));
/******** Stage 2 ********/
wire `routecfg_w route_config_unbuf;
arbitor arb(.rmatrix0(rmatrix0),
.rmatrix1(rmatrix1),
.rmatrix2(rmatrix2),
.rmatrix3(rmatrix3),
.rmatrix4(rmatrix4),
.control0_in(port0_c1),
.control1_in(port1_c1),
.control2_in(port2_c1),
.control3_in(port3_c1),
.control4_in(port4_c1),
.clk(clk),
.route_config_unbuf(route_config_unbuf),
.route_config(route_config));
ctl_xt cx(
.control0_in(port0_c1),
.control1_in(port1_c1),
.control2_in(port2_c1),
.control3_in(port3_c1),
.control4_in(port4_c1),
.route_config(route_config_unbuf),
.clk(clk),
.control0_out(port0_co),
.control1_out(port1_co),
.control2_out(port2_co),
.control3_out(port3_co),
.control4_out(port4_co));
data_buf data_s1(.data0_in(port0_d1),
.data1_in(port1_d1),
.data2_in(port2_d1),
.data3_in(port3_d1),
.data4_in(port4_d1),
.clk(clk),
.data0_out(port0_d2),
.data1_out(port1_d2),
.data2_out(port2_d2),
.data3_out(port3_d2),
.data4_out(port4_d2));
/*********** Stage 3 **********/
crossbar xbar(.data0_in(port0_d2),
.data1_in(port1_d2),
.data2_in(port2_d2),
.data3_in(port3_d2),
.data4_in(port4_d2),
.route_config(route_config),
.clk(clk),
.data0_out(port0_do),
.data1_out(port1_do),
.data2_out(port2_do),
.data3_out(port3_do),
.data4_out(port4_do));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__OR4B_BEHAVIORAL_PP_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:10:55 03/06/2016
// Design Name:
// Module Name: mult4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mult4(
input x0,
input x1,
input x2,
input x3,
input y0,
input y1,
input y2,
input y3,
output z0,
output z1,
output z2,
output z3,
output z4,
output z5,
output z6,
output z7
);
//productos
//wire p00; -> z0
wire p01;
wire p02;
wire p03;
wire p10;
wire p11;
wire p12;
wire p13;
wire p20;
wire p21;
wire p22;
wire p23;
wire p30;
wire p31;
wire p32;
wire p33;
//acarreos
wire c1;
wire c2;
wire c3;
wire c4;
wire c5;
wire c6;
wire c7;
wire c8;
wire c9;
wire c10;
wire c11;
wire c12;
wire c13;
wire c14;
wire c15;
//sumas
wire s1;
wire s2;
wire s3;
wire s4;
wire s5;
wire s6;
wire s7;
wire s8;
and(z0, x0, y0); //z0
and(p01, x0, y1);
and(p02, x0, y2);
and(p03, x0, y3);
and(p10, x1, y0);
and(p11, x1, y1);
and(p12, x1, y2);
and(p13, x1, y3);
and(p20, x2, y0);
and(p21, x2, y1);
and(p22, x2, y2);
and(p23, x2, y3);
and(p30, x3, y0);
and(p31, x3, y1);
and(p32, x3, y2);
and(p33, x3, y3);
summed HA1(p01, p10, z1, c1); //z1
summed HA2(p11, p20, s1, c2);
sumcomp FA2(p02, s1, c1, z2, c3); //z2
sumcomp FA31(p21, p30, p12, s2, c4);
summed HA3(p03, s2, s3, c5);
sumcomp FA32(c2, s3, c3, z3, c6); //z3
sumcomp FA41(p22, p31, p13, s4, c7);
summed HA4(s4, c4, s5, c8);
sumcomp FA42(c5, s5, c6, z4, c9); //z4
summed HA51(p23, p32, s6, c10);
summed HA52(s6, c7, s7, c11);
sumcomp FA5(c8, s7, c9, z5, c12); //z5
summed HA6(p33, c10, s8, c13);
sumcomp FA6(c11, s8, c12, z6, c14); //z6
summed HA7(c13, c14, z7, c15); //z7
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / D Flip-Flop with Clock Enable and Asynchronous Preset
// /___/ /\ Filename : FDPE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 08/25/10 - Initial version.
// 10/20/10 - remove unused pin line from table.
// 11/01/11 - Disable timing check when set reset active (CR632017)
// 12/08/11 - add MSGON and XON attributes (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
primitive ffsrce_fdpe (q, ici, clk, d, ce, set, rst, notifier);
output q; reg q;
input ici, clk, d, ce, set, rst, notifier;
table
// ici clk d ce set rst notifier q q+;
? ? ? ? 1 0 ? : ? : 1;
? ? ? ? ? 1 ? : ? : 0;
? (??) ? 0 ? ? ? : ? : -;
0 (01) 0 1 0 0 ? : ? : 0;
0 (01) 1 1 0 0 ? : ? : 1;
1 (10) 0 1 0 0 ? : ? : 0;
1 (10) 1 1 0 0 ? : ? : 1;
0 (01) x 1 0 0 ? : ? : x;
0 (01) 0 x 0 0 ? : 0 : 0;
0 (01) 1 x 0 0 ? : 1 : 1;
1 (10) x 1 0 0 ? : ? : x;
1 (10) 0 x 0 0 ? : 0 : 0;
1 (10) 1 x 0 0 ? : 1 : 1;
0 (1?) ? ? ? ? ? : ? : -;
0 (?0) ? ? ? ? ? : ? : -;
1 (?1) ? ? ? ? ? : ? : -;
1 (0?) ? ? ? ? ? : ? : -;
0 (01) 0 1 0 x ? : ? : 0;
0 (01) 1 1 x 0 ? : ? : 1;
1 (10) 0 1 0 x ? : ? : 0;
1 (10) 1 1 x 0 ? : ? : 1;
? ? ? ? 0 (?x) ? : 0 : 0;
? ? ? ? (?x) 0 ? : 1 : 1;
0 (?1) 1 ? ? 0 ? : 1 : 1;
0 (?1) 0 ? 0 ? ? : 0 : 0;
0 (0?) 1 ? ? 0 ? : 1 : 1;
0 (0?) 0 ? 0 ? ? : 0 : 0;
1 (?0) 1 ? ? 0 ? : 1 : 1;
1 (?0) 0 ? 0 ? ? : 0 : 0;
1 (1?) 1 ? ? 0 ? : 1 : 1;
1 (1?) 0 ? 0 ? ? : 0 : 0;
? ? (??) ? ? ? ? : ? : -;
? ? ? (??) ? ? ? : ? : -;
? ? ? ? (?0) ? ? : ? : -;
? ? ? ? x (?0) ? : ? : x;
? ? ? ? 0 (?0) ? : ? : -;
? ? ? ? ? ? * : ? : x;
endtable
endprimitive
`celldefine
module FDPE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_PRE_INVERTED = 1'b0
)(
output Q,
input C,
input CE,
input D,
input PRE
);
wire o_out;
`ifdef XIL_TIMING
wire D_dly, C_dly, CE_dly;
wire PRE_dly;
`endif
wire D_in, CE_in;
wire PRE_in;
wire [0:0] IS_C_INVERTED_BIN;
wire [0:0] IS_D_INVERTED_BIN;
wire [0:0] IS_PRE_INVERTED_BIN;
reg q_out = INIT;
reg notifier;
wire notifier1;
reg rst_int, set_int;
`ifdef XIL_TIMING
wire ngsr, in_out;
wire ni, nset;
wire in_clk_enable, ce_clk_enable;
wire in_clk_enable1, ce_clk_enable1;
wire set_clk_enable, set_clk_enable1;
`endif
tri0 glblGSR = glbl.GSR;
assign Q = q_out;
`ifdef XIL_TIMING
not (ngsr, glblGSR);
xor (in_out, D_in, Q);
not (ni, D_in);
not (nset, PRE_in);
and (in_clk_enable, ngsr, nset, CE_in);
and (ce_clk_enable, ngsr, nset, in_out);
and (set_clk_enable, ngsr, CE_in, ni);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign ce_clk_enable1 = (MSGON =="TRUE") && ce_clk_enable;
assign in_clk_enable1 = (MSGON =="TRUE") && in_clk_enable;
assign set_clk_enable1 = (MSGON =="TRUE") && set_clk_enable;
`else
assign notifier1 = 1'bx;
`endif
always @(glblGSR or PRE_in)
if (glblGSR)
if (INIT) begin
set_int = 1'b1;
rst_int = 1'b0;
end
else begin
set_int = 1'b0;
rst_int = 1'b1;
end
else begin
set_int = PRE_in;
rst_int = 1'b0;
end
`ifdef XIL_TIMING
ffsrce_fdpe (o_out, IS_C_INVERTED_BIN, C_dly, D_in, CE_in, set_int, rst_int, notifier1);
`else
ffsrce_fdpe (o_out, IS_C_INVERTED_BIN, C, D_in, CE_in, set_int, rst_int, notifier1);
`endif
always @(o_out) q_out = o_out;
assign IS_C_INVERTED_BIN = IS_C_INVERTED;
assign IS_D_INVERTED_BIN = IS_D_INVERTED;
assign IS_PRE_INVERTED_BIN = IS_PRE_INVERTED;
`ifdef XIL_TIMING
assign CE_in = CE_dly || (CE === 1'bz);
assign D_in = D_dly ^ IS_D_INVERTED_BIN;
assign PRE_in = (PRE_dly ^ IS_PRE_INVERTED_BIN) && (PRE !== 1'bz);
`else
assign CE_in = CE || (CE === 1'bz);
assign D_in = D ^ IS_D_INVERTED_BIN;
assign PRE_in = (PRE ^ IS_PRE_INVERTED_BIN) && (PRE !== 1'bz);
`endif
specify
(C => Q) = (100:100:100, 100:100:100);
(negedge PRE => (Q +: 1)) = (0:0:0, 0:0:0);
(posedge PRE => (Q +: 1)) = (0:0:0, 0:0:0);
(PRE => Q) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge C &&& CE, 0:0:0, notifier);
$period (posedge C &&& CE, 0:0:0, notifier);
$recrem (negedge PRE, negedge C &&& (set_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,PRE_dly, C_dly);
$recrem (negedge PRE, posedge C &&& (set_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,PRE_dly, C_dly);
$recrem (posedge PRE, negedge C &&& (set_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,PRE_dly, C_dly);
$recrem (posedge PRE, posedge C &&& (set_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,PRE_dly, C_dly);
$setuphold (negedge C, negedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (negedge C, negedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (negedge C, posedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (negedge C, posedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (posedge C, negedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (posedge C, negedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (posedge C, posedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (posedge C, posedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$width (negedge C &&& CE, 0:0:0, 0, notifier);
$width (negedge PRE, 0:0:0, 0, notifier);
$width (posedge C &&& CE, 0:0:0, 0, notifier);
$width (posedge PRE, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; long long int a[200005]; long long int dist[200005]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long int n; cin >> n; for (long long int i = 0; i < n; i++) dist[i] = INT_MAX; for (long long int i = 0; i < n; i++) cin >> a[i]; long long int m = INT_MAX; for (long long int i = 0; i < n; i++) { if (a[i] == 0) { m = i; dist[i] = 0; } if (m == INT_MAX) { dist[i] = INT_MAX; continue; } dist[i] = min(dist[i], i - m); } m = INT_MAX; for (long long int i = n - 1; i > -1; i--) { if (a[i] == 0) { m = i; dist[i] = 0; } dist[i] = min(dist[i], m - i); } for (long long int i = 0; i < n; i++) cout << dist[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; if (m == 0) { cout << n << n ; return 0; } string hint[m]; getline(cin, hint[0]); vector<vector<string> > h(m); for (int i = 0; i < m; i++) { getline(cin, hint[i]); stringstream ss(hint[i]); string w; while (ss >> w) h[i].push_back(w); } int i; int ans = 0; for (i = 0; i < n; i++) { bool yes = true; for (int j = 0; j < m; j++) { if (h[j][2] == left ) { int k = atoi(h[j][4].c_str()) - 1; if (i >= k) { yes = false; break; } } else if (h[j][2] == right ) { int k = atoi(h[j][4].c_str()) - 1; if (i <= k) { yes = false; break; } } } if (yes) ans++; } if (ans == 0) ans = -1; cout << ans << n ; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 13:53:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_1/affine_block_uint_to_ieee754_fp_0_1_stub.v
// Design : affine_block_uint_to_ieee754_fp_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "uint_to_ieee754_fp,Vivado 2016.4" *)
module affine_block_uint_to_ieee754_fp_0_1(x, y)
/* synthesis syn_black_box black_box_pad_pin="x[9:0],y[31:0]" */;
input [9:0]x;
output [31:0]y;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[18] = {0}; long long int get(long long int n, int l) { if (!n) return 0; if (l == 1) return n; long long int t = a[l]; if (n == t) return l; if (n < t) return min(get(n, l - 1), l + get(t - n, l - 1)); else return min((n / t) * l + get(n % t, l - 1), ((1 + (n / t)) * l) + get(t - n % t, l - 1)); } int main() { long long int n, i, ans; scanf( %I64d , &n); for (int i = 1; i < 18; i++) a[i] = a[i - 1] * 10 + 1; for (i = 1; n > a[i]; i++) ; ans = get(n, i); printf( %I64d n , ans); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A311OI_FUNCTIONAL_PP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311OI_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O21AI_BEHAVIORAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/05/2016 04:17:53 PM
// Design Name:
// Module Name: pipelined_multiplier
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pipelined_multiplier #(parameter WL=32)(
input wire CLK,
input wire [WL-1:0] A,
input wire [WL-1:0] B,
output reg [(WL-1) * 2:0] Out
);
reg [(WL-1):0] a_in, b_in;
wire [(WL-1) * 2:0] multi_reg;
reg [(WL-1) * 2:0] pipe1, pipe2, pipe3, pipe4, pipe5;
assign multi_reg = a_in * b_in;
always @(posedge CLK) begin
a_in <= A; b_in <= B;
pipe1 <= multi_reg;
pipe2 <= pipe1;
pipe3 <= pipe2;
pipe4 <= pipe3;
pipe5 <= pipe4;
Out <= pipe5;
end
endmodule |
// --------------------------------------------------
//
// Multi-input router controller
//
// Router controller which takes multiple sources of traffic
// via input FIFOs, arbitrates amongst the sources of traffic
// that have data to transfer, and then delivers the data to
// the output FIFO controller. The delay parameter indicates
// how many clocks after pop to the input FIFO is data available.
//
// --------------------------------------------------
module router_ctrl
#( parameter CLIENTS=2,
parameter WIDTH=32,
parameter DELAY=1 )
(
input wire clk,
input wire reset,
// Connect to input FIFO's
input wire [CLIENTS-1:0] empty,
output wire [CLIENTS-1:0] pop,
input wire [CLIENTS*WIDTH-1:0] data_in,
// Connect to output FIFO
input wire full,
output reg push,
output wire [WIDTH-1:0] data_out,
// Connect to the arbiter
output wire cycle,
output wire [CLIENTS-1:0] req,
input wire [CLIENTS-1:0] gnt
);
reg [CLIENTS-1:0] pop_delay_chain [DELAY:0];
// Simple Connections
assign cycle = !full;
assign req = ~empty;
assign pop = gnt;
assign push = |pop_delay_chain[DELAY];
// Need to mux the data and rive the push signal. The mux signal and
// push signal need to be delayed some number of clocks.
always @ (*) begin
pop_delay_chain[0] = pop;
end
integer pdc_index;
always @ (posedge clk) begin
for( pdc_index=1; pdc_index<=DELAY; pdc_index=pdc_index+1 ) begin
if( reset ) begin
pop_delay_chain[pdc_index] <= #0 0;
end
else begin
pop_delay_chain[pdc_index] <= #0 pop_delay_chain[pdc_index-1];
end
end
end
// Mux the data
integer mux_index;
always @ (*) begin
data_out = {WIDTH{1'b0}};
for( mux_index=0; mux_index<CLIENTS; mux_index=mux_index+1 ) begin
if( pop_delay_chain[mux_index] ) begin
data_out = data_in[(mux_index+1)*WIDTH-1:mux_index*WIDTH];
end
end
end
endmodule
|
/*
* Copyright (c) 2000 Intrinsity, Inc.
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test_nmos ();
wire t0, t1, t2, t3, t4, t5, t6, t7,
t8, t9, ta, tb, tc, td, te, tf;
reg gnd, vdd, x, z;
reg failed;
wire StH, StL;
assign (strong1, highz0) StH = 1'bx;
assign (highz1, strong0) StL = 1'bx;
nmos n0 ( t0, gnd, gnd);
nmos n1 ( t1, gnd, vdd);
nmos n2 ( t2, gnd, x);
nmos n3 ( t3, gnd, z);
nmos n4 ( t4, vdd, gnd);
nmos n5 ( t5, vdd, vdd);
nmos n6 ( t6, vdd, x);
nmos n7 ( t7, vdd, z);
nmos n8 ( t8, x, gnd);
nmos n9 ( t9, x, vdd);
nmos na ( ta, x, x);
nmos nb ( tb, x, z);
nmos nc ( tc, z, gnd);
nmos nd ( td, z, vdd);
nmos ne ( te, z, x);
nmos nf ( tf, z, z);
initial begin
assign gnd = 1'b1;
assign vdd = 1'b0;
assign x = 1'b0;
assign z = 1'b0;
#10;
assign gnd = 1'b0;
assign vdd = 1'b1;
assign x = 1'b1;
assign z = 1'b1;
#10;
assign gnd = 1'b0;
assign vdd = 1'b1;
assign x = 1'bx;
assign z = 1'bz;
#10;
failed = 0;
if (t0 !== z)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", gnd, gnd, t0 );
end
if (t1 !== 0)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:0", gnd, vdd, t1 );
end
if (t2 !== StL)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:StL", gnd, x, t2 );
end
if (t3 !== StL)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:StL", gnd, z, t3 );
end
if (t4 !== 1'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", vdd, gnd, t4 );
end
if (t5 !== 1)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:0", vdd, vdd, t5 );
end
if (t6 !== StH)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:StH", vdd, x, t6 );
end
if (t7 !== StH)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:StH", vdd, z, t7 );
end
if (t8 !== 1'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", x, gnd, t8 );
end
if (t9 !== 1'bx)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:x", x, vdd, t9 );
end
if (ta !== 1'bx)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:x", x, x, ta );
end
if (tb !== 1'bx)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:x", x, z, tb );
end
if (tc !== 1'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, gnd, tc );
end
if (td !== 1'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, vdd, td );
end
if (te !== 1'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, x, te );
end
if (tf !== 1'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, z, tf );
end
if (failed == 0)
$display ("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k; long long ans; long long matriz[505][505]; int main() { ans = 0; cin >> n >> k; long long aux = (n - k + 1) * n; aux = n * n - aux + 1; long long curr1 = 1; long long curr2 = aux; for (int i = 0; i < n; ++i) { int j = 0; for (; j < k - 1; ++j) { matriz[i][j] = curr1; curr1++; } ans += curr2; matriz[i][j] = curr2; curr2++; j++; for (; j < n; ++j) { matriz[i][j] = curr2; curr2++; } } cout << ans << endl; for (int i = 0; i < n; ++i) { for (int j = 0; j < n - 1; ++j) { cout << matriz[i][j] << ; } cout << matriz[i][n - 1] << endl; } return 0; } |
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); int n1 = n, dig, x = 0, y = 0, z = 0, r; while (n1 > 0) { dig = n1 % 10; if (dig != 4 && dig != 7) { x++; break; } n1 = n1 / 10; } if (x == 0) { printf( YES ); z++; } else if (x > 0) { for (int i = 1; i < n; i++) { y = 0; n1 = i; while (n1 > 0) { dig = n1 % 10; if (dig != 4 && dig != 7) { y++; break; } n1 = n1 / 10; } if (y == 0 && n % i == 0) { printf( YES ); z++; break; } } } if (z == 0) { printf( NO ); } return 0; } |
module crc_gen (
input Reset,
input Clk,
input Init,
input [7:0] Frame_data,
input Data_en,
input CRC_rd,
output [31:0] CRC_out,
output reg CRC_end
);
reg [31:0] CRC_reg;
reg [3:0] Counter;
function[31:0] NextCRC;
input[7:0] D;
input[31:0] C;
reg[31:0] NewCRC;
begin
NewCRC[0]=C[24]^C[30]^D[1]^D[7];
NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];
NewCRC[20]=C[12]^C[28]^D[3];
NewCRC[21]=C[13]^C[29]^D[2];
NewCRC[22]=C[14]^C[24]^D[7];
NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];
NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];
NewCRC[31]=C[23]^C[29]^D[2];
NextCRC=NewCRC;
end
endfunction
always @ ( negedge Clk )
if (Reset)
CRC_reg <= 32'hffffffff;
else
CRC_reg <= Init ? 32'hffffffff : Data_en ? NextCRC(Frame_data, CRC_reg ) : CRC_reg;
assign CRC_out = ~{ CRC_reg[24],CRC_reg[25],CRC_reg[26],CRC_reg[27],CRC_reg[28],CRC_reg[29],CRC_reg[30],CRC_reg[31], CRC_reg[16],CRC_reg[17],CRC_reg[18],CRC_reg[19],CRC_reg[20],CRC_reg[21],CRC_reg[22],CRC_reg[23], CRC_reg[ 8],CRC_reg[ 9],CRC_reg[10],CRC_reg[11],CRC_reg[12],CRC_reg[13],CRC_reg[14],CRC_reg[15], CRC_reg[ 0],CRC_reg[ 1],CRC_reg[ 2],CRC_reg[ 3],CRC_reg[ 4],CRC_reg[ 5],CRC_reg[ 6],CRC_reg[ 7] };
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a, b; int main() { cin >> n >> a >> b; n -= a; b++; cout << (n > b ? b : n); return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module handles the interface between the memory controller and the
// drawing engine. It aligns and breaks up requests into four page bursts,
// breaks up read-modify-write cycles and controls the datapath for
// drawing engine data (including blending, rops, z-masking, and keying
// support).
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module mc_de
#(parameter BYTES = 4)
(
/* Clocks and resets */
input mclock,
input reset_n,
// Signals from the 2D cache
input line_actv_4,
input de_read,
input de_rmw,
input de_pc_empty,
input [3:0] de_page,
input [31:0] de_address,
/* Data movement signals */
input de_push,
input de_almost_full,
input de_zen,
output reg fifo_push,
output de_popen,
output reg de_last,
output reg de_last4,
output reg de_pc_pop,
/* Arbiter interface signals */
output reg [1:0] de_arb_cmd, // Command to arb: 0 = wr, 1 = rd, 2 = rmw
output reg [31:0] de_arb_address,
/* Datapath control signals */
output reg mcb, // Memory controller busy DE operation
output reg de_push_mff,
output reg de_push_mff_z,
output reg de_push_mff_a
);
localparam // DE = 3'h4,
IDLE = 2'b00,
WAIT_GRAB = 2'b01,
DATA_GRAB = 2'b10,
WAIT4GNT = 2'b11;
// NUM_STAGE = 2'd1;
reg [1:0] de_cs, de_ns; // Drawing engine states
reg [6:0] page_count; // Keep track of page counts
reg grab_data;
reg [4:0] de_popen_pipe;
reg fifo_push_d; // delayed fifo_push for short requests
always @ (posedge mclock or negedge reset_n)
if(!reset_n) begin
mcb <= 1'b0;
de_cs <= IDLE;
de_popen_pipe <= 5'b0;
de_push_mff <= 1'b0;
de_push_mff_z <= 1'b0;
de_push_mff_a <= 1'b0;
de_last <= 1'b0;
de_last4 <= 1'b0;
page_count <= 7'b0;
de_arb_address <= 32'b0;
fifo_push_d <= 1'b0;
end else begin
fifo_push_d <= fifo_push;
// assign next state
de_cs <= de_ns;
// Busy back to host
mcb <= |de_cs;
// Initiate first request
if (grab_data) begin
de_arb_address <= de_address;
// We issue a read request here if we are doing a read,
// a read-modify-write, or due to a plane mask, we must do a RMW
casex ({de_read, de_rmw})
2'b01: de_arb_cmd <= 2'd2;
2'b00: de_arb_cmd <= 2'd0;
2'b1x: de_arb_cmd <= 2'd1;
endcase // casex({capt_read[current_output_select],...
end
de_last <= 1'b0;
de_last4 <= 1'b0;
// Pipeline pops for loading the MFF
de_popen_pipe <= (de_popen_pipe << 1) | (~de_read & |page_count);
de_push_mff <= de_popen_pipe[4];
de_push_mff_z <= (de_popen_pipe[4] & de_zen);
de_push_mff_a <= de_popen_pipe[1];
// The counter is loaded with the count.
if (grab_data)
if (line_actv_4)
page_count <= de_page + 5'b1;
else if (BYTES == 16)
page_count <= de_page + 5'b1;
else if (BYTES == 8)
page_count <= {de_page, 1'b1} + 5'b1;
else
page_count <= {de_page, 2'b11} + 5'b1;
// Don't roll the counter over.
else if ((de_push || ~de_read) && |page_count) begin
page_count <= page_count - 7'b1;
de_last <= (page_count == 1);
end
if (BYTES == 4)
de_last4 <= (page_count <= 4);
else if (BYTES == 8)
de_last4 <= (page_count <= 2);
else
de_last4 <= (page_count == 1);
end
assign de_popen = de_popen_pipe[0];
// Drawing engine access state machine.
// The drawing engine path to the Rams is heavily pipelined to allow for
// maximum speed and for Ram latencies. As such we need to generate:
//
// de_popen: The actual pop signal to move data from the drawing engine
// shift_en: The signal to push data through the pipeline
// de_push: The signal to pus hdata into the DE
always @* begin
de_pc_pop = 1'b0;
grab_data = 1'b0;
fifo_push = 1'b0;
de_ns = de_cs; // ?????
case (de_cs)
IDLE: begin
// if (~de_pc_empty && ~de_almost_full && (page_count < 5'd2)) begin
// if (~de_pc_empty && ~de_almost_full && ~|page_count) begin
if (~de_pc_empty && ~de_almost_full && ~|page_count
&& ~fifo_push_d && ~|de_popen_pipe[2:0]) begin
de_pc_pop = 1'b1; // need to register?
de_ns = WAIT_GRAB;
end else
de_ns = IDLE;
end
WAIT_GRAB: de_ns = DATA_GRAB;
DATA_GRAB: begin
grab_data = 1'b1;
de_ns = WAIT4GNT;
end
WAIT4GNT: begin
fifo_push = 1'b1;
de_ns = IDLE;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline bool equal(double _x, double _y) { return _x > _y - 1e-9 && _x < _y + 1e-9; } int l[105], r[105], t[105], c[105], ans, mx, id; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) scanf( %d%d%d%d , &l[i], &r[i], &t[i], &c[i]); for (int j = 1; j <= n; j++) { mx = 1e9; id = -1; for (int i = 0; i < m; i++) { if (l[i] <= j && j <= r[i] && t[i] < mx) { mx = t[i]; id = i; } } if (~id) ans += c[id]; } printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; long long int n, m, a[1000005]; multiset<long long int> st; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (long long int i = 1; i <= n; i++) cin >> a[i]; long long int ans = 0; for (long long int i = 1; i <= n; i++) { st.insert(a[i]); auto it = st.begin(); if (*it < a[i]) { ans += a[i] - *it; st.erase(it); st.insert(a[i]); } } cout << ans; return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cmp_pcxandcpx.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module cmp_pcxandcpx (/*AUTOARG*/
// Inputs
clk, rst_l, spc_pcx_req_pq, spc_pcx_data_pa, cpx_spc_data_cx, cpu
);
input clk;
input rst_l;
//siganls
input [4:0] spc_pcx_req_pq;
input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
input [`CPX_WIDTH-1:0] cpx_spc_data_cx;
input [31:0] cpu;
reg [127:0] pcx;
reg spc_pcx_req_pq_vld;
always @(posedge clk)begin
// victorm 08/11/03
spc_pcx_req_pq_vld <= #1 |spc_pcx_req_pq[4:0];
if(spc_pcx_data_pa[`PCX_VLD] &&
(`PC_CMP.finish_mask != `PC_CMP.good) &&
(`MONITOR.bad == 0)) begin
case(spc_pcx_data_pa[`PCX_RQ_HI:`PCX_RQ_LO])
`LOAD_RQ : pcx = "LOAD_RQ";
`IMISS_RQ : pcx = "IMISS_RQ";
`STORE_RQ : pcx = "STORE_RQ";
`CAS1_RQ : pcx = "CAS1_RQ";
`CAS2_RQ : pcx = "CAS2_RQ";
`SWAP_RQ : pcx = "SWAP_RQ";
`STRLOAD_RQ: pcx = "STRLOAD_RQ";
`STRST_RQ : pcx = "STRST_RQ";
`STQ_RQ : pcx = "STQ_RQ";
`INT_RQ : pcx = "INT_RQ";
`FWD_RQ : pcx = "FWD_RQ";
`FWD_RPY : pcx = "FWD_RPY";
`RSVD_RQ : pcx = "RSVD_RQ";
5'b01010 : pcx = "FPOP1";
5'b01011 : pcx = "FPOP2";
endcase
if(spc_pcx_req_pq_vld)
$display("%0d:Info cpu(%x) pcx %0s packet received -> %b", $time, cpu[2:0], pcx, spc_pcx_data_pa);
end
if(cpx_spc_data_cx[`CPX_VLD] &&
//(`PC_CMP.finish_mask != `PC_CMP.good) &&
(`MONITOR.bad == 0))begin
case(cpx_spc_data_cx[`CPX_RQ_HI:`CPX_RQ_LO])
`LOAD_RET : pcx = "LOAD_RET";
`IFILL_RET: pcx = "IFILL_RET";
`INV_RET : pcx = "INV_RET";
`ST_ACK : pcx = "ST_ACK";
`AT_ACK : pcx = "AT_ACK";
`INT_RET : begin
pcx = "INT_RET";
if(cpx_spc_data_cx[17:16] == 3)begin
if(`PC_CMP.active_thread[cpx_spc_data_cx[12:8]])begin
`PC_CMP.back_thread[cpx_spc_data_cx[12:8]]=1;
end
end
if(cpx_spc_data_cx[17:16] != 1)begin
$display("%0d:Info cpu(%x) thread(%x) received interrupt vector -> %x Also, active_thread->%x", $time,
cpx_spc_data_cx[12:10], cpx_spc_data_cx[9:8], cpx_spc_data_cx[5:0], `PC_CMP.active_thread);
end
else if(cpx_spc_data_cx[17:16] == 1)begin
if(`PC_CMP.active_thread[cpx_spc_data_cx[12:8]])`PC_CMP.back_thread[cpx_spc_data_cx[12:8]]=1;
`PC_CMP.active_thread[cpx_spc_data_cx[12:8]] = 1'b1;
$display("%0d:Info cpu(%x) thread(%x) received interrupt vector -> %x Also, active_thread->%x", $time,
cpx_spc_data_cx[12:10], cpx_spc_data_cx[9:8], cpx_spc_data_cx[5:0], `PC_CMP.active_thread);
end
end
`TEST_RET : pcx = "TEST_RET";
`FP_RET : pcx = "FP_RET";
`EVICT_REQ: pcx = "EVICT_REQ";
`ERR_RET : pcx = "ERR_RET";
`STRLOAD_RET : pcx = "STRLOAD_RET";
`STRST_ACK: pcx = "STRST_ACK";
`FWD_RQ_RET:pcx = "FWD_RQ_RET";
`FWD_RPY_RET:pcx= "FWD_RPY_RET";
`RSVD_RET : pcx = "RSVD_RET";
endcase
$display("%0d:Info cpu(%x) cpx %0s packet received -> %b", $time, cpu[2:0], pcx, cpx_spc_data_cx);
end
end
endmodule
|
/*
* Some more detailed tests of the abs() function.
*
* Copyright (C) 2007-2008 Cary R. ()
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
module main;
reg signed [7:0] a;
wire signed [7:0] vala = abs(a);
reg real b;
wire real valb = abs(b);
initial begin
a = 0;
b = 0;
#1 if (vala !== 0) begin
$display("FAILED -- a=%b, vala=%b", a, vala);
$finish;
end
#1 if (valb != 0) begin
$display("FAILED -- b=%g valb=%g", b, valb);
$finish;
end
a = 1;
b = 1;
#1 if (vala !== 1) begin
$display("FAILED -- a=%b, vala=%b", a, vala);
$finish;
end
#1 if (valb != 1) begin
$display("FAILED -- b=%g valb=%g", b, valb);
$finish;
end
a = -1;
b = -1;
#1 if (vala !== 1) begin
$display("FAILED -- a=%b, vala=%b", a, vala);
$finish;
end
#1 if (valb != 1) begin
$display("FAILED -- b=%g valb=%g", b, valb);
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; void solve(void) { int N; long int s = 0; cin >> N; for (int i = 2; i <= N; i++) s += i - 1; cout << s * 6 * 2 + 1 << endl; } int main(int argc, char const *argv[]) { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int d[400001], num[400001]; int decr[400001], inc[400001]; priority_queue<pair<long long int, int>, vector<pair<long long int, int> >, greater<pair<long long int, int> > > H1; priority_queue<pair<long long int, int> > H2; int main() { int i; int t, m; long long int n, k, p, o; scanf( %d , &t); while (t--) { scanf( %I64d %d %I64d , &n, &m, &k), o = 0; for (i = 0; i < m; i++) scanf( %I64d , &p), d[i] = p - o, o = p; d[m++] = n - o, k += m; long long int l = 1, r = n; while (l < r) { long long int mid = (l + r) / 2; long long int s = 0; for (i = 0; i < m; i++) s += (d[i] + mid - 1) / mid; if (s > k) l = mid + 1; else r = mid; } long long int s = 0; for (i = 0; i < m; i++) num[i] = (d[i] + r - 1) / r, s += num[i]; for (i = 0; i < m; i++) { if ((s < k) && ((d[i] + num[i] - 1) / num[i] == r)) { long long int x = (d[i] - 1) / (r - 1) - num[i] + 1; x = min(x, k - s); num[i] += x, s += x; } l = min(l, d[i] / num[i]); } long long int ans = r - l; for (i = 0; i < m; i++) H1.push(make_pair(d[i] / num[i], i)), H2.push(make_pair(d[i] / (num[i] + 1), i)); fill(decr, decr + m, 0), fill(inc, inc + m, 0); int tt = 10 * m; while (tt--) { while (d[H1.top().second] / num[H1.top().second] != H1.top().first) H1.pop(); while (d[H2.top().second] / (num[H2.top().second] + 1) != H2.top().first) H2.pop(); int u = H1.top().second, v = H2.top().second; H1.pop(), H2.pop(); if (u == v) break; num[u]--, num[v]++; decr[u] = 1, inc[v] = 1; if (decr[u] && inc[u]) break; if (decr[v] && inc[v]) break; if (num[u] == 0) break; r = max(r, (d[u] + num[u] - 1) / num[u]); H1.push(make_pair(d[u] / num[u], u)); if (d[u] / num[u] != d[u] / (num[u] + 1)) H2.push(make_pair(d[u] / (num[u] + 1), u)); if (d[v] / num[v] != d[v] / (num[v] - 1)) H1.push(make_pair(d[v] / num[v], v)); H2.push(make_pair(d[v] / (num[v] + 1), v)); while (d[H1.top().second] / num[H1.top().second] != H1.top().first) H1.pop(); ans = min(ans, r - H1.top().first); } printf( %I64d n , ans); while (!H1.empty()) H1.pop(); while (!H2.empty()) H2.pop(); } return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int go[2], sum; node(int x0, int x1, int _sum) { go[0] = x0, go[1] = x1, sum = _sum; } }; node root(-1, -1, 0); vector<node> t = {root}; int get_sum(int v) { return v == -1 ? 0 : t[v].sum; } int go(int v, int id) { if (t[v].go[id] == -1) { t[v].go[id] = t.size(); t.push_back(node(-1, -1, 0)); } return t[v].go[id]; } void add(int a) { int v = 0; for (int bit = 29; bit >= 0; bit--) { int x = (a >> bit) & 1; v = go(v, x); t[v].sum++; } } int get(int a, int k) { int v = 0, ans = 0, bit = 29; while (bit >= 0) { int x = (a >> bit) & 1, y = (k >> bit) & 1; if (x > y) ans += get_sum(t[v].go[0]); if ((x ^ 1) > y) ans += get_sum(t[v].go[1]); if (t[v].go[x ^ y] == -1) break; v = go(v, x ^ y); bit--; } if (bit == -1) ans += t[v].sum; return ans; } void solve() { int n, k; cin >> n >> k; add(0); long long pref = 0, ans = 0; for (int i = 1; i <= n; i++) { int v; cin >> v; pref = pref ^ v; ans += get(pref, k); add(pref); } cout << ans << n ; } int main() { ios::sync_with_stdio(NULL), cin.tie(0), cout.tie(0); cout.setf(ios::fixed), cout.precision(20); solve(); } |
#include <bits/stdc++.h> class Scanner { private: static const int BUFFER_SIZE = 10000; char buff[BUFFER_SIZE]; int buffPos, buffLim; public: Scanner() { buffLim = fread(buff, 1, BUFFER_SIZE, stdin); buffPos = 0; } private: inline void flushBuff() { buffLim = fread(buff, 1, BUFFER_SIZE, stdin); if (buffLim == 0) { buff[buffLim++] = n ; } buffPos = 0; } inline bool isWS(char t) { return t == || t == n ; } inline bool isDig(char t) { return t >= 0 && t <= 9 ; } void nextPos() { buffPos++; if (buffPos == buffLim) { flushBuff(); } } public: inline char getchar() { char ch = buff[buffPos]; nextPos(); return ch; } inline void next(char* s) { while (isWS(buff[buffPos])) { nextPos(); } while (!isWS(buff[buffPos])) { *s = buff[buffPos]; s++; nextPos(); } *s = 0 ; } inline void nextLine(char* s) { while (buff[buffPos] != n ) { nextPos(); } if (buff[buffPos] == n ) { nextPos(); } while (buff[buffPos] != n ) { *s = buff[buffPos]; s++; buffPos++; } *s = 0 ; } inline int nextInt() { while (!isDig(buff[buffPos]) && buff[buffPos] != - ) { nextPos(); } int sign = (buff[buffPos] == - ) ? nextPos(), -1 : 1; int res = 0; while (isDig(buff[buffPos])) { res = res * 10 + buff[buffPos] - 0 ; nextPos(); } return res * sign; } inline long long nextLong() { while (!isDig(buff[buffPos]) && buff[buffPos] != - ) { nextPos(); } long long sign = (buff[buffPos] == - ) ? nextPos(), -1 : 1; long long res = 0; while (isDig(buff[buffPos])) { res = res * 10 + buff[buffPos] - 0 ; nextPos(); } return res * sign; } inline int n() { while (buff[buffPos] < 0 || buff[buffPos] > 9 ) { buffPos++; if (buffPos == buffLim) { flushBuff(); } } int res = 0; while (buff[buffPos] >= 0 && buff[buffPos] <= 9 ) { res = res * 10 + (buff[buffPos] - 0 ); buffPos++; if (buffPos == buffLim) { flushBuff(); } } return res; } inline long long nl() { while (buff[buffPos] < 0 || buff[buffPos] > 9 ) { buffPos++; if (buffPos == buffLim) { flushBuff(); } } long long res = 0; while (buff[buffPos] >= 0 && buff[buffPos] <= 9 ) { res = res * 10 + (buff[buffPos] - 0 ); buffPos++; if (buffPos == buffLim) { flushBuff(); } } return res; } inline long long nlm(const int MOD) { while (buff[buffPos] < 0 || buff[buffPos] > 9 ) { buffPos++; if (buffPos == buffLim) { flushBuff(); } } long long res = 0; while (buff[buffPos] >= 0 && buff[buffPos] <= 9 ) { res = (res * 10 + (buff[buffPos] - 0 )) % MOD; buffPos++; if (buffPos == buffLim) { flushBuff(); } } return res; } inline double nextDouble() { while (isWS(buff[buffPos])) { nextPos(); } int sign = (buff[buffPos] == - ) ? nextPos(), -1 : 1; double res = 0; while (isDig(buff[buffPos])) { res = res * 10 + buff[buffPos] - 0 ; nextPos(); } if (buff[buffPos] == . ) { nextPos(); double ep = 1; while (isDig(buff[buffPos])) { ep *= 0.1; res += ep * (buff[buffPos] - 0 ); nextPos(); } } return sign * res; } inline char nextChar() { while (isWS(buff[buffPos])) nextPos(); char res = buff[buffPos]; nextPos(); return res; } }; Scanner sc; template <class _Type> void logArray(_Type a[], int n) { for (int i = 0; i < n; ++i) std::cout << a[i] << ; std::cout << std::endl; } template <class T> inline bool checkMin(T& a, T b) { return (a > b ? a = b, 1 : 0); } template <class T> inline bool checkMax(T& a, T b) { return (a < b ? a = b, 1 : 0); } void preInit(); void init(); void solve(); int32_t main() { preInit(); init(); solve(); return 0; } const int N = 300005; std::vector<int> e[N]; int col[N], n; int dp[N], sz[N]; void dfs(int u) { dp[u] = 1; sz[u] = (e[u].size() == 0); for (int v : e[u]) { dfs(v); sz[u] += sz[v]; } if (col[u] == 0) { for (int v : e[u]) dp[u] += dp[v] - 1; } else { for (int v : e[u]) checkMax(dp[u], sz[u] - sz[v] + dp[v]); } } void preInit() {} void init() { n = sc.n(); for (int i = 1; i <= n; i++) col[i] = sc.n(); for (int i = 2; i <= n; i++) { e[sc.n()].push_back(i); } } void solve() { dfs(1); printf( %d n , dp[1]); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1000010; int n, m, cnt, head[maxn], vis[maxn], mark[maxn], ans[maxn], tot; struct edge { int to, next; } e[maxn]; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return x * f; } void add(int from, int to) { e[++cnt] = (edge){to, head[from]}; head[from] = cnt; } void dfs(int now, int father, int edge) { vis[now] = 1; vector<int> bian; for (int i = head[now]; i; i = e[i].next) { int to = e[i].to; if (!vis[to]) dfs(to, now, i); } for (int i = head[now]; i; i = e[i].next) { int to = e[i].to; if (to != father && !mark[i]) { bian.push_back(i); mark[i] = 1; if (i & 1) mark[i + 1] = 1; else mark[i - 1] = 1; } } int size = bian.size(); for (int i = 0; i < size; i++) { if (i & 1) ans[++tot] = now; ans[++tot] = e[bian[i]].to; } if (size & 1) { if (father) ans[++tot] = now, ans[++tot] = father, mark[edge] = 1; else tot--; } } int main() { n = read(), m = read(); for (int i = 1; i <= m; i++) { int u = read(), v = read(); add(u, v), add(v, u); } for (int i = 1; i <= n; i++) if (!vis[i]) dfs(i, 0, 0); printf( %d n , tot / 3); for (int i = 1; i <= tot; i++) { printf( %d , ans[i]); if (i % 3 == 0) puts( ); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> bool chmax(T &x, const T &y) { return (x < y) ? (x = y, true) : false; }; template <typename T> bool chmin(T &x, const T &y) { return (x > y) ? (x = y, true) : false; }; constexpr long long int MOD = 10; constexpr long long int INF = 2e18; int main() { int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<long long int> p(n); for (long long int i = 0; i < (n); i++) cin >> p[i], p[i]--; vector<long long int> cnt(n, 0); for (long long int i = 0; i < (n); i++) { cnt[(p[i] - i + n) % n]++; } vector<long long int> ans; for (long long int i = 0; i < (n); i++) { if (n - cnt[i] <= m) { ans.push_back((-i + n) % n); } else if (n - cnt[i] <= m * 2) { int x = 0; vector<long long int> q(n); for (long long int j = 0; j < (n); j++) q[j] = p[(j - i + n) % n]; vector<long long int> f(n, 0); for (long long int j = 0; j < (n); j++) { if (f[j] == 0) { int now = j; while (f[now] == 0) { f[now] = 1; now = q[now]; x++; } x--; } } if (x <= m) ans.push_back((-i + n) % n); } } sort(ans.begin(), ans.end()); cout << ans.size(); for (auto i : ans) cout << << i; cout << endl; } return 0; } |
// limbus_mm_interconnect_0_avalon_st_adapter_006.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module limbus_mm_interconnect_0_avalon_st_adapter_006 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
limbus_mm_interconnect_0_avalon_st_adapter_006_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program tests that signed registers are compared using signed
* arithmetic.
*/
module main;
reg signed [7:0] vala;
reg signed [7:0] valb;
reg [7:0] valc;
initial begin
vala = -1;
valb = +1;
valc = -1;
if (vala >= valb) begin
$display("FAILED -- vala(%b) is >= valb(%b)", vala, valb);
$finish;
end
if (vala > valb) begin
$display("FAILED -- vala(%b) is > valb(%b)", vala, valb);
$finish;
end
if (valb <= vala) begin
$display("FAILED -- valb(%b) is <= vala(%b)", valb, vala);
$finish;
end
if (valb < vala) begin
$display("FAILED -- valb(%b) is < vala(%b)", valb, vala);
$finish;
end
if (valc <= valb) begin
$display("FAILED -- valc(%b) is not > valb(%b)", valc, valb);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n, x; vector<int> a, b, c; cin >> n; for (int i = 0; i < n; i++) { cin >> x; if (x == 1) a.push_back(i + 1); else if (x == 2) b.push_back(i + 1); else c.push_back(i + 1); } int res = min({a.size(), b.size(), c.size()}); cout << res << endl; for (int i = 0; i < res; i++) { cout << a[i] << << b[i] << << c[i] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 10000001; int a, n, x[maxn]; int main() { scanf( %d%d , &a, &n); for (int i = a; i <= a + n - 1; i++) x[i] = i; for (int i = 2; i * i <= a + n - 1; i++) { int p = i * i; int t = ((a + p - 1) / p) * p; for (int j = t; j <= a + n - 1; j += p) while (x[j] % p == 0) x[j] /= p; } long long ans = 0; for (int i = a; i <= a + n - 1; i++) ans += x[i]; printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int pos[109], npos[109]; int main() { int n, k; cin >> n >> k; for (int i = 1; i <= n; ++i) pos[i] = i; for (int i = 1; i <= k; ++i) { int cnt; cin >> cnt; int el = (1 + cnt) % n; if (el == 0) el = n; cout << pos[el] << ; int nw = 0, st = (el + 1) % n; if (st == 0) st = n; for (int j = 1; j < n; ++j) { npos[++nw] = pos[st]; ++st; st %= n; if (st == 0) st = n; } --n; for (int j = 1; j <= n; ++j) pos[j] = npos[j]; } cout << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DFBBP_BEHAVIORAL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBP_BEHAVIORAL_V |
/*
* This tests the synthesis of a case statement that has an empty case.
*/
module main;
reg clk, bit, foo, clr;
// Synchronous device that toggles whenever enabled by a high bit.
always @(posedge clk or posedge clr)
if (clr) foo = 0;
else case (bit)
1'b0: ;
1'b1: foo <= ~foo;
endcase // case(bit)
(* ivl_synthesis_off *)
always begin
#5 clk = 1;
#5 clk = 0;
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
bit = 0;
clr = 1;
# 6 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 0 || foo !== 0) begin
$display("FAILED");
$finish;
end
clr = 0;
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 0 || foo !== 0) begin
$display("FAILED");
$finish;
end
bit <= 1;
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 1 || foo !== 1) begin
$display("FAILED");
$finish;
end
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 1 || foo !== 0) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_PP_V |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_fdest #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
input [63:0] fml_di,
input flush,
output busy,
input fetch_en,
input pipe_stb_i,
output reg pipe_ack_o,
input [15:0] color,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
output pipe_stb_o,
input pipe_ack_i,
output reg [15:0] color_f,
output [fml_depth-1-1:0] dadr_f, /* in 16-bit words */
output reg [15:0] dcolor
);
/* Hit detection */
reg valid;
reg [fml_depth-1-1-4:0] tag;
reg [fml_depth-1-1:0] dadr_r;
reg hit;
reg tag_we;
always @(posedge sys_clk) begin
if(sys_rst) begin
valid <= 1'b0;
hit <= 1'b0;
dadr_r <= {fml_depth-1{1'b0}};
end else begin
if(tag_we)
valid <= 1'b1;
if(flush)
valid <= 1'b0;
if(pipe_stb_i & pipe_ack_o) begin
hit <= tag == dadr[fml_depth-1-1:4];
dadr_r <= dadr;
end
end
end
always @(posedge sys_clk) begin
if(sys_rst)
tag <= {fml_depth-1-4{1'b0}};
else if(tag_we)
tag <= dadr_r[fml_depth-1-1:4];
end
/* Forward */
always @(posedge sys_clk) begin
if(sys_rst)
color_f <= 16'd0;
else if(pipe_stb_i & pipe_ack_o)
color_f <= color;
end
assign dadr_f = dadr_r;
/* Storage */
reg [63:0] storage[0:3];
// synthesis translate_off
initial begin
storage[0] = 64'd0;
storage[1] = 64'd0;
storage[2] = 64'd0;
storage[3] = 64'd0;
end
// synthesis translate_on
wire [63:0] storage_do = storage[dadr_r[3:2]];
always @(*) begin
case(dadr_r[1:0])
2'd0: dcolor = storage_do[63:48];
2'd1: dcolor = storage_do[47:32];
2'd2: dcolor = storage_do[31:16];
2'd3: dcolor = storage_do[15:0];
endcase
end
reg [1:0] storage_wa;
reg storage_we;
always @(posedge sys_clk) begin
if(storage_we)
storage[storage_wa] = fml_di;
end
/* Control & bus master */
assign fml_adr = {dadr_r[fml_depth-1-1:4], 5'd0};
reg wanted;
always @(posedge sys_clk) begin
if(sys_rst)
wanted <= 1'b0;
else if(pipe_ack_o)
wanted <= pipe_stb_i;
end
reg stb_after_fetch;
reg [2:0] state;
reg [2:0] next_state;
parameter IDLE = 3'd0;
parameter FETCH1 = 3'd1;
parameter FETCH2 = 3'd2;
parameter FETCH3 = 3'd3;
parameter FETCH4 = 3'd4;
parameter OUT = 3'd5;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
next_state = state;
tag_we = 1'b0;
storage_we = 1'b0;
storage_wa = 2'bx;
fml_stb = 1'b0;
pipe_ack_o = 1'b0;
stb_after_fetch = 1'b0;
case(state)
IDLE: begin
pipe_ack_o = pipe_ack_i | ~wanted;
if(wanted & ~hit & fetch_en) begin
pipe_ack_o = 1'b0;
next_state = FETCH1;
end
end
FETCH1: begin
fml_stb = 1'b1;
storage_we = 1'b1;
storage_wa = 2'd0;
if(fml_ack)
next_state = FETCH2;
end
FETCH2: begin
storage_we = 1'b1;
storage_wa = 2'd1;
next_state = FETCH3;
end
FETCH3: begin
storage_we = 1'b1;
storage_wa = 2'd2;
next_state = FETCH4;
end
FETCH4: begin
storage_we = 1'b1;
storage_wa = 2'd3;
tag_we = 1'b1;
next_state = OUT;
end
OUT: begin
stb_after_fetch = 1'b1;
pipe_ack_o = pipe_ack_i;
if(pipe_ack_i)
next_state = IDLE;
end
endcase
end
assign pipe_stb_o = stb_after_fetch | (wanted & (hit | ~fetch_en));
assign busy = wanted;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 3; const int mod = 998244353; int n; map<int, int> a; char s[N]; long long ans = 0; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s , s + 1); int x = 0, l = strlen(s + 1); for (int j = 1; j <= l; j++) x = x ^ (1 << (s[j] - a )); for (int j = 0; j < 26; j++) ans += a[x ^ (1 << j)]; ans += a[x]; a[x]++; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int max(int a, int b) { if (a > b) return a; else return b; } long long min(long long a, long long b) { if (a < b) return a; else return b; } int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } int lcm(int a, int b) { return a * (b / gcd(a, b)); } vector<bool> isPrime(1000005 + 1, true); string tos(int n) { stringstream ss; ss << n; return ss.str(); } void seive() { isPrime[0] = 0, isPrime[1] = 0; for (long long i = 2; i * i <= 1000005; i++) if (isPrime[i]) for (long long j = i * i; j <= 1000005; j += i) isPrime[j] = 0; } int dx[] = {1, -1, 0, 0}; int dy[] = {0, 0, 1, -1}; const int val = 1 << 20; long long n, m, st, e, ans = 1, a[1111111], b[1111111]; int main() { string s1, s2; cin >> s1 >> s2; long long i = 0, j = 0, beg = -1; while (j < s2.size()) { if (s1[i] == s2[j]) { if (beg == -1) { beg = j; a[0] = j; } i++; } if (i == s1.size()) { b[0] = j; break; } j++; } i = s1.size(); j = s2.size(); beg = -1; while (j >= 0) { if (s1[i] == s2[j]) { if (beg == -1) { beg = j; b[1] = j; } i--; } if (i < 0) { a[1] = j; break; } j--; } ans = max(0, a[1] - b[0]); cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; struct bigint { int len, num[70]; bigint(int m = 0) { memset(num, 0, sizeof num); len = 1; num[1] = m; } bigint operator+(const bigint &b) { bigint c; c.len = max(len, b.len); int x = 0, y = 0; for (int i = 1; i <= c.len; i++) { y = x; if (i <= len) y += num[i]; if (i <= b.len) y += b.num[i]; c.num[i] = y % 1000000000; x = y / 1000000000; } if (x) c.len++, c.num[c.len] = x; return c; } void operator=(const bigint &b) { len = b.len; for (int i = 1; i <= len; i++) num[i] = b.num[i]; } bool operator<(const bigint &b) { if (len != b.len) return len < b.len; for (int i = len; i >= 1; i--) { if (num[i] != b.num[i]) return num[i] < b.num[i]; } return 0; } void print() { printf( %d , num[len]); for (int i = len - 1; i; i--) printf( %09d , num[i]); puts( ); } } f[5050], ex[2020]; inline bigint max(bigint a, bigint b) { return a < b ? b : a; } int n, x, last[2020]; char s[11]; int main() { ex[0] = bigint(1); for (int i = 1; i <= 2000; i++) ex[i] = ex[i - 1] + ex[i - 1]; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s %d , s, &x); f[i] = f[i - 1]; if (s[0] == w ) last[x] = i; else if (last[x]) { f[i] = max(f[i], f[last[x] - 1] + ex[x]); } } f[n].print(); return 0; } |
#include <bits/stdc++.h> using namespace std; string s; int n, i, k = 0; int main() { cin >> s; for (i = 0; i < s.size(); i++) { while (s[i] == s[i + 1] && s.size()) { s.erase(i, 2); i--; k++; } } if (k % 2 != 0) cout << YES << endl; else if (k % 2 == 0) cout << No << endl; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [7:0] crc;
wire [61:59] ah = crc[5:3];
wire [61:59] bh = ~crc[4:2];
wire [41:2] al = {crc,crc,crc,crc,crc};
wire [41:2] bl = ~{crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:2]};
reg sel;
wire [61:28] q = ( sel
? func(ah, al)
: func(bh, bl));
function [61:28] func;
input [61:59] inh;
input [41:2] inl;
reg [42:28] func_mid;
reg carry;
begin
carry = &inl[27:2];
func_mid = {1'b0,inl[41:28]} + {14'b0, carry};
func[61:59] = inh + {2'b0, func_mid[42]};
func[58:42] = {17{func_mid[41]}};
func[41:28] = func_mid[41:28];
end
endfunction
integer cyc; initial cyc=1;
always @ (posedge clk) begin
//$write("%d %x\n", cyc, q);
if (cyc!=0) begin
cyc <= cyc + 1;
sel <= ~sel;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==1) begin
sel <= 1'b1;
crc <= 8'h12;
end
if (cyc==2) if (q!=34'h100000484) $stop;
if (cyc==3) if (q!=34'h37fffeddb) $stop;
if (cyc==4) if (q!=34'h080001212) $stop;
if (cyc==5) if (q!=34'h1fffff7ef) $stop;
if (cyc==6) if (q!=34'h200000848) $stop;
if (cyc==7) if (q!=34'h380001ebd) $stop;
if (cyc==8) if (q!=34'h07fffe161) $stop;
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_BEHAVIORAL_V
`define SKY130_FD_SC_LP__OR4_BEHAVIORAL_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, c = 0; string s; cin >> n >> s; for (int i = 0; i < s.length(); i++) { if (s[i] == 1 ) c++; else { c++; break; } } cout << c; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { int sum = 0, ff = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) ff = -1; ch = getchar(); } while (isdigit(ch)) sum = sum * 10 + (ch ^ 48), ch = getchar(); return sum * ff; } int Q, n, a[10005], cnt; int main() { Q = read(); for (; Q--;) { n = read(); cnt = 0; if (n == 4) { puts( 3 1 4 2 ); continue; } if (n <= 3) printf( -1 ); else { if (n & 1) { for (int j = n; j >= 1; j--) if (j & 1) a[++cnt] = j; a[++cnt] = 4, a[++cnt] = 2; if (n >= 6) for (int j = 6; j <= n; j++) if (j % 2 == 0) a[++cnt] = j; } else { for (int j = n; j >= 1; j--) if (j % 2 == 0) a[++cnt] = j; a[++cnt] = 5, a[++cnt] = 1, a[++cnt] = 3; if (n >= 7) for (int j = 7; j <= n; j++) if (j & 1) a[++cnt] = j; } for (int i = 1; i <= cnt; i++) printf( %d , a[i]); } puts( ); } } |
#include <bits/stdc++.h> using namespace std; bool bi[12][12]; int main() { int a, b, c, d, e, x, y, z, n, k, N, M; scanf( %d %d , &N, &M); scanf( %d %d , &z, &k); for (a = 0; a < z; a++) { scanf( %d %d , &x, &y); bi[x][y] = true; } z = 0; for (a = 1; a <= N; a++) { for (b = 1; b <= M; b++) { for (c = a; c <= N; c++) { for (d = b; d <= M; d++) { e = 0; for (x = a; x <= c; x++) { for (y = b; y <= d; y++) if (bi[x][y]) e++; } if (e >= k) z++; } } } } cout << z << endl; return 0; } |
`timescale 1ns / 1ps
/*
* File : RegisterFile.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers ()
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 7-Jun-2011 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* A Register File for a MIPS processor. Contains 32 general-purpose
* 32-bit wide registers and two read ports. Register 0 always reads
* as zero.
*/
module RegisterFile(
input clock,
input reset,
input [4:0] ReadReg1, ReadReg2, WriteReg,
input [31:0] WriteData,
input RegWrite,
output [31:0] ReadData1, ReadData2,
// Voter Signals for Registers
input [991:0] registers_in,
output [991:0] registers_out
);
// Register file of 32 32-bit registers. Register 0 is hardwired to 0s
wire [31:0] registers [1:31];
reg [31:0] vote_registers [1:31];
// Sequential (clocked) write.
// 'WriteReg' is the register index to write. 'RegWrite' is the command.
integer i;
always @(posedge clock) begin
for (i=1; i<32; i=i+1) begin
vote_registers[i] <= (reset) ? 0 : (RegWrite && (WriteReg==i)) ? WriteData : registers[i];
end
end
genvar j;
generate
for (j=1; j<32; j=j+1) begin : Voter_Signals
assign registers[j] = registers_in[((32*j)-1):(32*(j-1))];
assign registers_out[((32*j)-1):(32*(j-1))] = vote_registers[j];
end
endgenerate
// Combinatorial Read. Register 0 is all 0s.
assign ReadData1 = (ReadReg1 == 0) ? 32'h00000000 : registers[ReadReg1];
assign ReadData2 = (ReadReg2 == 0) ? 32'h00000000 : registers[ReadReg2];
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> q[100002]; int ans[100002]; int flag, v[100002]; int k; void dfs(int len, int x, int f) { int i; v[x] = len; ans[len] = x; for (i = 0; i < q[x].size(); i++) { int j = q[x][i]; if (j == f) continue; if (v[j] != -1) { if (flag) break; if (len + 1 - v[j] >= k + 1) { printf( %d n , len + 1 - v[j]); for (i = v[j]; i <= len; i++) { if (i != v[j]) printf( ); printf( %d , ans[i]); } printf( n ); flag = 1; return; } continue; } dfs(len + 1, j, x); } } int main() { int n, m; while (scanf( %d%d%d , &n, &m, &k) != EOF) { while (m--) { int a, b; scanf( %d%d , &a, &b); q[a].push_back(b); q[b].push_back(a); } memset(v, -1, sizeof(v)); dfs(0, 1, -1); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2OI_TB_V
`define SKY130_FD_SC_HS__A2BB2OI_TB_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2bb2oi.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A1_N = 1'b1;
#160 A2_N = 1'b1;
#180 B1 = 1'b1;
#200 B2 = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A1_N = 1'b0;
#280 A2_N = 1'b0;
#300 B1 = 1'b0;
#320 B2 = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 B2 = 1'b1;
#440 B1 = 1'b1;
#460 A2_N = 1'b1;
#480 A1_N = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 B2 = 1'bx;
#560 B1 = 1'bx;
#580 A2_N = 1'bx;
#600 A1_N = 1'bx;
end
sky130_fd_sc_hs__a2bb2oi dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2OI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32AI_4_V
`define SKY130_FD_SC_MS__O32AI_4_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o32ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o32ai_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32AI_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:04:28 04/05/2016
// Design Name:
// Module Name: ALU_1bit_overflow
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALU_1bit_overflow
(
// Input
input a_in,
input b_in,
input carry_in,
input b_invert,
input less,
input [1:0] op,
// Output
output wire result,
output wire carry_out,
output wire set,
output wire overflow
);
// Internal Variables
reg b_invert_out;
reg mux_out;
reg check;
wire fa_01_out;
wire and_out;
wire or_out;
//assign
assign set = fa_01_out;
assign overflow = check;
assign result = mux_out;
//submodule
full_adder fa_01 (
.x_in ( a_in ),
.y_in ( b_invert_out ),
.c_in ( carry_in ),
.s_out ( fa_01_out ),
.c_out ( carry_out )
); // Full_Adder
// b_Inverter
always @ ( b_invert or b_in )
begin : Binvert
if ( !b_invert )
b_invert_out = b_in; // b
else
b_invert_out = ~ b_in; // b'
end
// Logical_operation
assign and_out = a_in & b_invert_out;
assign or_out = a_in | b_invert_out;
// op_Selection
always @ ( op or and_out or or_out or less or fa_01_out )
begin : Operation
if ( op == 0 )
mux_out = and_out;
else if ( op == 1)
mux_out = or_out;
else if ( op == 2)
mux_out = fa_01_out;
else
mux_out = less;
end
//Overflow_detection
always @ ( op or a_in or b_invert_out or fa_01_out)
begin : Checker
if ( op == 0 || op == 1 )
check = 1'b0;
else if ( !( a_in ) && !(b_invert_out) && fa_01_out )
check = 1'b1;
else if ( a_in && b_invert_out && !( fa_01_out ) )
check = 1'b1;
else
check = 1'b0;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/18/2016 01:33:37 PM
// Design Name:
// Module Name: scaler
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module axis_bayer_extractor #
(
parameter integer C_PIXEL_WIDTH = 8,
parameter integer C_BYPASS = 0,
parameter integer C_COL_ODD = 0,
parameter integer C_ROW_ODD = 0
) (
input wire clk,
input wire resetn,
input wire s_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tuser,
input wire s_axis_tlast,
output wire s_axis_tready,
output wire m_axis_tvalid,
output wire [C_PIXEL_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tuser,
output wire m_axis_tlast,
input wire m_axis_tready
);
generate
if (C_BYPASS == 1) begin: direct_connect
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tdata[C_PIXEL_WIDTH-1:0] = s_axis_tdata[C_PIXEL_WIDTH-1:0];
assign m_axis_tuser = s_axis_tuser;
assign m_axis_tlast = s_axis_tlast;
assign s_axis_tready = m_axis_tready;
end
else begin: extract_quater
reg r_m_axis_tvalid;
assign m_axis_tvalid = r_m_axis_tvalid;
reg [C_PIXEL_WIDTH-1:0] r_m_axis_tdata;
assign m_axis_tdata[C_PIXEL_WIDTH-1:0] = r_m_axis_tdata;
reg r_m_axis_tuser;
assign m_axis_tuser = r_m_axis_tuser;
reg r_m_axis_tlast;
assign m_axis_tlast = r_m_axis_tlast;
wire snext;
assign snext = s_axis_tvalid && s_axis_tready;
wire mnext;
assign mnext = m_axis_tvalid && m_axis_tready;
reg sline_lsb;
reg spixel_lsb;
always @ (posedge clk) begin
if (resetn == 1'b0)
sline_lsb <= 0;
else if (snext && s_axis_tlast)
sline_lsb <= ~sline_lsb;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
spixel_lsb <= 0;
else if (snext)
spixel_lsb <= ~spixel_lsb;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
r_m_axis_tdata <= 0;
else if (snext
&& (spixel_lsb == C_COL_ODD)
&& (sline_lsb == C_ROW_ODD))
r_m_axis_tdata <= s_axis_tdata;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
r_m_axis_tvalid <= 0;
else if (snext
&& (spixel_lsb == 1)
&& (sline_lsb == C_ROW_ODD))
r_m_axis_tvalid <= 1;
else if (m_axis_tready)
r_m_axis_tvalid <= 0;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
r_m_axis_tlast <= 0;
else if (snext
&& (spixel_lsb == 1)
&& (sline_lsb == C_ROW_ODD))
r_m_axis_tlast <= s_axis_tlast;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
r_m_axis_tuser <= 0;
else if (snext
&& s_axis_tuser)
r_m_axis_tuser <= 1;
else if (mnext)
r_m_axis_tuser <= 0;
end
assign s_axis_tready = (~m_axis_tvalid || m_axis_tready);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 7; const long long llinf = 1ll * inf * inf; const double eps = 1e-12; const int N = 1e5 + 10; int f[N], h[N], g[N]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= int(n); ++i) scanf( %d , &f[i]); map<int, vector<int> > uf; for (int i = 1; i <= int(n); ++i) uf[f[i]].push_back(i); int m = uf.size(); auto itr = uf.begin(); for (int x = 1; x <= m; ++x) { h[x] = itr->first; vector<int> nv = itr->second; itr++; for (int y : nv) g[y] = x; } int bad = 0; for (int x = 1; x <= m; ++x) if (g[h[x]] != x) bad = 1; for (int x = 1; x <= n; ++x) if (h[g[x]] != f[x]) bad = 1; if (bad) puts( -1 ); else { printf( %d n , m); for (int x = 1; x <= int(n); ++x) printf( %d%c , g[x], x == n ? n : ); for (int x = 1; x <= int(m); ++x) printf( %d%c , h[x], x == m ? n : ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O221AI_BEHAVIORAL_PP_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221AI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long a[300005]; string s, p; vector<long long> v; int main() { ios_base::sync_with_stdio(false); long long i, j, k, l, m, x, y, r, n, t; cin >> n >> m; for (i = 1; i <= n; i++) { cin >> x; if (x < 300005) a[x] = 1; } long long msd = 0; long long cnt = 0; for (i = 1; i <= 300000; i++) { if (msd >= m) { break; } if (a[i] == 0) { if ((msd + i) <= m) { cnt++; v.push_back(i); msd += i; } } } cout << cnt << endl; for (i = 0; i < v.size(); i++) { cout << v[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; string s1, s2; int len1, len2; int dp[5002][5002]; int func(int p1, int p2) { if ((p1 == len1) || (p2 == len2)) { return 0; } if (dp[p1][p2] != -1) { return dp[p1][p2]; } int ans = 0; if (s1[p1] == s2[p2]) { ans = (1 + ans + func(p1 + 1, p2 + 1)) % 1000000007; } ans = (ans + func(p1, p2 + 1)) % 1000000007; return dp[p1][p2] = ans; } int main() { std::ios_base::sync_with_stdio(false); ; cin >> s1 >> s2; len1 = s1.size(); len2 = s2.size(); memset((dp), -1, sizeof(dp)); int ans = 0; for (int i = 0; i <= len1 - 1; i++) { ans = (ans + func(i, 0)) % 1000000007; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline string itos(T n) { return (n) < 0 ? - + itos(-(n)) : (n) < 10 ? (string)( ) + (char)( 0 + (n)) : itos((n) / 10) + itos((n) % 10); } string name[60]; map<string, int> mp; int point[60], _plus[60], _minus[60]; vector<pair<pair<int, pair<int, int> >, string> > v; int main(void) { int N, i, j; string s; cin >> N; for ((i) = 0; (i) < (int)(N); (i)++) { cin >> name[i]; mp[name[i]] = i; } for ((i) = 0; (i) < (int)(N * (N - 1) / 2); (i)++) { cin >> s; for (j = 0;; j++) { if (s[j] == - ) break; } int a = mp[s.substr(0, j)]; int b = mp[s.substr(j + 1)]; int x, y; cin >> s; for ((j) = 0; (j) < (int)(s.length()); (j)++) { if (s[j] == : ) { s[j] = ; } } istringstream ss(s); ss >> x >> y; if (x > y) point[a] += 3; else if (x < y) point[b] += 3; else { point[a]++; point[b]++; } _plus[a] += x; _plus[b] += y; _minus[a] += y; _minus[b] += x; } for ((i) = 0; (i) < (int)(N); (i)++) { v.push_back(make_pair( make_pair(-point[i], make_pair(_minus[i] - _plus[i], -_plus[i])), name[i])); } sort(v.begin(), v.end()); vector<string> ans; for ((i) = 0; (i) < (int)(N / 2); (i)++) { ans.push_back(v[i].second); } sort(ans.begin(), ans.end()); for ((i) = 0; (i) < (int)(N / 2); (i)++) { cout << ans[i] << endl; } return 0; } |
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