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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/25 22:53:19
// Design Name:
// Module Name: decoder_74138_dataflow
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decoder_74138_dataflow(
input [2:0] x,
input g1,g2a_n,g2b_n,
output [7:0] y
);
assign y[0] = g2a_n|g2b_n|(~g1)|x[0]|x[1]|x[2];
assign y[1] = g2a_n|g2b_n|(~g1)|x[0]|x[1]|(~x[2]);
assign y[2] = g2a_n|g2b_n|(~g1)|x[0]|(~x[1])|x[2];
assign y[3] = g2a_n|g2b_n|(~g1)|x[0]|(~x[1])|(~x[2]);
assign y[4] = g2a_n|g2b_n|(~g1)|(~x[0])|x[1]|x[2];
assign y[5] = g2a_n|g2b_n|(~g1)|(~x[0])|x[1]|(~x[2]);
assign y[6] = g2a_n|g2b_n|(~g1)|(~x[0])|(~x[1])|x[2];
assign y[7] = g2a_n|g2b_n|(~g1)|(~x[0])|(~x[1])|(~x[2]);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, i, j, k, r; cin >> n >> k >> r; long long ar[n], arr[k]; for (i = 0; i < n; i++) { cin >> ar[i]; } for (i = 0; i < k; i++) { cin >> arr[i]; } sort(ar, ar + n); sort(arr, arr + k); long long a = ar[0], d, p; long long b = arr[k - 1]; d = r / a; p = r % a; long long sum = b * d + p; cout << max(sum, r) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; string t = abacaba ; int get(string a) { int cnt = 0; for (int i = 0; i < a.size(); i++) { if (a.substr(i, t.size()) == t) cnt++; } return cnt; } int main() { int T; scanf( %d , &T); while (T--) { int n; string a; cin >> n >> a; int cnt = 0; for (int i = 0; i < a.size(); i++) { if (a.substr(i, t.size()) == t) cnt++; } if (cnt > 1) puts( No ); else if (cnt == 1) { puts( Yes ); for (int i = 0; i < a.size(); i++) { if (a[i] != ? ) printf( %c , a[i]); else putchar( z ); } puts( ); } else { bool f = false; for (int i = 0; i < n; i++) { int cnt = 0; for (int k = i, j = 0; j < t.size() && k < a.size(); k++, j++) { if (a[k] == t[j] || a[k] == ? ) cnt++; else break; } if (cnt == t.size()) { string ts = a; for (int k = i, j = 0; j < t.size(); k++, j++) ts[k] = t[j]; if (get(ts) > 1) continue; else { f = true; puts( Yes ); for (int i = 0; i < ts.size(); i++) if (ts[i] == ? ) ts[i] = z ; cout << ts << endl; } break; } } if (!f) puts( No ); } } }
|
#include <bits/stdc++.h> using namespace std; signed main() { long long int t; cin >> t; while (t--) { long long int n; cin >> n; long long int a[n]; for (long long int i = 0; i < n; i++) { cin >> a[i]; a[i]--; } vector<long long int> pos(n); for (long long int i = 0; i < n; i++) { pos[a[i]] = i; } long long int mnpos = pos[0]; long long int mx = pos[0]; vector<long long int> ans(n); for (long long int i = 0; i < n; i++) { mnpos = min(mnpos, pos[i]); mx = max(mx, pos[i]); if (mx - mnpos == i) { ans[i] = 1; } else { ans[i] = 0; } } for (long long int x : ans) cout << x; cout << n ; } return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eb_e
//
// Generated
// by: wig
// on: Wed Jun 7 16:54:20 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eb_e.v,v 1.4 2006/06/22 07:19:59 wig Exp $
// $Date: 2006/06/22 07:19:59 $
// $Log: inst_eb_e.v,v $
// Revision 1.4 2006/06/22 07:19:59 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
//
// Generator: mix_0.pl Revision: 1.45 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_eb_e
//
// No user `defines in this module
module inst_eb_e
//
// Generated Module inst_eb
//
(
p_mix_c_addr_12_0_gi,
p_mix_c_bus_in_31_0_gi,
p_mix_tmi_sbist_fail_12_10_go
);
// Generated Module Inputs:
input [12:0] p_mix_c_addr_12_0_gi;
input [31:0] p_mix_c_bus_in_31_0_gi;
// Generated Module Outputs:
output [2:0] p_mix_tmi_sbist_fail_12_10_go;
// Generated Wires:
wire [12:0] p_mix_c_addr_12_0_gi;
wire [31:0] p_mix_c_bus_in_31_0_gi;
wire [2:0] p_mix_tmi_sbist_fail_12_10_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [12:0] c_addr; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] c_bus_in; // __W_PORT_SIGNAL_MAP_REQ
wire [12:0] tmi_sbist_fail; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign c_addr = p_mix_c_addr_12_0_gi; // __I_I_BUS_PORT
assign c_bus_in = p_mix_c_bus_in_31_0_gi; // __I_I_BUS_PORT
assign p_mix_tmi_sbist_fail_12_10_go[2:0] = tmi_sbist_fail[12:10]; // __I_O_SLICE_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_eba
inst_eba_e inst_eba (
.c_addr_i(c_addr),
.c_bus_i(c_bus_in), // CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
.mbist_aci_fail_o(tmi_sbist_fail[10]),
.mbist_vcd_fail_o(tmi_sbist_fail[11])
);
// End of Generated Instance Port Map for inst_eba
// Generated Instance Port Map for inst_ebb
inst_ebb_e inst_ebb (
.c_addr_i(c_addr),
.c_bus_i(c_bus_in), // CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
.mbist_sum_fail_o(tmi_sbist_fail[12])
);
// End of Generated Instance Port Map for inst_ebb
// Generated Instance Port Map for inst_ebc
inst_ebc_e inst_ebc (
.c_addr(c_addr),
.c_bus_in(c_bus_in) // CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
// End of Generated Instance Port Map for inst_ebc
endmodule
//
// End of Generated Module rtl of inst_eb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; long long n, m, a, b, x, y, z, ans, g[3010 * 3010], h[3010][3010], f[3010][3010]; deque<long long> q, zr; int main() { scanf( %lld%lld%lld%lld%lld%lld%lld%lld , &n, &m, &a, &b, g, &x, &y, &z); for (int i = 1; i <= n * m; i++) g[i] = (g[i - 1] * x + y) % z; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) h[i][j] = g[(i - 1) * m + j - 1]; for (int i = 1; i <= n; i++) { q = zr; for (int j = 1; j <= m; j++) { while (!q.empty() && h[i][q.back()] >= h[i][j]) q.pop_back(); while (!q.empty() && q.front() + b - 1 < j) q.pop_front(); q.push_back(j), f[i][j] = h[i][q.front()]; } } for (long long j = 1; j <= m; j++) { while (!q.empty()) q.pop_front(); for (long long i = 1; i <= n; i++) { while (!q.empty() && f[q.back()][j] >= f[i][j]) q.pop_back(); if (!q.empty() && q.front() + a - 1 < i) q.pop_front(); q.push_back(i); if (i >= a && j >= b) ans += f[q.front()][j]; } } cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_V
`define SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_pr/sky130_fd_sc_hd__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_V
|
`timescale 1ns / 1ps
/************************
* Willard Wider
* 6-6-17
* ELEC3725
* alupipe.v
* building a 32 bit ALU
************************/
//the top module, the ALU with piped input and output
module alupipe(S, abus, bbus, clk, Cin, dbus);
input [31:0] abus;
input [31:0] bbus;
input clk;
input [2:0] S;
input Cin;
output [31:0] dbus;
wire [31:0] aInput;//connects register A output to ALU A input
wire [31:0] bInput;//connects register B output to ALU B input
wire [31:0] dInput;//connects register D input to ALU D output
alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));
DflipFlop AFF(.dataIn(abus), .dataOut(aInput), .clk(clk));
DflipFlop BFF(.dataIn(bbus), .dataOut(bInput), .clk(clk));
DflipFlop DFF(.dataIn(dInput), .dataOut(dbus), .clk(clk));
endmodule
//flip flop module. requires a clock cycle to update value
module DflipFlop(dataIn, clk, dataOut);
input [31:0] dataIn;
input clk;
output [31:0] dataOut;
reg [31:0] dataOut;
always @(posedge clk) begin
dataOut = dataIn;
end
endmodule
//Below this point is code from assignment 1//
//The declaration of the entire ALU itself.
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over to the next circuit/ V is the overflow bit.
input [31:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a previous circuit
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [31:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 1. Caontains LACs for the root and level 4. Used in the core alu32 module
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03:04:50 02/19/2009
// Design Name:
// Module Name: RCB_FRL_LED_Clock
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_LED_Clock(Test_Clock_in, LED_Clock_out, RST);
input Test_Clock_in;
output LED_Clock_out;
input RST;
reg[9:0] count1;
reg[9:0] count2;
reg[9:0] count3;
reg LED_Clock_out_reg;
assign LED_Clock_out = LED_Clock_out_reg;
always @(posedge Test_Clock_in or posedge RST) begin
if (RST) begin
count1 <= 1'b0;
count2 <= 1'b0;
count3 <= 1'b0;
LED_Clock_out_reg <= 1'b0;
end
else begin
if (count3 < 448) begin
if (count2 < 1000) begin
if (count1 < 1000)
count1 <= count1 + 1'b1;
else
begin
count1 <= 1'b0;
count2 <= count2 + 1'b1;
end
end
else
begin
count2 <= 1'b0;
count3 <= count3 + 1'b1;
end
end
else
begin
count3 <= 1'b0;
LED_Clock_out_reg <= ~LED_Clock_out_reg;
end
end
end
endmodule
module RCB_FRL_LED_Clock_DIV(Test_Clock_in, LED_Clock_out, RST);
input Test_Clock_in;
output LED_Clock_out;
input RST;
reg[9:0] count1;
reg[9:0] count2;
reg[9:0] count3;
reg LED_Clock_out_reg;
assign LED_Clock_out = LED_Clock_out_reg;
always @(posedge Test_Clock_in or posedge RST) begin
if (RST) begin
count1 <= 1'b0;
count2 <= 1'b0;
count3 <= 1'b0;
LED_Clock_out_reg <= 1'b0;
end
else begin
if (count3 < 56) begin
if (count2 < 1000) begin
if (count1 < 1000)
count1 <= count1 + 1'b1;
else
begin
count1 <= 1'b0;
count2 <= count2 + 1'b1;
end
end
else
begin
count2 <= 1'b0;
count3 <= count3 + 1'b1;
end
end
else
begin
count3 <= 1'b0;
LED_Clock_out_reg <= ~LED_Clock_out_reg;
end
end
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Following defines conditionally include RX path circuitry
`include "config.vh" // resolved relative to project root
module rx_chain
(input clock,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
output wire hb_strobe,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debugdata,output wire [15:0] debugctrl
);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
wire [31:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] hb_in_i, hb_in_q;
assign debugdata = hb_in_i;
`ifdef RX_NCO_ON
phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
(.clk(clock),.reset(reset),.enable(enable),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.strobe(sample_strobe),.phase(phase) );
cordic rx_cordic
( .clock(clock),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase[31:16]),
.xo(bb_i),.yo(bb_q),.zo() );
`else
assign bb_i = i_in;
assign bb_q = q_in;
assign sample_strobe = 1;
`endif // !`ifdef RX_NCO_ON
`ifdef RX_CIC_ON
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i),.signal_out(hb_in_i) );
`else
assign hb_in_i = bb_i;
assign decimator_strobe = sample_strobe;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_i_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(hb_strobe),
.data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
`else
assign i_out = hb_in_i;
assign hb_strobe = decimator_strobe;
`endif
`ifdef RX_CIC_ON
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q),.signal_out(hb_in_q) );
`else
assign hb_in_q = bb_q;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_q_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(),
.data_in(hb_in_q),.data_out(q_out) );
`else
assign q_out = hb_in_q;
`endif
endmodule // rx_chain
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<bool> primes(n + 1, 1); primes[0] = primes[1] = 0; for (int i = 2; i <= n; ++i) { if (!primes[i]) continue; for (int j = i * i; j <= n; j += i) primes[j] = 0; } vector<int> quest; for (int i = 2; i <= n; ++i) { if (!primes[i]) continue; int k = i; do { quest.push_back(k); k *= i; } while (k <= n); } cout << quest.size() << n ; for (int i = 0; i < quest.size(); ++i) cout << quest[i] << ; return 0; }
|
Require Import
Unicode.Utf8 Setoid List Permutation Setoid Morphisms.
(** The standard Permutation property is not setoid-aware, so we
introduce a variant that is. *)
Section def.
Context {A: Type} (e: relation A) `{!Equivalence e}.
Inductive SetoidPermutation: list A → list A → Prop :=
| s_perm_nil : SetoidPermutation nil nil
| s_perm_skip x y: e x y -> ∀ l l', SetoidPermutation l l' → SetoidPermutation (x :: l) (y :: l')
| s_perm_swap x y l: SetoidPermutation (y :: x :: l) (x :: y :: l)
| s_perm_trans l l' l'': SetoidPermutation l l' → SetoidPermutation l' l'' → SetoidPermutation l l''.
Hint Constructors SetoidPermutation.
Global Instance: Equivalence SetoidPermutation.
Proof with eauto; intuition.
constructor...
intro l.
induction l...
intros x y H.
induction H...
Qed.
Global Instance: Proper (list_eq e ==> list_eq e ==> iff) SetoidPermutation.
Proof with eauto.
assert (forall a b, list_eq e a b → SetoidPermutation a b).
intros ?? E. apply (@list_eq_rect _ e SetoidPermutation); auto.
intros ?? E ?? F.
split; intro.
symmetry in E...
symmetry in F...
Qed.
End def.
Hint Constructors SetoidPermutation Permutation.
Lemma SetoidPermutation_stronger {A} (R U: relation A):
(forall x y: A, R x y → U x y) →
forall a b, SetoidPermutation R a b → SetoidPermutation U a b.
Proof. intros ??? P. induction P; eauto. Qed.
(** With eq for the element relation, SetoidPermutation is directly equivalent to Permutation: *)
Lemma SetoidPermutation_eq {A} (a b: list A): SetoidPermutation eq a b ↔ Permutation a b.
Proof. split; intro; induction H; eauto. subst; eauto. Qed.
(** And since eq is stronger than any other equivalence, SetoidPermutation always follows from Permutation: *)
Lemma SetoidPermutation_from_Permutation {A} (e: relation A) `{!Reflexive e} (a b: list A):
Permutation a b → SetoidPermutation e a b.
Proof.
intro.
apply SetoidPermutation_stronger with eq.
intros. subst. reflexivity.
apply SetoidPermutation_eq.
assumption.
Qed.
(** In general, SetoidPermutation is equivalent to Permutation modulo setoid list equivalence: *)
Lemma SetoidPermutation_meaning {A} (R: relation A) `{!Equivalence R} (x y: list A):
SetoidPermutation R x y ↔ ∃ y', list_eq R x y' ∧ Permutation y y'.
Proof with auto.
split.
intro H. induction H.
exists nil. intuition.
destruct IHSetoidPermutation as [?[??]].
exists (y :: x0).
repeat split...
exists (y :: x :: l).
split... reflexivity.
destruct IHSetoidPermutation1 as [x [H1 H3]].
destruct IHSetoidPermutation2 as [x0 [H2 H4]].
symmetry in H3.
destruct (Perm_list_eq_commute R x l' x0 H3 H2).
exists x1.
split.
transitivity x; intuition.
transitivity x0; intuition.
intros [?[E?]]. rewrite E.
symmetry. apply SetoidPermutation_from_Permutation...
apply _.
Qed.
Instance map_perm_proper {A B} (Ra: relation A) (Rb: relation B):
Equivalence Ra →
Equivalence Rb →
Proper ((Ra ==> Rb) ==> SetoidPermutation Ra ==> SetoidPermutation Rb) (@map A B).
Proof with simpl; auto; try reflexivity.
intros ??????? X.
induction X; simpl...
apply s_perm_trans with (x y0 :: x x0 :: map y l).
apply s_perm_skip...
apply s_perm_skip...
induction l... intuition.
apply s_perm_trans with (y y0 :: y x0 :: map y l)...
unfold respectful in *.
apply s_perm_skip. intuition.
apply s_perm_skip... intuition.
apply s_perm_trans with (map y l')...
apply s_perm_trans with (map x l')...
clear IHX1 IHX2 X1 X2.
induction l'... intuition.
Qed.
|
#include <bits/stdc++.h> using namespace std; clock_t __stt; inline void TStart() { __stt = clock(); } inline void TReport() { printf( nTaken Time : %.3lf sec n , (double)(clock() - __stt) / CLOCKS_PER_SEC); } template <typename T> T MIN(T a, T b) { return a < b ? a : b; } template <typename T> T MAX(T a, T b) { return a > b ? a : b; } template <typename T> T ABS(T a) { return a > 0 ? a : (-a); } template <typename T> void UMIN(T &a, T b) { if (b < a) a = b; } template <typename T> void UMAX(T &a, T b) { if (b > a) a = b; } const int bc = 6, mc = 64; int n, m, subcnt[mc], chcnt[mc], avai[100005]; char s[100005], tmp[10]; int main() { int i, j, k; scanf( %s , s); n = strlen(s); scanf( %d , &m); fill(avai, avai + n, mc - 1); while (m--) { scanf( %d%s , &j, tmp); k = strlen(tmp); avai[--j] = 0; for (i = 0; i < k; ++i) { avai[j] += (1 << (tmp[i] - a )); } } for (i = 0; i < n; ++i) { for (j = 0; j < mc; ++j) { if ((avai[i] & j) == avai[i]) { ++subcnt[j]; } if ((1 << (s[i] - a )) & j) { ++chcnt[j]; } } } for (i = 0; i < n; ++i) { for (j = 0; j < bc; ++j) { if (!(avai[i] & (1 << j))) continue; s[i] = a + j; for (k = 0; k < mc; ++k) { if ((avai[i] & k) == avai[i]) { --subcnt[k]; } if ((1 << j) & k) { --chcnt[k]; } } for (k = 0; k < mc; ++k) { if (chcnt[k] < subcnt[k]) break; } if (k == mc) break; for (k = 0; k < mc; ++k) { if ((avai[i] & k) == avai[i]) { ++subcnt[k]; } if ((1 << j) & k) { ++chcnt[k]; } } } if (j == bc) { printf( Impossible n ); return 0; } } printf( %s n , s); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_MUX_2TO1_N_TB_V
`define SKY130_FD_SC_LP__UDP_MUX_2TO1_N_TB_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_mux_2to1_n.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 A0 = 1'b1;
#100 A1 = 1'b1;
#120 S = 1'b1;
#140 A0 = 1'b0;
#160 A1 = 1'b0;
#180 S = 1'b0;
#200 S = 1'b1;
#220 A1 = 1'b1;
#240 A0 = 1'b1;
#260 S = 1'bx;
#280 A1 = 1'bx;
#300 A0 = 1'bx;
end
sky130_fd_sc_lp__udp_mux_2to1_N dut (.A0(A0), .A1(A1), .S(S), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_MUX_2TO1_N_TB_V
|
#include <bits/stdc++.h> using namespace std; const int MAX_PRIMES = 15; vector<int> primes; vector<int> num[(1 << MAX_PRIMES) + 5]; bool used[(1 << MAX_PRIMES) + 5]; vector<int> BFS(int sz, int k) { queue<int> fila; vector<int> ans; fila.push((1 << sz) - 1); used[(1 << sz) - 1] = true; while (!fila.empty() && ans.size() < k) { int mask = fila.front(); fila.pop(); for (int i = 0; i < (int)num[mask].size() && ans.size() < k; i++) { ans.push_back(num[mask][i]); } for (int i = 0; i < sz; i++) { int nmask = mask & (~(1 << i)); int bit = (mask >> i) & 1; if (bit && !used[nmask]) { used[nmask] = true; fila.push(nmask); } } } return ans; } int main(void) { int k; int maxi; vector<int> ans; scanf( %d , &k); maxi = 2 * k * k; for (int i = 2;; i++) { bool good = true; for (int j = 0; j < (int)primes.size(); j++) { if (i % primes[j] == 0) { good = false; break; } } if (good) { int val = 1; while (1LL * val * i <= maxi) { num[1 << primes.size()].push_back(val * i); val *= i; } for (int mask = 1; mask < 1 << primes.size(); mask++) { int nmask = (1 << primes.size()) | mask; for (int j = 0; j < num[mask].size(); j++) { for (int p = 0; p < num[1 << primes.size()].size(); p++) { if (1LL * num[mask][j] * num[1 << primes.size()][p] > maxi) break; num[nmask].push_back(num[mask][j] * num[1 << primes.size()][p]); } } } primes.push_back(i); int counter = 0; for (int mask = 1; mask < 1 << primes.size(); mask++) { counter += num[mask].size(); } if (counter >= k) { ans = BFS(primes.size(), k); break; } } } for (int i = 0; i < (int)ans.size(); i++) { if (i != 0) { printf( ); } printf( %d , ans[i]); } printf( n ); return 0; }
|
#include <bits/stdc++.h> const double PI = 3.141592653589793238463; using namespace std; inline long long add(long long a, long long b) { a += b; if (a >= 1000000007) a -= 1000000007; return a; } inline long long sub(long long a, long long b) { a -= b; if (a < 0) a += 1000000007; return a; } inline long long mul(long long a, long long b) { return (long long)((long long)a * b % 1000000007); } long long fast_power(long long base, long long power) { long long result = 1; while (power > 0) { if (power % 2 == 1) { result = (result * base); } base = (base * base); power = power / 2; } return result; } long long min(long long a, long long b) { return a > b ? b : a; } long long max(long long a, long long b) { return a > b ? a : b; } void SieveOfEratosthenes(long long n, unordered_set<long long> &s) { bool prime[n + 1]; memset(prime, true, sizeof(prime)); for (long long p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[i] = false; } } for (long long p = 2; p <= n; p++) if (prime[p]) s.insert(p); } void dfs(long long s, vector<bool> &vis, vector<vector<long long>> &adlist) { if (vis[s]) return; vis[s] = true; for (auto x : adlist[s]) { if (vis[x] == false) { cout << s << << x << n ; } dfs(x, vis, adlist); } } void bfs(long long x, vector<bool> &vis, vector<vector<long long>> &adlist) { queue<long long> q; vis[x] = true; q.push(x); while (!q.empty()) { long long s = q.front(); q.pop(); for (auto u : adlist[s]) { if (vis[u]) continue; vis[u] = true; q.push(u); } } } bool bpchk(vector<vector<long long>> &adj, vector<long long> &color) { color[1] = 1; queue<long long> q; q.push(1); while (!q.empty()) { long long u = q.front(); q.pop(); for (auto x : adj[u]) { if (color[x] == -1) { color[x] = color[u] ^ 1; q.push(x); } } } for (long long i = 1; i < adj.size(); i++) { for (auto x : adj[i]) { if (color[x] == color[i]) return false; } } return true; } int main() { string s; cin >> s; bool flag = true; long long zc = 0, oc = 0; for (long long i = 0; i < s.size(); i++) { if (s[i] == 0 ) { zc += 1; } else { oc += 1; } if (zc < oc) { flag = false; break; } } zc = 0, oc = 0; for (long long i = s.size() - 1; i >= 0; i--) { if (s[i] == 0 ) { zc += 1; } else { oc += 1; } if (zc < oc) { flag = false; break; } } if (flag == false) { cout << -1 << n ; } else { long long vecsz = 0; long long ctr = 1; long long i = 0; vector<long long> s2; while (i < s.size()) { if (i == 0) { ctr = 1; s2.push_back(ctr); } else { if (s[i] == s[i - 1] && s[i] == 0 ) { ctr += 1; s2.push_back(ctr); } else if (s[i] == s[i - 1] && s[i] == 1 ) { ctr -= 1; s2.push_back(ctr); } else { s2.push_back(ctr); } } vecsz = max(vecsz, ctr); i += 1; } cout << vecsz << n ; vector<vector<long long>> v(vecsz + 1, vector<long long>()); for (long long i = 0; i < s2.size(); i++) { v[s2[i]].push_back(i + 1); } for (long long i = 1; i < v.size(); i++) { cout << v[i].size() << ; for (long long j = 0; j < v[i].size(); j++) { cout << v[i][j] << ; } cout << n ; } } }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xen <>
* Copyright (C) 2018 David Shah <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_nexus_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
function integer round_up2;
input integer N;
begin
round_up2 = ((N + 1) / 2) * 2;
end
endfunction
localparam Y_WIDTH2 = round_up2(Y_WIDTH);
(* force_downto *)
wire [Y_WIDTH2-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] BX = B_buf;
(* force_downto *)
wire [Y_WIDTH2+1:0] FCO, Y1;
genvar i;
// Carry feed-in
CCU2 #(
.INIT0("0xFFFF"),
.INIT1("0x00AA"),
.INJECT("NO")
) ccu2c_i (
.A0(1'b1), .B0(1'b1), .C0(1'b1), .D0(1'b1),
.A1(CI), .B1(1'b1), .C1(1'b1), .D1(1'b1),
.COUT(FCO[0])
);
generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
CCU2 #(
.INIT0("0x96AA"),
.INIT1("0x96AA"),
.INJECT("NO")
) ccu2c_i (
.CIN(FCO[i]),
.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),
.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),
.S0(Y[i]), .S1(Y1[i]),
.COUT(FCO[i+2])
);
assign CO[i] = (AA[i] && BB[i]) || (((i == 0) ? CI : CO[i-1]) && (AA[i] || BB[i]));
if (i+1 < Y_WIDTH) begin
assign CO[i+1] = (AA[i+1] && BB[i+1]) || (CO[i] && (AA[i+1] || BB[i+1]));
assign Y[i+1] = Y1[i];
end
end endgenerate
assign X = AA ^ BB;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { long long n, m; cin >> n >> m; vector<string> ar(11); for (int i = 0; i < n; i++) { cin >> ar[i]; } string ans; bool res = false; for (int i = 0; i < m && !res; i++) { for (int j = 0; j < 26 && !res; j++) { string s = ar[0]; s[i] = a + j; bool te = true; for (int k = 0; k < n; k++) { long long co = 0; for (int l = 0; l < m; l++) { if (ar[k][l] != s[l]) { co++; } } if (co > 1) { te = false; break; } } if (te) { cout << s << endl; res = true; break; } } } if (!res) { cout << -1 << endl; } } }
|
#include <bits/stdc++.h> using namespace std; const long double pi = acos(-1.0); long long int inf = 0x3f3f3f3f3f3f3f3f; const long long int mod = 1e9 + 7; const long long int mx = 5 * 1000000; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; cin >> t; while (t--) { long long int n, T, a, b; cin >> n >> T >> a >> b; long long int type[n + 1]; for (long long int i = 0; i < n; i++) cin >> type[i]; vector<long long int> easy, hard; vector<long long int> seq; seq.push_back(0); set<long long int> ss; for (long long int i = 0; i < n; i++) { long long int in; cin >> in; ss.insert(in); if (type[i] == 0) easy.push_back(in); else hard.push_back(in); } for (auto i : ss) seq.push_back(max(i - 1, 0ll)); seq.push_back(T); sort(easy.begin(), easy.end()); sort(hard.begin(), hard.end()); long long int ans = 0; for (auto i : seq) { auto ee = upper_bound(easy.begin(), easy.end(), i); long long int ee1; if (ee == easy.end()) ee1 = easy.size(); else ee1 = ee - easy.begin(); auto hh = upper_bound(hard.begin(), hard.end(), i); long long int hh1; if (hh == hard.end()) hh1 = hard.size(); else hh1 = hh - hard.begin(); long long int mandt = ee1 * a + hh1 * b; long long int temp = 0; if (mandt <= i) temp = ee1 + hh1; long long int rem_time = i - mandt; long long int rem_easy = easy.size() - ee1; long long int rem_hard = hard.size() - hh1; temp += min(rem_easy, rem_time / a); rem_time -= min(rem_easy, rem_time / a) * a; temp += min(rem_hard, rem_time / b); ans = max(ans, temp); } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = (int)2e5 + 10, L = 4, INF = (int)1e9; struct State { int fa, len, tr[L], w[L]; } SAM[MAXN]; char t[MAXN]; vector<int> l[MAXN]; int m, tot; unsigned long long a[L], b[L][L], c[L][L]; unsigned long long n; int Build(int pre, int id) { int cp = ++tot; SAM[cp].len = SAM[pre].len + 1; for (; !SAM[pre].tr[id] && pre; SAM[pre].tr[id] = cp, pre = SAM[pre].fa) ; if (pre) if (SAM[pre].len + 1 == SAM[SAM[pre].tr[id]].len) SAM[cp].fa = SAM[pre].tr[id]; else { int tp = SAM[pre].tr[id]; ++tot, SAM[tot].len = SAM[pre].len + 1, SAM[tot].fa = SAM[tp].fa; memcpy(SAM[tot].tr, SAM[tp].tr, sizeof(SAM[tot].tr)); SAM[cp].fa = SAM[tp].fa = tot; for (; pre && SAM[pre].tr[id] == tp; SAM[pre].tr[id] = tot, pre = SAM[pre].fa) ; } else SAM[cp].fa = 1; return cp; } void init() { cin >> n; scanf( %s , t + 1); m = strlen(t + 1); tot = 1; for (int i = 1, p = 1; i <= m; ++i) p = Build(p, t[i] - A ); for (int i = 1; i <= tot; ++i) { for (int j = 0; j < L; ++j) if (!SAM[i].tr[j]) SAM[i].w[j] = 1; else SAM[i].w[j] = INF; l[SAM[i].len].push_back(i); } for (int i = m; i >= 0; --i) for (int j = 0; j < (int)l[i].size(); ++j) for (int k = 0; k < L; ++k) if (SAM[l[i][j]].tr[k]) for (int p = 0; p < L; ++p) { int first = l[i][j]; SAM[first].w[p] = min(SAM[first].w[p], SAM[SAM[first].tr[k]].w[p] + 1); } } void mul(unsigned long long a[][L], unsigned long long b[][L], unsigned long long c[][L]) { static unsigned long long w[L][L]; for (int i = 0; i < L; ++i) for (int j = 0; j < L; ++j) w[i][j] = n + 1; for (int i = 0; i < L; ++i) for (int j = 0; j < L; ++j) for (int k = 0; k < L; ++k) w[i][j] = min(w[i][j], b[i][k] + c[k][j]); for (int i = 0; i < L; ++i) for (int j = 0; j < L; ++j) a[i][j] = w[i][j]; } void Pow(unsigned long long a[][L], unsigned long long b) { static unsigned long long d[L][L]; for (int i = 0; i < L; ++i) for (int j = 0; j < L; ++j) d[i][j] = n + 1; for (int i = 0; i < L; ++i) d[i][i] = 0; for (; b; mul(a, a, a), b /= 2) if (b & 1) mul(d, d, a); memcpy(a, d, sizeof(d)); } unsigned long long check(unsigned long long k) { memcpy(b, c, sizeof(b)); Pow(b, k - 2); unsigned long long Tohka = n + 1; for (int i = 0; i < L; ++i) for (int j = 0; j < L; ++j) Tohka = min(Tohka, a[i] + b[i][j]); return Tohka; } unsigned long long Find(unsigned long long l, unsigned long long r) { while (l <= r) { unsigned long long mid = (l + r) >> 1; if (check(mid) > n) r = mid - 1; else l = mid + 1; } return r; } void solve() { for (int i = 0; i < L; ++i) a[i] = max(SAM[1].w[i], 1); for (int i = 0; i < L; ++i) for (int j = 0; j < L; ++j) c[i][j] = max(SAM[SAM[1].tr[i]].w[j], 1); if (n == 1) puts( 1 ); else cout << Find(2, n) << endl; } int main() { init(); solve(); fclose(stdin); fclose(stdout); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_V
|
// file: hashing_clock_multiplier.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___400.000______0.000______50.0_______85.815_____89.971
// CLK_OUT2___100.000______0.000______50.0______112.316_____89.971
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________200.000____________0.010
`timescale 1ps/1ps
module hashing_clock_multiplier_clk_wiz
(// Clock in ports
input clk_in1_p,
input clk_in1_n,
// Clock out ports
output tx_hash_clk,
output tx_comm_clk
);
// Input buffering
//------------------------------------
IBUFGDS clkin1_ibufgds
(.O (clk_in1_hashing_clock_multiplier),
.I (clk_in1_p),
.IB (clk_in1_n));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_hashing_clock_multiplier;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (5.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (2.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (10),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (5.0),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout_hashing_clock_multiplier),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (tx_hash_clk_hashing_clock_multiplier),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (tx_comm_clk_hashing_clock_multiplier),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_hashing_clock_multiplier),
.CLKIN1 (clk_in1_hashing_clock_multiplier),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (tx_hash_clk),
.I (tx_hash_clk_hashing_clock_multiplier));
BUFG clkout2_buf
(.O (tx_comm_clk),
.I (tx_comm_clk_hashing_clock_multiplier));
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> cities[100000]; vector<bool> visited(100000); vector<int> t(100000), low(100000); map<pair<int, int>, int> b; int c = 0, ans = 0; void dfs(int v, int p = -1) { visited[v] = true; t[v] = low[v] = c++; for (int dest : cities[v]) { if (dest == p) continue; if (visited[dest]) { low[v] = min(low[v], t[dest]); } else { dfs(dest, v); low[v] = min(low[v], low[dest]); if (low[dest] > t[v]) { b[{v, dest}] = 1; b[{dest, v}] = 1; } else { b[{v, dest}] = 0; b[{dest, v}] = 0; } } } } vector<long long> dist(100001); void Dijkstra(int r, int e) { set<pair<int, int> > s; dist[r] = 0; s.insert({0, r}); while (!s.empty()) { pair<int, int> p = *s.begin(); s.erase(s.begin()); int x = p.first, y = p.second; if (x > dist[y]) { continue; } else if (dist[e] != INT_MAX) { return; } for (int j = 0; j < cities[y].size(); j++) { if (dist[y] + b[{y, cities[y][j]}] < dist[cities[y][j]]) { dist[cities[y][j]] = dist[y] + b[{y, cities[y][j]}]; s.insert({dist[cities[y][j]], cities[y][j]}); } } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m, k; cin >> n >> m; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; cities[x - 1].push_back(y - 1); cities[y - 1].push_back(x - 1); } c = 0; t.assign(n, -1); low.assign(n, -1); visited.assign(n, false); for (int i = 0; i < n; ++i) { if (!visited[i]) { dfs(i); } } cin >> k; for (int i = 0; i < k; i++) { ans = 0; dist.assign(n, INT_MAX); int root, shop; cin >> root >> shop; Dijkstra(root - 1, shop - 1); cout << dist[shop - 1] << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A22O_BEHAVIORAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int pkt; int start = 0; int lr = 0; cin >> pkt; if (pkt < 0) pkt = pkt / -1; for (int a = 1; start != pkt; a++) { start = start + a; lr++; if (start > pkt) { if ((start - pkt) % 2 == 1) ; else break; } } cout << lr << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under The Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
timeunit 1ns;
timeprecision 1ps;
time t;
initial begin
t = 10ns;
$write("[%0t] In %m: Hi\n", $time);
$printtimescale;
$printtimescale();
$printtimescale(t);
$write("Time: '%t' 10ns=%0t\n", $time, t);
$timeformat(-3, 0, "-my-ms", 8);
$write("Time: '%t' 10ns=%0t\n", $time, t);
$timeformat(-3, 1, "-my-ms", 10);
$write("Time: '%t' 10ns=%0t\n", $time, t);
$timeformat(-6, 2, "-my-us", 12);
$write("Time: '%t' 10ns=%0t\n", $time, t);
$timeformat(-9, 3, "-my-ns", 13);
$write("Time: '%t' 10ns=%0t\n", $time, t);
$timeformat(-12, 3, "-my-ps", 13);
$write("Time: '%t' 10ns=%0t\n", $time, t);
$timeformat(-15, 4, "-my-fs", 14);
$write("Time: '%t' 10ns=%0t\n", $time, t);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int mx = 0, i, n, m, d, h, ld, lh; cin >> n >> m; for (i = 0; i < m; i++) { cin >> d >> h; if (i == 0) { ld = d; lh = h; mx = lh + ld - 1; continue; } if (abs(h - lh) > d - ld) { cout << IMPOSSIBLE ; return 0; } if (h - lh < 0) mx = max(mx, lh + (d - ld - abs(h - lh)) / 2); else mx = max(mx, h + (d - ld - abs(h - lh)) / 2); ld = d; lh = h; } mx = max(mx, lh + n - ld); cout << mx; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a[26]; char pal[111111]; inline bool is_pal(int k, int can) { vector<int> odd(0); for (int i = 0; i < n; ++i) { if (a[i] % k) return 0; if (a[i] % (2 * k)) odd.push_back(i); } if ((int)(odd).size() > 1) return 0; if ((int)(odd).size() == 1 && !can) return 0; int pos = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j < a[i] / (2 * k); ++j) { pal[pos++] = a + i; } } if ((int)(odd).size()) pal[pos++] = a + odd[0]; for (int i = n - 1; i >= 0; --i) { for (int j = 0; j < a[i] / (2 * k); ++j) { pal[pos++] = a + i; } } pal[pos] = 0; return 1; } inline void die(int ans, int reps, char middle) { printf( %d n , ans); for (int i = 0; i < reps; ++i) { printf( %s , pal); if (middle != ! ) printf( %c , middle); } printf( n ); exit(0); } int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); } for (int ans = 111111; ans > 1; --ans) { if (ans % 2 == 1) { for (int let = 0; let < n; ++let) { if (a[let] >= ans) { a[let] -= ans; if (is_pal(ans, 0)) { die(ans, ans, a + let); } a[let] += ans; } } } else { for (int let = 0; let < n; ++let) { if (is_pal(ans / 2, 0)) { die(ans, ans / 2, ! ); } } } } if (is_pal(1, 1)) { die(1, 1, ! ); } printf( 0 n ); for (int i = 0; i < n; ++i) { for (int j = 0; j < a[i]; ++j) { printf( %c , a + i); } } printf( n ); }
|
#include <bits/stdc++.h> using namespace std; int gi() { int a; scanf( %d , &a); return a; } long long gli() { long long a; scanf( %I64d , &a); return a; } long long gcd(long long a, long long b) { if (a == 0) return b; if (b == 0) return a; if (a > b) return gcd(a % b, b); return gcd(b % a, a); } int pr[1000000]; int main() { unordered_map<long long, vector<pair<long long, long long> > > m; unordered_map<long long, vector<pair<long long, long long> > >::iterator it; int n = gi(); for (int i = 0; i < n; i++) { long long x = gli(); long long y = gli(); long long c = gli(); m[x].push_back(make_pair(y, c)); } vector<pair<long long, long long> > main; int L = 0; long long gg = 0; int first = 1; for (it = m.begin(); it != m.end(); it++) { vector<pair<long long, long long> > &v = it->second; sort(v.begin(), v.end()); if (first) { first = 0; L = v.size(); long long g = 0; for (int i = 0; i < L; i++) g = gcd(g, v[i].second); for (int i = 0; i < L; i++) main.push_back(make_pair(v[i].first, v[i].second / g)); } else { if (int(v.size()) != L || v[0].first != main[0].first || v[0].second % main[0].second != 0) { printf( 0 n ); return 0; } long long f = v[0].second / main[0].second; for (int i = 1; i < L; i++) if (v[i].first != main[i].first || v[i].second % main[i].second != 0 || v[i].second / main[i].second != f) { printf( 0 n ); return 0; } } gg = gcd(gg, v[0].second); } m.clear(); long long g = 0; for (int i = 0; i < L; i++) g = gcd(g, main[i].second); g *= gg / main[0].second; memset(pr, -1, sizeof(pr)); long long r = 1; long long c = 1; while (g % 2 == 0) { c++; g /= 2; } r *= c; for (int i = 3; i < 1000000; i += 2) if (pr[i]) { for (int j = i * 3; j < 1000000; j += i * 2) pr[i] = 0; long long c = 1; while (g % i == 0) { c++; g /= i; } r *= c; } if (g > 1LL) r *= 2; cout << r << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } template <class T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T, class T1> inline void gn(T &first, T1 &second) { gn(first); gn(second); } template <class T, class T1, class T2> inline void gn(T &first, T1 &second, T2 &z) { gn(first); gn(second); gn(z); } template <class T> inline void print(T first) { if (first < 0) { putchar( - ); return print(-first); } if (first < 10) { putchar( 0 + first); return; } print(first / 10); putchar(first % 10 + 0 ); } template <class T> inline void printsp(T first) { print(first); putchar( ); } template <class T> inline void println(T first) { print(first); putchar( n ); } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } struct Node { int sz, val; Node *ls, *rs, *fa; } buf[1111111]; int used; struct Splay_Tree { Node *root, *NIL, *minf, *pinf; Node *create_node(int first = 0) { Node *node = &buf[used++]; node->sz = 1; node->val = first; node->ls = node->rs = node->fa = NIL; return node; } void init() { used = 0; NIL = create_node(0); NIL->sz = 0; Node *first = create_node(-0x3f3f3f3f); Node *second = create_node(0x3f3f3f3f); first->rs = second; second->fa = first; root = first; minf = first; pinf = second; update(first); } void update(Node *first) { first->sz = first->ls->sz + first->rs->sz + 1; } void zig(Node *first) { Node *second = first->rs, *p = first->fa; first->rs = second->ls; second->ls->fa = first; second->ls = first; first->fa = second; second->fa = p; if (p == NIL) root = second; else if (p->ls == first) p->ls = second; else p->rs = second; update(first); } void zag(Node *first) { Node *second = first->ls, *p = first->fa; first->ls = second->rs; second->rs->fa = first; second->rs = first; first->fa = second; second->fa = p; if (p == NIL) root = second; else if (p->rs == first) p->rs = second; else p->ls = second; update(first); } void splay(Node *first, Node *g) { Node *second, *z; while (first->fa != g) { second = first->fa; z = second->fa; if (z == g) { if (first == second->rs) zig(second); else zag(second); } else if (second == z->rs) { if (first == second->rs) zig(z), zig(second); else zag(second), zig(z); } else { if (first == second->rs) zig(second), zag(z); else zag(z), zag(second); } } update(first); } Node *find(Node *first, int k) { if (k <= first->ls->sz) return find(first->ls, k); if (k == first->ls->sz + 1) return first; return find(first->rs, k - first->ls->sz - 1); } Node *next(Node *first, int val) { if (first == NIL) return first; if (first->val > val) { Node *ans = next(first->ls, val); if (ans == NIL) ans = first; return ans; } else return next(first->rs, val); } Node *prev(Node *first, int val) { if (first == NIL) return first; if (first->val < val) { Node *ans = prev(first->rs, val); if (ans == NIL) ans = first; return ans; } else return prev(first->ls, val); } Node *insert(int val) { Node *first = create_node(val); Node *z = prev(root, val); Node *second = next(root, val); splay(z, NIL); splay(second, z); first->fa = second; second->ls = first; update(second); update(z); return first; } void removeFront(int val) { Node *first = minf; Node *second = next(root, val); splay(first, NIL); splay(second, first); second->ls = NIL; update(second); update(first); } void removeBack(int val) { Node *first = pinf; Node *second = prev(root, val); splay(first, NIL); splay(second, first); second->rs = NIL; update(second); update(first); } void remove(int k) { Node *z = find(root, k), *second = find(root, k + 2); splay(z, NIL); splay(second, z); second->ls = NIL; update(second); update(z); } void remove(Node *first) { splay(first, NIL); remove(first->ls->sz); } void dup(Node *first) { if (first == NIL) return; dup(first->ls); printf( %d , first->val); dup(first->rs); } } tree; int N, s1, s2; int first[111111]; bool possible(int d) { tree.init(); tree.insert(s1); int cur = s2; for (int i = 0; i < N; i++) { if (abs(cur - first[i]) <= d) tree.insert(cur); tree.removeFront(max(first[i] - d - 1, -0x3f3f3f3f + 1)); tree.removeBack(min(first[i] + d + 1, 0x3f3f3f3f - 1)); if (tree.root->sz == 2) { return false; } cur = first[i]; } return true; } int main() { gn(N, s1, s2); for (int i = 0; i < N; i++) gn(first[i]); int high = 1000000000, low = abs(s1 - s2); while (high > low + 1) { int mid = (high + low) / 2; if (possible(mid)) high = mid; else low = mid; } if (possible(low)) printf( %d n , low); else printf( %d n , high); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long inv[100010], fac[100010], p[100010], t[100010][20]; int n, l, r, P, tot, Phi; int phi(int k) { int i, s; s = k; for (i = 2; i * i <= k; i++) { if (k % i == 0) s = s / i * (i - 1); while (k % i == 0) k /= i; } if (k > 1) s = s / k * (k - 1); return s; } long long qpow(long long a, long long b, long long mod) { long long res = 1; while (b) { if (b & 1) res = res * a % mod; b >>= 1; a = a * a % mod; } return res; } void init() { long long x = P; Phi = phi(P); for (int i = 2; (long long)i * i <= x; i++) { if (x % i) continue; while (x % i == 0) x /= i; p[++tot] = i; } if (x > 1) p[++tot] = x; inv[0] = inv[1] = 1; fac[0] = fac[1] = 1; for (int i = 2; i < 100010; i++) { x = i; for (int j = 1; j <= tot; j++) { t[i][j] = t[i - 1][j]; if (x % p[j]) continue; while (x % p[j] == 0) x /= p[j], t[i][j]++; } fac[i] = fac[i - 1] * x % P; inv[i] = qpow(fac[i], Phi - 1, P); } } long long C(int n, int m) { long long res = 0; if (n < m || n < 0) return 0; res = fac[n] * inv[m] % P * inv[n - m] % P; for (int i = 1; i <= tot; i++) res = res * qpow(p[i], t[n][i] - t[m][i] - t[n - m][i], P) % P; return res; } int main() { scanf( %d%d%d%d , &n, &P, &l, &r); init(); long long ans = 0; for (int i = 0; i <= n; i++) { int m = n - i; ans = (ans + C(n, i) * (-C(m, (m + min(r, m) >> 1) + 1) + C(m, m + l + 1 >> 1)) % P) % P; } printf( %I64d n , ans); return 0; }
|
/*
# reset.v - System reset counter, count down for 32 clocks
#
# Copyright (C) 2014 Binary Logic (nhi.phan.logic at gmail.com).
#
# This file is part of the Virtual JTAG UART toolkit
#
# Virtual UART is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
*/
//=======================================================
// System reset timer
//=======================================================
`include "system_include.v"
module reset (
//////////// CLOCK //////////
input clk_i,
//////////// reset signal //////////
output nreset_o
);
reg [3:0] reset_counter = 4'b1111;
// Reset is LOW until reset counter is 0, then goes high and stays high
assign nreset_o = (reset_counter == 1'b0);
always @(posedge clk_i)
begin
if( reset_counter > 1'b0 ) reset_counter = reset_counter - 1'b1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[111][111][11], n, q, c, x, y, rx, ry, t, v; int main() { cin >> n >> q >> c; for (int i = 1; i <= n; i++) { cin >> x >> y >> t; a[x][y][t]++; } for (int l = 0; l <= c; l++) { for (int i = 1; i <= 100; i++) for (int j = 1; j <= 100; j++) a[i][j][l] += a[i][j - 1][l]; for (int i = 1; i <= 100; i++) for (int j = 1; j <= 100; j++) a[i][j][l] += a[i - 1][j][l]; } for (int i = 1; i <= q; i++) { v = 0; cin >> t >> x >> y >> rx >> ry; for (int j = 0; j <= c; j++) v += (j + t) % (c + 1) * (a[rx][ry][j] - a[rx][y - 1][j] - a[x - 1][ry][j] + a[x - 1][y - 1][j]); cout << v << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int loc[400000]; long long sumlen[400000]; double profit[400000]; int a[400000]; int b[400000]; double hit[200000]; class MaxSubstringSum { public: MaxSubstringSum(int n) { int real_n = 1; while (real_n < n) { real_n *= 2; } lb_ = new int[2 * real_n + 1]; ub_ = new int[2 * real_n + 1]; max_value_ = new double[2 * real_n + 1]; max_left_ = new double[2 * real_n + 1]; max_right_ = new double[2 * real_n + 1]; sum_all_ = new double[2 * real_n + 1]; for (int(i) = 0; (i) < (2 * real_n + 1); ++(i)) { lb_[i] = ub_[i] = 0; max_value_[i] = max_left_[i] = max_right_[i] = sum_all_[i] = 0.0; } for (int i = 0; i < real_n; ++i) { lb_[real_n + i] = i; ub_[real_n + i] = i; } for (int i = real_n - 1; i >= 1; --i) { lb_[i] = lb_[i * 2]; ub_[i] = ub_[i * 2 + 1]; } } void Build(int node) { if (lb_[node] == ub_[node]) { max_value_[node] = max_left_[node] = max_right_[node] = max(0.0, profit[lb_[node]]); sum_all_[node] = profit[lb_[node]]; } else { Build(node * 2); Build(node * 2 + 1); sum_all_[node] = sum_all_[node * 2] + sum_all_[node * 2 + 1]; max_left_[node] = max(max_left_[node * 2], sum_all_[node * 2] + max_left_[node * 2 + 1]); max_right_[node] = max(max_right_[node * 2 + 1], sum_all_[node * 2 + 1] + max_right_[node * 2]); max_value_[node] = max(max_value_[node * 2], max(max_value_[node * 2 + 1], max_right_[node * 2] + max_left_[node * 2 + 1])); } } double GetLMax(int low, int hi, int node = 1) { if (lb_[node] >= low && ub_[node] <= hi) { return max_left_[node]; } if (lb_[node] > hi || ub_[node] < low) return 0.0; double ret = GetLMax(low, hi, node * 2); if (lb_[node * 2] >= low && ub_[node * 2] <= hi) { ret = max((ret), (GetLMax(low, hi, node * 2 + 1) + sum_all_[node * 2])); } return ret; } double GetRMax(int low, int hi, int node = 1) { if (lb_[node] >= low && ub_[node] <= hi) { return max_right_[node]; } if (lb_[node] > hi || ub_[node] < low) return 0.0; double ret = GetRMax(low, hi, node * 2 + 1); if (lb_[node * 2 + 1] >= low && ub_[node * 2 + 1] <= hi) { ret = max((ret), (GetRMax(low, hi, node * 2) + sum_all_[node * 2 + 1])); } return ret; } double GetMax(int low, int hi, int node = 1) { if (lb_[node] >= low && ub_[node] <= hi) { return max_value_[node]; } if (lb_[node] > hi || ub_[node] < low) return 0.0; double best = max(GetMax(low, hi, node * 2), GetMax(low, hi, node * 2 + 1)); best = max((best), (GetRMax(low, hi, node * 2) + GetLMax(low, hi, node * 2 + 1))); return best; } private: int* lb_; int* ub_; double* max_value_; double* max_left_; double* max_right_; double* sum_all_; }; int main() { int n, m, c; cin >> n >> m >> c; for (int(i) = 0; (i) < (n); ++(i)) { scanf( %d , loc + i); } sumlen[0] = 0; for (int(i) = (1); (i) < (n); ++(i)) { sumlen[i] = sumlen[i - 1] + (long long)loc[i] - (long long)loc[i - 1]; } for (int(i) = 0; (i) < (n - 1); ++(i)) { int x; scanf( %d , &x); hit[i] = (double)x / 100.0; } for (int(i) = 0; (i) < (m); ++(i)) { scanf( %d%d , a + i, b + i); } for (int(i) = 0; (i) < (n - 1); ++(i)) { profit[i] = (double)(loc[i + 1] - loc[i]) / 2.0 - (double)hit[i] * (double)c; } MaxSubstringSum tree(n); tree.Build(1); double ret = 0.0; for (int(i) = 0; (i) < (m); ++(i)) { ret += tree.GetMax(a[i] - 1, b[i] - 2, 1); } printf( %.10lf n , ret); }
|
//---------------------------------------------------------------------------------------
// uart top level module
//
//---------------------------------------------------------------------------------------
module uart_top
(
// global signals
clock, reset,
// uart serial signals
ser_in, ser_out,
// transmit and receive internal interface signals
rx_data, new_rx_data,
tx_data, new_tx_data, tx_busy,
// baud rate configuration register - see baud_gen.v for details
baud_freq, baud_limit,
baud_clk
);
//---------------------------------------------------------------------------------------
// modules inputs and outputs
input clock; // global clock input
input reset; // global reset input
input ser_in; // serial data input
output ser_out; // serial data output
input [7:0] tx_data; // data byte to transmit
input new_tx_data; // asserted to indicate that there is a new data byte for transmission
output tx_busy; // signs that transmitter is busy
output [7:0] rx_data; // data byte received
output new_rx_data; // signs that a new byte was received
input [11:0] baud_freq; // baud rate setting registers - see header description
input [15:0] baud_limit;
output baud_clk;
// internal wires
wire ce_16; // clock enable at bit rate
assign baud_clk = ce_16;
//---------------------------------------------------------------------------------------
// module implementation
// baud rate generator module
baud_gen baud_gen_1
(
.clock(clock), .reset(reset),
.ce_16(ce_16), .baud_freq(baud_freq), .baud_limit(baud_limit)
);
// uart receiver
uart_rx uart_rx_1
(
.clock(clock), .reset(reset),
.ce_16(ce_16), .ser_in(ser_in),
.rx_data(rx_data), .new_rx_data(new_rx_data)
);
// uart transmitter
uart_tx uart_tx_1
(
.clock(clock), .reset(reset),
.ce_16(ce_16), .tx_data(tx_data), .new_tx_data(new_tx_data),
.ser_out(ser_out), .tx_busy(tx_busy)
);
endmodule
//---------------------------------------------------------------------------------------
// Th.. Th.. Th.. Thats all folks !!!
//---------------------------------------------------------------------------------------
|
Require Import List.
Require ReifySepExpr.
Require Import ILTacCommon.
Require Import SepIL.
Require Import TacPackIL.
Require Import IL ILEnv SymIL.
Require Import Word Memory.
Require Import Env.
Require PropX.
Require Import ILTacCommon.
Set Implicit Arguments.
Set Strict Implicit.
Add ML Path "reification".
Declare ML Module "extlib".
Declare ML Module "reif".
(** Cancellation **)
(******************)
Ltac sep_canceller isConst ext simplifier :=
(*TIME start_timer "sep_canceler:change_to_himp" ; *)
(try change_to_himp) ;
(*TIME stop_timer "sep_canceler:change_to_himp" ; *)
(*TIME start_timer "sep_canceler:init" ; *)
let ext' :=
match ext with
| tt => eval cbv delta [ ILAlgoTypes.BedrockPackage.bedrock_package ] in ILAlgoTypes.BedrockPackage.bedrock_package
| _ => eval cbv delta [ ext ] in ext
| _ => ext
end
in
match goal with
| [ |- himp ?cs ?L ?R ] =>
let types := reduce_repr ext tt (ILAlgoTypes.PACK.applyTypes (TacPackIL.ILAlgoTypes.Env ext) nil) in
let funcs := reduce_repr ext tt (ILAlgoTypes.PACK.applyFuncs (TacPackIL.ILAlgoTypes.Env ext) types (Env.repr (bedrock_funcs_r types) nil)) in
let preds := reduce_repr ext tt (ILAlgoTypes.PACK.applyPreds (TacPackIL.ILAlgoTypes.Env ext) types nil) in
let all_props := ReifyExpr.collect_props ltac:(ILTacCommon.reflectable shouldReflect) in
let pures := all_props in
let L := eval unfold empB, injB, injBX, starB, exB, hvarB in L in
let R := eval unfold empB, injB, injBX, starB, exB, hvarB in R in
let k :=
(fun types funcs uvars preds L R pures proofs =>
(*TIME stop_timer "sep_canceler:reify" ; *)
((** TODO: for some reason the partial application to proofs doesn't always work... **)
apply (@ApplyCancelSep types funcs preds
(ILAlgoTypes.Algos ext types)
(@ILAlgoTypes.Algos_correct ext types funcs preds) uvars pures L R);
[ solve [ apply proofs ] | compute; reflexivity | ]
(*TIME ; stop_timer "sep_canceler:apply_CancelSep" *)
)
|| (idtac "failed to apply, generalizing instead!" ;
let algos := constr:(ILAlgoTypes.Algos ext types) in
let algosC := constr:(@ILAlgoTypes.Algos_correct ext types funcs preds) in
generalize (@ApplyCancelSep types funcs preds algos algosC uvars pures L R));
(*TIME start_timer "sep_canceler:simplify" ; *)
first [ simplifier types funcs preds tt | fail 100000 "canceler: simplifier failed" ] ;
(*TIME stop_timer "sep_canceler:simplify" ; *)
(*TIME start_timer "sep_canceler:clear" ; *)
try clear types funcs preds
(*TIME ; stop_timer "sep_canceler:clear" *)
)
in
(*TIME start_timer "sep_canceler:reify"; *)
(((sep_canceler_plugin types funcs preds pures L R k))
(* || fail 10000 "sep_canceler_plugin failed" *))
| [ |- ?G ] =>
idtac "no match" G
end.
(** Symbolic Execution **)
(************************)
Ltac sym_eval isConst ext simplifier :=
(*TIME start_timer "sym_eval:init" ; *)
let rec init_from st :=
match goal with
| [ H : evalInstrs _ ?st' _ = Some st |- _ ] => init_from st'
| [ |- _ ] => st
end
in
let cs :=
match goal with
| [ H : PropX.codeSpec _ _ |- _ ] => H
end
in
let finish H :=
(*TIME start_timer "sym_eval:cleanup" ; *)
((try exact H)
||
(let rec destruct_exs H :=
match type of H with
| Logic.ex _ =>
destruct H as [ ? H ] ; destruct_exs H
| forall x : ?T, _ =>
let n := fresh in
evar (n : T);
let e := eval cbv delta [ n ] in n in
specialize (H e)
| (_ /\ (_ /\ _)) /\ (_ /\ _) =>
destruct H as [ [ ? [ ? ? ] ] [ ? ? ] ];
repeat match goal with
| [ H' : _ /\ _ |- _ ] => destruct H'
end
| False => destruct H
| ?G =>
fail 100000 "bad result goal" G
end
in let fresh Hcopy := fresh "Hcopy" in
let T := type of H in
assert (Hcopy : T) by apply H; clear H; destruct_exs Hcopy))
(*TIME ; stop_timer "sym_eval:cleanup" *)
in
let ext' :=
match ext with
| _ => eval cbv delta [ ext ] in ext
| _ => ext
end
in
let stn_st_SF :=
match goal with
| [ H : PropX.interp _ (![ ?SF ] ?X) |- _ ] =>
let SF := eval unfold empB, injB, injBX, starB, exB, hvarB in SF in
constr:((X, (SF, H)))
| [ H : Structured.evalCond _ _ _ ?stn ?st = _ |- _ ] =>
let st := init_from st in
constr:(((stn, st), tt))
| [ H : IL.evalInstrs ?stn ?st _ = _ |- _ ] =>
let st := init_from st in
constr:(((stn, st), tt))
| [ |- _ ] => tt
end
in
let types := reduce_repr ext tt (ILAlgoTypes.PACK.applyTypes (TacPackIL.ILAlgoTypes.Env ext) nil) in
let funcs := reduce_repr ext tt (ILAlgoTypes.PACK.applyFuncs (TacPackIL.ILAlgoTypes.Env ext) types (repr (bedrock_funcs_r types) nil)) in
let preds := reduce_repr ext tt (ILAlgoTypes.PACK.applyPreds (TacPackIL.ILAlgoTypes.Env ext) types nil) in
let all_props := ReifyExpr.collect_props ltac:(ILTacCommon.reflectable shouldReflect) in
let pures := all_props in
match stn_st_SF with
| tt => idtac (* nothing to symbolically evluate *)
| ((?stn, ?st), tt) =>
match find_reg st Rp with
| (?rp_v, ?rp_pf) =>
match find_reg st Sp with
| (?sp_v, ?sp_pf) =>
match find_reg st Rv with
| (?rv_v, ?rv_pf) =>
let k :=
(fun types funcs uvars preds rp sp rv is isP fin pures proofs =>
(*TIME stop_timer "sym_eval:reify" ; *)
(*TIME start_timer "sym_eval:apply" ; *)
generalize (@SymILTac.stateD_proof_no_heap types funcs preds
uvars st sp rv rp
sp_pf rv_pf rp_pf
pures proofs cs stn);
let H_stateD := fresh in
intro H_stateD ;
((apply (@SymILTac.Apply_sym_eval types funcs preds
(@ILAlgoTypes.Algos ext types) (@ILAlgoTypes.Algos_correct ext types funcs preds)
stn uvars fin st is isP) in H_stateD)
|| fail 100000 "couldn't apply sym_eval_any! (non-SF case)");
(*TIME stop_timer "sym_eval:apply" ; *)
(*TIME start_timer "sym_eval:simplify" ; *)
first [ simplifier types funcs preds H_stateD | fail 100000 "simplifier failed! (non-SF)" ] ;
try clear types funcs preds ;
(*TIME stop_timer "sym_eval:simplify" ; *)
first [ finish H_stateD (*; clear_instrs all_instrs*) | fail 100000 "finisher failed! (non-SF)" ]
)
in
(*TIME start_timer "sym_eval:reify"; *)
(sym_eval_nosep types funcs preds pures rp_v sp_v rv_v st k) || fail 10000 "sym_eval_nosep failed"
end
end
end
| ((?stn, ?st), (?SF, ?H_interp)) =>
match find_reg st Rp with
| (?rp_v, ?rp_pf) =>
match find_reg st Sp with
| (?sp_v, ?sp_pf) =>
match find_reg st Rv with
| (?rv_v, ?rv_pf) =>
let k := (fun types funcs uvars preds rp sp rv is isP fin pures proofs SF =>
(*TIME stop_timer "sym_eval:reify" ; *)
(*TIME start_timer "sym_eval:apply" ; *)
apply (@SymILTac.stateD_proof types funcs preds
uvars _ sp rv rp
sp_pf rv_pf rp_pf pures proofs SF _ _ (refl_equal _)) in H_interp ;
((apply (@SymILTac.Apply_sym_eval types funcs preds
(@ILAlgoTypes.Algos ext types) (@ILAlgoTypes.Algos_correct ext types funcs preds)
stn uvars fin st is isP) in H_interp)
) ;
(*TIME stop_timer "sym_eval:apply" ; *)
(*TIME start_timer "sym_eval:simplify" ; *)
first [ simplifier types funcs preds H_interp | fail 100000 "simplifier failed! (SF)" ] ;
try clear types funcs preds ;
(*TIME stop_timer "sym_eval:simplify" ; *)
first [ finish H_interp (* ; clear_instrs all_instrs *) | fail 100000 "finisher failed! (SF)" ])
in (*TIME start_timer "sym_eval:reify" ; *)
(sym_eval_sep types funcs preds pures rp_v sp_v rv_v st SF k) || fail 10000 "bad enough"
end
end
end
| ?X => idtac X ; fail 100000 "bad"
end.
|
#include <bits/stdc++.h> int main() { long long n, k, f[10005], t[10005], i, j, s = -1000000005, g = -1000000005, r; scanf( %lld %lld , &n, &k); for (i = 0; i < n; i++) { scanf( %lld %lld , &f[i], &t[i]); } for (j = 0; j < n; j++) { if (t[j] > k) { r = f[j] - (t[j] - k); if (r > s) s = r; } else if (t[j] <= k) { if (f[j] > g) g = f[j]; } } if (g > s) printf( %lld , g); else if (s >= g) printf( %lld , s); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Johan Bjork.
// SPDX-License-Identifier: CC0-1.0
parameter N = 4;
// verilator lint_off LITENDIAN
interface a_if #(parameter PARAM = 0) ();
logic long_name;
modport source (output long_name);
modport sink (input long_name);
endinterface
module intf_source
(
input logic [0:N-1] intf_input,
a_if.source i_intf_source[0:N-1]
);
generate
for (genvar i=0; i < N;i++) begin
assign i_intf_source[i].long_name = intf_input[i];
end
endgenerate
endmodule
module intf_sink
(
output [0:N-1] a_out,
a_if.sink i_intf_sink[0:N-1]
);
generate
for (genvar i=0; i < N;i++) begin
assign a_out[i] = i_intf_sink[i].long_name;
end
endgenerate
endmodule
module t
(
clk
);
input clk;
logic [0:N-1] a_in;
logic [0:N-1] a_out;
logic [0:N-1] ack_out;
a_if #(.PARAM(1)) tl_intf [0:N-1] ();
intf_source source(a_in, tl_intf);
intf_sink sink(a_out, tl_intf);
initial a_in = '0;
always @(posedge clk) begin
a_in <= a_in + { {N-1 {1'b0}}, 1'b1 };
ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 };
if (ack_out != a_out) begin
$stop;
end
if (& a_in) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// spram.v: Generic single port RAM //
// //
// Author: Ameer M.S. Abdelhadi (, ) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module spram
#( parameter MEMD = 512, // memory depth
parameter DATAW = 32 , // data width
parameter IZERO = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
parameter IFILE = "" ) // initialization hex file (don't pass extension), optional
( input clk , // clock
input wEnb , // write enable for port B
input [`log2(MEMD)-1:0] addr , // write/read address
input [DATAW -1:0] wData, // write data
output reg [DATAW -1:0] rData); // read data
// initialize RAM, with zeros if IZERO or file if IFLE.
integer i;
reg [DATAW-1:0] mem [0:MEMD-1]; // memory array
initial
if (IZERO)
for (i=0; i<MEMD; i=i+1) mem[i] = {DATAW{1'b0}};
else
if (IFILE != "") $readmemh({IFILE,".hex"}, mem);
always @(posedge clk) begin
// write/read; nonblocking statement to read old data
if (wEnb) begin
mem[addr] <= wData; // Change into blocking statement (=) to read new data
rData <= wData; // flow-through
end else
rData <= mem[addr]; //Change into blocking statement (=) to read new data
end
endmodule
|
// test_intermout_always_comb_1_test.v
module f1_test(a, b, c, d, z);
input a, b, c, d;
output z;
reg z, temp1, temp2;
always @(a or b or c or d)
begin
temp1 = a ^ b;
temp2 = c ^ d;
z = temp1 ^ temp2;
end
endmodule
// test_intermout_always_comb_3_test.v
module f2_test (in1, in2, out);
input in1, in2;
output reg out;
always @ ( in1 or in2)
if(in1 > in2)
out = in1;
else
out = in2;
endmodule
// test_intermout_always_comb_4_test.v
module f3_test(a, b, c);
input b, c;
output reg a;
always @(b or c) begin
a = b;
a = c;
end
endmodule
// test_intermout_always_comb_5_test.v
module f4_test(ctrl, in1, in2, out);
input ctrl;
input in1, in2;
output reg out;
always @ (ctrl or in1 or in2)
if(ctrl)
out = in1 & in2;
else
out = in1 | in2;
endmodule
// test_intermout_always_ff_3_test.v
module f5_NonBlockingEx(clk, merge, er, xmit, fddi, claim);
input clk, merge, er, xmit, fddi;
output reg claim;
reg fcr;
always @(posedge clk)
begin
fcr = er | xmit;
if(merge)
claim = fcr & fddi;
else
claim = fddi;
end
endmodule
// test_intermout_always_ff_4_test.v
module f6_FlipFlop(clk, cs, ns);
input clk;
input [31:0] cs;
output [31:0] ns;
integer is;
always @(posedge clk)
is <= cs;
assign ns = is;
endmodule
// test_intermout_always_ff_5_test.v
module f7_FlipFlop(clock, cs, ns);
input clock;
input [3:0] cs;
output reg [3:0] ns;
reg [3:0] temp;
always @(posedge clock)
begin
temp = cs;
ns = temp;
end
endmodule
// test_intermout_always_ff_6_test.v
module f8_inc(clock, counter);
input clock;
output reg [3:0] counter;
always @(posedge clock)
counter <= counter + 1;
endmodule
// test_intermout_always_ff_8_test.v
module f9_NegEdgeClock(q, d, clk, reset);
input d, clk, reset;
output reg q;
always @(negedge clk or negedge reset)
if(!reset)
q <= 1'b0;
else
q <= d;
endmodule
// test_intermout_always_ff_9_test.v
module f10_MyCounter (clock, preset, updown, presetdata, counter);
input clock, preset, updown;
input [1: 0] presetdata;
output reg [1:0] counter;
always @(posedge clock)
if(preset)
counter <= presetdata;
else
if(updown)
counter <= counter + 1;
else
counter <= counter - 1;
endmodule
// test_intermout_always_latch_1_test.v
module f11_test(en, in, out);
input en;
input [1:0] in;
output reg [2:0] out;
always @ (en or in)
if(en)
out = in + 1;
endmodule
// test_intermout_bufrm_1_test.v
module f12_test(input in, output out);
//no buffer removal
assign out = in;
endmodule
// test_intermout_bufrm_2_test.v
module f13_test(input in, output out);
//intermediate buffers should be removed
wire w1, w2;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
// test_intermout_bufrm_6_test.v
module f14_test(in, out);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign w4 = w3;
assign out = w4;
f14_mybuf _f14_mybuf(w2, w3);
endmodule
module f14_mybuf(in, out);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
// test_intermout_bufrm_7_test.v
module f15_test(in1, in2, out);
input in1, in2;
output out;
// Y with cluster of f15_mybuf instances at the junction
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
assign w1 = in1;
assign w2 = w1;
assign w5 = in2;
assign w6 = w5;
assign w10 = w9;
assign out = w10;
f15_mybuf _f15_mybuf0(w2, w3);
f15_mybuf _f15_mybuf1(w3, w4);
f15_mybuf _f15_mybuf2(w6, w7);
f15_mybuf _f15_mybuf3(w7, w4);
f15_mybuf _f15_mybuf4(w4, w8);
f15_mybuf _f15_mybuf5(w8, w9);
endmodule
module f15_mybuf(in, out);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
// test_intermout_exprs_add_test.v
module f16_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 + in2;
assign vout1 = vin1 + vin2;
endmodule
// test_intermout_exprs_binlogic_test.v
module f17_test(in1, in2, vin1, vin2, out, vout, vin3, vin4, vout1 );
input in1, in2;
input [1:0] vin1;
input [3:0] vin2;
input [1:0] vin3;
input [3:0] vin4;
output vout, vout1;
output out;
assign out = in1 && in2;
assign vout = vin1 && vin2;
assign vout1 = vin3 || vin4;
endmodule
// test_intermout_exprs_bitwiseneg_test.v
module f18_test(output out, input in, output [1:0] vout, input [1:0] vin);
assign out = ~in;
assign vout = ~vin;
endmodule
// test_intermout_exprs_buffer_test.v
module f19_buffer(in, out, vin, vout);
input in;
output out;
input [1:0] vin;
output [1:0] vout;
assign out = in;
assign vout = vin;
endmodule
// test_intermout_exprs_condexpr_mux_test.v
module f20_test(in1, in2, out, vin1, vin2, vin3, vin4, vout1, vout2, en1, ven1, ven2);
input in1, in2, en1, ven1;
input [1:0] ven2;
output out;
input [1:0] vin1, vin2, vin3, vin4;
output [1:0] vout1, vout2;
assign out = en1 ? in1 : in2;
assign vout1 = ven1 ? vin1 : vin2;
assign vout2 = ven2 ? vin3 : vin4;
endmodule
// test_intermout_exprs_condexpr_tribuf_test.v
module f21_test(in, out, en, vin1, vout1, en1);
input in, en, en1;
output out;
input [1:0] vin1;
output [1:0] vout1;
assign out = en ? in : 1'bz;
assign vout1 = en1 ? vin1 : 2'bzz;
endmodule
// test_intermout_exprs_constshift_test.v
module f22_test(in, out, vin, vout, vin1, vout1, vin2, vout2);
input in;
input [3:0] vin, vin1, vin2;
output [3:0] vout, vout1, vout2;
output out;
assign out = in << 1;
assign vout = vin << 2;
assign vout1 = vin1 >> 2;
assign vout2 = vin2 >>> 2;
endmodule
// test_intermout_exprs_const_test.v
module f23_test (out, vout);
output out;
output [7:0] vout;
assign out = 1'b1;
assign vout = 9;
endmodule
// test_intermout_exprs_div_test.v
module f24_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 / in2;
assign vout1 = vin1 / vin2;
endmodule
// test_intermout_exprs_logicneg_test.v
module f25_test(out, vout, in, vin);
output out, vout;
input in;
input [3:0] vin;
assign out = !in;
assign vout = !vin;
endmodule
// test_intermout_exprs_mod_test.v
module f26_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 % in2;
assign vout1 = vin1 % vin2;
endmodule
// test_intermout_exprs_mul_test.v
module f27_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 * in2;
assign vout1 = vin1 * vin2;
endmodule
// test_intermout_exprs_redand_test.v
module f28_test(output out, input [1:0] vin, output out1, input [3:0] vin1);
assign out = &vin;
assign out1 = &vin1;
endmodule
// test_intermout_exprs_redop_test.v
module f29_Reduction (A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6);
input [1:0] A1;
input [1:0] A2;
input [1:0] A3;
input [1:0] A4;
input [1:0] A5;
input [1:0] A6;
output Y1, Y2, Y3, Y4, Y5, Y6;
//reg Y1, Y2, Y3, Y4, Y5, Y6;
assign Y1=&A1; //reduction AND
assign Y2=|A2; //reduction OR
assign Y3=~&A3; //reduction NAND
assign Y4=~|A4; //reduction NOR
assign Y5=^A5; //reduction XOR
assign Y6=~^A6; //reduction XNOR
endmodule
// test_intermout_exprs_sub_test.v
module f30_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 - in2;
assign vout1 = vin1 - vin2;
endmodule
// test_intermout_exprs_unaryminus_test.v
module f31_test(output out, input in, output [31:0] vout, input [31:0] vin);
assign out = -in;
assign vout = -vin;
endmodule
// test_intermout_exprs_unaryplus_test.v
module f32_test(output out, input in);
assign out = +in;
endmodule
// test_intermout_exprs_varshift_test.v
module f33_test(vin0, vout0);
input [2:0] vin0;
output reg [7:0] vout0;
wire [7:0] myreg0, myreg1, myreg2;
integer i;
assign myreg0 = vout0 << vin0;
assign myreg1 = myreg2 >> i;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s1, s2; cin >> s1; cin >> s2; int arr[27] = {}; int a[27] = {}; string s = ; for (int i = 0; i < s1.length(); i++) { arr[int(s1[i]) - 97]++; } int count1 = 0; for (int i = 0; i < s2.length(); i++) { if (arr[int(s2[i]) - 97] == 0) { cout << -1; count1++; break; } else { if (a[int(s2[i]) - 97] == 0) { s += s2[i]; } a[int(s2[i]) - 97]++; } } long long int sum = 0; if (count1 == 0) { for (int i = 0; i < s.length(); i++) { if (a[int(s[i]) - 97] <= arr[int(s[i]) - 97]) { sum += a[int(s[i]) - 97]; } else { sum += arr[int(s[i]) - 97]; } } cout << sum << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, x = 0, c = 0; cin >> n; while (n != 1) { if (x == 3) { cout << -1 << endl; break; } if (n % 6 == 0) { n /= 6; c++; x = 0; } else { n *= 2; c++; x++; } } if (n == 1) { cout << c << endl; } } return 0; }
|
#include <bits/stdc++.h> int main() { int ele, n, x[110], y[110], p, q, e = 0, f = 0, i, e1 = 0, e2 = 0, o1 = 0, o2 = 0; char s1[300], s2[300]; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d%d , &x[i], &y[i]); for (i = 1; i <= n; i++) { if (x[i] % 2 == 0) e1++; if (x[i] % 2 != 0) { o1++; p = i; s2[f++] = (char)(i + 0); } if (y[i] % 2 == 0) e2++; if (y[i] % 2 != 0) { o2++; q = i; s1[e++] = (char)(i + 0); } } s2[f] = 0 ; s1[e] = 0 ; ele = strcmp(s1, s2); if (o1 % 2 == 0 && o2 % 2 == 0) { printf( 0 ); goto label; } if (o1 % 2 != 0 && o2 % 2 == 0) { printf( -1 ); goto label; } if (o1 % 2 == 0 && o2 % 2 != 0) { printf( -1 ); goto label; } if (o1 % 2 != 0 && o2 % 2 != 0) { if (o1 > 1 || o2 > 1) { if (ele == 0) printf( -1 ); else printf( 1 ); } else if (p == q) printf( -1 ); else printf( 1 ); } else printf( 0 ); label: return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long int a[n], p[n], s[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } int blocks = 0; p[0] = a[0]; for (int i = 1; i < n; i++) { p[i] = max(p[i - 1], a[i]); } s[n - 1] = a[n - 1]; for (int i = n - 2; i >= 0; i--) { s[i] = min(s[i + 1], a[i]); } for (int i = 0; i < n - 1; i++) { if (p[i] <= s[i + 1]) { blocks++; } } cout << blocks + 1 << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22AI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O22AI_PP_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o22ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22AI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A2BB2OI_PP_SYMBOL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a2bb2oi (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2OI_PP_SYMBOL_V
|
module sm (/*AUTOARG*/
// Outputs
state_r,
// Inputs
clk, rst_
);
//==================== Constant declarations ==============
parameter [2:0] // synopsys enum state_info
IDLE = 3'b000,
SEND = 3'b001,
WAIT1 = 3'b010,
UPDATE1 = 3'b011,
WAIT2 = 3'b100;
parameter [2:0] /* synopsys enum state_info */ UPDATE2 = 3'b101;
parameter [2:0] NOT_A_STATE_ELEMENT = 3'b101;
parameter [2:0] /* synopsys enum other */
A_OTHER_STATE_ELEMENT = 3'b101;
//==================== Input Signals ======================
input clk; // System clock signal
input rst_;
//==================== Output Signals =====================
// s_ynopsys requires the enum comment between the keyword and the symbol While this seems silly,
// verilog requires this also to avoid misleading people that also use their tools.
output [2:0] state_r; // SM State information (to GPF)
//==================== Intermediate Variables =============
reg [2:0] /* synopsys enum state_info */ state_r; /* synopsys state_vector state_r */
reg [2:0] /* synopsys enum state_info */ state_e1; // next state of state-machine
//==================== Code Begin =========================
always @(/*AUTOSENSE*/state_r) begin
case(state_r) // synopsys full_case parallel_case
IDLE: begin
state_e1 = SEND;
end
SEND: begin
state_e1 = WAIT1;
end
WAIT1: begin
state_e1 = UPDATE1;
end
UPDATE1: begin
state_e1 = UPDATE2;
end
WAIT2: begin
state_e1 = UPDATE2;
end
UPDATE2: begin
state_e1 = IDLE;
end
default: state_e1 = state_r;
endcase
end
always @(posedge clk or negedge rst_) begin
if (~rst_) begin
state_r <= #0 IDLE;
end
else begin
state_r <= #0 state_e1;
end
end
//==================== DEBUG ASCII CODE =========================
/*AUTOASCIIENUM("state_r", "_stateascii_r")*/
// Beginning of automatic ASCII enum decoding
reg [55:0] _stateascii_r; // Decode of state_r
always @(state_r) begin
case ({state_r})
IDLE: _stateascii_r = "idle ";
SEND: _stateascii_r = "send ";
WAIT1: _stateascii_r = "wait1 ";
UPDATE1: _stateascii_r = "update1";
WAIT2: _stateascii_r = "wait2 ";
UPDATE2: _stateascii_r = "update2";
default: _stateascii_r = "%Error ";
endcase
end
// End of automatics
endmodule
|
#include <bits/stdc++.h> using namespace std; long long N, K; long long num[3000]; long long OAO[3000]; bool test(long long c) { for (long long Ni = 0; Ni <= N; Ni++) { OAO[Ni] = Ni; for (long long Nj = 0; Nj < Ni; Nj++) { if (Ni != N && abs(num[Ni] - num[Nj]) > (long long)(c) * (Ni - Nj)) continue; OAO[Ni] = min(OAO[Ni], OAO[Nj] + Ni - Nj - 1); } } if (OAO[N] > K) return false; else return true; } int main() { scanf( %I64d %I64d , &N, &K); long long p = 0; for (long long Ni = 0; Ni < N; Ni++) { scanf( %I64d , &num[Ni]); if (Ni) p = max(p, (long long)abs(num[Ni] - num[Ni - 1])); } long long l = -1, r = p, mid; while (l + 1 != r) { mid = (l + r) / 2; if (test(mid)) r = mid; else l = mid; } printf( %I64d n , r); }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`ifdef BASIL_SBUS
`define SPLIT_BUS
`elsif BASIL_TOPSBUS
`define SPLIT_BUS
`endif
`ifndef BASIL_SBUS
`include "utils/bus_to_ip.v"
`include "gpio/gpio_core.v"
`include "gpio/gpio.v"
`include "spi/spi.v"
`include "spi/spi_core.v"
`include "spi/blk_mem_gen_8_to_1_2k.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "bram_fifo/bram_fifo_core.v"
`include "bram_fifo/bram_fifo.v"
`include "fast_spi_rx/fast_spi_rx.v"
`include "fast_spi_rx/fast_spi_rx_core.v"
`include "utils/cdc_syncfifo.v"
`include "utils/generic_fifo.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/CG_MOD_pos.v"
`include "utils/clock_divider.v"
`include "utils/3_stage_synchronizer.v"
`include "utils/RAMB16_S1_S9_sim.v"
`else
$fatal("Sbus modules not implemented yet");
`endif
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
`ifndef SPLIT_BUS
inout wire [31:0] BUS_DATA,
`else
input wire [31:0] BUS_DATA_IN,
output wire [31:0] BUS_DATA_OUT,
`endif
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
// MODULE ADREESSES //
localparam GPIO_BASEADDR = 32'h0000;
localparam GPIO_HIGHADDR = 32'h1000-1;
localparam SPI_BASEADDR = 32'h1000; //0x1000
localparam SPI_HIGHADDR = 32'h2000-1; //0x300f
localparam FAST_SR_AQ_BASEADDR = 32'h2000;
localparam FAST_SR_AQ_HIGHADDR = 32'h3000-1;
localparam PULSE_BASEADDR = 32'h3000;
localparam PULSE_HIGHADDR = PULSE_BASEADDR + 15;
localparam FIFO_BASEADDR = 32'h8000;
localparam FIFO_HIGHADDR = 32'h9000-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
// BUS/SBUS //
// Connect tb internal bus to external split bus
`ifdef BASIL_TOPSBUS
wire [31:0] BUS_DATA;
assign BUS_DATA = BUS_DATA_IN;
assign BUS_DATA_OUT = BUS_DATA;
`elsif BASIL_SBUS
wire [31:0] BUS_DATA_OUT_1;
wire [31:0] BUS_DATA_OUT_2;
wire [31:0] BUS_DATA_OUT_3;
wire [31:0] BUS_DATA_OUT_4;
wire [31:0] BUS_DATA_OUT_5;
assign BUS_DATA_OUT = BUS_DATA_OUT_1 | BUS_DATA_OUT_2 | BUS_DATA_OUT_3 | BUS_DATA_OUT_4 | BUS_DATA_OUT_5;
`endif
// MODULES //
`ifndef BASIL_SBUS
gpio #(
`else
gpio_sbus #(
`endif
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
`ifndef BASIL_SBUS
.BUS_DATA(BUS_DATA[7:0]),
`else
.BUS_DATA_IN(BUS_DATA_IN[7:0]),
.BUS_DATA_OUT(BUS_DATA_OUT_1[7:0]),
`endif
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO()
);
wire SPI_CLK;
wire EX_START_PULSE;
`ifndef BASIL_SBUS
pulse_gen #(
`else
pulse_gen_sbus #(
`endif
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pulse_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
`ifndef BASIL_SBUS
.BUS_DATA(BUS_DATA[7:0]),
`else
.BUS_DATA_IN(BUS_DATA_IN[7:0]),
.BUS_DATA_OUT(BUS_DATA_OUT_2[7:0]),
`endif
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(SPI_CLK),
.EXT_START(1'b0),
.PULSE(EX_START_PULSE)
);
clock_divider #(
.DIVISOR(4)
) i_clock_divisor_spi (
.CLK(BUS_CLK),
.RESET(1'b0),
.CE(),
.CLOCK(SPI_CLK)
);
wire SCLK, SDI, SDO, SEN, SLD;
`ifndef BASIL_SBUS
spi #(
`else
spi_sbus #(
`endif
.BASEADDR(SPI_BASEADDR),
.HIGHADDR(SPI_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(16)
) i_spi (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
`ifndef BASIL_SBUS
.BUS_DATA(BUS_DATA[7:0]),
`else
.BUS_DATA_IN(BUS_DATA_IN[7:0]),
.BUS_DATA_OUT(BUS_DATA_OUT_3[7:0]),
`endif
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SPI_CLK(SPI_CLK),
.EXT_START(EX_START_PULSE),
.SCLK(SCLK),
.SDI(SDI),
.SDO(SDO),
.SEN(SEN),
.SLD(SLD)
);
assign SDO = SDI;
wire FIFO_READ_SPI_RX;
wire FIFO_EMPTY_SPI_RX;
wire [31:0] FIFO_DATA_SPI_RX;
`ifndef BASIL_SBUS
fast_spi_rx #(
`else
fast_spi_rx_sbus #(
`endif
.BASEADDR(FAST_SR_AQ_BASEADDR),
.HIGHADDR(FAST_SR_AQ_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pixel_sr_fast_rx (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
`ifndef BASIL_SBUS
.BUS_DATA(BUS_DATA[7:0]),
`else
.BUS_DATA_IN(BUS_DATA_IN[7:0]),
.BUS_DATA_OUT(BUS_DATA_OUT_4[7:0]),
`endif
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SCLK(~SPI_CLK),
.SDI(SDI),
.SEN(SEN),
.FIFO_READ(FIFO_READ_SPI_RX),
.FIFO_EMPTY(FIFO_EMPTY_SPI_RX),
.FIFO_DATA(FIFO_DATA_SPI_RX)
);
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
assign FIFO_DATA = FIFO_DATA_SPI_RX;
assign FIFO_EMPTY = FIFO_EMPTY_SPI_RX;
assign FIFO_READ_SPI_RX = FIFO_READ;
`ifndef BASIL_SBUS
bram_fifo #(
`else
bram_fifo_sbus #(
`endif
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
`ifndef BASIL_SBUS
.BUS_DATA(BUS_DATA),
`else
.BUS_DATA_IN(BUS_DATA_IN),
.BUS_DATA_OUT(BUS_DATA_OUT_5),
`endif
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
`ifndef VERILATOR_SIM
initial begin
$dumpfile("spi.vcd");
$dumpvars(0);
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; void solve() { int n; cin >> n; vector<pair<int, int>> data(n); for (auto &x : data) cin >> x.first >> x.second; sort(data.begin(), data.end()); vector<vector<long long>> dp(2, vector<long long>(n, 0)); dp[0][0] = LLONG_MAX; dp[1][0] = data[0].second; for (int curr = 1; curr < n; curr++) { dp[1][curr] = data[curr].second + min(dp[0][curr - 1], dp[1][curr - 1]); dp[0][curr] = LLONG_MAX; long long sum = 0; int cnt = 1; for (int prev = curr - 1; prev >= 0; prev--) { sum += 1ll * (data[prev + 1].first - data[prev].first) * cnt; if (sum + dp[1][prev] < dp[0][curr]) dp[0][curr] = sum + dp[1][prev]; ; cnt++; } } cout << min(dp[0][n - 1], dp[1][n - 1]); } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); solve(); return 0; }
|
#include <bits/stdc++.h> const long long int mod = 1000000007; using namespace std; void toh_chaliye_shuru_karte_hain() {} void code_samapti_ki_ghoshna() {} long long int power(long long int a, long long int b, long long int modi) { a %= modi; long long int res = 1; while (b) { if (b % 2) { res = (res * a) % modi; } b /= 2; a = (a * a) % modi; } return res; } int main() { toh_chaliye_shuru_karte_hain(); ios::sync_with_stdio(0); cin.tie(0); int n, x1, y1, x2, y2; cin >> n >> x1 >> y1 >> x2 >> y2; if (x1 == 0 && x2 == 0 || x1 == n && x2 == n) { cout << abs(y1 - y2) << n ; } else if (y1 == 0 && y2 == 0 || y1 == n && y2 == n) { cout << abs(x1 - x2) << n ; } else { int ans = 0; ans += min(n - y1 + n - y2, y1 + y2); ans += min(n - x1 + n - x2, x1 + x2); cout << ans << n ; } code_samapti_ki_ghoshna(); return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: readmemh function - Read less data than length of array
//
//
module main ();
reg [7:0] array [0:7];
reg error ;
reg [3:0] count;
initial
begin
error = 0;
/* pre init the array to all zeroes. */
for(count = 0; count <= 7; count = count + 1)
array[count] = 8'h0;
$readmemh("ivltests/readmemh1.dat",array,0,3);
for(count = 0; count <= 3; count = count + 1)
begin
if(array[count[2:0]] !== count)
begin
error = 1;
$display("FAILED - array[count] == %h, s/b %h",
array[count],count);
end
end
if(array[4] !== 8'h0)
begin
error = 1;
$display("FAILED - array[4] == %h, s/b 0",
array[count]);
end
if(error == 0)
$display("PASSED\n");
$finish ;
end
endmodule
|
#include <bits/stdc++.h> int a[2005][2005], b[100005], c[8][10]; int max(int a, int b) { return a > b ? a : b; } int min(int a, int b) { return a < b ? a : b; } int main() { int n, m, k, s; while (scanf( %d%d%d%d , &n, &m, &k, &s) != EOF) { for (int i = 1; i <= 9; i++) { c[0][i] = -1 << 15; c[1][i] = 1 << 15; c[2][i] = -1 << 15; c[3][i] = 1 << 15; c[4][i] = -1 << 15; c[5][i] = 1 << 15; c[6][i] = -1 << 15; c[7][i] = 1 << 15; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &a[i][j]); c[0][a[i][j]] = max(c[0][a[i][j]], i + j); c[1][a[i][j]] = min(c[1][a[i][j]], i + j); c[2][a[i][j]] = max(c[2][a[i][j]], i - j); c[3][a[i][j]] = min(c[3][a[i][j]], i - j); } } for (int i = 0; i < s; i++) { scanf( %d , &b[i]); } int Max = n + m - 2; int ans = 0; for (int i = 0; i < s - 1; i++) { ans = max(ans, c[0][b[i]] - c[1][b[i + 1]]); ans = max(ans, -c[1][b[i]] + c[0][b[i + 1]]); ans = max(ans, c[2][b[i]] - c[3][b[i + 1]]); ans = max(ans, -c[3][b[i]] + c[2][b[i + 1]]); if (ans >= Max) { break; } } printf( %d n , ans); } }
|
#include <bits/stdc++.h> using namespace std; int x[1000001][2]; int main() { int i, j, k, l, test, m, n; int a[4100]; scanf( %d , &n); int c[4100]; for (i = 0; i < n; i++) { scanf( %d , &a[i]); c[i] = a[i]; } sort(c, c + n); int b[4100]; int d[4100]; b[0] = c[0]; d[0] = 1; int in = 0; for (i = 1; i < n; i++) if (c[i] != b[in]) { d[++in] = 1; b[in] = c[i]; } else { d[in]++; } int g = 0; for (i = 0; i <= in; i++) g = max(g, d[i]); int f = 0; for (i = 0; i <= in; i++) { for (j = 0; j <= in; j++) x[b[j]][0] = x[b[j]][1] = 0; int val = b[i]; for (j = 0; j < n; j++) { if (a[j] == val) x[val][1]++; else { k = a[j]; if (x[k][1] == x[val][1]) ; else { x[k][1] = x[val][1]; x[k][0] += 2; } } } for (j = 0; j <= in; j++) { if (x[b[j]][1] != x[val][1]) x[b[j]][0]++; } for (j = 0; j <= in; j++) f = max(f, x[b[j]][0]); } cout << max(f, g) << endl; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
//
module some_module (
input wrclk
);
logic [ 1 : 0 ] some_state;
logic [1:0] some_other_state;
always @(posedge wrclk) begin
case (some_state)
2'b11:
if (some_other_state == 0)
some_state <= 2'b00;
default:
$display ("This is a display statement");
endcase
if (wrclk)
some_other_state <= 0;
end
endmodule
`define BROKEN
module t1(
input [3:0] i_clks,
input i_clk0,
input i_clk1
);
some_module
some_module
(
`ifdef BROKEN
.wrclk (i_clks[3])
`else
.wrclk (i_clk1)
`endif
);
endmodule
module t2(
input [2:0] i_clks,
input i_clk0,
input i_clk1,
input i_clk2,
input i_data
);
logic [3:0] the_clks;
logic data_q;
assign the_clks[3] = i_clk1;
assign the_clks[2] = i_clk2;
assign the_clks[1] = i_clk1;
assign the_clks[0] = i_clk0;
always @(posedge i_clk0) begin
data_q <= i_data;
end
t1 t1
(
.i_clks (the_clks),
.i_clk0 (i_clk0),
.i_clk1 (i_clk1)
);
endmodule
module t(
/*AUTOARG*/
// Inputs
clk /*verilator clocker*/,
input clk0 /*verilator clocker*/,
input clk1 /*verilator clocker*/,
input clk2 /*verilator clocker*/,
input data_in
);
input clk;
logic [2:0] clks;
assign clks = {1'b0, clk1, clk0};
t2
t2
(
.i_clks (clks),
.i_clk0 (clk0),
.i_clk1 (clk),
.i_clk2 (clk2),
.i_data (data_in)
);
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int minx, maxx, miny, maxy, sumofarea = 0; int n; cin >> n; for (int i = 0; i < n; i++) { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; if (i == 0) { minx = x1; maxx = x2; miny = y1; maxy = y2; } else { minx = min(minx, x1); maxx = max(maxx, x2); miny = min(miny, y1); maxy = max(maxy, y2); } sumofarea += ((x2 - x1) * (y2 - y1)); } int final_square_area = (maxx - minx) * (maxy - miny); int lengthofside1 = maxx - minx; int lengthofside2 = maxy - miny; if (sumofarea == final_square_area && (lengthofside1 == lengthofside2)) { cout << YES ; } else { cout << NO ; } return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of tsd_top
//
// Generated
// by: wig
// on: Mon Jun 26 16:38:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: tsd_top.v,v 1.3 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: tsd_top.v,v $
// Revision 1.3 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of tsd_top
//
// No user `defines in this module
module tsd_top
//
// Generated Module tsd_top_i1
//
(
nreset // Async. Reset (CGU,PAD)
);
// Generated Module Inputs:
input nreset;
// Generated Wires:
wire nreset;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of tsd_top
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVPWRVGND_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__TAPVPWRVGND_FUNCTIONAL_PP_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVPWRVGND_FUNCTIONAL_PP_V
|
//#define _USE_MATH_DEFINES #include<bits/stdc++.h> //#pragma GCC optimize ( O3 ) //#pragma GCC target ( sse4 ) using namespace std; #define ll long long #define endl n #define f first #define s second #define ar array #define pb push_back #define eb emplace_back #define mp make_pair #define sz(X) ((int)(X).size()) #define rsz resize #define pcnt __builtin_popcount #define sort_unique(c) (sort(c.begin(),c.end()), c.resize(distance(c.begin(),unique(c.begin(),c.end())))) #define get_pos(c, x) (lower_bound(c.begin(),c.end(),x)-c.begin()) #define all(X) (X).begin(), (X).end() #define rall(X) (X).rbegin(), (X).rend() #define ms(c, x) memset(c,x,sizeof c) #define No(x) cout<<(x? NO : No )<<endl #define Yes(x) cout<<(x? YES : Yes )<<endl #define nl cout<<endl; #define forn(i, n) for(int i = 0; i < int(n); i++) #define fore(i, l, r) for(int i = l; i <r; i++) #define fored(i, l, r) for(int i = r-1; i >=l; i--) #define ford(i, n) for (int i = n - 1; i >= 0; --i) using ld = long double; using ul = unsigned long long; using db = double; using pi = pair<int, int>; using pl = pair<ll, ll>; using pd = pair<db, db>; using vvi = vector<vector<int>>; using vvl = vector<vector<ll>>; using vi = vector<int>; using vb = vector<bool>; using vl = vector<ll>; using vd = vector<ld>; using vs = vector<string>; using vpi = vector<pi>; using vpl = vector<pl>; using vpd = vector<pd>; template<typename T, size_t size> using va = vector<ar<T, size>>; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); template<typename A, typename B> istream &operator>>(istream &in, pair<A, B> &p) { return in >> p.first >> p.second; } template<typename T> istream &operator>>(istream &in, vector<T> &vec) { for (auto &x : vec) { in >> x; } return in; } template<typename T> ostream &operator<<(ostream &os, const vector<T> &v) { for (const auto &x : v) os << x << ; return os; } template<typename T, size_t size> ostream &operator<<(ostream &os, const array<T, size> &arr) { for (const auto &x : arr) os << x << ; return os; } template<typename A, typename B> ostream &operator<<(ostream &os, const pair<A, B> &p) { return os << p.first << << p.second; } template<class T> bool ckmin(T &a, const T &b) { return b < a ? a = b, 1 : 0; } template<class T> bool ckmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } void debug() { cerr << endl; } template<typename Head, typename... Tail> void debug(Head H, Tail... T) { cerr << << H; debug(T...); } #ifdef LOCAL #define dbg(...) cerr <<__LINE__<< [[DEBUG]] << ( << #__VA_ARGS__ << ): , debug(__VA_ARGS__) #else #define dbg(...) #endif const ll mod = 1e9 + 7; //const int mod = 998244353; const ll INF = 2e18 + 6; inline ll modPow(ll x, ll y, ll mod) { ll res = 1; x = x % mod;; while (y > 0) { if (y & 1) { res = (res * x) % mod; } y = y >> 1; x = (x * x) % mod; } return res; } int dx[4] = {0, 1, 0, -1}; int dy[4] = {1, 0, -1, 0}; char dirs[4] = { R , D , L , U }; unordered_map<char, int> rdirs = {{ R , 0}, { D , 1}, { L , 2}, { U , 3}}; void solve() { ll a, b, n; cin >> a >> b >> n; vpi in(n); forn(i,n)cin>>in[i].f; forn(i,n)cin>>in[i].s; sort(all(in)); forn(i, n) { ll times = (in[i].s+a-1) / a; b -= (times-1) * in[i].f; if(b <=0) { No(1); return; } b-=in[i].f; if(b<0&&i!=n-1){ No(1); return; } } Yes(1); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed << setprecision(6); #ifdef LOCAL freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif int t = 1, tc = 1; cin >> t; while (t--) { // cout<< Case # <<tc<< : ; solve(); tc++; } #ifdef LOCAL cerr << endl << Time elapsed : << clock() * 1000.0 / CLOCKS_PER_SEC << ms << n ; #endif return 0; } //NOTES //look if it requires ll // read the statement carefully // check array bounds and cases for n=1
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/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_spigpioport_1(
input clock,
input reset,
input io_spi_sck,
output io_spi_dq_0_i,
input io_spi_dq_0_o,
input io_spi_dq_0_oe,
output io_spi_dq_1_i,
input io_spi_dq_1_o,
input io_spi_dq_1_oe,
output io_spi_dq_2_i,
input io_spi_dq_2_o,
input io_spi_dq_2_oe,
output io_spi_dq_3_i,
input io_spi_dq_3_o,
input io_spi_dq_3_oe,
input io_spi_cs_0,
input io_pins_sck_i_ival,
output io_pins_sck_o_oval,
output io_pins_sck_o_oe,
output io_pins_sck_o_ie,
output io_pins_sck_o_pue,
output io_pins_sck_o_ds,
input io_pins_dq_0_i_ival,
output io_pins_dq_0_o_oval,
output io_pins_dq_0_o_oe,
output io_pins_dq_0_o_ie,
output io_pins_dq_0_o_pue,
output io_pins_dq_0_o_ds,
input io_pins_dq_1_i_ival,
output io_pins_dq_1_o_oval,
output io_pins_dq_1_o_oe,
output io_pins_dq_1_o_ie,
output io_pins_dq_1_o_pue,
output io_pins_dq_1_o_ds,
input io_pins_dq_2_i_ival,
output io_pins_dq_2_o_oval,
output io_pins_dq_2_o_oe,
output io_pins_dq_2_o_ie,
output io_pins_dq_2_o_pue,
output io_pins_dq_2_o_ds,
input io_pins_dq_3_i_ival,
output io_pins_dq_3_o_oval,
output io_pins_dq_3_o_oe,
output io_pins_dq_3_o_ie,
output io_pins_dq_3_o_pue,
output io_pins_dq_3_o_ds,
input io_pins_cs_0_i_ival,
output io_pins_cs_0_o_oval,
output io_pins_cs_0_o_oe,
output io_pins_cs_0_o_ie,
output io_pins_cs_0_o_pue,
output io_pins_cs_0_o_ds
);
wire T_267;
wire T_270;
wire T_273;
wire T_276;
assign io_spi_dq_0_i = io_pins_dq_0_i_ival;
assign io_spi_dq_1_i = io_pins_dq_1_i_ival;
assign io_spi_dq_2_i = io_pins_dq_2_i_ival;
assign io_spi_dq_3_i = io_pins_dq_3_i_ival;
assign io_pins_sck_o_oval = io_spi_sck;
assign io_pins_sck_o_oe = 1'h1;
assign io_pins_sck_o_ie = 1'h0;
assign io_pins_sck_o_pue = 1'h0;
assign io_pins_sck_o_ds = 1'h0;
assign io_pins_dq_0_o_oval = io_spi_dq_0_o;
assign io_pins_dq_0_o_oe = io_spi_dq_0_oe;
assign io_pins_dq_0_o_ie = T_267;
assign io_pins_dq_0_o_pue = 1'h1;
assign io_pins_dq_0_o_ds = 1'h0;
assign io_pins_dq_1_o_oval = io_spi_dq_1_o;
assign io_pins_dq_1_o_oe = io_spi_dq_1_oe;
assign io_pins_dq_1_o_ie = T_270;
assign io_pins_dq_1_o_pue = 1'h1;
assign io_pins_dq_1_o_ds = 1'h0;
assign io_pins_dq_2_o_oval = io_spi_dq_2_o;
assign io_pins_dq_2_o_oe = io_spi_dq_2_oe;
assign io_pins_dq_2_o_ie = T_273;
assign io_pins_dq_2_o_pue = 1'h1;
assign io_pins_dq_2_o_ds = 1'h0;
assign io_pins_dq_3_o_oval = io_spi_dq_3_o;
assign io_pins_dq_3_o_oe = io_spi_dq_3_oe;
assign io_pins_dq_3_o_ie = T_276;
assign io_pins_dq_3_o_pue = 1'h1;
assign io_pins_dq_3_o_ds = 1'h0;
assign io_pins_cs_0_o_oval = io_spi_cs_0;
assign io_pins_cs_0_o_oe = 1'h1;
assign io_pins_cs_0_o_ie = 1'h0;
assign io_pins_cs_0_o_pue = 1'h0;
assign io_pins_cs_0_o_ds = 1'h0;
assign T_267 = ~ io_spi_dq_0_oe;
assign T_270 = ~ io_spi_dq_1_oe;
assign T_273 = ~ io_spi_dq_2_oe;
assign T_276 = ~ io_spi_dq_3_oe;
endmodule
|
/*
* In The Name Of God
* ========================================
* [] File Name : cache.v
*
* [] Creation Date : 04-03-2015
*
* [] Last Modified : Wed 01 Apr 2015 09:12:09 AM IRDT
*
* [] Created By : Parham Alvani ()
* =======================================
*/
module cache (enable, index, word, comp,
write, tag_in, data_in, valid_in,
rst, hit, dirty, tag_out,
data_out, valid, ack);
parameter N = 15;
reg [0:3] counter;
input enable;
input [0:3] index;
input [0:1] word;
input comp;
input write;
input [0:4] tag_in;
input [0:15] data_in;
input valid_in;
input rst;
output reg hit;
output reg dirty;
output reg [0:4] tag_out;
output reg [0:15] data_out;
output reg valid;
output reg ack;
reg set_en [0:N];
reg [0:1] set_word [0:N];
reg set_cmp [0:N];
reg set_wr [0:N];
reg [0:4] set_tag_in [0:N];
reg [0:15] set_in [0:N];
reg set_valid_in [0:N];
reg set_rst [0:N];
wire set_hit [0:N];
wire set_dirty_out [0:N];
wire [0:4] set_tag_out [0:N];
wire [0:15] set_out [0:N];
wire set_valid_out [0:N];
wire set_ack [0:N];
generate
genvar i;
for (i = 0; i < N; i = i + 1) begin
set set_ins(set_en[i], set_word[i], set_cmp[i], set_wr[i], set_rst[i],
set_tag_in[i], set_in[i], set_valid_in[i], set_hit[i], set_dirty_out[i],
set_tag_out[i], set_out[i], set_valid_out[i], set_ack[i]);
end
endgenerate
always @ (enable) begin
ack = 1'b0;
if (enable) begin
if (rst) begin
for (counter = 0; counter < N; counter = counter + 1) begin
set_en[counter] = 1'b1;
set_rst[counter] = 1'b1;
wait (set_ack[counter]) begin
set_en[counter] = 1'b0;
set_rst[counter] = 1'b0;
end
end
ack = 1'b1;
end else begin
set_word[index] = word;
set_cmp[index] = comp;
set_wr[index] = write;
set_tag_in[index] = tag_in;
set_in[index] = data_in;
set_valid_in[index] = valid_in;
set_en[index] = 1'b1;
wait (set_ack[index]) begin
hit = set_hit[index];
dirty = set_dirty_out[index];
tag_out = set_tag_out[index];
valid = set_valid_out[index];
data_out = set_out[index];
end
ack = 1'b1;
end
end else begin
set_en[index] = 1'b0;
end
end
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_randgen.v
// Version : v1.0
// Description: Random number generator:Used during random address
// generation.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
/*
*
* Ygal Arbel's Random Number Generator
*
*
*
* Random Address gen - random lfsr. Ygal 10/26/2010
Use a 20-bit LFSR to generate random addr.
Per xapp052: for 20 bits, shift in the xnor from bits 20,17
*
*
* grahams modified to be 24b
*
*/
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_randgen(
input [15:0] seed ,
output [15:0] randnum ,
input generate_next ,
input reset ,
input clk
);
reg [15:0] lfsr;
wire lfsr_xnor;
always @(posedge clk) begin
if (reset) begin
lfsr <= seed;
end else if(generate_next) begin
lfsr <= {lfsr_xnor,lfsr[15:1]};
end
end
assign randnum = lfsr;
assign lfsr_xnor = (lfsr[12] ^ lfsr[3] ^ lfsr[1]^ lfsr[0]) ? 1'd0 : 1'd1;
endmodule // axi_traffic_gen_v2_0_7_randgen
|
#include <bits/stdc++.h> using namespace std; pair<int, int> arr[200000]; int ans[200000], tree[500000], lazy[500000]; set<int> s; int n; set<int>::iterator it; int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) { cin >> arr[i].first; arr[i].second = i; } sort(arr, arr + n); int l, r, mn = arr[0].second, len; for (int i = 0; i < n; i++) { ans[i] = arr[0].first; } s.insert(arr[0].second); for (int i = 1; i < n; i++) { it = s.lower_bound(arr[i].second); r = *it; if (it == s.end()) { r = n; } if (*it == mn) { l = -1; } else { it--; l = *it; } mn = min(mn, arr[i].second); s.insert(arr[i].second); len = r - l - 1; ans[len - 1] = max(arr[i].first, ans[len - 1]); } for (int i = n - 2; i >= 0; i--) { ans[i] = max(ans[i], ans[i + 1]); } for (int i = 0; i < n; i++) { cout << ans[i] << ; } }
|
`include "hi_simulate.v"
/*
pck0 - input main 24MHz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, x, y; cin >> n >> m; vector<pair<int, int>> v; for (int i = 0; i < m; i++) { cin >> x >> y; v.push_back({y, x}); } sort(v.begin(), v.end()); int ans = 0, counter = 0; for (int i = m - 1; i >= 0; i--) { if (counter + v[i].second <= n) { ans += v[i].first * v[i].second; counter += v[i].second; } else { ans += v[i].first * (n - counter); break; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int dr[4][2] = {{1, 1}, {-1, 1}, {-1, -1}, {1, -1}}; bool eq(double d1, double d2) { return fabs(d1 - d2) < 1e-7; } int getState(double dx, double dy) { for (int i = 0; i < 4; i++) if (!eq(dx, 0) && !eq(dy, 0)) if (dx * dr[i][0] > 0 && dy * dr[i][1] > 0) return i; if (eq(dx, 0)) { if (dy > 0) return 1; else return 3; } if (eq(dy, 0)) { if (dx > 0) return 0; else return 2; } return 10000; } namespace std { bool operator<(const complex<double>& a, const complex<double>& b) { return real(a) != real(b) ? real(a) < real(b) : imag(a) < imag(b); } } // namespace std double cross(const complex<double>& a, const complex<double>& b) { return imag(conj(a) * b); } double dot(const complex<double>& a, const complex<double>& b) { return real(conj(a) * b); } int ccw(complex<double> a, complex<double> b, complex<double> c) { b -= a; c -= a; if (cross(b, c) > 0) return +1; if (cross(b, c) < 0) return -1; if (dot(b, c) < 0) return +2; if (norm(b) < norm(c)) return -2; return 0; } bool isconvex(const vector<complex<double> >& P) { for (int i = 0; i < P.size(); ++i) { if (ccw(P[(i + P.size() - 1) % P.size()], P[(i) % P.size()], P[(i + 1) % P.size()]) > 0) return false; } return true; } vector<complex<double> > convex_hull(vector<complex<double> >& ps) { int n = ps.size(), k = 0; sort(ps.begin(), ps.end()); vector<complex<double> > ch(2 * n); for (int i = 0; i < n; ch[k++] = ps[i++]) while (k >= 2 && ccw(ch[k - 2], ch[k - 1], ps[i]) <= 0) --k; for (int i = n - 2, t = k + 1; i >= 0; ch[k++] = ps[i--]) while (k >= t && ccw(ch[k - 2], ch[k - 1], ps[i]) <= 0) --k; ch.resize(k - 1); return ch; } vector<complex<double> > poly, temp; vector<complex<double> > cn; int n, ptr = 0; bool eqq(complex<double> p1, complex<double> p2) { return eq(p1.imag(), p2.imag()) && eq(p1.real(), p2.real()); } int main() { cin >> n; poly.resize(n); for (int i = 0; i < n; i++) { int x, y; scanf( %d%d , &x, &y); poly[i] = complex<double>(x, y); } sort(poly.begin(), poly.end()); for (int i = 0; i < poly.size(); i++) if (i == 0 || poly[i] != poly[i - 1]) temp.push_back(poly[i]); poly = temp; n = poly.size(); if (n == 1) cout << 4 << endl; else { cn = convex_hull(poly); n = cn.size(); int res = 0, curS = getState(cn[1].real() - cn[0].real(), cn[1].imag() - cn[0].imag()); int fs = curS; for (int i = 0; i < cn.size(); i++) { int j = (i + 1) % cn.size(); int dx = (int)(cn[j].real() - cn[i].real()); int dy = (int)(cn[j].imag() - cn[i].imag()); int state = getState(dx, dy); res += max(abs(dx), abs(dy)); while (curS != state) res++, curS = (curS + 1) % 4; } while (curS != fs) res++, curS = (curS + 1) % 4; cout << res << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long read() { char ch = getchar(); long long nega = 1; while (!isdigit(ch)) { if (ch == - ) nega = -1; ch = getchar(); } long long ans = 0; while (isdigit(ch)) { ans = ans * 10 + ch - 48; ch = getchar(); } if (nega == -1) return -ans; return ans; } long long a[40005], b[40005]; long long u[40005], v[40005], n, m; signed main() { cin >> n >> m; for (long long i = 1; i <= n; i++) a[i] = read(); for (long long j = 1; j <= m; j++) b[j] = read(); vector<long long> s; for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { s.push_back(a[i] + b[j]); u[a[i] + b[j] + 20000] |= (1LL << (i - 1)); v[a[i] + b[j] + 20000] |= (1LL << (j - 1)); } } sort(s.begin(), s.end()); s.erase(unique(s.begin(), s.end()), s.end()); long long ans = 0; for (long long i : s) { for (long long j : s) { long long r = u[i + 20000] | u[j + 20000], s = v[i + 20000] | v[j + 20000]; ans = max(ans, 0LL + __builtin_popcountll(r) + __builtin_popcountll(s)); } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e3 + 5; const int mod = 998244353; inline void add_mod(int &a, int b) { a += b; if (a >= mod) a -= mod; } inline void chk_mod(int &a) { if (a < 0) a += mod; } inline long long pw(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = res * a % mod; a = a * a % mod; b >>= 1; } return res; } long long pw2[MAXN], icoef[MAXN]; int n, c; int a[MAXN]; namespace Subtask1 { int sum[MAXN][MAXN], f[MAXN][MAXN], g[MAXN][MAXN]; void solve(void) { for (int i = 1; i <= n; ++i) { for (int j = 1; j <= c; ++j) sum[i][j] = sum[i - 1][j]; ++sum[i][a[i]]; } for (int i = 1; i <= n; ++i) { if (c == 1) { f[i][i] = 1; continue; } static int t[MAXN]; for (int j = 1; j <= c; ++j) t[j] = 0; int cnt = 0, cur = 1; for (int j = i; j <= n; ++j) { int ct = ++t[a[j]]; if (ct == 1) { ++cnt; if (cnt == c) { for (int k = 1; k <= c; ++k) if (k != a[i]) cur = cur * (pw2[t[k]] - 1) % mod; chk_mod(cur); } } else if (cnt == c && a[j] != a[i]) chk_mod(cur = cur * icoef[ct - 1] % mod * (pw2[ct] - 1) % mod); if (cnt == c && a[j] != a[i]) f[i][j] = cur * icoef[ct] % mod * pw2[t[a[i]] - 1] % mod; } } g[n + 1][0] = 1; for (int i = n; i >= 1; --i) { int mxp = (n - i + 1) / c; for (int j = i; j <= n; ++j) if (f[i][j]) for (int k = 1; k <= mxp; ++k) g[i][k] = (g[i][k] + (long long)g[j + 1][k - 1] * f[i][j]) % mod; g[i][0] = pw2[n - i]; for (int j = 1; j <= n; ++j) add_mod(g[i][0], mod - g[i][j]); for (int j = 0; j <= n; ++j) add_mod(g[i][j], g[i + 1][j]); } add_mod(g[1][0], mod - 1); for (int i = 0; i <= n; ++i) printf( %d , g[1][i]); exit(0); } } // namespace Subtask1 namespace Subtask2 { const int ALL = (1 << 12) + 5; long long g[MAXN][ALL]; void solve(void) { int all = (1 << c) - 1; g[0][0] = 1; for (int k = n; k >= 1; --k) { int mxp = (n - k + 1) / c; int cura = (1 << (a[k] - 1)); for (int i = mxp; i >= 0; --i) for (int mask = all - 1; mask >= 0; --mask) if (g[i][mask]) { if ((mask | cura) == all) g[i + 1][0] += g[i][mask]; else g[i][mask | cura] += g[i][mask]; } if (k % 20 == 0) { for (int i = 0; i <= mxp; ++i) for (int mask = 0; mask <= all; ++mask) g[i][mask] %= mod; } } g[0][0] += mod - 1; int mxp = n / c; for (int i = 0; i <= n; ++i) { if (i > mxp) { printf( 0 ); continue; } int res = 0; for (int mask = 0; mask < all; ++mask) add_mod(res, g[i][mask] % mod); printf( %d , res); } exit(0); } } // namespace Subtask2 int main(void) { pw2[0] = 1; for (int i = 1; i < MAXN; ++i) pw2[i] = pw2[i - 1] * 2 % mod; for (int i = 0; i < MAXN; ++i) icoef[i] = pw((pw2[i] - 1 + mod) % mod, mod - 2); scanf( %d%d , &n, &c); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); if (c <= 12) Subtask2::solve(); else Subtask1::solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
`define SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200009; long long N, M; long long Max[MAXN], A[MAXN]; long long maxLL(long long num1, long long num2) { return (num1 > num2 ? num1 : num2); } void Update(int x, long long nh) { for (int i = x; i <= N; i += (i & (-i))) Max[i] = maxLL(Max[i], nh); } long long Find(int x) { long long ret = 0; for (int i = x; i >= 1; i -= (i & (-i))) ret = maxLL(ret, Max[i]); return ret; } int main() { cin >> N; for (int i = 1; i <= N; i++) Max[i] = 0; for (int i = 1; i <= N; i++) { cin >> A[i]; Update(i, A[i]); } cin >> M; for (int i = 1; i <= M; i++) { long long Xx, Yy; cin >> Xx >> Yy; long long Ans = Find(Xx); Update(1, Ans + Yy); cout << Ans << n ; } }
|
#include <bits/stdc++.h> using namespace std; int n, m, zero, one, tot; long long mod; long long dp[505][505]; string str[505]; long long dfs(int z, int o) { long long& ret = dp[z][o]; if (ret != -1) return ret; ret = 0; if (z == 0 && o == 0) return ret = 1; if (z > 0 && o > 0) { long long nxt = dfs(z - 1, o); nxt = nxt * (long long)z % mod; nxt = nxt * (long long)o % mod; ret = (ret + nxt) % mod; } if (z > 1) { long long nxt = dfs(z - 2, o + 2); nxt = nxt * (long long)z * (z - 1) / 2 % mod; ret = (ret + nxt) % mod; } if (o > 1) { long long nxt = dfs(z, o - 2); nxt = nxt * (long long)o * (o - 1) / 2 % mod; ret = (ret + nxt) % mod; } return ret; } int main() { scanf( %d %d %I64d , &n, &m, &mod); int flag = 0; for (int i = 0; i < m; i++) { cin >> str[i]; int cnt = 0; for (int j = 0; j < n; j++) { if (str[i][j] == 1 ) ++cnt; } if (cnt != 2) { flag = 1; } } if (flag) { puts( 0 ); return 0; } for (int j = 0; j < n; j++) { int cc = 0; for (int i = 0; i < m; i++) { if (str[i][j] == 1 ) ++cc; } if (cc >= 3) { puts( 0 ); return 0; } if (cc == 0) zero++; else if (cc == 1) one++; } if (zero + zero + one != 2 * (n - m)) { puts( 0 ); return 0; } memset(dp, -1, sizeof(dp)); long long ans = dfs(zero, one); cout << ans; }
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long f = 1, x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } const int maxn = 5e5 + 5; char st1[maxn], st2[maxn]; long long ans = 0, pre = 0; int n, k; int main() { n = read(), k = read(); scanf( %s , st1); scanf( %s , st2); for (int i = 0; i <= n - 1; i++) { pre = min(pre * 2 + (int)(st2[i] - st1[i]), 1ll << 36); ans += min(pre + 1, (long long)k); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, z = 0; cin >> n; long long a[n], b[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < n; i++) { cin >> b[i]; } vector<long long> neg, pos; for (long long i = 0; i < n; i++) { if (a[i] == b[i]) z++; if ((a[i] - b[i]) >= 0) pos.push_back(a[i] - b[i]); else neg.push_back(b[i] - a[i]); } if (!pos.empty()) sort(pos.begin(), pos.end()); if (!neg.empty()) sort(neg.begin(), neg.end()); long long ans = 0, cnt = 0, j = (long long)neg.size() - 1, k = (long long)pos.size() - 1; ans += (k * (k + 1)) / 2; ans -= (z * (z - 1)) / 2; while (j >= 0 && !pos.empty()) { if (k >= 0 && neg[j] < pos[k]) { cnt++; k--; } else { ans += cnt; j--; } } cout << ans << endl; return; } int main() { long long t; t = 1; while (t--) { solve(); } return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module daq1_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio);
// 4 wire
input [ 2:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (((spi_count == 6'd16) && (spi_csn[2] == 1'b0)) ||
((spi_count == 6'd8) && (spi_csn[1] == 1'b0)) ||
((spi_count == 6'd16) && (spi_csn[0] == 1'b0))) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NOR4BB_BEHAVIORAL_PP_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4BB_BEHAVIORAL_PP_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_shr(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATA_WIDTH = 32;
parameter CONFIG_WIDTH= 5;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [CONFIG_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_dataout_stall;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = CONFIG_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
assign is_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & ~i_dataout_stall);
assign o_dataout = dataa >> datab;
assign o_dataout_valid = is_fifo_a_valid & is_fifo_b_valid;
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2017 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`timescale 1ps / 1ps
//Need a buffer depth of at least 512 (address width = 9)
module adapter_rgb_2_ppfifo #(
parameter DATA_WIDTH = 24
)(
input clk,
input rst,
input [23:0] i_rgb,
input i_h_sync,
input i_h_blank,
input i_v_sync,
input i_v_blank,
input i_data_en,
//Ping Pong FIFO Write Controller
output o_ppfifo_clk,
input [1:0] i_ppfifo_rdy,
output reg [1:0] o_ppfifo_act,
input [23:0] i_ppfifo_size,
output reg o_ppfifo_stb,
output reg [DATA_WIDTH - 1:0] o_ppfifo_data
);
//local parameters
localparam IDLE = 0;
localparam READY = 1;
localparam RELEASE = 2;
//registes/wires
reg [23:0] r_count;
reg [2:0] state;
//submodules
//asynchronous logic
assign o_ppfifo_clk = clk;
//synchronous logic
always @ (posedge clk) begin
o_ppfifo_stb <= 0;
if (rst) begin
r_count <= 0;
o_ppfifo_act <= 0;
o_ppfifo_data <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
o_ppfifo_act <= 0;
if ((i_ppfifo_rdy > 0) && (o_ppfifo_act == 0)) begin
r_count <= 0;
if (i_ppfifo_rdy[0]) begin
o_ppfifo_act[0] <= 1;
end
else begin
o_ppfifo_act[1] <= 1;
end
state <= READY;
end
end
READY: begin
if (r_count < i_ppfifo_size) begin
if (!i_h_blank) begin
o_ppfifo_stb <= 1;
o_ppfifo_data <= i_rgb;
r_count <= r_count + 1;
end
end
//Conditions to release the FIFO or stop a transaction
else begin
state <= RELEASE;
end
if (r_count > 0 && i_h_blank) begin
state <= RELEASE;
end
end
RELEASE: begin
o_ppfifo_act <= 0;
state <= IDLE;
end
default: begin
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__AND3B_FUNCTIONAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and3b (
X ,
A_N,
B ,
C
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3B_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; template <class T1, class T2> ostream &operator<<(ostream &os, const pair<T1, T2> &p) { os << { << p.first << , << p.second << } ; return os; } const int N = 2e6 + 5; const int oo = 1e9 + 7; int lp[N + 1]; vector<int> pr; void sieve() { for (int i = 2; i <= N; ++i) { if (lp[i] == 0) { lp[i] = i; pr.push_back(i); } for (int j = 0; j < (int)pr.size() && pr[j] <= lp[i] && i * pr[j] <= N; ++j) lp[i * pr[j]] = pr[j]; } } int n; int a[N]; bool isp[N]; int cnt(int x) { return upper_bound(a, a + n, x) - lower_bound(a, a + n, x); } int chk() { for (int i = upper_bound(a, a + n, 1) - a; i < n; i++) { if (isp[a[i] + 1]) return a[i]; } return 0; } int32_t main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); sieve(); for (int i : pr) isp[i] = 1; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); int y = chk(); int x = cnt(1) + (y > 0); if (x >= 2) { cout << x << n ; if (y) { cout << y << ; x--; } for (int i = 1; i <= x; i++) cout << 1 ; cout << n ; } else { for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if (isp[a[i] + a[j]]) { cout << 2 n ; cout << a[i] << << a[j] << endl; return 0; } } } cout << 1 n ; cout << a[0] << n ; } }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// RMON_CTRL.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2006/01/19 14:07:55 maverickist
// verification is complete.
//
// Revision 1.2 2005/12/16 06:44:19 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
module RMON_CTRL (
Clk ,
Reset ,
//RMON_CTRL
Reg_apply_0 ,
Reg_addr_0 ,
Reg_data_0 ,
Reg_next_0 ,
Reg_apply_1 ,
Reg_addr_1 ,
Reg_data_1 ,
Reg_next_1 ,
//dual-port ram
Addra ,
Dina ,
Douta ,
Wea ,
//CPU
CPU_rd_addr ,
CPU_rd_apply ,
CPU_rd_grant ,
CPU_rd_dout
);
input Clk ;
input Reset ;
//RMON_CTRL
input Reg_apply_0 ;
input [4:0] Reg_addr_0 ;
input [15:0] Reg_data_0 ;
output Reg_next_0 ;
input Reg_apply_1 ;
input [4:0] Reg_addr_1 ;
input [15:0] Reg_data_1 ;
output Reg_next_1 ;
//dual-port ram
//port-a for Rmon
output [5:0] Addra ;
output [31:0] Dina ;
input [31:0] Douta ;
output Wea ;
//CPU
input [5:0] CPU_rd_addr ;
input CPU_rd_apply ;
output CPU_rd_grant ;
output [31:0] CPU_rd_dout ;
//******************************************************************************
//internal signals
//******************************************************************************
parameter StateCPU =4'd00;
parameter StateMAC0 =4'd01;
parameter StateMAC1 =4'd02;
reg [3:0] CurrentState /* synthesys syn_keep=1 */;
reg [3:0] NextState;
reg [3:0] CurrentState_reg;
reg [4:0] StepCounter;
reg [31:0] DoutaReg;
reg [5:0] Addra ;
reg [31:0] Dina;
reg Reg_next_0 ;
reg Reg_next_1 ;
reg Write;
reg Read;
reg Pipeline;
reg [31:0] CPU_rd_dout ;
reg CPU_rd_apply_reg ;
//******************************************************************************
//State Machine
//******************************************************************************
always @(posedge Clk or posedge Reset)
if (Reset)
CurrentState <=StateMAC0;
else
CurrentState <=NextState;
always @(posedge Clk or posedge Reset)
if (Reset)
CurrentState_reg <=StateMAC0;
else if(CurrentState!=StateCPU)
CurrentState_reg <=CurrentState;
always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg
or Reg_apply_1
or StepCounter
)
case(CurrentState)
StateMAC0:
if(!Reg_apply_0&&CPU_rd_apply_reg)
NextState =StateCPU;
else if(!Reg_apply_0)
NextState =StateMAC1;
else
NextState =CurrentState;
StateMAC1:
if(!Reg_apply_1&&CPU_rd_apply_reg)
NextState =StateCPU;
else if(!Reg_apply_1)
NextState =StateMAC0;
else
NextState =CurrentState;
StateCPU:
if (StepCounter==3)
case (CurrentState_reg)
StateMAC0 :NextState =StateMAC0 ;
StateMAC1 :NextState =StateMAC1 ;
default :NextState =StateMAC0;
endcase
else
NextState =CurrentState;
default:
NextState =StateMAC0;
endcase
always @(posedge Clk or posedge Reset)
if (Reset)
StepCounter <=0;
else if(NextState!=CurrentState)
StepCounter <=0;
else if (StepCounter!=4'hf)
StepCounter <=StepCounter + 1;
//******************************************************************************
//temp signals
//******************************************************************************
always @(StepCounter)
if( StepCounter==1||StepCounter==4||
StepCounter==7||StepCounter==10)
Read =1;
else
Read =0;
always @(StepCounter or CurrentState)
if( StepCounter==2||StepCounter==5||
StepCounter==8||StepCounter==11)
Pipeline =1;
else
Pipeline =0;
always @(StepCounter or CurrentState)
if( StepCounter==3||StepCounter==6||
StepCounter==9||StepCounter==12)
Write =1;
else
Write =0;
always @(posedge Clk or posedge Reset)
if (Reset)
DoutaReg <=0;
else if (Read)
DoutaReg <=Douta;
//******************************************************************************
//gen output signals
//******************************************************************************
//Addra
always @(*)
case(CurrentState)
StateMAC0 : Addra={1'd0 ,Reg_addr_0 };
StateMAC1 : Addra={1'd1 ,Reg_addr_1 };
StateCPU: Addra=CPU_rd_addr;
default: Addra=0;
endcase
//Dina
always @(posedge Clk or posedge Reset)
if (Reset)
Dina <=0;
else
case(CurrentState)
StateMAC0 : Dina<=Douta+Reg_data_0 ;
StateMAC1 : Dina<=Douta+Reg_data_1 ;
StateCPU: Dina<=0;
default: Dina<=0;
endcase
assign Wea =Write;
//Reg_next
always @(CurrentState or Pipeline)
if(CurrentState==StateMAC0)
Reg_next_0 =Pipeline;
else
Reg_next_0 =0;
always @(CurrentState or Pipeline)
if(CurrentState==StateMAC1)
Reg_next_1 =Pipeline;
else
Reg_next_1 =0;
//CPU_rd_grant
reg CPU_rd_apply_dl1;
reg CPU_rd_apply_dl2;
//rising edge
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
CPU_rd_apply_dl1 <=0;
CPU_rd_apply_dl2 <=0;
end
else
begin
CPU_rd_apply_dl1 <=CPU_rd_apply;
CPU_rd_apply_dl2 <=CPU_rd_apply_dl1;
end
always @ (posedge Clk or posedge Reset)
if (Reset)
CPU_rd_apply_reg <=0;
else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2)
CPU_rd_apply_reg <=1;
else if (CurrentState==StateCPU&&Write)
CPU_rd_apply_reg <=0;
assign CPU_rd_grant =!CPU_rd_apply_reg;
always @ (posedge Clk or posedge Reset)
if (Reset)
CPU_rd_dout <=0;
else if (Pipeline&&CurrentState==StateCPU)
CPU_rd_dout <=Douta;
endmodule
|
//#############################################################################
//# Purpose: SPI master IO state-machine #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module spi_master_io
(
//clk, reset, cfg
input clk, // core clock
input nreset, // async active low reset
input cpol, // cpol
input cpha, // cpha
input lsbfirst, // send lsbfirst
input manual_mode,// sets automatic ss mode
input send_data, // controls ss in manual ss mode
input [7:0] clkdiv_reg, // baudrate
output reg [2:0] spi_state, // current spi tx state
// data to transmit
input [7:0] fifo_dout, // data payload
input fifo_empty, //
output fifo_read, // read new byte
// receive data (for sregs)
output [63:0] rx_data, // rx data
output rx_access, // transfer done
// IO interface
output reg sclk, // spi clock
output mosi, // slave input
output ss, // slave select
input miso // slave output
);
//###############
//# LOCAL WIRES
//###############
reg fifo_empty_reg;
reg load_byte;
reg ss_reg;
wire [7:0] data_out;
wire [15:0] clkphase0;
wire period_match;
wire phase_match;
wire clkout;
wire clkchange;
wire data_done;
wire spi_wait;
wire shift;
wire spi_active;
wire tx_shift;
wire rx_shift;
/*AUTOWIRE*/
//#################################
//# CLOCK GENERATOR
//#################################
assign clkphase0[7:0] = 'b0;
assign clkphase0[15:8] = (clkdiv_reg[7:0]+1'b1)>>1;
oh_clockdiv
oh_clockdiv (.clkdiv (clkdiv_reg[7:0]),
.clken (1'b1),
.clkrise0 (period_match),
.clkfall0 (phase_match),
.clkphase1 (16'b0),
.clkout0 (clkout),
//clocks not used ("single clock")
.clkout1 (),
.clkrise1 (),
.clkfall1 (),
.clkstable (),
//ignore for now, assume no writes while spi active
.clkchange (1'b0),
/*AUTOINST*/
// Inputs
.clk (clk),
.nreset (nreset),
.clkphase0 (clkphase0[15:0]));
//#################################
//# STATE MACHINE
//#################################
`define SPI_IDLE 3'b000 // set ss to 1
`define SPI_SETUP 3'b001 // setup time
`define SPI_DATA 3'b010 // send data
`define SPI_HOLD 3'b011 // hold time
`define SPI_MARGIN 3'b100 // pause
always @ (posedge clk or negedge nreset)
if(!nreset)
spi_state[2:0] <= `SPI_IDLE;
else
case (spi_state[2:0])
`SPI_IDLE :
spi_state[2:0] <= fifo_read ? `SPI_SETUP : `SPI_IDLE;
`SPI_SETUP :
spi_state[2:0] <= phase_match ? `SPI_DATA : `SPI_SETUP;
`SPI_DATA :
spi_state[2:0] <= data_done ? `SPI_HOLD : `SPI_DATA;
`SPI_HOLD :
spi_state[2:0] <= phase_match ? `SPI_MARGIN : `SPI_HOLD;
`SPI_MARGIN :
spi_state[2:0] <= phase_match ? `SPI_IDLE : `SPI_MARGIN;
endcase // case (spi_state[1:0])
//read fifo on phase match (due to one cycle pipeline latency
assign fifo_read = ~fifo_empty & ~spi_wait & phase_match;
//data done whne
assign data_done = fifo_empty & ~spi_wait & phase_match;
//load is the result of the fifo_read
always @ (posedge clk)
load_byte <= fifo_read;
//#################################
//# CHIP SELECT
//#################################
assign spi_active = ~(spi_state[2:0]==`SPI_IDLE | spi_state[2:0]==`SPI_MARGIN);
assign ss = ~((spi_active & ~manual_mode) | (send_data & manual_mode));
//#################################
//# DRIVE OUTPUT CLOCK
//#################################
always @ (posedge clk or negedge nreset)
if(~nreset)
sclk <= 1'b0;
else if (period_match & (spi_state[2:0]==`SPI_DATA))
sclk <= 1'b1;
else if (phase_match & (spi_state[2:0]==`SPI_DATA))
sclk <= 1'b0;
//#################################
//# TX SHIFT REGISTER
//#################################
//shift on falling edge
assign tx_shift = phase_match & (spi_state[2:0]==`SPI_DATA);
oh_par2ser #(.PW(8),
.SW(1))
par2ser (// Outputs
.dout (mosi), // serial output
.access_out (),
.wait_out (spi_wait),
// Inputs
.clk (clk),
.nreset (nreset), // async active low reset
.din (fifo_dout[7:0]), // 8 bit data from fifo
.shift (tx_shift), // shift on neg edge
.datasize (8'd7), // 8 bits at a time (0..7-->8)
.load (load_byte), // load data from fifo
.lsbfirst (lsbfirst), // serializer direction
.fill (1'b0), // fill with slave data
.wait_in (1'b0)); // no wait
//#################################
//# RX SHIFT REGISTER
//#################################
//shift in rising edge
assign rx_shift = (spi_state[2:0] == `SPI_DATA) & period_match;
oh_ser2par #(.PW(64),
.SW(1))
ser2par (//output
.dout (rx_data[63:0]), // parallel data out
//inputs
.din (miso), // serial data in
.clk (clk), // shift clk
.lsbfirst (lsbfirst), // shift direction
.shift (rx_shift)); // shift data
//generate access pulse at rise of ss
always @ (posedge clk or negedge nreset)
if(!nreset)
ss_reg <= 1'b1;
else
ss_reg <= ss;
assign rx_access = ss & ~ss_reg;
endmodule // spi_master_io
// Local Variables:
// verilog-library-directories:("." "../../common/hdl" "../../emesh/hdl")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBN_2_V
`define SKY130_FD_SC_HS__DFBBN_2_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog wrapper for dfbbn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfbbn_2 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfbbn_2 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBN_2_V
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } int main() { vector<long long int> v1; vector<long long int> v2; long long int n, mo = 0, x, y, f; scanf( %lld , &n); for (long long int i = 0; i < n; i++) { scanf( %lld , &f); v1.push_back(f); } for (long long int i = 0; i < n; ++i) { v2.push_back(v1[i]); if (i + 1 == n) break; x = v1[i], y = v1[i + 1]; if (x < y) swap(x, y); if (gcd(x, y) != 1) { mo++; v2.push_back(1); } } printf( %lld n , mo); for (long long int i = 0; i < v2.size(); ++i) printf( %lld , v2[i]); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > points; pair<int, int> dif(pair<int, int> pa, pair<int, int> pb) { pair<int, int> res; res.first = pb.first - pa.first; res.second = pb.second - pa.second; return res; } int dot(pair<int, int> a, pair<int, int> b) { return a.first * b.first + a.second * b.second; } double dist(pair<int, int> a, pair<int, int> b) { return ((double)((a.first - b.first) * (a.first - b.first) + (a.second - b.second) * (a.second - b.second))); } double len(pair<int, int> a) { return dist(a, make_pair(0, 0)); } int main() { for (int i = 0; i < 8; i++) { int x, y; cin >> x >> y; points.push_back(make_pair(x, y)); } vector<int> perm; for (int i = 0; i < 8; i++) perm.push_back(i); int cnt = 0; bool found = false; do { cnt++; bool fs = false, ss = false; bool fis = true, sif = true; pair<int, int> a = points[perm[0]]; pair<int, int> b = points[perm[1]]; pair<int, int> c = points[perm[2]]; pair<int, int> d = points[perm[3]]; pair<int, int> e = points[perm[4]]; pair<int, int> f = points[perm[5]]; pair<int, int> g = points[perm[6]]; pair<int, int> h = points[perm[7]]; pair<int, int> ab = dif(a, b); pair<int, int> bc = dif(b, c); pair<int, int> cd = dif(c, d); pair<int, int> da = dif(d, a); fs = (dot(ab, bc) == 0 && dot(bc, cd) == 0 && dot(cd, da) == 0 && dot(da, ab) == 0 && fabs(len(ab) - len(bc)) < 0.01 && fabs(len(bc) - len(cd)) < 0.01 && fabs(len(cd) - len(da)) < 0.01); pair<int, int> ef = dif(e, f); pair<int, int> fg = dif(f, g); pair<int, int> gh = dif(g, h); pair<int, int> he = dif(h, e); ss = (dot(ef, fg) == 0 && dot(fg, gh) == 0 && dot(gh, he) == 0 && dot(he, ef) == 0 && fabs(len(ef) - len(gh)) < 0.01 && fabs(len(fg) - len(he)) < 0.01); if (ss && fs) { found = true; break; } } while (next_permutation(perm.begin(), perm.end())); if (found) { cout << YES << endl; for (int i = 0; i < 4; i++) { if (i != 0) cout << ; cout << perm[i] + 1; } cout << endl; for (int i = 4; i < 8; i++) { if (i != 4) cout << ; cout << perm[i] + 1; } cout << endl; } else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> int main() { long long count = 0; long long int n, a[100010], j, i; scanf( %lld , &n); for (i = 1; i <= n; i++) scanf( %lld , &a[i]); for (i = 1; i <= n; i++) { for (j = i + 1; j <= n; j++) if (a[i] != a[j]) break; count += ((j - i - 1) * (j - i)) / 2; i = j - 1; } printf( %lld n , count + n); return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_dbg_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Top level Module: jbi_dbg_buf
// Where Instantiated: jbi_dbg
// Description: Debug Port Queue
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
`include "jbi.h"
module jbi_dbg_buf(/*AUTOARG*/
// Outputs
dbgq_hi_rdata, dbgq_lo_rdata,
// Inputs
clk, hold, testmux_sel, scan_en, csr_16x65array_margin,
dbgq_hi_raddr, dbgq_lo_raddr, dbgq_hi_waddr, dbgq_lo_waddr,
dbgq_hi_csn_wr, dbgq_lo_csn_wr, dbgq_hi_csn_rd, dbgq_lo_csn_rd,
dbgq_hi_wdata, dbgq_lo_wdata
);
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
input clk;
input hold;
input testmux_sel;
input scan_en;
input [4:0] csr_16x65array_margin;
input [`JBI_DBGQ_ADDR_WIDTH-1:0] dbgq_hi_raddr;
input [`JBI_DBGQ_ADDR_WIDTH-1:0] dbgq_lo_raddr;
input [`JBI_DBGQ_ADDR_WIDTH-1:0] dbgq_hi_waddr;
input [`JBI_DBGQ_ADDR_WIDTH-1:0] dbgq_lo_waddr;
input dbgq_hi_csn_wr;
input dbgq_lo_csn_wr;
input dbgq_hi_csn_rd;
input dbgq_lo_csn_rd;
input [`JBI_DBGQ_WIDTH-1:0] dbgq_hi_wdata;
input [`JBI_DBGQ_WIDTH-1:0] dbgq_lo_wdata;
output [`JBI_DBGQ_WIDTH-1:0] dbgq_hi_rdata;
output [`JBI_DBGQ_WIDTH-1:0] dbgq_lo_rdata;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
reg [`JBI_DBGQ_WIDTH-1:0] dbgq_hi_rdata;
reg [`JBI_DBGQ_WIDTH-1:0] dbgq_lo_rdata;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
wire dbgq_hi_csn_wr0;
wire dbgq_hi_csn_wr1;
wire [`JBI_DBGQ_WIDTH-1:0] dbgq_hi_rdata0;
wire [`JBI_DBGQ_WIDTH-1:0] dbgq_hi_rdata1;
wire dbgq_hi_rdata_sel;
wire next_dbgq_hi_rdata_sel;
wire dbgq_lo_csn_wr0;
wire dbgq_lo_csn_wr1;
wire [`JBI_DBGQ_WIDTH-1:0] dbgq_lo_rdata0;
wire [`JBI_DBGQ_WIDTH-1:0] dbgq_lo_rdata1;
wire dbgq_lo_rdata_sel;
wire next_dbgq_lo_rdata_sel;
wire [65-`JBI_DBGQ_WIDTH-1:0] dangle_hi0;
wire [65-`JBI_DBGQ_WIDTH-1:0] dangle_hi1;
wire [65-`JBI_DBGQ_WIDTH-1:0] dangle_lo0;
wire [65-`JBI_DBGQ_WIDTH-1:0] dangle_lo1;
//*******************************************************************************
// DBG HI
//*******************************************************************************
assign dbgq_hi_csn_wr0 = ~(~dbgq_hi_csn_wr & ~dbgq_hi_waddr[`JBI_DBGQ_ADDR_WIDTH-1]);
assign dbgq_hi_csn_wr1 = ~(~dbgq_hi_csn_wr & dbgq_hi_waddr[`JBI_DBGQ_ADDR_WIDTH-1]);
assign next_dbgq_hi_rdata_sel = dbgq_hi_raddr[`JBI_DBGQ_ADDR_WIDTH-1];
always @ ( /*AUTOSENSE*/dbgq_hi_rdata0 or dbgq_hi_rdata1
or dbgq_hi_rdata_sel) begin
if (dbgq_hi_rdata_sel)
dbgq_hi_rdata = dbgq_hi_rdata1;
else
dbgq_hi_rdata = dbgq_hi_rdata0;
end
bw_rf_16x65 #(1, 1, 1, 0) u_dbg_hi_buf0
(.rd_clk(clk), // read clock
.wr_clk(clk), // read clock
.csn_rd(dbgq_hi_csn_rd), // read enable -- active low
.csn_wr(dbgq_hi_csn_wr0), // write enable -- active low
.hold(hold), // Bypass signal -- unflopped -- bypass input data when 0
.scan_en(scan_en), // Scan enable unflopped
.margin(csr_16x65array_margin), // Delay for the circuits--- set to 10101
.rd_a(dbgq_hi_raddr[`JBI_DBGQ_ADDR_WIDTH-2:0]), // read address
.wr_a(dbgq_hi_waddr[`JBI_DBGQ_ADDR_WIDTH-2:0]), // Write address
.di({ {65-`JBI_DBGQ_WIDTH{1'b0}},
dbgq_hi_wdata[`JBI_DBGQ_WIDTH-1:0] }), // Data input
.testmux_sel(testmux_sel), // bypass signal -- unflopped -- testmux_sel = 1 bypasses di to do
.si(), // scan in -- NOT CONNECTED
.so(), // scan out -- TIED TO ZERO
.listen_out(), // Listening flop--
.do( {dangle_hi0,
dbgq_hi_rdata0[`JBI_DBGQ_WIDTH-1:0]} ) // Data out
);
bw_rf_16x65 #(1, 1, 1, 0) u_dbg_hi_buf1
(.rd_clk(clk), // read clock
.wr_clk(clk), // read clock
.csn_rd(dbgq_hi_csn_rd), // read enable -- active low
.csn_wr(dbgq_hi_csn_wr1), // write enable -- active low
.hold(hold), // Bypass signal -- unflopped -- bypass input data when 0
.scan_en(scan_en), // Scan enable unflopped
.margin(csr_16x65array_margin), // Delay for the circuits--- set to 10101
.rd_a(dbgq_hi_raddr[`JBI_DBGQ_ADDR_WIDTH-2:0]), // read address
.wr_a(dbgq_hi_waddr[`JBI_DBGQ_ADDR_WIDTH-2:0]), // Write address
.di({ {65-`JBI_DBGQ_WIDTH{1'b0}},
dbgq_hi_wdata[`JBI_DBGQ_WIDTH-1:0] }), // Data input
.testmux_sel(testmux_sel), // bypass signal -- unflopped -- testmux_sel = 1 bypasses di to do
.si(), // scan in -- NOT CONNECTED
.so(), // scan out -- TIED TO ZERO
.listen_out(), // Listening flop--
.do( {dangle_hi1,
dbgq_hi_rdata1[`JBI_DBGQ_WIDTH-1:0]} ) // Data out
);
dff_ns #(1) u_dff_dbgq_hi_rdata_sel
(.din(next_dbgq_hi_rdata_sel),
.clk(clk),
.q(dbgq_hi_rdata_sel)
);
//*******************************************************************************
// DBG HI
//*******************************************************************************
assign dbgq_lo_csn_wr0 = ~(~dbgq_lo_csn_wr & ~dbgq_lo_waddr[`JBI_DBGQ_ADDR_WIDTH-1]);
assign dbgq_lo_csn_wr1 = ~(~dbgq_lo_csn_wr & dbgq_lo_waddr[`JBI_DBGQ_ADDR_WIDTH-1]);
assign next_dbgq_lo_rdata_sel = dbgq_lo_raddr[`JBI_DBGQ_ADDR_WIDTH-1];
always @ ( /*AUTOSENSE*/dbgq_lo_rdata0 or dbgq_lo_rdata1
or dbgq_lo_rdata_sel) begin
if (dbgq_lo_rdata_sel)
dbgq_lo_rdata = dbgq_lo_rdata1;
else
dbgq_lo_rdata = dbgq_lo_rdata0;
end
bw_rf_16x65 #(1, 1, 1, 0) u_dbg_lo_buf0
(.rd_clk(clk), // read clock
.wr_clk(clk), // read clock
.csn_rd(dbgq_lo_csn_rd), // read enable -- active low
.csn_wr(dbgq_lo_csn_wr0), // write enable -- active low
.hold(hold), // Bypass signal -- unflopped -- bypass input data when 0
.scan_en(scan_en), // Scan enable unflopped
.margin(csr_16x65array_margin), // Delay for the circuits--- set to 10101
.rd_a(dbgq_lo_raddr[`JBI_DBGQ_ADDR_WIDTH-2:0]), // read address
.wr_a(dbgq_lo_waddr[`JBI_DBGQ_ADDR_WIDTH-2:0]), // Write address
.di({ {65-`JBI_DBGQ_WIDTH{1'b0}},
dbgq_lo_wdata[`JBI_DBGQ_WIDTH-1:0] }), // Data input
.testmux_sel(testmux_sel), // bypass signal -- unflopped -- testmux_sel = 1 bypasses di to do
.si(), // scan in -- NOT CONNECTED
.so(), // scan out -- TIED TO ZERO
.listen_out(), // Listening flop--
.do( {dangle_lo0,
dbgq_lo_rdata0[`JBI_DBGQ_WIDTH-1:0]} ) // Data out
);
bw_rf_16x65 #(1, 1, 1, 0) u_dbg_lo_buf1
(.rd_clk(clk), // read clock
.wr_clk(clk), // read clock
.csn_rd(dbgq_lo_csn_rd), // read enable -- active low
.csn_wr(dbgq_lo_csn_wr1), // write enable -- active low
.hold(hold), // Bypass signal -- unflopped -- bypass input data when 0
.scan_en(scan_en), // Scan enable unflopped
.margin(csr_16x65array_margin), // Delay for the circuits--- set to 10101
.rd_a(dbgq_lo_raddr[`JBI_DBGQ_ADDR_WIDTH-2:0]), // read address
.wr_a(dbgq_lo_waddr[`JBI_DBGQ_ADDR_WIDTH-2:0]), // Write address
.di({ {65-`JBI_DBGQ_WIDTH{1'b0}},
dbgq_lo_wdata[`JBI_DBGQ_WIDTH-1:0] }), // Data input
.testmux_sel(testmux_sel), // bypass signal -- unflopped -- testmux_sel = 1 bypasses di to do
.si(), // scan in -- NOT CONNECTED
.so(), // scan out -- TIED TO ZERO
.listen_out(), // Listening flop--
.do( {dangle_lo1,
dbgq_lo_rdata1[`JBI_DBGQ_WIDTH-1:0]} ) // Data out
);
dff_ns #(1) u_dff_dbgq_lo_rdata_sel
(.din(next_dbgq_lo_rdata_sel),
.clk(clk),
.q(dbgq_lo_rdata_sel)
);
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-files:("../../../common/rtl/swrvr_u1_clib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const int inf = 0x3f3f3f3f; int n; vector<int> vec[N]; int dis(int s, int t) { if (t >= s) return t - s; return t - s + n; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int m; cin >> n >> m; int num = 0; for (int i = 1; i <= m; i++) { int a, b; cin >> a >> b; vec[a].push_back(dis(a, b)); num = max(num, (int)vec[a].size()); } for (int i = 1; i <= n; i++) { sort(vec[i].begin(), vec[i].end()); } for (int st = 1; st <= n; st++) { int ans = 0; for (int i = 1; i <= n; i++) { if (vec[i].size() > 0) ans = max(ans, dis(st, i) + ((int)vec[i].size() - 1) * n + vec[i][0]); } cout << ans << ; } cout << endl; }
|
/*
*This HDL is top level module.
*HDL depends on other modules.
*It is
* spi_rx.v
* synth_arb.v
* operator.v
* -sine.v
* -diff_rom.v
* -sin_rom.v
* pwm_out.v
* fifo_tx.v(Altera QuartusII Megafunction IP dcfifo)
* pll.v(Altera QuartusII Megafunction IP altpll)
*
*External MicroController can controll module by 3wire-Serial interface like SPI(mode 0,0)
*
*Input Freq : 12.288MHz(XO or TCXO)
*
*PLL output Freq :
* C0 24.576MHz
* C1 196.608MHz
*/
module synth1(
input wire clk,
input wire reset_n,
input wire sdi,
input wire sck,
input wire ss_n,
output wire pwm_out_l,
output wire pwm_out_r,
input wire [3:0] gnd);
/*Signal Declaration*/
reg clr_reg1, clr_reg2;
wire clr_n, wrreq, wwreq2arb, rdreq, full, empty, clk_int, clk_ext;
wire [20:0] phase;
wire [15:0] data_out;
wire [31:0] data, fifo_in;
wire [7:0] synth_ctrl, synth_data, memadrs, memdata;
reg [7:0] clr_cnt = 8'h00;
/*End Declaration*/
/*Instantiation Modules*/
synth_arb arbiter(
.clk(clk_int),
.reset_n(clr_n),
.memadrs(memadrs),
.memdata(memdata),
.wreq(wrreq2arb),
.synth_ctrl(synth_ctrl),
.synth_data(synth_data),
.fifo_full(full)
);
spi_rx spi_rx(
.clk(clk_int),
.reset_n(clr_n),
.sdi(sdi),
.sck(sck),
.ss_n(ss_n),
.adrs(memadrs),
.data(memdata),
.rx_valid(wrreq2arb));
pwm_out pwm_out(
.clk(clk_ext),
.reset_n(clr_n),
.fifo_rdreq(rdreq),
.fifo_empty(empty),
.fifo_data(data),
.pwm_out_r(pwm_out_r),
.pwm_out_l(pwm_out_l)
);
operator operator_1(
.clk(clk_int),
.reset_n(clr_n),
.synth_ctrl(synth_ctrl),
.synth_data(synth_data),
.data_out(data_out),
.wreq(wrreq));
fifo_tx fifo_tx (
.aclr ( clr ),
.data ( fifo_in ),
.rdclk ( clk_ext ),
.rdreq ( rdreq ),
.wrclk ( clk_int ),
.wrreq ( wrreq ),
.q ( data ),
.rdempty ( empty ),
.wrfull ( full )
);
pll pll (
.inclk0 ( clk ),
.c0 ( clk_int ),
.c1 ( clk_ext )
);
/*End Instantiation*/
/*Reset Logic*/
assign clr_n = clr_reg2 | (~&clr_cnt);
always @(posedge clk_int, negedge reset_n)
begin
if(!reset_n)
begin
clr_reg1 <= 0;
clr_reg2 <= 0;
end
else
begin
clr_reg1 <= 1;
clr_reg2 <= clr_reg1;
end
end
always @(posedge clk_int)
begin
if(clr_cnt == 8'hFF) clr_cnt <= clr_cnt;
else clr_cnt <= clr_cnt + 1;
end
/*Assign*/
assign fifo_in = {12'd0, gnd, data_out};
assign clr = ~clr_n;
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: gsu_cache.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module gsu_cache (
address,
clock,
data,
wren,
q);
input [8:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:671088640 ) using namespace std; const int MOD = 1000000007; const int INF = 20000000; const long double EPS = 1e-7; const int HASH_POW = 29; const long double PI = acos(-1.0); mt19937_64 rnd(1); double workTime() { return double(clock()) / CLOCKS_PER_SEC; } void my_return(int code) { exit(code); } int bin_pow(int a, int n) { int ans = 1; while (n) { if (n & 1) ans = ans * 1ll * a % MOD; n >>= 1; a = a * 1ll * a % MOD; } return ans; } int f[100010], rev[100010]; int C(int n, int k) { if (k < 0 || k > n) return 0; int res = f[n] * 1ll * rev[k] % MOD; return res * 1ll * rev[n - k] % MOD; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); f[0] = 1; for (int i = 1; i <= 100000; ++i) f[i] = f[i - 1] * 1ll * i % MOD; for (int i = 0; i <= 100000; ++i) rev[i] = bin_pow(f[i], MOD - 2); int f, w, h; scanf( %d %d %d , &f, &w, &h); if (w == 0) { printf( 1 n ); my_return(0); } else if (f == 0) { if (w > h) { printf( 1 n ); my_return(0); } else { printf( 0 n ); my_return(0); } } else if (w <= h) { printf( 0 n ); my_return(0); } int total = 0, good = 0; for (int i = 1; i <= w; ++i) { if (i > 1) total = (total + C(w - 1, i - 1) * 1ll * C(f - 1, i - 2)) % MOD; total = (total + 2ll * C(w - 1, i - 1) * C(f - 1, i - 1)) % MOD; total = (total + C(w - 1, i - 1) * 1ll * C(f - 1, i)) % MOD; } for (int i = 1; i <= w; ++i) { if (i * (h + 1) > w) break; int w1 = w - i * h; if (i > 1) good = (good + C(w1 - 1, i - 1) * 1ll * C(f - 1, i - 2)) % MOD; good = (good + 2ll * C(w1 - 1, i - 1) * C(f - 1, i - 1)) % MOD; good = (good + C(w1 - 1, i - 1) * 1ll * C(f - 1, i)) % MOD; } printf( %d n , good * 1ll * bin_pow(total, MOD - 2) % MOD); my_return(0); }
|
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-10; const double PI = acos(-1.0); struct Edge { int to, cost; Edge(int t, int c) : to(t), cost(c) {} bool operator>(const Edge& rhs) const { return cost > rhs.cost; } }; long long N, S; vector<int> dp, parent; vector<vector<Edge>> G; void dfs(int par, int node, int d) { parent[node] = par; dp[node] = 1; for (int i = 0; i < int((G[node]).size()); ++i) { int& to = G[node][i].to; if (to == par) continue; dfs(node, to, d + 1); dp[node] += dp[to]; S += 2 * dp[to] * (N - dp[to]) * G[node][i].cost; } } int main() { cin.tie(0); ios_base::sync_with_stdio(false); cin >> N; G.assign(N + 1, vector<Edge>()); vector<pair<int, Edge>> edges; for (int i = (0); i < (N - 1); ++i) { int a, b, c; cin >> a >> b >> c; G[a].push_back(Edge(b, c)); G[b].push_back(Edge(a, c)); edges.push_back(make_pair(a, Edge(b, c))); } dp.assign(N + 1, 0); parent.assign(N + 1, -1); S = 0; dfs(-1, 1, 0); int Q; cin >> Q; while (Q--) { int idx, c; cin >> idx >> c; --idx; Edge& e = edges[idx].second; int a = edges[idx].first, b = e.to; if (parent[b] == a) swap(a, b); S -= (e.cost - c) * 2 * dp[a] * (N - dp[a]); cout << fixed << setprecision(7) << 3 * S * 1. / (N * (N - 1)) << endl; e.cost = c; } return 0; }
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`ifdef SMV
`include "ovl_ported/std_ovl_defines.h"
`else
`include "std_ovl_defines.h"
`endif
`module ovl_always (clock, reset, enable, test_expr, fire, fire_comb);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
output [`OVL_FIRE_WIDTH-1:0] fire_comb;
// Parameters that should not be edited
parameter assert_name = "OVL_ALWAYS";
`ifdef SMV
`include "ovl_ported/std_ovl_reset.h"
`include "ovl_ported/std_ovl_clock.h"
`include "ovl_ported/std_ovl_cover.h"
`include "ovl_ported/std_ovl_init.h"
`else
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_init.h"
`include "std_ovl_task.h"
`endif
`ifdef OVL_VERILOG
`ifdef SMV
`include "./ovl_ported/vlog95/ovl_always_logic.v"
`else
`include "./vlog95/ovl_always_logic.v"
`endif
`endif
`ifdef OVL_SVA
`include "./sva05/ovl_always_logic.sv"
`endif
`ifdef OVL_PSL
`include "./psl05/assert_always_psl_logic.v"
`else
assign fire = {fire_cover, fire_xcheck, fire_2state};
assign fire_comb = {2'b0, fire_2state_comb};
`endmodule // ovl_always
`endif
|
#include <bits/stdc++.h> using namespace std; int a; char str[100002]; int sum[100002]; int cnt[100002]; int main() { scanf( %d n , &a); gets(str); int len = strlen(str); sum[0] = (str[0] - 0 ); for (int i = 1; i < len; i++) { sum[i] = sum[i - 1] + (str[i] - 0 ); } int id, x, y, mx = 0; for (int i = 0; i < len; i++) { for (int j = i; j < len; j++) { if (i > 0) id = sum[j] - sum[i - 1]; else id = sum[j]; cnt[id]++; mx = max(mx, id); } } long long ans = 0; for (int i = 0; i < len; i++) { for (int j = i; j < len; j++) { if (i > 0) x = sum[j] - sum[i - 1]; else x = sum[j]; if (a == 0) { ans += cnt[0]; } if (x == 0) continue; if (a % x != 0) continue; y = a / x; if (y > mx) continue; ans = ans + (long long)(cnt[y]); } } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4B_4_V
`define SKY130_FD_SC_HS__NAND4B_4_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4b_4 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4b_4 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4B_4_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_req_ack_unique (clock, reset, enable, req, ack, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter min_cks = 1;
parameter max_cks = 15;
parameter method = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input req, ack;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_REQ_ACK_UNIQUE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_req_ack_unique_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_req_ack_unique
|
#include <bits/stdc++.h> using namespace std; const int N = 1001; char s[N]; bool check(char a, char b) { if (a == b) return true; if (a > b) swap(a, b); if (b - a > 2) return false; if (b - a == 2) return true; if (b - a == 1) return false; } bool solve() { int n; scanf( %d%s , &n, s); for (int i = 0; i < n; i++) if (!check(s[i], s[n - 1 - i])) return false; return true; } int main() { int t; scanf( %d , &t); while (t--) { if (solve()) printf( YES n ); else printf( NO n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mn = 1005; int n, v[mn]; int main() { ios_base::sync_with_stdio(false); cin >> n; for (int x = 0; x < n; ++x) cin >> v[x]; int ans = 0; for (int x = 0; x < n; ++x) { if (v[x] == 0) continue; while (v[x] == 1 && x < n) ++ans, ++x; ++ans; } if (ans != 0) --ans; cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; void main0(); int main() { clock_t start, end; ios::sync_with_stdio(false); cin.tie(0); main0(); return 0; } const int dx[8] = {0, 1, -1, 0, 1, 1, -1, -1}; const int dy[8] = {1, 0, 0, -1, 1, -1, -1, 1}; const int N = 2e5 + 5; const int M = 1e5; const int INF = 0x3f3f3f3f; const long long INFF = 0x3f3f3f3f3f3f3f3f; const int mod = 998244353; const double eps = 1e-6; mt19937 rnd( (unsigned int)chrono::steady_clock::now().time_since_epoch().count()); template <typename T> bool chkmin(T &x, T y) { return y < x ? x = y, 1 : 0; } template <typename T> bool chkmax(T &x, T y) { return y > x ? x = y, 1 : 0; } int n, k; string s; int lc[N], rc[N]; int ord[N]; int idx[N]; int p = 0; int flag[N]; void dfs1(int u) { if (lc[u]) dfs1(lc[u]); ord[++p] = u; idx[u] = p; if (rc[u]) dfs1(rc[u]); } int rep[N]; int dfs2(int u, int k) { if (k == 0) return 0; int cost = 0; if (lc[u]) cost += dfs2(lc[u], k - 1); if (flag[u] || cost) { rep[u] = 1, cost++; if (rc[u]) cost += dfs2(rc[u], k - cost); } return cost; } void main0() { cin >> n >> k >> s; s = $ + s; for (int i = 1; i <= n; ++i) { cin >> lc[i] >> rc[i]; } dfs1(1); flag[ord[n]] = 0; for (int i = n - 1; i >= 1; --i) { int cur = ord[i]; int nxt = ord[i + 1]; flag[cur] = (s[cur] == s[nxt] ? flag[nxt] : s[cur] < s[nxt]); } dfs2(1, k); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= rep[ord[i]] + 1; ++j) { cout << s[ord[i]]; } } cout << endl; }
|
#include <bits/stdc++.h> using namespace std; const int cmax = 1e5 + 8; int n; int cnt[cmax]; vector<pair<int, int> > l(cmax); long long psum[cmax]; int d[202]; int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 1; i <= n; i++) cin >> l[i].first, cnt[l[i].first]++; for (int i = 1; i <= n; i++) cin >> l[i].second; sort(l.begin() + 1, l.begin() + n + 1); for (int i = 1; i <= n; i++) psum[i] = psum[i - 1] + l[i].second; long long ans = 284488937875784; for (int i = 1; i <= n; i++) { int p = i; while (i < n and l[i].first == l[i + 1].first) i++; long long t = psum[n] - psum[i]; int x = max(0, i - 2 * cnt[l[i].first] + 1); for (int j = 1; j <= 200 and x > 0; j++) { int u = min(x, d[j]); x -= u; t += (long long)u * j; } ans = min(ans, t); for (int k = p; k <= i; k++) d[l[k].second]++; } cout << ans << n ; return 0; }
|
`timescale 1ns / 1ps
module ADAU1761Top(
input clk,
input filter_onoff,
input AC_GPIO1,
input AC_GPIO2,
input AC_GPIO3,
output AC_GPIO0,
output AC_ADR0,
output AC_ADR1,
output AC_MCLK,
output AC_SCK,
inout AC_SDA,
input [3:0] shift,
output [2:0] display_rgb1,
output [2:0] display_rgb2,
output [3:0] display_addr,
output display_clk,
output display_oe,
output display_lat,
//input on_off,
output spi_clk,
output spi_mosi,
output spi_cs,
input spi_miso,
input rst,
output [7:0] sample,
output usb_rxd,
input usb_txd,
input mode,
input uart_active
);
wire throwaway, bt1, bt2, uart1, uart2, clean;
reg [3:0] height;
reg on_off;
initial begin
height <=0;
on_off <=0;
end
always @(posedge CLK_OUT2) begin
if (mode == 1'b0 && clean == 1'b1) begin
on_off <= ~on_off;
end
end
always @ (posedge clk_48) begin
if (filter_onoff) begin
height <= ((((headphone_left[14:0] >>> 14) ^ headphone_left) - (headphone_left >>>14)) >> shift) - 15;
end
else begin
height <= (((headphone_left >>> 15) ^ headphone_left) - (headphone_left >>> 15)) >> 4;
end
end
// 48 MHz clock
wire clk_48, CLK_OUT1, CLK_OUT2, CLK_OUT4, LOCKED;
Clock48MHZ c48(// Clock in ports
.CLK_100(clk),
.CLK_48(clk_48),
.CLK_OUT1(CLK_OUT1),
.CLK_OUT2(CLK_OUT2),
.CLK_OUT4(CLK_OUT4),
// Status and control signals
.LOCKED(LOCKED)
);
MicrophoneSampler microphone(
spi_clk,
spi_mosi,
spi_cs,
spi_miso,
CLK_OUT2,
rst,
sample);
/* Clock48MHZ c48(
.CLK_100(clk),
.CLK_48(clk_48)
);*/
// Audio module
wire [15:0] headphone_left, headphone_right, linein_left, linein_right;
wire new_sample;
adau1761_izedboard(
.clk_48(clk_48),
.AC_GPIO1(AC_GPIO1),
.AC_GPIO2(AC_GPIO2),
.AC_GPIO3(AC_GPIO3),
.hphone_l(headphone_left),
.hphone_r(headphone_right),
.AC_SDA(AC_SDA),
.AC_ADR0(AC_ADR0),
.AC_ADR1(AC_ADR1),
.AC_GPIO0(AC_GPIO0),
.AC_MCLK(AC_MCLK),
.AC_SCK(AC_SCK),
.line_in_l(linein_left),
.line_in_r(linein_right),
.new_sample(new_sample)
);
fpga_top(
.clk(clk),
.led(throwaway),
.bluetooth_rxd(bt1),
.bluetooth_txd(bt2),
.display_rgb1(display_rgb1),
.display_rgb2(display_rgb2),
.display_addr(display_addr),
.display_clk(display_clk),
.display_oe(display_oe),
.display_lat(display_lat),
.usb_rxd(usb_rxd),
.usb_txd(usb_txd),
.height(height),
.mode(mode),
.on_off(on_off),
.sysclk(CLK_OUT1),
.uartclk(CLK_OUT4),
.uart_active(uart_active),
.pll_locked(LOCKED));
wire [15:0] filter_out_left, filter_out_right;
SystolicFilter(clk_48, new_sample, linein_left, filter_out_left);
SystolicFilter(clk_48, new_sample, linein_right, filter_out_right);
assign headphone_left = (filter_onoff) ? filter_out_left : linein_left;
assign headphone_right = (filter_onoff) ? filter_out_right : linein_right;
endmodule
module debouncer(clk, button, clean);
input clk, button;
output reg clean;
parameter delay = 500;
reg [8:0] delay_count;
always@(posedge clk)
if (button==1) begin
if (delay_count==delay) begin
assign delay_count=delay_count+1'b1;
assign clean=1;
end else begin
if(delay_count==9'b1111_11111) begin
assign clean=0;
assign delay_count=9'b1111_11111;
end else begin
assign delay_count=delay_count+1'b1;
assign clean=0;
end
end
end else begin
assign delay_count=0;
assign clean=0;
end
endmodule
|
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