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#include <bits/stdc++.h> using namespace std; int b[111111], n; int check(int k) { int l = n / k; for (int i = 0; i < l; i++) { int ok = 1; int cur = i; for (int j = 0; ok && j < k; j++) { if (!b[cur]) ok = 0; cur += l; cur %= n; } if (ok) return 1; } return 0; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> b[i]; int flag = 0; for (int i = 3; i <= n; i++) { if (n % i == 0) { if (check(i)) flag = 1; } } printf(flag ? YES n : NO n ); return 0; }
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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:33:57 04/26/2017
// Design Name: decrypter
// Module Name: C:/Users/vkoro/Final_Project/project/vga/decrypt_manager_tb.v
// Project Name: vga
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: decrypter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module decrypt_manager_tb;
// Inputs
reg clk;
reg reset;
reg [7:0] encrypted_data;
reg decrypter_active;
reg [63:0] key;
// Outputs
wire [14:0] read_addr;
wire [7:0] decrypted_data;
wire [14:0] write_addr;
wire done;
integer clk_cnt;
parameter CLK_PERIOD = 10;
// Instantiate the Unit Under Test (UUT)
decrypter uut (
.clk(clk),
.reset(reset),
.encrypted_data(encrypted_data),
.decrypter_active(decrypter_active),
.key(key),
.read_addr(read_addr),
.decrypted_data(decrypted_data),
.write_addr(write_addr),
.done(done)
);
initial
begin : CLK_GENERATOR
clk = 0;
forever
begin
#(CLK_PERIOD/2) clk = ~clk;
end
end
initial
begin : RESET_GENERATOR
reset = 1;
#(10 * CLK_PERIOD) reset = 0;
end
initial
begin : CLK_COUNTER
clk_cnt = 0;
forever
begin
#(CLK_PERIOD) clk_cnt = clk_cnt + 1;
end
end
parameter [63:0] data = 64'b1110000010100110111110111111100010010010011001011010011101100101;
integer i;
initial begin
// Initialize Inputs
encrypted_data = 0;
decrypter_active = 1;
key = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
key = 64'h133457799BBCDFF1;
#100;
for (i = 0; i < 8; i = i + 1) begin
encrypted_data = data[8 * i +: 8];
#(CLK_PERIOD);
end
//ack = 1;
# 10;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR4BB_PP_BLACKBOX_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4BB_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <class T> void chkmax(T& x, T y) { x = x > y ? x : y; } template <class T> void chkmin(T& x, T y) { x = x < y ? x : y; } int n, m; vector<string> s; int calc(int mask, int j) { int res = 0; for (int i = 0; i < n; ++i) if ((mask >> i & 1) != (s[i][j] - 0 )) ++res; return res; } bool check(int a, int b) { for (int i = 0; i < n - 1; ++i) if (((a >> i & 1) + (a >> i + 1 & 1) + (b >> i & 1) + (b >> i + 1 & 1)) % 2 == 0) return 0; return 1; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cin >> n >> m; if (n >= 4) { cout << -1 << n ; return 0; } s.resize(n); for (int i = 0; i < n; ++i) cin >> s[i]; vector<vector<int>> dp(m, vector<int>(1 << n, 1e9)); for (int mask = 0; mask < 1 << n; ++mask) dp[0][mask] = calc(mask, 0); for (int i = 0; i < m - 1; ++i) for (int c_mask = 0; c_mask < 1 << n; ++c_mask) for (int n_mask = 0; n_mask < 1 << n; ++n_mask) if (check(c_mask, n_mask)) chkmin(dp[i + 1][n_mask], dp[i][c_mask] + calc(n_mask, i + 1)); int ans = 1e9; for (int mask = 0; mask < 1 << n; ++mask) chkmin(ans, dp[m - 1][mask]); cout << ans << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_TB_V
`define SKY130_FD_SC_HVL__OR3_TB_V
/**
* or3: 3-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__or3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hvl__or3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_TB_V
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; int n, l[100100], r[100100]; int rs[100100], dp[2][100100]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> l[i]; for (int i = 1; i <= n; i++) cin >> r[i]; int val = n, cnt = n; for (int i = 1; i <= n; i++) { if (l[i] == r[i] && !r[i]) rs[i] = val, cnt--; } int cn = 0; while (cnt && cn <= 10000) { val--; for (int i = 1; i <= n; i++) dp[0][i] = dp[0][i - 1] + (rs[i] > 0); for (int i = n; i; i--) dp[1][i] = dp[1][i + 1] + (rs[i] > 0); for (int i = 1; i <= n; i++) { if (!rs[i] && dp[0][i] == l[i] && dp[1][i] == r[i]) rs[i] = val, cnt--; } cn++; } if (cn >= 10000) return cout << NO , 0; for (int i = 1; i <= n; i++) if (rs[i] <= 0) return cout << NO , 0; cout << YES n ; for (int i = 1; i <= n; i++) cout << rs[i] << ; return 0; }
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#include <bits/stdc++.h> bool g[1111][1111]; int main() { int n, m; memset(g, false, sizeof(g)); scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int u, v; scanf( %d%d , &u, &v); g[u][v] = true; } int count = 0; for (int i = 2; i < n; i++) { bool flag = false; for (int j = 1; j <= n; j++) if (g[i][j] == true) { flag = true; break; } if (flag) continue; count++; } for (int j = 2; j < n; j++) { bool flag = false; for (int i = 1; i <= n; i++) if (g[i][j]) { flag = true; break; } if (flag) continue; count++; } if (n & 1) { int i, j; for (i = 1; i <= n; i++) if (g[i][n / 2 + 1]) break; for (j = 1; j <= n; j++) if (g[n / 2 + 1][j]) break; if (i > n && j > n) if (count) count--; } printf( %d n , count); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long int N = 200005; const long long int mod = 1e9 + 7; long long int n, i, j, m, k; long long int a[N]; long long int sz[N], c[N]; long long int vis[N]; vector<long long int> g[N]; long long int ans = 0; void dfs(long long int v, long long int p) { vis[v] = c[v]; for (auto x : g[v]) { if (x != p) { dfs(x, v); vis[v] += vis[x]; } } ans += min(vis[v], 2 * k - vis[v]); } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> k; for (i = 1; i <= 2 * k; i++) { long long int x; cin >> x; c[x] = 1; } for (i = 1; i < n; i++) { long long int x, y; cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } dfs(1, 0); cout << ans; }
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#include <bits/stdc++.h> using namespace std; int N, Q; vector<vector<int> > adj; vector<set<int> > grp; vector<int> dep, tin, tout; vector<vector<int> > par; int num = 0; void dfs(int now, int bf) { tin[now] = num++; if (bf != -1) par[now][0] = bf; for (int i = 1; i < 18; i++) { int tmp = par[now][i - 1]; if (tmp == -1) break; par[now][i] = par[tmp][i - 1]; } for (int i = 0; i < adj[now].size(); i++) { int nxt = adj[now][i]; if (nxt == bf) continue; dep[nxt] = dep[now] + 1; dfs(nxt, now); } tout[now] = num - 1; } void preproc() { dep.resize(N); tin.resize(N); tout.resize(N); par = vector<vector<int> >(N, vector<int>(18, -1)); dep[0] = 0; dfs(0, -1); } int lca(int x, int y) { if (dep[x] > dep[y]) swap(x, y); int dx = dep[y] - dep[x]; for (int i = 0; i < 18; i++) { if (dx & (1 << i)) y = par[y][i]; } if (x == y) return x; for (int i = 18; i--;) { if (par[x][i] != par[y][i]) { x = par[x][i]; y = par[y][i]; } } return par[x][0]; } int K; vector<int> V; vector<vector<int> > adj2; map<int, int> imp; bool cmp(int a, int b) { return tin[a] < tin[b]; } vector<int> dp, rem; void dfs2(int now, int bf) { int cnt = 0; for (int i = 0; i < adj2[now].size(); i++) { int nxt = adj2[now][i]; if (nxt == bf) continue; dfs2(nxt, now); dp[now] += dp[nxt]; if (rem[nxt] > 0) cnt++; } if (imp[V[now]]) { dp[now] += cnt; rem[now] = 1; } else { if (cnt > 1) { dp[now]++; rem[now] = 0; } else rem[now] = cnt; } } void get_dp() { dp.clear(); rem.clear(); dp = rem = vector<int>(V.size(), 0); dfs2(0, -1); } void solve() { sort(V.begin(), V.end(), cmp); for (int i = 0; i < K - 1; i++) { int x = lca(V[i], V[i + 1]); V.push_back(x); } sort(V.begin(), V.end(), cmp); V.resize(unique(V.begin(), V.end()) - V.begin()); stack<int> st; adj2.clear(); adj2.resize(V.size()); for (int i = V.size(); i--;) { while (!st.empty() && tin[V[st.top()]] <= tout[V[i]]) { adj2[i].push_back(st.top()); adj2[st.top()].push_back(i); st.pop(); } st.push(i); } bool ok = true; for (int i = 0; i < V.size(); i++) { for (int j = 0; j < adj2[i].size(); j++) { int k = adj2[i][j]; int u = V[i], v = V[k]; if (!imp[u] || !imp[v]) continue; if (grp[u].find(v) != grp[u].end()) { ok = false; break; } } } if (!ok) { printf( -1 n ); return; } get_dp(); printf( %d n , dp[0]); } int main() { scanf( %d , &N); adj.resize(N); grp.resize(N); for (int i = 0; i < N - 1; i++) { int u, v; scanf( %d %d , &u, &v); u--; v--; adj[u].push_back(v); adj[v].push_back(u); grp[u].insert(v); grp[v].insert(u); } preproc(); scanf( %d , &Q); for (int i = 0; i < Q; i++) { scanf( %d , &K); V.clear(); V.resize(K); imp.clear(); for (int j = 0; j < K; j++) { scanf( %d , &V[j]); V[j]--; imp[V[j]] = 1; } solve(); } }
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`include "alink_define.v"
module txc(
input clk ,
input rst ,
input reg_flush ,
input [`PHY_NUM-1:0] reg_mask ,
input task_id_vld ,
input [31:0] reg_tout ,
input tx_task_vld ,//tx fifo not empty
output tx_phy_start,
output reg [`PHY_NUM-1:0]tx_phy_sel ,
input tx_phy_done ,
output reg [1:0] cur_state ,
output reg [1:0] nxt_state ,
output [32*`PHY_NUM-1:0] timer_cnt ,//to slave
output [`PHY_NUM-1:0] reg_busy
);
parameter IDLE = 2'b00 ;
parameter REQ = 2'b01 ;
parameter SENT = 2'b10 ;
wire [`PHY_NUM-1:0] timer_start ;
wire [`PHY_NUM-1:0] timer_busy ;
assign tx_phy_start = cur_state == REQ && nxt_state == SENT ;
//----------------------------------------------
// Timer
//----------------------------------------------
genvar i ;
generate
for( i=0 ; i < `PHY_NUM ; i = i + 1 ) begin : G
assign timer_start[i] = task_id_vld & tx_phy_sel[i] ;
tx_timer tx_timer(
/*input */ .clk (clk ) ,
/*input */ .rst (rst ) ,
/*input */ .reg_flush (reg_flush ) ,
/*input [31:0] */ .reg_tout (reg_tout ) ,
/*input */ .timer_start (timer_start[i] ) ,
/*output */ .timer_busy (timer_busy[i] ) ,
/*output reg [31:0]*/ .timer_cnt (timer_cnt[i*32+32-1:i*32] )
);
assign reg_busy[i] = timer_start[i] | timer_busy[i] ;
end
endgenerate
//----------------------------------------------
// State Machine
//----------------------------------------------
always @ ( posedge clk ) begin
if( rst || reg_flush )
cur_state <= IDLE ;
else
cur_state <= nxt_state ;
end
always @ ( * ) begin
nxt_state = cur_state ;
case( cur_state )
IDLE: if( |tx_phy_sel ) nxt_state = REQ ;
REQ : if( tx_task_vld ) nxt_state = SENT ;
SENT: if( tx_phy_done ) nxt_state = IDLE ;
default : nxt_state = IDLE ;
endcase
end
//----------------------------------------------
// Arbiter
//----------------------------------------------
always @ ( posedge clk ) begin
if( rst || reg_flush || (cur_state == SENT && nxt_state == IDLE))
tx_phy_sel <= 32'b0 ;
else if( cur_state == IDLE ) begin
if( ~reg_busy[0 ]&®_mask[0 ] ) tx_phy_sel <= 32'b1<<0 ;
else if( ~reg_busy[1 ]&®_mask[1 ] ) tx_phy_sel <= 32'b1<<1 ;
else if( ~reg_busy[2 ]&®_mask[2 ] ) tx_phy_sel <= 32'b1<<2 ;
else if( ~reg_busy[3 ]&®_mask[3 ] ) tx_phy_sel <= 32'b1<<3 ;
else if( ~reg_busy[4 ]&®_mask[4 ] ) tx_phy_sel <= 32'b1<<4 ;
`ifdef PHY_10
else if( ~reg_busy[5 ]&®_mask[5 ] ) tx_phy_sel <= 32'b1<<5 ;
else if( ~reg_busy[6 ]&®_mask[6 ] ) tx_phy_sel <= 32'b1<<6 ;
else if( ~reg_busy[7 ]&®_mask[7 ] ) tx_phy_sel <= 32'b1<<7 ;
else if( ~reg_busy[8 ]&®_mask[8 ] ) tx_phy_sel <= 32'b1<<8 ;
else if( ~reg_busy[9 ]&®_mask[9 ] ) tx_phy_sel <= 32'b1<<9 ;
else if( ~reg_busy[10]&®_mask[10] ) tx_phy_sel <= 32'b1<<10 ;
else if( ~reg_busy[11]&®_mask[11] ) tx_phy_sel <= 32'b1<<11 ;
else if( ~reg_busy[12]&®_mask[12] ) tx_phy_sel <= 32'b1<<12 ;
else if( ~reg_busy[13]&®_mask[13] ) tx_phy_sel <= 32'b1<<13 ;
else if( ~reg_busy[14]&®_mask[14] ) tx_phy_sel <= 32'b1<<14 ;
else if( ~reg_busy[15]&®_mask[15] ) tx_phy_sel <= 32'b1<<15 ;
else if( ~reg_busy[16]&®_mask[16] ) tx_phy_sel <= 32'b1<<16 ;
else if( ~reg_busy[17]&®_mask[17] ) tx_phy_sel <= 32'b1<<17 ;
else if( ~reg_busy[18]&®_mask[18] ) tx_phy_sel <= 32'b1<<18 ;
else if( ~reg_busy[19]&®_mask[19] ) tx_phy_sel <= 32'b1<<19 ;
else if( ~reg_busy[20]&®_mask[20] ) tx_phy_sel <= 32'b1<<20 ;
else if( ~reg_busy[21]&®_mask[21] ) tx_phy_sel <= 32'b1<<21 ;
else if( ~reg_busy[22]&®_mask[22] ) tx_phy_sel <= 32'b1<<22 ;
else if( ~reg_busy[23]&®_mask[23] ) tx_phy_sel <= 32'b1<<23 ;
else if( ~reg_busy[24]&®_mask[24] ) tx_phy_sel <= 32'b1<<24 ;
else if( ~reg_busy[25]&®_mask[25] ) tx_phy_sel <= 32'b1<<25 ;
else if( ~reg_busy[26]&®_mask[26] ) tx_phy_sel <= 32'b1<<26 ;
else if( ~reg_busy[27]&®_mask[27] ) tx_phy_sel <= 32'b1<<27 ;
else if( ~reg_busy[28]&®_mask[28] ) tx_phy_sel <= 32'b1<<28 ;
else if( ~reg_busy[29]&®_mask[29] ) tx_phy_sel <= 32'b1<<29 ;
else if( ~reg_busy[30]&®_mask[30] ) tx_phy_sel <= 32'b1<<30 ;
else if( ~reg_busy[31]&®_mask[31] ) tx_phy_sel <= 32'b1<<31 ;
`endif
else tx_phy_sel <= 32'b0 ;
end
end
endmodule
|
module phyInital (
input clk,reset,
input iniStart,
input [3:0]ram_read_addr,
input [31:0] command,
input [15:0]command_and,
inout md_inout,
output mdc,
output reg [3: 0] comm_addr,
output reg iniEnd,
output reg [12:0]stateout,
output [15:0]readDataoutRam,
output busy,
output WCtrlDataStartout
);
wire Busy;
wire WCtrlDataStart, RStatStart, UpdateMIIRX_DATAReg, Nvalid;
wire [15:0] writeData;
wire [15:0] readData;
wire [15:0] writeData_and;
assign busy = Busy;
assign WCtrlDataStartout = WCtrlDataStart;
//assign readDataout = readData;
reg save ;
reg [3:0]mi_addr;
always @ (posedge clk)
begin
if (reset) begin
mi_addr<= 4'b0;
end
else begin
if (save) begin
if (mi_addr < 4'b1110)
mi_addr <= mi_addr + 1'b1;
end
end
end
mi_data_ram mi_data_ram_ins(
.data_a(readData),
//.data_b,
.addr_a(mi_addr),
.addr_b(ram_read_addr),
.we_a(save),
.we_b(1'b0),
.clk(clk),
//.q_a,
.q_b(readDataoutRam)
);
wire [4:0] pyhAddr;
wire [4:0] regAddr;
wire writeOp;
assign writeOp = command[31];
assign pyhAddr = command[30:26];
assign regAddr = command[25:21];
assign writeData = command[15:0];
assign writeData_and = command_and;
wire [15: 0] ctrlData;
assign ctrlData = (readData | writeData) & writeData_and;
reg WCtrlData,RStat;
wire md_we, md_out,md_in;
assign md_inout = md_we? md_out:1'bz;
assign md_in = md_inout;
reg comm_addr_rst, comm_addr_en;
eth_miim eth_miim_ins (
.Clk(clk),
.Reset(reset),
.Divider(8'd50),
.NoPre(1'b0),
.CtrlData(ctrlData),
.Rgad(regAddr),
.Fiad(pyhAddr),
.WCtrlData(WCtrlData),
.RStat(RStat),
.ScanStat(1'b0),
.Mdi(md_in),
.Mdo(md_out),
.MdoEn(md_we),
.Mdc(mdc),
.Busy(Busy),
.Prsd(readData),
//.LinkFail(LEDG[1]),
.Nvalid(Nvalid),
.WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart),
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
);
always @ (posedge clk)
begin
if (comm_addr_rst) begin
comm_addr <= 4'b0;
end
else begin
if (comm_addr_en ) comm_addr <= comm_addr + 4'b1;
end
end
reg [3:0]state, next_state;
// Declare states
parameter s_rst = 0, s_ini = 1, s_read1 = 2, s_read2 = 3, s_wait= 4, s_write1 = 5 , s_write2 = 6, s_delay1=7, s_delay2=8, s_delay3=9 ;
// Determine the next state synchronously, based on the
// current state and the input
always @ (posedge clk ) begin
if (reset)
state <= s_rst;
else
state <= next_state;
end
// Determine the output based only on the current state
// and the input (do not wait for a clock edge).
always @ (state or iniStart or UpdateMIIRX_DATAReg or command or Busy or RStatStart or WCtrlDataStart)
begin
next_state = state;
WCtrlData = 1'b0;
RStat = 1'b0;
comm_addr_en = 0;
comm_addr_rst = 0;
stateout=0;
save = 0;
iniEnd = 0 ;
case (state)
s_rst:
begin
comm_addr_rst = 1;
if (iniStart) begin
next_state = s_ini;
end
else begin
next_state = s_rst;
end
end
s_ini:
begin
if ( |command & ~Busy) begin
next_state = s_read1; stateout=1;
end
else if ( ~(|command) & ~Busy) begin
next_state = s_ini;
iniEnd = 1;
end
else begin
next_state = s_ini; stateout=2;
end
end
s_read1:
begin
WCtrlData = 1'b0;
RStat = 1'b1;
if ( RStatStart ) begin
next_state = s_read2;stateout=4;
end
else begin
next_state = s_read1;stateout=8;
end
end
s_read2:
begin
WCtrlData = 1'b0;
RStat = 1'b1;
if (UpdateMIIRX_DATAReg) begin
next_state = s_wait;stateout=16;
save = 1;
end
else begin
next_state = s_read2;stateout=32;
end
end
s_wait:
begin
WCtrlData = 1'b0;
RStat = 1'b0;
if (~Busy) begin
next_state = s_write1;
end
else begin
next_state = s_wait;stateout=1024;
end
end
s_write1:
begin
WCtrlData = 1'b1;
RStat = 1'b0;
if ( WCtrlDataStart ) begin
next_state = s_write2; stateout=64;
end
else begin
next_state = s_write1;stateout=128;
end
end
s_write2:
begin
WCtrlData = 1'b0;
RStat = 1'b0;
if ( ~Busy ) begin
next_state = s_delay1;stateout=256;
comm_addr_en = 1;
end
else begin
next_state = s_write2;stateout=512;
end
end
s_delay1:
begin
next_state = s_delay2;
end
s_delay2:
begin
next_state = s_delay3;
end
s_delay3:
begin
next_state = s_ini;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A32O_BEHAVIORAL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long int n; cin >> n; long long int a[n]; map<long long int, long long int> mp; for (long long int i = 0; i < n; i++) { cin >> a[i]; mp[a[i]] = i; } long long int prev = mp[1]; long long int mx = 1; for (long long int i = 2; i <= n; i++) { if (mp[i] > mp[i - 1]) { long long int j = i; long long int cnt = 1; while (mp[j] > mp[j - 1]) { cnt++; j++; } mx = max(mx, cnt); i = j - 1; } } long long int ans = n - mx; cout << ans << n ; cerr << nTime elapsed: << 1000 * clock() / CLOCKS_PER_SEC << ms n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_8_V
`define SKY130_FD_SC_HD__BUFBUF_8_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__bufbuf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__bufbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_8_V
|
#include <bits/stdc++.h> using namespace std; int n, x, sum, ans, a; int main() { scanf( %d %d , &n, &x); for (int i = 0; i < n; i++) { scanf( %d , &a); sum += a; } sum = abs(sum); ans = (sum / x) + (sum % x != 0); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { map<char, long long> m; for (long long i = 0; i < 26; i++) { char ch; cin >> ch; m[ch] = i; } string str; cin >> str; long long ans = 0, sum = 0; for (long long i = 0; i < str.length() - 1; i++) { sum = abs(m[str[i]] - m[str[i + 1]]); ans += sum; } cout << ans << n ; return; } signed main() { ios_base::sync_with_stdio(false), cin.tie(NULL); long long t = 1; cin >> t; for (long long i = 0; i < t; i++) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > a[100500]; int d[100500]; int main() { int n, m, cap; scanf( %d%d%d , &n, &m, &cap); cap--; for (int i = 0; i < (m); i++) { int x, y, w; scanf( %d%d%d , &x, &y, &w); x--, y--; a[x].push_back(pair<int, int>(y, w)); a[y].push_back(pair<int, int>(x, w)); } int l; scanf( %d , &l); const int INF = 1100000000; for (int i = 0; i < (n); i++) d[i] = INF; d[cap] = 0; set<pair<int, int> > s; s.insert(pair<int, int>(d[cap], cap)); while (!s.empty()) { int v = s.begin()->second; s.erase(s.begin()); for (typeof((a[v]).begin()) it = (a[v]).begin(); it != (a[v]).end(); ++it) { int u = it->first; int w = it->second; if (d[u] >= INF || d[u] >= d[v] + w) { if (d[u] < INF) s.erase(s.find(pair<int, int>(d[u], u))); d[u] = d[v] + w; s.insert(pair<int, int>(d[u], u)); } } } int ans = 0; for (int i = 0; i < (n); i++) for (typeof((a[i]).begin()) it = (a[i]).begin(); it != (a[i]).end(); ++it) { int u = i; int v = it->first; int w = it->second; int x = d[v] - d[u] + w; assert(0 <= x && x <= w + w); if (0 < x && x < w + w) { if (d[u] < l && l + l <= 2 * d[u] + x) ans++; if (d[v] < l && l + l <= 2 * d[v] + w + w - x) ans++; if (l + l == 2 * d[u] + x && l + l == 2 * d[v] + w + w - x) ans--; } else { if (min(d[u], d[v]) < l && l < max(d[u], d[v])) ans++; } } ans >>= 1; for (int i = 0; i < (n); i++) ans += d[i] == l; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> _edge; set<int> se, to_del; int main() { ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(0); int t, n, m, i, j, k, x, y, z, a, b, c; cin >> t; while (t--) { cin >> n >> m; n *= 3; se.clear(); _edge.clear(); for (i = 1; i <= n; ++i) se.insert(i); for (i = 1; i <= m; ++i) { cin >> x >> y; if (se.find(x) != se.end() && se.find(y) != se.end()) { se.erase(x); se.erase(y); _edge.push_back(i); } } n = n / 3; if (_edge.size() >= n) { cout << Matching << endl; for (i = 0; i < _edge.size() && i < n; ++i) cout << _edge[i] << ; cout << endl; } else if (se.size() >= n) { cout << IndSet << endl; i = 0; for (auto it : se) { cout << it << ; i += 1; if (i == n) break; } cout << endl; } else cout << Impossible << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_0_V
`define SKY130_FD_SC_LP__CLKBUF_0_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuf_0 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuf_0 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_0_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR2_BEHAVIORAL_V
`define SKY130_FD_SC_MS__XOR2_BEHAVIORAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR2_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, od = 0, ev = 0, ans = 0; cin >> n; vector<int> vec; vector<int>::iterator it; while (n--) { cin >> a; vec.push_back(a); if (a % 2 == 0) ev++; else od++; } for (it = vec.begin(); it != vec.end(); it++) { if (ev > od) { if (*it % 2 != 0) ans = distance(vec.begin(), it); } else if (od > ev) { if (*it % 2 == 0) ans = distance(vec.begin(), it); } } cout << ans + 1; }
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_32_32x16_be.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1.30 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dpram_32_32x16_be (
data,
wren,
wraddress,
rdaddress,
byteena_a,
wrclock,
rdclock,
q);
input [31:0] data;
input wren;
input [3:0] wraddress;
input [3:0] rdaddress;
input [3:0] byteena_a;
input wrclock;
input rdclock;
output [31:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL wraddress[3..0]
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL rdaddress[3..0]
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC byteena_a[3..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be_wave*.jpg FALSE
|
#include <bits/stdc++.h> using namespace std; int n; int a[101101]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n); int l = 0, r = n - 1, ans = 0; for (int i = 0; i < n; i++) { if (a[l] < a[i]) { ans++; l++; } else r--; } printf( %d n , ans); return 0; }
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_eth_fcs_insert_64
*/
module test_axis_eth_fcs_insert_64_pad;
// Parameters
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] s_axis_tdata = 0;
reg [7:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [63:0] m_axis_tdata;
wire [7:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tuser,
busy
);
// dump file
$dumpfile("test_axis_eth_fcs_insert_64_pad.lxt");
$dumpvars(0, test_axis_eth_fcs_insert_64_pad);
end
axis_eth_fcs_insert_64 #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.busy(busy)
);
endmodule
|
/************************************************************************
fx3StateMachine.v
FX3 State-Machine module
Domesday Duplicator - LaserDisc RF sampler
Copyright (C) 2018 Simon Inns
This file is part of Domesday Duplicator.
Domesday Duplicator is free software: you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation, either version 3 of the
License, or (at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Email:
************************************************************************/
module fx3StateMachine (
input nReset,
input fx3_clock,
input readData,
output fx3isReading
);
// State machine logic ---------------------------------------------------
// State machine state definitions (4-bit 0-15)
reg [3:0]sm_currentState;
reg [3:0]sm_nextState;
parameter [3:0] state_waitForRequest = 4'd01;
parameter [3:0] state_sendPacket = 4'd02;
// Set state to state_idle on reset - or assign the next state
always @(posedge fx3_clock, negedge nReset) begin
if(!nReset) begin
sm_currentState <= state_waitForRequest;
end else begin
sm_currentState <= sm_nextState;
end
end
// Ensure that the readData signal is only read
// on the FX3 clock edge
reg readData_flag;
always @(posedge fx3_clock, negedge nReset) begin
if(!nReset) begin
readData_flag <= 1'b0;
end else begin
readData_flag <= readData;
end
end
// Counter for the sendPacket state
// Here we should send 8192 words to the FX3
reg [15:0] wordCounter;
always @(posedge fx3_clock, negedge nReset) begin
if (!nReset) begin
wordCounter = 16'd0;
end else begin
if (sm_currentState == state_sendPacket) begin
wordCounter = wordCounter + 16'd1;
end else begin
wordCounter = 16'd0;
end
end
end
// Generate fx3isReading flag
assign fx3isReading = (sm_currentState == state_sendPacket) ? 1'b1 : 1'b0;
// State machine transition logic
always @(*)begin
sm_nextState = sm_currentState;
case(sm_currentState)
// state_waitForRequest (waits for the FX3 to request a packet)
state_waitForRequest:begin
// Is the GPIF reading data?
if (readData_flag == 1'b1 && wordCounter == 16'd0) begin
sm_nextState = state_sendPacket;
end else begin
// GPIF not ready... wait
sm_nextState = state_waitForRequest;
end
end
// state_sendPacket (sends a packet of 8192 words to the FX3)
state_sendPacket:begin
if (wordCounter == 16'd8191) begin
// Packet send, go back to waiting
sm_nextState = state_waitForRequest;
end else begin
// Continue sending packet
sm_nextState = state_sendPacket;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int shape[4][4][2] = {{{1, 0}, {2, 0}, {1, 1}, {1, 2}}, {{1, 0}, {2, 0}, {2, -1}, {2, 1}}, {{0, 1}, {0, 2}, {-1, 2}, {1, 2}}, {{0, 1}, {0, 2}, {1, 1}, {2, 1}}}; int x, y; struct node { char g[9][9]; int num; int sx, sy; int layer; node() { layer = 0; sx = sy = 0; memset(g, 0, sizeof(g)); num = 0; } void printNode() { for (int i = 0; i < y; i++) { for (int j = 0; j < x; j++) printf( %c , g[i][j] ? g[i][j] : . ); cout << << endl; } } }; stack<node> q; int ans; node ansNode; int maxG[9][9][4]; void bfs() { while (!q.empty()) { node now = q.top(); q.pop(); if (now.num > ans) { ans = now.num; ansNode = now; } now.num++; char ch = A + now.num - 1; for (int i = now.sy; i < y; i++) { for (int j = 0; j < x; j++) { if (!now.g[i][j]) { for (int k = 0; k < 4; k++) { if (maxG[i][j][k] > now.num + 1) continue; bool flag = true; for (int l = 0; l < 4 && flag; l++) { int tx = j + shape[k][l][1]; int ty = i + shape[k][l][0]; if (tx < 0 || tx >= x || ty < 0 || ty >= y || now.g[ty][tx]) { flag = false; } } if (flag) { node tNode = now; tNode.g[i][j] = ch; for (int l = 0; l < 4; l++) { int tx = j + shape[k][l][1]; int ty = i + shape[k][l][0]; tNode.g[ty][tx] = ch; } tNode.sx = j + 1; tNode.sy = i; tNode.layer++; q.push(tNode); maxG[i][j][k] = max(maxG[i][j][k], now.num); } } } } } } } int main() { ans = -1; cin >> y >> x; while (!q.empty()) q.pop(); q.push(node()); bfs(); cout << ans << endl; ansNode.printNode(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; pair<long long, long long> res; long long a[N]; void dfs(long long cur, long long cnt, long long sum) { if (!cur) { res = max(res, {cnt, sum}); return; } else { int p = upper_bound(a + 1, a + N, cur) - a; --p; dfs(cur - a[p], cnt + 1, sum + a[p]); if (p > 1) dfs(a[p] - 1 - a[p - 1], cnt + 1, sum + a[p - 1]); } } int main() { for (int i = 1; i <= N - 1; ++i) a[i] = 1ll * i * i * i; long long m; scanf( %lld , &m); dfs(m, 0, 0); printf( %lld %lld n , res.first, res.second); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 2e5 + 15; inline long long read() { long long x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 1) + (x << 3) + c - 0 ; c = getchar(); } return x * f; } long long T, n, tot, last, len[maxn], size[maxn], link[maxn], nxt[maxn][30]; inline long long extend(long long last, long long x) { long long now = ++tot, pos = last, tmp, cln; len[now] = len[pos] + 1; size[now]++; while (pos != 0 && nxt[pos][x] == 0) nxt[pos][x] = now, pos = link[pos]; if (!pos) { link[now] = 1; return now; } tmp = nxt[pos][x]; if (len[tmp] == len[pos] + 1) { link[now] = tmp; return now; } cln = ++tot; len[cln] = len[pos] + 1; for (long long i = 1; i <= 26; i++) nxt[cln][i] = nxt[tmp][i]; link[cln] = link[tmp]; link[tmp] = link[now] = cln; while (pos != 0 && nxt[pos][x] == tmp) nxt[pos][x] = cln, pos = link[pos]; return now; } string s; long long beg[maxn], nex[maxn], to[maxn], e; inline void add(long long x, long long y) { e++; nex[e] = beg[x]; beg[x] = e; to[e] = y; } long long val[maxn], k; inline void dfs(long long x) { for (long long i = beg[x]; i; i = nex[i]) dfs(to[i]), size[x] += size[to[i]]; val[size[x]] += (len[x] - len[link[x]]); } inline void pre() { for (long long i = 0; i <= tot; i++) { val[i] = beg[i] = len[i] = size[i] = link[i] = 0; for (long long j = 1; j <= 26; j++) nxt[i][j] = 0; } e = tot = 0; } signed main() { T = read(); while (T--) { pre(); cin >> s; n = s.size(); s = + s; last = ++tot; for (long long i = 1; i <= n; i++) last = extend(last, s[i] - 96); for (long long i = 2; i <= tot; i++) add(link[i], i); dfs(1); long long ans = 0; for (long long i = n; i >= 1; i--) ans += val[i] * i * i; printf( %lld n , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_SYMBOL_V
`define SKY130_FD_SC_HS__AND3B_SYMBOL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and3b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/29/2016 05:57:16 AM
// Design Name:
// Module Name: Testbench_FPU_Add_Subt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_FPU_Add_Subt();
parameter PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;//
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk;
//INPUT signals
reg rst;
reg beg_FSM;
reg ack_FSM;
//Oper_Start_in signals
reg [W-1:0] Data_X;
reg [W-1:0] Data_Y;
reg add_subt;
//Round signals signals
reg [1:0] r_mode;
//OUTPUT SIGNALS
wire overflow_flag;
wire underflow_flag;
wire ready;
wire [W-1:0] final_result_ieee;
`ifdef SINGLE
FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5 uut(
.clk(clk),
.rst(rst),
.beg_FSM(beg_FSM),
.ack_FSM(ack_FSM),
.Data_X(Data_X),
.Data_Y(Data_Y),
.add_subt(add_subt),
.r_mode(r_mode),
.overflow_flag(overflow_flag),
.underflow_flag(underflow_flag),
.ready(ready),
.final_result_ieee(final_result_ieee)
);
`endif
`ifdef DOUBLE
FPU_Add_Subtract_Function_W64_EW11_SW52_SWR55_EWR6 uut(
.clk(clk),
.rst(rst),
.beg_FSM(beg_FSM),
.ack_FSM(ack_FSM),
.Data_X(Data_X),
.Data_Y(Data_Y),
.add_subt(add_subt),
.r_mode(r_mode),
.overflow_flag(overflow_flag),
.underflow_flag(underflow_flag),
.ready(ready),
.final_result_ieee(final_result_ieee)
);
`endif
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
beg_FSM = 0;
ack_FSM = 0;
Data_X = 0;
Data_Y = 0;
r_mode = 2'b00;
add_subt = 0;
// // Wait 100 ns for global reset to finish
// #100 rst = 0;
//Abre el archivo testbench
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
Recept = 1;
// Wait 100 ns for global reset to finish
#100 rst = 0;
//Add stimulus here
end
//**************************** Se lee el archivo txt y se almacena en un arrays***************************************************//
initial begin
$readmemh("Hexadecimal_A.txt", Array_IN);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
end
//**************************** Transmision de datos de forma paralela ************************************************************//
always @(posedge clk) begin
if(rst) begin
contador = 0;
Cont_CLK = 0;
end
else begin
if (contador == (2**PERIOD)) begin
$fclose(FileSaveData);
$finish;
end
else begin
if(Cont_CLK ==1) begin
contador = contador + 1;
beg_FSM = 0;
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
Cont_CLK = Cont_CLK + 1;
ack_FSM = 0;
end
else if(Cont_CLK ==2) begin
ack_FSM = 0;
beg_FSM = 1;
Cont_CLK = Cont_CLK +1 ;
end
else begin
ack_FSM = 0;
Cont_CLK = Cont_CLK + 1;
beg_FSM = 0;
end
if(ready==1) begin
ack_FSM = 1;
Cont_CLK = 0;
end
if(ready==1 && ack_FSM) begin
Cont_CLK = 0;
end
end
end
end
// Recepción de datos y almacenamiento en archivo*************
always @(posedge clk) begin
if(ready) begin
if(Recept == 1) begin
$fwrite(FileSaveData,"%h\n",final_result_ieee);
Recept = 0;
end
end
else begin
Recept = 1;
end
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
//initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/19/2016 08:12:53 AM
// Design Name:
// Module Name: D_Register
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module D_Register (
input [7:0] D,
input CLK,
input ARST,
input SRST,
output [7:0] Q
);
DFF_Slice Bit0 (
.D(D[0]),
.Clk(CLK),
.ARst(ARST),
.SRst(SRST),
.Q(Q[0])
);
DFF_Slice Bit1 (
.D(D[1]),
.Clk(CLK),
.ARst(ARST),
.SRst(SRST),
.Q(Q[1])
);
DFF_Slice Bit2 (
.D(D[2]),
.Clk(CLK),
.ARst(ARST),
.SRst(SRST),
.Q(Q[2])
);
DFF_Slice Bit3 (
.D(D[3]),
.Clk(CLK),
.ARst(ARST),
.SRst(SRST),
.Q(Q[3])
);
DFF_Slice Bit4 (
.D(D[4]),
.Clk(CLK),
.ARst(ARST),
.SRst(SRST),
.Q(Q[4])
);
DFF_Slice Bit5 (
.D(D[5]),
.Clk(CLK),
.ARst(ARST),
.SRst(SRST),
.Q(Q[5])
);
DFF_Slice Bit6 (
.D(D[6]),
.Clk(CLK),
.ARst(ARST),
.SRst(SRST),
.Q(Q[6])
);
DFF_Slice Bit7 (
.D(D[7]),
.Clk(CLK),
.ARst(ARST),
.SRst(SRST),
.Q(Q[7])
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int a, b; cin >> a >> b; int c = 2 * min(a, b); int d = max(a, b); if (c > max(a, b)) { cout << c * c << endl; } else { cout << d * d << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<int, int>; using i3 = pair<int, ii>; using li = pair<ll, int>; using lii = pair<ll, ii>; using vi = vector<int>; using vl = vector<ll>; using vli = vector<li>; using vii = vector<ii>; using vi3 = vector<i3>; using vlii = vector<lii>; const int N = 1e5 + 5; const int INF = 1e9 + 7; const double eps = 1e-12, PI = acos(-1); int n, m; char s[N]; int mem[N][5]; int dp(int i, int rem) { if (i == n) { return rem == 0 ? 0 : INF; } int &ret = mem[i][rem]; if (ret != -1) return ret; return ret = min(1 + dp(i + 1, rem), dp(i + 1, (rem * 10 + int(s[i] - 0 )) % 3)); } vi ans; void path(int i, int rem) { if (i == n) return; if (dp(i + 1, (rem * 10 + int(s[i] - 0 )) % 3) == dp(i, rem)) { ans.push_back(s[i] - 0 ); path(i + 1, (rem * 10 + int(s[i] - 0 )) % 3); return; } path(i + 1, rem); } void solve(int cs) { scanf( %s , s); n = strlen(s); int mn = INF, idx = INF; bool isZero = 0; memset(mem, -1, sizeof mem); for (int i = 0; s[i]; i++) { if (s[i] == 0 ) { isZero = 1; continue; } int curr = dp(i + 1, int(s[i] - 0 ) % 3) + i; if (curr < mn) { mn = curr; idx = i; } } if (idx == INF) { printf( %d n , isZero ? 0 : -1); return; } path(idx + 1, int(s[idx] - 0 ) % 3); printf( %c , s[idx]); for (int A : ans) printf( %d , A); printf( n ); } int main() { int t = 1; for (int cs = 1; t--; cs++) { solve(cs); } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct node { int l, r, x, y; }; vector<node> p[500010]; int a[500010], b[500010], c[500010]; int main() { int i, j, k, n, m, s; node e; scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) scanf( %d , &a[i]); b[0] = 0; for (i = 1; i <= n + 1; i++) { b[i] = b[i - 1]; if (a[i] == m) b[i]++; } a[n + 1] = 0; j = 0; k = 0; for (i = 1; i <= n + 1; i++) { if (a[i] == a[i - 1]) k++; else { e.l = j; e.r = k; e.x = k - j + 1; p[a[i - 1]].push_back(e); j = i; k = i; } } s = 0; for (i = 1; i <= 500010 - 10; i++) { k = p[i].size(); if (k == 0) continue; e.l = n + 1; e.r = n + 1; e.x = 0; p[i].push_back(e); p[i][0].y = p[i][0].x + b[n] - b[p[i][0].r] + b[p[i][0].l - 1]; s = max(s, p[i][0].y); c[p[i][0].l] = b[p[i][0].l - 1] + p[i][0].x; for (j = 1; j < k; j++) { p[i][j].y = p[i][j].x + max(c[p[i][j - 1].l], b[p[i][j].l - 1]) + b[n] - b[p[i][j].r]; s = max(s, p[i][j].y); c[p[i][j].l] = max(c[p[i][j - 1].l] + p[i][j].x, p[i][j].x + b[p[i][j].l - 1]); } } printf( %d n , s); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int B = 31; const int N = 107; int a[N]; bool vis[1000007]; map<int, int> state; map<int, int> sgn; int tc = -1; inline int grrr(int mask) { if (mask < 2) return 0; auto it = sgn.find(mask); if (it != sgn.end()) return it->second; vector<int> to_clear; for (int i = 1; i < B; ++i) { int small = (mask & ((1 << i) - 1)); int large = (mask >> i); int nmask = (small | large); if (nmask == mask) continue; int val = grrr(nmask); to_clear.push_back(val); } for (int x : to_clear) vis[x] = true; int ret = 0; while (vis[ret]) ++ret; for (int x : to_clear) vis[x] = false; return sgn[mask] = ret; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) { int x = a[i]; for (int k = 2; k * k <= x; ++k) { int cnt = 0; while (x % k == 0) { x /= k; ++cnt; } if (cnt) state[k] |= (1 << cnt); } if (x > 1) state[x] |= 2; } int res = 0; for (auto &qq : state) { res ^= grrr(qq.second); } cout << (res ? Mojtaba : Arpa ) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) const long long INFll = 1e18; const int INFint = 1e9; const long long MOD = 1e9 + 7; void needForSpeed() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } bool isPrime(long long a) { if (a < 2) return 0; for (long long i = 2; i <= sqrt(a); i++) if (a % i == 0) return 0; return 1; } long long binpow(long long base, long long pow, long long mod = INFll) { if (pow == 0) return 1; else if (pow % 2) return base * binpow(base, pow - 1, mod) % mod; else { long long p = binpow(base, pow / 2LL, mod); return p * p % mod; } } template <class T> void PR_VEC(const vector<T> &vec) { cout << size( << vec.size() << ):[ ; if (vec.size() == 0) { cout << !EMPTY! ] n ; return; } cout << vec[0] << ; for (int i = 1; i < vec.size(); ++i) cout << , << vec[i] << ; cout << ] n ; } int solve() { long long n, m, ans; cin >> n >> m; string s; cin >> s; ans = n * (m - 1LL); for (int i = 1; i < n; ++i) { if (s[i] != s[i - 1]) ans += n * (m - 1LL); } int len = 1; for (int i = 1; i < n; ++i) { if (len == 1) { if (s[i] != s[i - 1]) { len = 2; } else { continue; } } else { if (s[i] != s[i - 2]) { ans -= (len * (len - 1LL)) / 2LL; if (s[i] == s[i - 1]) len = 1; else len = 2; } else { ++len; } } } ans -= (len * (len - 1LL)) / 2LL; cout << ans; return 0; } int main() { needForSpeed(); int tests = 1; while (tests--) { solve(); } return 0; }
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_AVMM_CSR_CONTROLLER
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_avmm_csr_controller (
// To/From System
clock,
reset_n,
// To/From Avalon_MM csr slave interface
avmm_read,
avmm_write,
avmm_addr,
avmm_writedata,
avmm_readdata,
// To/From Avalon_MM data slave interface
csr_status,
csr_control
);
parameter AVMM_CSR_DATA_WIDTH = 32;
localparam [1:0] ERASE_ST_IDLE = 0,
ERASE_ST_PENDING = 1,
ERASE_ST_BUSY = 2;
localparam [1:0] STATUS_IDLE = 0,
STATUS_BUSY_ERASE = 1,
STATUS_BUSY_WRITE = 2,
STATUS_BUSY_READ = 3;
// To/From System
input clock;
input reset_n;
// To/From Avalon_MM csr slave interface
input avmm_read;
input avmm_write;
input avmm_addr;
input [AVMM_CSR_DATA_WIDTH-1:0] avmm_writedata;
output [AVMM_CSR_DATA_WIDTH-1:0] avmm_readdata;
// To/From Avalon_MM data slave interface
input [9:0] csr_status;
output [31:0] csr_control;
reg [22:0] csr_sector_page_erase_addr_reg;
reg [4:0] csr_wp_mode;
reg [1:0] csr_erase_state;
reg csr_control_access;
reg reset_n_reg1;
reg reset_n_reg2;
wire reset_n_w;
wire is_idle;
wire is_erase_busy;
wire valid_csr_erase_addr;
wire valid_csr_write;
wire [31:0] csr_control_signal;
wire [22:0] csr_erase_addr;
assign is_idle = (csr_status[1:0] == STATUS_IDLE);
assign is_erase_busy = (csr_status[1:0] == STATUS_BUSY_ERASE);
assign csr_erase_addr = avmm_writedata[22:0];
assign valid_csr_erase_addr = (csr_erase_addr != {(23){1'b1}});
assign valid_csr_write = (avmm_write & avmm_addr);
assign csr_control_signal = { csr_erase_state, {(2){1'b1}}, csr_wp_mode, csr_sector_page_erase_addr_reg };
assign csr_control = csr_control_signal;
assign avmm_readdata = (csr_control_access) ? csr_control_signal : { {(22){1'b1}}, csr_status[9:0] };
// avoid async reset removal issue
assign reset_n_w = reset_n_reg2;
// Initiate register value for simulation. The initiate value can't be xx
initial begin
csr_sector_page_erase_addr_reg <= {(23){1'b1}};
csr_wp_mode = {(5){1'b1}};
csr_erase_state = ERASE_ST_IDLE;
csr_control_access = 1'b0;
reset_n_reg1 = 1'b0;
reset_n_reg2 = 1'b0;
end
// -------------------------------------------------------------------
// Avoid async reset removal issue
// -------------------------------------------------------------------
always @ (negedge reset_n or posedge clock) begin
if (~reset_n) begin
{reset_n_reg2, reset_n_reg1} <= 2'b0;
end
else begin
{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
end
end
// -------------------------------------------------------------------
// Avalon_MM read/write
// -------------------------------------------------------------------
always @ (posedge clock) begin
// synchronous reset
if (~reset_n_w) begin
// reset all register
csr_sector_page_erase_addr_reg <= {(23){1'b1}};
csr_wp_mode <= {(5){1'b1}};
csr_erase_state <= ERASE_ST_IDLE;
csr_control_access <= 1'b0;
end
else begin
// store read address
if (avmm_read) begin
csr_control_access <= avmm_addr;
end
// write control register
if (valid_csr_write) begin
csr_wp_mode <= avmm_writedata[27:23];
if (is_idle) begin
csr_sector_page_erase_addr_reg <= avmm_writedata[22:0];
end
end
// erase control fsm
case (csr_erase_state)
ERASE_ST_IDLE:
if (is_idle && valid_csr_write && valid_csr_erase_addr) begin
csr_erase_state <= ERASE_ST_PENDING;
end
ERASE_ST_PENDING:
if (is_erase_busy) begin
csr_erase_state <= ERASE_ST_BUSY;
end
ERASE_ST_BUSY:
if (is_idle) begin
csr_erase_state <= ERASE_ST_IDLE;
end
default: begin
csr_erase_state <= ERASE_ST_IDLE;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &x) { x = 0; char c = getchar(); T sig = 1; for (; !isdigit(c); c = getchar()) if (c == - ) sig = -1; for (; isdigit(c); c = getchar()) x = (x << 3) + (x << 1) + c - 0 ; x *= sig; } class Solution { public: void solve() { int n; read(n); set<pair<int, int>> s; for (int i = 0; i < n; ++i) { string t; cin >> t; int b = 0; for (char c : t) b += c == B ; s.insert({b, t.size() - b}); }; vector<pair<int, int>> vs(s.begin(), s.end()); auto check = [&](int l, bool output) { int xl = 0, xr = 5e5, yl = 0, yr = 5e5, zl = -5e5, zr = 5e5; for (auto p : vs) { xl = max(xl, p.first - l); xr = min(xr, p.first + l); yl = max(yl, p.second - l); yr = min(yr, p.second + l); zl = max(zl, p.first - p.second - l); zr = min(zr, p.first - p.second + l); } if (xl > xr || yl > yr || zl > zr) return false; int zl1 = xl - yr, zr1 = xr - yl; if (output) { int x = min(xr, zr + yr); int y = min(yr, x - zl); string s(x, B ), t(y, N ); printf( %s , (s + t).c_str()); } return max(zl, zl1) <= min(zr, zr1); }; int lo = 0, hi = 1e6; while (lo <= hi) { int mid = (lo + hi) >> 1; if (check(mid, false)) hi = mid - 1; else lo = mid + 1; } printf( %d n , lo); check(lo, true); } }; int main() { Solution solution = Solution(); solution.solve(); }
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#include <bits/stdc++.h> const bool debugging = 1; const long long mod = 1e9 + 7; using namespace std; template <class T> ostream &operator<<(ostream &os, vector<T> V) { for (auto v : V) { os << v << ; } return os << ; } template <class T> ostream &operator<<(ostream &os, vector<vector<T>> V) { for (long long i = 0; i < V.size(); i++) { for (long long j = 0; j < V[i].size(); j++) { os << V[i][j] << ; } os << n ; } return os << ; } template <class T> ostream &operator<<(ostream &os, set<T> S) { for (auto s : S) { os << s << ; } return os << ; } template <class L, class R> ostream &operator<<(ostream &os, pair<L, R> P) { return os << P.first << << P.second; } template <class L, class R> ostream &operator<<(ostream &os, map<L, R> M) { os << n ; for (auto m : M) { os << m << n ; } return os << ; } void solve() { long long N; cin >> N; vector<long long> elements(N); for (long long i = 0; i < N; i++) { cin >> elements[i]; } vector<long long> max_val(N); long long contri_front = elements[0]; long long contri_end = 0; long long index = N; bool single = 1; for (long long i = 0; i < N; i++) { if (contri_front >= elements[i] && single) { contri_front = elements[i]; elements[i] = 0; } else { single = 0; long long need_from_end = elements[i] - contri_front; if (need_from_end > elements[N - 1]) { cout << NO << n ; return; } if (need_from_end < contri_end) { contri_front = elements[i] - contri_end; if (contri_front < 0) { cout << NO << n ; return; } } else { contri_end = need_from_end; } } } cout << YES << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long no_of_testcases; cin >> no_of_testcases; while (no_of_testcases-- > 0) { solve(); } return 0; }
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#include <bits/stdc++.h> int n, m, f, c[150005], p, a, b; long long A; struct odp { long long L, M, R, S; odp() {} odp(long long L, long long M, long long R, long long S) : L(L), M(M), R(R), S(S) {} } t[150005 * 4]; void init(int n, int l, int r) { if (l == r) t[n].L = t[n].R = t[n].M = ((t[n].S = c[l]) > (0) ? (t[n].S = c[l]) : (0)); else { int L = n * 2, R = L + 1, c = l + r >> 1; init(L, l, c); init(R, c + 1, r); t[n].S = t[L].S + t[R].S; t[n].L = ((t[L].L) > (t[L].S + t[R].L) ? (t[L].L) : (t[L].S + t[R].L)); t[n].R = ((t[R].R) > (t[L].R + t[R].S) ? (t[R].R) : (t[L].R + t[R].S)); t[n].M = ((t[L].M) > (((t[R].M) > (t[L].R + t[R].L) ? (t[R].M) : (t[L].R + t[R].L))) ? (t[L].M) : (((t[R].M) > (t[L].R + t[R].L) ? (t[R].M) : (t[L].R + t[R].L)))); } } odp q(int n, int l, int r) { if (l >= a && r <= b) return odp(t[n].L, t[n].M, t[n].R, t[n].S); int c = l + r >> 1; if (c >= b) return q(n * 2, l, c); if (c < a) return q(n * 2 + 1, c + 1, r); odp L = q(n * 2, l, c), R = q(n * 2 + 1, c + 1, r); return odp(((L.L) > (L.S + R.L) ? (L.L) : (L.S + R.L)), ((L.M) > (((R.M) > (L.R + R.L) ? (R.M) : (L.R + R.L))) ? (L.M) : (((R.M) > (L.R + R.L) ? (R.M) : (L.R + R.L)))), ((R.R) > (L.R + R.S) ? (R.R) : (L.R + R.S)), L.S + R.S); } int main() { scanf( %d %d %d , &n, &m, &f); for (int i = 1; i <= n; i++) scanf( %d , &c[i]), c[i - 1] = (c[i] - c[i - 1]) * 50; for (int i = 1; i < n; i++) scanf( %d , &p), c[i] -= p * f; init(1, 1, n - 1); while (m--) { scanf( %d %d , &a, &b); b--; A += q(1, 1, n - 1).M; } printf( %.8lf n , A * 0.01); }
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////////////////////////////////////////////////////////////////////////////////////////////////////
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
// 02111-1307, USA.
//
// ©2013 - Roman Ovseitsev <>
////////////////////////////////////////////////////////////////////////////////////////////////////
//##################################################################################################
//
// Register configuration for OV7670 camera module.
// Initializes RGB565 VGA, with distorted colors... I yet to find the register settings to fix this.
//
//
// Calculating required clock frequency. 30fps RGB565 VGA:
//
// HREF = tLINE = 640*tP + 144*tP = 784*tP
// VSYNC = 510 * tLINE = 510 * 784*tP
// PCLK = VSYNC * FPS * BYTES_PER_PIXEL = 784 * 510 * 30 * 2 = 23990400 ~= 24MHz
//
//##################################################################################################
`timescale 1ns / 1ps
module OV7670Init (index_i, data_o);
input [5:0] index_i; // Register index.
output reg [16:0] data_o; // {Register_address, register_value, rw_flag} :
// Where register_value is the value to write if rw_flag = 1
// otherwise it's not used when rw_flag = 0 (read).
// {16'hffff, 1'b1} - denotes end of the register set.
// {16'hf0f0, 1'b1} - denotes that a delay is needed at this point.
always @* begin
(* parallel_case *) case(index_i)
//6'd0 : data_o = {16'h0A76, 1'b0};
6'd0 : data_o = {16'h1280, 1'b1}; // COM7 Reset.
6'd1 : data_o = {16'hf0f0, 1'b1}; // Denotes delay.
6'd2 : data_o = {16'h1204, 1'b1}; // COM7 Set RGB (06 enables color bar overlay).
6'd3 : data_o = {16'h1100, 1'b1}; // CLKRC Use external clock directly.
6'd4 : data_o = {16'h0C00, 1'b1}; // COM3 Disable DCW & scalling. + RSVD bits.
6'd5 : data_o = {16'h3E00, 1'b1}; // COM14 Normal PCLK.
6'd6 : data_o = {16'h8C00, 1'b1}; // RGB444 Disable RGB444
6'd7 : data_o = {16'h0400, 1'b1}; // COM1 Disable CCIR656. AEC low 2 LSB.
6'd8 : data_o = {16'h40d0, 1'b1}; // COM15 Set RGB565 full value range
6'd9 : data_o = {16'h3a04, 1'b1}; // TSLB Don't set window automatically. + RSVD bits.
6'd10: data_o = {16'h1418, 1'b1}; // COM9 Maximum AGC value x4. Freeze AGC/AEC. + RSVD bits.
6'd11: data_o = {16'h4fb3, 1'b1}; // MTX1 Matrix Coefficient 1
6'd12: data_o = {16'h50b3, 1'b1}; // MTX2 Matrix Coefficient 2
6'd13: data_o = {16'h5100, 1'b1}; // MTX3 Matrix Coefficient 3
6'd14: data_o = {16'h523d, 1'b1}; // MTX4 Matrix Coefficient 4
6'd15: data_o = {16'h53a7, 1'b1}; // MTX5 Matrix Coefficient 5
6'd16: data_o = {16'h54e4, 1'b1}; // MTX6 Matrix Coefficient 6
6'd17: data_o = {16'h589e, 1'b1}; // MTXS Enable auto contrast center. Matrix coefficient sign. + RSVD bits.
6'd18: data_o = {16'h3dc0, 1'b1}; // COM13 Gamma enable. + RSVD bits.
6'd19: data_o = {16'h1100, 1'b1}; // CLKRC Use external clock directly.
6'd20: data_o = {16'h1714, 1'b1}; // HSTART HREF start high 8 bits.
6'd21: data_o = {16'h1802, 1'b1}; // HSTOP HREF stop high 8 bits.
6'd22: data_o = {16'h3280, 1'b1}; // HREF HREF edge offset. HSTART/HSTOP low 3 bits.
6'd23: data_o = {16'h1903, 1'b1}; // VSTART VSYNC start high 8 bits.
6'd24: data_o = {16'h1A7b, 1'b1}; // VSTOP VSYNC stop high 8 bits.
6'd25: data_o = {16'h030a, 1'b1}; // VREF VSYNC edge offset. VSTART/VSTOP low 3 bits.
6'd26: data_o = {16'h0f41, 1'b1}; // COM6 Disable HREF at optical black. Reset timings. + RSVD bits.
6'd27: data_o = {16'h1e03, 1'b1}; // MVFP No mirror/vflip. Black sun disable. + RSVD bits.
6'd28: data_o = {16'h330b, 1'b1}; // CHLF Array Current Control - Reserved
//6'd29: data_o = {16'h373f, 1'b1}; // ADC
//6'd30: data_o = {16'h3871, 1'b1}; // ACOM ADC and Analog Common Mode Control - Reserved
//6'd31: data_o = {16'h392a, 1'b1}; // OFON ADC Offset Control - Reserved
6'd29: data_o = {16'h3c78, 1'b1}; // COM12 No HREF when VSYNC is low. + RSVD bits.
6'd30: data_o = {16'h6900, 1'b1}; // GFIX Fix Gain Control? No.
6'd31: data_o = {16'h6b1a, 1'b1}; // DBLV Bypass PLL. Enable internal regulator. + RSVD bits.
6'd32: data_o = {16'h7400, 1'b1}; // REG74 Digital gain controlled by VREF[7:6]. + RSVD bits.
6'd33: data_o = {16'hb084, 1'b1}; // RSVD ?
6'd34: data_o = {16'hb10c, 1'b1}; // ABLC1 Enable ABLC function. + RSVD bits.
6'd35: data_o = {16'hb20e, 1'b1}; // RSVD ?
6'd36: data_o = {16'hb380, 1'b1}; // THL_ST ABLC Target.
/*6'd37: data_o = {16'h7a20, 1'b1}; // SLOP Gamma Curve Highest Segment Slope
6'd38: data_o = {16'h7b10, 1'b1}; // GAM1
6'd39: data_o = {16'h7c1e, 1'b1}; // GAM2
6'd40: data_o = {16'h7d35, 1'b1}; // GAM3
6'd41: data_o = {16'h7e5a, 1'b1}; // GAM4
6'd42: data_o = {16'h7f69, 1'b1}; // GAM5
6'd43: data_o = {16'h8076, 1'b1}; // GAM6
6'd44: data_o = {16'h8180, 1'b1}; // GAM7
6'd45: data_o = {16'h8288, 1'b1}; // GAM8
6'd46: data_o = {16'h838f, 1'b1}; // GAM9
6'd47: data_o = {16'h8496, 1'b1}; // GAM10
6'd48: data_o = {16'h85a3, 1'b1}; // GAM11
6'd49: data_o = {16'h86af, 1'b1}; // GAM12
6'd50: data_o = {16'h87c4, 1'b1}; // GAM13
6'd51: data_o = {16'h88d7, 1'b1}; // GAM14
6'd52: data_o = {16'h89e8, 1'b1}; // GAM15*/
default: data_o = {16'hffff, 1'b1};
endcase
end
endmodule
|
module BigSDRAM(clock0,clock180,clock270,reset,leds,ddr_clock0,ddr_clock90,ddr_clock270,ddr_cke,ddr_csn,ddr_rasn,ddr_casn,ddr_wen,ddr_ba,ddr_addr,ddr_dm,ddr_dq,ddr_dqs);
input wire clock0;
input wire clock180;
input wire clock270;
input wire reset;
output wire [7:0] leds;
input wire ddr_clock0;
input wire ddr_clock90;
input wire ddr_clock270;
output wire ddr_cke;
output wire ddr_csn;
output wire ddr_rasn;
output wire ddr_casn;
output wire ddr_wen;
output wire [1:0] ddr_ba;
output wire [12:0] ddr_addr;
output wire [1:0] ddr_dm;
inout wire [15:0] ddr_dq;
inout wire [1:0] ddr_dqs;
wire [7:0] seq_next;
wire [11:0] seq_oreg;
wire [7:0] seq_oreg_wen;
wire [19:0] coderom_data_o;
wire [4095:0] coderomtext_data_o;
wire [31:0] ddrctl_page;
wire ddrctl_ready;
wire swc_ready;
Seq
seq (.clock(clock0),
.reset(reset),
.inst(coderom_data_o),
.inst_text(coderomtext_data_o),
.inst_en(1),
.ireg_0(ddrctl_page[7:0]),
.ireg_1({7'h00,ddrctl_ready}),
.ireg_2({7'h00,swc_ready}),
.ireg_3(8'h00),
.next(seq_next),
.oreg(seq_oreg),
.oreg_wen(seq_oreg_wen));
BigSDRAMRom
coderom (.addr(seq_next),
.data_o(coderom_data_o));
`ifdef SIM
BigSDRAMRomText
coderomtext (.addr(seq_next),
.data_o(coderomtext_data_o));
`endif
DdrCtl1
ddrctl (.clock0(clock180),
.clock90(clock270),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[0]),
.page(ddrctl_page),
.ready(ddrctl_ready),
.ddr_clock0(ddr_clock0),
.ddr_clock90(ddr_clock90),
.ddr_clock270(ddr_clock270),
.ddr_cke(ddr_cke),
.ddr_csn(ddr_csn),
.ddr_rasn(ddr_rasn),
.ddr_casn(ddr_casn),
.ddr_wen(ddr_wen),
.ddr_ba(ddr_ba),
.ddr_addr(ddr_addr),
.ddr_dm(ddr_dm),
.ddr_dq(ddr_dq),
.ddr_dqs(ddr_dqs));
LedBank
ledbank (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[1]),
.leds(leds));
Swc
swc (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[2]),
.ready(swc_ready));
endmodule // BigSDRAM
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, l, k; cin >> n >> l >> k; vector<int> cnt(26, 0); for (int i = 0; i < n * l; ++i) { char c; cin >> c; cnt[c - a ]++; } int last = 0; int cur = 0; vector<string> ans(n, string(l, # )); for (int i = 0; i < l; ++i) { while (!cnt[cur]) cur++; while (cnt[cur] < k - last && k - last > 0) { for (int j = 0; j < cnt[cur]; ++j) { ans[last + j][i] = char( a + cur); } last += cnt[cur]; cur++; } for (int j = 0; j < k - last; ++j) { ans[j + last][i] = char( a + cur); } cnt[cur] -= k - last; } for (int i = 0; i < n; ++i) { for (int j = 0; j < l; ++j) { if (ans[i][j] == # ) { cnt[cur]--; cout << char( a + cur); } else cout << ans[i][j]; while (!cnt[cur]) cur++; } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 5 * 1e5 + 1; long long n, a[N], sum[N], s, f, ans; int32_t main() { ios_base ::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (long long i = 0; i < n; i++) { cin >> a[i]; if (i) sum[i] = sum[i - 1] + a[i]; else sum[i] = a[i]; } if (sum[n - 1] % 3) return cout << 0 n , 0; s = sum[n - 1] / 3; if (!s) { for (long long i = 0; i < n - 1; i++) { if (!sum[i]) f++; } cout << f * (f - 1) / 2 << n ; return 0; } for (long long i = 0; i < n - 1; i++) { if (sum[i] == s) f++; else if (sum[i] == s * 2) ans += f; } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> template <class T> inline T lowbit(T x) { return x & (-x); } template <class T> inline T sqr(T x) { return x * x; } template <class T> inline bool scan(T &ret) { char c; int sgn; if (c = getchar(), c == EOF) return 0; while (c != - && (c < 0 || c > 9 )) c = getchar(); sgn = (c == - ) ? -1 : 1; ret = (c == - ) ? 0 : (c - 0 ); while (c = getchar(), c >= 0 && c <= 9 ) ret = ret * 10 + (c - 0 ); ret *= sgn; return 1; } const double pi = 3.14159265358979323846264338327950288L; using namespace std; int n, pre; char a[100005]; bool vis[100005]; pair<int, int> q[100005]; vector<int> ans[100005], num; long long Pow[100005], fac[100005], rev[100005]; long long qpow(long long a, long long b) { if (b == 0) return 1; long long ans = qpow(a, b >> 1); ans = ans * ans % 1000000007; if (b & 1) ans = ans * a % 1000000007; return ans; } long long C(int m, int n) { if (m < n) return 0; return fac[m] * rev[n] % 1000000007 * rev[m - n] % 1000000007; } void solve() { fac[0] = 1; for (int i = 1; i < 100005; i++) fac[i] = fac[i - 1] * i % 1000000007; rev[100005 - 1] = qpow(fac[100005 - 1], 1000000007 - 2); for (int i = 100005 - 2; i >= 0; i--) rev[i] = rev[i + 1] * (i + 1) % 1000000007; for (int i = 0; i < 100005; i++) ans[i].clear(); num.clear(); Pow[0] = 1; for (int i = 1; i < 100005; i++) Pow[i] = Pow[i - 1] * 25 % 1000000007; for (int i = 1; i <= 100000; i++) if (vis[i]) { num.push_back(i); for (int j = 0; j < 100005; j++) { if (j < i) { ans[i].push_back(0); continue; } long long tmp = 1LL * ans[i][j - 1] * 26 % 1000000007 + C(j - 1, i - 1) * Pow[j - i] % 1000000007; ans[i].push_back(tmp % 1000000007); } } for (int i = 0; i < n; i++) { if (q[i].first == 1) { pre = q[i].second; } else { int k = *(lower_bound(num.begin(), num.end(), pre)); printf( %d n , ans[k][q[i].second]); } } } int main() { memset(vis, 0, sizeof(vis)); cin >> n >> a; vis[pre = strlen(a)] = 1; for (int i = 0; i < n; i++) { cin >> q[i].first; if (q[i].first == 1) { cin >> a; int len = strlen(a); q[i].second = len; vis[len] = 1; } else { cin >> q[i].second; } } solve(); return 0; }
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbarbiter.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: At some point in time, I might wish to have two masters connect
// to the same wishbone bus. As an example, I might wish to have
// both the instruction fetch and the load/store operators
// of my Zip CPU access the the same bus. How shall they both
// get access to the same resource? This module allows the
// wishbone interfaces from two sources to drive the bus, while
// guaranteeing that only one drives the bus at a time.
//
// The core logic works like this:
//
// 1. If 'A' or 'B' asserts the o_cyc line, a bus cycle will begin,
// with acccess granted to whomever requested it.
// 2. If both 'A' and 'B' assert o_cyc at the same time, only 'A'
// will be granted the bus. (If the alternating parameter
// is set, A and B will alternate who gets the bus in
// this case.)
// 3. The bus will remain owned by whomever the bus was granted to
// until they deassert the o_cyc line.
// 4. At the end of a bus cycle, o_cyc is guaranteed to be
// deasserted (low) for one clock.
// 5. On the next clock, bus arbitration takes place again. If
// 'A' requests the bus, no matter how long 'B' was
// waiting, 'A' will then be granted the bus. (Unless
// again the alternating parameter is set, then the
// access is guaranteed to switch to B.)
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`define WBA_ALTERNATING
module wbarbiter(i_clk, i_rst,
// Bus A
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err,
// Bus B
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err,
// Both buses
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err);
// 18 bits will address one GB, 4 bytes at a time.
// 19 bits will allow the ability to address things other than just
// the 1GB of memory we are expecting.
parameter DW=32, AW=19;
// Wishbone doesn't use an i_ce signal. While it could, they dislike
// what it would (might) do to the synchronous reset signal, i_rst.
input wire i_clk, i_rst;
// Bus A
input wire i_a_cyc, i_a_stb, i_a_we;
input wire [(AW-1):0] i_a_adr;
input wire [(DW-1):0] i_a_dat;
input wire [(DW/8-1):0] i_a_sel;
output wire o_a_ack, o_a_stall, o_a_err;
// Bus B
input wire i_b_cyc, i_b_stb, i_b_we;
input wire [(AW-1):0] i_b_adr;
input wire [(DW-1):0] i_b_dat;
input wire [(DW/8-1):0] i_b_sel;
output wire o_b_ack, o_b_stall, o_b_err;
//
output wire o_cyc, o_stb, o_we;
output wire [(AW-1):0] o_adr;
output wire [(DW-1):0] o_dat;
output wire [(DW/8-1):0] o_sel;
input wire i_ack, i_stall, i_err;
// All the fancy stuff here is done with the three primary signals:
// o_cyc
// w_a_owner
// w_b_owner
// These signals are helped by r_cyc, r_a_owner, and r_b_owner.
// If you understand these signals, all else will fall into place.
// r_cyc just keeps track of the last o_cyc value. That way, on
// the next clock we can tell if we've had one non-cycle before
// starting another cycle. Specifically, no new cycles will be
// allowed to begin unless r_cyc=0.
reg r_cyc;
always @(posedge i_clk)
if (i_rst)
r_cyc <= 1'b0;
else
r_cyc <= o_cyc;
// Go high immediately (new cycle) if ...
// Previous cycle was low and *someone* is requesting a bus cycle
// Go low immadiately if ...
// We were just high and the owner no longer wants the bus
// WISHBONE Spec recommends no logic between a FF and the o_cyc
// This violates that spec. (Rec 3.15, p35)
wire w_a_owner, w_b_owner;
assign o_cyc = ((~r_cyc)&&((i_a_cyc)||(i_b_cyc))) || ((r_cyc)&&((w_a_owner)||(w_b_owner)));
// Register keeping track of the last owner, wire keeping track of the
// current owner allowing us to not lose a clock in arbitrating the
// first clock of the bus cycle
reg r_a_owner, r_b_owner;
`ifdef WBA_ALTERNATING
reg r_a_last_owner;
`endif
always @(posedge i_clk)
if (i_rst)
begin
r_a_owner <= 1'b0;
r_b_owner <= 1'b0;
end else begin
r_a_owner <= w_a_owner;
r_b_owner <= w_b_owner;
`ifdef WBA_ALTERNATING
if (w_a_owner)
r_a_last_owner <= 1'b1;
else if (w_b_owner)
r_a_last_owner <= 1'b0;
`endif
end
//
// If you are the owner, retain ownership until i_x_cyc is no
// longer asserted. Likewise, you cannot become owner until o_cyc
// is de-asserted for one cycle.
//
// 'A' is given arbitrary priority over 'B'
// 'A' may own the bus only if he wants it. When 'A' drops i_a_cyc,
// o_cyc must drop and so must w_a_owner on the same cycle.
// However, when 'A' asserts i_a_cyc, he can only capture the bus if
// it's had an idle cycle.
// The same is true for 'B' with one exception: if both contend for the
// bus on the same cycle, 'A' arbitrarily wins.
`ifdef WBA_ALTERNATING
assign w_a_owner = (i_a_cyc) // if A requests ownership, and either
&& ((r_a_owner) // A has already been recognized or
|| ((~r_cyc) // the bus is free and
&&((~i_b_cyc) // B has not requested, or if he
||(~r_a_last_owner)) )); // has, it's A's turn
assign w_b_owner = (i_b_cyc)&& ((r_b_owner) || ((~r_cyc)&&((~i_a_cyc)||(r_a_last_owner)) ));
`else
assign w_a_owner = (i_a_cyc)&& ((r_a_owner) || (~r_cyc) );
assign w_b_owner = (i_b_cyc)&& ((r_b_owner) || ((~r_cyc)&&(~i_a_cyc)) );
`endif
// Realistically, if neither master owns the bus, the output is a
// don't care. Thus we trigger off whether or not 'A' owns the bus.
// If 'B' owns it all we care is that 'A' does not. Likewise, if
// neither owns the bus than the values on the various lines are
// irrelevant. (This allows us to get two outputs per Xilinx 6-LUT)
assign o_stb = (o_cyc) && ((w_a_owner) ? i_a_stb : i_b_stb);
assign o_we = (w_a_owner) ? i_a_we : i_b_we;
assign o_adr = (w_a_owner) ? i_a_adr : i_b_adr;
assign o_dat = (w_a_owner) ? i_a_dat : i_b_dat;
assign o_sel = (w_a_owner) ? i_a_sel : i_b_sel;
// We cannot allow the return acknowledgement to ever go high if
// the master in question does not own the bus. Hence we force it
// low if the particular master doesn't own the bus.
assign o_a_ack = (w_a_owner) ? i_ack : 1'b0;
assign o_b_ack = (w_b_owner) ? i_ack : 1'b0;
// Stall must be asserted on the same cycle the input master asserts
// the bus, if the bus isn't granted to him.
assign o_a_stall = (w_a_owner) ? i_stall : 1'b1;
assign o_b_stall = (w_b_owner) ? i_stall : 1'b1;
//
//
assign o_a_err = (w_a_owner) ? i_err : 1'b0;
assign o_b_err = (w_b_owner) ? i_err : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { char name[55]; int score; int c[50]; } comp[55]; int cmp1(node x, node y) { if (x.score > y.score) return 1; else if (x.score == y.score) { for (int i = 0; i < 50; i++) if (x.c[i] > y.c[i]) return 1; else if (x.c[i] < y.c[i]) return 0; } else return 0; } int cmp2(node x, node y) { if (x.c[0] > y.c[0]) return 1; else if (x.c[0] == y.c[0]) { if (x.score > y.score) return 1; else if (x.score == y.score) { for (int i = 1; i < 50; i++) if (x.c[i] > y.c[i]) return 1; else if (x.c[i] < y.c[i]) return 0; } else return 0; } else return 0; } int s[10] = {25, 18, 15, 12, 10, 8, 6, 4, 2, 1}; int main() { int t; while (scanf( %d , &t) != EOF) { memset(comp, 0, sizeof(comp)); int sum = 0; while (t--) { int n, i; char na[55]; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %s , na); int j; for (j = 0; j < sum; j++) { if (strcmp(comp[j].name, na) == 0) { if (i < 10) comp[j].score += s[i]; comp[j].c[i]++; break; } } if (j == sum) { strcpy(comp[sum].name, na); if (i < 10) comp[sum].score += s[i]; comp[sum].c[i]++; sum++; } } } sort(comp, comp + sum, cmp1); printf( %s n , comp[0].name); sort(comp, comp + sum, cmp2); printf( %s n , comp[0].name); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int x, y, n, m, i, k, ans; string s[30], s1[30]; int main() { cin >> n >> m; for (i = 0; i < n; i++) { cin >> s[i]; } for (i = 0; i < m; i++) { cin >> s1[i]; } cin >> k; for (i = 0; i < k; i++) { cin >> x; if (x % n == 0) cout << s[n - 1]; else cout << s[x % n - 1]; if (x % m == 0) cout << s1[m - 1]; else cout << s1[x % m - 1]; cout << endl; } }
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for ptp_perout
*/
module test_ptp_perout;
// Parameters
parameter FNS_ENABLE = 1;
parameter OUT_START_S = 48'h0;
parameter OUT_START_NS = 30'h0;
parameter OUT_START_FNS = 16'h0000;
parameter OUT_PERIOD_S = 48'd1;
parameter OUT_PERIOD_NS = 30'd0;
parameter OUT_PERIOD_FNS = 16'h0000;
parameter OUT_WIDTH_S = 48'h0;
parameter OUT_WIDTH_NS = 30'd1000;
parameter OUT_WIDTH_FNS = 16'h0000;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [95:0] input_ts_96 = 0;
reg input_ts_step = 0;
reg enable = 0;
reg [95:0] input_start = 0;
reg input_start_valid = 0;
reg [95:0] input_period = 0;
reg input_period_valid = 0;
reg [95:0] input_width = 0;
reg input_width_valid = 0;
// Outputs
wire locked;
wire error;
wire output_pulse;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
input_ts_96,
input_ts_step,
enable,
input_start,
input_start_valid,
input_period,
input_period_valid,
input_width,
input_width_valid
);
$to_myhdl(
locked,
error,
output_pulse
);
// dump file
$dumpfile("test_ptp_perout.lxt");
$dumpvars(0, test_ptp_perout);
end
ptp_perout #(
.FNS_ENABLE(FNS_ENABLE),
.OUT_START_S(OUT_START_S),
.OUT_START_NS(OUT_START_NS),
.OUT_START_FNS(OUT_START_FNS),
.OUT_PERIOD_S(OUT_PERIOD_S),
.OUT_PERIOD_NS(OUT_PERIOD_NS),
.OUT_PERIOD_FNS(OUT_PERIOD_FNS),
.OUT_WIDTH_S(OUT_WIDTH_S),
.OUT_WIDTH_NS(OUT_WIDTH_NS),
.OUT_WIDTH_FNS(OUT_WIDTH_FNS)
)
UUT (
.clk(clk),
.rst(rst),
.input_ts_96(input_ts_96),
.input_ts_step(input_ts_step),
.enable(enable),
.input_start(input_start),
.input_start_valid(input_start_valid),
.input_period(input_period),
.input_period_valid(input_period_valid),
.input_width(input_width),
.input_width_valid(input_width_valid),
.locked(locked),
.error(error),
.output_pulse(output_pulse)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 55; const int d[4][2] = {-1, 0, 0, 1, 1, 0, 0, -1}; char a[N][N]; int v[4][N][N][2], m, n; int q[N * N * 4 * 2][4]; int check(int x, int y) { if (x >= 1 && x <= m && y >= 1 && y <= n && a[x][y] == B ) return 1; else return 0; } int bfs(int sx, int sy) { int l = 1, r = 0, i, j, x, y, k, t, nx, ny, nk; memset(v, 0, sizeof(v)); for (i = 0; i < 4; i++) { v[i][sx][sy][0] = 1; r++; q[r][0] = i; q[r][1] = sx; q[r][2] = sy; q[r][3] = 0; } while (l <= r) { x = q[l][1]; y = q[l][2]; k = q[l][0]; t = q[l][3]; l++; nx = x + d[k][0]; ny = y + d[k][1]; if (check(nx, ny)) if (!v[k][nx][ny][t]) { v[k][nx][ny][t] = 1; r++; q[r][0] = k; q[r][1] = nx; q[r][2] = ny; q[r][3] = t; } if (t == 0) { for (i = -1; i <= 1; i += 2) { nk = (k + 4 + i) % 4; if (!v[nk][x][y][1]) { v[nk][x][y][1] = 1; r++; q[r][0] = nk; q[r][1] = x; q[r][2] = y; q[r][3] = 1; } } } } for (i = 1; i <= m; i++) for (j = 1; j <= n; j++) if (a[i][j] == B ) { int f = 0; for (k = 0; k < 4; k++) for (t = 0; t <= 1; t++) if (v[k][i][j][t]) f = 1; if (f == 0) return 0; } return 1; } int main() { int i, j; scanf( %d%d , &m, &n); for (i = 1; i <= m; i++) scanf( %s , a[i] + 1); for (i = 1; i <= m; i++) for (j = 1; j <= n; j++) if (a[i][j] == B ) { if (bfs(i, j) == 0) { printf( NO n ); return 0; } } printf( YES n ); }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_tfifo.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// - Igor Mohor () ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'd1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 0;
count <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 0;
count <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= top_plus_1;
count <= count + 5'd1;
end
2'b01 : if(count>0)
begin
bottom <= bottom + 4'd1;
count <= count - 5'd1;
end
2'b11 : begin
bottom <= bottom + 4'd1;
top <= top_plus_1;
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & (count==fifo_depth))
overrun <= 1'b1;
end // always
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2016 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`timescale 1ps / 1ps
`define MAJOR_VERSION 1
`define MINOR_VERSION 0
`define REVISION 0
`define MAJOR_RANGE 31:28
`define MINOR_RANGE 27:20
`define REVISION_RANGE 19:16
module axi_lite_demo #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter INVERT_AXI_RESET = 1
)(
input clk,
input rst,
//AXI Lite Interface
//Write Address Channel
input i_awvalid,
input [ADDR_WIDTH - 1: 0] i_awaddr,
output o_awready,
//Write Data Channel
input i_wvalid,
output o_wready,
input [DATA_WIDTH - 1: 0] i_wdata,
//Write Response Channel
output o_bvalid,
input i_bready,
output [1:0] o_bresp,
//Read Address Channel
input i_arvalid,
output o_arready,
input [ADDR_WIDTH - 1: 0] i_araddr,
//Read Data Channel
output o_rvalid,
input i_rready,
output [1:0] o_rresp,
output [DATA_WIDTH - 1: 0] o_rdata
);
//local parameters
//Address Map
localparam REG_CONTROL = 0;
localparam REG_STATUS = 1;
localparam REG_VERSION = 2;
//Register/Wire
//AXI Signals
reg [31:0] control;
wire [31:0] status;
//Simple User Interface
wire [ADDR_WIDTH - 1: 0] w_reg_address;
wire [((ADDR_WIDTH - 1) - 2): 0] w_reg_32bit_address;
reg r_reg_invalid_addr;
wire w_reg_in_rdy;
reg r_reg_in_ack_stb;
wire [DATA_WIDTH - 1: 0] w_reg_in_data;
wire w_reg_out_req;
reg r_reg_out_rdy_stb;
reg [DATA_WIDTH - 1: 0] r_reg_out_data;
wire w_axi_rst;
//Submodules
//Convert AXI Slave signals to a simple register/address strobe
axi_lite_slave #(
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH )
) axi_lite_reg_interface (
.clk (clk ),
.rst (w_axi_rst ),
.i_awvalid (i_awvalid ),
.i_awaddr (i_awaddr ),
.o_awready (o_awready ),
.i_wvalid (i_wvalid ),
.o_wready (o_wready ),
.i_wdata (i_wdata ),
.o_bvalid (o_bvalid ),
.i_bready (i_bready ),
.o_bresp (o_bresp ),
.i_arvalid (i_arvalid ),
.o_arready (o_arready ),
.i_araddr (i_araddr ),
.o_rvalid (o_rvalid ),
.i_rready (i_rready ),
.o_rresp (o_rresp ),
.o_rdata (o_rdata ),
.o_reg_address (w_reg_address ),
.i_reg_invalid_addr (r_reg_invalid_addr ),
.o_reg_in_rdy (w_reg_in_rdy ),
.i_reg_in_ack_stb (r_reg_in_ack_stb ),
.o_reg_in_data (w_reg_in_data ),
.o_reg_out_req (w_reg_out_req ),
.i_reg_out_rdy_stb (r_reg_out_rdy_stb ),
.i_reg_out_data (r_reg_out_data )
);
//Asynchronous Logic
assign w_axi_rst = (INVERT_AXI_RESET) ? ~rst : rst;
assign w_reg_32bit_address = w_reg_address[(ADDR_WIDTH - 1): 2];
//blocks
always @ (posedge clk) begin
//De-assert Strobes
r_reg_in_ack_stb <= 0;
r_reg_out_rdy_stb <= 0;
r_reg_invalid_addr <= 0;
if (w_axi_rst) begin
control <= 0;
r_reg_out_data <= 0;
end
else begin
if (w_reg_in_rdy && !r_reg_in_ack_stb) begin
//From master
case (w_reg_32bit_address)
REG_CONTROL: begin
control <= w_reg_in_data;
end
default: begin
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_in_ack_stb <= 1;
end
else if (w_reg_out_req && !r_reg_out_rdy_stb) begin
//To master
case (w_reg_32bit_address)
REG_CONTROL: begin
r_reg_out_data <= control;
end
REG_STATUS: begin
r_reg_out_data <= status;
end
REG_VERSION: begin
r_reg_out_data <= 32'h00;
r_reg_out_data[`MAJOR_RANGE] <= `MAJOR_VERSION;
r_reg_out_data[`MINOR_RANGE] <= `MINOR_VERSION;
r_reg_out_data[`REVISION_RANGE] <= `REVISION;
end
default: begin
r_reg_out_data <= 32'h00;
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_out_rdy_stb <= 1;
end
end
end
endmodule
|
//% @file adc_cnv_sipo.v
//% @brief Drive ADC (LTC2325-16) conversion and convert Serial dataIn to Parallel dataOut.
//% @author Yuan Mei
//%
//% @param[in] NCH total number of ADC channels
//%
//% Relative time (phase) relation between cnv_n and clkff is
//% critical. One can swap D1, D2 bits in ODDR to achieve half-CLK
//% shift, or change the cnt condition number between 2 and 3 for
//% adc_clkff_oe to achieve 1-CLK shift. set_output_delay in .xdc must
//% be commensurate.
`timescale 1ns / 1ps
module adc_cnv_sipo
#(
parameter NCH = 20
)
(
input RESET,
input CLK, //% DELAY_* must be synchronous to this clock
input REFCLK, //% REFCLK (200MHz) for IDELAYCTRL
input [7:0] DELAY_CHANNEL, //% ADC data input iodelay channel selection
input [4:0] DELAY_VALUE, //% ADC data input iodelay value
input DELAY_UPDATE, //% a pulse to update the delay value
input [3:0] CLKFF_DIV,
output CLKFF_P,
output CLKFF_N,
input CLK_LPBK_P,
input CLK_LPBK_N,
output CLK_LPBK,
output CNV_N_P,
output CNV_N_N,
output CNV_N,
input [NCH-1:0] INPUTS_P,
input [NCH-1:0] INPUTS_N,
output [NCH-1:0] INPUTS_OUT,
(* ASYNC_REG = "TRUE" *)
output reg [NCH*16-1:0] DOUT,
output reg DOUT_VALID
);
localparam iodelay_group_name = "tms_iodelay_grp";
reg adc_cnv_n;
reg adc_sample_n;
wire [NCH-1:0] adc_sdin_v;
wire adc_clkff_tmp, adc_clkff_tmp1;
(* KEEP = "TRUE" *)
wire adc_clk_lpbk;
reg adc_clkff_oe;
reg [4:0] cnt;
reg [3:0] idx;
reg [15:0] sdo_v[NCH-1:0];
(* IODELAY_GROUP = iodelay_group_name *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYCTRL adc_idelayctrl_inst
(
.RDY(), // 1-bit output: Ready output
.REFCLK(REFCLK), // 1-bit input: Reference clock input
.RST(RESET) // 1-bit input: Active high reset input
);
diffiodelay
#(
.NINPUT(NCH+1),
.NOUTPUT(1),
.INPUT_DIFF_TERM("TRUE"),
.IODELAY_GROUP_NAME(iodelay_group_name)
)
adc_diffiodelay_inst
(
.RESET(RESET),
.CLK(CLK), //% DELAY_* must be synchronous to this clock
.DELAY_CHANNEL(DELAY_CHANNEL),
.DELAY_VALUE(DELAY_VALUE),
.DELAY_UPDATE(DELAY_UPDATE), //% a pulse to update the delay value
.INPUTS_OUT({adc_clk_lpbk, adc_sdin_v}),
.INPUTS_P({CLK_LPBK_P, INPUTS_P}),
.INPUTS_N({CLK_LPBK_N, INPUTS_N}),
.OUTPUTS_IN(0),
.OUTPUTS_P(),
.OUTPUTS_N()
);
assign INPUTS_OUT[NCH-1:0] = adc_sdin_v;
// clkff
clk_div
#(
.WIDTH(32),
.PBITS(4)
)
adc_clkff_div_inst
(
.RESET(RESET),
.CLK(CLK),
.DIV(CLKFF_DIV),
.CLK_DIV(adc_clkff_tmp)
);
// clock forwarding
ODDR
#(
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
)
adc_clkff_forward_inst
(
.Q(adc_clkff_tmp1), // 1-bit DDR output
.C(adc_clkff_tmp), // 1-bit clock input
.CE(1), // 1-bit clock enable input
.D1(0), // 1-bit data input (positive edge)
.D2(1), // 1-bit data input (negative edge)
.R(~adc_clkff_oe), // 1-bit reset
.S(0) // 1-bit set
);
OBUFDS
#(
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
adc_clkff_obufds_inst
(
.O(CLKFF_P), // Diff_p output (connect directly to top-level port)
.OB(CLKFF_N), // Diff_n output (connect directly to top-level port)
.I(adc_clkff_tmp1) // Buffer input
);
// clk_lpbk
assign CLK_LPBK = adc_clk_lpbk;
// adc_cnv_n
OBUFDS
#(
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
adc_cnv_n_obufds_inst
(
.O(CNV_N_P), // Diff_p output (connect directly to top-level port)
.OB(CNV_N_N), // Diff_n output (connect directly to top-level port)
.I(adc_cnv_n) // Buffer input
);
assign CNV_N = adc_cnv_n;
always @ (posedge adc_clkff_tmp or posedge RESET) begin
if (RESET) begin
cnt <= 0;
adc_cnv_n <= 1;
adc_sample_n <= 1;
adc_clkff_oe <= 0;
end
else begin
cnt <= cnt + 1;
if (cnt>=19) begin
cnt <= 0;
end
adc_cnv_n <= 0;
if (0<=cnt && cnt<3) begin
adc_cnv_n <= 1;
end
adc_sample_n <= 0;
if (0<cnt && cnt<3) begin
adc_sample_n <= 1;
end
adc_clkff_oe <= 1;
if ((0<=cnt && cnt<3) || cnt>=3+16) begin // Adjust the number (2 or 3) to satisfy the external time delay.
adc_clkff_oe <= 0;
end
end
end
// sample in CLK domain
reg adc_sample_n_prev;
always @ (posedge CLK or posedge RESET) begin
if (RESET) begin
adc_sample_n_prev <= 0;
DOUT_VALID <= 0;
end
else begin
adc_sample_n_prev <= adc_sample_n;
DOUT_VALID <= 0;
if (adc_sample_n_prev == 0 && adc_sample_n == 1) begin // rising edge
DOUT_VALID <= 1;
end
end
end
genvar i;
generate
for (i=0; i<NCH; i=i+1) begin
always @ (posedge adc_clk_lpbk or posedge adc_sample_n or posedge RESET) begin
if (RESET) begin
sdo_v[i] <= 0;
end
else begin
if (adc_sample_n) begin
idx <= 15;
end
else begin
sdo_v[i][idx] <= adc_sdin_v[i];
idx <= idx - 1;
end
end
end
// sample in CLK domain
always @ (posedge CLK or posedge RESET) begin
if (RESET) begin
DOUT[16*i+15:16*i] <= 0;
end
else begin
if (adc_sample_n_prev == 0 && adc_sample_n == 1) begin // rising edge
DOUT[16*i+15:16*i] <= sdo_v[i];
end
end
end
end
endgenerate
endmodule // adc_cnv_sipo
|
#include <bits/stdc++.h> using namespace std; const int M = 3e5 + 10; const long long inf = 1e18 + 10; const long long mod = 1e1; long long a[M], p[M], dp[3][M]; int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); for (int i = 0; i <= n; i++) dp[0][i] = dp[1][i] = dp[2][i] = inf; for (int i = 1; i <= n; i++) { scanf( %lld%lld , &a[i], &p[i]); } dp[0][1] = 0; dp[1][1] = p[1]; dp[2][1] = 2 * p[1]; for (int i = 2; i <= n; i++) { if (a[i - 1] == a[i]) { dp[0][i] = min(dp[1][i - 1], dp[2][i - 1]); dp[1][i] = min(dp[0][i - 1], dp[2][i - 1]) + p[i]; dp[2][i] = min(dp[0][i - 1], dp[1][i - 1]) + 2 * p[i]; } else if (a[i - 1] + 1 == a[i]) { dp[0][i] = min(dp[0][i - 1], dp[2][i - 1]); dp[1][i] = min(dp[1][i - 1], dp[0][i - 1]) + p[i]; dp[2][i] = min(dp[0][i - 1], min(dp[2][i - 1], dp[1][i - 1])) + 2 * p[i]; } else if (a[i - 1] + 2 == a[i]) { dp[0][i] = min(dp[0][i - 1], dp[1][i - 1]); dp[1][i] = min(dp[0][i - 1], min(dp[1][i - 1], dp[2][i - 1])) + p[i]; dp[2][i] = min(dp[0][i - 1], min(dp[1][i - 1], dp[2][i - 1])) + 2 * p[i]; } else if (a[i - 1] == a[i] + 1) { dp[0][i] = min(dp[0][i - 1], min(dp[1][i - 1], dp[2][i - 1])); dp[1][i] = min(dp[1][i - 1], dp[2][i - 1]) + p[i]; dp[2][i] = min(dp[0][i - 1], dp[2][i - 1]) + 2 * p[i]; } else if (a[i - 1] == a[i] + 2) { dp[0][i] = min(dp[0][i - 1], min(dp[1][i - 1], dp[2][i - 1])); dp[1][i] = min(dp[0][i - 1], min(dp[1][i - 1], dp[2][i - 1])) + p[i]; dp[2][i] = min(dp[1][i - 1], dp[2][i - 1]) + 2 * p[i]; } else { dp[0][i] = min(dp[0][i - 1], min(dp[1][i - 1], dp[2][i - 1])); dp[1][i] = min(dp[0][i - 1], min(dp[1][i - 1], dp[2][i - 1])) + p[i]; dp[2][i] = min(dp[0][i - 1], min(dp[1][i - 1], dp[2][i - 1])) + 2 * p[i]; } } printf( %lld n , min(dp[0][n], min(dp[1][n], dp[2][n]))); } return 0; }
|
// ----------------------------
// This module impelements a scanflop.
//
// Note:
// - Syntax works and compiles with Verilog2LPN compiler
// - async. design follows dual rail encoding that maps
// input to output and output to internal states
//
// author: Tramy Nguyen
// ----------------------------
module scanflop_imp (in1_0, in1_1, in2_0, in2_1, sel0, sel1, q0, q1, req, ack);
input wire in1_0, in1_1, in2_0, in2_1, sel0, sel1, req;
output reg q1, q0, ack;
reg state;
initial begin
q0 = 1'b0;
q1 = 1'b0;
ack = 1'b0;
state = 1'b0;
end
always begin
wait (req == 1'b1) #5;
// input to output
if(sel0 == 1'b1 && in1_0 == 1'b1) begin
#5 q0 = 1'b1;
#5 ack = 1'b1;
end else if(sel0 == 1'b1 && in1_1 == 1'b1) begin
#5 q1 = 1'b1;
#5 ack = 1'b1;
end else if(sel0 == 1'b1 && in1_0 == 1'b0 && in1_1 == 1'b0 && state == 1'b0) begin
#5 q0 = 1'b1;
#5 ack = 1'b1;
end else if(sel0 == 1'b1 && in1_0 == 1'b0 && in1_1 == 1'b0 && state == 1'b1) begin
#5 q1 = 1'b1;
#5 ack = 1'b1;
end else if(sel1 == 1'b1 && in2_0 == 1'b1) begin
#5 q0 = 1'b1;
#5 ack = 1'b1;
end else if(sel1 == 1'b1 && in2_1 == 1'b1) begin
#5 q1 = 1'b1;
#5 ack = 1'b1;
end else if(sel1 == 1'b1 && in2_0 == 1'b0 && in2_1 == 1'b0 && state == 1'b0) begin
#5 q0 = 1'b1;
#5 ack = 1'b1;
end else if(sel1 == 1'b1 && in2_0 == 1'b0 && in2_1 == 1'b0 && state == 1'b1) begin
#5 q1 = 1'b1;
#5 ack = 1'b1;
end
// output to next state
if(q0 == 1'b1 && state == 1'b1) begin
state = 1'b0;
end
else if(q1 == 1'b1 && state == 1'b0) begin
state = 1'b1;
end
//stabilize the signals
wait((q0 == 1'b1 && state != 1'b1) || (q1 == 1'b1 && state == 1'b1)) #5;
//reset
wait(req != 1'b1) #5;
if (q0 == 1'b1) begin
#5 q0 = 1'b0;
end
if(q1 == 1'b1) begin
#5 q1 = 1'b0;
end
#5 ack = 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, x, y, z; cin >> a >> b >> c; cin >> x >> y >> z; a -= x; b -= y; c -= z; if (a >= 0) a /= 2; if (b >= 0) b /= 2; if (c >= 0) c /= 2; if (a + b + c >= 0) cout << Yes << endl; else cout << No << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; double const e = 0.000001; int main() { int n, a, d; cin >> n >> a >> d; int prevv = 10000000; double prevt = 0; for (int i = 0; i < n; i++) { int t, v; cin >> t >> v; double t1 = (double)v / a; double s1 = a * t1 * t1 / 2; double t2 = 0; if (s1 - d > e) { t1 = sqrt((2.0 * d) / a); } else { double s2 = d - s1; t2 = s2 / v; } double tt = t1 + t2; if (t + tt - prevt > e) { prevt = t + tt; prevv = v; } printf( %f n , prevt); } return 0; }
|
#include <bits/stdc++.h> using namespace std; #define fast ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int main() { fast; int t; cin >> t; while (t--) { int n; cin >> n; vector<int> a(n + 1); a[0] = 0; for (int i = 1; i <= n; i++) a[i] = i; if (n % 2 == 0) { for (int i = 1; i < n; i += 2) swap(a[i], a[i + 1]); } else { for (int i = 1; i < n - 2; i+= 2) swap(a[i], a[i + 1]); int temp = a[n]; a[n] = a[n - 1]; a[n - 1] = a[n - 2]; a[n - 2] = temp; } for (int i = 1; i <= n; i++) cout << a[i] << ; cout << endl; } }
|
//
// (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
//
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ps/1ps
module srio_gen2_0_srio_rst
(
input cfg_clk, // CFG interface clock
input log_clk, // LOG interface clock
input phy_clk, // PHY interface clock
input gt_pcs_clk, // GT Fabric interface clock
input sys_rst, // Global reset signal
input port_initialized, // Port is intialized
input phy_rcvd_link_reset, // Received 4 consecutive reset symbols
input force_reinit, // Force reinitialization
input clk_lock, // Indicates the MMCM has achieved a stable clock
output reg controlled_force_reinit, // Force reinitialization
output cfg_rst, // CFG dedicated reset
output log_rst, // LOG dedicated reset
output buf_rst, // BUF dedicated reset
output phy_rst, // PHY dedicated reset
output gt_pcs_rst // GT dedicated reset
);
// {{{ Parameter declarations -----------
// Reset State Machine
localparam IDLE = 4'b0001;
localparam LINKRESET = 4'b0010;
localparam PHY_RESET1 = 4'b0100;
localparam PHY_RESET2 = 4'b1000;
// }}} End Parameter declarations -------
wire sys_rst_buffered;
// {{{ wire declarations ----------------
reg [0:3] reset_state = IDLE;
reg [0:3] reset_next_state = IDLE;
(* ASYNC_REG = "TRUE" *)
reg [3:0] cfg_rst_srl;
(* ASYNC_REG = "TRUE" *)
reg [3:0] log_rst_srl;
(* ASYNC_REG = "TRUE" *)
reg [3:0] phy_rst_srl;
(* ASYNC_REG = "TRUE" *)
reg [3:0] gt_pcs_rst_srl;
reg sys_rst_int;
wire reset_condition = sys_rst || phy_rcvd_link_reset || sys_rst_int;
// }}} End wire declarations ------------
assign cfg_rst = cfg_rst_srl[3];
always @(posedge cfg_clk or posedge reset_condition) begin
if (reset_condition) begin
cfg_rst_srl <= 4'b1111;
end else if (clk_lock) begin
cfg_rst_srl <= {cfg_rst_srl[2:0], 1'b0};
end
end
assign log_rst = log_rst_srl[3];
always @(posedge log_clk or posedge reset_condition) begin
if (reset_condition) begin
log_rst_srl <= 4'b1111;
end else if (clk_lock) begin
log_rst_srl <= {log_rst_srl[2:0], 1'b0};
end
end
// The Buffer actively manages the reset due to the
// nature of the domain crossing being done in the buffer.
assign buf_rst = reset_condition;
assign phy_rst = phy_rst_srl[3];
always @(posedge phy_clk or posedge reset_condition) begin
if (reset_condition) begin
phy_rst_srl <= 4'b1111;
end else if (clk_lock) begin
phy_rst_srl <= {phy_rst_srl[2:0], 1'b0};
end
end
assign gt_pcs_rst = gt_pcs_rst_srl[3];
always @(posedge gt_pcs_clk or posedge reset_condition) begin
if (reset_condition) begin
gt_pcs_rst_srl <= 4'b1111;
end else if (clk_lock) begin
gt_pcs_rst_srl <= {gt_pcs_rst_srl[2:0], 1'b0};
end
end
// This controller is used to properly send link reset requests that were
// made by the user.
always@(posedge log_clk) begin
reset_state <= reset_next_state;
end
always @* begin
casex (reset_state)
IDLE: begin
// Current State Outputs
sys_rst_int = 1'b0;
controlled_force_reinit = 1'b0;
// Next State Outputs
if (force_reinit)
reset_next_state = LINKRESET;
else
reset_next_state = IDLE;
end
LINKRESET: begin
// Current State Outputs
sys_rst_int = 1'b0;
controlled_force_reinit = 1'b1;
// Next State Outputs
if (~port_initialized)
reset_next_state = PHY_RESET1;
else
reset_next_state = LINKRESET;
end
PHY_RESET1: begin
// Current State Outputs
sys_rst_int = 1'b1;
controlled_force_reinit = 1'b0;
// Next State Outputs
reset_next_state = PHY_RESET2;
end
PHY_RESET2: begin
// Current State Outputs
sys_rst_int = 1'b1;
controlled_force_reinit = 1'b0;
// Next State Outputs
if (force_reinit)
reset_next_state = PHY_RESET2;
else
reset_next_state = IDLE;
end
default: begin
// Current State Outputs
sys_rst_int = 1'b0;
controlled_force_reinit = 1'b0;
// Next State Outputs
reset_next_state = IDLE;
end
endcase
end
endmodule
// {{{ DISCLAIMER OF LIABILITY
// -----------------------------------------------------------------
// (c) Copyright 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// }}}
|
#include <bits/stdc++.h> using namespace std; int a[51]; int b[51]; int d1[51]; int d2[51]; int main() { int n, l; int i, j, k; cin >> n >> l; for (i = 1; i <= n; i++) { cin >> a[i]; if (i >= 2) d1[i] = a[i] - a[i - 1]; } d1[1] = a[1] + l - a[n]; for (i = 1; i <= n; i++) { cin >> b[i]; if (i >= 2) d2[i] = b[i] - b[i - 1]; } d2[1] = b[1] + l - b[n]; int same = 0; for (i = 1; i <= n; i++) { int flag = 1; for (k = 1, j = i; k <= n; j++, k++) { if (j > n) j = 1; if (d1[j] != d2[k]) { flag = 0; break; } } if (flag == 1) { same = 1; break; } } if (same == 1) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m, k; cin >> n >> m >> k; vector<vector<int> > g(n); vector<int> deg(n); for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; --x; --y; g[x].push_back(y); g[y].push_back(x); deg[x]++; deg[y]++; } for (int i = 0; i < n; i++) sort(g[i].begin(), g[i].end()); vector<bool> used(n), vis(n); vector<int> q(n); int top = 0; vector<int> vert(k); bool f = 0; for (int i = 0; i < n; i++) { used[i] = vis[i] = 0; if (deg[i] < k) { vis[i] = 1; q[top++] = i; } } for (int i = 0; i < top; i++) { int u = q[i]; vis[u] = 0; used[u] = 1; if (deg[u] < k - 1) { for (auto j : g[u]) { if (!used[j]) --m; deg[j]--; if (!vis[j] and !used[j] and deg[j] < k) { vis[j] = 1; q[top++] = j; } } continue; } else if (deg[u] == k - 1) { if ((long long)k * (k - 1) <= 2 * (long long)m) { int r = 0; for (auto p : g[u]) { if (!used[p]) vert[r++] = p; } bool ff = 1; for (int x = 0; x < r; x++) { if (!ff) break; for (int y = x + 1; y < r; y++) { int pp = lower_bound(g[vert[x]].begin(), g[vert[x]].end(), vert[y]) - g[vert[x]].begin(); if (pp == g[vert[x]].size() or g[vert[x]][pp] != vert[y]) { ff = 0; break; } } } if (ff) { f = 1; cout << 2 n << u + 1 << ; for (int c = 0; c < r; c++) cout << vert[c] + 1 << ; cout << n ; break; } } } for (auto j : g[u]) { deg[j]--; if (!used[j]) --m; if (!vis[j] and !used[j] and deg[j] < k) { vis[j] = 1; q[top++] = j; } } } if (f) continue; vector<int> ff; for (int i = 0; i < n; i++) if (!used[i]) ff.push_back(i); if (!ff.empty()) { cout << 1 << ff.size() << n ; for (auto c : ff) { c++; cout << c << ; } cout << n ; } else cout << -1 n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = (int)1e9; const int mod = (int)1e9 + 7; const int MAXN = (int)3e5 + 5; vector<int> primes[1000005]; int x, p, k; vector<pair<int, int> > v(1 << 7); int calc(int a) { int cnt = 1; int num = 0; int tmp = a; a = 0; for (int i = 1; i < (1 << primes[p].size()); i++) { if (cnt * 2 == i) { cnt *= 2; num++; } v[i] = {v[i - cnt].first * primes[p][num], v[i - cnt].second + 1}; if (v[i].second % 2) { a += tmp / v[i].first; } else { a -= tmp / v[i].first; } } return tmp - a; } void solve() { cin >> x >> p >> k; k += calc(x); int l = x + 1, r = 6e6 + 5e5 + 3e4 + 4e3 + 5e2; while (l < r) { int m = (l + r) / 2; if (calc(m) >= k) { r = m; } else { l = m + 1; } } cout << l << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); for (int i = 2; i < 1000005; i++) { if (!primes[i].size()) { for (int j = i; j < 1000005; j += i) { primes[j].push_back(i); } } } v[0] = {1, 0}; int t = 1; cin >> t; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); ; unsigned long long x, y; cin >> x >> y; if (x < y) { return cout << -1, 0; } if ((x - y) & 1) { return cout << -1, 0; } long long z = (x - y) / 2; if (y & z) { cout << -1; return 0; } long long a = z; long long b = x - z; if (a > b) swap(a, b); cout << a << << b << n ; }
|
module Rx(CLK,reset,cableReset_L,hardReset_L, message_received_for_Phy, CC_Busy, CC_Idle, Start, Unexpected_goodCRC, Tx_state_Machine, Data_from_I2C,
Tx_Message_Discarded,ALERT,RECEIVE_BYTE_COUNT, GoodCRCtoPhy, address, DataToReg);
localparam Rx_Idle = 4'b0000;
localparam Rx_Wait_For_Phy_Message = 4'b0001;
localparam Rx_Message_Discarded = 4'b0010;
localparam Rx_Send_GoodCRC = 4'b0100;
localparam Rx_Report_SOP = 4'b1000;
input wire RECEIVE_DETECT_I;
input wire CLK;
input wire reset;
input wire cableReset_L;
input wire hardReset_L;
input wire message_received_for_Phy;
input wire CC_Busy;
input wire CC_Idle;
input wire Start;
input Unexpected_goodCRC;
input Tx_state_Machine;
input wire [7:0] Data_from_I2C;
output reg Tx_Message_Discarded;
output reg [15:0] ALERT;
output reg [7:0] RECEIVE_BYTE_COUNT;
output reg GoodCRCtoPhy;
output reg [7:0] address;
output reg [7:0] DataToReg;
reg [7:0] next_address;
reg [7:0] next_RECEIVE_BYTE_COUNT;
reg next_GoodCRCtoPhy;
reg [7:0] next_DATA;
reg [15:0] next_ALERT_OUT;
reg next_Tx_Message_Discarded;
reg[3:0] state;
reg [3:0] next_state;
assign Rx_Reset = !cableReset_L | !hardReset_L;
//assign message_received_for_Phy = RECEIVE_DETECT_I && 8'h01;
assign Rx_Buffer_Overflow = ALERT[10];
//FlipFlops
always@(posedge CLK)
begin
if(~reset)
begin
state <= Rx_Idle;
Tx_Message_Discarded <= 0;
ALERT <= 16'h0000;
RECEIVE_BYTE_COUNT <= 8'h00;
GoodCRCtoPhy <= 0;
address <= 8'h00;
DataToReg <= 8'h00;
end
else
begin
state <= next_state;
Tx_Message_Discarded <= next_Tx_Message_Discarded;
ALERT <= next_ALERT_OUT;
RECEIVE_BYTE_COUNT <= next_RECEIVE_BYTE_COUNT;
GoodCRCtoPhy <= next_GoodCRCtoPhy ;
address <= next_address;
DataToReg <= next_DATA;
end
end
//Logica de estados.
always@(*)
begin
case(state)
Rx_Idle:
if(Rx_Reset || ~Start)
begin
next_state = Rx_Idle;
end
else
begin
next_state = Rx_Wait_For_Phy_Message;
end
Rx_Wait_For_Phy_Message:
begin
if(Rx_Buffer_Overflow)
begin
next_state = Rx_Wait_For_Phy_Message;
end
else
if(message_received_for_Phy)
next_state = Rx_Message_Discarded;
else
next_state = Rx_Wait_For_Phy_Message;
end
Rx_Message_Discarded:
begin
next_state = Unexpected_goodCRC ? Rx_Report_SOP : Rx_Send_GoodCRC ;
end
Rx_Send_GoodCRC:
begin
if(CC_Busy || CC_Idle)
begin
next_state = Rx_Wait_For_Phy_Message;
end else
begin
next_state = Rx_Report_SOP;
end
end
Rx_Report_SOP:
next_state = Rx_Wait_For_Phy_Message;
default:
next_state = state;
endcase
end
//Logica de Salidas.
always @(*)
begin
case(state)
Rx_Message_Discarded:
begin
if(Tx_state_Machine)
begin
next_Tx_Message_Discarded = 1;
next_ALERT_OUT = ALERT | 16'h0020;
end
end
Rx_Send_GoodCRC:
begin
next_GoodCRCtoPhy = 1;
end
Rx_Report_SOP:
begin
next_DATA = Data_from_I2C;
next_RECEIVE_BYTE_COUNT <= RECEIVE_BYTE_COUNT + 1;
next_address = RECEIVE_BYTE_COUNT + 8'h30;
if(RECEIVE_BYTE_COUNT == 31)
begin
next_ALERT_OUT = ALERT | 16'h0404;
next_RECEIVE_BYTE_COUNT <= 0;
end
else
begin
next_ALERT_OUT = ALERT | 16'h0004;
end
end
default:
begin
next_address = address;
next_ALERT_OUT = ALERT;
next_RECEIVE_BYTE_COUNT = RECEIVE_BYTE_COUNT;
next_GoodCRCtoPhy= GoodCRCtoPhy;
next_DATA = DataToReg;
next_Tx_Message_Discarded = Tx_Message_Discarded;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 5; const int inf = 0x3f3f3f3f; int t, n; int a[200]; int main() { int n, q, t, k, d; int cnt; int sum; memset(a, 0, sizeof a); cin >> n >> q; for (int i = 0; i < q; i++) { cnt = 0; sum = 0; cin >> t >> k >> d; for (int j = 0; j < n; j++) { if (a[j] < t) cnt++; } if (cnt < k) cout << -1 << endl; else { for (int j = 0; j < n; j++) { if (a[j] < t) { k--; a[j] = t + d - 1; sum += j + 1; } if (k == 0) break; } cout << sum << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<long long int> dis(n); vector<long long int> ans(n); vector<bool> vis(n, 0); long long int acc = 0; for (long int i = 0; i < n; i++) { cin >> dis[i]; acc += dis[i]; } vector<vector<int>> edg(n); for (long int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; a--; b--; edg[a].push_back(b); edg[b].push_back(a); } vector<vector<int>> p(3); p[0].push_back(0); p[1].push_back(0); p[2].push_back(0); vis[0] = 1; int i = 0; long long int x = 0; while (p[0].size() < n) { for (long int j = 0; j < edg[p[0][i]].size(); j++) { if (!vis[edg[p[0][i]][j]]) { p[0].push_back(edg[p[0][i]][j]); p[1].push_back(p[0][i]); p[2].push_back(p[2][i] + 1); x += ((long long int)(p[2][i] + 1)) * (dis[edg[p[0][i]][j]]); vis[edg[p[0][i]][j]] = 1; } } i++; } for (int j = n - 1; j > 0; j--) { dis[p[1][j]] += dis[p[0][j]]; } ans[0] = x; for (long int i = 0; i < n; i++) { if (i == 0) continue; ans[p[0][i]] = acc + ans[p[1][i]] - 2 * dis[p[0][i]]; } cout << *max_element(ans.begin(), ans.end()); return 0; }
|
module fmrv32im_BADMEM_sel
(
// Data Memory Bus
output D_MEM_WAIT,
input D_MEM_ENA,
input [3:0] D_MEM_WSTB,
input [31:0] D_MEM_ADDR,
input [31:0] D_MEM_WDATA,
output [31:0] D_MEM_RDATA,
output D_MEM_BADMEM_EXCPT,
// DMEM
input C_MEM_WAIT,
output C_MEM_ENA,
output [3:0] C_MEM_WSTB,
output [31:0] C_MEM_ADDR,
output [31:0] C_MEM_WDATA,
input [31:0] C_MEM_RDATA,
input C_MEM_BADMEM_EXCPT,
// Local Inerface
input PERIPHERAL_BUS_WAIT,
output PERIPHERAL_BUS_ENA,
output [3:0] PERIPHERAL_BUS_WSTB,
output [31:0] PERIPHERAL_BUS_ADDR,
output [31:0] PERIPHERAL_BUS_WDATA,
input [31:0] PERIPHERAL_BUS_RDATA,
// PLIC
output PLIC_BUS_WE,
output [3:0] PLIC_BUS_ADDR,
output [31:0] PLIC_BUS_WDATA,
input [31:0] PLIC_BUS_RDATA,
// TIMER
output TIMER_BUS_WE,
output [3:0] TIMER_BUS_ADDR,
output [31:0] TIMER_BUS_WDATA,
input [31:0] TIMER_BUS_RDATA
);
// メモリマップ判定
wire dsel_ram, dsel_io, dsel_sys;
wire dsel_sys_plic, dsel_sys_timer;
wire dsel_illegal;
assign dsel_ram = (D_MEM_ADDR[31:30] == 2'b00);
assign dsel_io = (D_MEM_ADDR[31:30] == 2'b10);
assign dsel_sys = (D_MEM_ADDR[31:30] == 2'b11);
assign dsel_sys_plic = (dsel_sys & (D_MEM_ADDR[29:16] == 14'h0000));
assign dsel_sys_timer = (dsel_sys & (D_MEM_ADDR[29:16] == 14'h0001));
assign dsel_illegal = D_MEM_ENA & ~(dsel_ram | dsel_io | dsel_sys |
dsel_sys_plic | dsel_sys_timer);
// DMEM
assign C_MEM_ENA = (D_MEM_ENA & dsel_ram)?D_MEM_ENA:1'b0;
assign C_MEM_WSTB = (D_MEM_ENA & dsel_ram)?D_MEM_WSTB:4'd0;
assign C_MEM_ADDR = (D_MEM_ENA & dsel_ram)?D_MEM_ADDR:32'd0;
assign C_MEM_WDATA = (D_MEM_ENA & dsel_ram)?D_MEM_WDATA:32'd0;
// LOCAL
assign PERIPHERAL_BUS_ENA = (D_MEM_ENA & dsel_io)?D_MEM_ENA:1'b0;
assign PERIPHERAL_BUS_ADDR = (D_MEM_ENA & dsel_io)?D_MEM_ADDR:32'd0;
assign PERIPHERAL_BUS_WSTB = (D_MEM_ENA & dsel_io)?D_MEM_WSTB:4'd0;
assign PERIPHERAL_BUS_WDATA = (D_MEM_ENA & dsel_io)?D_MEM_WDATA:32'd0;
// PLIC
assign PLIC_BUS_WE = (D_MEM_ENA & dsel_sys_plic)?D_MEM_ENA & |D_MEM_WSTB:1'b0;
assign PLIC_BUS_ADDR = (D_MEM_ENA & dsel_sys_plic)?D_MEM_ADDR[5:2]:4'd0;
assign PLIC_BUS_WDATA = (D_MEM_ENA & dsel_sys_plic)?D_MEM_WDATA:32'd0;
// TIMER
assign TIMER_BUS_WE = (D_MEM_ENA & dsel_sys_timer)?D_MEM_ENA & |D_MEM_WSTB:1'b0;
assign TIMER_BUS_ADDR = (D_MEM_ENA & C_MEM_ENA & dsel_sys_timer)?D_MEM_ADDR[5:2]:4'd0;
assign TIMER_BUS_WDATA = (dsel_sys_timer)?D_MEM_WDATA:32'd0;
//
assign D_MEM_WAIT = (D_MEM_ENA & dsel_ram)?C_MEM_WAIT:
(D_MEM_ENA & dsel_io)?PERIPHERAL_BUS_WAIT:
1'b0;
assign D_MEM_RDATA = (dsel_ram)?C_MEM_RDATA:
(dsel_io)?PERIPHERAL_BUS_RDATA:
(dsel_sys_plic)?PLIC_BUS_RDATA:
(dsel_sys_timer)?TIMER_BUS_RDATA:
32'd0;
assign D_MEM_BADMEM_EXCPT = ((~C_MEM_WAIT & ~PERIPHERAL_BUS_WAIT) & D_MEM_ENA & dsel_ram)?C_MEM_BADMEM_EXCPT:
dsel_illegal;
endmodule // fmrv32im_dmemsel
|
#include <bits/stdc++.h> using namespace std; struct __s { __s() { if (1) { ios_base::Init i; cin.sync_with_stdio(0); cin.tie(0); } } ~__s() { if (!1) fprintf(stderr, Execution time: %.3lf s. n , (double)clock() / CLOCKS_PER_SEC); long long n; cin >> n; } } __S; long long n, m; long long x[55]; long long y[55]; long long first[55]; long long second[55]; long long I[55][55]; long long J[55][55]; bool u[55][55]; bool up[55]; bool ud[55]; bool ok[55]; vector<pair<pair<long long, long long>, pair<long long, long long> > > ans; long long findUp() { long long idx = -1; for (long long i = 0; i < (long long)(m); i++) { if (up[i]) continue; if (idx == -1 || x[i] < x[idx] || (x[i] == x[idx] && y[i] < y[idx])) { idx = i; } } return idx; } long long findDown() { long long idx = -1; for (long long i = 0; i < (long long)(m); i++) { if (ud[i]) continue; if (idx == -1 || first[i] > first[idx] || (first[i] == first[idx] && second[i] < second[idx])) { idx = i; } } return idx; } void move(long long i, long long dx, long long dy) { u[x[i]][y[i]] = false; I[x[i]][y[i]] = -1; ans.push_back( make_pair(make_pair(x[i], y[i]), make_pair(x[i] + dx, y[i] + dy))); x[i] += dx; y[i] += dy; u[x[i]][y[i]] = true; I[x[i]][y[i]] = i; } void shift(long long i, long long dx, long long dy) { long long first = x[i] + dx; long long second = y[i] + dy; if (u[first][second]) shift(I[first][second], dx, dy); move(i, dx, dy); } int main(void) { cin >> n >> m; for (long long i = 0; i < (long long)(n); i++) for (long long j = 0; j < (long long)(n); j++) J[i][j] = -1; for (long long i = 0; i < (long long)(m); i++) { cin >> x[i] >> y[i]; x[i]--; y[i]--; u[x[i]][y[i]] = true; I[x[i]][y[i]] = i; } for (long long i = 0; i < (long long)(m); i++) { cin >> first[i] >> second[i]; first[i]--; second[i]--; J[first[i]][second[i]] = i; } for (long long i = 0; i < (long long)(m); i++) { long long idx = findUp(); while (x[idx] != 0 || y[idx] != i) { while (x[idx] != 0 && !u[x[idx] - 1][y[idx]]) { move(idx, -1, 0); } while (y[idx] != i) { while (y[idx] > i && !u[x[idx]][y[idx] - 1]) { move(idx, 0, -1); } while (y[idx] < i && !u[x[idx]][y[idx] + 1]) { move(idx, 0, 1); } if (y[idx] != i) { idx = I[x[idx]][y[idx] + 1]; } } while (x[idx] != 0 && !u[x[idx] - 1][y[idx]]) { move(idx, -1, 0); } } up[idx] = true; } for (long long i = 0; i < (long long)(m); i++) { long long idx = findDown(); ud[idx] = true; if (first[idx] < 2) continue; while (x[idx] != first[idx] || y[idx] != second[idx]) { while (x[idx] != first[idx] - 1) { move(idx, 1, 0); } while (y[idx] > second[idx]) { move(idx, 0, -1); } while (y[idx] < second[idx]) { move(idx, 0, 1); } move(idx, 1, 0); } ok[idx] = true; } vector<long long> w[2]; for (long long i = 0; i < (long long)(min(n, 2LL)); i++) { for (long long j = 0; j < (long long)(n); j++) { if (J[i][j] == -1) continue; w[i].push_back(J[i][j]); } } for (long long i = 0; i < (long long)(2); i++) { for (long long j = 1; j < w[i].size(); ++j) { if (y[w[i][j - 1]] < y[w[i][j]]) continue; move(w[i][j], 1, 0); while (y[w[i][j]] < y[w[i][j - 1]]) move(w[i][j], 0, 1); shift(w[i][j - 1], 0, -1); move(w[i][j], -1, 0); } } for (long long i = 0; i < (long long)(w[1].size()); i++) { move(w[1][i], 1, 0); } for (long long i = 0; i < (long long)(2); i++) { for (long long jj = 0; jj < (long long)(w[i].size()); jj++) { long long j = w[i].size() - 1 - jj; while (y[w[i][j]] != n - 1 - jj) move(w[i][j], 0, 1); } for (long long j = 0; j < (long long)(w[i].size()); j++) { while (y[w[i][j]] != second[w[i][j]]) move(w[i][j], 0, -1); } } cout << ans.size() << n ; for (long long i = 0; i < (long long)(ans.size()); i++) { cout << ans[i].first.first + 1 << << ans[i].first.second + 1 << << ans[i].second.first + 1 << << ans[i].second.second + 1 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k; cin >> n >> k; long long int prices[n]; for (long long int i = 0; i < n; i++) { cin >> prices[i]; } long long int minimum = prices[0]; long long int ans = 0; for (long long int i = 1; i < n; i++) { if (prices[i] < minimum) { minimum = prices[i]; } } for (long long int i = 0; i < n; i++) { prices[i] -= minimum; } for (long long int i = 0; i < n; i++) { if (prices[i] % k != 0) { cout << -1 << endl; return 0; } } for (long long int i = 0; i < n; i++) { ans += prices[i] / k; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 100005; const int MOD = 1000000007; unordered_map<int, bool> sp; vector<int> g[MAX]; struct node { int u, v; int cost; node(int _u, int _v, int _cost) { u = _u; v = _v; cost = _cost; } }; bool mst_sort(node &a, node &b) { return a.cost < b.cost; } bool ans_sort(node &a, node &b) { return a.cost > b.cost; } vector<node> e; int par[MAX]; int findpar(int r) { if (par[r] == r) return r; par[r] = findpar(par[r]); return par[r]; } vector<node> tree; void mst(int n) { for (int i = 0; i < n; i++) par[i] = i; sort(e.begin(), e.end(), mst_sort); int c = 0; for (int i = 0; i < e.size(); i++) { int u = findpar(e[i].u); int v = findpar(e[i].v); if (u != v) { par[u] = v; tree.push_back(e[i]); g[e[i].u].push_back(e[i].v); g[e[i].v].push_back(e[i].u); c++; if (c == n - 1) break; } } return; } int can[MAX]; map<pair<int, int>, bool> vis; bool dfs(int n, int par) { if (sp[n]) return can[n] = true; if (vis[pair<int, int>(n, par)]) return can[n] = false; if (can[n] != -1) return can[n]; bool ret = false; for (int i : g[n]) { if (i != par) ret |= dfs(i, n); if (ret) return can[n] = ret; } return can[n] = ret; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); ; int n, m, k; cin >> n >> m >> k; for (int i = 0; i < k; i++) { int temp; cin >> temp; sp[temp] = true; } while (m--) { int u, v, cost; cin >> u >> v >> cost; e.push_back(node(u, v, cost)); } mst(n); sort(tree.begin(), tree.end(), ans_sort); int ans = 0; memset(can, -1, sizeof can); for (int i = 0; i < tree.size(); i++) { node p = tree[i]; if (sp[p.u] && sp[p.v]) { ans = p.cost; break; } if (sp[p.u]) { can[p.v] = -1; if (dfs(p.v, p.u)) { ans = p.cost; break; } } else if (sp[p.v]) { can[p.u] = -1; if (dfs(p.u, p.v)) { ans = p.cost; break; } } else { can[p.u] = can[p.v] = -1; if (dfs(p.u, p.v) && dfs(p.v, p.u)) { ans = p.cost; break; } } vis[pair<int, int>(p.u, p.v)] = true; } for (int i = 0; i < k; i++) cout << ans << ; cout << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_1_V
`define SKY130_FD_SC_HS__A311O_1_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a311o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a311o_1 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_1_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: cpci_pci2net_16x60.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cpci_pci2net_16x60 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [59:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [59:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [59:0] sub_wire3;
wire sub_wire4;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [59:0] q = sub_wire3[59:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 11,
scfifo_component.intended_device_family = "Stratix IV",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 60,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "11"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "60"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "60"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "11"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "60"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 60 0 INPUT NODEFVAL "data[59..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 60 0 OUTPUT NODEFVAL "q[59..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 60 0 data 0 0 60 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 60 0 @q 0 0 60 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cpci_pci2net_16x60.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cpci_pci2net_16x60.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cpci_pci2net_16x60.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cpci_pci2net_16x60.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cpci_pci2net_16x60_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cpci_pci2net_16x60_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`ifndef INCLUDE_PARAMS
`include "params.v"
`endif
//Data Memory
module DMem(
input wire rst_n,
input wire [`WIDTH - 1:0] add,
inout wire [`WIDTH - 1:0] data,
input wire wr,
input wire rd,
output reg rd_st,
input wire [1:0] mode //mode: 0-word, 1-halfword, 2-byte
// mem trace
`ifdef TRACE_MEM
,input wire Print
`endif
);
reg [7:0] mem [0:`WIDTH - 1];
reg [`WIDTH - 1:0] data_r;
assign data = (rd == 1)? data_r : 32'bZ;
always @(posedge wr) begin
case (mode)
0: begin // word
{mem[add], mem[add+1], mem[add+2], mem[add+3]} = data;
end
1: begin // half-word
{mem[add], mem[add+1]} = data[15:0];
end
2: begin // byte
mem[add] = data[7:0];
end
endcase
end
always @(posedge rd) begin
rd_st = 0;
case (mode)
0: begin // word
data_r = {mem[add], mem[add+1], mem[add+2], mem[add+3]};
rd_st = 1;
end
1: begin // half-word
data_r = {16'b0 ,mem[add], mem[add+1]};
rd_st = 1;
end
2: begin // byte
data_r = {24'b0, mem[add]};
rd_st = 1;
end
endcase
end
always @(negedge rst_n) begin
$readmemh("data.hex", mem, 0, 20);
end
`ifdef TRACE_MEM
always @(posedge Print) begin
$writememh("data.hex", mem, 0, 20);
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int len, k; cin >> len >> k; string s; cin >> s; sort(s.begin(), s.end()); if (s[0] != s[k - 1]) cout << s[k - 1] << endl; else { cout << s[k - 1]; if (s[k] == s[len - 1]) { int q = (len - k) / k; if ((len - k) % k) q++; while (q--) cout << s[k]; } else for (int i = k; i < len; i++) cout << s[i]; cout << endl; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_SYMBOL_V
`define SKY130_FD_SC_LS__CLKBUF_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NOR2B_PP_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (a % b == 0) return b; return gcd(b, a % b); } int v[11]; int main() { int a, k = 0; scanf( %d , &a); for (int i = 2; i < a; i++) { int t = a; int pos = 0; while (t) { int mod = t % i; k += mod; t = (t - mod) / i; if (!t) break; } } int vbcd = gcd(k, a - 2); printf( %d/%d , k / vbcd, (a - 2) / vbcd); return 0; }
|
// Listing 5.6
module debouncer
(
input wire clk, reset,
input wire sw,
output reg db
);
// symbolic state declaration
localparam [2:0]
zero = 3'b000,
wait1_1 = 3'b001,
wait1_2 = 3'b010,
wait1_3 = 3'b011,
one = 3'b100,
wait0_1 = 3'b101,
wait0_2 = 3'b110,
wait0_3 = 3'b111;
// number of counter bits (2^N * 20ns = 10ms tick)
localparam N =19;
// signal declaration
reg [N-1:0] q_reg;
wire [N-1:0] q_next;
wire m_tick;
reg [2:0] state_reg, state_next;
// body
//=============================================
// counter to generate 10 ms tick
//=============================================
always @(posedge clk)
q_reg <= q_next;
// next-state logic
assign q_next = q_reg + 1;
// output tick
assign m_tick = (q_reg==0) ? 1'b1 : 1'b0;
//=============================================
// debouncing FSM
//=============================================
// state register
always @(posedge clk, posedge reset)
if (reset)
state_reg <= zero;
else
state_reg <= state_next;
// next-state logic and output logic
always @*
begin
state_next = state_reg; // default state: the same
db = 1'b0; // default output: 0
case (state_reg)
zero:
if (sw)
state_next = wait1_1;
wait1_1:
if (~sw)
state_next = zero;
else
if (m_tick)
state_next = wait1_2;
wait1_2:
if (~sw)
state_next = zero;
else
if (m_tick)
state_next = wait1_3;
wait1_3:
if (~sw)
state_next = zero;
else
if (m_tick)
state_next = one;
one:
begin
db = 1'b1;
if (~sw)
state_next = wait0_1;
end
wait0_1:
begin
db = 1'b1;
if (sw)
state_next = one;
else
if (m_tick)
state_next = wait0_2;
end
wait0_2:
begin
db = 1'b1;
if (sw)
state_next = one;
else
if (m_tick)
state_next = wait0_3;
end
wait0_3:
begin
db = 1'b1;
if (sw)
state_next = one;
else
if (m_tick)
state_next = zero;
end
default: state_next = zero;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41OI_4_V
`define SKY130_FD_SC_LS__A41OI_4_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a41oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a41oi_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41OI_4_V
|
`include "../include/tune.v"
// PentEvo project (c) NedoPC 2008-2009
//
// Z80 memory manager: routes ROM/RAM accesses, makes wait-states for 14MHz or stall condition, etc.
//
//
// fclk _/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\
// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
// zclk /```\___/```\___/```\___/```````\_______/```````\_______/```````````````\_______________/```````````````\_______________/`
// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
// zpos `\___/```\___/```\___/```\___________/```\___________/```\___________________________/```\___________________________/```\
// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
// zneg _/```\___/```\___/```\_______/```\___________/```\___________________/```\___________________________/```\________________
module zmem(
input wire fclk,
input wire rst_n,
input wire zpos, //
input wire zneg, // strobes which show positive and negative edges of zclk
input wire cbeg, // DRAM synchronization
input wire post_cbeg, //
input wire pre_cend, //
input wire cend, //
input wire [15:0] za,
input wire [ 7:0] zd_in, // won't emit anything to Z80 bus, data bus mux is another module
output wire [ 7:0] zd_out, // output to Z80 bus
output wire zd_ena, // out bus to the Z80
input wire m1_n,
input wire rfsh_n,
input wire mreq_n,
input wire iorq_n,
input wire rd_n,
input wire wr_n,
input wire [ 1:0] int_turbo, // 2'b00 - 3.5,
// 2'b01 - 7.0,
// 2'b1x - 14.0
input wire win0_romnram, // four windows, each 16k,
input wire win1_romnram, // ==1 - there is rom,
input wire win2_romnram, // ==0 - there is ram
input wire win3_romnram, //
input wire [ 7:0] win0_page, // which 16k page is in given window
input wire [ 7:0] win1_page, //
input wire [ 7:0] win2_page, //
input wire [ 7:0] win3_page, //
input wire romrw_en,
output reg [ 4:0] rompg, // output for ROM paging
output wire romoe_n,
output wire romwe_n,
output wire csrom,
output wire cpu_req,
output wire cpu_rnw,
output wire [20:0] cpu_addr,
output wire [ 7:0] cpu_wrdata,
output wire cpu_wrbsel,
input wire [15:0] cpu_rddata,
input wire cpu_next,
input wire cpu_strobe,
output wire cpu_stall // for zclock
);
wire [1:0] win;
reg [7:0] page;
reg romnram;
reg [15:0] rd_buf;
reg [15:1] cached_addr;
reg cached_addr_valid;
wire cache_hit;
wire dram_beg;
wire opfetch, memrd, memwr;
wire stall14, stall7_35;
wire stall14_ini;
wire stall14_cyc;
reg stall14_cycrd;
reg stall14_fin;
reg r_mreq_n;
reg pending_cpu_req;
reg cpu_rnw_r;
// this is for 7/3.5mhz
wire ramreq;
wire ramwr,ramrd;
wire cpureq_357;
reg ramrd_reg,ramwr_reg;
// make paging
assign win[1:0] = za[15:14];
always @*
case( win )
2'b00: begin
page = win0_page;
romnram = win0_romnram;
end
2'b01: begin
page = win1_page;
romnram = win1_romnram;
end
2'b10: begin
page = win2_page;
romnram = win2_romnram;
end
2'b11: begin
page = win3_page;
romnram = win3_romnram;
end
endcase
// rom paging - only half a megabyte addressing.
always @*
begin
rompg[4:0] = page[4:0];
end
assign romwe_n = wr_n | mreq_n | (~romrw_en);
assign romoe_n = rd_n | mreq_n;
assign csrom = romnram; // positive polarity!
// 7/3.5mhz support
assign ramreq = (~mreq_n) && (~romnram) && rfsh_n;
assign ramrd = ramreq & (~rd_n);
assign ramwr = ramreq & (~wr_n);
always @(posedge fclk)
if( cend && (!cpu_stall) )
begin
ramrd_reg <= ramrd;
ramwr_reg <= ramwr;
end
assign cpureq_357 = ( ramrd & (~ramrd_reg) ) | ( ramwr & (~ramwr_reg) );
assign zd_ena = (~mreq_n) & (~rd_n) & (~romnram);
assign cache_hit = ( (za[15:1] == cached_addr[15:1]) && cached_addr_valid );
// strobe the beginnings of DRAM cycles
always @(posedge fclk)
if( zneg )
r_mreq_n <= mreq_n | (~rfsh_n);
//
assign dram_beg = ( (!cache_hit) || memwr ) && zneg && r_mreq_n && (!romnram) && (!mreq_n) && rfsh_n;
// access type
assign opfetch = (~mreq_n) && (~m1_n);
assign memrd = (~mreq_n) && (~rd_n);
assign memwr = (~mreq_n) && rd_n && rfsh_n;
// wait tables:
//
// M1 opcode fetch, dram_beg coincides with:
// cend: +3
// pre_cend: +4
// post_cbeg: +5
// cbeg: +6
//
// memory read, dram_beg coincides with:
// cend: +2
// pre_cend: +3
// post_cbeg: +4
// cbeg: +5
//
// memory write: no wait
//
// special case: if dram_beg pulses 1 when cpu_next is 0,
// unconditional wait has to be performed until cpu_next is 1, and
// then wait as if dram_beg would coincide with cbeg
assign stall14_ini = dram_beg && ( (!cpu_next) || opfetch || memrd ); // no wait at all in write cycles, if next dram cycle is available
// memrd, opfetch - wait till cend & cpu_next,
// memwr - wait till cpu_next
assign stall14_cyc = memwr ? (!cpu_next) : stall14_cycrd;
//
always @(posedge fclk, negedge rst_n)
if( !rst_n )
stall14_cycrd <= 1'b0;
else // posedge fclk
begin
if( cpu_next && cend )
stall14_cycrd <= 1'b0;
else if( dram_beg && ( (!cend) || (!cpu_next) ) && (opfetch || memrd) )
stall14_cycrd <= 1'b1;
end
//
always @(posedge fclk, negedge rst_n)
if( !rst_n )
stall14_fin <= 1'b0;
else // posedge fclk
begin
if( stall14_fin && ( (opfetch&pre_cend) || (memrd&post_cbeg) ) )
stall14_fin <= 1'b0;
else if( cpu_next && cend && cpu_req && (opfetch || memrd) )
stall14_fin <= 1'b1;
end
//
assign cpu_stall = int_turbo[1] ? (stall14_ini | stall14_cyc | stall14_fin) : (cpureq_357 && (!cpu_next));
// cpu request
assign cpu_req = int_turbo[1] ? (pending_cpu_req | dram_beg) : cpureq_357;
//
assign cpu_rnw = int_turbo[1] ? (dram_beg ? (!memwr) : cpu_rnw_r) : ramrd;
//
//
always @(posedge fclk, negedge rst_n)
if( !rst_n )
pending_cpu_req <= 1'b0;
else if( cpu_next && cend )
pending_cpu_req <= 1'b0;
else if( dram_beg )
pending_cpu_req <= 1'b1;
//
always @(posedge fclk)
if( dram_beg )
cpu_rnw_r <= !memwr;
// address, data in and data out
//
assign cpu_wrbsel = za[0];
assign cpu_addr[20:0] = { page[7:0], za[13:1] };
assign cpu_wrdata = zd_in;
//
always @* if( cpu_strobe ) // WARNING! ACHTUNG! LATCH!!!
rd_buf <= cpu_rddata;
//
assign zd_out = cpu_wrbsel ? rd_buf[7:0] : rd_buf[15:8];
wire io;
reg io_r;
//
assign io = (~iorq_n);
//
always @(posedge fclk)
if( zpos )
io_r <= io;
//
always @(posedge fclk, negedge rst_n)
if( !rst_n )
begin
cached_addr_valid <= 1'b0;
end
else
begin
if( (zneg && r_mreq_n && (!mreq_n) && rfsh_n && romnram) ||
(zneg && r_mreq_n && memwr ) ||
(io && (!io_r) && zpos ) )
cached_addr_valid <= 1'b0;
else if( cpu_strobe )
cached_addr_valid <= 1'b1;
end
//
always @(posedge fclk)
if( !rst_n )
begin
cached_addr <= 15'd0;
end
else if( cpu_strobe )
begin
cached_addr[15:1] <= za[15:1];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; vector<int> adj[105]; int n, k, dp[105][50], tmp[50]; void dfs(int u, int p) { dp[u][0] = dp[u][k + 1] = 1; for (int x = 0; x < adj[u].size(); x++) { int v = adj[u][x]; if (v == p) continue; dfs(v, u); memset(tmp, 0, sizeof tmp); for (int i = 0; i <= 2 * k; i++) { for (int j = 0; j <= 2 * k; j++) { if (i + j <= 2 * k) tmp[min(i, j + 1)] = (tmp[min(i, j + 1)] + 1ll * dp[u][i] * dp[v][j]) % mod; else tmp[max(i, j + 1)] = (tmp[max(i, j + 1)] + 1ll * dp[u][i] * dp[v][j]) % mod; } } for (int i = 0; i <= 2 * k; i++) dp[u][i] = tmp[i]; } } int main() { scanf( %d %d , &n, &k); int i, ans = 0; for (i = 1; i < n; i++) { int u, v; scanf( %d %d , &u, &v); adj[u].push_back(v); adj[v].push_back(u); } dfs(1, 0); for (i = 0; i <= k; i++) ans = (ans + dp[1][i]) % mod; printf( %d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__EDFXTP_PP_BLACKBOX_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int p[200] = {0}; int main() { string a; int m; cin >> m; cin >> a; int n = a.length(); for (int i = 0; i < n; i++) { if (a[i] != ? ) p[a[i] - a ] = 1; if (a[i] != ? && a[i] - a >= m) { cout << IMPOSSIBLE << endl; return 0; } } for (int i = 0; i < n; i++) { if (a[i] == ? && a[n - i - 1] != ? ) a[i] = a[n - i - 1]; } for (int i = n / 2; i >= 0; i--) { if (a[i] == ? && a[n - i - 1] == ? ) { for (int j = m - 1; j >= 0; j--) { if (!p[j]) { a[i] = j + a ; a[n - i - 1] = j + a ; p[j] = 1; break; } } if (a[i] == ? ) a[i] = a , a[n - i - 1] = a ; } } for (int i = 0; i < n; i++) { if (a[i] != a[n - i - 1]) { cout << IMPOSSIBLE << endl; return 0; } } for (int i = 0; i < m; i++) if (!p[i]) { cout << IMPOSSIBLE << endl; return 0; } cout << a << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND2_PP_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A32O_BEHAVIORAL_PP_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a32o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32O_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O311A_PP_BLACKBOX_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main(void) { int n; cin >> n; int ans = 1; for (int i = 1; i < n; i++) { ans *= 3; ans %= 1000003; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, sum; long long arr[105]; long long val[105]; void icchhipadey() { long long n; cin >> n; long long arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } long long f, x; cin >> f >> x; long long ans = 0; for (int i = 0; i < n; i++) { if (arr[i] > f) { long long xx = arr[i] - f; xx = (xx + f + x - 1) / (f + x); ans += xx; } } cout << ans * x << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); icchhipadey(); }
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("f64.const.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("f64.const_tb.vcd");
$dumpvars(0, cpu_tb);
#12
`assert(result, 64'hc000000000000000);
`assert(result_empty, 0);
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTN_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DFRTN_PP_SYMBOL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTN_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; string s; cin >> s; vector<vector<int>> lcp(n, vector<int>(n)); for (int i = n - 1; i >= 0; --i) { for (int j = n - 1; j >= 0; --j) { lcp[i][j] = (s[i] == s[j] ? ((i < n - 1 && j < n - 1) ? lcp[i + 1][j + 1] : 0) + 1 : 0); } } vector<int> dp(n); for (int i = 0; i < n; ++i) { dp[i] = n - i; for (int j = 0; j < i; ++j) { if (i + lcp[i][j] < n && s[j + lcp[i][j]] < s[i + lcp[i][j]]) { dp[i] = max(dp[i], dp[j] + (n - lcp[j][i] - i)); } } } cout << *max_element(dp.begin(), dp.end()) << n ; } }
|
// hub_mem
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
// Hub RAM
//
// This is instantiated 4 times to allow writing by byte, word or long
module hub_ram
(
input clk,
input enable,
input w,
input wb,
input [13:0] a,
input [7:0] d8,
output [7:0] q8
);
// Size of RAM block in bytes.
parameter SIZE_BYTES;
reg [7:0] ram[SIZE_BYTES - 1:0];
always @(posedge clk)
begin
if (enable && w && wb)
begin
ram[a] <= d8;
end
q8 <= ram[a];
end
endmodule
//-----------------------------------------------------------------------------
// Hub ROM
//
// The ROM size can be varied by overriding the parameter, but it's always
// mapped to the top of the hub space, regardless of whether the entire 32KB
// ROM is implemented or not.
// If the ROM size parameter is set to a value less than 8192 (32KB),
// the missing amount of ROM is mapped in front of the actual ROM.
// For example, if the ROM size is set to the minimum of 512 (4KB), the
// actual ROM starts at $F000 instead of $8000, and the macros declared
// below will insert 28KB of "missing ROM" in addresses $8000-$EFFF.
// A couple of macros are used to initialize the ROM and calculate addresses
// based on its size and/or the hub address where the image files need to
// be stored.
module hub_rom
(
input clk,
input enable,
input [13:0] a,
input [31:0] d,
output [31:0] q
);
// Size of hub ROM in longs
parameter SIZE_LONGS;
reg [31:0] rom [SIZE_LONGS - 1:0];
// Amount of missing ROM in longs
`define ROMMISSING (8192 - SIZE_LONGS)
// Calculate offset in ROM area ($8000-$FFFF) based on no missing ROM
`define ROMOFFSET(hubaddress) (((hubaddress) - 'h8000) >> 2)
// Init ROM from file unless the destination ROM is missing
`define ROMINIT(file, hubstart, hubend) \
if (`ROMOFFSET(hubstart) >= `ROMMISSING) \
$readmemh(file, rom, `ROMOFFSET(hubstart) - `ROMMISSING, `ROMOFFSET(hubend) - `ROMMISSING)
initial
begin
`ROMINIT("rom_8000_bfff_font.hex", 'h8000, 'hBFFF);
`ROMINIT("rom_c000_cfff_log.hex", 'hC000, 'hCFFF);
`ROMINIT("rom_d000_dfff_antilog.hex", 'hD000, 'hDFFF);
`ROMINIT("rom_e000_f003_sine.hex", 'hE000, 'hF003);
`ifdef ENABLE_UNSCRAMBLED_ROM
`ROMINIT("rom_f004_f7a3_unscrambled_interpreter.hex", 'hF004, 'hF7A3);
`ROMINIT("rom_f800_fb93_unscrambled_booter.hex", 'hF800, 'hFB93);
`else
`ROMINIT("rom_f004_f7a3_scrambled_interpreter.hex", 'hF004, 'hF7A3);
`ROMINIT("rom_f800_fb93_scrambled_booter.hex", 'hF800, 'hFB93);
`endif
`ROMINIT("rom_ff00_ff5f_copyright.hex", 'hFF00, 'hFF5F);
`ROMINIT("rom_ff70_ffff_runner.hex", 'hFF70, 'hFFFF);
end
always @(posedge clk)
begin
q <= rom[a - `ROMMISSING];
end
endmodule
//-----------------------------------------------------------------------------
// Hub memory
module hub_mem
(
input clk_cog,
input ena_bus,
input nres,
input w,
input [3:0] wb,
input [13:0] a,
input [31:0] d,
output [31:0] q
);
// RAM and ROM sizes in blocks.
// The standard Propeller has 32KB RAM, 32KB ROM
// RAM size should be 32KB, reduce at your own risk
// ROM should be between 512 and 8192 longs (4KB..32KB)
parameter HUB_RAM_SIZE_BYTES = 32768;
parameter HUB_ROM_SIZE_BYTES = 32768;
// Check if address is in RAM
// TODO: simplify with log2 combined with logical AND
wire in_ram = (a < HUB_RAM_SIZE_BYTES >> 2);
// Check if address is in ROM
// TODO: simplify with log2 combined with logical AND
wire in_rom = (a >= 16384 - (HUB_ROM_SIZE_BYTES >> 2));
// Instantiate 4 instances of RAM
reg [31:0] ram_q;
genvar i;
generate
for (i = 0; i < 4; i = i + 1)
begin : ramgen
hub_ram
#(
.SIZE_BYTES (HUB_RAM_SIZE_BYTES >> 2)
)
ram_(
.clk (clk_cog),
.enable (ena_bus && in_ram),
.w (w),
.wb (wb[i]),
.a (a),
.d8 (d[(i+1)*8-1:i*8]),
.q8 (ram_q[(i+1)*8-1:i*8])
);
end
endgenerate
// Instantiate ROM
reg [31:0] rom_q;
hub_rom
#(
.SIZE_LONGS (HUB_ROM_SIZE_BYTES >> 2)
)
rom_(
.clk (clk_cog),
.enable (ena_bus && in_rom),
.a (a),
.d (d),
.q (rom_q)
);
// memory output mux
reg mem;
always @(posedge clk_cog)
if (ena_bus)
mem <= in_ram;
assign q = mem ? ram_q : rom_q;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0); int n; cin >> n; vector<pair<int, int>> d(n); for (auto &i : d) cin >> i.first, i.second = &i - &d[0] + 1; sort(d.begin(), d.end()); vector<pair<int, int>> e; vector<int> a; a.push_back(2 * d.back().second - 1); for (int i = 1; i < d.back().first; ++i) a.push_back(-1); a.push_back(2 * d.back().second); int l = 0, r = a.size() - 1; d.pop_back(); while (!d.empty()) { auto p = d.back(); d.pop_back(); if (a[l + 1] == -1) { ++l; a[l] = 2 * p.second - 1; if (p.first == r - l + 1) { ++r; a.push_back(2 * p.second); } else { e.push_back({l + p.first - 1, 2 * p.second}); } } else { ++r; a.push_back(2 * p.second); e.push_back({r - p.first + 1, 2 * p.second - 1}); } } for (size_t i = 1; i < a.size(); ++i) cout << a[i - 1] << << a[i] << n ; for (auto &i : e) cout << a[i.first] << << i.second << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { int N, M; string K; while (cin >> N >> M >> K) { K = K.substr(2); stringstream ss(K); int k; ss >> k; map<string, int> inp; for (int i = 0; i < (int)(N); i++) { string name; int level; cin >> name >> level; level = (level * k) / 100; if (level >= 100) { inp.insert(make_pair(name, level)); } } for (int i = 0; i < (int)(M); i++) { string name; cin >> name; if (inp.count(name) == 0) inp[name] = 0; } cout << inp.size() << endl; for (map<string, int>::iterator it = inp.begin(); it != inp.end(); it++) { cout << it->first << << it->second << endl; } } } int main() { solve(); return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file cx4_datrom.v when simulating
// the core, cx4_datrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module cx4_datrom(
clka,
addra,
douta
);
input clka;
input [9 : 0] addra;
output [23 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("cx4_datrom.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(24),
.C_READ_WIDTH_B(24),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(24),
.C_WRITE_WIDTH_B(24),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; const int M = 1e5 + 10; const int INF = 2147483647; const int MOD = 1e9 + 7; int T, n, m; int sum; int a[N]; pair<int, int> b[N]; long long gcd(long long x, long long y) { return y == 0 ? x : gcd(y, x % y); } long long qpow(long long base, long long x) { long long res = 1; while (x) { if (x & 1) res *= base; base *= base; base %= MOD; res %= MOD; x >>= 1; } return res; } long long qmul(long long a, long long b, long long mod) { long long res = 0; while (b) { if (b & 1) res = (res + a) % mod; a = (a + a) % mod; b >>= 1; } return res; } void exgcd(long long a, long long b, long long &x, long long &y) { if (b == 0) { x = 1; y = 0; return; } exgcd(b, a % b, y, x); y -= (a / b) * x; } long long getinv(long long x, long long mod) { long long x_0, y_0; exgcd(x, mod, x_0, y_0); return x_0; } bool check(int x) { if (sum > x) return false; vector<int> day(n + 1, 0); for (int i = 1; i <= m; i++) { int d = b[i].first, item = b[i].second; if (d <= x) { day[item] = max(day[item], d); } } vector<vector<int>> tmp(200005); for (int i = 1; i <= n; i++) { if (day[i]) { tmp[day[i]].emplace_back(i); } } vector<int> use(n + 1, 0); for (int i = 1; i <= n; i++) use[i] = a[i]; int cur = 0; for (int i = 1; i <= x; i++) { ++cur; if (i > 200000) continue; for (auto &t : tmp[i]) { if (cur >= a[t]) { cur -= a[t]; use[t] = 0; } else { use[t] -= cur; cur = 0; break; } } } int ss = 0; for (int i = 1; i <= n; i++) ss += use[i]; return cur >= ss * 2; } void solve() { cin >> n >> m; for (int i = 1; i <= n; i++) cin >> a[i], sum += a[i]; for (int i = 1; i <= m; i++) cin >> b[i].first >> b[i].second; int l = 1, r = 1e9; while (l < r) { int mid = (l + r) >> 1; if (check(mid)) r = mid; else l = mid + 1; } cout << l << endl; } int main() { ios::sync_with_stdio(0); cin.tie(nullptr); T = 1; while (T--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200010; struct tree { int lt, rt; long long sumdis, sum, cnt; } a[N * 4]; int c[N], b[N], tmp[N], cnt, bb[N]; int find(int x) { int lt = 1, rt = cnt, mid; while (lt <= rt) { mid = (lt + rt) / 2; if (c[mid] == x) return mid; if (c[mid] > x) rt = mid - 1; else lt = mid + 1; } } int find_lt(int x) { int lt = 1, rt = cnt, mid, ans = -1; while (lt <= rt) { mid = (lt + rt) / 2; if (c[mid] >= x) ans = mid, rt = mid - 1; else lt = mid + 1; } return ans; } int find_rt(int x) { int lt = 1, rt = cnt, mid, ans = -1; while (lt <= rt) { mid = (lt + rt) / 2; if (c[mid] <= x) ans = mid, lt = mid + 1; else rt = mid - 1; } return ans; } void init(int lt, int rt, int step) { a[step].lt = lt; a[step].rt = rt; a[step].sumdis = a[step].sum = a[step].cnt = 0; if (lt == rt) return; int mid = (lt + rt) / 2; init(lt, mid, 2 * step); init(mid + 1, rt, 2 * step + 1); } void insert(int pos, int step, int val) { if (a[step].lt == a[step].rt) { a[step].sumdis += c[pos] * val; a[step].sum = 0; a[step].cnt += val; return; } if (pos <= a[2 * step].rt) insert(pos, 2 * step, val); else insert(pos, 2 * step + 1, val); a[step].sumdis = a[2 * step].sumdis + a[2 * step + 1].sumdis; a[step].cnt = a[2 * step].cnt + a[2 * step + 1].cnt; a[step].sum = a[2 * step].sum + a[2 * step + 1].sum; a[step].sum += a[2 * step + 1].sumdis * a[step * 2].cnt - a[2 * step].sumdis * a[step * 2 + 1].cnt; } void query(int lt, int rt, int step, long long &sumdis, long long &ccnt, long long &sum) { if (a[step].lt == lt && a[step].rt == rt) { sumdis = a[step].sumdis; ccnt = a[step].cnt; sum = a[step].sum; return; } if (rt <= a[2 * step].rt) query(lt, rt, 2 * step, sumdis, ccnt, sum); else if (lt > a[2 * step].rt) query(lt, rt, 2 * step + 1, sumdis, ccnt, sum); else { long long sumdis1, sumdis2, cnt1, cnt2, sum1, sum2; query(lt, a[2 * step].rt, 2 * step, sumdis1, cnt1, sum1); query(a[2 * step + 1].lt, rt, 2 * step + 1, sumdis2, cnt2, sum2); sum = sum1 + sum2; sum += sumdis2 * cnt1 - sumdis1 * cnt2; ccnt = cnt1 + cnt2; sumdis = sumdis1 + sumdis2; } } struct point { int x, y, z; void read() { scanf( %d%d%d , &x, &y, &z); } } pt[N]; int main() { int n, m; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &b[i]); tmp[i] = bb[i] = b[i]; } int tot = n; scanf( %d , &m); for (int i = 1; i <= m; i++) { pt[i].read(); if (pt[i].x == 1) { b[pt[i].y] += pt[i].z; tmp[++tot] = b[pt[i].y]; } } sort(tmp + 1, tmp + tot + 1); cnt = 1; c[1] = tmp[1]; for (int i = 2; i <= tot; i++) if (tmp[i] != c[cnt]) c[++cnt] = tmp[i]; init(1, cnt, 1); int x, y, z; for (int i = 1; i <= n; i++) insert(find(bb[i]), 1, 1); for (int i = 1; i <= m; i++) { x = pt[i].x, y = pt[i].y, z = pt[i].z; if (x == 1) { insert(find(bb[y]), 1, -1); bb[y] += z; insert(find(bb[y]), 1, 1); } else { long long t1 = 0, t2 = 0, t3 = 0; y = find_lt(y); z = find_rt(z); if (y == -1 || z == -1 || y > z) printf( 0 n ); else { query(y, z, 1, t1, t2, t3); printf( %I64d n , t3); } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 300005; const int mod = 1e9 + 7; const double eps = 1e-8; const double PI = acos(-1.0); long long qpow(long long a, long long b, long long p) { long long res = 1; while (b) { if (b & 1) res = res * a % p; a = a * a % p; b >>= 1; } return res; } long long a[N]; int main() { std::ios::sync_with_stdio(false); int n, p, k; while (cin >> n >> p >> k) { for (int i = 1; i <= n; i++) cin >> a[i]; map<long long, long long> mp; for (int i = 1; i <= n; i++) mp[(qpow(a[i], 4, p) - k % p * a[i] % p + p) % p]++; map<long long, long long>::iterator it = mp.begin(); long long ans = 0; for (it; it != mp.end(); it++) { ans += (*it).second * ((*it).second - 1) / 2; } cout << ans << endl; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: HORIE Tetsuya
//
// Create Date: 2015/11/27 19:43:29
// Design Name:
// Module Name: Clocks
// Project Name: TD4-GateLevel
// Target Devices: Nexys4 DDR
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// Copyright © 2015 HORIE Tetsuya.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//////////////////////////////////////////////////////////////////////////////////
/**
* @brief システムに必要なクロックを生成するモジュールです。
*
* @param baseClock この信号からクロック信号を生成します。(100MHzを前提としています)
* @param reset リセット信号です。
* @param clock1Hz 1Hzのクロック信号を生成します。
* @param clock10Hz 10Hzのクロック信号を生成します。
*/
module Clocks
(input baseClock,
input reset,
output clock1Hz,
output clock10Hz);
parameter COUNT_HALF_1HZ = 26'd49999999;
parameter COUNT_HALF_BIT_WIDTH_1HZ = 26;
parameter COUNT_HALF_10HZ = 23'd4999999;
parameter COUNT_HALF_BIT_WIDTH_10HZ = 23;
Clock #(COUNT_HALF_1HZ, COUNT_HALF_BIT_WIDTH_1HZ)clk1Hz(baseClock, reset, clock1Hz);
Clock #(COUNT_HALF_10HZ, COUNT_HALF_BIT_WIDTH_10HZ)clk10Hz(baseClock, reset, clock10Hz);
endmodule // Clocks
/**
* @brief クロックを作成するモジュールです。
*
* @param #COUNT_HALF_CYCLE 周期の半分のカウント数
* @param baseClock この信号からクロック信号を生成します。
* @param reset リセット信号です。
* @param clock クロック信号を出力します。
*/
module Clock
#(COUNT_HALF_CYCLE = 26'd49999999,
COUNT_BIT_WIDTH = 26)
(input baseClock,
input reset,
output reg derivClock);
reg [COUNT_BIT_WIDTH - 1:0] halfCycleCount; // 周期の半分をカウントするためのカウンタ
wire isPassedHalfCycle = (halfCycleCount == COUNT_HALF_CYCLE); // 周期の半分経過時の信号
// 周期の半分をカウントし、カウントアップ完了時に、clockの0と1を切り替える。
// (周期的なクロック信号ができる)
always @(posedge baseClock) begin
if (reset) begin
halfCycleCount <= 1'b0;
derivClock <= 1'b0;
end
else if (isPassedHalfCycle) begin
halfCycleCount <= 1'b0;
derivClock <= ~derivClock;
end
else
halfCycleCount <= halfCycleCount + 1'b1;
end;
endmodule // Clock
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#include <bits/stdc++.h> int ATTENTION() { http: return 0; } using namespace std; const int iinf = 0x7fffffff; const long long linf = ~(1LL << 63); template <typename T> inline T gcd(T a, T b) { if (a < 0) return gcd(-a, b); if (b < 0) return gcd(a, -b); if (a < b) return gcd(b, a); if (b == 0) return a; return gcd(b, a % b); } long long qpow(long long a, long long n, long long mod) { a %= mod; long long ans = 1LL; while (n) { if (n & 1) ans = (ans * a % mod); a = (a * a % mod); n >>= 1; } return ans; } inline long long rev(long long a, long long p) { return qpow(a, p - 2, p); } template <typename T> inline void BPS(T* DST, T* SRC, int N, int s = 0) { DST[s] = SRC[s]; for (int i = 1; i < N; i++) DST[s + i] = DST[s + i - 1] + SRC[s + i]; } inline int in() { int x; cin >> x; return x; } inline void tic() {} inline void toc() {} bitset<100000001> is_prime; int n, A, B, C, D; void unset_prime(unsigned int v) { is_prime.reset(v / 3); } unsigned int f(unsigned int x) { return ((((unsigned int)A * x + (unsigned int)B)) * x + (unsigned int)C) * x + (unsigned int)D; } int main() { scanf( %u%u%u%u%u , &n, &A, &B, &C, &D); is_prime.set(); unsigned int res = 0; unsigned int t = n; unsigned int p2 = 2; unsigned int fp = f(2); while (t >= p2) { res += t / p2 * fp; p2 *= 2; } p2 = 3; fp = f(3); while (t >= p2) { res += t / p2 * fp; p2 *= 3; } for (unsigned int i = 5; i <= n; i += 2) { if (is_prime[i / 3] == 0) { if (i % 3 == 1) i += 2; continue; } for (unsigned int j = 5 * i, k = 5; j <= n; j += 2 * i, k += 2) { unset_prime(j); if (k % 3 == 1) { k += 2; j += 2 * i; } } t = n; long long pi = i; fp = f(i); while (t >= pi) { res += t / pi * fp; pi *= i; } if (i % 3 == 1) i += 2; } printf( %u n , res); return 0; }
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